| Commit message (Collapse) | Author | Age |
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for-next
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Rename clk_init_one() to clk_preinit() to distinguish its function
from clk_init() and the individual struct clk init functions.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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On our system we see the following messages:
Disabling unused clock "gpt2_ick"
Disabling unused clock "gpt3_ick"
Disabling unused clock "gpt4_ick"
Disabling unused clock "gpt5_ick"
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The messages have KERN_INFO level and if you have serial
console, they normally go there. I do not think it is good
idea to print that much stuff there. Moreover, messages
are not properly prefixed and for mortals it is not
immeadietly clear where they come from.
Let's give them debugging level instead.
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: trimmed debugging output in patch description]
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The CORE DPLL M2 frequency change code should use pr_debug(), not
pr_info(), for its debug messages. Same with
omap2_clksel_round_rate_div(). While here, convert a few printk(KERN_ERR ..
into pr_err().
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the
DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC
clock frequency from 83MHz to 166MHz. CDP code unconditionally
unlocked the DLL whenever shifting to a lower SDRC speed, but this
seems unnecessary and error-prone, as the DLL is no longer able to
compensate for process, voltage, and temperature variations. Instead,
only unlock the DLL when the SDRC clock rate would be less than 83MHz.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Renumber registers in omap3_sram_configure_core_dpll() assembly code to
make space for additional parameters.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Initialize SDRC_POWER to a known-good setting when the kernel boots.
Necessary since some bootloaders don't initialize SDRC_POWER properly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Clear the SDRC_POWER.PWRENA bit before putting the SDRAM into self-refresh
mode. This prevents the SDRC from attempting to power off the SDRAM,
which can cause the system to hang.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Where necessary, add interconnect barriers to force posted writes to
complete before continuing.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Add more barriers in the SRAM CORE DPLL M2 divider change code.
- Add a DSB SY after the function's entry point to flush all cached
and buffered writes and wait for the interconnect to claim that they
have completed[1]. The idea here is to force all delayed write
traffic going to the SDRAM to at least post to the L3 interconnect
before continuing. If these writes are allowed to occur after the
SDRC is idled, the writes will not be acknowledged and the ARM will
stall.
Note that in this case, it does not matter if the writes actually
complete to the SDRAM - it is only necessary for the writes to leave
the ARM itself. If the writes are posted by the interconnect when
the SDRC goes into idle, the writes will be delayed until the SDRC
returns from idle[2]. If the SDRC is in the middle of a write when
it is requested to enter idle, the SDRC will not acknowledge the
idle request until the writes complete to the SDRAM.[3]
The old-style DMB in sdram_in_selfrefresh is now superfluous, so,
remove it.
- Add an ISB before the function's exit point to prevent the ARM from
speculatively executing into SDRAM before the SDRAM is enabled[4].
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1. ARMv7 ARM (DDI 0406A) A3-47, A3-48.
2. Private communication with Richard Woodruff <r-woodruff2@ti.com>.
3. Private communication with Richard Woodruff <r-woodruff2@ti.com>.
4. ARMv7 ARM (DDI 0406A) A3-48.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
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Mark the SRAM (aka OCM RAM) as Non-cacheable Normal memory[1]. This
is to prevent the ARM from evicting existing cache lines to SDRAM
while code is executing from the SRAM. Necessary since one of the
primary uses for the SRAM is to hold the code and data for the CORE
DPLL M2 divider reprogramming code, which must execute while the SDRC
is idled. If the ARM attempts to write cache lines back to the while
the SRAM code is running, the ARM will stall[2].
TI deals with this problem in the CDP kernel by marking the SRAM as
Strongly-ordered memory.
Tero Kristo <tero.kristo@nokia.com> caught a bug in an earlier version of
this patch - thanks Tero.
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1. ARMv7 ARM (DDI 0406A) pp. A3-30, A3-31, B3-32.
2. Private communication with Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <tero.kristo@nokia.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
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This patch removes unnecessary omap2_globals and pass the global structures
directly as function argument.
The proposed cleanup was suggested by Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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This patch removes fixes omap_sram_error() function and replace the
error paths with BUG_ON.
The proposed fix was suggested by Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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This patch fixes the compiler warning "assignment from incompatible
pointer type" in dmtimer.c and removes the tye casts. These warnings
were suppressed by type catsing.
The proposed fix was suggested by Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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We don't necessarily want to compile in irq.o and sdrc.o for omap4.
Also, clock and prcm may not be implemented initially.
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Processor specific macros should be used instead.
Signed-off-by: Tony Lindgren <tony@atomide.com>
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It's currently unused, and processor specific defines should
be used instead.
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Move define of OMAP2_VA_IC_BASE to be local to entry-macro.S
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Remove OMAP_PRM_REGADDR and use processor specific defines instead.
Also fold in a patch from Kevin Hilman to add _OFFSET #defines
for the PRCM registers to be used with the prm_[read|write]_* macros.
These are used extensively in the forthcoming OMAP PM support.
Also remove now unused OMAP2_PRM_BASE.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Use processor specific defines instead.
As an extra bonus, this patch fixes the problem of CONFIG_DEBUG_SPINLOCK
calling sched_clock before we have things initialized:
http://patchwork.kernel.org/patch/15810/
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Some DMA_32BIT_MASK usage snuck in with the MMC platform support.
Convert these to the new preferred DMA_BIT_MASK(32).
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci into devel
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DaVinci EMAC driver is now upstream. Enable it in default defconfig.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Provide a generic SRAM allocator using genalloc, and vaguely
modeled after what AVR32 uses. This builds on top of the
static CPU mapping set up in the previous patch, and returns
DMA mappings as requested (if possible).
Compared to its OMAP cousin, there's no current support for
(currently non-existent) DaVinci power management code running
in SRAM; and this has ways to deallocate, instead of being
allocate-only.
The initial user of this should probably be the audio code,
because EDMA from DDR is subject to various dropouts on at
least DM355 and DM6446 chips.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Package on-chip SRAM. It's always accessible from the ARM, so
set up a standardized virtual address mapping into a 128 KiB
area that's reserved for platform use.
In some cases (dm6467) the physical addresses used for EDMA are
not the same as the ones used by the ARM ... so record that info
separately in the SOC data, for chips (unlike the OMAP-L137)
where SRAM may be used with EDMA.
Other blocks of SRAM, such as the ETB buffer or DSP L1/L2 RAM,
may be unused/available on some system. They are ignored here.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Remove remnants of dm6446-specific SRAM allocator, as preparation for
a more generic replacement.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Different SoC have different numbers of pinmux registers and other
resources that overlap with each other. To clean up the code and
eliminate defines that overlap with each other, move the PINMUX
defines to the SoC specific files.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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The Timer64p timer has 8 compare registers that can
be used to generate interrupts when the timer value
matches the compare reg's value. They do not disturb
the timer itself. This can be useful when there is
only one timer available for both clock events and
clocksource.
When enabled, the clocksource remains a continuous
32-bit counter but the clock event will no longer
support periodic interrupts. Instead only oneshot
timers will be supported and implemented by setting
the compare register to the current timer value plus
the period that the clock event subsystem is requesting.
Compare registers support is enabled automatically
when the following conditions are met:
1) The same timer is being used for clock events
and clocksource.
2) The timer is the bottom half (32 bits) of the
64-bit timer (hardware limitation).
3) The the compare register offset and irq are
not zero.
Since the timer is always running, there is a hardware
race in timer32_config() between reading the current
timer value, and adding the period to the current
timer value and writing the compare register.
Testing on a da830 evm board with the timer clocked
at 24 MHz and the processor clocked at 300 MHz,
showed the number of counter ticks to do this ranged
from 20-53 (~1-2.2 usecs) but usually around 41 ticks.
This includes some artifacts from collecting the
information. So, the minimum period should be
at least 5 usecs to be safe.
There is also an non-critical lower limit that
the period should be since there is no point in
setting an event that is much shorter than the
time it takes to set the event, and get & handle
the timer interrupt for that event. There can
also be all sorts of delays from activities
occuring elsewhere in the system (including
hardware activitis like cache & TLB management).
These are virtually impossible to quantify so a
minimum period of 50 usecs was chosen. That will
certianly be enough to avoid the actual hardware
race but hopefully not large enough to cause
unreasonably course-grained timers.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Integrate the Common Platform Interrupt Controller (cp_intc)
support into the low-level irq handling for davinci and similar
platforms. Do it such that support for cp_intc and the original
aintc can coexist in the same kernel binary.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Factor out the code to extract that mac address from
i2c eeprom.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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The dm644x and dm646x board files have i2c eeprom read and
write routines but they are not used so remove them.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Since most of the emac platform_data is really SoC specific
and not board specific, move it to the SoC-specific files.
Put a pointer to the platform_data in the soc_info structure
so the board-specific code can set some of the platform_data
if it needs to.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Currently, there is one set of platform_device and platform_data
structures for all DaVinci SoCs. The differences in the data
between the various SoCs is handled by davinci_serial_init()
by checking the SoC type. However, as new SoCs appear, this
routine will become more & more cluttered.
To clean up the routine and make it easier to add support for new
SoCs, move the platform_device and platform_data structures into the
SoC-specific code and use the SoC infrastructure to provide access
to the data.
In the process, fix a bug where the wrong irq is used for uart2
of the dm646x.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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The current gpio code needs to know the number of
gpio irqs there are and what the bank irq number is.
To determine those values, it checks the SoC type.
It also assumes that the base address and the number
of irqs the interrupt controller uses is fixed.
To clean up the SoC checks and make it support
different base addresses and interrupt controllers,
have the SoC-specific code set those values in
the soc_info structure and have the gpio code
reference them there.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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The watchdog code currently hardcodes the base address
of the timer its using. To support new SoCs, make it
support timers at any address. Use the soc_info structure
to do this.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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The davinci timer code currently hardcodes the timer register
base addresses, the timer irq numbers, and the timers to use
for clock events and clocksource. This won't work for some
a new SoC so put those values into the soc_info structure
and set them up in the SoC-specific files.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Use the SoC infrastructure to hold the interrupt controller
information (i.e., base address, default priorities,
interrupt controller type, and the number of IRQs).
The interrupt controller base, although initially put
in the soc_info structure's intc_base field, is eventually
put in the global 'davinci_intc_base' so the low-level
interrupt code can access it without a dereference.
These changes enable the SoC default irq priorities to be
put in the SoC-specific files, and the interrupt controller
to be at any base address.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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The pinmux register base and setup can be different for different
SoCs so move the pinmux reg base, pinmux table (and its size) to
the SoC infrastructure.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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The current code to support the DaVinci Power and Sleep Controller (PSC)
assumes that there is only one controller. This assumption is no longer
valid so expand the support to allow greater than one PSC.
To accomplish this, put the base addresses for the PSCs in the SoC
infrastructure so it can be referenced by the PSC code. This also
requires adding an extra parameter to davinci_psc_config() to specify
the PSC that is to be enabled/disabled.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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All of the davinci SoCs need to call davinci_clk_init() so
put the call in the common init routine.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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The Davinci cpu_is_davinci_*() macros use the SoC part number
and variant retrieved from the JTAG ID register to determine the
type of cpu that the kernel is running on. Currently, the code to
read the JTAG ID register assumes that the register is always at
the same base address. This isn't true on some newer SoCs.
To solve this, have the SoC-specific code set the JTAG ID register
base address in soc_info structure and add a 'cpu_id' member to it.
'cpu_id' will be used by the cpu_is_davinci_*() macros to match
the cpu id. Also move the info used to identify the cpu type into
the SoC-specific code to keep all SoC-specific code together.
The common code will read the JTAG ID register, search through
an array of davinci_id structures to identify the cpu type.
Once identified, it will set the 'cpu_id' member of the soc_info
structure to the proper value and the cpu_is_davinci_*() macros
will now work.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Create a structure to encapsulate SoC-specific information.
This will assist in generalizing code so it can be used by
different SoCs that have similar hardware but with minor
differences such as having a different base address.
The idea is that the code for each SoC fills out a structure
with the correct information. The board-specific code then
calls the SoC init routine which in turn will call a common
init routine that makes a copy of the structure, maps in I/O
regions, etc.
After initialization, code can get a pointer to the structure
by calling davinci_get_soc_info(). Eventually, the common
init routine will make a copy of all of the data pointed to
by the structure so the original data can be made __init_data.
That way the data for SoC's that aren't being used won't consume
memory for the entire life of the kernel.
The structure will be extended in subsequent patches but
initially, it holds the map_desc structure for any I/O
regions the SoC/board wants statically mapped.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Add SoC and platform-specific data and init for DaVinci EMAC network
driver.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Add SoC and platform-specific data and init for MMC driver.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Add support for DM646x SoC (a.k.a DaVinci HD) and its Evalution
Module (EVM.)
Original support done by Sudhakar Rajashekhara.
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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In addition, add board support for the DM355 Evaluation Module (EVM)
and the DM355 Leopard board.
Original DM355 EVM support done by Sandeep Paulraj, with significant
updates and improvements by David Brownell. DM355 Leopord support
done by Koen Kooi.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Koen Kooi <koen@beagleboard.org>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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