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* davinci: da8xx: Add base DA830/OMAP-L137 SoC supportMark A. Greer2009-08-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The da830/omap l137 is a new SoC from TI that is similar to the davinci line. Since its so similar to davinci, put the support for the da830 in the same directory as the davinci code. There are differences, however. Some of those differences prevent support for davinci and da830 platforms to work in the same kernel binary. Those differences are: 1) Different physical address for RAM. This is relevant to Makefile.boot addresses and PHYS_OFFSET. The Makefile.boot issue isn't truly a kernel issue but it means u-boot won't work with a uImage including both architectures. The PHYS_OFFSET issue is addressed by the "Allow for runtime-determined PHYS_OFFSET" patch by Lennert Buytenhek but it hasn't been accepted yet. 2) Different uart addresses. This is only an issue for the 'addruart' assembly macro when CONFIG_DEBUG_LL is enabled. Since the code in that macro is called so early (e.g., by _error_p in kernel/head.S when the processor lookup fails), we can't determine what platform the kernel is running on at runtime to use the correct uart address. These areas have compile errors intentionally inserted to indicate to the builder they're doing something wrong. A new config variable, CONFIG_ARCH_DAVINCI_DMx, is added to distinguish between a true davinci architecture and the da830 architecture. Note that the da830 currently has an issue with writeback data cache so CONFIG_CPU_DCACHE_WRITETHROUGH should be enabled when building a da830 kernel. Additional generalizations for future SoCs in the da8xx family done by Sudhakar Rajashekhara and Sekhar Nori. Signed-off-by: Steve Chen <schen@mvista.com> Signed-off-by: Mikhail Cherkashin <mcherkashin@ru.mvista.com> Signed-off-by: Mark A. Greer <mgreer@mvista.com> Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Cc: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: dm365 evm cpld support: leds, card detect, other setupDavid Brownell2009-08-26
| | | | | | | | | | | | | | | | | | Add basic support for the CPLD on the DM365 EVM board: - Read SW5 to set up NAND and keypad vs (someday) OneNAND - Export MMC/SD card detect and writeprotect signals - LED support (same layout as on DM355 EVM) - Static config for video input: * external HD imager precludes MMC1, Ethernet, audio * else either tvp5146 (SD/default) or tvp7002 (HD) The video input could actually be switched around dynamically; change that if/when that's needed (and after those other video inputs have driver support). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: dm365: add NAND support to EVM boardSandeep Paulraj2009-08-26
| | | | | Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: MMC/SD Support for dm365 EVMSandeep Paulraj2009-08-26
| | | | | | | | | Patch adds support for MMC/SD in the DM365 EVM. Pinmux for MMC/SD slot 1 on the DM365 EVM is also configured. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: dm365: add MMC/SD supportSandeep Paulraj2009-08-26
| | | | | Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: dm365: add EDMA supportSandeep Paulraj2009-08-26
| | | | | Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: dm365: EMAC support for SoC and dm365 EVMSandeep Paulraj2009-08-26
| | | | | | | | The patch adds Support for EMAC in the DM365 SOC and the DM365 EVM board. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: dm365: add mux entries for EDMA, RTC, EMAC, keypad.Sandeep Paulraj2009-08-26
| | | | | Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Adding DM365 entries to Makefile/Kconfig/defconfigSandeep Paulraj2009-08-26
| | | | | | | | | | This patch does the following 1) Adds entries to davinci_all_defconfig for DM365 2) Adds entries to the Makefile for DM365 3) Adds entries for DM365 in the Kconfig Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Adding DM365 EVM board supportSandeep Paulraj2009-08-26
| | | | | | | | The patch adds support for Evaluation Module (EVM) board for the dm365 SoC. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Adding DM365 SOC SupportSandeep Paulraj2009-08-26
| | | | | | | | The patch adds base support for new TI SOC DM365, which s similar to the dm355. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: remove watchdog from soc_infoKevin Hilman2009-08-26
| | | | | | | watchdog info is not needed in soc_info, platform_device can be used directly in core code. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: sram warning fixDavid Brownell2009-08-26
| | | | | | | | | CC arch/arm/mach-davinci/sram.o arch/arm/mach-davinci/sram.c: In function 'sram_init': arch/arm/mach-davinci/sram.c:63: warning: comparison of distinct pointer types lacks a cast Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Kconfig: enable EVMs by default when SoCs are enabledKevin Hilman2009-08-26
| | | | Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: dm644x: Support for dm644x silicon revision 2.1Rajashekhara, Sudhakar2009-08-26
| | | | | | | | | JTAG ID for DM644x silicon revision 2.1 has changed. An entry for the new silicon revision needs to be added to the davinci_id structure. Without this addition, EVMs with new silicon revision fail to boot the kernel. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Fix watchdog reset codeDavid Griego2009-08-26
| | | | | | | | | | | | | The davinci reset routine, davinci_watchdog_reset(), sets the TCR register instead of the TGCR register as it should to put the WDT into its "Initial State". It also writes the WDTCR register without the proper WDKEY which is pointless since the register will be write-protected. Signed-off-by: David Griego <dgriego@mvista.com> Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: dm646x: Adds McASP clockChaithrika U S2009-08-26
| | | | | | | | | Adds McASP clock support for the two instances of mcasp (mcasp0,mcasp1). This patch is part of the audio support for dm646x series. Signed-off-by: Naresh Medisetty <naresh@ti.com> Signed-off-by: Chaithrika U S <chaithrika@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: EDMA: add support for dm646xSudhakar Rajashekhara2009-08-26
| | | | | | | | | Enables module clock for DM646x EDMA channel controller and transfer controller. Signed-off-by: Naresh Medisetty <naresh@ti.com> Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: EDMA: multiple CCs, channel mapping and API changesSudhakar Rajashekhara2009-08-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - restructure to support multiple channel controllers by using additional struct resources for each CC - interface changes visible to EDMA clients Introduce macros to build IDs from controller and channel number, and to extract them. Modify the edma_alloc_slot function to take an extra argument for the controller. Also update ASoC drivers to use API. ASoC changes Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> - Move queue related mappings to dm<soc>.c EDMA in DM355 and DM644x has two transfer controllers while DM646x has four transfer controllers. Moving the queue to tc mapping and queue priority mapping to dm<soc>.c will be helpful to probe these mappings from platform device so that the machine_is_* testing will be avoided. - add channel mapping logic Channel mapping logic is introduced in dm646x EDMA. This implies that there is no fixed association for a channel number to a parameter entry number. In other words, using the DMA channel mapping registers (DCHMAPn), a PaRAM entry can be mapped to any channel. While in the case of dm644x and dm355 there is a fixed mapping between the EDMA channel and Param entry number. Signed-off-by: Naresh Medisetty <naresh@ti.com> Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Reviewed-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* ARM: 5673/1: U300 fix initsection compile warningLinus Walleij2009-08-15
| | | | | | | | | The u300_init_check_chip() function was not properly tagged with the __init macro and provided a initsection mismatch on compilation. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 's3c-fixes' of git://aeryn.fluff.org.uk/bjdooks/linuxRussell King2009-08-15
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| * ARM: S3C24XX: Fix clkout mpx errorDavide Rizzo2009-08-13
| | | | | | | | | | | | | | | | Bug correction: CLK Outputs cannot have XTAL as parent Signed-off-by: Davide Rizzo <elpa.rizzo@gmail.com> [ben-linux@fluff.org: updated patch subject] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
* | Merge branch 'for-rmk-rc' of git://git.pengutronix.de/git/imx/linux-2.6Russell King2009-08-15
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| * | mx31moboard: invert sdhc ro signal senseValentin Longchamp2009-08-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Small confusion with our hardware engineer, the WP signal (RO) is active low on our boards, the signal has to inverted. This is a pretty straightforward patch, it could even go to -rc, but if not, then push it for 2.6.32. Signed-off-by: Valentin Longchamp <valentin.longchamp@epfl.ch> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | mx3: Fix double pin allocation in pcm037_eet.cGuennadi Liakhovetski2009-07-31
| | | | | | | | | | | | | | | | | | | | | SPI pins are now allocated in pcm037.c, remove them from EET. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | ARM: Fix broken highmem supportRussell King2009-08-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, highmem is selectable, and you can request an increased vmalloc area. However, none of this has any effect on the memory layout since a patch in the highmem series was accidentally dropped. Moreover, even if you did want highmem, all memory would still be registered as lowmem, possibly resulting in overflow of the available virtual mapping space. The highmem boundary is determined by the highest allowed beginning of the vmalloc area, which depends on its configurable minimum size (see commit 60296c71f6c5063e3c1f1d2619ca0b60940162e7 for details on this). We should create mappings and initialize bootmem only for low memory, while the zone allocator must still be told about highmem. Currently, memory nodes which are completely located in high memory are not supported. This is not a huge limitation since systems relying on highmem support are unlikely to have discontiguous memory with large holes. [ A similar patch was meant to be merged before commit 5f0fbf9ecaf3 and be available in Linux v2.6.30, however some git rebase screw-up of mine dropped the first commit of the series, and that goofage escaped testing somehow as well. -- Nico ] Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Reviewed-by: Nicolas Pitre <nico@marvell.com>
* | | Merge branch 'ixp4xx-fixes' of ↵Russell King2009-08-13
|\ \ \ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/chris/linux-2.6
| * | | IXP4xx: Fix IO_SPACE_LIMIT for 2.6.31-rc core PCI changesMikael Pettersson2009-08-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2.6.31-rc kernels don't boot on my ixp4xx box (ds101), because the libata driver doesn't find the PCI IDE controller any more. 2.6.30 was fine. I traced this to a PCI update (1f82de10d6b1d845155363c895c552e61b36b51a) in 2.6.30-git19. Diffing the kernel boot logs from 2.6.30-git18 and 2.6.30-git19 illustrates the breakage: > --- dmesg-2.6.30-git18 2009-08-04 01:45:22.000000000 +0200 > +++ dmesg-2.6.30-git19 2009-08-04 01:45:46.000000000 +0200 > @@ -26,6 +26,13 @@ > pci 0000:00:02.2: PME# supported from D0 D1 D2 D3hot > pci 0000:00:02.2: PME# disabled > PCI: bus0: Fast back to back transfers disabled > +pci 0000:00:01.0: BAR 0: can't allocate I/O resource [0x10000-0xffff] > +pci 0000:00:01.0: BAR 1: can't allocate I/O resource [0x10000-0xffff] > +pci 0000:00:01.0: BAR 2: can't allocate I/O resource [0x10000-0xffff] > +pci 0000:00:01.0: BAR 3: can't allocate I/O resource [0x10000-0xffff] > +pci 0000:00:01.0: BAR 4: can't allocate I/O resource [0x10000-0xffff] > +pci 0000:00:02.0: BAR 4: can't allocate I/O resource [0x10000-0xffff] > +pci 0000:00:02.1: BAR 4: can't allocate I/O resource [0x10000-0xffff] > bio: create slab <bio-0> at 0 > SCSI subsystem initialized > NET: Registered protocol family 2 > @@ -44,11 +51,7 @@ > console [ttyS0] enabled > serial8250.0: ttyS1 at MMIO 0xc8001000 (irq = 13) is a XScale > Driver 'sd' needs updating - please use bus_type methods > -PCI: enabling device 0000:00:01.0 (0140 -> 0141) > -scsi0 : pata_artop > -scsi1 : pata_artop > -ata1: PATA max UDMA/100 cmd 0x1050 ctl 0x1060 bmdma 0x1040 irq 28 > -ata2: PATA max UDMA/100 cmd 0x1058 ctl 0x1064 bmdma 0x1048 irq 28 > +pata_artop 0000:00:01.0: no available native port > Using configured DiskOnChip probe address 0x50000000 > DiskOnChip found at 0x50000000 > NAND device: Manufacturer ID: 0x98, Chip ID: 0x73 (Toshiba NAND 16MiB 3,3V 8-bit) The specific change in 1f82de10d6b1d845155363c895c552e61b36b51a responsible for this failure turned out to be the following: > --- a/drivers/pci/probe.c > +++ b/drivers/pci/probe.c > @@ -193,7 +193,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, > res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; > if (type == pci_bar_io) { > l &= PCI_BASE_ADDRESS_IO_MASK; > - mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff; > + mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT; > } else { > l &= PCI_BASE_ADDRESS_MEM_MASK; > mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; Every arch except arm's ixp4xx defines IO_SPACE_LIMIT as an all-bits-one bitmask, typically -1UL but sometimes only a 16-bit 0x0000ffff. But ixp4xx defines it as 0xffff0000, which is now causing the PCI failures. Russell King noted that ixp4xx has 64KB PCI IO space, so IO_SPACE_LIMIT should be 0x0000ffff. This patch makes that change, which fixes the PCI failures on my ixp4xx box. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
* | | | Merge branch 'pm-upstream/fixes' of ↵Russell King2009-08-10
|\ \ \ \ | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm
| * | | | OMAP3: Overo: add missing pen-down GPIO definitionKevin Hilman2009-08-05
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | | | OMAP: GPIO: clear/restore level/edge detect settings on mask/unmaskKevin Hilman2009-08-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If IRQ triggering is enabled, it can trigger a pending interrupt even for masked interrupts. Any pending GPIO interrupts can prevent the powerdomain from hitting retention. Problem found, reported and additional review and testing by Chunquiu Wang. Tested-by: Chunquiu Wang <cqwang@motorola.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | | | OMAP3: PM: Fix wrong sequence in suspend.Jouni Hogander2009-08-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Powerdomain previous state is checked after restoring new states in suspend. This patch fixes this problem. Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | | | OMAP: PM: CPUfreq: obey min/max settings of policyEero Nurkkala2009-08-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the min/max settings from CPUfreq policy rather than processor defined min/max settings. Without this patch, it's possible to scale frequency outside the current policy range. Signed-off-by: Eero Nurkkala <ext-eero.nurkkala@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | | | OMAP2/3/4: UART: allow in-order port traversalKevin Hilman2009-08-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use list_add_tail() when adding discovered UART ports. This is so traversal using list_for_each_entry() will traverse the list in the order they were found. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | | | OMAP2/3/4: UART: Allow per-UART disabling wakeup for serial portsKevin Hilman2009-08-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch causes the OMAP uarts to honor the sysfs power/wakeup file for IOPAD wakeups. Before the OMAP was always woken up from off mode on a rs232 signal change. This patch also creates a different platform device for each serial port so that the wakeup properties can be control per port. By default, IOPAD wakeups are enabled for each UART. To disable, # echo disabled > /sys/devices/platform/serial8250.0/power/wakeup Where serial8250.0 can be replaced by .1, or .2 to control the other ports. Original idea and original patch from Russ Dill <russ.dill@gmail.com> Cc: Russ Dill <russ.dill@gmail.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | | | OMAP3: Fixed crash bug with serial + suspendTero Kristo2009-08-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It was possible for an unhandled interrupt to occur if there was incoming serial traffic during wakeup from suspend. This was caused by the code in arch-arm/mach-omap2/serial.c keeping interrupt enabled all the time, but not acking its interrupts. Applies on top of PM branch. Use the PM begin/end hooks to ensure that the "serial idle" interrupts are disabled during the suspend path. Also, since begin/end hooks are now used, use the suspend_state that is passed in the begin hook instead of the enter hook as per the platform_suspend_ops docs. Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | | | OMAP4: UART: cleanup special case IRQ handlingKevin Hilman2009-08-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Streamline the OMAP4 special IRQ assignments by putting inside normal init loop instead of having a separate loop. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | | | OMAP3: PM: Do not build suspend code if SUSPEND is not enabledKevin Hilman2009-08-05
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | | | OMAP3: PM: prevent module wakeups from waking IVA2Kevin Hilman2009-08-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default, prevent functional wakeups from inside a module from waking up the IVA2. Let DSP Bridge code handle this when loaded. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | | | OMAP3: PM: Clear pending PRCM reset flags on initKevin Hilman2009-08-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Any pending reset flags can prevent retention. Ensure they are all cleared during boot. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | | | OMAP3: PM: Ensure PRCM interrupts are cleared at bootKevin Hilman2009-08-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Any pending PRCM interrupts can prevent retention. Ensure they are cleared during boot. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | | | OMAP3: PM: CM_REGADDR macros using wrong nameKevin Hilman2009-08-05
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * | | | OMAP2/3: PM: make PM __init calls staticKevin Hilman2009-08-05
| |/ / / | | | | | | | | | | | | Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* | | | Merge branch 'omap_fixes_31' of git://git.pwsan.com/linux-2.6Russell King2009-08-10
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| * | | | OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSBPaul Walmsley2009-07-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS, USBHOST, and HSOTGUSB devices. These devices are both interconnect initiators and targets. Without this patch, clk_enable()s on clocks for these modules can be very high latency (potentially up to ~200 milliseconds) and message such as the following are generated: Clock usbhost_48m_fck didn't enable in 100000 tries Two bugs are fixed by this patch. First, OMAP hardware only supports target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips should not wait for these clocks to enable. So, split the appropriate clocks into ES1 and ES2+ variants, so that kernels running on ES1 devices won't try to wait. Second, the current heuristic in omap2_clk_dflt_find_idlest() will fail for these clocks. It assumes that the CM_IDLEST bit to wait upon is the same as the CM_*CLKEN bit, which is false[1]. Fix by implementing custom clkops .find_idlest function pointers for the appropriate clocks that return the correct slave IDLEST bit shift. This was originally fixed in the linux-omap kernel during 2.6.29 in a slightly different manner[2][3]. In the medium-term future, all of the module IDLEST code will eventually be moved to the omap_hwmod code. Problem reported by Jarkko Nikula <jhnikula@gmail.com>: http://marc.info/?l=linux-omap&m=124306184903679&w=2 ... 1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the DSS case). 2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq. 3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Jarkko Nikula <jhnikula@gmail.com>
| * | | | OMAP2 clock: 2430 I2CHS uses non-standard CM_IDLEST registerPaul Walmsley2009-07-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE [1]. Fix by implementing a custom clkops .find_idlest function to return the correct slave IDLEST register. ... 1. OMAP2430 Multimedia Device Package-on-Package (POP) Silicon Revision 2.1 (Rev. V) Technical Reference Manual, tables 4-99 and 4-105. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | | OMAP2/3 clock: split, rename omap2_wait_clock_ready()Paul Walmsley2009-07-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some OMAP2/3 hardware modules have CM_IDLEST attributes that are not handled by the current omap2_wait_clock_ready() code. In preparation for patches that fix the unusual devices, rename the function omap2_wait_clock_ready() to omap2_wait_module_ready() and split it into three parts: 1. A clkops-specific companion clock return function (by default, omap2_clk_dflt_find_companion()) 2. A clkops-specific CM_IDLEST register address and bit shift return function (by default, omap2_clk_dflt_find_idlest()) 3. Code to wait for the CM to indicate that the module is ready (omap2_cm_wait_idlest()) Clocks can now specify their own custom find_companion() and find_idlest() functions; used in subsequent patches. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | | OMAP3 SDRC: Move the clk stabilization delay to the right placeRajendra Nayak2009-07-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock stabilization delay post a M2 divider change is needed even before a SDRC interface clock re-enable and not only before jumping back to SDRAM. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | | OMAP3 SDRC: Fix freeze when scaling CORE dpll to < 83MhzRajendra Nayak2009-07-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a bug in the CORE dpll scaling sequence which was errouneously clearing some bits in the SDRC DLLA CTRL register and hence causing a freeze. The issue was observed only on platforms which scale CORE dpll to < 83Mhz and hence program the DLL in fixed delay mode. Issue reported by Limei Wang <E12499@motorola.com>, with debugging assistance from Richard Woodruff <r-woodruff2@ti.com> and Girish Ghongdemath <girishsg@ti.com>. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Cc: Limei Wang <E12499@motorola.com> Cc: Richard Woodruff <r-woodruff2@ti.com> Cc: Girish Ghongdemath <girishsg@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> [paul@pwsan.com: updated patch description to include collaboration credits]
| * | | | OMAP2/3 SDRC: don't set SDRC_POWER.PWDENA on bootPaul Walmsley2009-07-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stop setting SDRC_POWER.PWDENA on boot. There is a nasty erratum (34xx erratum 1.150) that can cause memory corruption if PWDENA is enabled. Based originally on a patch from Samu P. Onkalo <samu.p.onkalo@nokia.com>. Tested on BeagleBoard rev C2. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Samu P. Onkalo <samu.p.onkalo@nokia.com>
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