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* [PATCH] GPIO API: SA1100 wrapper cleanupPhilipp Zabel2007-02-20
| | | | | | | | | | | | | | Based on the discussion last december (http://lkml.org/lkml/2006/12/20/241), this patch - adds gpio_direction_input/output functions to generic.c instead of making them inline, - fixes comment and includes and uses inline functions instead of macros in gpio.h Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [PATCH] GPIO API: PXA wrapper cleanupPhilipp Zabel2007-02-20
| | | | | | | | | | | | | | | | | | Based on the discussion last december (http://lkml.org/lkml/2006/12/20/242), this patch: - moves the PXA_LAST_GPIO check into pxa_gpio_mode - fixes comment and includes in gpio.h - replaces the gpio_set/get_value macros with inline functions and adds a non-inline version to avoid code explosion when gpio is not a constant. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Nicolas Pitre <nico@cam.org> Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge ARM fixesRussell King2007-02-20
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| * [ARM] 4165/1: S3C24XX: Select CONFIG_NO_IOPORTBen Dooks2007-02-20
| | | | | | | | | | | | | | | | On S3C24XX architecture, select CONFIG_NO_IOPORT as we only have memory based IO. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] fix mach-at91 build breakageDavid Brownell2007-02-20
| | | | | | | | | | | | | | | | | | The rename of the AT91 subtree from mach-at91rm9200 to mach-at91 (to accomodate at91sam926x processors) was incomplete. It needs this patch to be able to build again. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] Fix jornada720 build errorsRussell King2007-02-20
| | | | | | | | | | | | | | | | | | kernel/built-in.o: In function `pm_suspend': utsname_sysctl.c:(.text+0x23008): multiple definition of `pm_suspend' arch/arm/mach-sa1100/built-in.o:arch/arm/mach-sa1100/sleep.S:(.text+0xf68): first defined here arm-linux-ld: Warning: size of symbol `pm_suspend' changed from 20 in arch/arm/mach-sa1100/built-in.o to 44 in kernel/built-in.o Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] Fix iop13xx build errorRussell King2007-02-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CC arch/arm/mach-iop13xx/setup.o arch/arm/mach-iop13xx/setup.c: In function 'iq8134x_probe_flash_size': arch/arm/mach-iop13xx/setup.c:210: warning: implicit declaration of function 'ioremap' arch/arm/mach-iop13xx/setup.c:210: warning: initialization makes pointer from integer without a cast arch/arm/mach-iop13xx/setup.c:218: warning: implicit declaration of function 'writew' arch/arm/mach-iop13xx/setup.c:222: warning: implicit declaration of function 'readb' arch/arm/mach-iop13xx/setup.c:231: warning: implicit declaration of function 'iounmap' LD .tmp_vmlinux1 arch/arm/mach-iop13xx/built-in.o: In function `iop13xx_platform_init': iq81340mc.c:(.init.text+0x150): undefined reference to `ioremap' iq81340mc.c:(.init.text+0x21c): undefined reference to `writew' iq81340mc.c:(.init.text+0x24c): undefined reference to `writew' iq81340mc.c:(.init.text+0x254): undefined reference to `iounmap' iq81340mc.c:(.init.text+0x2c4): undefined reference to `readb' iq81340mc.c:(.init.text+0x2e8): undefined reference to `readb' Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] Fix build error caused by move of apmRussell King2007-02-20
| | | | | | | | | | | | | | | | CC arch/arm/common/sharpsl_pm.o arch/arm/common/sharpsl_pm.c:30:31: error: asm/apm-emulation.h: No such file or directory ... Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * Merge git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivialLinus Torvalds2007-02-19
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial: (25 commits) Documentation/kernel-docs.txt update. arch/cris: typo in KERN_INFO Storage class should be before const qualifier kernel/printk.c: comment fix update I/O sched Kconfig help texts - CFQ is now default, not AS. Remove duplicate listing of Cris arch from README kbuild: more doc. cleanups doc: make doc. for maxcpus= more visible drivers/net/eexpress.c: remove duplicate comment add a help text for BLK_DEV_GENERIC correct a dead URL in the IP_MULTICAST help text fix the BAYCOM_SER_HDX help text fix SCSI_SCAN_ASYNC help text trivial documentation patch for platform.txt Fix typos concerning hierarchy Fix comment typo "spin_lock_irqrestore". Fix misspellings of "agressive". drivers/scsi/a100u2w.c: trivial typo patch Correct trivial typo in log2.h. Remove useless FIND_FIRST_BIT() macro from cardbus.c. ...
| | * kbuild: Replace remaining "depends" with "depends on"Robert P. J. Day2007-02-17
| | | | | | | | | | | | | | | | | | | | | | | | Replace the very few remaining "depends" Kconfig directives with "depends on". Signed-off-by: Robert P. J. Day <rpjday@mindspring.com> Signed-off-by: Adrian Bunk <bunk@stusta.de>
| * | Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2007-02-19
| |\ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (117 commits) [ARM] 4058/2: iop32x: set ->broken_parity_status on n2100 onboard r8169 ports [ARM] 4140/1: AACI stability add ac97 timeout and retries [ARM] 4139/1: AACI record support [ARM] 4138/1: AACI: multiple channel support for IRQ handling [ARM] 4211/1: Provide a defconfig for ns9xxx [ARM] 4210/1: base for new machine type "NetSilicon NS9360" [ARM] 4222/1: S3C2443: Remove reference to missing S3C2443_PM [ARM] 4221/1: S3C2443: DMA support [ARM] 4220/1: S3C24XX: DMA system initialised from sysdev [ARM] 4219/1: S3C2443: DMA source definitions [ARM] 4218/1: S3C2412: fix CONFIG_CPU_S3C2412_ONLY wrt to S3C2443 [ARM] 4217/1: S3C24XX: remove the dma channel show at startup [ARM] 4090/2: avoid clash between PXA and SA1111 defines [ARM] 4216/1: add .gitignore entries for ARM specific files [ARM] 4214/2: S3C2410: Add Armzone QT2410 [ARM] 4215/1: s3c2410 usb device: per-platform vbus_draw [ARM] 4213/1: S3C2410 - Update definition of ADCTSC_XY_PST [ARM] 4098/1: ARM: rtc_lock only used with rtc_cmos [ARM] 4137/1: Add kexec support [ARM] 4201/1: SMP barriers pair needed for the secondary boot process ... Fix up conflict due to typedef removal in sound/arm/aaci.h
| * | [PATCH] genirq: remove IRQ_DISABLEDIngo Molnar2007-02-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that disable_irq() defaults to delayed-disable semantics, the IRQ_DISABLED flag is not needed anymore. Signed-off-by: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | [PATCH] clocksource: fixup is_continous changes on ARMThomas Gleixner2007-02-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixup the is_contionous replacement by a flag field. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Cc: Russell King <rmk@arm.linux.org.uk> Cc: john stultz <johnstul@us.ibm.com> Cc: Roman Zippel <zippel@linux-m68k.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | [PATCH] sysctl: remove insert_at_head from register_sysctlEric W. Biederman2007-02-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The semantic effect of insert_at_head is that it would allow new registered sysctl entries to override existing sysctl entries of the same name. Which is pain for caching and the proc interface never implemented. I have done an audit and discovered that none of the current users of register_sysctl care as (excpet for directories) they do not register duplicate sysctl entries. So this patch simply removes the support for overriding existing entries in the sys_sysctl interface since no one uses it or cares and it makes future enhancments harder. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: David Howells <dhowells@redhat.com> Cc: "Luck, Tony" <tony.luck@intel.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Andi Kleen <ak@muc.de> Cc: Jens Axboe <axboe@kernel.dk> Cc: Corey Minyard <minyard@acm.org> Cc: Neil Brown <neilb@suse.de> Cc: "John W. Linville" <linville@tuxdriver.com> Cc: James Bottomley <James.Bottomley@steeleye.com> Cc: Jan Kara <jack@ucw.cz> Cc: Trond Myklebust <trond.myklebust@fys.uio.no> Cc: Mark Fasheh <mark.fasheh@oracle.com> Cc: David Chinner <dgc@sgi.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Patrick McHardy <kaber@trash.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | [PATCH] mark struct file_operations const 2Arjan van de Ven2007-02-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many struct file_operations in the kernel can be "const". Marking them const moves these to the .rodata section, which avoids false sharing with potential dirty data. In addition it'll catch accidental writes at compile time to these shared resources. [akpm@osdl.org: sparc64 fix] Signed-off-by: Arjan van de Ven <arjan@linux.intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | [PATCH] Dynamic kernel command-line: armAlon Bar-Lev2007-02-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Rename saved_command_line into boot_command_line. 2. Set command_line as __initdata. Signed-off-by: Alon Bar-Lev <alon.barlev@gmail.com> Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | [PATCH] AT91 GPIO wrappersDavid Brownell2007-02-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a first cut at making the AT91 code use the generic GPIO calls. Note that the original AT91 GPIO calls merged the "mux pin as GPIO" and "set GPIO direction" functionality into one API call, contrary to what's specified as a cross-platform portable model. So this involved a few non-inlinable functions. [akpm@osdl.org: cleanups] Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | [PATCH] sort the devres mess outAl Viro2007-02-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Split the implementation-agnostic stuff in separate files. * Make sure that targets using non-default request_irq() pull kernel/irq/devres.o * Introduce new symbols (HAS_IOPORT and HAS_IOMEM) defaulting to positive; allow architectures to turn them off (we needed these symbols anyway for dependencies of quite a few drivers). * protect the ioport-related parts of lib/devres.o with CONFIG_HAS_IOPORT. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | [PATCH] Consolidate default sched_clock()Alexey Dobriyan2007-02-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use attribute(weak). Signed-off-by: Alexey Dobriyan <adobriyan@openvz.org> Acked-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | [PATCH] disable init/initramfs.c: architecturesJean-Paul Saman2007-02-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update all arch/*/kernel/vmlinux.lds.S to not include space for initramfs when CONFIG_BLK_DEV_INITRAMFS is not selected. This saves another 4 kbytes on most platfoms (some reserve PAGE_SIZE for initramfs). Signed-off-by: Jean-Paul Saman <jean-paul.saman@nxp.com> Cc: Al Viro <viro@zeniv.linux.org.uk> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | [PATCH] Set CONFIG_ZONE_DMA for arches with GENERIC_ISA_DMAChristoph Lameter2007-02-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As Andi pointed out: CONFIG_GENERIC_ISA_DMA only disables the ISA DMA channel management. Other functionality may still expect GFP_DMA to provide memory below 16M. So we need to make sure that CONFIG_ZONE_DMA is set independent of CONFIG_GENERIC_ISA_DMA. Undo the modifications to mm/Kconfig where we made ZONE_DMA dependent on GENERIC_ISA_DMA and set theses explicitly in each arches Kconfig. Reviews must occur for each arch in order to determine if ZONE_DMA can be switched off. It can only be switched off if we know that all devices supported by a platform are capable of performing DMA transfers to all of memory (Some arches already support this: uml, avr32, sh sh64, parisc and IA64/Altix). In order to switch ZONE_DMA off conditionally, one would have to establish a scheme by which one can assure that no drivers are enabled that are only capable of doing I/O to a part of memory, or one needs to provide an alternate means of performing an allocation from a specific range of memory (like provided by alloc_pages_range()) and insure that all drivers use that call. In that case the arches alloc_dma_coherent() may need to be modified to call alloc_pages_range() instead of relying on GFP_DMA. Signed-off-by: Christoph Lameter <clameter@sgi.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | [APM] ARM: Convert to use shared APM emulation.Ralf Baechle2007-02-09
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | [ARM] Merge remaining IOP codeRussell King2007-02-20
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | Conflicts: include/asm-arm/arch-at91rm9200/entry-macro.S Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] 4187/1: iop: unify time implementation across iop32x, iop33x, and iop13xxDan Williams2007-02-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * architecture specific details are handled in asm/arch/time.h * ARCH_IOP13XX now selects PLAT_IOP * as suggested by Lennert use ifdef CONFIG_XSCALE to skip the cp_wait on XSC3 Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] 4186/1: iop: remove cp6_enable/disable routinesDan Williams2007-02-17
| | | | | | | | | | | | | | | | | | | | | This functionality is replaced by cp6_trap Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] 4185/2: entry: introduce get_irqnr_preamble and arch_ret_to_userDan Williams2007-02-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_irqnr_preamble allows machines to take some action before entering the get_irqnr_and_base loop. On iop we enable cp6 access. arch_ret_to_user is added to the userspace return path to allow individual architectures to take actions, like disabling coprocessor access, before the final return to userspace. Per Nicolas Pitre's note, there is no need to cp_wait on the return to user as the latency to return is sufficient. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | Merge the easy part of the IOP branchRussell King2007-02-18
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| * | [ARM] 4184/1: iop: cp6 access handler (undef_hook)Dan Williams2007-02-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable svc access to cp6 via an undefined instruction hook. Do not enable access for usr code. This patch also makes iop13xx select PLAT_IOP, this requires a small change to drivers/i2c/busses/i2c-iop3xx.c. Per Lennert Buytenhek's note, the cp6 trap routine is moved to arch/arm/plat-iop Per Nicolas Pitre's note, the cp_wait is skipped since the latency to return to the faulting function is longer than cp_wait. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] 4183/1: do_undefinstr: read svc undefined instructions with svc privilegesDan Williams2007-02-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | do_undefinstr currently does not expect undefined instructions in kernel code, since it always uses get_user() to read the instruction. Dereference the 'pc' pointer directly in the SVC case. Per Nicolas Pitre's note, kernel code is never in thumb mode. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] 4182/1: iop3xx: fix the ioremap implementation to not remap static rangesDan Williams2007-02-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a custom ioremap implementation for iop3xx. This saves establishing new mappings. It also cleans up the PCI IO resource to be a physical address rather than a virtual address as Russell pointed out on the original iop13xx port. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | Merge NetSilicon NS93xx treeRussell King2007-02-18
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixed conflicts: arch/arm/Makefile arch/arm/mm/Kconfig Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | [ARM] 4211/1: Provide a defconfig for ns9xxxUwe Kleine-König2007-02-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a follow up for the patch providing the base support for the ns9xxx machine type. Signed-off-by: Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | [ARM] 4210/1: base for new machine type "NetSilicon NS9360"Uwe Kleine-König2007-02-17
| |/ / | | | | | | | | | | | | Signed-off-by: Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] 4058/2: iop32x: set ->broken_parity_status on n2100 onboard r8169 portsLennert Buytenhek2007-02-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | On the n2100, both onboard r8169 ports exhibit PCI parity problems. Set the ->broken_parity_status flag for both ports so that the r8169 drivers knows it should ignore error interrupts. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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*---------. \ \ Merge AT91, EP93xx, General devel, PXA, S3C, V6+ and Xscale treesRussell King2007-02-17
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| | | | | | * | | [ARM] 4123/1: xsc3: general cleanupLennert Buytenhek2007-02-08
| | | | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up proc-xsc3: - Correct a number of typos. - Fix up indentation in a number of places. - Change references to the various caches to be more clear about whether we're talking about the L1 D, the L1 I or the unified L2 cache. - Rename "drain write buffer" to "data write barrier", the official name used in the Manzano manual. - Change the xsc3 cpu name from "XScale-Core3" to "XScale-V3 based processor". Also, since a previously merged patch implements proper support for using a MAC or iWMMXt coprocessor on xsc3 platforms, we no longer need to enable access to CP0 on boot. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | [ARM] 4201/1: SMP barriers pair needed for the secondary boot processCatalin Marinas2007-02-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some situations, the pen_release store in platform_secondary_init() may stay forever in the write buffer while the CPU is waiting on the boot_lock to be released in boot_secondary(). The primary CPU could never see the pen_release update without the barriers. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | [ARM] 4130/1: Add L220 support to RealView/EBCatalin Marinas2007-02-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the L220 on the RealView/EB MPCore platform. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | Merge Realview GIC codeRussell King2007-02-15
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| | | | | | * | | [ARM] 4109/2: Add support for the RealView/EB MPCore revC platformCatalin Marinas2007-02-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel originally supported revB only. This patch enables revC by default and adds a config option for building the kernel for the revB platform. Since the SCU base address was hard-coded in the proc-v6.S file (and only valid for RealView/EB revB), this patch also adds a more generic support for defining the SCU information. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | [ARM] 4190/2: Add the secondary GIC support for the RealView/EBCatalin Marinas2007-02-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPCore platform This patch adds the registration of the secondary GIC on the baseboard, together with the IRQ chaining setup. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | [ARM] 4108/2: Allow multiple GIC interrupt controllers in a systemCatalin Marinas2007-02-15
| | | | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation only assumes one GIC to be present in the system. However, there are platforms with more than one cascaded interrupt controllers (RealView/EB MPCore for example). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | [ARM] 4135/1: Add support for the L210/L220 cache controllersCatalin Marinas2007-02-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the support for the L210/L220 (outer) cache controller. The cache range operations are done by index/way since L2 cache controller only accepts physical addresses. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | [ARM] Always mark ARMv6 PTWs outer cacheableRussell King2007-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other platforms other than SMP may have an outer cache. For these, we also need to mark the page table walks outer cacheable. Since marking the walks always outer cacheable apparantly has no side effects, we might as well always mark them so. However, we continue to only mark PTWs shared if we have SMP enabled. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | [ARM] 4153/1: fix consistent_sync() off-by-one BUG checkLennert Buytenhek2007-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In consistent_sync(), start + size can end up pointing one byte beyond the end of the direct RAM mapping. We shouldn't BUG() when this happens. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | [ARM] Convert DMA cache handling to take const void * argsRussell King2007-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMA cache handling functions take virtual addresses, but in the form of unsigned long arguments. This leads to a little confusion about what exactly they take. So, convert them to take const void * instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | [ARM] 4134/1: Add generic support for outer cachesCatalin Marinas2007-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The outer cache can be L2 as on RealView/EB MPCore platform or even L3 or further on ARMv7 cores. This patch adds the generic support for flushing the outer cache in the DMA operations. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | [ARM] Don't call consistent_sync() for DMA coherent memoryRussell King2007-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Memory allocated by the coherent memory allocators will be marked uncacheable, which means it's pointless calling consistent_sync() to perform cache maintainence on this memory; it's just a waste of CPU cycles. Moreover, with the (subsequent) merge of outer cache support, it actually breaks things to call consistent_sync() on anything but direct-mapped memory. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | [ARM] 4129/1: Add barriers after the TLB operationsCatalin Marinas2007-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The architecture specification states that TLB operations are guaranteed to be complete only after the execution of a DSB (Data Synchronisation Barrier, former Data Write Barrier or Drain Write Buffer). The branch target cache invalidation is also needed. The ISB (Instruction Synchronisation Barrier, formerly Prefetch Flush) is needed unless there will be a return from exception before the corresponding mapping is used (i.e. user mappings). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | [ARM] 4128/1: Architecture compliant TTBR changing sequenceCatalin Marinas2007-02-08
| | | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On newer architectures (ARMv6, ARMv7), the depth of the prefetch and branch prediction is implementation defined and there is a small risk of wrong ASID tagging when changing TTBR0 before setting the new context id. The recommended solution is to set a reserved ASID during TTBR changing. This patch reserves ASID 0. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-18 10:10:39 -0500