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* at91/atmel-mci: inclusion of sd/mmc driver in at91sam9g45 chip and boardNicolas Ferre2010-10-26
| | | | | | | | This adds the support of atmel-mci sd/mmc driver in at91sam9g45 devices and board files. This also configures the DMA controller slave interface for at_hdmac dmaengine driver. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* AT91: pm: make sure that r0 is 0 when dealing with cache operationsNicolas Ferre2010-10-26
| | | | | | | When using CP15 cache operations (c7), we make sure that Rd (r0) is actually 0 as ARM 926 TRM is saying. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* AT91: pm: use plain cpu_do_idle() for "wait for interrupt"Nicolas Ferre2010-10-26
| | | | | | | | | | | For power management at91_pm_enter() routine, use the cpu_do_idle() for a rock solid "wait for interrupt" implementation. For AT91SAM9 ARM 926 based chips, we can exceed the cache line length as we can access RAM even while in self-refresh mode. We keep plain access to CP15 for at91rm9200 as this feature is not available: instructions have to be in a single cache line. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* AT91: reset: extend alternate reset procedure to several chipsNicolas Ferre2010-10-26
| | | | | | | | | Several at91sam9 chips need the alternate reset procedure to be sure to halt SDRAM smoothly before resetting the chip. This is an extension of previous patch "Fix AT91SAM9G20 reset" to all chips affected. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* AT91: reset routine cleanup, remove not needed icache flushNicolas Ferre2010-10-26
| | | | | | | | | | | | | Generalize assembler reset routine to allow use on several at91sam9 chips. This patch replace double definitions of SDRAM controller registers and RSTC registers with use of classical header files. For this rework, we remove the not needed icache flush as it is already done in the calling function: arm_machine_restart(). Rename at91sam9g20_reset.S to generalize to several chips. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* AT91: trivial: align comment of at91sam9g20_reset with one more tabNicolas Ferre2010-10-26
| | | | | | Preparing next patch with longer names Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* AT91: Fix AT91SAM9G20 reset as per the errata in the data sheetPeter Horton2010-10-26
| | | | | | | | | If the SDRAM is not cleanly shutdown before reset it can be left driving the bus, which then stops the bootloader booting from NAND. Signed-off-by: Peter Horton <phorton@bitbox.co.uk> [nicolas.ferre@atmel.com: change file header line order] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* AT91: add board support for Pcontrol_G20Peter Gsellmann2010-10-26
| | | | | | | | | Board is a carrier board for Stamp9G20, with additional peripherals for a building automation system Signed-off-by: Peter Gsellmann <pgsellmann@portner-elektronik.at> [nicolas.ferre@atmel.com: remove machine_desc.io_pg_offst and .phys_io] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* Merge branch 'for-next' of git://android.git.kernel.org/kernel/tegraLinus Torvalds2010-10-25
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-next' of git://android.git.kernel.org/kernel/tegra: spi: tegra: fix error setting on timeout spi: add spi_tegra driver tegra: harmony: enable PCI Express tegra: add PCI Express support tegra: add PCI Express clocks [ARM] tegra: Add APB DMA support [ARM] tegra: Add cpufreq support [ARM] tegra: common: Update common clock init table [ARM] tegra: clock: Add dvfs support, bug fixes, and cleanups [ARM] tegra: Add support for reading fuses [ARM] tegra: gpio: Add suspend and wake support [ARM] tegra: pinmux: add safe values, move tegra2, add suspend [ARM] tegra: add suspend and mirror irqs to legacy controller [ARM] tegra: Add legacy irq support [ARM] tegra: update iomap
| * tegra: harmony: enable PCI ExpressMike Rapoport2010-10-21
| | | | | | | | | | | | | | Signed-off-by: Mike Rapoport <mike@compulab.co.il> CC: Olof Johansson <olof@lixom.net> CC: Gary King <GKing@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
| * tegra: add PCI Express supportMike Rapoport2010-10-21
| | | | | | | | | | | | | | | | | | Change-Id: Ibd0bcd46895eb88952b9db29e1f68572d39aae01 Signed-off-by: Mike Rapoport <mike@compulab.co.il> Acked-by: Arnd Bergmann <arnd@arndb.de> CC: Russell King <linux@arm.linux.org.uk> CC: Gary King <GKing@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
| * tegra: add PCI Express clocksMike Rapoport2010-10-21
| | | | | | | | | | | | Signed-off-by: Mike Rapoport <mike@compulab.co.il> CC: Gary King <GKing@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
| * [ARM] tegra: Add APB DMA supportColin Cross2010-10-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The APB DMA block handles DMA transfers to and from some peripherals in the Tegra SOC. It reads from sequential addresses on the memory bus, and writes repeatedly to the same address on the APB bus. Two transfer modes are supported, oneshot for transferring a known size to or from a peripheral, and continuous for streaming data. In continuous mode, a callback occurs when the buffer is half full to allow the existing data to be handled and a new request queued.x v2 changes: dma API no longer uses PTR_ERR Signed-off-by: Erik Gilling <konkers@android.com> Signed-off-by: Colin Cross <ccross@android.com>
| * [ARM] tegra: Add cpufreq supportColin Cross2010-10-21
| | | | | | | | | | | | | | | | | | Implement cpufreq support for the Tegra SOC. DVFS is handled by the core virtual cpu clock. The frequencies of the two cores are tied together, the highest frequency requested by either core determines the actual frequency. Signed-off-by: Colin Cross <ccross@android.com>
| * [ARM] tegra: common: Update common clock init tableColin Cross2010-10-21
| | | | | | | | | | | | Renames clocks in the clock init table to match the datasheet names Signed-off-by: Colin Cross <ccross@android.com>
| * [ARM] tegra: clock: Add dvfs support, bug fixes, and cleanupsColin Cross2010-10-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add drivers to clock lookup table - Add new pll_m entries - Support I2C U16 divider - Fix rate reporting on 32.768kHz clock - Call propagate rate only if set_rate succeeds - Add support for audio_sync clock - Add 24MHz to PLLA frequency list - Correct i2s1/2/spdifout mux - Add suspend support - Fix enable/disable parent clocks in set_parent - Add max_rate parameter to all clocks - DVFS support - Add virtual cpu clock with dvfs - Support clk_round_rate - Fix requesting very high periph frequencies - Add quirks for PLLU: PLLU is slightly different from the rest of the PLLs. The lock enable bit is at bit 22 instead of 18 in the MISC register, and the post divider field is a single bit with reversed values from other PLLs. - Simplify recalculating clock rates - Fix UART divider flags - Remove unused clock ops Signed-off-by: Colin Cross <ccross@android.com>
| * [ARM] tegra: Add support for reading fusesColin Cross2010-10-21
| | | | | | | | | | | | | | | | The Tegra SOC contains fuses to identify the CPU type and bin, and a unique id. The CPU info is required to determine the correct voltages for each cpu and core frequency. Signed-off-by: Colin Cross <ccross@android.com>
| * [ARM] tegra: gpio: Add suspend and wake supportColin Cross2010-10-21
| | | | | | | | | | | | | | Includes checkpatch fixes and TEGRA_NR_GPIOS changes from Mike Rapoport <mike@compulab.co.il> Signed-off-by: Colin Cross <ccross@android.com>
| * [ARM] tegra: pinmux: add safe values, move tegra2, add suspendColin Cross2010-10-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - the reset values for some pin groups in the tegra pin mux can result in functional errors due to conflicting with actively-configured pin groups muxing from the same controller. this change adds a known safe, non- conflicting mux for every pin group, which can be used on platforms where the pin group is not routed to any peripheral - also add each pin group's I/O voltage rail, to enable platform code to map from the pin groups used by each interface to the regulators used for dynamic voltage control - add routines to individually configure the tristate, pin mux and pull- ups for a pingroup_config array, so that it is possible to program individual values at run-time without modifying other values. this allows driver power-management code to reprogram individual interfaces into lower power states during idle / suspend, or to reprogram the pin mux to support multiple physical busses per internal controller (e.g., sharing a single I2C or SPI controller across multiple pin groups) - move chip-specific data like pingroups and drive-pingroups out of the common code and into chip-specific code - fix debug output for group with no pullups - add a TEGRA_MUX_SAFE function. Setting a pingroup to TEGRA_MUX_SAFE will automatically select a mux setting that is guaranteed not to conflict with any of the hardware blocks. Signed-off-by: Gary King <gking@nvidia.com>
| * [ARM] tegra: add suspend and mirror irqs to legacy controllerGary King2010-10-21
| | | | | | | | | | | | | | | | | | | | mirror IRQ enable and disable operations on the legacy PPI system interrupt controller, since the legacy controller is responsible for responding to wakeup interrupts when the CPU is in LP2 idle mode save the irq controller state on suspend and restore on resume Signed-off-by: Gary King <gking@nvidia.com>
| * [ARM] tegra: Add legacy irq supportColin Cross2010-10-21
| | | | | | | | | | | | | | | | The "legacy irq controller" duplicates the functionality of the GIC, but remains powered during the cpu suspend and idle modes that power down the CPU and the GIC. Signed-off-by: Colin Cross <ccross@android.com>
| * [ARM] tegra: update iomapColin Cross2010-10-21
| | | | | | | | | | | | | | | | Add missing io address map entries from datasheet. Add the IRAM area to the statically mapped io regions. Correct the onewire, USB, and statmon addresses Signed-off-by: Colin Cross <ccross@android.com>
* | Merge branch 'hwmon-for-linus' of ↵Linus Torvalds2010-10-25
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/groeck/staging * 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/staging: (24 commits) hwmon: lis3: Release resources in case of failure hwmon: lis3: Short explanations of platform data fields hwmon: lis3: Enhance lis3 selftest with IRQ line test hwmon: lis3: use block read to access data registers hwmon: lis3: Adjust fuzziness for 8 bit device hwmon: lis3: New parameters to platform data hwmon: lis3: restore axis enabled bits hwmon: lis3: Power on corrections hwmon: lis3: Update coordinates at polled device open hwmon: lis3: Cleanup interrupt handling hwmon: lis3: regulator control hwmon: lis3: pm_runtime support Kirkwood: add fan support for Network Space Max v2 hwmon: add generic GPIO fan driver hwmon: (coretemp) fix reading of microcode revision (v2) hwmon: ({core, pkg, via-cpu}temp) remove unnecessary CONFIG_HOTPLUG_CPU ifdefs hwmon: (pkgtemp) align driver initialization style with coretemp hwmon: LTC4261 Hardware monitoring driver hwmon: (lis3) add axes module parameter for custom axis-mapping hwmon: (hp_accel) Add HP Mini 510x family support ...
| * | Kirkwood: add fan support for Network Space Max v2Simon Guinot2010-10-25
| | | | | | | | | | | | | | | | | | Signed-off-by: Simon Guinot <sguinot@lacie.com> Acked-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
* | | Merge branch 'omap-for-linus' of ↵Linus Torvalds2010-10-25
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 * 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (163 commits) omap: complete removal of machine_desc.io_pg_offst and .phys_io omap: UART: fix wakeup registers for OMAP24xx UART2 omap: Fix spotty MMC voltages ASoC: OMAP4: MCPDM: Remove unnecessary include of plat/control.h serial: omap-serial: fix signess error OMAP3: DMA: Errata i541: sDMA FIFO draining does not finish omap: dma: Fix buffering disable bit setting for omap24xx omap: serial: Fix the boot-up crash/reboot without CONFIG_PM OMAP3: PM: fix scratchpad memory accesses for off-mode omap4: pandaboard: enable the ehci port on pandaboard omap4: pandaboard: Fix the init if CONFIG_MMC_OMAP_HS is not set omap4: pandaboard: remove unused hsmmc definition OMAP: McBSP: Remove null omap44xx ops comment OMAP: McBSP: Swap CLKS source definition OMAP: McBSP: Fix CLKR and FSR signal muxing OMAP2+: clock: reduce the amount of standard debugging while disabling unused clocks OMAP: control: move plat-omap/control.h to mach-omap2/control.h OMAP: split plat-omap/common.c OMAP: McBSP: implement functional clock switching via clock framework OMAP: McBSP: implement McBSP CLKR and FSR signal muxing via mach-omap2/mcbsp.c ... Fixed up trivial conflicts in arch/arm/mach-omap2/ {board-zoom-peripherals.c,devices.c} as per Tony
| * | omap: complete removal of machine_desc.io_pg_offst and .phys_ioAnand Gadiyar2010-10-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ab69bcd66fb4be64edfc767365cb9eb084961246 (arm: remove machine_desc.io_pg_offst and .phys_io) could not update the new boards in the omap tree. This causes the build of omap2plus_defconfig to fail. Fix this. Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: Eric Miao <eric.miao at canonical.com> [tony@atomide.com: updated description] Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | omap: UART: fix wakeup registers for OMAP24xx UART2Kevin Hilman2010-10-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP24xx, UART2 WKEN and WKST registers are in PM_WKEN2_CORE and PM_WKST2_CORE respecitvely. Fix the OMAP2 register init to use the correct registers on OMAP24xx. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | omap: Fix spotty MMC voltagesTony Lindgren2010-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As noted by Michał Mirosław <mirqus@gmail.com>, the voltages should cover the supported voltage range, or support only one voltage. As all these boards are using a GPIO to enable the power, chances are that only 3.3V cards are supported on these boards. Reported-by: Michał Mirosław <mirqus@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | OMAP3: DMA: Errata i541: sDMA FIFO draining does not finishPeter Ujfalusi2010-10-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the suggested workaround for OMAP3 regarding to sDMA draining issue, when the channel is disabled on the fly. This errata affects the following configuration: sDMA transfer is source synchronized Buffering is enabled SmartStandby is selected. The issue can be easily reproduced by creating overrun situation while recording audio. Either introduce load to the CPU: nice -19 arecord -D hw:0 -M -B 10000 -F 5000 -f dat > /dev/null & \ dd if=/dev/urandom of=/dev/null or suspending the arecord, and resuming it: arecord -D hw:0 -M -B 10000 -F 5000 -f dat > /dev/null CTRL+Z; fg; CTRL+Z; fg; ... In case of overrun audio stops DMA, and restarts it (without reseting the sDMA channel). When we hit this errata in stop case (sDMA drain did not complete), at the coming start the sDMA will not going to be operational (it is still draining). This leads to DMA stall condition. On OMAP3 we can recover with sDMA channel reset, it has been observed that by introducing unrelated sDMA activity might also help (reading from MMC for example). The same errata exists for OMAP2, where the suggestion is to disable the buffering to avoid this type of error. On OMAP3 the suggestion is to set sDMA to NoStandby before disabling the channel, and wait for the drain to finish, than configure sDMA to SmartStandby again. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by : Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by : Manjunath Kondaiah G <manjugk@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | omap: dma: Fix buffering disable bit setting for omap24xxJarkko Nikula2010-10-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An errata workaround for omap24xx is not setting the buffering disable bit 25 what is the purpose but channel enable bit 7 instead. Background for this fix is the DMA stalling issue with ASoC omap-mcbsp driver. Peter Ujfalusi <peter.ujfalusi@nokia.com> has found an issue in recording that the DMA stall could happen if there were a buffer overrun detected by ALSA and the DMA was stopped and restarted due that. This problem is known to occur on both OMAP2420 and OMAP3. It can recover on OMAP3 after dma free, dma request and reconfiguration cycle. However, on OMAP2420 it seems that only way to recover is a reset. Problem was not visible before the commit c12abc0. That commit changed that the McBSP transmitter/receiver is released from reset only when needed. That is, only enabled McBSP transmitter without transmission was able to prevent this DMA stall problem in receiving side and underlying problem did not show up until now. McBSP transmitter itself seems to no be reason since DMA stall does not recover by enabling the transmission after stall. Debugging showed that there were a DMA write active during DMA stop time and it never completed even when restarting the DMA. Experimenting showed that the DMA buffering disable bit could be used to avoid stalling when using source synchronized transfers. However that could have performance hit and OMAP3 TRM states that buffering disable is not allowed for destination synchronized transfers so subsequent patch will implement a method to complete DMA writes when stopping. This patch is based on assumtion that complete lock-up on OMAP2420 is different but related problem. I don't have access to OMAP2420 errata but I believe this old workaround here is put for a reason but unfortunately a wrong bit was typed and problem showed up only now. Signed-off-by: Jarkko Nikula <jhnikula@gmail.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Manjunath Kondaiah G <manjugk@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | omap: serial: Fix the boot-up crash/reboot without CONFIG_PMSantosh Shilimkar2010-10-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The omap2plus_defconfig doesn't boot up when built with CONFIG_PM disabled on the latest linux-omap master. Below are the observations 1. OMAP3 reboots in the middle of boot -------------------------------------------------- [ 0.000000] Calibrating delay loop... 494.72 BogoMIPS (lpj=1933312) [ 0.000000] pid_max: default: 32768 minimum: 301 [ 0.000000] Security Framework initialized [ 0.000000] Mount-cache hash table entries: 512 [ 0.000000] CPU: Testing write buffer coherency: ok [ 0.000000] Brought up 1 CPUs [ 0.000000] SMP: Total of 1 processors activated (494.72 BogoMIPS). [ 0.000000] regulator: core version 0.5 [ 0.000000] NET: Registered protocol family 16 U-Boot 1.1.4 (Feb 11 2009 - 16:10:23) OMAP3430-GP rev 2, CPU-OPP2 L3-165MHz TI 3430SDP 1.0 Version + mDDR (Boot NOR) DRAM: 128 MB Flash: 128 MB NAND:128 MiB -------------------------------------------------- 2. OMAP4 does a kernel PANIC ------------------------------------- [ 0.000000] Calibrating delay loop... 1195.29 BogoMIPS (lpj=4669440) [ 0.000000] pid_max: default: 32768 minimum: 301 [ 0.000000] Security Framework initialized [ 0.000000] Mount-cache hash table entries: 512 [ 0.000000] CPU: Testing write buffer coherency: ok [ 0.000000] L310 cache controller enabled [ 0.000000] l2x0: 16 ways, CACHE_ID 0x410000c2, AUX_CTRL 0x0e050000 [ 0.000000] CPU1: Booted secondary processor [ 0.000000] Brought up 2 CPUs [ 0.000000] SMP: Total of 2 processors activated (2395.78 BogoMIPS). [ 0.000000] regulator: core version 0.5 [ 0.000000] NET: Registered protocol family 16 [ 0.000000] mux: Could not set signal i2c2_scl.i2c2_scl [ 0.000000] mux: Could not set signal i2c2_sda.i2c2_sda [ 0.000000] mux: Could not set signal i2c3_scl.i2c3_scl [ 0.000000] mux: Could not set signal i2c3_sda.i2c3_sda [ 0.000000] mux: Could not set signal i2c4_scl.i2c4_scl [ 0.000000] mux: Could not set signal i2c4_sda.i2c4_sda ------------------------------------- This is happening because 'omap_serial_init()' is hanging in the boot. On OMAP3 the watchdog is generating reboot because devices_init doesn't happens where as on OMAP4 it just hangs without reboot. The uart clock is not getting enabled after omap_device_idle as part of omap_serial_init. The omap_device_idle(will disable the clock) then omap_uart_block_sleep() should enable clock back disabled during the boot up phase. But omap_uart_block_sleep() stuffed version is binded only under CONFIG_PM and other version is just empty. Hence it is not enabling clock back as expected This patch adds uart clock enable code to omap_uart_block_sleep() function built with CONFIG_PM disabled. Thanks to Charulatha and Govindraj for their help on this debug. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Charulatha V <charu@ti.com> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | OMAP3: PM: fix scratchpad memory accesses for off-modeKevin Hilman2010-10-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 914bab936fe0388a529079679e2f137aa4ff548d (OMAP: mach-omap2: Fix incorrect assignment warnings) changed a pointer from 'u32 *' to 'void *' without also fixing up the pointer arithmetic. Fix the scratchpad offsets so they are byte offsets instead of word offsets and thus work correctly with a void pointer base. Special thanks to Jean Pihet for taking the time track down this problem and propose an initial solution. Tested with off-idle and off-suspend on 36xx/Zoom3 and 34xx/omap3evm. Cc: Manjunath Kondaiah G <manjugk@ti.com> Reported-by: Jean Pihet <jean.pihet@newoldbits.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Jean Pihet <jean.pihet@newoldbits.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | Merge branch 'control_mcbsp_fix_2.6.37' of git://git.pwsan.com/linux-2.6 ↵Tony Lindgren2010-10-08
| |\ \ | | | | | | | | | | | | into omap-for-linus
| | * | OMAP: McBSP: Remove null omap44xx ops commentJarkko Nikula2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It seems these comments where accidentally added so remove them. Signed-off-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by: Paul Walmsley <paul@pwsan.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
| | * | OMAP: McBSP: Swap CLKS source definitionJarkko Nikula2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is just a readability and debugging improvement. As selection bit in DEVCONF register is cleared when using 96 MHz PRCM source and set when using external CLKS pin, change definitions to be sync with these. Signed-off-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by: Paul Walmsley <paul@pwsan.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
| | * | OMAP: McBSP: Fix CLKR and FSR signal muxingJarkko Nikula2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix bit clear. Now it clears all other bits than mask bit where it should clear only it. Signed-off-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by: Paul Walmsley <paul@pwsan.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com>
| | * | OMAP2+: clock: reduce the amount of standard debugging while disabling ↵Paul Walmsley2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | unused clocks Reduce the amount of debugging generated by default when unused clocks are being disabled by the clock code. The previous code would only generate debug-level messages, but some people who wished to run production kernels with debug-level messages enabled reported that the large number of clock disable messages were slowing boot. Now to enable clock-by-clock disable messages, DEBUG needs to be defined in mach-omap2/clock.c. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Tuukka Tikkanen <tuukka.tikkanen@nokia.com> Cc: Tim Bird <tim.bird@am.sony.com>
| | * | OMAP: control: move plat-omap/control.h to mach-omap2/control.hPaul Walmsley2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only OMAP2+ platforms have the System Control Module (SCM) IP block. In the past, we've kept the SCM header file in plat-omap. This has led to abuse - device drivers including it; includes being added that create implicit dependencies on OMAP2+ builds; etc. In response, move the SCM headers into mach-omap2/. As part of this, remove the direct SCM access from the OMAP UDC driver. It was clearly broken. The UDC code needs an indepth review for use on OMAP2+ chips. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Cory Maccarrone <darkstar6262@gmail.com> Cc: Kyungmin Park <kyungmin.park@samsung.com>
| | * | OMAP: split plat-omap/common.cPaul Walmsley2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split plat-omap/common.c into three pieces: 1. the 32KiHz sync timer and clocksource code, which now lives in plat-omap/counter_32k.c; 2. the OMAP2+ common code, which has been moved to mach-omap2/common.c; 3. and the remainder of the OMAP-wide common code, which includes the deprecated ATAGs code and a deprecated video RAM reservation function. The primary motivation for doing this is to move the OMAP2+-specific parts into an OMAP2+-specific file, so that build breakage related to the System Control Module code can be resolved. Benoît Cousson <b-cousson@ti.com> suggested a new filename and found some bugs in the counter_32k.c comments - thanks Benoît. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com>
| | * | OMAP: McBSP: implement functional clock switching via clock frameworkPaul Walmsley2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously the OMAP McBSP ASoC driver implemented CLKS switching by using omap_ctrl_{read,write}l() directly. This is against policy; the OMAP System Control Module functions are not intended to be exported to drivers. These symbols are no longer exported, so as a result, the OMAP McBSP ASoC driver does not build as a module. Resolve the CLKS clock changing portion of this problem by creating a clock parent changing function that lives in arch/arm/mach-omap2/mcbsp.c, and modify the ASoC driver to use it. Due to the unfortunate way that McBSP support is implemented in ASoC and the OMAP tree, this symbol must be exported for use by sound/soc/omap/omap-mcbsp.c. Going forward, the McBSP device driver should be moved from arch/arm/*omap* into drivers/ or sound/soc/* and the CPU DAI driver should be implemented as a platform_driver as many other ASoC CPU DAI drivers are. These two steps should resolve many of the layering problems, which will rapidly reappear during a McBSP hwmod/PM runtime conversions. Signed-off-by: Paul Walmsley <paul@pwsan.com> Acked-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
| | * | OMAP: McBSP: implement McBSP CLKR and FSR signal muxing via mach-omap2/mcbsp.cPaul Walmsley2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP ASoC McBSP code implemented CLKR and FSR signal muxing via direct System Control Module writes on OMAP2+. This required the omap_ctrl_{read,write}l() functions to be exported, which is against policy: the only code that should call those functions directly is OMAP core code, not device drivers. omap_ctrl_{read,write}*() are no longer exported, so the driver no longer builds as a module. Fix the pinmuxing part of the problem by removing calls to omap_ctrl_{read,write}l() from the OMAP ASoC McBSP code and implementing signal muxing functions in arch/arm/mach-omap2/mcbsp.c. Due to the unfortunate way that McBSP support is implemented in ASoC and the OMAP tree, these symbols must be exported for use by sound/soc/omap/omap-mcbsp.c. Going forward, the McBSP device driver should be moved from arch/arm/*omap* into drivers/ or sound/soc/*, and the CPU DAI driver should be implemented as a platform_driver as many other ASoC CPU DAI drivers are. These two steps should resolve many of the layering problems, which will rapidly reappear during a McBSP hwmod/PM runtime conversion. Signed-off-by: Paul Walmsley <paul@pwsan.com> Acked-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
| | * | OMAP3xxx: clock: add clkdev aliases for McBSP fclk source switchingPaul Walmsley2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP3 clock tree already contains the infrastructure to support clock framework-based McBSP functional clock source switching. But it did not contain the clkdev aliases for the McBSP code to refer to the parent clocks in an SoC integration-neutral way. So, add the clkdev aliases for the parent clocks. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | OMAP2430: clock: add MCBSP_CLKS node and clkdev aliasesPaul Walmsley2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the MCBSP_CLKS clock and the clksel structures needed to support clock framework-based source switching for McBSPs 1-5. Also, add clkdev aliases on the parent clocks for the McBSP source switching code, added in a subsequent patch. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | OMAP2420: clock: add MCBSP_CLKS node and clkdev aliasesPaul Walmsley2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the MCBSP_CLKS clock and the clksel structures needed to support clock framework-based source switching for McBSP 1 and 2. Also, add clkdev aliases on the parent clocks for the McBSP source switching code, added in a subsequent patch. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | OMAP2420: CTRL: fix OMAP242X_CTRL_REGADDR macroPaul Walmsley2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conform the OMAP2420_CTRL_BASE macro name to the standard of the rest of the OMAP*_CTRL_BASE macro names. This fixes a bug in the OMAP2420 SCM code that prevented OMAP242X_CTRL_REGADDR from working. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | OMAP2+: Kconfig: disallow builds for boards that don't use the ↵Paul Walmsley2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | currently-selected SoC Currently, if, for example, CONFIG_ARCH_OMAP2420 is not selected, OMAP2420 board files can still be included in the build. This results in link errors: arch/arm/mach-omap2/built-in.o: In function `omap_generic_map_io': .../arch/arm/mach-omap2/board-generic.c:51: undefined reference to `omap2_set_globals_242x' arch/arm/mach-omap2/built-in.o: In function `omap_h4_init': .../arch/arm/mach-omap2/board-h4.c:330: undefined reference to `omap2420_mux_init' arch/arm/mach-omap2/built-in.o: In function `omap_h4_map_io': .../arch/arm/mach-omap2/board-h4.c:373: undefined reference to `omap2_set_globals_242x' arch/arm/mach-omap2/built-in.o: In function `omap_apollon_init': .../arch/arm/mach-omap2/board-apollon.c:325: undefined reference to `omap2420_mux_init' arch/arm/mach-omap2/built-in.o: In function `omap_apollon_map_io': .../arch/arm/mach-omap2/board-apollon.c:353: undefined reference to `omap2_set_globals_242x' make: *** [.tmp_vmlinux1] Error 1 Fix this by making the boards depend on the Kconfig option for the specific SoC that they use. Also, while here, fix the mach-omap2/board-generic.c file to remove the dependency on OMAP2420. Charulatha Varadarajan <charu@ti.com> caught a typo - thanks Charu. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Charulatha Varadarajan <charu@ti.com>
| * | | omap4: pandaboard: enable the ehci port on pandaboardDavid Anders2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP4 PandaBoard has EHCI port1 hooked up to an external SMSC3320 transciever. GPIO 1 is used to power on the transceiver and GPIO 62 for reset on the transceiver. Signed-off-by: David Anders <x0132446@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | omap4: pandaboard: Fix the init if CONFIG_MMC_OMAP_HS is not setDavid Anders2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid possible crash if CONFIG_MMC_OMAP_HS is not set. Signed-off-by: David Anders <x0132446@ti.com> Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | omap4: pandaboard: remove unused hsmmc definitionDavid Anders2010-10-08
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | remove the second hsmmc definition as it is only used on the expansion header of the PandaBoard and can be mux for other functions. Signed-off-by: David Anders <x0132446@ti.com> Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | omap: Update omap2plus_defconfig to use ttyO instead ttySTony Lindgren2010-10-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the omap-serial the device has changed from ttyS to ttyO as the system may have both omap-serial and 8250 ports. Note that systems using omap-serial need to be updated to use ttyO[012] instead of ttyS[012] in the bootloader, CONFIG_CMDLINE, /etc/inittab, and the root file system with mknod. Also you may need to add ttyO[012] to /etc/securetty. Signed-off-by: Tony Lindgren <tony@atomide.com>