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* ARM: Ensure PTE modifications via dma_alloc_coherent are visibleRussell King2010-09-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Dave Hylands reports: | We've observed a problem with dma_alloc_writecombine when the system | is under heavy load (heavy bus traffic). We've managed to reduce the | problem to the following snippet, which is run from a kthread in a | continuous loop: | | void *virtAddr; | dma_addr_t physAddr; | unsigned int numBytes = 256; | | for (;;) { | virtAddr = dma_alloc_writecombine(NULL, | numBytes, &physAddr, GFP_KERNEL); | if (virtAddr == NULL) { | printk(KERN_ERR "Running out of memory\n"); | break; | } | | /* access DMA memory allocated */ | tmp = virtAddr; | *tmp = 0x77; | | /* free DMA memory */ | dma_free_writecombine(NULL, | numBytes, virtAddr, physAddr); | | ...sleep here... | } | | By itself, the code will run forever with no issues. However, as we | increase our bus traffic (typically using DMA) then the *tmp = 0x77 | line will eventually cause a page fault. If we add a small delay (a | few microseconds) before the *tmp = 0x77, then we don't see a page | fault, even under heavy load. A dsb() is required after modifying the PTE entries to ensure that they will always be visible. Add this dsb(). Reported-by: Dave Hylands <dhylands@gmail.com> Tested-by: Dave Hylands <dhylands@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6344/1: Mark CPU_32v6K as depended on CPU_V7Catalin Marinas2010-09-02
| | | | | | | | CPU_32v6K is selected by CPU_V7 but it only depends on CPU_V6. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branches 'master' and 'devel' into for-linusRussell King2010-08-10
|\ | | | | | | | | | | Conflicts: arch/arm/Kconfig arch/arm/mm/Kconfig
| * Merge branch 'for-rmk' of ↵Russell King2010-08-09
| |\ | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into devel-stable Conflicts: arch/arm/Kconfig
| | * ARM: S5PV310: Add new Kconfig and MakefilesChanghwan Youn2010-08-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the Kconfig and Makefile for the new S5PV310 SoC. It also updates arch/arm Kconfig, Makefile and arch/arm/mm/Kconfig to include support for the new S5PV310. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | kmap_atomic: make kunmap_atomic() harder to misuseCesar Eduardo Barros2010-08-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kunmap_atomic() is currently at level -4 on Rusty's "Hard To Misuse" list[1] ("Follow common convention and you'll get it wrong"), except in some architectures when CONFIG_DEBUG_HIGHMEM is set[2][3]. kunmap() takes a pointer to a struct page; kunmap_atomic(), however, takes takes a pointer to within the page itself. This seems to once in a while trip people up (the convention they are following is the one from kunmap()). Make it much harder to misuse, by moving it to level 9 on Rusty's list[4] ("The compiler/linker won't let you get it wrong"). This is done by refusing to build if the type of its first argument is a pointer to a struct page. The real kunmap_atomic() is renamed to kunmap_atomic_notypecheck() (which is what you would call in case for some strange reason calling it with a pointer to a struct page is not incorrect in your code). The previous version of this patch was compile tested on x86-64. [1] http://ozlabs.org/~rusty/index.cgi/tech/2008-04-01.html [2] In these cases, it is at level 5, "Do it right or it will always break at runtime." [3] At least mips and powerpc look very similar, and sparc also seems to share a common ancestor with both; there seems to be quite some degree of copy-and-paste coding here. The include/asm/highmem.h file for these three archs mention x86 CPUs at its top. [4] http://ozlabs.org/~rusty/index.cgi/tech/2008-03-30.html [5] As an aside, could someone tell me why mn10300 uses unsigned long as the first parameter of kunmap_atomic() instead of void *? Signed-off-by: Cesar Eduardo Barros <cesarb@cesarb.net> Cc: Russell King <linux@arm.linux.org.uk> (arch/arm) Cc: Ralf Baechle <ralf@linux-mips.org> (arch/mips) Cc: David Howells <dhowells@redhat.com> (arch/frv, arch/mn10300) Cc: Koichi Yasutake <yasutake.koichi@jp.panasonic.com> (arch/mn10300) Cc: Kyle McMartin <kyle@mcmartin.ca> (arch/parisc) Cc: Helge Deller <deller@gmx.de> (arch/parisc) Cc: "James E.J. Bottomley" <jejb@parisc-linux.org> (arch/parisc) Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> (arch/powerpc) Cc: Paul Mackerras <paulus@samba.org> (arch/powerpc) Cc: "David S. Miller" <davem@davemloft.net> (arch/sparc) Cc: Thomas Gleixner <tglx@linutronix.de> (arch/x86) Cc: Ingo Molnar <mingo@redhat.com> (arch/x86) Cc: "H. Peter Anvin" <hpa@zytor.com> (arch/x86) Cc: Arnd Bergmann <arnd@arndb.de> (include/asm-generic) Cc: Rusty Russell <rusty@rustcorp.com.au> ("Hard To Misuse" list) Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | [ARM] tegra: initial tegra supportErik Gilling2010-08-05
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: Fixes from Mike Rapoport - remove unused header files (mach/dma.h and mach/nand.h) - remove tegra 1 references from Makefile.boot v2: fixes from Russell King - remove mach/io.h include from mach/iomap.h - fix whitespace in Kconfig v2: from Colin Cross - fix invalid immediate in debug-macro.S v3: - allow selection of multiple boards Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com>
* | Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2010-08-03
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (291 commits) ARM: AMBA: Add pclk support to AMBA bus infrastructure ARM: 6278/2: fix regression in RealView after the introduction of pclk ARM: 6277/1: mach-shmobile: Allow users to select HZ, default to 128 ARM: 6276/1: mach-shmobile: remove duplicate NR_IRQS_LEGACY ARM: 6246/1: mmci: support larger MMCIDATALENGTH register ARM: 6245/1: mmci: enable hardware flow control on Ux500 variants ARM: 6244/1: mmci: add variant data and default MCICLOCK support ARM: 6243/1: mmci: pass power_mode to the translate_vdd callback ARM: 6274/1: add global control registers definition header file for nuc900 mx2_camera: fix type of dma buffer virtual address pointer mx2_camera: Add soc_camera support for i.MX25/i.MX27 arm/imx/gpio: add spinlock protection ARM: Add support for the LPC32XX arch ARM: LPC32XX: Arch config menu supoport and makefiles ARM: LPC32XX: Phytec 3250 platform support ARM: LPC32XX: Misc support functions ARM: LPC32XX: Serial support code ARM: LPC32XX: System suspend support ARM: LPC32XX: GPIO, timer, and IRQ drivers ARM: LPC32XX: Clock driver ...
| * Merge branch 'devel-stable' into develRussell King2010-07-31
| |\ | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/kernel/entry-armv.S arch/arm/kernel/setup.c arch/arm/mm/init.c
| | * Merge git://git.kernel.org/pub/scm/linux/kernel/git/nico/orion into devel-stableRussell King2010-07-21
| | |\
| | * \ Merge git://git.linaro.org/nico/arm_security into devel-stableRussell King2010-06-30
| | |\ \
| | | * | [ARM] add address randomization to mmap()Nicolas Pitre2010-06-14
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| | * | | arm: mm: Don't free prohibited memmap entriesMichael Bohan2010-06-15
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VM subsystem assumes that there are valid memmap entries to the bank end aligned to MAX_ORDER_NR_PAGES. It will try and read these page structs, and so we cannot free any memmap entries that it may inspect. Signed-off-by: Michael Bohan <mbohan@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
| * | | Merge branch 'misc' into develRussell King2010-07-31
| |\ \ \ | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/mm/init.c
| | * | | ARM: Factor out common code from cpu_proc_fin()Russell King2010-07-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All implementations of cpu_proc_fin() start by disabling interrupts and then flush caches. Rather than have every processors proc_fin() implementation do this, move it out into generic code - and move the cache flush past setup_mm_for_reboot() (so it can benefit from having caches still enabled.) This allows cpu_proc_fin() to become independent of the L1/L2 cache types, and eventually move the L2 cache flushing into the L2 support code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: 6268/1: ARMv6K and ARMv7 use fault statuses 3 and 6 as Access Flag faultKirill A. Shutemov2010-07-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Statuses 3 (0b00011) and 6 (0x00110) of DFSR are Access Flags faults on ARMv6K and ARMv7. Let's patch fsr_info[] at runtime if we are on ARMv7 or later. Unfortunately, we don't have runtime check for 'K' extension, so we can't check for it. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: 6256/1: Check arch version and modify fsr_info[] depends on it at runtimeKirill A. Shutemov2010-07-27
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: 6255/1: Workaround infinity loop in handling of translation faultsKirill A. Shutemov2010-07-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ARM one Linux PGD entry contains two hardware entries (see page tables layout in pgtable.h). We normally guarantee that we always fill both L1 entries. But create_mapping() doesn't follow the rule. It can create inidividual L1 entries, so here we have to call pmd_none() check in do_translation_fault() for the entry really corresponded to address, not for the first of pair. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: 6269/1: Add 'code' parameter for hook_fault_code()Kirill A. Shutemov2010-07-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add one more parameter to hook_fault_code() to be able to set 'code' field of struct fsr_info. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: 6252/1: Use SIGBUS for unaligned access instead of SIGILLKirill A. Shutemov2010-07-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | POSIX specify to use signal SIGBUS with code BUS_ADRALN for invalid address alignment. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: DMA coherent allocator: align remapped addressesRussell King2010-07-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMA coherent remap area is used to provide an uncached mapping of memory for coherency with DMA engines. Currently, we look for any free hole which our allocation will fit in with page alignment. However, this can lead to fragmentation of the area, and allows small allocations to cross L1 entry boundaries. This is undesirable as we want to move towards allocating sections of memory. Align allocations according to the size, limiting the alignment between the page and section sizes. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: use generic ioremap_page_range()Russell King2010-07-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't need our own implementation of this, use the generic library implementation instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | Merge branch 'origin' into miscRussell King2010-07-27
| | |\ \ \ | | | | |/ | | | |/|
| | * | | ARM: 6225/1: make TCM allocation static and common for all archsLinus Walleij2010-07-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This changes the TCM handling so that a fixed area is reserved at 0xfffe0000-0xfffeffff for TCM. This areas is used by XScale but XScale does not have TCM so the mechanisms are mutually exclusive. This change is needed to make TCM detection more dynamic while still being able to compile code into it, and is a must for the unified ARM goals: the current TCM allocation at different places in memory for each machine would be a nightmare if you want to compile a single image for more than one machine with TCM so it has to be nailed down in one place. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: 6224/1: print TCM whereabouts in init messageLinus Walleij2010-07-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If TCM is in use, we should display it in the virtual memory layout along with everything else. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | | ARM: 6222/1: add memory types for the TCMsLinus Walleij2010-07-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The earlier TCM memory regions were mapped as MT_MEMORY_UNCACHED which doesn't really work on platforms supporting the new v6 features like the NX bit. Add unique MT_MEMORY_[I|D]TCM types instead. Cc: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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| *-----. \ \ \ Merge branches 'at91', 'ep93xx', 'kexec', 'iop', 'lmb', 'nomadik', 'nuc', ↵Russell King2010-07-31
| |\ \ \ \ \ \ \ | | | | |_|/ / / | | | |/| | / / | | |_|_|_|/ / | |/| | | | / | | | |_|_|/ | | |/| | | 'pl', 'spear' and 'versatile' into devel
| | | | * | ARM: Remove unnecessary call to find_limits()Russell King2010-07-27
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | ARM: LMB: convert pfn_valid to use LMBRussell King2010-07-27
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | ARM: LMB: Convert arm_memory_present() to use LMB memory informationRussell King2010-07-27
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | ARM: Convert platform reservations to use LMB rather than bootmemRussell King2010-07-27
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | ARM: initial LMB trialRussell King2010-07-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | ARM: early_pte_alloc()Russell King2010-07-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a common function for allocating early PTE tables. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | ARM: early_alloc()Russell King2010-07-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a common early allocator function, in preparation for switching over to LMB. When we do, this function will need to do a little more than just allocating memory; we need it zero initialized too. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | ARM: Move platform memory reservations out of generic codeRussell King2010-07-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the platform specific bootmem memory reservations out of arch/arm/mm/mmu.c into their respective platform files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | ARM: Remove 'node' argument form arch_adjust_zones()Russell King2010-07-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we no longer support discontigmem, node is always zero, so remove this argument. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | ARM: Remove DISCONTIGMEM supportRussell King2010-07-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Everything should now be using sparsemem rather than discontigmem, so remove the code supporting discontigmem from ARM. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | ARM: Precalculate vmalloc_minRussell King2010-07-16
| | |_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than storing the minimum size of the vmalloc area, store the maximum permitted address of the vmalloc area instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | ARM: 6207/1: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6Tony Lindgren2010-07-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TLS register is only available on ARM1136 r1p0 and later. Set HWCAP_TLS flags if hardware TLS is available and test for it if CONFIG_CPU_32v6K is not set for V6. Note that we set the TLS instruction in __kuser_get_tls dynamically as suggested by Jamie Lokier <jamie@shareable.org>. Also the __switch_to code is optimized out in most cases as suggested by Nicolas Pitre <nico@fluxnic.net>. Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | ARM: Prohibit ioremap() on kernel managed RAMRussell King2010-06-21
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv6 and above have a restriction whereby aliasing virtual:physical mappings must not have differing memory type and sharability attributes. Strictly, this covers the memory type (strongly ordered, device, memory), cache attributes (uncached, write combine, write through, write back read alloc, write back write alloc) and the shared bit. However, using ioremap() and its variants on system RAM results in mappings which differ in these attributes from the main system RAM mapping. Other architectures which similar restrictions approch this problem in the same way - they do not permit ioremap on main system RAM. Make ARM behave in the same way, with a WARN_ON() such that users can be traced and an alternative approach found. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 6279/1: highmem: fix SMP preemption bug in kmap_high_l1_viptGary King2010-07-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | smp_processor_id() must not be called from a preemptible context (this is checked by CONFIG_DEBUG_PREEMPT). kmap_high_l1_vipt() was doing so. This lead to a problem where the wrong per_cpu kmap_high_l1_vipt_depth could be incremented, causing a BUG_ON(*depth <= 0); in kunmap_high_l1_vipt(). The solution is to move the call to smp_processor_id() after the call to preempt_disable(). Originally by: Andrew Howe <ahowe@nvidia.com> Signed-off-by: Gary King <gking@nvidia.com> Acked-by: Nicolas Pitre <nico.as.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 6272/1: Convert L2x0 to use the IO relaxed operationsCatalin Marinas2010-07-29
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is in preparation for a subsequent patch which adds barriers to the I/O accessors. Since the mandatory barriers may do an L2 cache sync, this patch avoids a recursive call into l2x0_cache_sync() via the write*() accessors and wmb() and a call into l2x0_cache_sync() with the l2x0_lock held. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | / ARM: 6210/1: Do not rely on reset defaults of L2X0_AUX_CTRLSascha Hauer2010-07-09
| |/ |/| | | | | | | | | | | | | | | | | On i.MX35 the L2X0_AUX_CTRL register does not have sensible reset default values. Allow them to be overwritten with the aux_val/aux_mask arguments passed to l2x0_init(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6202/1: Do not ARM_DMA_MEM_BUFFERABLE on RealView boards with L210/L220Catalin Marinas2010-07-02
| | | | | | | | | | | | | | | | | | | | | | RealView boards with certain revisions of the L210/L220 cache controller may have issues (hardware deadlock) with the mandatory barriers (DSB followed by an L2 cache sync) when ARM_DMA_MEM_BUFFERABLE is enabled. The patch disables ARM_DMA_MEM_BUFFERABLE for these boards. Tested-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6188/1: Add a config option for the ARM11MPCore DMA cache maintenance ↵Catalin Marinas2010-07-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | workaround Commit f4d6477f introduced a workaround for the lack of hardware broadcasting of the cache maintenance operations on ARM11MPCore. However, the workaround is only valid on CPUs that do not do speculative loads into the D-cache. This patch adds a Kconfig option with the corresponding help to make the above clear. When the DMA_CACHE_RWFO option is disabled, the kernel behaviour is that prior to the f4d6477f commit. This also allows ARMv6 UP processors with speculative loads to work correctly. For other processors, a different workaround may be needed. Cc: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6187/1: The v6_dma_inv_range() function must preserve data on SMPCatalin Marinas2010-07-01
| | | | | | | | | | | | | | | | | | | | | | | | | | A recent patch for DMA cache maintenance on ARM11MPCore added a write for ownership trick to the v6_dma_inv_range() function. Such operation destroys data already present in the buffer. However, this function is used with with dma_sync_single_for_device() which is supposed to preserve the existing data transfered into the buffer. This patch adds a combination of read/write for ownership to preserve the original data. Reported-by: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6186/1: Avoid the CONSISTENT_DMA_SIZE warning on noMMU buildsCatalin Marinas2010-07-01
|/ | | | | | | | This macro is not defined when !CONFIG_MMU so this patch moves the CONSISTENT_* definitions to the CONFIG_MMU section. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6164/1: Add kto and kfrom to input operands list.Khem Raj2010-06-08
| | | | | | | | | | | | | | | | | When functions incoming parameters are not in input operands list gcc 4.5 does not load the parameters into registers before calling this function but the inline assembly assumes valid addresses inside this function. This breaks the code because r0 and r1 are invalid when execution enters v4wb_copy_user_page () Also the constant needs to be used as third input operand so account for that as well. Tested on qemu arm. CC: <stable@kernel.org> Signed-off-by: Khem Raj <raj.khem@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6166/1: Proper prefetch abort handling on pre-ARMv6Anfei2010-06-08
| | | | | | | | | | | | Instruction faults on pre-ARMv6 CPUs are interpreted as a 'translation fault', but do_translation_fault doesn't handle well if user mode trying to run instruction above TASK_SIZE, and result in the infinite retry of that instruction. CC: <stable@kernel.org> Signed-off-by: Anfei Zhou <anfei.zhou@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6165/1: trap overflows on highmem pages from kmap_atomic when debuggingNicolas Pitre2010-06-08
| | | | | | | | | | | | | | | | When CONFIG_DEBUG_HIGHMEM is used, the fixmap entry used for a highmem page by kmap_atomic() is always cleared by kunmap_atomic(). This helps find bad usages such as dereferences after the unmap, or overflow into the adjacent fixmap areas. But this debugging aid is completely bypassed when a kmap for the same page already exists as the kmap is reused instead. ON VIVT systems we have no choice but to reuse that kmap due to cache coherency issues, but on non VIVT systems we should always force the fixmap usage when debugging is active. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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