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* [ARM] 2969/1: miscellaneous whitespace cleanupGeorge G. Davis2005-10-12
| | | | | | | | | | Patch from George G. Davis Fix leading, trailing and other miscellaneous whitespace issues in arch/arm/kernel/alignment.c. Signed-off-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 2959/1: Add test for invalid LDRD/STRD Rd cases in ARM alignment handlerGeorge G. Davis2005-10-10
| | | | | | | | | | | Patch from George G. Davis Add test for invalid LDRD/STRD Rd cases in ARM alignment handler and restore SWP printk KERN_ERR. Signed-off-by: Steve Longerbeam <slongerbeam@mvista.com> Signed-off-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 2954/1: Allow D and I cache and branch prediction disabling for ARMv6Catalin Marinas2005-10-05
| | | | | | | | | | Patch from Catalin Marinas There is no reason to not allow these config options. They are useful when the hardware has problems. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 2943/1: Clear the exclusive monitor in v6_early_abortCatalin Marinas2005-10-02
| | | | | | | | | | | Patch from Catalin Marinas Data abort caused by ldrex/strex can leave the exclusive monitor in an unpredictable state. It is recommended that a clrex/strex is performed to clear this state. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 2940/1: Fix BTB entry flush in arch/arm/mm/cache-v6.SGen FUKATSU2005-09-30
| | | | | | | | | | | | Patch from Gen FUKATSU Invalidate BTB entry instruction flushes two instruction at a time. Therefore this instruction should be done four times after invalidate instruction cache line. Signed-off-by: Gen Fukatsu Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 2939/1: Fix compilation error in arch/arm/mm/flush.cCatalin Marinas2005-09-30
| | | | | | | | | | | Patch from Catalin Marinas When CONFIG_CPU_CACHE_VIPT is defined, the flush_pfn_alias() function is implicitely declared and it later conflicts with its actual definition. This patch moves the function definition to the beginning of the file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Prevent deadlock in page fault handlerRussell King2005-09-20
| | | | | | | | As per x86, we may deadlock while trying to get the mmap semaphore. Implement the same fix, which allows (eg) recursive faults to cause an oops instead of deadlocking. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 2926/1: .proc.info - postfix section with .init for `make buildcheck`Ben Dooks2005-09-20
| | | | | | | | | | | Patch from Ben Dooks The `make buildcheck` is erroneously reporting that the .proc.info list is referencing items in the .init section as it is not itself postfixed with .init Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge master.kernel.org:/pub/scm/linux/kernel/git/sam/kbuild Linus Torvalds2005-09-09
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| * kbuild: arm - use generic asm-offsets.h supportSam Ravnborg2005-09-09
| | | | | | | | | | | | | | Delete obsoleted stuff from arch Makefile and rename constants.h to asm-offsets.h Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
* | [ARM] Fix ARMv6 VIPT cache >= 32KRussell King2005-09-08
|/ | | | | | | This adds the necessary changes to ensure that we flush the caches correctly with aliasing VIPT caches. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 2875/1: Data Abort fixesTimothy Baldwin2005-09-04
| | | | | | | | | Patch from Timothy Baldwin All data aborts are treated as read accesses. The existing code updates the wrong bit of r1, also the comments are wrong in that the sense of the L bit is inverted. Signed-off-by: Timothy E. Baldwin <T.E.Baldwin99@members.leeds.ac.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix ARMv6 page table bitsRussell King2005-09-01
| | | | | | | | We weren't explicitly setting the page table bits we desired in user_prot in the protection table, which resulted in the user mappings for v6 CPUs being marked global. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Simplify setup_mm_for_reboot()Russell King2005-09-01
| | | | | | | | No point checking what CPU architecture level we have each time within the loop, so precompute the base PMD flags outside the loop. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Convert open-coded __pmd_populate to use inline functionRussell King2005-09-01
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 2867/2: unaligned ldrd/strd fixupsSteve Longerbeam2005-08-31
| | | | | | | | | | | | | | | Patch from Steve Longerbeam Adds an implementation of unaligned LDRD and STRD fixups. Also fixes a bug where do_alignment() would misinterpret and fixup an unaligned LDRD/STRD as LDRH/STRH, causing memory corruption. This is the same as Patch #2867/1, but with minor whitespace and comments changes, plus a check for arch-level >= v5TE before printing ai_dword count in proc_alignment_read(). Signed-off-by: Steve Longerbeam <stevel@mwwireless.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 2853/1: Make alloc_init_supersection() work with 36-bit mappingsDeepak Saxena2005-08-29
| | | | | | | | | | | | | | | | | | | Patch from Deepak Saxena Working on adding support for 36-bit static mappings for ARMv6 and Intel's XSC3 core and noticed that alloc_init_supersection currently increments the phys addr by 1MB on each of the 16 iterations and then forces alignment to supersection size (16MB). This is really uneeded b/c we have already forced the phys address to be 16MB aligned in create_mapping(). Furthermore, this breaks 36-bit addressing b/c bits [23:20] of the PMD contain bits [35:32] of the physical address and the masking causes us to loose those bits thus ending up with an incorrect virt -> phys translation. The other option is to have an alloc_init_supersection36. Tested on Intel IXP2350 CPU with 36-bit static I/O mappings. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 2852/1: Correct the mistake in arch/arm/mm/Kconfig fileSean Lee2005-08-17
| | | | | | | | | | | | Patch from Sean Lee In the arch/arm/mm/Kconfig file, the CPU_DCACHE_WRITETHROUGH option is depend on the CPU_DISABLE_DCACHE, but the "Disable D-Cache" option is configured as CPU_DCACHE_DISABLE. The CPU_DISABLE_DCACHE should be CPU_DCACHE_DISABLE Signed-off-by: Sean Lee <beginner2arm@eyou.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Remove extraneous whitespace introduced in previous ARMv6 patchRussell King2005-08-15
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Control v6 'global' bit via Linux PTE entriesRussell King2005-08-10
| | | | | | | | | | | | Unfortunately, we can't use the "user" bit in the page tables to control whether a page table entry is "global" or "asid" specific, since the vector page is mapped as "user" accessible but is not process specific. Therefore, give direct control of the ARMv6 "nG" (not global) bit to the mm layers. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Use #defined constants for manipulating v6 hardware PTE bitsRussell King2005-08-10
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Fix ARM fault handler for get_user_pages() fixes.Russell King2005-08-04
| | | | | | | | The ARM fault handler is optimised to make the fast path, err, fast. The renumbering of the VM_FAULT_* codes broke this because numbers were used instead of the definitions. Fix this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2839/1: Remove XScale cache and TLB locking codeDeepak Saxena2005-08-03
| | | | | | | | | | | Patch from Deepak Saxena The XScale locking code is not something that has been validated on 2.6 and needs to be replaced with a more generic API to use with other ARMs that support locking features. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM SMP: Mark device mappings as "device" in ARMv6 parlanceRussell King2005-07-26
| | | | | | | ARMv6 introduces memory types into the page tables. Mark devices mappings with the "shared device" memory type. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2798/1: OMAP update 2/11: Change ARM Kconfig to support omap1 ↵Tony Lindgren2005-07-10
| | | | | | | | | | | | | | | | | and omap2 Patch from Tony Lindgren This patch by Paul Mundt and other OMAP developers modifies ARM specific Kconfig to allow sharing code between OMAP1 and OMAP2 architectures. In order to share code between OMAP1 and OMAP2, all OMAP1 specific code is moved into mach-omap1 directory in the following patch. A new mach-omap2 directory will be added later on. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2796/1: Fix ARMv5[TEJ] check in MMU initalizationDeepak Saxena2005-07-10
| | | | | | | | | | | Patch from Deepak Saxena The code in mm-armv.c checks for the condition (cpu_architecture()<= ARMv5) in a few places but should be checking for ARMv5TEJ as the MMU is shared across all v5 variations. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2789/1: Enable access to both CP10 and CP11 on ARMv6Catalin Marinas2005-07-06
| | | | | | | | | | | Patch from Catalin Marinas The VFP instructions trigger undefined exceptions because the access to CP11 is disabled (only CP10 is currently enabled by the kernel). The patch fixes this problem. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2784/1: Fix the block cache flush operation rangeCatalin Marinas2005-07-03
| | | | | | | | | | | | | Patch from Catalin Marinas The range for the ARMv6 block cache operations is inclusive but the kernel doesn't re-calculate the end address, causing a page fault when used (this only happens with support for cache aliasing, otherwise the blk_flush_kern_dcache_page() is not called). This patch subtracts L1_CACHE_BYTES from the end address. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2779/1: Fix the V bit setting for the ARM1020x CPUsCatalin Marinas2005-06-30
| | | | | | | | | | | Patch from Catalin Marinas This patch fixes the V bit setting for the ARM1020x processors. At reset, this bit is automatically set to the value of the HIVECSINIT input signal which just happened to be 1 but it is not mandatory. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2777/1: Fix broken comment arch/arm/mm/proc-arm1020.SCatalin Marinas2005-06-30
| | | | | | | | | | Patch from Catalin Marinas This patch fixes a broken comment in the proc-arm1020.S file which prevents the file compilation Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Don't try to send a signal to pid0Russell King2005-06-30
| | | | | | | | | If we receive an unrecognised abort during boot, don't try to send a signal to pid0, but instead report the current state. This leads to less confusing debug reports. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM SMP: Use local_flush_tlb* where we really want to be localRussell King2005-06-28
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Move memmap freeing into init.cRussell King2005-06-27
| | | | | | | It doesn't make sense for this to be in mm-armv.c now that 26-bit ARM support is no longer integrated into arch/arm. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Move PGD kernel page table initialisationRussell King2005-06-27
| | | | | | | | It doesn't make sense to have the PGD kernel pointers initialisation separate from the PGD user pointers, especially when we clean the data cache over the whole range. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2698/1: Enable kernel r/w access to user pages on ARMv6Catalin Marinas2005-06-24
| | | | | | | | | | | | Patch from Catalin Marinas cpu_v6_set_pte() sets the kernel access rights to r/o for user pages (L_PTE_USER) when neither L_PTE_WRITE nor L_PTE_DIRTY are set. This causes a kernel data abort when writing the TLS value in the 0xffff0000 page. This patch enables the kernel r/w access. Signed-off-by: Catalin Marinas Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Remove explicit page-alignments in memory initRussell King2005-06-22
| | | | | | | | Since meminfo.bank[] array contains page-aligned start/size, we no longer need to explicitly round up/down the addresses when converting to PFNs. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] Avoiding mmap fragmentationWolfgang Wander2005-06-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ingo recently introduced a great speedup for allocating new mmaps using the free_area_cache pointer which boosts the specweb SSL benchmark by 4-5% and causes huge performance increases in thread creation. The downside of this patch is that it does lead to fragmentation in the mmap-ed areas (visible via /proc/self/maps), such that some applications that work fine under 2.4 kernels quickly run out of memory on any 2.6 kernel. The problem is twofold: 1) the free_area_cache is used to continue a search for memory where the last search ended. Before the change new areas were always searched from the base address on. So now new small areas are cluttering holes of all sizes throughout the whole mmap-able region whereas before small holes tended to close holes near the base leaving holes far from the base large and available for larger requests. 2) the free_area_cache also is set to the location of the last munmap-ed area so in scenarios where we allocate e.g. five regions of 1K each, then free regions 4 2 3 in this order the next request for 1K will be placed in the position of the old region 3, whereas before we appended it to the still active region 1, placing it at the location of the old region 2. Before we had 1 free region of 2K, now we only get two free regions of 1K -> fragmentation. The patch addresses thes issues by introducing yet another cache descriptor cached_hole_size that contains the largest known hole size below the current free_area_cache. If a new request comes in the size is compared against the cached_hole_size and if the request can be filled with a hole below free_area_cache the search is started from the base instead. The results look promising: Whereas 2.6.12-rc4 fragments quickly and my (earlier posted) leakme.c test program terminates after 50000+ iterations with 96 distinct and fragmented maps in /proc/self/maps it performs nicely (as expected) with thread creation, Ingo's test_str02 with 20000 threads requires 0.7s system time. Taking out Ingo's patch (un-patch available per request) by basically deleting all mentions of free_area_cache from the kernel and starting the search for new memory always at the respective bases we observe: leakme terminates successfully with 11 distinctive hardly fragmented areas in /proc/self/maps but thread creating is gringdingly slow: 30+s(!) system time for Ingo's test_str02 with 20000 threads. Now - drumroll ;-) the appended patch works fine with leakme: it ends with only 7 distinct areas in /proc/self/maps and also thread creation seems sufficiently fast with 0.71s for 20000 threads. Signed-off-by: Wolfgang Wander <wwc@rentec.com> Credit-to: "Richard Purdie" <rpurdie@rpsys.net> Signed-off-by: Ken Chen <kenneth.w.chen@intel.com> Acked-by: Ingo Molnar <mingo@elte.hu> (partly) Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] ARM: 2686/2: AAEC-2000 Core supportBellido Nicolas2005-06-20
| | | | | | | | | | | | | Patch from Bellido Nicolas Core support for AAEC-2000 based platforms. This is an updated version of the previous patch, and takes into account Russell's comments. AAED-2000 default configuration will follow as soon as some problems with the bootloader are sorted out... Signed-off-by: Nicolas Bellido Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Add iomap support for ARMRussell King2005-06-20
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Add common CACHE_COLOUR macroRussell King2005-06-20
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Fix delayed dcache flush for ARMv6 non-aliasing cachesRussell King2005-06-20
| | | | | | | | flush_dcache_page() did nothing for these caches, but since they suffer from I/D cache coherency issues, we need to ensure that data is written back to RAM. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Remove zero-byte sized fileRussell King2005-06-09
| | | | | | | Remove the remaining zero byte file left over from the Xscale fixes. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
* [PATCH] ARM: 2664/2: add support for atomic ops on pre-ARMv6 SMP systemsNicolas Pitre2005-06-08
| | | | | | | | | | Patch from Nicolas Pitre Not that there might be many of them on the planet, but at least RMK apparently has one. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Fix Xscale copy_page implementationRussell King2005-06-08
| | | | | | | | | | The ARM copypage changes in 2.6.12-rc4-git1 removed the preempt locking from the copypage functions which broke the XScale implementation. This patch fixes the locking on XScale and removes the now unneeded minicache code. Signed-off-by: Russell King <rmk@arm.linux.org.uk> Checked-by: Richard Purdie
* [PATCH] ARM: Fix build errorRussell King2005-05-16
| | | | | | Mainline kernels don't have VECTORS_HIGH nor COPYPAGE_MINICACHE yet. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
* [PATCH] ARM: 2680/1: refine TLS reg availability some more againNicolas Pitre2005-05-12
| | | | | | | | | Patch from Nicolas Pitre Not all ARMv6 processors implement the TLS register. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2663/2: I can't typeNicolas Pitre2005-05-10
| | | | | | | Patch from Nicolas Pitre Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Add V6 aliasing cache flushRussell King2005-05-10
| | | | | | | Add cache flushing support for aliased V6 caches to flush_dcache_page. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
* [PATCH] ARM: Use top_pmd for V6 copy/clear user_pageRussell King2005-05-10
| | | | | | Remove needless page table walking for v6 page operations. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
* [PATCH] ARM: Move copy/clear user_page locking into implementationRussell King2005-05-10
| | | | | | | | | Move the locking for copy_user_page() and clear_user_page() into the implementations which require locking. For simple memcpy/ memset based implementations, the locking is extra overhead which is not necessary, and prevents preemption occuring. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
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