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* ARM: fix PAGE_KERNELRussell King2009-12-24
| | | | | | | | PAGE_KERNEL should not be executable; any area marked executable can be prefetched into the instruction cache. We don't want vmalloc areas to be read in this way. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Fix wrong shared bit for CPU write buffer bug testRussell King2009-12-23
| | | | | | | | It is unpredictable to have the same memory mapped using different shared bit settings for ARMv6 and ARMv7 CPUs. Fix this for the CPU write buffer bug test. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Kill CONFIG_CPU_32Russell King2009-12-18
| | | | | | | | 26-bit ARM support was removed a long time ago, and this symbol has been defined to be 'y' ever since. As it's never disabled anymore, we can kill it without any side effects. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5853/1: ARM: Fix build break on ARM v6 and v7Anand Gadiyar2009-12-18
| | | | | | | | | | | | | | | | | | Commit 2c9b9c849 added an argument to __cpuc_flush_dcache_page and renamed it. Update a caller of the old function to fix this build error: CC arch/arm/mm/copypage-v6.o arch/arm/mm/copypage-v6.c: In function 'v6_copy_user_highpage_nonaliasing': arch/arm/mm/copypage-v6.c:51: error: implicit declaration of function '__cpuc_flush_dcache_page' make[1]: *** [arch/arm/mm/copypage-v6.o] Error 1 make: *** [arch/arm/mm] Error 2 Reported-by: Jinsung Yang <jsgood.yang@samsung.com> Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'cache' (early part)Russell King2009-12-17
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| * Merge branch 'pending-l2x0' into cacheRussell King2009-12-14
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| | * ARM: cache-l2x0: make better use of background cache handlingRussell King2009-12-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no point having the hardware support background operations if we issue a cache operation, and then wait for it to complete before calculating the address of the next operation. We gain no advantage in the cache controller stalling the bus until completion. What we should be doing is using the 'wait' time productively by calculating the address of the next operation, and only then waiting for the previous operation to complete. This means that cache operations can occur in parallel with the CPU calculating the next address. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
| | * ARM: cache-l2x0: avoid taking spinlock for every iterationRussell King2009-12-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | Taking the spinlock for every iteration is very expensive; instead, batch iterations up into 4K blocks, releasing and reacquiring the spinlock between each block. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
| * | ARM: add size argument to __cpuc_flush_dcache_pageRussell King2009-12-14
| | | | | | | | | | | | | | | | | | | | | ... and rename the function since it no longer operates on just pages. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 5848/1: kill flush_ioremap_region()Nicolas Pitre2009-12-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is not enough users to warrant its existence, and it is actually an obstacle to progress with the new DMA API which cannot cover this case properly. To keep backward compatibility, let's perform the necessary custom cache maintenance locally in the only driver affected. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | Merge branch 'for-rmk' of git://git.marvell.com/orionRussell King2009-12-16
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| * | | ARM: dove: fix the mm mmu flags of the pj4 procinfoSaeed Bishara2009-12-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ... to be the same as proc-v6 Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* | | | fix broken aliasing checks for MAP_FIXED on sparc32, mips, arm and shAl Viro2009-12-11
| |/ / |/| | | | | | | | | | | | | | | | | | | | We want addr - (pgoff << PAGE_SHIFT) consistently coloured... Acked-by: Paul Mundt <lethal@linux-sh.org> Acked-by: Hugh Dickins <hugh.dickins@tiscali.co.uk> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* | | Merge branch 'devel-stable' into develRussell King2009-12-05
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| * \ \ Merge branch 'devel' of ↵Russell King2009-12-04
| |\ \ \ | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel-stable
| | * | | [ARM] pxa/treo: add Palm Centro 685 supportTomáš Čech2009-11-30
| | | |/ | | |/| | | | | | | | | | | | | Signed-off-by: Tomáš Čech <sleep_walker@suse.cz> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * | | Merge branch 'for-rmk' of git://git.marvell.com/orion into devel-stableRussell King2009-12-01
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| | * | ARM: Add Tauros2 L2 cache controller supportLennert Buytenhek2009-11-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
| | * | ARM: add base support for Marvell Dove SoCSaeed Bishara2009-11-27
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
| * | Merge branch 'next' of ↵Russell King2009-11-20
| |\ \ | | |/ | |/| | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/xscaleiop into devel-stable
| | * iop: implement sched_clock()Mikael Pettersson2009-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a better sched_clock() to the IOP platform, implemented using its new clocksource support. Tested on n2100, compile-tested for all plat-iop machines. [dan.j.williams@intel.com: allow early cp6 access] Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | | Merge branch 'pending-dma-coherent' into develRussell King2009-12-04
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| * | | ARM: dma-mapping: switch ARMv7 DMA mappings to retain 'memory' attributeRussell King2009-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ARMv7, it is invalid to map the same physical address multiple times with different memory types. Since system RAM is already mapped as 'memory', subsequent remapping of it must retain this attribute. However, DMA memory maps it as "strongly ordered". Fix this by introducing 'pgprot_dmacoherent()' which provides the necessary page table bits for DMA mappings. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
| * | | ARM: dma-mapping: get rid of setting/clearing the reserved page bitRussell King2009-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's unnecessary; x86 doesn't do it, and ALSA doesn't require it anymore. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
| * | | ARM: dma-mapping: Factor out noMMU dma buffer allocation codeRussell King2009-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This entirely separates the DMA coherent buffer remapping code from the allocation code, and gets rid of the duplicate copy in the !MMU section. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
| * | | ARM: dma-mapping: clean up coherent arch dma allocationRussell King2009-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IXP23xx added support for dma_alloc_coherent() for DMA arches with an exception in dma_alloc_coherent(). This is a subset of what goes on in __dma_alloc(), and there is no reason why dma_alloc_writecombine() should not be given the same treatment (except, maybe, that IXP23xx doesn't use it.) We can better deal with this by moving the arch_is_coherent() test inside __dma_alloc() and killing the code duplication. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
| * | | ARM: dma-mapping: move consistent_init into CONFIG_MMU sectionRussell King2009-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No point wrapping the contents of this function with #ifdef CONFIG_MMU when we can place it and the core_initcall() entirely within the existing conditional block. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
| * | | ARM: dma-mapping: factor dma_free_coherent() common codeRussell King2009-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We effectively have three implementations of dma_free_coherent() mixed up in the code; the incoherent MMU, coherent MMU and noMMU versions. The coherent MMU and noMMU versions are actually functionally identical. The incoherent MMU version is almost the same, but with the additional step of unmapping the secondary mapping. Separate out this additional step into __dma_free_remap() and simplify the resulting dma_free_coherent() code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
| * | | ARM: dma-mapping: fix nommu dma_alloc_coherent()Russell King2009-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The nommu version of dma_alloc_coherent was using kmalloc/kfree to manage the memory. dma_alloc_coherent() is expected to work with a granularity of a page, so this is wrong. Fix it by using the helper functions now provided. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
| * | | ARM: dma-mapping: fix coherent arch dma_alloc_coherent()Russell King2009-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The coherent architecture dma_alloc_coherent was using kmalloc/kfree to manage the memory. dma_alloc_coherent() is expected to work with a granularity of a page, so this is wrong. Fix it by using the helper functions now provided. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
| * | | ARM: dma-mapping: functions to allocate/free a coherent bufferRussell King2009-11-24
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
| * | | ARM: dma-mapping: split out vmregion code from dma coherent mapping codeRussell King2009-11-24
| |/ / | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
* | | Merge branch 'pending-misc' (early part) into develRussell King2009-12-04
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| * | | ARM: I-cache: flush executable mappings in flush_cache_range()Russell King2009-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Dirk Behme reported instability on ARM11 SMP (VIPT non-aliasing cache) caused by the dynamic linker changing protection on text pages to write GOT entries. The problem is due to an interaction between the write faulting code providing new anonymous pages which are incoherent with the I-cache due to write buffering, and the I-cache not having been invalidated. a4db94d plugs the hole with the data cache coherency. This patch provides the other half of the fix by flushing the I-cache in flush_cache_range() for VM_EXEC VMAs (which is what we have when the region is being made executable again.) This ensures that the I-cache will be up to date with the newly COW'd pages. Note: if users are writing instructions, then they still need to use the ARM sys_cacheflush API to ensure that the caches are correctly synchronized. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: I-cache: avoid flushing in flush_cache_mm()Russell King2009-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flush_cache_mm() is called in two cases: 1. when a process exits, just before the page tables are torn down. We can allow the stale lines to evict themselves over time without causing any harm. 2. when a process forks, and we've allocated a new ASID. The instruction cache issues are dealt with as pages are brought into the new process address space. Flushing the I-cache here is therefore unnecessary. However, we must keep the VIPT aliasing D-cache flush to ensure that any dirty cache lines are not written back after the pages have been reallocated for some other use - which would result in corruption. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: I-cache: Add invalidation for VIVT ASID tagged cachesRussell King2009-12-04
| | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: 5794/1: Flush the D-cache during copy_user_highpage()Catalin Marinas2009-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The I and D caches for copy-on-write pages on processors with write-allocate caches become incoherent causing problems on application relying on CoW for text pages (dynamic linker relocating symbols in a text page). This patch flushes the D-cache for such pages. Cc: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: Remove __flush_icache_all() from __flush_dcache_page()Russell King2009-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both call sites for __flush_dcache_page() end up calling __flush_icache_all() themselves, so having __flush_dcache_page() do this as well is wasteful. Remove the duplicated icache flushing. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: Move __flush_icache_all() out of flush_pfn_alias()Russell King2009-12-04
| | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: Reduce __flush_dcache_page() visibilityRussell King2009-12-04
| | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: ZERO_PAGE: Avoid flush_dcache_page() for zero pageRussell King2009-12-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The zero page is read-only, and has its cache state cleared during boot. No further maintanence for this page is required. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: Avoid evaluating page_address() multiple timesRussell King2009-12-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | page_address() is a function call rather than a macro, and so: if (page_address(page)) do_something(page_address(page)); results in two calls to this function. This is unnecessary; remove the duplication. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: Avoid duplicated implementation for VIVT cache flushingRussell King2009-12-01
| |/ / | | | | | | | | | | | | | | | | | | | | | We had two copies of the wrapper code for VIVT cache flushing - one in asm/cacheflush.h and one in arch/arm/mm/flush.c. Reduce this down to one common copy. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARMv7: Check whether the SMP/nAMP mode was already enabledTony Thompson2009-11-04
| | | | | | | | | | | | | | | | | | | | | | | | If running in non-secure mode, enabling this register will fault. Signed-off-by: Tony Thompson <Anthony.Thompson@arm.com> Acked-by: Srinidhi Kasagar <srinidhikasagar@gmail.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * | ARM: ensure initial page tables are setup for SMP systemsRussell King2009-11-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mapping the same memory using two different attributes (memory type, shareability, cacheability) is unpredictable. During boot, we encounter a situation when we're updating the kernel's page tables which can lead to dirty cache lines existing in the cache which are subsequently missed. This causes stack corruption, and therefore a crash. Therefore, ensure that the shared and cacheability settings matches the configuration that will be used later; this together with the restriction in early_cachepolicy() ensures that we won't create a mismatch during boot. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: Fix errata 411920 workaroundsRussell King2009-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Errata 411920 indicates that any "invalidate entire instruction cache" operation can fail if the right conditions are present. This is not limited just to those operations in flush.c, but elsewhere. Place the workaround in the already existing __flush_icache_all() function instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: Fix sparsemem with SPARSEMEM_EXTREME enabledRussell King2009-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When SPARSEMEM_EXTREME is enabled, memory_present() wants to use bootmem to allocate data structures. However, we call memory_present() after declaring memory to bootmem, but before we've reserved areas. This leads to sparsemem data structures being overwritten later in the kernel's initialization (when slab initializes.) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: Use GFP_DMA only for masks _less_ than 32-bitRussell King2009-10-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | We were using GFP_DMA for masks other than 0xffffffff, which is wrong when some masks are initialized to 0xffffffffffffffff. This caused such masks to obtain memory from the precious DMA pool. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 5769/1: CPU_ARM920T: remove dead Maverick EP9312 URLHartley Sweeten2009-10-21
| |/ | | | | | | | | | | | | | | | | Remove the URL listed for Maverick EP9312 since it is not available and modify the help text appropriately. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Ryan Mallon <ryan@bluewatersys.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 5845/1: l2x0: check whether l2x0 already enabledSrinidhi Kasagar2009-12-03
| | | | | | | | | | | | | | | | | | | | | | If running in non-secure mode accessing some registers of l2x0 will fault. So check if l2x0 is already enabled, if so do not access those secure registers. Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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