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* [ARM] iop: iop3xx needs registers mapped uncached+unbufferedRussell King2008-11-09
| | | | | | | | | | | | | | | | | | | | | Mikael Pettersson reported: The 2.6.28-rc kernels fail to detect PCI device 0000:00:01.0 (the first ethernet port) on my Thecus n2100 XScale box. There is however still a strange "ghost" device that gets partially detected in 2.6.28-rc2 vanilla. The IOP321 manual says: The user designates the memory region containing the OCCDR as non-cacheable and non-bufferable from the IntelR XScaleTM core. This guarantees that all load/stores to the OCCDR are only of DWORD quantities. Ensure that the OCCDR is so mapped. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 5329/1: Feroceon: fix feroceon_l2_inv_rangeNicolas Pitre2008-11-08
| | | | | | | | | | Same fix as commit c7cf72dcadb: when 'start' and 'end' are less than a cacheline apart and 'start' is unaligned we are done after cleaning and invalidating the first cacheline. Cc: <stable@kernel.org> Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'fixes' of ↵Russell King2008-11-06
|\ | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/xscaleiop
| * [ARM] xsc3: fix xsc3_l2_inv_rangeDan Williams2008-11-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When 'start' and 'end' are less than a cacheline apart and 'start' is unaligned we are done after cleaning and invalidating the first cacheline. So check for (start < end) which will not walk off into invalid address ranges when (start > end). This issue was caught by drivers/dma/dmatest. 2.6.27 is susceptible. Cc: <stable@kernel.org> Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: Lothar WaÃ<9f>mann <LW@KARO-electronics.de> Cc: Lennert Buytenhek <buytenh@marvell.com> Cc: Eric Miao <eric.miao@marvell.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | [ARM] mm: fix page table initializationRussell King2008-11-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As a result of the ptebits changes, we ended up marking device mappings as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with serial ports and the like. While reviewing the section mapping table entries, other errors in the memory type settings for devices were detected and confirmed to prevent Xscale3 platforms booting. Tested on: OMAP34xx (ARMv7), OMAP24xx (ARMv6), OMAP16xx (ARM926T, ARMv5), PXA311 (Xscale3), PXA272 (Xscale), PXA255 (Xscale), IXP42x (Xscale), S3C2410 (ARM920T, ARMv4T), ARM720T (ARMv4T) StrongARM-110 (ARMv4) Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Mike Rapoport <mike@compulab.co.il> Tested-by: Ben Dooks <ben-linux@fluff.org> Tested-by: Anders Grafström <grfstrm@users.sourceforge.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] fix naming of MODULE_START / MODULE_ENDRussell King2008-11-06
|/ | | | | | | | | | | | | As of 73bdf0a60e607f4b8ecc5aec597105976565a84f, the kernel needs to know where modules are located in the virtual address space. On ARM, we located this region between MODULE_START and MODULE_END. Unfortunately, everyone else calls it MODULES_VADDR and MODULES_END. Update ARM to use the same naming, so is_vmalloc_or_module_addr() can work properly. Also update the comment on mm/vmalloc.c to reflect that ARM also places modules in a separate region from the vmalloc space. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] xsc3: revert writethrough memory-type encoding changeDan Williams2008-10-24
| | | | | | | | | | Commit 40df2d1d "[ARM] Update Xscale and Xscale3 PTE mappings" was fingered by git-bisect for a boot failure on iop13xx. The change made L_PTE_MT_WRITETHROUGH mappings L2-uncacheable. Russell points out that this mapping is used for the vector page. Given the regression, and the fact this page is used often, restore the old behaviour. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* [ARM] 5318/1: Swap the PRRR and NMRR values in proc-v7.SCatalin Marinas2008-10-22
| | | | | | | | A typo caused these values to be swapped leading to incorrect memory type attributes. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'for-rmk' of git://git.android.com/kernel into develRussell King2008-10-22
|\
| * [ARM] msm: rename ARCH_MSM7X00A to ARCH_MSMBrian Swetland2008-10-22
| | | | | | | | | | | | | | | | | | | | | | The MSM architecture covers a wider family of chips than just the MSM7X00A. Move to a more generic name, in perparation for supporting the specific SoC variants as sub-architectures (ARCH_MSM7X01A, ARCH_MSM722X, etc). This gives us ARCH_MSM for the (many) common peripherals. This also removes the unused/obsolete config item MSM7X00A_IDLE. Signed-off-by: Brian Swetland <swetland@google.com>
* | [ARM] 5310/1: Fix cache flush functions for ARMv4Anders Grafström2008-10-17
|/ | | | | | | | | | ARMv4 (ARM720T) cache flush functions are broken in 2.6.19+ kernels. The issue was introduced by commit f12d0d7c7786af39435ef6ae9defe47fb58f6091 This patch corrects the CPU_CP15 ifdef statements so that they actually do something. Signed-off-by: Anders Grafström <grfstrm@users.sourceforge.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'omap-all' into develRussell King2008-10-14
|\ | | | | | | | | | | | | Conflicts: arch/arm/mach-omap2/gpmc.c arch/arm/mach-omap2/irq.c
| * ARM: OMAP3: Add minimal Beagle board supportSyed Mohammed, Khasim2008-10-09
| | | | | | | | | | | | | | | | | | | | Add minimal Beagle board support. Based on earlier patches by Syed Mohammed Khasim with some fixes from linux-omap tree. Signed-off-by: Syed Mohammed Khasim <khasim@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | Merge branch 'for-rmk' of git://git.marvell.com/orionRussell King2008-10-09
|\ \ | | | | | | | | | Merge branch 'orion-devel' into devel
| * | [ARM] Feroceon: small cleanups to L2 cache codeNicolas Pitre2008-09-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Make sure that coprocessor instructions for range ops are contiguous and not reordered. - s/invalidate_and_disable_dcache/flush_and_disable_dcache/ - Don't re-enable I/D caches if they were not enabled initially. - Change some masks to shifts for better generated code. Signed-off-by: Nicolas Pitre <nico@marvell.com> Acked-by: Lennert Buytenhek <buytenh@marvell.com>
| * | [ARM] Kirkwood: add support for L2 cache WB/WT selectionRonen Shitrit2008-09-25
| |/ | | | | | | | | | | | | | | Feroceon L2 cache can work in eighther write through or write back mode on Kirkwood. Add the option to configure this mode according to Kconfig. Signed-off-by: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* | Merge branch 'ptebits' into develRussell King2008-10-09
|\ \ | | | | | | | | | | | | | | | Conflicts: arch/arm/Kconfig
| * | [ARM] Don't include asm/elf.h in asm codeRussell King2008-10-01
| | | | | | | | | | | | | | | | | | asm code really wants asm/hwcap.h, so include that instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] Remove MT_DEVICE_IXP2000 and associated definitionsRussell King2008-10-01
| | | | | | | | | | | | | | | | | | | | | | | | As of the previous commit, MT_DEVICE_IXP2000 encodes to the same PTE bit encoding as MT_DEVICE, so it's now redundant. Convert MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] Update Xscale and Xscale3 PTE mappingsRussell King2008-10-01
| | | | | | | | | | | | | | | | | | | | | Use 'shared device' mappings for devices, and use the standard bit combinations for Xscale3. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] remove 'prot_pte_ext' from memory type tableRussell King2008-10-01
| | | | | | | | | | | | | | | | | | | | | This member is now redundant; the memory type is encoded in the Linux PTE bits. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] Convert ARMv7 to use TEX remappingRussell King2008-10-01
| | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] Convert ARMv6 and ARMv7 to use new memory typesRussell King2008-10-01
| | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] Convert Xscale and Xscale3 to use new memory typesRussell King2008-10-01
| | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] Introduce new PTE memory type bitsRussell King2008-10-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide L_PTE_MT_xxx definitions to describe the memory types that we use in Linux/ARM. These definitions are carefully picked such that: 1. their LSBs match what is required for pre-ARMv6 CPUs. 2. they all have a unique encoding, including after modification by build_mem_type_table() (the result being that some have more than one combination.) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] Convert set_pte_ext implementions to macrosRussell King2008-10-01
| | | | | | | | | | | | | | | | | | | | | There are actually only four separate implementations of set_pte_ext. Use assembler macros to insert code for these into the proc-*.S files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] 5241/1: provide ioremap_wc()Lennert Buytenhek2008-09-06
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides an ARM implementation of ioremap_wc(). We use different page table attributes depending on which CPU we are running on: - Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four possible mapping types (CB=00/01/10/11). We can't use any of the cached memory types (CB=10/11), since that breaks coherency with peripheral devices. Both CB=00 and CB=01 are suitable for _wc, and CB=01 (Uncached/Buffered) allows the hardware more freedom than CB=00, so we'll use that. (The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores but isn't allowed to merge them, but there is no other mapping type we can use that allows the hardware to delay and merge stores, so we'll go with CB=01.) - XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight difference that on these platforms, CB=01 actually _does_ allow merging stores. (If you want noncoalescing bufferable behavior on Xscale v1/v2, you need to use XCB=101.) - Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100 mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal in ARMv6 parlance). The ARMv6 ARM explicitly says that any accesses to Normal memory can be merged, which makes Normal memory more suitable for _wc mappings than Device or Strongly Ordered memory, as the latter two mapping types are guaranteed to maintain transaction number, size and order. We use the Uncached variety of Normal mappings for the same reason that we can't use C=1 mappings on ARMv5. The xsc3 Architecture Specification documents TEXCB=00100 as being Uncacheable and allowing coalescing of writes, which is also just what we need. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 5229/3: Replace some ARMv7 opcodes with the instruction nameCatalin Marinas2008-10-03
| | | | | | | | | | | | | | | | | | These instructions were placed in the code directly as opcodes because early compilers didn't support them. Toolchains supporting ARMv7 understand these instructions and the patch puts the mnemonics back. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] mm: finish ARM sparsemem supportRussell King2008-10-01
| | | | | | | | | | | | | | | | | | ... including some comments about the ordering required to bring sparsemem up. You have to repeatedly guess, test, reguess, try again and again to work out what the right ordering is. Many hours later... Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] mm: provide helpers for accessing membanksRussell King2008-10-01
| | | | | | | | | | | | | | | | Provide helpers for getting physical addresses or pfns from the meminfo array, and use them. Move for_each_nodebank() to asm/setup.h alongside the meminfo structure definition. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] mm: move vmalloc= parsing to arch/arm/mm/mmu.cRussell King2008-09-30
| | | | | | | | | | | | | | | | | | There's no point scattering this around the tree, the parsing of the parameter might as well live beside the code which uses it. That also means we can make vmalloc_reserve a static variable. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] mm: move validation of membanks to one placeRussell King2008-09-30
| | | | | | | | | | | | | | | | The newly introduced sanity_check_meminfo() function should be used to collect all validation of the meminfo array, which we have in bootmem_init(). Move it there. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 5272/1: remove conditional compilation in show_pte()Nicolas Pitre2008-09-30
| | | | | | | | | | | | | | | | The PTRS_PER_PMD != 1 condition can be evaluated with C code and optimized at compile time. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] dma: don't touch cache on dma_*_for_cpu()Russell King2008-09-30
| | | | | | | | | | | | | | | | | | | | As per the dma_unmap_* calls, we don't touch the cache when a DMA buffer transitions from device to CPU ownership. Presently, no problems have been identified with speculative cache prefetching which in itself is a new feature in later architectures. We may have to revisit the DMA API later for these architectures anyway. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] dma: Reduce to one dma_sync_sg_* implementationRussell King2008-09-29
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] dma: Reduce to one dma_map_sg()/dma_unmap_sg() implementationRussell King2008-09-25
| | | | | | | | | | | | | | No point having two of these; dma_map_page() can do all the work for us. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] Update dma_map_sg()/dma_unmap_sg() APIRussell King2008-09-25
| | | | | | | | | | | | Update the ARM DMA scatter gather APIs for the scatterlist changes. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] dma: rename consistent.c to dma-mapping.cRussell King2008-09-25
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] Convert asm/io.h to linux/io.hRussell King2008-09-06
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] Convert asm/uaccess.h to linux/uaccess.hRussell King2008-09-06
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] clean up a load of old declarationsRussell King2008-09-06
| | | | | | | | | | | | ... some of which are now in linux/*.h headers. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] move initrd code from kernel/setup.c to mm/init.cRussell King2008-09-06
| | | | | | | | | | | | | | This quietens some sparse warnings about phys_initrd_start and phys_initrd_size. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] sparse: fix several warningsRussell King2008-09-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch/arm/kernel/process.c:270:6: warning: symbol 'show_fpregs' was not declared. Should it be static? This function isn't used, so can be removed. arch/arm/kernel/setup.c:532:9: warning: symbol 'len' shadows an earlier one arch/arm/kernel/setup.c:524:6: originally declared here A function containing two 'len's. arch/arm/mm/fault-armv.c:188:13: warning: symbol 'check_writebuffer_bugs' was not declared. Should it be static? arch/arm/mm/mmap.c:122:5: warning: symbol 'valid_phys_addr_range' was not declared. Should it be static? arch/arm/mm/mmap.c:137:5: warning: symbol 'valid_mmap_phys_addr_range' was not declared. Should it be static? Missing includes. arch/arm/kernel/traps.c:71:77: warning: Using plain integer as NULL pointer arch/arm/mm/ioremap.c:355:46: error: incompatible types in comparison expression (different address spaces) Sillies. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 5227/1: Add the ENDPROC declarations to the .S filesCatalin Marinas2008-09-01
| | | | | | | | | | | | | | | | | | This declaration specifies the "function" type and size for various assembly functions, mainly needed for generating the correct branch instructions in Thumb-2. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] cachetype: move definitions to separate headerRussell King2008-09-01
| | | | | | | | | | | | | | | | Rather than pollute asm/cacheflush.h with the cache type definitions, move them to asm/cachetype.h, and include this new header where necessary. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] cputype: separate definitions, use themRussell King2008-09-01
|/ | | | | | | | Add asm/cputype.h, moving functions and definitions from asm/system.h there. Convert all users of 'processor_id' to the more efficient read_cpuid_id() function. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] add proc-macros.S include to proc-arm940 and proc-arm946Russell King2008-08-12
| | | | | | ... otherwise these fail to build. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] prevent crashing when too much RAM installedLennert Buytenhek2008-08-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch will truncate and/or ignore memory banks if their kernel direct mappings would (partially) overlap with the vmalloc area or the mappings between the vmalloc area and the address space top, to prevent crashing during early boot if there happens to be more RAM installed than we are expecting. Since the start of the vmalloc area is not at a fixed address (but the vmalloc end address is, via the per-platform VMALLOC_END define), a default area of 128M is reserved for vmalloc mappings, which can be shrunk or enlarged by passing an appropriate vmalloc= command line option as it is done on x86. On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe000000, two 512M RAM banks and vmalloc=128M (the default), this patch gives: Truncating RAM at 20000000-3fffffff to -35ffffff (vmalloc region overlap). Memory: 512MB 352MB = 864MB total On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe800000, two 256M RAM banks and vmalloc=768M, this patch gives: Truncating RAM at 00000000-0fffffff to -0e7fffff (vmalloc region overlap). Ignoring RAM at 10000000-1fffffff (vmalloc region overlap). Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Tested-by: Riku Voipio <riku.voipio@iki.fi>
* [ARM] Move include/asm-arm/plat-orion to arch/arm/plat-orion/include/platLennert Buytenhek2008-08-09
| | | | | | | This patch performs the equivalent include directory shuffle for plat-orion, and fixes up all users. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
* [ARM] Move include/asm-arm/arch-* to arch/arm/*/include/machRussell King2008-08-07
| | | | | | This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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