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* [ARM] 3439/2: xsc3: add I/O coherency supportLennert Buytenhek2006-04-01
| | | | | | | | | | | | | | | | | | | | | Patch from Lennert Buytenhek This patch adds support for the I/O coherent cache available on the xsc3. The approach is to provide a simple API to determine whether the chipset supports coherency by calling arch_is_coherent() and then setting the appropriate system memory PTE and PMD bits. In addition, we call this API on dma_alloc_coherent() and dma_map_single() calls. A generic version exists that will compile out all the coherency-related code that is not needed on the majority of ARM systems. Note that we do not check for coherency in the dma_alloc_writecombine() function as that still requires a special PTE setting. We also don't touch dma_mmap_coherent() as that is a special ARM-only API that is by definition only used on non-coherent system. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3425/1: xsc3: need to include pgtable-hwdef.hLennert Buytenhek2006-03-30
| | | | | | | | | | Patch from Lennert Buytenhek Adapt xsc3 to the changes in 74945c8616a50074277e18641baaae7464006766 (xsc3 was written before but merged after the latter went in.) Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3377/2: add support for intel xsc3 coreLennert Buytenhek2006-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Lennert Buytenhek This patch adds support for the new XScale v3 core. This is an ARMv5 ISA core with the following additions: - L2 cache - I/O coherency support (on select chipsets) - Low-Locality Reference cache attributes (replaces mini-cache) - Supersections (v6 compatible) - 36-bit addressing (v6 compatible) - Single instruction cache line clean/invalidate - LRU cache replacement (vs round-robin) I attempted to merge the XSC3 support into proc-xscale.S, but XSC3 cores have separate errata and have to handle things like L2, so it is simpler to keep it separate. L2 cache support is currently a build option because the L2 enable bit must be set before we enable the MMU and there is no easy way to capture command line parameters at this point. There are still optimizations that can be done such as using LLR for copypage (in theory using the exisiting mini-cache code) but those can be addressed down the road. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] proc-v6: mark page table walks outer-cacheable, shared. Enable NX.Russell King2006-03-27
| | | | | | | Mark page table walks with outer-cacheable attribute, and enable no-execute in page tables. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge nommu treeRussell King2006-03-25
|\ | | | | | | | | | | Fix merge conflict in arch/arm/mm/proc-xscale.S Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] select TLS_REG_EMUL and NEEDS_SYSCALL_FOR_CMPXCHGRussell King2006-03-21
| | | | | | | | | | | | | | Rather than having a growing dependency line, use select to set these configuration symbols. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] nommu: Move hardware page table definitions to pgtable-hwdef.hRussell King2006-03-21
| | | | | | | | | | | | | | Move the hardware PMD and PTE page table definitions from pgtable.h into pgtable-hwdef.h, and include pgtable-hwdef.h as necessary. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2006-03-22
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/home/rmk/linux-2.6-arm: (45 commits) [ARM] 3389/1: typo and grammar fix [ARM] 3386/1: AT91RM9200 Clock update [ARM] 3384/1: AT91RM9200: Timer [ARM] 3382/1: ixp2000: unify defconfigs [ARM] 3381/1: ixp2000: fix slowport write timing control register fields [ARM] 3380/1: ixp2000: simplify ixdp2x00_master_npu() check [ARM] 3379/1: ixp2000: use generic 8250 debug macros [ARM] 3378/1: ixp2000: fix gpio interrupt handling [ARM] Quieten spurious IRQ detection [ARM] Use kcalloc to allocate counter_config array rather than kmalloc [ARM] Oprofile: dynamically allocate counter_config [ARM] Oprofile: Convert semaphore to mutex [ARM] 3376/2: S3C2410 - update defconfig [ARM] 3375/1: S3C2440 - fix osiris machine build [ARM] 3374/1: ep93xx: gpio interrupt support [ARM] 3361/1: S3C24XX - add USB bus clock source [ARM] 3360/1: S3C2440 - add set rate methods and camera clock [ARM] 3359/1: S3C24XX - add support for clk_set_rate [ARM] Convert kmalloc+memset to kzalloc [ARM] 3373/1: move uengine loader to arch/arm/common ...
| * | [ARM] 3369/1: ep93xx: add core cirrus ep93xx supportLennert Buytenhek2006-03-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Lennert Buytenhek This patch adds support for the Cirrus ep93xx series of CPUs. The ep93xx is an ARM920T based CPU with two VICs, PL010 based UARTs, IrDA, MaverickCrunch floating point coprocessor, between 24 and 64 GPIOs, ethernet, OHCI USB and, depending on the model, pcmcia, raster engine, graphics accelerator, IDE controller and a bunch of other stuff. This patch adds the core ep93xx support code, and support for the Glomation GESBC-9312-sx and the Technologic Systems TS-72xx SBCs. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | [ARM] Remove unnecessary asm/hardware.h includesRussell King2006-03-21
| |/ | | | | | | | | | | | | | | | | asm/hardware.h is not required for the majority of processor support files, ioremap support, mm initialisation, acorn IO support, nor the debug code (which picks up its machine specific includes via debug-macros.S) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [PATCH] remove set_page_count() outside mm/Nick Piggin2006-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | set_page_count usage outside mm/ is limited to setting the refcount to 1. Remove set_page_count from outside mm/, and replace those users with init_page_count() and set_page_refcounted(). This allows more debug checking, and tighter control on how code is allowed to play around with page->_count. Signed-off-by: Nick Piggin <npiggin@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | [PATCH] mm: split highorder pagesNick Piggin2006-03-22
|/ | | | | | | | | | | | | | | | | Have an explicit mm call to split higher order pages into individual pages. Should help to avoid bugs and be more explicit about the code's intention. Signed-off-by: Nick Piggin <npiggin@suse.de> Cc: Russell King <rmk@arm.linux.org.uk> Cc: David Howells <dhowells@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mundt <lethal@linux-sh.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Chris Zankel <chris@zankel.net> Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [ARM] 3356/1: Workaround for the ARM1136 I-cache invalidation problemCatalin Marinas2006-03-10
| | | | | | | | | | | | | | | | Patch from Catalin Marinas ARM1136 erratum 371025 (category 2) specifies that, under rare conditions, an invalidate I-cache by MVA (line or range) operation can fail to invalidate a cache line. The recommended workaround is to either invalidate the entire I-cache or invalidate the range by set/way rather than MVA. Note that for a 16K cache size, invalidating a 4K page by set/way is equivalent to invalidating the entire I-cache. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3352/1: DSB required for the completion of a TLB maintenance operationCatalin Marinas2006-03-07
| | | | | | | | | | | | | | | | Patch from Catalin Marinas Chapter B2.7.3 in the latest ARM ARM (with v6 information) states that the completion of a TLB maintenance operation is only guaranteed by the execution of a DSB (Data Syncronization Barrier, formerly Data Write Barrier or Drain Write Buffer). Note that a DSB is only needed in the flush_tlb_kernel_* functions since the completion is guaranteed by a mode change (i.e. switching back to user mode) for the flush_tlb_user_* functions. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] CONFIG_CPU_MPCORE -> CONFIG_CPU_32v6KRussell King2006-02-22
| | | | | | | CONFIG_CPU_MPCORE has never been a configuration symbol - it should be CONFIG_CPU_32v6K. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3294/1: don't invalidate individual BTB entries on ARMv6Nicolas Pitre2006-02-01
| | | | | | | | | | Patch from Nicolas Pitre Doing so adds a much larger cost to the loop than the cost implied by simply invalidating the whole BTB at once. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3293/1: don't invalidate the whole I-cache with xscale_coherent_user_rangeNicolas Pitre2006-02-01
| | | | | | | | | | Patch from Nicolas Pitre The mini I-cache issue is valid only for kernel space since debuggers would not fly if they used user space addresses for their stubs. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3269/1: Add ARMv6 MT_NONSHARED_DEVICE mem_types[] indexGeorge G. Davis2006-01-26
| | | | | | | | | | | | | Patch from George G. Davis This Freescale Semiconductor, Inc. contributed patch adds mem_types[] support for ARMv6 non-shared device memory region attributes. This implementation provides support for only first level section mapped non-shared devices. Second level non-shared device mappings are not yet supported. Signed-off-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix ioremap.c vfree type warningRussell King2006-01-20
| | | | | | | | arch/arm/mm/ioremap.c:145: warning: passing argument 1 of 'vfree' makes pointer from integer without a cast resulted from commit id 9d4ae7276ae26c5bfba6207cf05340af1931d8d4 Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3209/1: Configurable DMA-consistent memory regionKevin Hilman2006-01-12
| | | | | | | | | Patch from Kevin Hilman This patch increase available DMA-consistent memory allocated by dma_coherent_alloc(). The default remains at 2M (defined in asm/memory.h) and each platform has the ability to override in asm/arch-foo/memory.h. Signed-off-by: Kevin Hilman <kevin@hilman.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3070/2: Add __ioremap_pfn() APIDeepak Saxena2006-01-09
| | | | | | | | | | | | | | | | | | | | Patch from Deepak Saxena In working on adding 36-bit addressed supersection support to ioremap(), I came to the conclusion that it would be far simpler to do so by just splitting __ioremap() into a main external interface and adding an __ioremap_pfn() function that takes a pfn + offset into the page that __ioremap() can call. This way existing callers of __ioremap() won't have to change their code and 36-bit systems will just call __ioremap_pfn() and we will not have to deal with unsigned long long variables. Note that __ioremap_pfn() should _NOT_ be called directly by drivers but is reserved for use by arch_ioremap() implementations that map 32-bit resource regions into the real 36-bit address and then call this new function. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3240/2: AT91RM9200 support for 2.6 (Core)SAN People2006-01-09
| | | | | | | | | | | | | | | Patch from SAN People Following changes were made to clock.c: 1) Replaced <asm/hardware/clock.h> with <linux/clk.h> 2) Removed old unused clk_enable & clk_disable. 3) Replaced clk_use/clk_unuse with clk_enable/clk_disable. Otherwise it's the same as the previous patch. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Remove EPXA10DB machine supportRussell King2006-01-08
| | | | | | | | | | | | EPXA10DB seems to be uncared for: - the "PLD" code has never been merged - no one has reported that this platform has been broken since at least 2.6.10 - interest seems to have dried up around March 2003. Therefore, remove EPXA10DB support. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Cleanup ARM includesRussell King2006-01-03
| | | | | | | | | | | | | | | | arch/arm/kernel/entry-armv.S has contained a comment suggesting that asm/hardware.h and asm/arch/irqs.h should be moved into the asm/arch/entry-macro.S include. So move the includes to these two files as required. Add missing includes (asm/hardware.h, asm/io.h) to asm/arch/system.h includes which use those facilities, and remove asm/io.h from kernel/process.c. Remove other unnecessary includes from arch/arm/kernel, arch/arm/mm and arch/arm/mach-footbridge. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM SMP] Disable lazy flush_dcache_page for SMPRussell King2005-11-30
| | | | | | | Lazy flush_dcache_page() causes userspace instability on SMP platforms, so disable it for now. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Do not call flush_tlb_kernel_range() with IRQs disabled.Russell King2005-11-25
| | | | | | | | | | | | | | | | | | We must not call TLB maintainence operations with interrupts disabled, otherwise we risk a lockup in the SMP IPI code. This means that consistent_free() can not be called from a context with IRQs disabled. In addition, we must not hold the lock in consistent_free when we call flush_tlb_kernel_range(). However, we must continue to prevent consistent_alloc() from re-using the memory region until we've finished tearing down the mapping and dealing with the TLB. Therefore, leave the vm_region entry in the list, but mark it inactive before dropping the lock and starting the tear-down process. After the mapping has been torn down, re-acquire the lock and remove the entry from the list. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3168/1: Update ARM signal delivery and maskingDaniel Jacobowitz2005-11-19
| | | | | | | | | | | | | | | | | Patch from Daniel Jacobowitz After delivering a signal (creating its stack frame) we must check for additional pending unblocked signals before returning to userspace. Otherwise signals may be delayed past the next syscall or reschedule. Once that was fixed it became obvious that the ARM signal mask manipulation was broken. It was a little bit broken before the recent SA_NODEFER changes, and then very broken after them. We must block the requested signals before starting the handler or the same signal can be delivered again before the handler even gets a chance to run. Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix some corner cases in new mm initialisationRussell King2005-11-17
| | | | | | | | | | | | | | Document that the VMALLOC_END address must be aligned to 2MB since it must align with a PGD boundary. Allocate the vectors page early so that the flush_cache_all() later will cause any dirty cache lines in the direct mapping will be safely written back. Move the flush_cache_all() to the second local_flush_cache_tlb() and remove the now redundant first local_flush_cache_tlb(). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] __ioremap doesn't use 4th argumentRussell King2005-11-17
| | | | | | | | The "align" argument in ARMs __ioremap is unused and provides a misleading expectation that it might do something. It doesn't. Remove it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3145/1: OMAP 3a/5: Add support for omap24xxTony Lindgren2005-11-10
| | | | | | | | | | | | | | | | | | | Patch from Tony Lindgren This patch adds support for omap24xx series of processors. The files live in arch/arm/mach-omap2, and share common files with omap15xx and omap16xx processors in arch/arm/plat-omap. Omap24xx support was originally added for 2.6.9 by TI. This code was then improved and integrated to share common code with omap15xx and omap16xx processors by various omap developers, such as Paul Mundt, Juha Yrjola, Imre Deak, Tony Lindgren, Richard Woodruff, Nishant Menon, Komal Shah et al. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3141/1: OMAP 1/5: Update omap1 specific filesTony Lindgren2005-11-10
| | | | | | | | | | | | | | | | | | | | | | | | | Patch from Tony Lindgren This patch syncs the mainline kernel with linux-omap tree. The highlights of the patch are: - Omap1 serial pport and framebuffer init updates by Imre Deak - Add support for omap310 processor and Palm Tungsten E PDA by Laurent Gonzales, Romain Goyet, et al. Omap310 and omap1510 processors are now handled as omap15xx. - Omap1 specific changes to shared omap clock framework by Tony Lindgren - Omap1 specific changes to shared omap pin mux framework by Tony Lindgren - Other misc fixes, such as update memory timings for smc91x, omap1 specific device initialization etc. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM SMP] Add Realview MPcore SMP supportRussell King2005-11-07
| | | | | | | Add SMP support for the MPcore tile fitted to the Realview ARM platform. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM SMP] Add support for shared memory attributeRussell King2005-11-07
| | | | | | | We need to set the shared memory attribute in the page tables on SMP systems to allow the cache coherency to operate. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Merge SMP treeRussell King2005-11-03
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| * [ARM SMP] Add configuration option for ARMv6K processorsRussell King2005-11-03
| | | | | | | | | | | | | | The 'K' extension adds several new instructions to the ARMv6 ISA which are primerily useful for SMP. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 3092/1: remove excessive print format paddingNicolas Pitre2005-11-03
|/ | | | | | | | | | | Patch from Nicolas Pitre Using a llx format to print addresses that might possibly be (only) 36 bits wide make sense. However making it a zero padded 16 char wide field is a bit excessive and useless. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix mm initialisation with write buffered write allocate cachesRussell King2005-11-02
| | | | | | | | It seems that without the extra tlb flush, we may end up faulting during the early kernel initialisation because the TLB can't see the updated page tables. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Add support for ARM RealView boardCatalin Marinas2005-10-31
| | | | | | | Support for RealView EB. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Make v6 copypage function static and cleanup pgprotsRussell King2005-10-30
| | | | | | | | We know what pgprot we're going to use, so don't #define it. Also, since we select the nonaliasing/aliasing copypage implementation at run time, there's no point having it globally visible. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] mm: split page table lockHugh Dickins2005-10-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Christoph Lameter demonstrated very poor scalability on the SGI 512-way, with a many-threaded application which concurrently initializes different parts of a large anonymous area. This patch corrects that, by using a separate spinlock per page table page, to guard the page table entries in that page, instead of using the mm's single page_table_lock. (But even then, page_table_lock is still used to guard page table allocation, and anon_vma allocation.) In this implementation, the spinlock is tucked inside the struct page of the page table page: with a BUILD_BUG_ON in case it overflows - which it would in the case of 32-bit PA-RISC with spinlock debugging enabled. Splitting the lock is not quite for free: another cacheline access. Ideally, I suppose we would use split ptlock only for multi-threaded processes on multi-cpu machines; but deciding that dynamically would have its own costs. So for now enable it by config, at some number of cpus - since the Kconfig language doesn't support inequalities, let preprocessor compare that with NR_CPUS. But I don't think it's worth being user-configurable: for good testing of both split and unsplit configs, split now at 4 cpus, and perhaps change that to 8 later. There is a benefit even for singly threaded processes: kswapd can be attacking one part of the mm while another part is busy faulting. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] mm: arm ready for split ptlockHugh Dickins2005-10-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare arm for the split page_table_lock: three issues. Signal handling's preserve and restore of iwmmxt context currently involves reading and writing that context to and from user space, while holding page_table_lock to secure the user page(s) against kswapd. If we split the lock, then the structure might span two pages, secured by to read into and write from a kernel stack buffer, copying that out and in without locking (the structure is 160 bytes in size, and here we're near the top of the kernel stack). Or would the overhead be noticeable? arm_syscall's cmpxchg emulation use pte_offset_map_lock, instead of pte_offset_map and mm-wide page_table_lock; and strictly, it should now also take mmap_sem before descending to pmd, to guard against another thread munmapping, and the page table pulled out beneath this thread. Updated two comments in fault-armv.c. adjust_pte is interesting, since its modification of a pte in one part of the mm depends on the lock held when calling update_mmu_cache for a pte in some other part of that mm. This can't be done with a split page_table_lock (and we've already taken the lowest lock in the hierarchy here): so we'll have to disable split on arm, unless CONFIG_CPU_CACHE_VIPT to ensures adjust_pte never used. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] mm: arches skip ptlockHugh Dickins2005-10-30
| | | | | | | | | | | | | | | Convert those few architectures which are calling pud_alloc, pmd_alloc, pte_alloc_map on a user mm, not to take the page_table_lock first, nor drop it after. Each of these can continue to use pte_alloc_map, no need to change over to pte_alloc_map_lock, they're neither racy nor swappable. In the sparc64 io_remap_pfn_range, flush_tlb_range then falls outside of the page_table_lock: that's okay, on sparc64 it's like flush_tlb_mm, and that has always been called from outside of page_table_lock in dup_mmap. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] mm: init_mm without ptlockHugh Dickins2005-10-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First step in pushing down the page_table_lock. init_mm.page_table_lock has been used throughout the architectures (usually for ioremap): not to serialize kernel address space allocation (that's usually vmlist_lock), but because pud_alloc,pmd_alloc,pte_alloc_kernel expect caller holds it. Reverse that: don't lock or unlock init_mm.page_table_lock in any of the architectures; instead rely on pud_alloc,pmd_alloc,pte_alloc_kernel to take and drop it when allocating a new one, to check lest a racing task already did. Similarly no page_table_lock in vmalloc's map_vm_area. Some temporary ugliness in __pud_alloc and __pmd_alloc: since they also handle user mms, which are converted only by a later patch, for now they have to lock differently according to whether or not it's init_mm. If sources get muddled, there's a danger that an arch source taking init_mm.page_table_lock will be mixed with common source also taking it (or neither take it). So break the rules and make another change, which should break the build for such a mismatch: remove the redundant mm arg from pte_alloc_kernel (ppc64 scrapped its distinct ioremap_mm in 2.6.13). Exceptions: arm26 used pte_alloc_kernel on user mm, now pte_alloc_map; ia64 used pte_alloc_map on init_mm, now pte_alloc_kernel; parisc had bad args to pmd_alloc and pte_alloc_kernel in unused USE_HPPA_IOREMAP code; ppc64 map_io_page forgot to unlock on failure; ppc mmu_mapin_ram and ppc64 im_free took page_table_lock for no good reason. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [ARM] 3059/1: fix XIP supportNicolas Pitre2005-10-29
| | | | | | | | | Patch from Nicolas Pitre Fix XIP support after recent bootmem code refactoring. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2005-10-28
|\ | | | | | | Minor manual fixups for gfp_t clashes.
| * [ARM] 3017/1: Add support for 36-bit addresses to create_mapping()Deepak Saxena2005-10-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Deepak Saxena This patch adds support for 36-bit static mapped I/O. While there are no platforms in the tree ATM that use it, it has been tested tested on the IXP2350 NPU and I would like to get the support for that chipset upstream one piece at a time. There are also other Intel chipset ports in development that are waiting on this to go upstream. The patch replaces the print formats for physical addresses with %016llx which will create a bit extraneous output on 32-bit systems, but I think that is cleaner than having #ifdefs, specially since users will only see the output in error cases. Depends on 3016/1. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] 3016/1: Replace map_desc.physical with map_desc.pfnDeepak Saxena2005-10-28
| | | | | | | | | | | | | | | | | | | | | | Patch from Deepak Saxena Convert map_desc.physical to map_desc.pfn. This allows us to add support for 36-bit addressed physical devices in the static maps without having to resort to u64 variables. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] Re-jig bootmem initialisationRussell King2005-10-28
| | | | | | | | | | | | | | | | Make ARM independent of the way bootmem operates internally. We now map each node as we initialise it, and place the bootmem bitmap inside each node, rather than all in the first node. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] Fix sparse warningsRussell King2005-10-28
| | | | | | | | | | | | | | | | Fix sparse warnings in arch/arm/kernel/module.c, arch/arm/mm/consistent.c, drivers/pcmcia/sa1111_generic.c, and platform support files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] 3/4: Remove asm/hardware.h from SA1100 io.hRussell King2005-10-28
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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