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* ARM: 5888/1: arm: Update comments in cacheflush.h and remove unnecessary V6 ↵Tony Lindgren2010-01-19
| | | | | | | | | | | and V7 comments The comments in cacheflush.h should follow what's in struct cpu_cache_fns. The comments for V6 and V7 are unnecessary. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: dove: fix the mm mmu flags of the pj4 procinfoSaeed Bishara2009-12-07
| | | | | | | ... to be the same as proc-v6 Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* ARM: add base support for Marvell Dove SoCSaeed Bishara2009-11-27
| | | | | | | | | | | The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* ARM: ensure initial page tables are setup for SMP systemsRussell King2009-11-02
| | | | | | | | | | | | | | | | | Mapping the same memory using two different attributes (memory type, shareability, cacheability) is unpredictable. During boot, we encounter a situation when we're updating the kernel's page tables which can lead to dirty cache lines existing in the cache which are subsequently missed. This causes stack corruption, and therefore a crash. Therefore, ensure that the shared and cacheability settings matches the configuration that will be used later; this together with the restriction in early_cachepolicy() ensures that we won't create a mismatch during boot. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5727/1: Pass IFSR register to do_PrefetchAbort()Kirill A. Shutemov2009-10-02
| | | | | | | | | | | | | | | | | Instruction fault status register, IFSR, was introduced on ARMv6 to provide status information about the last insturction fault. It needed for proper prefetch abort handling. Now we have three prefetch abort model: * legacy - for CPUs before ARMv6. They doesn't provide neither IFSR nor IFAR. We simulate IFSR with section translation fault status for them to generalize code; * ARMv6 - provides IFSR, but not IFAR; * ARMv7 - provides both IFSR and IFAR. Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Add core support for ARMv6/v7 big-endianCatalin Marinas2009-05-30
| | | | | | | | | | | | | | | | Starting with ARMv6, the CPUs support the BE-8 variant of big-endian (byte-invariant). This patch adds the core support: - setting of the BE-8 mode via the CPSR.E register for both kernel and user threads - big-endian page table walking - REV used to rotate instructions read from memory during fault processing as they are still little-endian format - Kconfig and Makefile support for BE-8. The --be8 option must be passed to the final linking stage to convert the instructions to little-endian Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm: Use __INIT macro instead of .text.init.Tim Abbott2009-04-27
| | | | | | | | | | | | | arm is placing some code in the .text.init section, but it does not reference that section in its linker scripts. This change moves this code from the .text.init section to the .init.text section, which is presumably where it belongs. Signed-off-by: Tim Abbott <tabbott@mit.edu> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Modern processors may need to drain the WB before WFICatalin Marinas2008-11-10
| | | | | | | | | | | | | Since WFI may cause the processor to enter a low-power mode, data may still be in the write buffer. This patch adds a DSB (or DWB) to the cpu_(v6|v7)_do_idle functions before the WFI. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* [ARM] Don't include asm/elf.h in asm codeRussell King2008-10-01
| | | | | | asm code really wants asm/hwcap.h, so include that instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Convert ARMv6 and ARMv7 to use new memory typesRussell King2008-10-01
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Convert set_pte_ext implementions to macrosRussell King2008-10-01
| | | | | | | There are actually only four separate implementations of set_pte_ext. Use assembler macros to insert code for these into the proc-*.S files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] fix 48d7927bdf071d05cf5d15b816cf06b0937cb84fCatalin Marinas2008-04-24
| | | | | | | | | | The proc-*.S files have the _prefetch_abort pointer placed at the end of the processor structure but the cpu-multi32.h defines it in the second position. The patch also fixes the support for XSC3 and the MMU-less CPUs (740, 7tdmi, 940, 946 and 9tdmi). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* RealView: Move the SCU initialisation out of __v6_setupCatalin Marinas2008-04-18
| | | | | | | | | This patch moves the SCU initialisation from __v6_setup to the smp_prepare_cpus() function as it relies on platform-specific settings. Changes to get_core_count() are mainly for allowing cleaner code with the upcoming PB11MPCore patches. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* Add a prefetch abort handlerPaul Brook2008-04-18
| | | | | | | | | This patch adds a prefetch abort handler similar to the data abort one and renames the latter for consistency. Initial implementation by Paul Brook with some renaming by Catalin Marinas. Signed-off-by: Paul Brook <paul@codesourcery.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* Merge Realview GIC codeRussell King2007-02-15
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| * [ARM] 4109/2: Add support for the RealView/EB MPCore revC platformCatalin Marinas2007-02-15
| | | | | | | | | | | | | | | | | | | | | | The kernel originally supported revB only. This patch enables revC by default and adds a config option for building the kernel for the revB platform. Since the SCU base address was hard-coded in the proc-v6.S file (and only valid for RealView/EB revB), this patch also adds a more generic support for defining the SCU information. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] Always mark ARMv6 PTWs outer cacheableRussell King2007-02-08
|/ | | | | | | | | | | Other platforms other than SMP may have an outer cache. For these, we also need to mark the page table walks outer cacheable. Since marking the walks always outer cacheable apparantly has no side effects, we might as well always mark them so. However, we continue to only mark PTWs shared if we have SMP enabled. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Unuse another Linux PTE bitRussell King2006-12-13
| | | | | | | | | | L_PTE_ASID is not really required to be stored in every PTE, since we can identify it via the address passed to set_pte_at(). So, create set_pte_ext() which takes the address of the PTE to set, the Linux PTE value, and the additional CPU PTE bits which aren't encoded in the Linux PTE value. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Formalise the ARMv6 processor name stringRussell King2006-12-08
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Handle HWCAP_VFP in VFP support codeRussell King2006-12-08
| | | | | | | | | | | | Don't set HWCAP_VFP in the processor support file; not only does it depend on the processor features, but it also depends on the support code being present. Therefore, only set it if the support code detects that we have a VFP coprocessor attached. Also, move the VFP handling of the coprocessor access register into the VFP support code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Include asm/elf.h instead of asm/procinfo.hRussell King2006-11-30
| | | | | | | These files want to provide/access ELF hwcap information, so should be including asm/elf.h rather than asm/procinfo.h Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge nommu branchRussell King2006-07-01
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| * [ARM] nommu: provide a way for correct control register value selectionRussell King2006-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most MMU-based CPUs have a restriction on the setting of the data cache enable and mmu enable bits in the control register, whereby if the data cache is enabled, the MMU must also be enabled. Enabling the data cache without the MMU is an invalid combination. However, there are CPUs where the data cache can be enabled without the MMU. In order to allow these CPUs to take advantage of that, provide a method whereby each proc-*.S file defines the control regsiter value for use with nommu (with the MMU disabled.) Later on, when we add support for enabling the MMU on these devices, we can adjust the "crval" macro to also enable the data cache for nommu. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] Set bit 4 on section mappings correctly depending on CPURussell King2006-06-29
|/ | | | | | | | | | | | | | On some CPUs, bit 4 of section mappings means "update the cache when written to". On others, this bit is required to be one, and others it's required to be zero. Finally, on ARMv6 and above, setting it turns on "no execute" and prevents speculative prefetches. With all these combinations, no one value fits all CPUs, so we have to pick a value depending on the CPU type, and the area we're mapping. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: Initial uCLinux support for MMU-based CPUsHyok S. Choi2006-06-28
| | | | | | | | | | In noMMU mode, various of functions which are defined in mm/proc-*.S is not valid or needed to be avoided. i.g. switch_mm is not needed, just returns and this makes the I & D caches are valid which shows great improvement of performance including task switching and IPC. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Remove partial non-v6 binutils compatibilityRussell King2006-06-25
| | | | | | | | | proc-v6 contains some compatibility to be able to use the V6 "cps" instruction. However, the kernel makes use of this instruction elsewhere extensively, so there's no point keeping this compatibility anymore. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] proc-v6: mark page table walks outer-cacheable, shared. Enable NX.Russell King2006-03-27
| | | | | | | Mark page table walks with outer-cacheable attribute, and enable no-execute in page tables. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: Move hardware page table definitions to pgtable-hwdef.hRussell King2006-03-21
| | | | | | | Move the hardware PMD and PTE page table definitions from pgtable.h into pgtable-hwdef.h, and include pgtable-hwdef.h as necessary. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM SMP] Add Realview MPcore SMP supportRussell King2005-11-07
| | | | | | | Add SMP support for the MPcore tile fitted to the Realview ARM platform. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM SMP] Add support for shared memory attributeRussell King2005-11-07
| | | | | | | We need to set the shared memory attribute in the page tables on SMP systems to allow the cache coherency to operate. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3024/1: Add cpu_v6_proc_finTony Lindgren2005-10-19
| | | | | | | | | | | Patch from Tony Lindgren Machine restart calls cpu_proc_fin() to clean and disable cache, and turn off interrupts. This patch adds proper cpu_v6_proc_fin. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 2926/1: .proc.info - postfix section with .init for `make buildcheck`Ben Dooks2005-09-20
| | | | | | | | | | | Patch from Ben Dooks The `make buildcheck` is erroneously reporting that the .proc.info list is referencing items in the .init section as it is not itself postfixed with .init Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* kbuild: arm - use generic asm-offsets.h supportSam Ravnborg2005-09-09
| | | | | | | Delete obsoleted stuff from arch Makefile and rename constants.h to asm-offsets.h Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
* [ARM] Remove extraneous whitespace introduced in previous ARMv6 patchRussell King2005-08-15
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Control v6 'global' bit via Linux PTE entriesRussell King2005-08-10
| | | | | | | | | | | | Unfortunately, we can't use the "user" bit in the page tables to control whether a page table entry is "global" or "asid" specific, since the vector page is mapped as "user" accessible but is not process specific. Therefore, give direct control of the ARMv6 "nG" (not global) bit to the mm layers. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Use #defined constants for manipulating v6 hardware PTE bitsRussell King2005-08-10
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2789/1: Enable access to both CP10 and CP11 on ARMv6Catalin Marinas2005-07-06
| | | | | | | | | | | Patch from Catalin Marinas The VFP instructions trigger undefined exceptions because the access to CP11 is disabled (only CP10 is currently enabled by the kernel). The patch fixes this problem. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2698/1: Enable kernel r/w access to user pages on ARMv6Catalin Marinas2005-06-24
| | | | | | | | | | | | Patch from Catalin Marinas cpu_v6_set_pte() sets the kernel access rights to r/o for user pages (L_PTE_USER) when neither L_PTE_WRITE nor L_PTE_DIRTY are set. This causes a kernel data abort when writing the TLS value in the 0xffff0000 page. This patch enables the kernel r/w access. Signed-off-by: Catalin Marinas Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-16
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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