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* Merge git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivialLinus Torvalds2006-06-30
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial: Remove obsolete #include <linux/config.h> remove obsolete swsusp_encrypt arch/arm26/Kconfig typos Documentation/IPMI typos Kconfig: Typos in net/sched/Kconfig v9fs: do not include linux/version.h Documentation/DocBook/mtdnand.tmpl: typo fixes typo fixes: specfic -> specific typo fixes in Documentation/networking/pktgen.txt typo fixes: occuring -> occurring typo fixes: infomation -> information typo fixes: disadvantadge -> disadvantage typo fixes: aquire -> acquire typo fixes: mecanism -> mechanism typo fixes: bandwith -> bandwidth fix a typo in the RTC_CLASS help text smb is no longer maintained Manually merged trivial conflict in arch/um/kernel/vmlinux.lds.S
| * Remove obsolete #include <linux/config.h>Jörn Engel2006-06-30
| | | | | | | | | | Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
* | [PATCH] zoned vm counters: conversion of nr_pagetables to per zone counterChristoph Lameter2006-06-30
|/ | | | | | | | | Conversion of nr_page_table_pages to a per zone counter [akpm@osdl.org: bugfix] Signed-off-by: Christoph Lameter <clameter@sgi.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] ARM: Fix XScale PMD settingDeepak Saxena2006-05-31
| | | | | | | | | | | | The ARM Architecture Reference Manual lists bit 4 of the PMD as "implementation defined" and it must be set to zero on Intel XScale CPUs or the cache does not behave properly. Found by Mike Rapoport while debugging a flash issue on the PXA255: http://marc.10east.com/?l=linux-arm-kernel&m=114845287600782&w=1 Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [ARM] 3439/2: xsc3: add I/O coherency supportLennert Buytenhek2006-04-01
| | | | | | | | | | | | | | | | | | | | | Patch from Lennert Buytenhek This patch adds support for the I/O coherent cache available on the xsc3. The approach is to provide a simple API to determine whether the chipset supports coherency by calling arch_is_coherent() and then setting the appropriate system memory PTE and PMD bits. In addition, we call this API on dma_alloc_coherent() and dma_map_single() calls. A generic version exists that will compile out all the coherency-related code that is not needed on the majority of ARM systems. Note that we do not check for coherency in the dma_alloc_writecombine() function as that still requires a special PTE setting. We also don't touch dma_mmap_coherent() as that is a special ARM-only API that is by definition only used on non-coherent system. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3377/2: add support for intel xsc3 coreLennert Buytenhek2006-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Lennert Buytenhek This patch adds support for the new XScale v3 core. This is an ARMv5 ISA core with the following additions: - L2 cache - I/O coherency support (on select chipsets) - Low-Locality Reference cache attributes (replaces mini-cache) - Supersections (v6 compatible) - 36-bit addressing (v6 compatible) - Single instruction cache line clean/invalidate - LRU cache replacement (vs round-robin) I attempted to merge the XSC3 support into proc-xscale.S, but XSC3 cores have separate errata and have to handle things like L2, so it is simpler to keep it separate. L2 cache support is currently a build option because the L2 enable bit must be set before we enable the MMU and there is no easy way to capture command line parameters at this point. There are still optimizations that can be done such as using LLR for copypage (in theory using the exisiting mini-cache code) but those can be addressed down the road. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3269/1: Add ARMv6 MT_NONSHARED_DEVICE mem_types[] indexGeorge G. Davis2006-01-26
| | | | | | | | | | | | | Patch from George G. Davis This Freescale Semiconductor, Inc. contributed patch adds mem_types[] support for ARMv6 non-shared device memory region attributes. This implementation provides support for only first level section mapped non-shared devices. Second level non-shared device mappings are not yet supported. Signed-off-by: George G. Davis <gdavis@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Cleanup ARM includesRussell King2006-01-03
| | | | | | | | | | | | | | | | arch/arm/kernel/entry-armv.S has contained a comment suggesting that asm/hardware.h and asm/arch/irqs.h should be moved into the asm/arch/entry-macro.S include. So move the includes to these two files as required. Add missing includes (asm/hardware.h, asm/io.h) to asm/arch/system.h includes which use those facilities, and remove asm/io.h from kernel/process.c. Remove other unnecessary includes from arch/arm/kernel, arch/arm/mm and arch/arm/mach-footbridge. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM SMP] Add support for shared memory attributeRussell King2005-11-07
| | | | | | | We need to set the shared memory attribute in the page tables on SMP systems to allow the cache coherency to operate. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3092/1: remove excessive print format paddingNicolas Pitre2005-11-03
| | | | | | | | | | | Patch from Nicolas Pitre Using a llx format to print addresses that might possibly be (only) 36 bits wide make sense. However making it a zero padded 16 char wide field is a bit excessive and useless. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] mm: split page table lockHugh Dickins2005-10-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Christoph Lameter demonstrated very poor scalability on the SGI 512-way, with a many-threaded application which concurrently initializes different parts of a large anonymous area. This patch corrects that, by using a separate spinlock per page table page, to guard the page table entries in that page, instead of using the mm's single page_table_lock. (But even then, page_table_lock is still used to guard page table allocation, and anon_vma allocation.) In this implementation, the spinlock is tucked inside the struct page of the page table page: with a BUILD_BUG_ON in case it overflows - which it would in the case of 32-bit PA-RISC with spinlock debugging enabled. Splitting the lock is not quite for free: another cacheline access. Ideally, I suppose we would use split ptlock only for multi-threaded processes on multi-cpu machines; but deciding that dynamically would have its own costs. So for now enable it by config, at some number of cpus - since the Kconfig language doesn't support inequalities, let preprocessor compare that with NR_CPUS. But I don't think it's worth being user-configurable: for good testing of both split and unsplit configs, split now at 4 cpus, and perhaps change that to 8 later. There is a benefit even for singly threaded processes: kswapd can be attacking one part of the mm while another part is busy faulting. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [PATCH] mm: arches skip ptlockHugh Dickins2005-10-30
| | | | | | | | | | | | | | | Convert those few architectures which are calling pud_alloc, pmd_alloc, pte_alloc_map on a user mm, not to take the page_table_lock first, nor drop it after. Each of these can continue to use pte_alloc_map, no need to change over to pte_alloc_map_lock, they're neither racy nor swappable. In the sparc64 io_remap_pfn_range, flush_tlb_range then falls outside of the page_table_lock: that's okay, on sparc64 it's like flush_tlb_mm, and that has always been called from outside of page_table_lock in dup_mmap. Signed-off-by: Hugh Dickins <hugh@veritas.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [ARM] 3017/1: Add support for 36-bit addresses to create_mapping()Deepak Saxena2005-10-28
| | | | | | | | | | | | | | | | | | | | | Patch from Deepak Saxena This patch adds support for 36-bit static mapped I/O. While there are no platforms in the tree ATM that use it, it has been tested tested on the IXP2350 NPU and I would like to get the support for that chipset upstream one piece at a time. There are also other Intel chipset ports in development that are waiting on this to go upstream. The patch replaces the print formats for physical addresses with %016llx which will create a bit extraneous output on 32-bit systems, but I think that is cleaner than having #ifdefs, specially since users will only see the output in error cases. Depends on 3016/1. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3016/1: Replace map_desc.physical with map_desc.pfnDeepak Saxena2005-10-28
| | | | | | | | | | | Patch from Deepak Saxena Convert map_desc.physical to map_desc.pfn. This allows us to add support for 36-bit addressed physical devices in the static maps without having to resort to u64 variables. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Re-jig bootmem initialisationRussell King2005-10-28
| | | | | | | | Make ARM independent of the way bootmem operates internally. We now map each node as we initialise it, and place the bootmem bitmap inside each node, rather than all in the first node. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix ARMv6 page table bitsRussell King2005-09-01
| | | | | | | | We weren't explicitly setting the page table bits we desired in user_prot in the protection table, which resulted in the user mappings for v6 CPUs being marked global. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Simplify setup_mm_for_reboot()Russell King2005-09-01
| | | | | | | | No point checking what CPU architecture level we have each time within the loop, so precompute the base PMD flags outside the loop. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Convert open-coded __pmd_populate to use inline functionRussell King2005-09-01
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 2853/1: Make alloc_init_supersection() work with 36-bit mappingsDeepak Saxena2005-08-29
| | | | | | | | | | | | | | | | | | | Patch from Deepak Saxena Working on adding support for 36-bit static mappings for ARMv6 and Intel's XSC3 core and noticed that alloc_init_supersection currently increments the phys addr by 1MB on each of the 16 iterations and then forces alignment to supersection size (16MB). This is really uneeded b/c we have already forced the phys address to be 16MB aligned in create_mapping(). Furthermore, this breaks 36-bit addressing b/c bits [23:20] of the PMD contain bits [35:32] of the physical address and the masking causes us to loose those bits thus ending up with an incorrect virt -> phys translation. The other option is to have an alloc_init_supersection36. Tested on Intel IXP2350 CPU with 36-bit static I/O mappings. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Control v6 'global' bit via Linux PTE entriesRussell King2005-08-10
| | | | | | | | | | | | Unfortunately, we can't use the "user" bit in the page tables to control whether a page table entry is "global" or "asid" specific, since the vector page is mapped as "user" accessible but is not process specific. Therefore, give direct control of the ARMv6 "nG" (not global) bit to the mm layers. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM SMP: Mark device mappings as "device" in ARMv6 parlanceRussell King2005-07-26
| | | | | | | ARMv6 introduces memory types into the page tables. Mark devices mappings with the "shared device" memory type. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2796/1: Fix ARMv5[TEJ] check in MMU initalizationDeepak Saxena2005-07-10
| | | | | | | | | | | Patch from Deepak Saxena The code in mm-armv.c checks for the condition (cpu_architecture()<= ARMv5) in a few places but should be checking for ARMv5TEJ as the MMU is shared across all v5 variations. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM SMP: Use local_flush_tlb* where we really want to be localRussell King2005-06-28
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Move memmap freeing into init.cRussell King2005-06-27
| | | | | | | It doesn't make sense for this to be in mm-armv.c now that 26-bit ARM support is no longer integrated into arch/arm. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Move PGD kernel page table initialisationRussell King2005-06-27
| | | | | | | | It doesn't make sense to have the PGD kernel pointers initialisation separate from the PGD user pointers, especially when we clean the data cache over the whole range. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: Fix build errorRussell King2005-05-16
| | | | | | Mainline kernels don't have VECTORS_HIGH nor COPYPAGE_MINICACHE yet. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
* [PATCH] ARM: Add top_pmd, which points at the top-most page tableRussell King2005-05-10
| | | | Signed-off-by: Russell King <rmk@arm.linux.org.uk>
* [PATCH] ARM: Add inline functions to find the pmd from virtual addressRussell King2005-05-09
| | | | | | | Add pmd_off() and pmd_off_k() to obtain the pmd pointer for a virtual address, and use them throughout the mm initialisation. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
* [PATCH] ARM: 2656/1: Access permission bits are wrong for kernel XIP ↵George G. Davis2005-04-29
| | | | | | | | | | | | sections on ARMv6 Patch from George G. Davis This patch is required for kernel XIP support on ARMv6 machines. It ensures that the access permission bits for kernel XIP section descriptors are APX=1 and AP[1:0]=01, which is Kernel read-only/User no access permissions. Prior to this change, kernel XIP section descriptor access permissions were set to Kernel no access/User no access on ARMv6 machines and the kernel would therefore hang upon entry to userspace when set_fs(USER_DS) was executed. Signed-off-by: Steve Longerbeam Signed-off-by: George G. Davis Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-16
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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