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* Merge branch 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2011-03-17
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm: (289 commits) davinci: DM644x EVM: register MUSB device earlier davinci: add spi devices on tnetv107x evm davinci: add ssp config for tnetv107x evm board davinci: add tnetv107x ssp platform device spi: add ti-ssp spi master driver mfd: add driver for sequencer serial port ARM: EXYNOS4: Implement Clock gating for System MMU ARM: EXYNOS4: Enhancement of System MMU driver ARM: EXYNOS4: Add support for gpio interrupts ARM: S5P: Add function to register gpio interrupt bank data ARM: S5P: Cleanup S5P gpio interrupt code ARM: EXYNOS4: Add missing GPYx banks ARM: S3C64XX: Fix section mismatch from cpufreq init ARM: EXYNOS4: Add keypad device to the SMDKV310 ARM: EXYNOS4: Update clocks for keypad ARM: EXYNOS4: Update keypad base address ARM: EXYNOS4: Add keypad device helpers ARM: EXYNOS4: Add support for SATA on ARMLEX4210 plat-nomadik: make GPIO interrupts work with cpuidle ApSleep mach-u300: define a dummy filter function for coh901318 ... Fix up various conflicts in - arch/arm/mach-exynos4/cpufreq.c - arch/arm/mach-mxs/gpio.c - drivers/net/Kconfig - drivers/tty/serial/Kconfig - drivers/tty/serial/Makefile - drivers/usb/gadget/fsl_mxc_udc.c - drivers/video/Kconfig
| * Merge branch 'for-rmk' of ↵Russell King2011-03-15
| |\ | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into devel-stable Conflicts: arch/arm/mm/Kconfig
| | * ARM: EXYNOS4: Update Kconfig and Makefile for the new ARCH_EXYNOS4Kukjin Kim2011-02-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the Kconfig and Makefile for the new ARCH_EXYNOS4. It also updates arch/arm/Kconfig, Makeifile and arch/arm/mm/Kconfig to include support for the new ARCH_EXYNOS4. Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into ↵Russell King2011-03-10
| |\ \ | | |/ | |/| | | | devel-stable
| | * ARM: imx3x: clean up ARCH_MX3XRichard Zhao2011-03-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move to SOC_SOC_IMX3X. Leave ARCH_MX31/35 definitions there, in case some place prevent multi-soc single image. Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'v6v7' into develRussell King2011-03-16
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/include/asm/cacheflush.h arch/arm/include/asm/proc-fns.h arch/arm/mm/Kconfig
| * | | ARM: v6k: DMA_CACHE_RWFO isn't appropriate for non-v6k CPUsRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Limit DMA_CACHE_RWFO to only v6k SMP CPUs - V6 CPUs aren't SMP capable, so the read/write for ownership work-around doesn't apply to them. Acked-by: Will Deacon <will.deacon@arm.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: v6k: allow swp emulation again when ARMv7 is enabledRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we build a v6+v6k+v7 kernel with -march=armv6k for everything, we don't need to disable swp emulation to work around the build problem with OMAP. Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: v6k: do not disable CPU_32v6K based on platform selectionRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPU_32v6K controls whether we use the ARMv6K extension instructions in the kernel, and in some places whether we use SMP-safe code sequences (eg, bitops.) MX3 prevents the selection of this option to ensure that it is not enabled for their CPU, which is ARMv6 only. Now that we've split the CPU_V6 option, V6K support won't be offered for MX3 anymore. OMAP prevents the selection of this option in an attempt to produce a kernel which runs on architectures from ARMv6 to ARMv7 MPCore. We now achieve this in a different way (see the previous patches). As such, we no longer need to offer this as a configuration option to the user. Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: v6k: use CPU domain feature if we include support for arch < ARMv6KRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than turning off CPU domain switching when the build architecture includes ARMv6K, thereby causing problems for ARMv6-supporting kernels, turn it on when it's required to support a CPU architecture. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: v6k: Dove platforms use V6K architecture CPUsRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make Dove platforms select the new V6K CPU option. Tested-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: v6k: introduce CPU_V6K optionRussell King2011-02-02
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a CPU_V6K configuration option for platforms to select if they have a V6K CPU core. This allows us to identify whether we need to support ARMv6 CPUs without the V6K SMP extensions at build time. Currently CPU_V6K is just an alias for CPU_V6, and all places which reference CPU_V6 are replaced by (CPU_V6 || CPU_V6K). Select CPU_V6K from platforms which are known to be V6K-only. Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | Merge branch 'misc' into develRussell King2011-03-16
|\ \ \ | |_|/ |/| | | | | | | | Conflicts: arch/arm/Kconfig
| * | ARM: move L1_CACHE_SHIFT_6 to mm/KconfigRussell King2011-02-23
| |/ | | | | | | | | | | | | Move L1_CACHE_SHIFT related options together, rather than spreading them across two separate Kconfig files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: make SWP emulation explicit on !CPU_USE_DOMAINSRussell King2011-02-10
| | | | | | | | | | | | | | | | SWP emulation requires that CPU domain support is disabled in order to work safely. Make that explicit in the kernel configuration to prevent illegal configurations being generated. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: Avoid building unsafe kernels on OMAP2 and MX3Russell King2011-02-09
|/ | | | | | | | | | | | | | | OMAP2 (armv6) and MX3 turn off support for the V6K instructions, which when they include support for SMP kernels means that the resulting kernel is unsafe on SMP and can result in corrupted filesystems as we end up using unsafe bitops. Re-enable the use of V6K instructions on such kernels, and let such kernels running on V6 CPUs eat undefined instruction faults which will be much safer than filesystem corruption. Next merge window we can fix this properly (as it requires a much bigger set of changes.) Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'omap-fixes-for-linus' of ↵Linus Torvalds2011-01-14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 * 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (27 commits) omap4: Fix ULPI PHY init for ES1.0 SDP omap3: beaglexm: fix power on of DVI omap3: igep3: Add omap_reserve functionality omap3: beaglexm: fix DVI reset GPIO omap3: beaglexm: fix EHCI power up GPIO dir omap3: igep2: Add keypad support omap3: igep3: Fix IGEP module second MMC channel power supply omap3: igep3: Add USB EHCI support for IGEP module omap3: clocks: Fix build error 'CK_3430ES2' undeclared here arm: omap4: pandaboard: turn on PHY reference clock at init omap2plus: prm: Trvial build break fix for undefined reference to 'omap2_prm_read_mod_reg' omap2plus: voltage: Trivial linking fix for 'EINVAL' undeclared omap2plus: voltage: Trivial linking fix 'undefined reference' omap2plus: voltage: Trivial warning fix 'no return statement' omap2plus: clockdomain: Trivial fix for build break because of clktrctrl_mask arm: omap: gpio: don't access irq_desc array directly omap2+: pm_bus: make functions used as pointers as static OMAP: GPIO: fix _set_gpio_triggering() for OMAP2+ OMAP2+: TWL: include pm header for init protos OMAP2+: TWL: make conversion routines static ... Fix up conflicts in arch/arm/mach-omap2/board-omap3beagle.c ("DVI reset GPIO" vs "use generic DPI panel driver")
| * ARM: Do not enable SWP emulation if CPU_V6 && CPU_V7Catalin Marinas2011-01-06
| | | | | | | | | | | | | | | | | | | | This option uses LDREXB/STREXB to emulate SWPB but these instructions are not supported on all the ARMv6 processors. Reported-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Leif Lindholm <Leif.Lindholm@arm.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | Merge branch 'master' of ↵Paul Mundt2011-01-06
|\| | | | | | | | | | | | | | | | | master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6 into rmobile-latest Conflicts: arch/arm/mach-shmobile/Kconfig Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * Merge branch 'devel-stable' into develRussell King2011-01-06
| |\ | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-pxa/clock.c arch/arm/mach-pxa/clock.h
| | * ARM: mmp: select CPU_PJ4Haojian Zhuang2010-12-18
| | | | | | | | | | | | | | | | | | | | | | | | Since CPU_PJ4 is shared between PXA95x and MMP2, select CPU_PJ4 in MMP2 configuration. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| | * ARM: pxa: support pxa95xHaojian Zhuang2010-12-18
| | | | | | | | | | | | | | | | | | | | | | | | The core of PXA955 is PJ4. Add new PJ4 support. And add new macro CONFIG_PXA95x. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * | ARM: 6396/1: Add SWP/SWPB emulation for ARMv7 processorsLeif Lindholm2010-11-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SWP instruction was deprecated in the ARMv6 architecture, superseded by the LDREX/STREX family of instructions for load-linked/store-conditional operations. The ARMv7 multiprocessing extensions mandate that SWP/SWPB instructions are treated as undefined from reset, with the ability to enable them through the System Control Register SW bit. This patch adds the alternative solution to emulate the SWP and SWPB instructions using LDREX/STREX sequences, and log statistics to /proc/cpu/swp_emulation. To correctly deal with copy-on-write, it also modifies cpu_v7_set_pte_ext to change the mappings to priviliged RO when user RO. Signed-off-by: Leif Lindholm <leif.lindholm@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6384/1: Remove the domain switching on ARMv6k/v7 CPUsCatalin Marinas2010-11-04
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the domain switching functionality via the set_fs and __switch_to functions on cores that have a TLS register. Currently, the ioremap and vmalloc areas share the same level 1 page tables and therefore have the same domain (DOMAIN_KERNEL). When the kernel domain is modified from Client to Manager (via the __set_fs or in the __switch_to function), the XN (eXecute Never) bit is overridden and newer CPUs can speculatively prefetch the ioremap'ed memory. Linux performs the kernel domain switching to allow user-specific functions (copy_to/from_user, get/put_user etc.) to access kernel memory. In order for these functions to work with the kernel domain set to Client, the patch modifies the LDRT/STRT and related instructions to the LDR/STR ones. The user pages access rights are also modified for kernel read-only access rather than read/write so that the copy-on-write mechanism still works. CPU_USE_DOMAINS gets disabled only if the hardware has a TLS register (CPU_32v6K is defined) since writing the TLS value to the high vectors page isn't possible. The user addresses passed to the kernel are checked by the access_ok() function so that they do not point to the kernel space. Tested-by: Anton Vorontsov <cbouatmailru@gmail.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* / ARM: mach-shmobile: Initial AG5 and AG5EVM supportMagnus Damm2010-11-18
|/ | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds initial support for Renesas SH-Mobile AG5. At this point the AG5 CPU support is limited to the ARM core, SCIF serial and a CMT timer together with L2 cache and the GIC. The AG5EVM board also supports Ethernet. Future patches will add support for GPIO, INTCS, CPGA and platform data / driver updates for devices such as IIC, LCDC, FSI, KEYSC, CEU and SDHI among others. The code in entry-macro.S will be cleaned up when the ARM IRQ demux code improvements have been merged. Depends on the AG5EVM mach-type recently registered but not yet present in arch/arm/tools/mach-types. As the AG5EVM board comes with 512MiB memory it is recommended to turn on HIGHMEM. Many thanks to Yoshii-san for initial bring up. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* ARM: Improve the L2 cache performance when PL310 is usedCatalin Marinas2010-10-26
| | | | | | | | | | | With this L2 cache controller, the cache maintenance by PA and sync operations are atomic and do not require a "wait" loop. This patch conditionally defines the cache_wait() function. Since L2x0 cache controllers do not work with ARMv7 CPUs, the patch automatically enables CACHE_PL310 when only CPU_V7 is defined. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* ARM: 6344/1: Mark CPU_32v6K as depended on CPU_V7Catalin Marinas2010-09-02
| | | | | | | | CPU_32v6K is selected by CPU_V7 but it only depends on CPU_V6. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branches 'master' and 'devel' into for-linusRussell King2010-08-10
|\ | | | | | | | | | | Conflicts: arch/arm/Kconfig arch/arm/mm/Kconfig
| * Merge branch 'for-rmk' of ↵Russell King2010-08-09
| |\ | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into devel-stable Conflicts: arch/arm/Kconfig
| | * ARM: S5PV310: Add new Kconfig and MakefilesChanghwan Youn2010-08-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the Kconfig and Makefile for the new S5PV310 SoC. It also updates arch/arm Kconfig, Makefile and arch/arm/mm/Kconfig to include support for the new S5PV310. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | [ARM] tegra: initial tegra supportErik Gilling2010-08-05
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: Fixes from Mike Rapoport - remove unused header files (mach/dma.h and mach/nand.h) - remove tegra 1 references from Makefile.boot v2: fixes from Russell King - remove mach/io.h include from mach/iomap.h - fix whitespace in Kconfig v2: from Colin Cross - fix invalid immediate in debug-macro.S v3: - allow selection of multiple boards Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com>
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*-. \ Merge branches 'at91', 'ep93xx', 'kexec', 'iop', 'lmb', 'nomadik', 'nuc', ↵Russell King2010-07-31
|\ \ \ | |_|/ |/| | | | | 'pl', 'spear' and 'versatile' into devel
| | * ARM: 6207/1: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6Tony Lindgren2010-07-09
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TLS register is only available on ARM1136 r1p0 and later. Set HWCAP_TLS flags if hardware TLS is available and test for it if CONFIG_CPU_32v6K is not set for V6. Note that we set the TLS instruction in __kuser_get_tls dynamically as suggested by Jamie Lokier <jamie@shareable.org>. Also the __switch_to code is optimized out in most cases as suggested by Nicolas Pitre <nico@fluxnic.net>. Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6202/1: Do not ARM_DMA_MEM_BUFFERABLE on RealView boards with L210/L220Catalin Marinas2010-07-02
| | | | | | | | | | | | | | | | | | | | | | RealView boards with certain revisions of the L210/L220 cache controller may have issues (hardware deadlock) with the mandatory barriers (DSB followed by an L2 cache sync) when ARM_DMA_MEM_BUFFERABLE is enabled. The patch disables ARM_DMA_MEM_BUFFERABLE for these boards. Tested-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6188/1: Add a config option for the ARM11MPCore DMA cache maintenance ↵Catalin Marinas2010-07-01
|/ | | | | | | | | | | | | | | | | | | | workaround Commit f4d6477f introduced a workaround for the lack of hardware broadcasting of the cache maintenance operations on ARM11MPCore. However, the workaround is only valid on CPUs that do not do speculative loads into the D-cache. This patch adds a Kconfig option with the corresponding help to make the above clear. When the DMA_CACHE_RWFO option is disabled, the kernel behaviour is that prior to the f4d6477f commit. This also allows ARMv6 UP processors with speculative loads to work correctly. For other processors, a different workaround may be needed. Cc: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'devel-stable' into develRussell King2010-05-17
|\ | | | | | | | | | | | | Conflicts: arch/arm/Kconfig arch/arm/include/asm/system.h arch/arm/mm/Kconfig
| * Merge branch 'devel' of ↵Russell King2010-05-13
| |\ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel-stable
| | * [ARM] mmp: enable L2 in mmp2Haojian Zhuang2010-05-11
| | | | | | | | | | | | | | | | | | | | | Enable Tauros2 L2 in mmp2. Tauros2 L2 is shared in Marvell ARM cores. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * | arm: mm: qsd8x50: Fix incorrect permission faultsDave Estes2010-05-03
| |/ | | | | | | | | | | | | | | | | Handle incorrectly reported permission faults for qsd8650. On permission faults, retry MVA to PA conversion. If retry detects translation fault. Report as translation fault. Cc: Jamie Lokier <jamie@shareable.org> Signed-off-by: Dave Estes <cestes@quicinc.com>
| * ARM: 5996/1: ARM: Change the mandatory barriers implementation (4/4)Catalin Marinas2010-03-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mandatory barriers (mb, rmb, wmb) are used even on uniprocessor systems for things like ordering Normal Non-cacheable memory accesses with DMA transfer (via Device memory writes). The current implementation uses dmb() for mb() and friends but this is not sufficient. The DMB only ensures the relative ordering of the observability of accesses by other processors or devices acting as masters. In case of DMA transfers started by writes to device memory, the relative ordering is not ensured because accesses to slave ports of a device are not considered observable by the DMB definition. A DSB is required for the data to reach the main memory (even if mapped as Normal Non-cacheable) before the device receives the notification to begin the transfer. Furthermore, some L2 cache controllers (like L2x0 or PL310) buffer stores to Normal Non-cacheable memory and this would need to be drained with the outer_sync() function call. The patch also allows platforms to define their own mandatory barriers implementation by selecting CONFIG_ARCH_HAS_BARRIERS and providing a mach/barriers.h file. Note that the SMP barriers are unchanged (being DMBs as before) since they are only guaranteed to work with Normal Cacheable memory. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5995/1: ARM: Add L2x0 outer_sync() support (3/4)Catalin Marinas2010-03-25
| | | | | | | | | | | | | | | | The L2x0 cache controllers need to explicitly drain their write buffer even for Normal Noncacheable memory accesses. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5994/1: ARM: Add outer_cache_fns.sync function pointer (2/4)Catalin Marinas2010-03-25
| | | | | | | | | | | | | | | | | | This patch introduces the outer_cache_fns.sync function pointer together with the OUTER_CACHE_SYNC config option that can be used to drain the write buffer of the outer cache. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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*---. \ Merge branches 'at91', 'bcmring', 'ep93xx', 'iop', 'misc', 'nomadik', ↵Russell King2010-05-17
|\ \ \ \ | |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | 'omap', 'pxa', 'spear' and 'versatile' into devel Conflicts: arch/arm/Makefile arch/arm/common/Makefile arch/arm/mm/Kconfig
| | | * ARM: Add Versatile Express CA9x4 processor supportRussell King2010-05-02
| |_|/ |/| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * ARM: 6027/1: ux500: enable l2x0 supportSrinidhi Kasagar2010-04-14
| |/ |/| | | | | | | | | | | | | | | This enables the l2x0 support and ensures that the secondary CPU can see the page table and secondary data at this point. Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: Optionally allow ARMv6 to use 'normal, bufferable' memory for DMARussell King2010-05-17
|/ | | | | | | | | | | | | Provide a configuration option to allow the ARMv6 to use normal bufferable memory for coherent DMA. This option is forced to 'y' for ARMv7, and offered as a configuration option on ARMv6. Enabling this option requires drivers to have the necessary barriers to ensure that data in DMA coherent memory is visible prior to the DMA operation commencing. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5952/1: ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH ↵Kukjin Kim2010-02-24
| | | | | | | | | | | | | | | | Kconfig Add ARM_L1_CACHE_SHIFT_6 to arch/arm/Kconfig to allow CPUs with L1 cache lines which are 64bytes to indicate this without having to alter the arch/arm/mm/Kconfig entry each time. Update the mm Kconfig so that ARM_L1_CACHE_SHIFT default value uses this and change OMAP3 and S5PC1XX to select ARM_L1_CACHE_SHIFT_6. Acked-by: Ben Dooks <ben-linux@fluff.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5917/1: OMAP4: Add L2 Cache supportSantosh Shilimkar2010-02-15
| | | | | | | | | | This patch adds L2 Cache support for OMAP4. External L2 cache is used in OMAP4 CC: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5911/1: ARM: Select CPU_32v6K for CPU_V7 only if ARCH_OMAP2 is not selectedTony Lindgren2010-02-15
| | | | | | | | Otherwise the kernel built with both CPU_V6 and CPU_V7 will not boot on omap2. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Kill CONFIG_CPU_32Russell King2009-12-18
| | | | | | | | 26-bit ARM support was removed a long time ago, and this symbol has been defined to be 'y' ever since. As it's never disabled anymore, we can kill it without any side effects. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 21:19:18 -0500