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* Merge branch 'msm-move-gpio' of ↵Grant Likely2011-08-01
|\ | | | | | | | | | | | | | | git://codeaurora.org/quic/kernel/davidb/linux-msm into gpio/next Conflicts: drivers/gpio/Kconfig drivers/gpio/Makefile
| * gpio_msm: Move Qualcomm MSM v2 gpio driver into driversDavid Brown2011-08-01
| | | | | | | | | | | | | | | | | | | | Migrate the driver for the v7-based MSM chips into drivers/gpio. The driver is unchanged, only moved. Change-Id: I810db5b50b71cdca4e869aa0d0310f7f48781a55 Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * gpio_msm: Move Qualcomm v6 MSM driver into driversDavid Brown2011-08-01
| | | | | | | | | | | | | | | | | | | | Migrate the driver for the v6-based MSM chips into drivers/gpio. The driver is unchanged, only moved. Change-Id: I03ba597b95b4d62b42da112a8efac88d67aa40f9 Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * msm: gpio: Fold register defs into C fileDavid Brown2011-08-01
| | | | | | | | | | | | | | | | No need to have a separate header file containing only register definitions that are used by a single driver. Fold these into the gpio driver. Signed-off-by: David Brown <davidb@codeaurora.org>
| * msm: gpiomux: Move public API to public headerDavid Brown2011-08-01
| | | | | | | | | | | | | | | | | | | | | | The gpiomux.h header contains some SOC ifdefs. However, the API that is actually used by the GPIO driver only uses two functions that are general. Move these general definitions into a public header file. Change-Id: Ia5df8af87dba268225598d56908e523bcfc24ef6 Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * msm: gpio: Remove ifdefs on gpio chip registersDavid Brown2011-08-01
| | | | | | | | | | | | | | | | | | | | Select the GPIO register configuration at runtime rather than through idefs. Change-Id: I02ea0a3d61bc81669f32097c32420f0688552231 Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * msm: gpio: Remove chip-specific register definitionsDavid Brown2011-08-01
| | | | | | | | | | | | | | | | | | | | Put an SOC prefix on each GPIO register definition, eliminating the need to have SOC ifdefs around the definitions. Change-Id: I5a01fd328a89ce1be610847934d6e118f5465e42 Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * msm: Remove chip-ifdefs for GPIO io mappingsDavid Brown2011-08-01
| | | | | | | | | | | | | | | | | | | | | | | | | | The two GPIO controllers are always mapped to the same virtual address across all MSM devices. Instead of selecting this at compile time, determine the physical address at runtime, eliminating yet something else preventing multiple MSM targets from being compiled into the same kernel. Change-Id: I1672219d978ab6243526adeda6badf49472baa27 Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * msm: gpio: Remove unsupported devicesDavid Brown2011-08-01
| | | | | | | | | | | | | | | | | | | | The MSM7x25 and MSM7x27 devices are not yet supported in the kernel. Remove #ifdef-based tables supporting these chips for now. Change-Id: I4d9f5abc4cc0942ce75a067097b072489493c1b8 Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* | Merge branch 'next/cross-platform' of ↵Linus Torvalds2011-07-26
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc * 'next/cross-platform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: ARM: Consolidate the clkdev header files ARM: set vga memory base at run-time ARM: convert PCI defines to variables ARM: pci: make pcibios_assign_all_busses use pci_has_flag ARM: remove unnecessary mach/hardware.h includes pci: move microblaze and powerpc pci flag functions into asm-generic powerpc: rename ppc_pci_*_flags to pci_*_flags Fix up conflicts in arch/microblaze/include/asm/pci-bridge.h
| * | ARM: Consolidate the clkdev header filesKyungmin Park2011-07-19
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now most of ARM machines has the alsmot same __clk_get/put() macro So place it at the arch/arm/include/asm/clkdev.h and remove the reduntant header files But some machines don't have the same form as above. It can use the machince specific clkdev file by HAVE_MACH_CLKDEV config Now there are only 3 caese. 1) define the clk structure with clkdev macro => Need to move clk structure to proper header file arch/arm/mach-versatile/include/mach/clkdev.h arch/arm/mach-realview/include/mach/clkdev.h arch/arm/mach-vexpress/include/mach/clkdev.h arch/arm/mach-integrator/include/mach/clkdev.h 2) export the __clk_get/put function at clock.c arch/arm/mach-shmobile/include/mach/clkdev.h 3) demuxing the clk source arch/arm/mach-u300/include/mach/clkdev.h Acked-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* | Merge branch 'next/fixes' of ↵Linus Torvalds2011-07-25
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc * 'next/fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (35 commits) ARM: msm: platsmp: determine number of CPU cores at boot time ARM: Tegra: Seaboard: Fix I2C bus numbering for ADT7461 ARM: Tegra: Trimslice: Tri-state DAP3 pinmux ARM: orion5x: fixup 5181 MPP mask check ARM: mxs-dma: include <linux/dmaengine.h> ARM: i.MX53: consistently use MX53_UART_PAD_CTRL for uart txd/rxd/rts/cts ARM: i.MX53: UARTn_CTS pin should not change RTS input select ARM: i.MX53: UARTn_TXD pin should not change RXD input select ARM: mx25: Fix typo on CAN1_RX pad setting iomux-mx53: add missing 'IOMUX_CONFIG_SION' for some I2C pad definitions ARM: NUC93X: add UL suffix to VMALLOC_END to ensure it is properly typed ARM: LPC32XXX: add UL suffix to VMALLOC_END to ensure it is properly typed ARM: CNS3XXX: add UL suffix to VMALLOC_END to ensure it is properly typed ARM: i.MX53: Fix IOMUX type o's ARM i.MX dma: Fix burstsize settings mach-mx5: fix the I2C clock parents ARM: mxs/tx28: according to the TX28's datasheet D4-D7 are not used for MMC0 ARM i.MX23/28: platform-mxsfb: Add missing include of linux/dma-mapping.h ARM: mx53: Fix some interrupts marked as reserved. MXC: iomux-v3: correct NO_PAD_CTRL definition ... Fix up trivial conflict in arch/arm/mach-imx/mach-mx31_3ds.c
| * | ARM: msm: platsmp: determine number of CPU cores at boot timeJeff Ohlstein2011-07-21
| |/ | | | | | | | | | | | | | | | | | | | | Previously we just assumed there were CONFIG_NR_CPUS cpus present in the system. Instead, figure out the number of cpus from the MIDR register. Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org> [arnd: clarified patch title] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2011-07-24
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (237 commits) ARM: 7004/1: fix traps.h compile warnings ARM: 6998/2: kernel: use proper memory barriers for bitops ARM: 6997/1: ep93xx: increase NR_BANKS to 16 for support of 128MB RAM ARM: Fix build errors caused by adding generic macros ARM: CPU hotplug: ensure we migrate all IRQs off a downed CPU ARM: CPU hotplug: pass in proper affinity mask on IRQ migration ARM: GIC: avoid routing interrupts to offline CPUs ARM: CPU hotplug: fix abuse of irqdesc->node ARM: 6981/2: mmci: adjust calculation of f_min ARM: 7000/1: LPAE: Use long long printk format for displaying the pud ARM: 6999/1: head, zImage: Always Enter the kernel in ARM state ARM: btc: avoid invalidating the branch target cache on kernel TLB maintanence ARM: ARM_DMA_ZONE_SIZE is no more ARM: mach-shark: move ARM_DMA_ZONE_SIZE to mdesc->dma_zone_size ARM: mach-sa1100: move ARM_DMA_ZONE_SIZE to mdesc->dma_zone_size ARM: mach-realview: move from ARM_DMA_ZONE_SIZE to mdesc->dma_zone_size ARM: mach-pxa: move from ARM_DMA_ZONE_SIZE to mdesc->dma_zone_size ARM: mach-ixp4xx: move from ARM_DMA_ZONE_SIZE to mdesc->dma_zone_size ARM: mach-h720x: move from ARM_DMA_ZONE_SIZE to mdesc->dma_zone_size ARM: mach-davinci: move from ARM_DMA_ZONE_SIZE to mdesc->dma_zone_size ...
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| *-. \ Merge branches 'btc', 'dma', 'entry', 'fixes', 'linker-layout', 'misc', ↵Russell King2011-07-22
| |\ \ \ | | | |/ | | |/| | | | | 'mmci', 'suspend' and 'vfp' into for-next
| | | * ARM: 6993/1: platsmp: Allow secondary cpu hotplug with maxcpus=1Stephen Boyd2011-07-07
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an ARM system has multiple cpus in the same socket and the kernel is booted with maxcpus=1, secondary cpus are possible but not present due to how platform_smp_prepare_cpus() is called. Since most typical ARM processors don't actually support physical hotplug, initialize the present map to be equal to the possible map in generic ARM SMP code. Also, always call platform_smp_prepare_cpus() as long as max_cpus is non-zero (0 means no SMP) to allow platform code to do any SMP setup. After applying this patch it's possible to boot an ARM system with maxcpus=1 on the command line and then hotplug in secondary cpus via sysfs. This is more in line with how x86 does things. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: David Brown <davidb@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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*-. \ \ Merge branches 'amd/transparent-bridge' and 'core'Joerg Roedel2011-06-21
|\ \ \ \ | | |/ / | |/| / | |_|/ |/| | | | | | | | | | | Conflicts: arch/x86/include/asm/amd_iommu_types.h arch/x86/kernel/amd_iommu.c Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | * msm: iommu: move to drivers/iommu/Ohad Ben-Cohen2011-06-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This should ease finding similarities with different platforms, with the intention of solving problems once in a generic framework which everyone can use. Compile-tested for MSM8X60. Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Acked-by: David Brown <davidb@codeaurora.org> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| | * drivers: iommu: move to a dedicated folderOhad Ben-Cohen2011-06-14
| |/ | | | | | | | | | | | | | | | | | | | | | | | | Create a dedicated folder for iommu drivers, and move the base iommu implementation over there. Grouping the various iommu drivers in a single location will help finding similar problems shared by different platforms, so they could be solved once, in the iommu framework, instead of solved differently (or duplicated) in each driver. Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
* | msm: timer: Fix DGT rate on 8960 and 8660Stephen Boyd2011-06-20
| | | | | | | | | | | | | | The DGT runs at 27 MHz divided by 4 on 8660 and 8960. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
* | msm: timer: compensate for timer shift in msm_read_timer_countJeff Ohlstein2011-06-17
| | | | | | | | | | | | | | | | | | | | | | Some msm targets have timers whose lower bits are unreliable. So, we present our timers as lower frequency than they actually are, and ignore the bottom 5 bits on such targets. This compensation was erroneously removed from the msm_read_timer_count function, so restore it. This was broken by 94790ec25 "msm: timer: SMP timer support for msm". Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
* | msm: timer: Fix SMP build errorStephen Boyd2011-05-31
|/ | | | | | | | | | | | Fix build breakage on SMP=y builds due to 0f7b332 (ARM: consolidate SMP cross call implementation, 2011-04-03) arch/arm/mach-msm/timer.c: In function 'local_timer_setup': arch/arm/mach-msm/timer.c:295: error: implicit declaration of function 'gic_enable_ppi' Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
* Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2011-05-23
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (137 commits) ARM: bcmring: convert to use sp804 clockevents ARM: bcmring: convert to sp804 clocksource ARM: 6912/1: bcmring: Add clkdev table in init_early clockevents: ARM sp804: obtain sp804 timer rate via clks clockevents: ARM sp804: allow clockevent name to be specified clocksource: ARM sp804: obtain sp804 timer rate via clks clocksource: ARM sp804: allow clocksource name to be specified clocksource: convert OMAP1 to 32-bit down counting clocksource clocksource: convert MXS timrotv2 to 32-bit down counting clocksource clocksource: convert SPEAr platforms 16-bit up counting clocksource clocksource: convert Integrator/AP 16-bit down counting clocksource clocksource: convert W90x900 24-bit down counting clocksource clocksource: convert ARM 32-bit down counting clocksources clocksource: convert ARM 32-bit up counting clocksources clocksource: add common mmio clocksource ARM: update sa1100 to reflect PXA updates ARM: omap1: convert to using readl/writel instead of volatile struct ARM: omap1: delete useless interrupt handler ARM: s5p: consolidate selection of timer register ARM: 6939/1: fix missing 'cpu_relax()' declaration ...
| * Merge branch 'devel-stable' into for-linusRussell King2011-05-23
| |\ | | | | | | | | | | | | | | | Conflicts: arch/arm/Kconfig arch/arm/mach-ns9xxx/include/mach/uncompress.h
| | * ARM: msm: update GPIO chained IRQ handler to use entry/exit functionsWill Deacon2011-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the MSM gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. Tested-and-reviewed-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Acked-by: David Brown <davidb@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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| *-. \ Merge branches 'consolidate-clksrc', 'consolidate-flash', ↵Russell King2011-05-23
| |\ \ \ | | |_|/ | |/| | | | | | 'consolidate-generic', 'consolidate-smp', 'consolidate-stmp' and 'consolidate-zones' into consolidate
| | | * ARM: consolidate SMP cross call implementationRussell King2011-05-23
| | |/ | | | | | | | | | | | | | | | | | | | | | Rather than having each platform class provide a mach/smp.h header for smp_cross_call(), arrange for them to register the function with the core ARM SMP code instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | / treewide: fix a few typos in commentsJustin P. Mattock2011-05-10
|/ / | | | | | | | | | | | | | | | | | | - kenrel -> kernel - whetehr -> whether - ttt -> tt - sss -> ss Signed-off-by: Justin P. Mattock <justinmattock@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* | Merge branch 'for-39-rc4' of git://codeaurora.org/quic/kernel/davidb/linux-msmLinus Torvalds2011-04-18
|\ \ | | | | | | | | | | | | | | | * 'for-39-rc4' of git://codeaurora.org/quic/kernel/davidb/linux-msm: msm: timer: fix missing return value msm: Remove extraneous ffa device check
| * | msm: timer: fix missing return valueDavid Brown2011-03-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change af90f10d38 "ARM: 6759/1: smp: Select local timers vs broadcast timer support runtime" missed a return statement, causing a compile warning: arch/arm/mach-msm/timer.c:272: warning: 'return' with no value, in function returning non-void Trivially return 0 for success when running on cpu 0 (to match the comment and previous behavior). Signed-off-by: David Brown <davidb@codeaurora.org>
| * | msm: Remove extraneous ffa device checkDavid Brown2011-03-31
| |/ | | | | | | | | | | | | | | | | | | | | The qsd8x50 board file contains a few references to machine_is_... macros that are otherwise unused, and contain no machine definition. The recent purge of unused machine definitions breaks the compilation of this target. Since the machine cannot ever be used, just remove the bogus checks. Signed-off-by: David Brown <davidb@codeaurora.org>
* / Fix common misspellingsLucas De Marchi2011-03-31
|/ | | | | | Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
* arm: Fold irq_set_chip/irq_set_handlerThomas Gleixner2011-03-29
| | | | | | Use irq_set_chip_and_handler() instead. Converted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* arm: Cleanup the irq namespaceThomas Gleixner2011-03-29
| | | | | | Convert to the new function names. Automated with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* arm: msm: Use proper irq accessor functionsThomas Gleixner2011-03-29
| | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* arm: msm: Convert to new irq chip functionsThomas Gleixner2011-03-29
| | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2011-03-23
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (35 commits) ARM: Update (and cut down) mach-types ARM: 6771/1: vexpress: add support for multiple core tiles ARM: 6797/1: hw_breakpoint: Fix newlines in WARNings ARM: 6751/1: vexpress: select applicable errata workarounds in Kconfig ARM: 6753/1: omap4: Enable ARM local timers with OMAP4430 es1.0 exception ARM: 6759/1: smp: Select local timers vs broadcast timer support runtime ARM: pgtable: add pud-level code ARM: 6673/1: LPAE: use phys_addr_t instead of unsigned long for start of membanks ARM: Use long long format when printing meminfo physical addresses ARM: integrator: add Integrator/CP sched_clock support ARM: realview/vexpress: consolidate SMP bringup code ARM: realview/vexpress: consolidate localtimer support ARM: integrator/versatile: consolidate FPGA IRQ handling code ARM: rationalize versatile family Kconfig/Makefile ARM: realview: remove old AMBA device DMA definitions ARM: versatile: remove old AMBA device DMA definitions ARM: vexpress: use new init_early for clock tree and sched_clock init ARM: realview: use new init_early for clock tree and sched_clock init ARM: versatile: use new init_early for clock tree and sched_clock init ARM: integrator: use new init_early for clock tree init ...
| *---. Merge branches 'fixes', 'pgt-next' and 'versatile' into develRussell King2011-03-20
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| | | | * ARM: 6759/1: smp: Select local timers vs broadcast timer support runtimeSantosh Shilimkar2011-02-23
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code support of dummy timers in absence of local timer is compile time. This is an attempt to convert it to runtime so that on few SOC version if the local timers aren't supported kernel can switch to dummy timers. OMAP4430 ES1.0 does suffer from this limitation. This patch should not have any functional impact on affected files. Cc: Daniel Walker <dwalker@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Colin Cross <ccross@android.com> Cc: Erik Gilling <konkers@android.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: David Brown <davidb@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | Merge remote branch 'rmk/for-linus' into for-linusDavid Brown2011-03-17
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * rmk/for-linus: (1557 commits) ARM: 6806/1: irq: introduce entry and exit functions for chained handlers ARM: 6781/1: Thumb-2: Work around buggy Thumb-2 short branch relocations in gas ARM: 6747/1: P2V: Thumb2 support ARM: 6798/1: aout-core: zero thread debug registers in a.out core dump ARM: 6796/1: Footbridge: Fix I/O mappings for NOMMU mode ARM: 6784/1: errata: no automatic Store Buffer drain on Cortex-A9 ARM: 6772/1: errata: possible fault MMU translations following an ASID switch ARM: 6776/1: mach-ux500: activate fix for errata 753970 ARM: 6794/1: SPEAr: Append UL to device address macros. ARM: 6793/1: SPEAr: Remove unused *_SIZE macros from spear*.h files ARM: 6792/1: SPEAr: Replace SIZE macro's with SZ_4K macros ARM: 6791/1: SPEAr3xx: Declare device structures after shirq code ARM: 6790/1: SPEAr: Clock Framework: Rename usbd clock and align apb_clk entry ARM: 6789/1: SPEAr3xx: Rename sdio to sdhci ARM: 6788/1: SPEAr: Include mach/hardware.h instead of mach/spear.h ARM: 6787/1: SPEAr: Reorder #includes in .h & .c files. ARM: 6681/1: SPEAr: add debugfs support to clk API ARM: 6703/1: SPEAr: update clk API support ARM: 6679/1: SPEAr: make clk API functions more generic ARM: 6737/1: SPEAr: formalized timer support ... Conflicts: arch/arm/mach-msm/board-msm7x27.c arch/arm/mach-msm/board-msm7x30.c arch/arm/mach-msm/board-qsd8x50.c arch/arm/mach-msm/board-sapphire.c arch/arm/mach-msm/include/mach/memory.h
| * | | ARM: P2V: avoid initializers and assembly using PHYS_OFFSETRussell King2011-02-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As PHYS_OFFSET will be becoming a variable, we can't have it used in initializers nor assembly code. Replace those in generic code with a run-time initialization. Replace those in platform code using the individual platform specific PLAT_PHYS_OFFSET. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Acked-by: David Brown <davidb@codeaurora.org> Acked-by: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: P2V: separate PHYS_OFFSET from platform definitionsRussell King2011-02-17
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This uncouple PHYS_OFFSET from the platform definitions, thereby facilitating run-time computation of the physical memory offset. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Magnus Damm <damm@opensource.se> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Wan ZongShun <mcuos.com@gmail.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Acked-by: Eric Miao <eric.y.miao@gmail.com> Acked-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | msm: scm: Check for interruption immediatelyStephen Boyd2011-03-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | When we're interrupted on the secure side, we should just issue another smc instruction again instead of replaying the arguments to smc. Fix it. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
* | | msm: scm: Fix improper register assignmentStephen Boyd2011-03-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Assign the registers used in the inline assembly immediately before the inline assembly block. This ensures the compiler doesn't optimize away dead register assignments when it shouldn't. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: David Brown <davidb@codeaurora.org>
* | | msm: scm: Mark inline asm as volatileStephen Boyd2011-03-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | We don't want the compiler to remove these asm statements or reorder them in any way. Mark them as volatile to be sure. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Brown <davidb@codeaurora.org>
* | | msm: iommu: Enable HTW L2 redirection on MSM8960Stepan Moskovchenko2011-03-08
| | | | | | | | | | | | | | | | | | | | | | | | Allow the MSM8960 IOMMU to access its page tables directly through the L2 cache. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
* | | msm: iommu: Don't read from write-only registersStepan Moskovchenko2011-03-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't read from V2Pxx command registers when doing iova-to-phys operations. These registers are write-only and reading the value before modifying the VA bits is unnecessary. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
* | | msm: iommu: Remove dependency on IDRStepan Moskovchenko2011-03-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the depencency on the IOMMU IDR register, as it may not be accessible depending on the security configuraton. This involves moving the NCB field of IDR into the platform data. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
* | | msm: iommu: Use ASID tagging instead of VMID taggingStepan Moskovchenko2011-03-08
| | | | | | | | | | | | | | | | | | | | | | | | Use ASID tags in the TLB instead of VMID tags in preparation for changes to the secure environment. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
* | | msm: iommu: Rework clock logic and add IOMMU bus clock controlStepan Moskovchenko2011-03-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up the clock control code in the probe calls, and add support for controlling the clock for the IOMMU bus interconnect. With the (proper) clock driver in place, the clock control logic in the probe function can be made much cleaner since it does not have to deal with the placeholder driver anymore. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Reviewed-by: Trilok Soni <tsoni@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
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