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* ARM: imx: enable suspend for imx6slShawn Guo2013-10-20
| | | | | | | | | | The imx6sl low power mode implementation inherits imx6q/dl one, and pm-imx6q.c can just work for imx6sl with some minor updates. Let's enable imx6sl suspend support by reusing pm-imx6q.c and use cpu_is_imxXX() to handle the those minor differences between imx6sl and imx6q/dl. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: ensure dsm_request signal is not asserted when setting LPMShawn Guo2013-10-20
| | | | | | | | | | | | | | | | | | | | | | | | | There is a defect in imx6 LPM design. When SW tries to enter low power mode with following sequence, the chip will enter low power mode before A9 CPU execute WFI instruction: 1. Set CCM_CLPCR[1:0] to 2'b00; 2. ARM CPU enters WFI; 3. ARM CPU wakeup from an interrupt event, which is masked by GPC or not visible to GPC, such as interrupt from local timer; 4. Set CCM_CLPCR[1:0] to 2'b01 or 2'b10; 5. ARM CPU execute WFI. Before the last step, the chip will enter WAIT mode if CCM_CLPCR[1:0] is set to 2'b01, or enter STOP mode if CCM_CLPCR[1:0] is set to 2'b10. The patch implements a recommended workaround for this issue. 1. SW triggers irq #32(IOMUX) to be always pending manually by setting IOMUX_GPR1_GINT bit; 2. SW should then unmask it in GPC before setting CCM LPM; 3. SW should mask it right after CCM LPM is set (bit0-1 of CCM_CLPCR). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: call WB and RBC configuration from imx6q_pm_enter()Shawn Guo2013-10-20
| | | | | | | | | | | | | | | | | | | | The WB and RBC configuration calls are currently made from imx6q_set_lpm() for WAIT_CLOCKED and WAIT_UNCLOCKED mode with a simple state tracking. This becomes unnecessary since we can make the calls from imx6q_pm_enter() directly now for suspend. More importantly, the current call of imx6q_enable_wb() from imx6q_set_lpm() is buggy. The CLPCR register bits configured by imx6q_enable_wb() will get lost, because imx6q_set_lpm() caches the same register and write it back at the end of the function. That's why the imx6dl suspend/resume does not work currently - the wakeup from suspend triggers a reset on imx6dl. Moves the WB and RBC calls into imx6q_pm_enter() to save the state tracking and fixes above bug, so that suspend/resume can start working on imx6dl. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6q: move low-power code out of clock driverShawn Guo2013-10-20
| | | | | | | | | | | | | | The LPM (Low Power Mode) code that currently sits in imx6q clock driver will be reused by imx6sl. Let's move it into pm-imx6q.c, so that we can keep clock driver SoC specific and reuse pm-imx6q.c on imx6sl. In order to avoid adding another ioremap for CCM block, imx6q_pm_set_ccm_base() is created to let clock driver set up ccm_base for pm code. During the move, the unused CCGR macros get removed. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: enable anatop suspend/resumeAnson Huang2013-04-12
| | | | | | | | | | | | | | Anatop module have sereval configurations for user to reduce the power consumption in suspend, provide suspend/resume interface for further use and enable fet_odrive to reduce CORE LDO leakage during suspend. As we have a common anatop file, remove all the operations of anatop module in other files, use anatop interfaces to do that. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: mach-imx: move early resume code out of the .data sectionNicolas Pitre2013-03-03
| | | | | | | | | | | | | | | | Building the kernel with allyesconfig fails because the i.mx early resume code located in the .data section is unable to fixup the bl relocation as the branch target gets too far away. The idea of having code in the .data section allows for easy access to nearby data using relative addressing while the MMU is off. However it is probably best to move the code back to the .text section where it belongs and fixup the data access instead. This solves the bl reloc issue (at least until this becomes a general problem) and simplifies the code as well. Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: correct low-power mode settingShawn Guo2013-01-14
| | | | | | | | | | | The hardware reset value of bit CCM_CLPCR_LPM enables WAIT mode (WAIT_UNCLOCKED) by default. However this is undesirable because WAIT mode should only be enabled when there is a driver managing ARM clock gating. Correct the initial power mode to WAIT_CLOCKED (disable WAIT mode). While at it, the power mode after resuming is also set back to WAIT_CLOCKED from STOP_POWER_OFF. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: include hardware.h rather than mach/hardware.hShawn Guo2012-10-14
| | | | | | | | | | | It moves a bunch of header files included in hardware.h and itself from mach-imx/include/mach to mach-imx, and updates users to include hardware.h rather than mach/hardware.h. The files in mach-imx/devices will need to include "../hardware.h". Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
* ARM: imx: include common.h rather than mach/common.hShawn Guo2012-10-14
| | | | | | | | | | | | Rename mach-imx/include/mach/common.h to mach-imx/common.h and update all users to include common.h rather than mach/common.h. It also removes an unneeded inclusion to common.h in mach-imx/devices/devices.c. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
* ARM: imx6q: resume PL310 only when CACHE_L2X0 definedEric Miao2011-12-25
| | | | | | | | | Original patch from Lothar Waßmann, this patch fixes a building error when CONFIG_CACHE_L2X0 is not defined. Cc: Lothar Waßmann <lw@karo-electronics.de> Signed-off-by: Eric Miao <eric.miao@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* arm/imx6q: add suspend/resume supportShawn Guo2011-10-31
It adds suspend/resume support for imx6q. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>