aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/kvm
Commit message (Collapse)AuthorAge
...
| * | | | ARM: KVM: allow HYP mappings to be at an offset from kernel mappingsMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arm64 cannot represent the kernel VAs in HYP mode, because of the lack of TTBR1 at EL2. A way to cope with this situation is to have HYP VAs to be an offset from the kernel VAs. Introduce macros to convert a kernel VA to a HYP VA, make the HYP mapping functions use these conversion macros. Also change the documentation to reflect the existence of the offset. On ARM, where we can have an identity mapping between kernel and HYP, the macros are without any effect. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * | | | ARM: KVM: use kvm_kernel_vfp_t as an abstract type for VFP containersMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to keep the VFP allocation code common, use an abstract type for the VFP containers. Maps onto struct vfp_hard_struct on ARM. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * | | | ARM: KVM: move hyp init to kvm_host.hMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the split of the pgd_ptr an implementation specific thing by moving the init call to an inline function. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * | | | ARM: KVM: abstract most MMU operationsMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move low level MMU-related operations to kvm_mmu.h. This makes the MMU code reusable by the arm64 port. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * | | | KVM: ARM: Reintroduce trace_kvm_hvcChristoffer Dall2013-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This one got lost in the move to handle_exit, so let's reintroduce it using an accessor to the immediate value field like the other ones. Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
| * | | | ARM: KVM: move exit handler selection to a separate fileMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The exit handler selection code cannot be shared with arm64 (two different modes, more exception classes...). Move it to a separate file (handle_exit.c). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
| * | | | ARM: KVM: move kvm_condition_valid to emulate.cMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is really hardware emulation, and as such it better be with its little friends. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * | | | ARM: KVM: abstract HSR_EC_IABT awayMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * | | | ARM: KVM: abstract fault decoding awayMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * | | | ARM: KVM: abstract exception class decoding awayMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * | | | ARM: KVM: abstract IL decoding awayMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
| * | | | ARM: KVM: abstract SAS decoding awayMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
| * | | | ARM: KVM: abstract S1TW abort detection awayMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
| * | | | ARM: KVM: abstract (and fix) external abort detection awayMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bit 8 is cache maintenance, bit 9 is external abort. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
| * | | | ARM: KVM: abstract HSR_SRT_{MASK,SHIFT} awayMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * | | | ARM: KVM: abstract HSR_SSE awayMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
| * | | | ARM: KVM: abstract HSR_WNR awayMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
| * | | | ARM: KVM: abstract HSR_ISV awayMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
| * | | | ARM: KVM: abstract fault register accessesMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of directly accessing the fault registers, use proper accessors so the core code can be shared. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * | | | ARM: KVM: convert GP registers from u32 to unsigned longMarc Zyngier2013-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 32bit ARM, unsigned long is guaranteed to be a 32bit quantity. On 64bit ARM, it is a 64bit quantity. In order to be able to share code between the two architectures, convert the registers to be unsigned long, so the core code can be oblivious of the change. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * | | | KVM: ARM: Fix wrong address in commentJonghwan Choi2013-03-06
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | hyp_hvc vector offset is 0x14 and hyp_svc vector offset is 0x8. Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com> Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
* | | | Merge branch 'for-linus' of ↵Linus Torvalds2013-04-30
|\ \ \ \ | |_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial Pull trivial tree updates from Jiri Kosina: "Usual stuff, mostly comment fixes, typo fixes, printk fixes and small code cleanups" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (45 commits) mm: Convert print_symbol to %pSR gfs2: Convert print_symbol to %pSR m32r: Convert print_symbol to %pSR iostats.txt: add easy-to-find description for field 6 x86 cmpxchg.h: fix wrong comment treewide: Fix typo in printk and comments doc: devicetree: Fix various typos docbook: fix 8250 naming in device-drivers pata_pdc2027x: Fix compiler warning treewide: Fix typo in printks mei: Fix comments in drivers/misc/mei treewide: Fix typos in kernel messages pm44xx: Fix comment for "CONFIG_CPU_IDLE" doc: Fix typo "CONFIG_CGROUP_CGROUP_MEMCG_SWAP" mmzone: correct "pags" to "pages" in comment. kernel-parameters: remove outdated 'noresidual' parameter Remove spurious _H suffixes from ifdef comments sound: Remove stray pluses from Kconfig file radio-shark: Fix printk "CONFIG_LED_CLASS" doc: put proper reference to CONFIG_MODULE_SIG_ENFORCE ...
| * | | treewide: Fix typo in printk and commentsMasanari Iida2013-04-24
| |/ / | | | | | | | | | | | | | | | | | | Fix typo in printk and comments within various drivers. Signed-off-by: Masanari Iida <standby24x7@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* | | ARM: KVM: fix unbalanced get_cpu() in access_dcswMarc Zyngier2013-04-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the very unlikely event where a guest would be foolish enough to *read* from a write-only cache maintainance register, we end up with preemption disabled, due to a misplaced get_cpu(). Just move the "is_write" test outside of the critical section. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | ARM: KVM: fix KVM_CAP_ARM_SET_DEVICE_ADDR reportingMarc Zyngier2013-04-16
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 3401d54696f9 (KVM: ARM: Introduce KVM_ARM_SET_DEVICE_ADDR ioctl) added support for the KVM_CAP_ARM_SET_DEVICE_ADDR capability, but failed to add a break in the relevant case statement, returning the number of CPUs instead. Luckilly enough, the CONFIG_NR_CPUS=0 patch hasn't been merged yet (https://lkml.org/lkml/diff/2012/3/31/131/1), so the bug wasn't noticed. Just give it a break! Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
* | Merge branch 'kvm-arm/vgic-fixes' of ↵Russell King2013-03-22
|\ \ | |/ |/| | | git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into fixes
| * ARM: KVM: vgic: take distributor lock on sync_hwstate pathMarc Zyngier2013-02-22
| | | | | | | | | | | | | | | | | | | | | | Now that the maintenance interrupt handling is actually out of the handler itself, the code becomes quite racy as we can get preempted while we process the state. Wrapping this code around the distributor lock ensures that we're not preempted and relatively race-free. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: KVM: vgic: force EOIed LRs to the empty stateMarc Zyngier2013-02-22
| | | | | | | | | | | | | | | | | | | | The VGIC doesn't guarantee that an EOIed LR that has been configured to generate a maintenance interrupt will appear as empty. While the code recovers from this situation, it is better to clean the LR and flag it as empty so it can be quickly recycled. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | ARM: KVM: fix compilation after removal of user_alloc from struct ↵Marc Zyngier2013-02-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | kvm_memory_slot Commit 7a905b1 (KVM: Remove user_alloc from struct kvm_memory_slot) broke KVM/ARM by removing the user_alloc field from a public structure. As we only used this field to alert the user that we didn't support this operation mode, there is no harm in discarding this bit of code without any remorse. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Gleb Natapov <gleb@redhat.com>
* | ARM: KVM: fix kvm_arch_{prepare,commit}_memory_regionMarc Zyngier2013-02-25
|/ | | | | | | | | | | Commit f82a8cfe9 (KVM: struct kvm_memory_slot.user_alloc -> bool) broke the ARM KVM port by changing the prototype of two global functions. Apply the same change to fix the compilation breakage. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Gleb Natapov <gleb@redhat.com>
* ARM: KVM: arch_timers: Wire the init code and config optionMarc Zyngier2013-02-11
| | | | | | | | | It is now possible to select CONFIG_KVM_ARM_TIMER to enable the KVM architected timer support. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* ARM: KVM: arch_timers: Add timer world switchMarc Zyngier2013-02-11
| | | | | | | | | | Do the necessary save/restore dance for the timers in the world switch code. In the process, allow the guest to read the physical counter, which is useful for its own clock_event_device. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* ARM: KVM: arch_timers: Add guest timer core supportMarc Zyngier2013-02-11
| | | | | | | | | | | | | | | | Add some the architected timer related infrastructure, and support timer interrupt injection, which can happen as a resultof three possible events: - The virtual timer interrupt has fired while we were still executing the guest - The timer interrupt hasn't fired, but it expired while we were doing the world switch - A hrtimer we programmed earlier has fired Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* ARM: KVM: Add VGIC configuration optionMarc Zyngier2013-02-11
| | | | | | | | It is now possible to select the VGIC configuration option. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* ARM: KVM: VGIC initialisation codeMarc Zyngier2013-02-11
| | | | | | | | | | | | | | | | Add the init code for the hypervisor, the virtual machine, and the virtual CPUs. An interrupt handler is also wired to allow the VGIC maintenance interrupts, used to deal with level triggered interrupts and LR underflows. A CPU hotplug notifier is registered to disable/enable the interrupt as requested. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* ARM: KVM: VGIC control interface world switchMarc Zyngier2013-02-11
| | | | | | | | Enable the VGIC control interface to be save-restored on world switch. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* ARM: KVM: VGIC interrupt injectionMarc Zyngier2013-02-11
| | | | | | | | | Plug the interrupt injection code. Interrupts can now be generated from user space. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* ARM: KVM: vgic: retire queued, disabled interruptsMarc Zyngier2013-02-11
| | | | | | | | | | | | | | An interrupt may have been disabled after being made pending on the CPU interface (the classic case is a timer running while we're rebooting the guest - the interrupt would kick as soon as the CPU interface gets enabled, with deadly consequences). The solution is to examine already active LRs, and check the interrupt is still enabled. If not, just retire it. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* ARM: KVM: VGIC virtual CPU interface managementMarc Zyngier2013-02-11
| | | | | | | | | | Add VGIC virtual CPU interface code, picking pending interrupts from the distributor and stashing them in the VGIC control interface list registers. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* ARM: KVM: VGIC distributor handlingMarc Zyngier2013-02-11
| | | | | | | | | Add the GIC distributor emulation code. A number of the GIC features are simply ignored as they are not required to boot a Linux guest. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* ARM: KVM: VGIC accept vcpu and dist base addresses from user spaceChristoffer Dall2013-02-11
| | | | | | | | | | | | User space defines the model to emulate to a guest and should therefore decide which addresses are used for both the virtual CPU interface directly mapped in the guest physical address space and for the emulated distributor interface, which is mapped in software by the in-kernel VGIC support. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* ARM: KVM: Initial VGIC infrastructure codeMarc Zyngier2013-02-11
| | | | | | | | | Wire the basic framework code for VGIC support and the initial in-kernel MMIO support code for the VGIC, used for the distributor emulation. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* ARM: KVM: Keep track of currently running vcpusMarc Zyngier2013-02-11
| | | | | | | | | | | | | | | | When an interrupt occurs for the guest, it is sometimes necessary to find out which vcpu was running at that point. Keep track of which vcpu is being run in kvm_arch_vcpu_ioctl_run(), and allow the data to be retrieved using either: - kvm_arm_get_running_vcpu(): returns the vcpu running at this point on the current CPU. Can only be used in a non-preemptible context. - kvm_arm_get_running_vcpus(): returns the per-CPU variable holding the running vcpus, usable for per-CPU interrupts. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* KVM: ARM: Introduce KVM_ARM_SET_DEVICE_ADDR ioctlChristoffer Dall2013-02-11
| | | | | | | | | | | | | | | | On ARM some bits are specific to the model being emulated for the guest and user space needs a way to tell the kernel about those bits. An example is mmio device base addresses, where KVM must know the base address for a given device to properly emulate mmio accesses within a certain address range or directly map a device with virtualiation extensions into the guest address space. We make this API ARM-specific as we haven't yet reached a consensus for a generic API for all KVM architectures that will allow us to do something like this. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* KVM: ARM: Power State Coordination Interface implementationMarc Zyngier2013-01-23
| | | | | | | | | | | | | | | | Implement the PSCI specification (ARM DEN 0022A) to control virtual CPUs being "powered" on or off. PSCI/KVM is detected using the KVM_CAP_ARM_PSCI capability. A virtual CPU can now be initialized in a "powered off" state, using the KVM_ARM_VCPU_POWER_OFF feature flag. The guest can use either SMC or HVC to execute a PSCI function. Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
* KVM: ARM: Handle I/O abortsChristoffer Dall2013-01-23
| | | | | | | | | | | | | | | | | | | | | When the guest accesses I/O memory this will create data abort exceptions and they are handled by decoding the HSR information (physical address, read/write, length, register) and forwarding reads and writes to QEMU which performs the device emulation. Certain classes of load/store operations do not support the syndrome information provided in the HSR. We don't support decoding these (patches are available elsewhere), so we report an error to user space in this case. This requires changing the general flow somewhat since new calls to run the VCPU must check if there's a pending MMIO load and perform the write after userspace has made the data available. Reviewed-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
* KVM: ARM: Handle guest faults in KVMChristoffer Dall2013-01-23
| | | | | | | | | | | | | | | | | | | Handles the guest faults in KVM by mapping in corresponding user pages in the 2nd stage page tables. We invalidate the instruction cache by MVA whenever we map a page to the guest (no, we cannot only do it when we have an iabt because the guest may happily read/write a page before hitting the icache) if the hardware uses VIPT or PIPT. In the latter case, we can invalidate only that physical page. In the first case, all bets are off and we simply must invalidate the whole affair. Not that VIVT icaches are tagged with vmids, and we are out of the woods on that one. Alexander Graf was nice enough to remind us of this massive pain. Reviewed-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
* KVM: ARM: VFP userspace interfaceRusty Russell2013-01-23
| | | | | | | | | We use space #18 for floating point regs. Reviewed-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
* KVM: ARM: Demux CCSIDR in the userspace APIChristoffer Dall2013-01-23
| | | | | | | | | | | | | | | | | | | The Cache Size Selection Register (CSSELR) selects the current Cache Size ID Register (CCSIDR). You write which cache you are interested in to CSSELR, and read the information out of CCSIDR. Which cache numbers are valid is known by reading the Cache Level ID Register (CLIDR). To export this state to userspace, we add a KVM_REG_ARM_DEMUX numberspace (17), which uses 8 bits to represent which register is being demultiplexed (0 for CCSIDR), and the lower 8 bits to represent this demultiplexing (in our case, the CSSELR value, which is 4 bits). Reviewed-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
* KVM: ARM: User space API for getting/setting co-proc registersChristoffer Dall2013-01-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following three ioctls are implemented: - KVM_GET_REG_LIST - KVM_GET_ONE_REG - KVM_SET_ONE_REG Now we have a table for all the cp15 registers, we can drive a generic API. The register IDs carry the following encoding: ARM registers are mapped using the lower 32 bits. The upper 16 of that is the register group type, or coprocessor number: ARM 32-bit CP15 registers have the following id bit patterns: 0x4002 0000 000F <zero:1> <crn:4> <crm:4> <opc1:4> <opc2:3> ARM 64-bit CP15 registers have the following id bit patterns: 0x4003 0000 000F <zero:1> <zero:4> <crm:4> <opc1:4> <zero:3> For futureproofing, we need to tell QEMU about the CP15 registers the host lets the guest access. It will need this information to restore a current guest on a future CPU or perhaps a future KVM which allow some of these to be changed. We use a separate table for these, as they're only for the userspace API. Reviewed-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Christoffer Dall <c.dall@virtualopensystems.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-09 00:08:19 -0400