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* [ARM] CONFIG_CPU_MPCORE -> CONFIG_CPU_32v6KRussell King2006-02-22
| | | | | | | CONFIG_CPU_MPCORE has never been a configuration symbol - it should be CONFIG_CPU_32v6K. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3310/1: add a comment about the possible __kuser_cmpxchg transient falseNicolas Pitre2006-02-08
| | | | | | | | | | | | | | | negative Patch from Nicolas Pitre The pre ARMv5 implementation can be aborted if an exception occurs in the middle of it. Because of that, the ARMv6 implementation doesn't re-attempt the operation on a failed strex either. Let's make this transient nature of such a false positive more explicit in the definition. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3309/1: disable the pre-ARMv5 NPTL kernel helper in the non MMU caseNicolas Pitre2006-02-08
| | | | | | | | | | | | | | | | | | | Patch from Nicolas Pitre The cmpxchg emulation on pre-ARMv5 relies on user code executed from a kernel address. If the operation cannot complete atomically, it is aborted from the usr_entry macro by clearing the Z flag. This clearing of the Z flag is done whenever the user pc is above TASK_SIZE. However this "pc >= TASK_SIZE" test cannot work in the non MMU case. Worse: the current code will corrupt the Z flag on every entry to the kernel. Let's disable it in the non MMU case for now. Using NPTL on non MMU targets needs to be worked out anyway. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3271/1: ARM EABI: fix calling of cmpxchg syscall emulationNicolas Pitre2006-01-18
| | | | | | | | | | | Patch from Nicolas Pitre This is kernel provided user space code. Since a syscall is used, it has to be updated to work with EABI. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3102/1: ARM EABI: stack pointer must be 64-bit aligned after a CPU ↵Nicolas Pitre2006-01-14
| | | | | | | | | | | | | | | | | | | | exception Patch from Nicolas Pitre The ARM EABI says that the stack pointer has to be 64-bit aligned for reasons already mentioned in patch #3101 when calling C functions. We therefore must verify and adjust sp accordingly when taking an exception from kernel mode since sp might not necessarily be 64-bit aligned if the exception occurs in the middle of a kernel function. If the exception occurs while in user mode then no sp fixup is needed as long as sizeof(struct pt_regs) as well as any additional syscall data stack space remain multiples of 8. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Support register switch in nommu modeHyok S. Choi2006-01-13
| | | | | | | This patch adds register switch support in nommu mode. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Cleanup ARM includesRussell King2006-01-03
| | | | | | | | | | | | | | | | arch/arm/kernel/entry-armv.S has contained a comment suggesting that asm/hardware.h and asm/arch/irqs.h should be moved into the asm/arch/entry-macro.S include. So move the includes to these two files as required. Add missing includes (asm/hardware.h, asm/io.h) to asm/arch/system.h includes which use those facilities, and remove asm/io.h from kernel/process.c. Remove other unnecessary includes from arch/arm/kernel, arch/arm/mm and arch/arm/mach-footbridge. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3210/1: add missing memory barrier helper for NPTL supportNicolas Pitre2005-12-19
| | | | | | | | | | | | | | | | | | Patch from Nicolas Pitre Strictly speaking, the NPTL kernel helpers are required for pre ARMv6 only. They are available on ARMv6+ as well for obvious compatibility reasons. However there are cases where extra memory barriers are needed when using an SMP ARMv6 machine but not on pre-ARMv6. This patch adds a memory barrier kernel helper that glibc can use as needed for pre-ARMv6 binaries to be forward compatible with an SMP kernel on ARMv6, as well as the necessary dmb instructions to the cmpxchg helper. Signed-off-by: Nicolas Pitre <nico@cam.org> Acked-by: Daniel Jacobowitz <dan@codesourcery.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM SMP] Add core ARM support for local timersRussell King2005-11-08
| | | | | | | Add infrastructure for supporting per-cpu local timers to update the profiling information and update system time accounting. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3115/1: small optimizations to exception vector entry codeNicolas Pitre2005-11-06
| | | | | | | | | | Patch from Nicolas Pitre Since we know the value of cpsr on entry, we can replace the bic+orr with a single eor. Also remove a possible result delay (at least on XScale). Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 3060/1: allow constants found in asm/memory.h to be used in asm codeNicolas Pitre2005-10-29
| | | | | | | | | | | | Patch from Nicolas Pitre This patch allows for assorted type of cleanups by letting assembly code use the same set of defines for constant values and avoid duplicated definitions that might not always be in sync, or that might simply be confusing due to the different names for the same thing. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix context switch with ARMv6 + TLSRussell King2005-09-23
| | | | | | | We accidentally corrupted the TLS value when clearing out the ARMv6 exclusive monitor. Avoid doing so. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM SMP] Clear the exclusive monitor on ARMv6 CPUs on context switchRussell King2005-08-10
| | | | | | | Ensure that the exclusive monitor is cleared on context switch with ARMv6 CPUs. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge with ../linux-2.6-smpRussell King2005-06-18
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| * [PATCH] ARM SMP: Fix vector entryRussell King2005-05-31
| | | | | | | | | | | | | | | | | | | | The current vector entry system does not allow for SMP. In order to work around this, we need to eliminate our reliance on the fixed save areas, which breaks the way we enable alignment traps. This patch changes the way we handle the save areas such that we can have one per CPU. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
| * [PATCH] ARM SMP: convert alignment enableRussell King2005-05-31
| | | | | | | | | | | | | | | | | | | | The current vector entry system does not allow for SMP. In order to work around this, we need to eliminate our reliance on the fixed save areas, which breaks the way we enable alignment traps. This patch makes the alignment trap enable code independent of the way we handle the save areas. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
| * [PATCH] ARM SMP: add IPI supportRussell King2005-05-21
| | | | | | | | | | | | | | Add support for inter-processor interrupts to the main IRQ handling code. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
| * [PATCH] ARM SMP: reallocate main IRQ handler code registersRussell King2005-05-21
| | | | | | | | | | | | | | By changing r9 -> r8 and r8 to 'tsk' (r9) we are able to remove one instruction from the preempt path. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
| * [PATCH] ARM SMP: consolidate main IRQ handler codeRussell King2005-05-21
| | | | | | | | Signed-off-by: Russell King <rmk@arm.linux.org.uk>
* | [PATCH] ARM: 2664/2: add support for atomic ops on pre-ARMv6 SMP systemsNicolas Pitre2005-06-08
|/ | | | | | | | | | Patch from Nicolas Pitre Not that there might be many of them on the planet, but at least RMK apparently has one. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2665/1: kill warnings in entry-armv.SNicolas Pitre2005-05-05
| | | | | | | Patch from Nicolas Pitre Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2663/1: straightify TLS register emulation a bit moreNicolas Pitre2005-05-05
| | | | | | | | | Patch from Nicolas Pitre This better express things, and should cover RMK's weird SMP toys. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: 2651/3: kernel helpers for NPTL supportNicolas Pitre2005-04-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch from Nicolas Pitre This patch entirely reworks the kernel assistance for NPTL on ARM. In particular this provides an efficient way to retrieve the TLS value and perform atomic operations without any instruction emulation nor special system call. This even allows for pre ARMv6 binaries to be forward compatible with SMP systems without any penalty. The problematic and performance critical operations are performed through segment of kernel provided user code reachable from user space at a fixed address in kernel memory. Those fixed entry points are within the vector page so we basically get it for free as no extra memory page is required and nothing else may be mapped at that location anyway. This is different from (but doesn't preclude) a full blown VDSO implementation, however a VDSO would prevent some assembly tricks with constants that allows for efficient branching to those code segments. And since those code segments only use a few cycles before returning to user code, the overhead of a VDSO far call would add a significant overhead to such minimalistic operations. The ARM_NR_set_tls syscall also changed number. This is done for two reasons: 1) this patch changes the way the TLS value was previously meant to be retrieved, therefore we ensure whatever library using the old way gets fixed (they only exist in private tree at the moment since the NPTL work is still progressing). 2) the previous number was allocated in a range causing an undefined instruction trap on kernels not supporting that syscall and it was determined that allocating it in a range returning -ENOSYS would be much nicer for libraries trying to determine if the feature is present or not. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [PATCH] ARM: make entry*.S includes more logicalRussell King2005-04-26
| | | | | | | Move common includes to entry-header, and file specific includes to the relevant file. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
* [PATCH] ARM: Remove SVC_MODE definitionRussell King2005-04-26
| | | | | | | SVC_MODE reflects the MODE_SVC definition in asm/ptrace.h. Use the asm/ptrace.h definition instead, and remove SVC_MODE. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
* [PATCH] ARM: Remove argument for disable_irq/enable_irqRussell King2005-04-26
| | | | | | | Since we do not require a register for these operations, we can remove this unnecessary argument. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
* [PATCH] ARM: remove some entry initialisation asm codeRussell King2005-04-26
| | | | | | Convert the trivial vector entry initialisation code to C code. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
* Linux-2.6.12-rc2v2.6.12-rc2Linus Torvalds2005-04-16
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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