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*-----. Merge branches 'at91', 'ep93xx', 'kexec', 'iop', 'lmb', 'nomadik', 'nuc', ↵Russell King2010-07-31
|\ \ \ \ | | | | | | | | | | | | | | | 'pl', 'spear' and 'versatile' into devel
| | | * | ARM: Convert platform reservations to use LMB rather than bootmemRussell King2010-07-27
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | ARM: initial LMB trialRussell King2010-07-27
| | | | | | | | | | | | | | | | | | | | | | | | | Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | ARM: Move platform memory reservations out of generic codeRussell King2010-07-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the platform specific bootmem memory reservations out of arch/arm/mm/mmu.c into their respective platform files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | ARM: Remove 'node' argument form arch_adjust_zones()Russell King2010-07-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we no longer support discontigmem, node is always zero, so remove this argument. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | ARM: Remove DISCONTIGMEM supportRussell King2010-07-16
| |_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | Everything should now be using sparsemem rather than discontigmem, so remove the code supporting discontigmem from ARM. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 6117/1: kdump: implement crash_setup_regs()Mika Westerberg2010-07-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement machine specific function crash_setup_regs() which is responsible for storing machine state when crash occured. Signed-off-by: Mika Westerberg <ext-mika.1.westerberg@nokia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 6207/1: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6Tony Lindgren2010-07-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TLS register is only available on ARM1136 r1p0 and later. Set HWCAP_TLS flags if hardware TLS is available and test for it if CONFIG_CPU_32v6K is not set for V6. Note that we set the TLS instruction in __kuser_get_tls dynamically as suggested by Jamie Lokier <jamie@shareable.org>. Also the __switch_to code is optimized out in most cases as suggested by Nicolas Pitre <nico@fluxnic.net>. Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 6203/1: Make VFPv3 usable on ARMv6Tony Lindgren2010-07-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MVFR0 and MVFR1 are only available starting with ARM1136 r1p0 release according to "B.5 VFP changes" in DDI0211F_arm1136_r1p0_trm.pdf. This is also when TLS register got added, so we can use HAS_TLS also to test for MVFR0 and MVFR1. Otherwise VFPFMRX and VFPFMXR access fails and we get: Internal error: Oops - undefined instruction: 0 [#1] PC is at no_old_VFP_process+0x8/0x3c LR is at __und_svc+0x48/0x80 ... Signed-off-by: Tony Lindgren <tony@atomide.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 6199/1: Add kprobe-based event tracerWill Deacon2010-07-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the HAVE_REGS_AND_STACK_ACCESS_API option for ARM which is required by the kprobe events tracer. Code based on the PowerPC port. Cc: Jean Pihet <jpihet@mvista.com> Tested-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | ARM: 6197/2: preliminary support for sparse IRQeric miao2010-07-09
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | So to allow NR_IRQS to be dynamic and platforms to specify the number of IRQs really needed. Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | ARM: 6212/1: atomic ops: add memory constraints to inline asmWill Deacon2010-07-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the 32-bit and 64-bit atomic operations on ARM do not include memory constraints in the inline assembly blocks. In the case of barrier-less operations [for example, atomic_add], this means that the compiler may constant fold values which have actually been modified by a call to an atomic operation. This issue can be observed in the atomic64_test routine in <kernel root>/lib/atomic64_test.c: 00000000 <test_atomic64>: 0: e1a0c00d mov ip, sp 4: e92dd830 push {r4, r5, fp, ip, lr, pc} 8: e24cb004 sub fp, ip, #4 c: e24dd008 sub sp, sp, #8 10: e24b3014 sub r3, fp, #20 14: e30d000d movw r0, #53261 ; 0xd00d 18: e3011337 movw r1, #4919 ; 0x1337 1c: e34c0001 movt r0, #49153 ; 0xc001 20: e34a1aa3 movt r1, #43683 ; 0xaaa3 24: e16300f8 strd r0, [r3, #-8]! 28: e30c0afe movw r0, #51966 ; 0xcafe 2c: e30b1eef movw r1, #48879 ; 0xbeef 30: e34d0eaf movt r0, #57007 ; 0xdeaf 34: e34d1ead movt r1, #57005 ; 0xdead 38: e1b34f9f ldrexd r4, [r3] 3c: e1a34f90 strexd r4, r0, [r3] 40: e3340000 teq r4, #0 44: 1afffffb bne 38 <test_atomic64+0x38> 48: e59f0004 ldr r0, [pc, #4] ; 54 <test_atomic64+0x54> 4c: e3a0101e mov r1, #30 50: ebfffffe bl 0 <__bug> 54: 00000000 .word 0x00000000 The atomic64_set (0x38-0x44) writes to the atomic64_t, but the compiler doesn't see this, assumes the test condition is always false and generates an unconditional branch to __bug. The rest of the test is optimised away. This patch adds suitable memory constraints to the atomic operations on ARM to ensure that the compiler is informed of the correct data hazards. We have to use the "Qo" constraints to avoid hitting the GCC anomaly described at http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44492 , where the compiler makes assumptions about the writeback in the addressing mode used by the inline assembly. These constraints forbid the use of auto{inc,dec} addressing modes, so it doesn't matter if we don't use the operand exactly once. Cc: stable@kernel.org Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | ARM: 6211/1: atomic ops: fix register constraints for atomic64_add_unlessWill Deacon2010-07-09
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The atomic64_add_unless function compares an atomic variable with a given value and, if they are not equal, adds another given value to the atomic variable. The function returns zero if the addition did not occur and non-zero otherwise. On ARM, the return value is initialised to 1 in C code. Inline assembly code then performs the atomic64_add_unless operation, setting the return value to 0 iff the addition does not occur. This means that when the addition *does* occur, the value of ret must be preserved across the inline assembly and therefore requires a "+r" constraint rather than the current one of "=&r". Thanks to Nicolas Pitre for helping to spot this. Cc: stable@kernel.org Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge branch 'fix' of ↵Russell King2010-07-01
|\ \ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
| * | [ARM] pxa: fix incorrect gpio type in udc_pxa2xx.hSteve Bennett2010-06-13
| |/ | | | | | | | | | | | | | | gpio must be int, not u16, otherwise -1 isn't recognised by gpio_is_valid(). Signed-off-by: Steve Bennett <steveb@workware.net.au> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* / ARM: 6194/1: change definition of cpu_relax() for ARM11MPCoreWill Deacon2010-07-01
|/ | | | | | | | | | | | | | | | | | | | | | Linux expects that if a CPU modifies a memory location, then that modification will eventually become visible to other CPUs in the system. On an ARM11MPCore processor, loads are prioritised over stores so it is possible for a store operation to be postponed if a polling loop immediately follows it. If the variable being polled indirectly depends on the outstanding store [for example, another CPU may be polling the variable that is pending modification] then there is the potential for deadlock if interrupts are disabled. This deadlock occurs in the KGDB testsuire when executing on an SMP ARM11MPCore configuration. This patch changes the definition of cpu_relax() to smp_mb() for ARMv6 cores, forcing a flushing of the write buffer on SMP systems before the next load takes place. If the Kernel is not compiled for SMP support, this will expand to a barrier() as before. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* asm-generic: remove ARCH_HAS_SG_CHAIN in scatterlist.hFUJITA Tomonori2010-05-27
| | | | | | | | | | | | | There are more architectures that don't support ARCH_HAS_SG_CHAIN than those that support it. This removes removes ARCH_HAS_SG_CHAIN in asm-generic/scatterlist.h and lets arhictectures to define it. It's clearer than defining ARCH_HAS_SG_CHAIN asm-generic/scatterlist.h and undefing it in arhictectures that don't support it. Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2010-05-25
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (103 commits) ARM: 6141/1: Add audio support part in arch/arm/mach-w90x900 ARM: 5939/1: ARM: Add option CMDLINE_FORCE to force usage of the in-kernel cmdline ARM: 6140/1: silence a bogus sparse warning in unwind.c ARM: mach-at91: duplicated include ARM: arch/arm/nwfpe/fpsr.h: Checkpatch cleanup ARM: arch/arm/mach-shark/pci.c: Checkpatch cleanup ARM: arch/arm/nwfpe/ChangeLog: Checkpatch cleanup ARM: arch/arm/mach-sa1100/leds.c: Checkpatch cleanup ARM: arch/arm/mach-h720x/common.h: Checkpatch cleanup ARM: arch/arm/mach-footbridge/ebsa285-pci.c: Checkpatch cleanup ARM: arch/arm/mach-clps711x/Makefile.boot: Checkpatch cleanup ARM: arch/arm/boot/bootp/bootp.lds: Checkpatch cleanup ARM: SPEAR6xx: remove duplicated #include ARM: s3c6400_defconfig: Add NAND driver ARM: s3c6400_defconfig: enable sound as modules ARM: s3c6400_defconfig: enable power management ARM: s5pv210_defconfig: Update s5pv210_defconfig to v2.6.34 ARM: s5pc110_defconfig: Update s5pc110_defconfig to v2.6.34 ARM: s5p6442_defconfig: Update s5p6442_defconfig to v2.6.34 ARM: s5p6440_defconfig: Update s5p6440_defconfig to v2.6.34 ...
| * ARM: 6138/1: Add support for 10 hardirq bitsMagnus Damm2010-05-20
| | | | | | | | | | | | | | | | | | | | This patch adds support for 10 hardirq bits to the ARM architecture. Needed by the SH-Mobile ARM processor sh7372 that has more than 512 IRQs. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | kdb: core for kgdb back end (2 of 2)Jason Wessel2010-05-20
| | | | | | | | | | | | | | | | | | | | This patch contains the hooks and instrumentation into kernel which live outside the kernel/debug directory, which the kdb core will call to run commands like lsmod, dmesg, bt etc... CC: linux-arch@vger.kernel.org Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Martin Hicks <mort@sgi.com>
* | Merge branch 'for-linus' of ↵Linus Torvalds2010-05-20
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (44 commits) vlynq: make whole Kconfig-menu dependant on architecture add descriptive comment for TIF_MEMDIE task flag declaration. EEPROM: max6875: Header file cleanup EEPROM: 93cx6: Header file cleanup EEPROM: Header file cleanup agp: use NULL instead of 0 when pointer is needed rtc-v3020: make bitfield unsigned PCI: make bitfield unsigned jbd2: use NULL instead of 0 when pointer is needed cciss: fix shadows sparse warning doc: inode uses a mutex instead of a semaphore. uml: i386: Avoid redefinition of NR_syscalls fix "seperate" typos in comments cocbalt_lcdfb: correct sections doc: Change urls for sparse Powerpc: wii: Fix typo in comment i2o: cleanup some exit paths Documentation/: it's -> its where appropriate UML: Fix compiler warning due to missing task_struct declaration UML: add kernel.h include to signal.c ...
| * add descriptive comment for TIF_MEMDIE task flag declaration.Andreas Dilger2010-05-14
| | | | | | | | | | | | Signed-off-by: Andreas Dilger <adilger@dilger.ca> Acked-by: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* | Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2010-05-19
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (224 commits) ARM: remove 'select GENERIC_TIME' ARM: 6136/1: ARCH_REQUIRE_GPIOLIB selects GENERIC_GPIO ARM: 6074/1: oprofile: convert from sysdev to platform device ARM: 6073/1: oprofile: remove old files and update KConfig ARM: 6072/1: oprofile: use perf-events framework as backend ARM: 6071/1: perf-events: allow modules to query the number of hardware counters ARM: 6070/1: perf-events: add support for xscale PMUs ARM: 6069/1: perf-events: use numeric ID to identify PMU ARM: 6064/1: pmu: register IRQs at runtime ARM: Optionally allow ARMv6 to use 'normal, bufferable' memory for DMA ARM: 6134/1: Handle instruction cache maintenance fault properly ARM: nwfpe: allow debugging output to be configured at runtime ARM: rename mach_cpu_disable() to platform_cpu_disable() ARM: 6132/1: PL330: Add common core driver ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310 ARM: Move memory mapping into mmu.c ARM: Ensure meminfo is sorted prior to sanity_check_meminfo ARM: Remove useless linux/bootmem.h includes ARM: convert /proc/cpu/aligment to seq_file arm: use asm-generic/scatterlist.h ...
| * \ Merge branch 'devel-stable' into develRussell King2010-05-17
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/Kconfig arch/arm/include/asm/system.h arch/arm/mm/Kconfig
| * | | ARM: 6071/1: perf-events: allow modules to query the number of hardware countersWill Deacon2010-05-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For OProfile to initialise oprofilefs correctly, it needs to know the number of counters it can represent. This patch adds a function to the ARM perf-events backend to return the number of hardware counters available for the current PMU. Cc: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: 6069/1: perf-events: use numeric ID to identify PMUWill Deacon2010-05-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM perf-events framework provides support for a number of different PMUs using struct arm_pmu. The char *name field of this struct can be used to identify the PMU, but this is cumbersome if used outside of perf. This patch replaces the name string for a PMU with an enum, which holds a unique ID for the PMU being represented. This ID can be used to index an array of names within perf, so no functionality is lost. The presence of the ID field, allows other kernel subsystems [currently oprofile] to use their own mappings for the PMU name. Cc: Jean Pihet <jpihet@mvista.com> Acked-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: 6064/1: pmu: register IRQs at runtimeWill Deacon2010-05-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current PMU infrastructure for ARM requires that the IRQs for the PMU device are fixed at compile time and are selected based on the ARCH_ or MACH_ flags. This has the disadvantage of tying the Kernel down to a particular board as far as profiling is concerned. This patch replaces the compile-time IRQ registration with a runtime mechanism which allows the IRQs to be registered with the framework as a platform_device. A further advantage of this change is that there is scope for registering different types of performance counters in the future by changing the id of the platform_device and attaching different resources to it. Acked-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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| *-------. \ \ Merge branches 'at91', 'bcmring', 'ep93xx', 'iop', 'misc', 'nomadik', ↵Russell King2010-05-17
| |\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'omap', 'pxa', 'spear' and 'versatile' into devel Conflicts: arch/arm/Makefile arch/arm/common/Makefile arch/arm/mm/Kconfig
| | | | | | * | | ARM: ICST: kill duplicate icst codeRussell King2010-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only difference between ICST307 and ICST525 are the two arrays for calculating the S parameter; the code is now identical. Merge the two files and kill the duplicated code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | ARM: ICST: indirect s2div and idx2s arrays via icst_paramsRussell King2010-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | ARM: ICST: move minimum VCO frequency to icst_paramsRussell King2010-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | ARM: ICST: use Hz instead of kHzRussell King2010-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes the ICST support fit more nicely with the clk API, eliminating the need to *1000 and /1000 in places. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | ARM: ICST: provide definitions for max/min VCO frequenciesRussell King2010-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | ARM: ICST: icst.*_ps_to_vco() functions are unused, remove themRussell King2010-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These functions were originally implemented for the CLCD driver before we had clk API support. Since the CLCD driver does not use these anymore, we can remove them. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | ARM: ICST: merge common ICST VCO structuresRussell King2010-05-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The structures for the ICST307 and ICST525 VCO devices are identical, so merge them together. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * | | ARM: Improve documentation in arm_timer.hRussell King2010-04-29
| | | |_|_|/ / / | | |/| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * | | ARM: 6021/1: ST SPEAr: Added ARM PrimeXsys System Controller SP810 header fileviresh kumar2010-04-14
| | | | |/ / / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reviewed-by: Linus Walleij <linux.walleij@stericsson.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: Optionally allow ARMv6 to use 'normal, bufferable' memory for DMARussell King2010-05-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a configuration option to allow the ARMv6 to use normal bufferable memory for coherent DMA. This option is forced to 'y' for ARMv7, and offered as a configuration option on ARMv6. Enabling this option requires drivers to have the necessary barriers to ensure that data in DMA coherent memory is visible prior to the DMA operation commencing. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: rename mach_cpu_disable() to platform_cpu_disable()Russell King2010-05-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consistently name all SMP platform related functions. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 6132/1: PL330: Add common core driverJassi Brar2010-05-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PL330 is a configurable DMA controller PrimeCell device. The register map of the device is well defined. The configuration of a particular implementation can be read from the six configuration registers CR0-4,Dn. This patch implements a driver for the specification:- http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424a/DDI0424A_dmac_pl330_r0p0_trm.pdf The exported interface should be sufficient to implement a driver for any DMA API. Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310Jason McMullan2010-05-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The L310 cache controller's interface is almost identical to the L210. One major difference is that the PL310 can have up to 16 ways. This change uses the cache's part ID and the Associativity bits in the AUX_CTRL register to determine the number of ways. Also, this version prints out the CACHE_ID and AUX_CTRL registers. Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Jason S. McMullan <jason.mcmullan@netronome.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | arm: use asm-generic/scatterlist.hFUJITA Tomonori2010-05-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: 6058/1: Add support for PCI domainsAnton Vorontsov2010-04-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for PCI domains on ARM platforms. Also, protect asm/mach/pci.h from multiple inclustions, otherwise build fails because of pci_domain_nr() and pci_proc_domain() redefinitions. Signed-off-by: Anton Vorontsov <avorontsov@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * | | ARM: convert arm to arch_gettimeoffset()John Stultz2010-03-24
| | | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert arm to use GENERIC_TIME via the arch_getoffset() infrastructure, reducing the amount of arch specific code we need to maintain. The arm architecture is the last arch that need to be converted. Signed-off-by: John Stultz <johnstul@us.ibm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Andrew Morton <akpm@linux-foundation.org>
| | * / / / ARM: 6063/1: pmu: add enum describing PMU typesWill Deacon2010-04-29
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds an enum describing the potential PMU device types in preparation for PMU device registration via platform devices. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * / / / ARM: 6092/1: atmel_serial: support for RS485 communicationsClaudio Scordino2010-05-04
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Final version of the patch that adds support for RS485 communications to the atmel_serial driver. The patch has been already sent and discussed on both linux-kernel and linux-arm-kernel mailing lists several times. Many people collaborated to improve and test the code: Tested-by: Sebastian Heutling <Sebastian.Heutling@who-ing.de> Tested-by: Bernhard Roth <br@pwrnet.de> Reviewed-by: Ryan Mallon <ryan@bluewatersys.com> Signed-off-by: Claudio Scordino <claudio@evidence.eu.com> Signed-off-by: Michael Trimarchi <michael@evidence.eu.com> Signed-off-by: Rick Bronson <rick@efn.org> Signed-off-by: Sebastian Heutling <Sebastian.Heutling@who-ing.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | atomic_t: Cast to volatile when accessing atomic variablesAnton Blanchard2010-05-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for removing volatile from the atomic_t definition, this patch adds a volatile cast to all the atomic read functions. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | | ARM: 6125/1: ARM TWD: move TWD registers to common headerSrinidhi Kasagar2010-05-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This moves the TWD register set of MPcore to a common existing file so that watchdog driver can access it Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMPCatalin Marinas2010-05-08
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | The standard I-cache Invalidate All (ICIALLU) and Branch Predication Invalidate All (BPIALL) operations are not automatically broadcast to the other CPUs in an ARMv7 MP system. The patch adds the Inner Shareable variants, ICIALLUIS and BPIALLIS, if ARMv7 and SMP. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | arch/arm/include/asm/elf.h: forward-declare the task-structAndrew Morton2010-05-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | iop32x_defconfig: In file included from include/linux/elf.h:7, from kernel/elfcore.c:1: arch/arm/include/asm/elf.h:101: warning: "struct task_struct" declared inside parameter list arch/arm/include/asm/elf.h:101: warning: its scope is only this definition or declaration, which is probably not what you want Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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