aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/include/asm/mach
Commit message (Collapse)AuthorAge
* Merge branch 'devel' of ↵Russell King2011-03-26
|\ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel-stable Conflicts: arch/arm/mach-pxa/tosa.c
| * ARM: pxa: drop gpio_vbus field from pxa2xx_udc_mach_infoDmitry Eremin-Solenikov2011-03-16
| | | | | | | | | | | | | | | | Neither pxa25x_udc, nor pxa27x_udc use gpio_vbus/gpio_vbus_inverted anymore. Drop those two fields from udc info completely. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* | Merge branch 'misc' into develRussell King2011-03-16
|\ \ | |/ |/| | | | | Conflicts: arch/arm/Kconfig
| * ARM: 6806/1: irq: introduce entry and exit functions for chained handlersWill Deacon2011-03-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some chained IRQ handlers are written to cope with primary chips of potentially different flow types. Whether this a sensible thing to do is a point of contention. This patch introduces entry/exit functions for chained handlers which infer the flow type of the primary chip as fasteoi or level-type by checking whether or not the ->irq_eoi function pointer is present and calling back to the primary chip as necessary. Other methods of flow control are not considered. Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6765/1: remove obsolete comment from asm/mach/arch.hNicolas Pitre2011-02-26
|/ | | | | | | Since commit 6fc31d54 this comment is no longer true. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'smp' into miscRussell King2011-01-06
|\ | | | | | | | | | | Conflicts: arch/arm/kernel/entry-armv.S arch/arm/mm/ioremap.c
| * ARM: fix /proc/interrupts formattingRussell King2010-12-20
| | | | | | | | | | | | | | | | | | As per x86, align the initial column according to how many IRQs we have. Also, provide an english explaination for the 'LOC:' and 'IPI:' lines. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: provide an early platform initialization hookRussell King2010-12-24
| | | | | | | | | | | | | | This allows platforms to hook into the initialization early to setup things like scheduler clocks, etc. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: simplify early machine init hooksRussell King2010-12-24
| | | | | | | | | | | | | | | | | | | | Rather than storing each machine init hook separately, store a pointer to the machine description record and dereference this instead. This pointer is only available while the init sections are present, which is not a problem as we only use it from init code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6532/1: Allow machine to specify it's own IRQ handlers at run-timeeric miao2010-12-24
|/ | | | | | | | | | | | | | | | | | | | | | | | | | Normally different ARM platform has different way to decode the IRQ hardware status and demultiplex to the corresponding IRQ handler. This is highly optimized by macro irq_handler in entry-armv.S, and each machine defines their own macro to decode the IRQ number. However, this prevents multiple machine classes to be built into a single kernel. By allowing each machine to specify thier own handler, and making function pointer 'handle_arch_irq' to point to it at run time, this can be solved. And introduce CONFIG_MULTI_IRQ_HANDLER to allow both solutions to work. Comparing with the highly optimized macro of irq_handler, the new function must be written with care not to lose too much performance. And the IPI stuff on SMP is expected to move to the provided arch IRQ handler as well. The assembly code to invoke handle_arch_irq is optimized by Russell King. Signed-off-by: Eric Miao <eric.miao@canonical.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* arm: remove machine_desc.io_pg_offst and .phys_ioNicolas Pitre2010-10-20
| | | | | | | | | | | | | | | Since we're now using addruart to establish the debug mapping, we can remove the io_pg_offst and phys_io members of struct machine_desc. The various declarations were removed using the following script: grep -rl MACHINE_START arch/arm | xargs \ sed -i '/MACHINE_START/,/MACHINE_END/ { /\.\(phys_io\|io_pg_offst\)/d }' [ Initial patch was from Jeremy Kerr, example script from Russell King ] Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Eric Miao <eric.miao at canonical.com>
* ARM: make struct machine_desc definition coherent with its commentNicolas Pitre2010-10-20
| | | | | | | | As mentioned in the comment right at the top, the first four fields are directly accessed by assembly code in head.S. Move nr_irqs so the comment is true again. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* Merge branch 'devel-stable' into develRussell King2010-07-31
|\ | | | | | | | | | | | | Conflicts: arch/arm/kernel/entry-armv.S arch/arm/kernel/setup.c arch/arm/mm/init.c
| * [ARM] PCI: add platform private data to pci_sys_dataSaeed Bishara2010-07-16
| | | | | | | | | | | | | | | | Add private_data pointer to the pci_sys_data, this pointer can be used for holding platform specific data for each pci controller. Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* | Merge branch 'misc' into develRussell King2010-07-31
|\ \ | | | | | | | | | | | | Conflicts: arch/arm/mm/init.c
| * | Merge branch 'origin' into miscRussell King2010-07-27
| |\|
| * | ARM: 6222/1: add memory types for the TCMsLinus Walleij2010-07-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The earlier TCM memory regions were mapped as MT_MEMORY_UNCACHED which doesn't really work on platforms supporting the new v6 features like the NX bit. Add unique MT_MEMORY_[I|D]TCM types instead. Cc: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | |
| \ \
| \ \
| \ \
*---. \ \ Merge branches 'at91', 'ep93xx', 'kexec', 'iop', 'lmb', 'nomadik', 'nuc', ↵Russell King2010-07-31
|\ \ \ \ \ | | | |/ / | | |/| / | |_|_|/ |/| | | 'pl', 'spear' and 'versatile' into devel
| | | * ARM: Move platform memory reservations out of generic codeRussell King2010-07-16
| |_|/ |/| | | | | | | | | | | | | | | | | Move the platform specific bootmem memory reservations out of arch/arm/mm/mmu.c into their respective platform files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * ARM: 6197/2: preliminary support for sparse IRQeric miao2010-07-09
| |/ | | | | | | | | | | | | | | | | So to allow NR_IRQS to be dynamic and platforms to specify the number of IRQs really needed. Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* / [ARM] pxa: fix incorrect gpio type in udc_pxa2xx.hSteve Bennett2010-06-13
|/ | | | | | | | gpio must be int, not u16, otherwise -1 isn't recognised by gpio_is_valid(). Signed-off-by: Steve Bennett <steveb@workware.net.au> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* ARM: 6058/1: Add support for PCI domainsAnton Vorontsov2010-04-22
| | | | | | | | | | | This patch adds support for PCI domains on ARM platforms. Also, protect asm/mach/pci.h from multiple inclustions, otherwise build fails because of pci_domain_nr() and pci_proc_domain() redefinitions. Signed-off-by: Anton Vorontsov <avorontsov@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: convert arm to arch_gettimeoffset()John Stultz2010-03-24
| | | | | | | | | | | Convert arm to use GENERIC_TIME via the arch_getoffset() infrastructure, reducing the amount of arch specific code we need to maintain. The arm architecture is the last arch that need to be converted. Signed-off-by: John Stultz <johnstul@us.ibm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Andrew Morton <akpm@linux-foundation.org>
* ARM: remove old RTC supportRussell King2010-02-15
| | | | | | | | All RTC drivers have been converted to rtclib, so the old code providing the set_rtc function pointer, save_time_delta() and restore_time_delta() functions is obsolete. Remove it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* genirq: Convert irq_desc.lock to raw_spinlockThomas Gleixner2009-12-14
| | | | | | | | | Convert locks which cannot be sleeping locks in preempt-rt to raw_spinlocks. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra <peterz@infradead.org> Acked-by: Ingo Molnar <mingo@elte.hu>
* ARM: 5720/1: Move MMCI header to amba include dirLinus Walleij2009-09-22
| | | | | | | | | | | | | This moves the mmci platform data definition struct away from arch/arm/include/asm/mach/mmc.h into the more proper place among the other primecells in include/linux/amba/mmci.h and at the same time renames it to "mmci.h", and also the struct in this file confusingly named mmc_platform_data has been renamed mmci_platform_data for clarity. Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5698/1: MMCI pass capabilities in platform dataLinus Walleij2009-09-15
| | | | | | | | | | | | This makes it possible to pass down the host controller capabilities for the MMCI driver using the platform data. It also provides the capabilties for the U300 implementation as an example, and makes sure the 4bit wide mode is set if this is requested by the ios() now that we can actually set that capability for a platform. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* MMC: MMCI: allow GPIOs to be passedRussell King2009-07-09
| | | | | | | | Add and initialize the gpio_wp and gpio_cd members. We need to ensure that all users are covered, because GPIO 0 may be valid. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Linus Walleij <linus.walleij@stericsson.com>
* omap iommu: simple virtual address space managementHiroshi DOYU2009-05-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides a device drivers, which has a omap iommu, with address mapping APIs between device virtual address(iommu), physical address and MPU virtual address. There are 4 possible patterns for iommu virtual address(iova/da) mapping. |iova/ mapping iommu_ page | da pa va (d)-(p)-(v) function type --------------------------------------------------------------------------- 1 | c c c 1 - 1 - 1 _kmap() / _kunmap() s 2 | c c,a c 1 - 1 - 1 _kmalloc()/ _kfree() s 3 | c d c 1 - n - 1 _vmap() / _vunmap() s 4 | c d,a c 1 - n - 1 _vmalloc()/ _vfree() n* 'iova': device iommu virtual address 'da': alias of 'iova' 'pa': physical address 'va': mpu virtual address 'c': contiguous memory area 'd': dicontiguous memory area 'a': anonymous memory allocation '()': optional feature 'n': a normal page(4KB) size is used. 's': multiple iommu superpage(16MB, 1MB, 64KB, 4KB) size is used. '*': not yet, but feasible. Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
* [ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory typePaul Walmsley2009-03-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a Non-cacheable Normal ARM executable memory type, MT_MEMORY_NONCACHED. On OMAP3, this is used for rapid dynamic voltage/frequency scaling in the VDD2 voltage domain. OMAP3's SDRAM controller (SDRC) is in the VDD2 voltage domain, and its clock frequency must change along with voltage. The SDRC clock change code cannot run from SDRAM itself, since SDRAM accesses are paused during the clock change. So the current implementation of the DVFS code executes from OMAP on-chip SRAM, aka "OCM RAM." If the OCM RAM pages are marked as Cacheable, the ARM cache controller will attempt to flush dirty cache lines to the SDRC, so it can fill those lines with OCM RAM instruction code. The problem is that the SDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU subsystem to hang. TI's original solution to this problem was to mark the OCM RAM sections as Strongly Ordered memory, thus preventing caching. This is overkill: since the memory is marked as non-bufferable, OCM RAM writes become needlessly slow. The idea of "Strongly Ordered SRAM" is also conceptually disturbing. Previous LAKML list discussion is here: http://www.spinics.net/lists/arm-kernel/msg54312.html This memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future patch. Cc: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'dma' into develRussell King2009-02-21
|\ | | | | | | | | | | Conflicts: arch/arm/plat-mxc/dma-mx1-mx2.c
| * [ARM] dma: move IOMD and floppy DMA structures to RiscPC DMA codeRussell King2009-02-21
| | | | | | | | | | | | | | There's no point these being in a generic include file when they're only used in arch/arm/mach-rpc/dma.c. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] dma: remove dmamode_t typedefRussell King2009-01-02
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] dma: constify dma controller name and dma opsRussell King2008-12-11
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] dma: move RiscPC specific DMA data out of dma_structRussell King2008-12-11
| | | | | | | | | | | | | | Separate the RiscPC specific (IOMD and floppy FIQ) data out of the core DMA structure by making the IOMD and floppy DMA supersets. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] dma: rejig DMA initializationRussell King2008-12-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than having the central DMA multiplexer call the architecture specific DMA initialization function, have each architecture DMA initialization function use core_initcall(), and register each DMA channel separately with the multiplexer. This removes the array of dma structures in the central multiplexer, replacing it with an array of pointers instead; this is more flexible since it allows the drivers to wrap the DMA structure (eventually allowing us to transition non-ISA DMA drivers away.) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] dma: remove dmach_t typedefRussell King2008-12-08
| | | | | | | | | | | | Remove a pointless integer typedef. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | PCI: arm: use generic INTx swizzle from PCI coreBjorn Helgaas2009-01-07
|/ | | | | | | Use the generic pci_common_swizzle() instead of arch-specific code. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* [ARM] iop: iop3xx needs registers mapped uncached+unbufferedRussell King2008-11-09
| | | | | | | | | | | | | | | | | | | | | Mikael Pettersson reported: The 2.6.28-rc kernels fail to detect PCI device 0000:00:01.0 (the first ethernet port) on my Thecus n2100 XScale box. There is however still a strange "ghost" device that gets partially detected in 2.6.28-rc2 vanilla. The IOP321 manual says: The user designates the memory region containing the OCCDR as non-cacheable and non-bufferable from the IntelR XScaleTM core. This guarantees that all load/stores to the OCCDR are only of DWORD quantities. Ensure that the OCCDR is so mapped. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'pxa-all' into develRussell King2008-10-09
|\ | | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-pxa/Kconfig arch/arm/mach-pxa/corgi.c arch/arm/mach-pxa/include/mach/hardware.h arch/arm/mach-pxa/spitz.c
| * Merge branches 'pxa-core' and 'pxa-machines' into pxa-allRussell King2008-10-07
| |\ | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-pxa/Kconfig arch/arm/mach-pxa/pxa25x.c arch/arm/mach-pxa/pxa27x.c
| * | [ARM] pxa: remove references to pxa_gpio_mode() in commentsRussell King2008-09-25
| | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] Remove MT_NONSHARED_DEVICE aliasRussell King2008-10-01
| | | | | | | | | | | | | | | | | | Use MT_DEVICE_NONSHARED instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | [ARM] Remove MT_DEVICE_IXP2000 and associated definitionsRussell King2008-10-01
| |/ |/| | | | | | | | | | | | | As of the previous commit, MT_DEVICE_IXP2000 encodes to the same PTE bit encoding as MT_DEVICE, so it's now redundant. Convert MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] 5241/1: provide ioremap_wc()Lennert Buytenhek2008-09-06
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides an ARM implementation of ioremap_wc(). We use different page table attributes depending on which CPU we are running on: - Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four possible mapping types (CB=00/01/10/11). We can't use any of the cached memory types (CB=10/11), since that breaks coherency with peripheral devices. Both CB=00 and CB=01 are suitable for _wc, and CB=01 (Uncached/Buffered) allows the hardware more freedom than CB=00, so we'll use that. (The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores but isn't allowed to merge them, but there is no other mapping type we can use that allows the hardware to delay and merge stores, so we'll go with CB=01.) - XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight difference that on these platforms, CB=01 actually _does_ allow merging stores. (If you want noncoalescing bufferable behavior on Xscale v1/v2, you need to use XCB=101.) - Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100 mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal in ARMv6 parlance). The ARMv6 ARM explicitly says that any accesses to Normal memory can be merged, which makes Normal memory more suitable for _wc mappings than Device or Strongly Ordered memory, as the latter two mapping types are guaranteed to maintain transaction number, size and order. We use the Uncached variety of Normal mappings for the same reason that we can't use C=1 mappings on ARMv5. The xsc3 Architecture Specification documents TEXCB=00100 as being Uncacheable and allowing coalescing of writes, which is also just what we need. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix circular include dependency with IRQ headersRussell King2008-08-07
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] move include/asm-arm to arch/arm/include/asmRussell King2008-08-02
Move platform independent header files to arch/arm/include/asm, leaving those in asm/arch* and asm/plat* alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 21:06:38 -0500