| Commit message (Collapse) | Author | Age |
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Follows the sh_clk_div_recalc() change.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This generalizes the div4 recalc routine for use by div6 and others, then
makes it the default.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This plugs in a div_mask for the clock and sets it up for the existing
div6/4 cases. This will make it possible to support other div types, as
well as share more div6/4 infrastructure.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This plugs in a generic clk_div_table, based on the div4 version. div6 is
then adopted to use it for encapsulating its div table, which permits us
to start div6/4 unification, as well as preparation for other div types.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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WARNING: vmlinux.o(.cpuinit.text+0x280): Section mismatch in reference from the function cpu_probe() to the function .init.text:sh64_tlb_init()
The function __cpuinit cpu_probe() references
a function __init sh64_tlb_init().
If sh64_tlb_init is only used by cpu_probe then
annotate sh64_tlb_init with a matching annotation.
sh64_tlb_init() simply needs to be __cpuinit annotated, so fix that up.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This has been long overdue. No functional changes.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This kills off the _64 versions and consolidates on the more robust _32
versions instead.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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There's not much here that we can't get at through alternate means (aside
from the TLB contents, but that doesn't belong here anyways). Most of
this information is already provided by the sh32 routines, which we'll
consolidate on next.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This switches over from the special-casing that sh64 had and to the model
that's being employed for sh32.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Now that legacy pre-allocation is done away with, we can just use the
generic stub in kernel/softirq.c.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Conflicts:
drivers/sh/intc/dynamic.c
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This switches to using irq_alloc_desc() directly for subgroup IRQs.
We still need to call activate_irq() on these in order to make them
requestable, at least up until these get moved in to their own irq
domain..
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Now that all of the users have been converted away, kill off the remnants
of the old API.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Follows the se7722 change, see there for more information.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This implements a total rewrite of the rather buggy SE7722 FPGA IRQ code,
utilizing a linear irq domain as well as the generic irq chip type.
While the interaction between the two APIs is a bit clunky (ie, revmap
lookup for gc irq_base), they work well enough together that it's easy
enough to work with going forward.
While we're at it, deal with irq_mask_ack/unmask of the chained IRQ in
the demux handler to prevent smc91x screaming about spurious interrupts.
There's also some more improvement that can be made to the irqdomain code
to create backing irqdescs for the entire linear range in one bang
instead of iterating over the number of hwirqs and doing it
irq-at-a-time. This is easily dealt with at a later point, though.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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In the interest of getting off of the create_irq() API we can get all of
the functionality we're interested in through a linear IRQ domain. Fairly
straightforward conversion utilizing a single linear domain.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Switches from create_irq_nr() to irq_alloc_descs().
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Switches from create_irq_nr() to irq_alloc_descs().
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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The generic hardirq layer provides all of the routines that we need these
days, so we don't require any of the dynamic IRQ API wrapping, and can
call in to irq_alloc_descs() directly.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Since sh64 depends on kallsyms unconditionally for its stack unwinding to
be of any use, make sure it's selected. In practice we don't have any
case where it's disabled anyways, so moving to this to a select is fine.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This switches over to use the sh unwinder API which brings it all in line
with the general sh routines (which we shuffle around at the same time),
and lets us kill off more sh64-specific cruft.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull powerpc updates from Benjamin Herrenschmidt:
"Notable highlights:
- iommu improvements from Anton removing the per-iommu global lock in
favor of dividing the DMA space into pools, each with its own lock,
and hashed on the CPU number. Along with making the locking more
fine grained, this gives significant improvements in multiqueue
networking scalability.
- Still from Anton, we know provide a vdso based variant of getcpu
which makes sched_getcpu with the appropriate glibc patch something
like 18 times faster.
- More anton goodness (he's been busy !) in other areas such as a
faster __clear_user and copy_page on P7, various perf fixes to
improve sampling quality, etc...
- One more step toward removing legacy i2c interfaces by using new
device-tree based probing of platform devices for the AOA audio
drivers
- A nice series of patches from Michael Neuling that helps avoiding
confusion between register numbers and litterals in assembly code,
trying to enforce the use of "%rN" register names in gas rather
than plain numbers.
- A pile of FSL updates
- The usual bunch of small fixes, cleanups etc...
You may spot a change to drivers/char/mem. The patch got no comment
or ack from outside, it's a trivial patch to allow the architecture to
skip creating /dev/port, which we use to disable it on ppc64 that
don't have a legacy brige. On those, IO ports 0...64K are not mapped
in kernel space at all, so accesses to /dev/port cause oopses (and
yes, distros -still- ship userspace that bangs hard coded ports such
as kbdrate)."
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (106 commits)
powerpc/mpic: Create a revmap with enough entries for IPIs and timers
Remove stale .rej file
powerpc/iommu: Fix iommu pool initialization
powerpc/eeh: Check handle_eeh_events() return value
powerpc/85xx: Add phy nodes in SGMII mode for MPC8536/44/72DS & P2020DS
powerpc/e500: add paravirt QEMU platform
powerpc/mpc85xx_ds: convert to unified PCI init
powerpc/fsl-pci: get PCI init out of board files
powerpc/85xx: Update corenet64_smp_defconfig
powerpc/85xx: Update corenet32_smp_defconfig
powerpc/85xx: Rename P1021RDB-PC device trees to be consistent
powerpc/watchdog: move booke watchdog param related code to setup-common.c
sound/aoa: Adapt to new i2c probing scheme
i2c/powermac: Improve detection of devices from device-tree
powerpc: Disable /dev/port interface on systems without an ISA bridge
of: Improve prom_update_property() function
powerpc: Add "memory" attribute for mfmsr()
powerpc/ftrace: Fix assembly trampoline register usage
powerpc/hw_breakpoints: Fix incorrect pointer access
powerpc: Put the gpr save/restore functions in their own section
...
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The current mpic code creates a linear revmap just big enough for all
the sources, which happens to miss the IPIs and timers on some machines.
This will in turn break when the irqdomain code loses the fallback of
doing a linear search when the revmap fails (and really slows down IPIs
otherwise).
This happens for example on the U4 based Apple machines such as the
dual core PowerMac G5s.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Commit 9778b696a0188ad3b3524b383953ee73b31b7b68 accidentally added
a .rej file (probably my fault), remove it.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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The iommu pool patch has a bug where it would cause a crash when using
only one pool (based on the size of the DMA window).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Freescale updates for 3.6
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In SGMII riser card different PHY chip are used with different external
IRQ from eTSEC. To support PHY link state auto detect in SGMII mode we
should add another group of PHY nodes for SGMII mode.
For MPC8572DS IRQ6 is used for PHY0~PHY1, IRQ7 is used for PHY2~PHY3.
For MPC8544DS and MPC8536DS IRQ6 is used for PHY0~PHY1.
For P2020DS IRQ5 is used for PHY1~PHY2.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This gives the kernel a paravirtualized machine to target, without
requiring both sides to pretend to be targeting a specific board
that likely has little to do with the host in KVM scenarios. This
avoids the need to add new boards to QEMU just to be able to
run KVM on new CPUs.
As this is the first platform that can run with either e500v2 or
e500mc, CONFIG_PPC_E500MC is now a legitimately user configurable
option, so add a help text.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Similar to how the primary PCI bridge is identified by looking
for an isa subnode, we determine whether to apply uli exclusions
by looking for a uli subnode.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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As an alternative incremental starting point to Jia Hongtao's patchset,
get the FSL PCI init out of the board files, but do not yet convert to a
platform driver.
Rather than having each board supply a magic register offset for
determining the "primary" bus, we look for which PCI host bridge
contains an ISA node within its subtree. If there is no ISA node,
normally that would mean there is no primary bus, but until certain
bugs are fixed we arbitrarily designate a primary in this case.
Conversion to a platform driver and related improvements can happen
after this, as the ordering issues are sorted out.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Enable USB, MMC, SATA, LBC, MTD, NAND, SPI, PCIe, EDAC, VFAT, NFS, etc.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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- Enable NAND support
- Enable CONFIG_PCI_MSI and CONFIG_MMC_SDHCI_OF
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The board is really P1021RDB-PC, so rename from p1021rdb.* to p1021rdb-pc.*
Signed-off-by: Xu Jiucheng <Jiucheng.Xu@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Currently, BOOKE watchdog code for checking "wdt" and "wdt_period" is
in setup_32.c, it cannot be used in 64-bit, so move it to a common place
setup-common.c, which will be shared by 32-bit and 64-bit.
Also, replace the simple_strtoul with kstrtol.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Add device tree nodes to enable ucc uart support on P1025RDB.
Signed-off-by: Zhicheng Fan <B32736@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Freescale PowerPC SoCs share a number of IP blocks with Freescale
ARM/IMX SoCs, FlexCAN, SSI, FEC, eSDHC, USB, etc. There are some
effort consolidating those drivers to make them work for both
architectures.
One outstanding difference between two architectures is ARM/IMX will
turn off module clocks during platform initialization for power saving
and expects drivers manage clocks using clk API, while PowerPC
mostly does not do that, and thus does not always build in clk API.
Listing all those driver Kconfig options in "select PPC_CLOCK if" seems
not scalable for long term maintenance, and could easily introduce
Kconfig recursive dependency. This patch chooses to select PPC_CLOCK
unconditionally for FSL_SOC to always build clk API for PowerPC in.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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QE Microcode Initialization using qe_upload_microcode() does not work on
P1021 if the IRAM-Ready register is not set after the microcode upload. Add
a definition for the "I-RAM Ready" register and sets it upon microcode
upload completion.
Signed-off-by: Ioannis Kokkoris <ioannis.kokoris@siemens-enterprise.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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With 2-cell format interrupts of MSI PCIe ethernet card can not work.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The issue log on core1 is:
root@mpc8572ds:~# ifconfig eth0 10.192.208.244
net eth0: could not attach to PHY
SIOCSIFFLAGS: No such device
To attach PHY node mdio@24520 should not be disabled in dts of core1.
Because all PHYs are controlled through this node as follows:
mdio@24520 {
phy0: ethernet-phy@0 {
interrupts = <10 1 0 0>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupts = <10 1 0 0>;
reg = <0x1>;
};
phy2: ethernet-phy@2 {
interrupts = <10 1 0 0>;
reg = <0x2>;
};
phy3: ethernet-phy@3 {
interrupts = <10 1 0 0>;
reg = <0x3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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CONFIG_FSL_BOOKE is only defined in 32-bit, CONFIG_PPC_FSL_BOOK3E is
defined in both 32-bit and 64-bit, so use CONFIG_PPC_FSL_BOOK3E to make
driver work in 32-bit & 64-bit.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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We should use the MPIC_LARG_VECTORS flag while intializing the MPIC.
This prevents us from eating in to hardware vector number space (MSIs)
while setting up internal sources.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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So that we can call it when improving SPE switch like book3e did for fp
switch.
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Olivia Yin <hong-hua.yin@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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BSC9131RDB is a Freescale reference design board for BSC9131 SoC. The
BSC9131 is integrated SoC that targets Femto base station market. It
combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte
shared L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel
Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE
UP/DL Channel processing, and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix
Inversion operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit
with ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network
acceleration including IEEE 1588. v2 hardware support and
virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single
port) and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD
support
. Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers
The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.
BSC9131RDB Overview
----------------------
BSC9131 SoC
1Gbyte DDR3 (on board DDR)
128Mbyte 2K page size NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
USB-ULPI
eTSEC1: Connected to RGMII PHY
eTSEC2: Connected to RGMII PHY
DUART interface: supports one UARTs up to 115200 bps for console display
Linux runs on e500v2 core and access some DSP peripherals like AIC
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This reverts commit 96cc017c5b7ec095ef047d3c1952b6b6bbf98943.
The P3060 was cancelled before it went into production, so there's no point
in supporting it.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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In order to enable the DIU video controller on the P1022DS, the FPGA needs
to be switched to "indirect mode", where the localbus is disabled and
the FPGA is accessed via writes to localbus chip select signals CS0 and CS1.
To obtain the address of CS0 and CS1, the platform driver uses an "indirect
pixis mode" device tree node. This node assumes that the localbus 'ranges'
property is sorted in chip-select order. That is, reg value 0 maps to
CS0, reg value 1 maps to CS1, etc. This is how the 'ranges' property is
supposed to be arranged.
Unfortunately, the 'ranges' property is often mis-arranged, and not just on
the P1022DS. Linux normally does not care, since it does not program the
localbus. But the indirect-mode code on the P1022DS does care.
The "proper" fix is to have U-Boot fix the 'ranges' property, but this would
be too cumbersome. The names and 'reg' properties of all the localbus
devices would also need to be updated, and determining which localbus device
maps to which chip select is board-specific.
Instead, we determine the CS0/CS1 base addresses the same way that U-boot
does -- by reading the BRx registers directly and mapping them to physical
addresses. This code is simpler and more reliable, and it does not require
a U-boot or device tree change.
Since the indirect pixis device tree node is no longer needed, the node is
deleted from the DTS.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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NAND on p2041 uses CS1 as chip select.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This reference board dates back to 2004, and is largely a legacy
EOL product. The MPC8560 is a pre e500v2 CPU. The SBC8548 is
a more modern, better e500v2 target for people to use as a
reference board with today's kernels, should they require one.
Removing support for it will also allow us to remove some
sbc8560 specific quirk handling in 8250 UART code, and some
MTD mapping support.
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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