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* Merge tag 'highbank-cpuidle' of git://sources.calxeda.com/kernel/linux into ↵Olof Johansson2012-11-21
|\ | | | | | | | | | | | | | | | | | | next/soc From Rob Herring: Add cpuidle driver support for Calxeda Highbank SOC. * tag 'highbank-cpuidle' of git://sources.calxeda.com/kernel/linux: cpuidle: add Calxeda SOC idle support
| * cpuidle: add Calxeda SOC idle supportRob Herring2012-11-07
| | | | | | | | | | | | | | | | | | | | Add support for core powergating on Calxeda platforms. Initially, this supports ECX-1000 (highbank), but support will be added for ECX-2000 later. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Len Brown <len.brown@intel.com> Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
* | Merge tag 'highbank-debugll-cleanup' of ↵Olof Johansson2012-11-21
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://sources.calxeda.com/kernel/linux into next/soc From Rob Herring: Use common debug_ll_init function and remove the static mapping code from mach-highbank. * tag 'highbank-debugll-cleanup' of git://sources.calxeda.com/kernel/linux: ARM: highbank: use common debug_ll_io_init ARM: implement debug_ll_io_init()
| * | ARM: highbank: use common debug_ll_io_initRob Herring2012-11-07
| | | | | | | | | | | | | | | | | | | | | Remove the platform static mapping code for uart and use the common debug_ll_io_init function. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | Merge remote-tracking branch 'arm-soc/devel/debug_ll_init' into debug_llRob Herring2012-11-07
| |\ \
| | * | ARM: implement debug_ll_io_init()Rob Herring2012-11-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using DEBUG_LL, the UART's (or other HW's) registers are mapped into early page tables based on the results of assembly macro addruart. Later, when the page tables are replaced, the same virtual address must remain valid. Historically, this has been ensured by using defines from <mach/iomap.h> in both the implementation of addruart, and the machine's .map_io() function. However, with the move to single zImage, we wish to remove <mach/iomap.h>. To enable this, the macro addruart may be used when constructing the late page tables too; addruart is exposed as a C function debug_ll_addr(), and used to set up the required mapping in debug_ll_io_init(), which may called on an opt-in basis from a machine's .map_io() function. Signed-off-by: Rob Herring <rob.herring@calxeda.com> [swarren: Mask map.virtual with PAGE_MASK. Checked for NULL results from debug_ll_addr (e.g. when selected UART isn't valid). Fixed compile when either !CONFIG_DEBUG_LL or CONFIG_DEBUG_SEMIHOSTING.] Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* | | | Merge branch 'vexpress-clk-soc' of ↵Olof Johansson2012-11-21
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/pawelmoll/linux into next/soc From Pawel Moll: * 'vexpress-clk-soc' of git://git.linaro.org/people/pawelmoll/linux: ARM: vexpress: Remove motherboard dependencies in the DTS files ARM: vexpress: Start using new Versatile Express infrastructure ARM: vexpress: Add config bus components and clocks to DTs mfd: Versatile Express system registers driver mfd: Versatile Express config infrastructure
| * | | | ARM: vexpress: Remove motherboard dependencies in the DTS filesPawel Moll2012-11-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way the VE motherboard Device Trees were constructed enforced naming and structure of daughterboard files. This patch makes it possible to simply include the motherboard description anywhere in the main Device Tree and retires the "arm,v2m-timer" alias - any of the motherboard SP804 timers will be used instead. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
| * | | | ARM: vexpress: Start using new Versatile Express infrastructurePawel Moll2012-11-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch starts using all the configuration infrastructure. - generic GPIO library is forced now - sysreg GPIOs are used as MMC CD and WP information sources; thanks to this MMCI auxiliary data is not longer necessary - DVI muxer and mode control is removed from non-DT V2P-CA9 code as this is now handled by the vexpress-dvi driver - clock generators control is removed as is being handled by the common clock driver now - the sysreg and sysctl control is now delegated to the appropriate drivers and all related code was removed - NOR Flash set_vpp function has been removed as the control bit used does _not_ control its VPP line, but the #WP signal instead (which is de facto unusable in case of Linux MTD drivers); this also allowed the remove its DT auxiliary data The non-DT code defines only minimal required number of the config devices. Device Trees are updated to make use of all new features. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
| * | | | ARM: vexpress: Add config bus components and clocks to DTsPawel Moll2012-11-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add description of all functions provided by Versatile Express motherboard and daughterboards configuration controllers and clock dependencies between devices. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
| * | | | mfd: Versatile Express system registers driverPawel Moll2012-11-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a platform driver for Versatile Express' "system register" block. It's a random collection of registers providing the following functionality: - low level platform functions like board ID access; in order to use those, the driver must be initialized early, either statically or based on the DT - config bus bridge via "system control" interface; as the response from the controller does not generate interrupt (yet), the status register is periodically polled using a timer - pseudo GPIO lines providing MMC card status and Flash WP# signal control - LED interface for a set of 8 LEDs on the motherboard, with "heartbeat", "mmc0" and "cpu0" to "cpu5" as default triggers Signed-off-by: Pawel Moll <pawel.moll@arm.com>
| * | | | mfd: Versatile Express config infrastructurePawel Moll2012-11-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Versatile Express platform has an elaborated configuration system, consisting of microcontrollers residing on the mother- and daughterboards known as Motherboard/Daughterboard Configuration Controller (MCC and DCC). The controllers are responsible for the platform initialization (reset generation, flash programming, FPGA bitfiles loading etc.) but also control clock generators, voltage regulators, gather environmental data like temperature, power consumption etc. Even the video output switch (FPGA) is controlled that way. Those devices are _not_ visible in the main address space and the usual communication channel uses some kind of a bridge in the peripheral block sending commands (requests) to the controllers and receiving responses. It can take up to 500 microseconds for a transaction to be completed, therefore it is important to provide a non-blocking interface to it. This patch adds an abstraction of this infrastructure. Bridge drivers can register themselves with the framework. Then, a driver of a device can request an abstract "function" - the request will be redirected to a bridge referred by thedd "arm,vexpress,config-bridge" property of the device tree node. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
* | | | | Merge branch 'depends/clk' into next/socOlof Johansson2012-11-21
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From Mike Turquette: * depends/clk: clk: Common clocks implementation for Versatile Express clk: Versatile Express clock generators ("osc") driver CLK: clk-twl6040: Initial clock driver for OMAP4+ McPDM fclk clock clk: fix return value check in sirfsoc_of_clk_init() clk: fix return value check in of_fixed_clk_setup() clk: ux500: Update sdmmc clock to 100MHz for u8500 clk: ux500: Support prcmu ape opp voltage clock mfd: dbx500: Export prmcu_request_ape_opp_100_voltage clk: Don't return negative numbers for unsigned values with !clk clk: Fix documentation typos clk: Document .is_enabled op clk: SPEAr: Vco-pll: Fix compilation warning
| * | | | clk: Common clocks implementation for Versatile ExpressPawel Moll2012-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a DT and non-DT based implementation of the common clock infrastructure for Versatile Express platform. It registers (statically or using DT) all required fixed clocks, initialises motherboard's SP810 cell (that provides clocks for SP804 timers) and explicitly registers VE "osc" driver, to make the clock generators available early. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | clk: Versatile Express clock generators ("osc") driverPawel Moll2012-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver provides a common clock framework hardware driver for Versatile Express clock generators (a.k.a "osc") controlled via the config bus. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | CLK: clk-twl6040: Initial clock driver for OMAP4+ McPDM fclk clockPeter Ujfalusi2012-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP4+ platforms the functional clock for the McPDM IP is suplied by the twl6040 codec (bit clock on the PDM bus). This common clock driver for twl6040 will register the mcpdm_fclk clock to be used by the McPDM driver to make sure that the needed clocks are available when needed. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | clk: fix return value check in sirfsoc_of_clk_init()Wei Yongjun2012-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of error, the function clk_register() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). dpatch engine is used to auto generate this patch. (https://github.com/weiyj/dpatch) Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | clk: fix return value check in of_fixed_clk_setup()Wei Yongjun2012-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of error, the function clk_register_fixed_rate() returns ERR_PTR() not NULL pointer. The NULL test in the return value check should be replaced with IS_ERR(). dpatch engine is used to auto generated this patch. (https://github.com/weiyj/dpatch) Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | clk: ux500: Update sdmmc clock to 100MHz for u8500Ulf Hansson2012-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For u8500 and using 100MHz as the frequency also requires the ape opp 100 voltage, thus use the prcmu_opp_volt_scalable clock type. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | clk: ux500: Support prcmu ape opp voltage clockUlf Hansson2012-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some scalable prcmu clocks needs to be handled in conjuction with the ape opp 100 voltage. A new prcmu clock type clk_prcmu_opp_volt_scalable is implemented to handle this. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | mfd: dbx500: Export prmcu_request_ape_opp_100_voltageUlf Hansson2012-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function needs to be exported to let clients be able to request the ape opp 100 voltage. Cc: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | clk: Don't return negative numbers for unsigned values with !clkStephen Boyd2012-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the helper functions return negative error codes if passed a NULL clock. This can lead to confusing behavior when the expected return value is unsigned. Fix up these accessors so that they return unsigned values (or bool in the case of is_enabled). This way we can't interpret NULL clocks as having valid and interesting values. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | clk: Fix documentation typosStephen Boyd2012-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix some minor typos in the documentation for the ops structure. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | clk: Document .is_enabled opStephen Boyd2012-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the missing kernel-doc for this op. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | clk: SPEAr: Vco-pll: Fix compilation warningViresh Kumar2012-10-29
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we are getting following warning for SPEAr clk-vco-pll. "warning: i is used uninitialized in this function." This is because we are getting value of i by passing its pointer to another routine. The variables here are really not used uninitialized. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | | Merge tag 'bcm2835-for-3.8-defconfig' of ↵Olof Johansson2012-11-21
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi into next/soc From Stephen Warren: ARM: bcm2835: defconfig updates procfs and sysfs are enabled in bcm2835_defconfig. * tag 'bcm2835-for-3.8-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi: ARM: bcm2835: enable procfs and sysfs in defconfig Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | ARM: bcm2835: enable procfs and sysfs in defconfigThomas Petazzoni2012-10-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some reason, support for proc and sysfs is currently disabled in the bcm2835_defconfig, even though those filesystems are quite essential even for very basic Linux userspace. As most defconfig have them enabled by default, enable them as well in bcm2835_defconfig. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | | | | Merge tag 'bcm2835-for-3.8-soc' of ↵Olof Johansson2012-11-21
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi into next/soc From Stephen Warren: ARM: bcm2835: core SoC enhancements A machine restart/reboot implementation is added. The GPIO/pinmux controller is instantiated, and dummy gpio.h added. * tag 'bcm2835-for-3.8-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi: ARM: bcm2835: enable GPIO/pinctrl ARM: bcm2835: implement machine restart hook Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | | ARM: bcm2835: enable GPIO/pinctrlStephen Warren2012-10-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable GPIO and pinctrl in Kconfig. Add required <mach/gpio.h> for gpiolib. Instantiate the BCM2835 GPIO module in bcm2835.dtsi. Add a pinctrl definition to bcm2835-rpi-b.dts that sets up all of the board's required pinmux configuration. GPIO aren't specified; that's left to gpio_request(). Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | | ARM: bcm2835: implement machine restart hookStephen Warren2012-10-25
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the machine restart hook using the SoC's watchdog timer module. To support this, define a DT binding for the watchdog module, and add it to the device tree. The downstream rpi-split branch contains a full watchdog timer driver implementation, which also implements the restart hook. However, the restart function is largely separate from the watchdog driver, so for simplicity, the restart hook is implemented here directly in the main machine source file. Overall structure (separate setup/restart) functions derived from the picoxcell ARM support. Watchdog register IO sequence taken from code by Simon Arlott. Note that the watchdog module is not documented in BCM2835-ARM-Peripherals.pdf. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | | | | Merge tag 'tegra-for-3.8-defconfig' of ↵Olof Johansson2012-11-21
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stephen Warren: ARM: tegra: defconfig update Many new features are enabled in tegra_defconfig: * BRCMFMAC: wlan driver, enable as module. * MTD, MTD_CHAR, MTD_M25P80, SPI_TEGRA20_SLINK, CONFIG_SPI_TEGRA20_SFLASH to enable serial flash on Cardhu and TrimSlice. * PWM/backlight features for use with tegradrm. * tegradrm; Tegra's new display driver. * CMA, so that tegradrm can allocate large buffers. * SquashFS, which is used as the root filesystem on boards based on the Tamonten processor module. * tag 'tegra-for-3.8-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra: defconfig updates
| * | | | | ARM: tegra: defconfig updatesStephen Warren2012-11-15
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New options enabled: * BRCMFMAC: wlan driver, enable as module. * MTD, MTD_CHAR, MTD_M25P80, SPI_TEGRA20_SLINK, CONFIG_SPI_TEGRA20_SFLASH to enable serial flash on Cardhu and TrimSlice. * PWM/backlight features for use with tegradrm. * tegradrm; Tegra's new display driver. * CMA, so that tegradrm can allocate large buffers. * SquashFS, which is used as the root filesystem on boards based on the Tamonten processor module. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | | Merge tag 'tegra-for-3.8-cpuidle' of ↵Olof Johansson2012-11-21
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stephen Warren: ARM: tegra: cpuidle enhancements A cpuidle state "LP2" is added, which power-gates the CPUs. Support for CPUs 1..n is essentially complete, although support for CPU0 could benefit from future use of coupled-cpuidle or similar techniques. A couple of very minor cleanups to cpuidle were included too. This pull request is based on tegra-for-3.8-soc. * tag 'tegra-for-3.8-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra: retain L2 content over CPU suspend/resume ARM: tegra30: cpuidle: add powered-down state for CPU0 ARM: tegra30: flowctrl: add cpu_suspend_exter/exit function ARM: tegra30: clocks: add CPU low-power function into tegra_cpu_car_ops ARM: tegra30: common: enable csite clock ARM: tegra30: cpuidle: add powered-down state for secondary CPUs ARM: tegra: cpuidle: add CPU resume function ARM: tegra: cpuidle: separate cpuidle driver for different chips ARM: tegra: rename the file of "sleep-tXX" to "sleep-tegraXX" ARM: tegra: cpuidle: replace LP3 with ARM_CPUIDLE_WFI_STATE
| * | | | | ARM: tegra: retain L2 content over CPU suspend/resumeJoseph Lo2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The L2 RAM is in different power domain from the CPU cluster. So the L2 content can be retained over CPU suspend/resume. To do that, we need to disable L2 after the MMU is disabled, and enable L2 before the MMU is enabled. But the L2 controller is in the same power domain with the CPU cluster. We need to restore it's settings and re-enable it after the power be resumed. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: tegra30: cpuidle: add powered-down state for CPU0Joseph Lo2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a power gating idle mode. It support power gating vdd_cpu rail after all cpu cores in "powered-down" status. For Tegra30, the CPU0 can enter this state only when all secondary CPU is offline. We need to take care and make sure whole secondary CPUs were offline and checking the CPU power gate status. After that, the CPU0 can go into "powered-down" state safely. Then shut off the CPU rail. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Base on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: tegra30: flowctrl: add cpu_suspend_exter/exit functionJoseph Lo2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The flow controller can help CPU to go into suspend mode (powered-down state). When CPU go into powered-down state, it needs some careful settings before getting into and after leaving. The enter and exit functions do that by configuring appropriate mode for flow controller. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: tegra30: clocks: add CPU low-power function into tegra_cpu_car_opsJoseph Lo2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add suspend, resume and rail_off_ready API into tegra_cpu_car_ops. These functions were used for CPU powered-down state maintenance. One thing needs to notice the rail_off_ready API only availalbe for cpu_g cluster not cpu_lp cluster. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: tegra30: common: enable csite clockJoseph Lo2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable csite (debug and trace controller) clock at init to prevent it be disabled. And this also the necessary clock for CPU be brought up or resumed from a power-gating low power state. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: tegra30: cpuidle: add powered-down state for secondary CPUsJoseph Lo2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This supports power-gated idle on secondary CPUs for Tegra30. The secondary CPUs can go into powered-down state independently. When CPU goes into this state, it saves it's contexts and puts itself to flow controlled WFI state. After that, it will been power gated. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: tegra: cpuidle: add CPU resume functionJoseph Lo2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU suspending on Tegra means CPU power gating. We add a resume function for taking care the CPUs that resume from power gating status. This function was been hooked to the reset handler. We take care everything here before go into kernel. Be aware of that, you may see the legacy power status "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Scott Williams <scwilliams@nvidia.com> Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: tegra: cpuidle: separate cpuidle driver for different chipsJoseph Lo2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The different Tegra chips may have different CPU idle states and data. Individual CPU idle driver make it more easy to maintain. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: tegra: rename the file of "sleep-tXX" to "sleep-tegraXX"Joseph Lo2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the naming consistency under the mach-tegra, we re-name the file of "sleep-tXX" to "sleep-tegraXX" (e.g., sleep-t30 to sleep-tegra30). Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: tegra: cpuidle: replace LP3 with ARM_CPUIDLE_WFI_STATEJoseph Lo2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra CPU idle LP3 state is doing ARM WFI only. So it's same with the common ARM_CPUIDLE_WFI_STATE. Using it to replace LP3 now. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | | | Merge tag 'tegra-for-3.8-soc' of ↵Olof Johansson2012-11-21
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stephen Warren: ARM: tegra: core SoC code enhancements Various small clock initialization table and driver changes to support WiFi modules, SPI controllers, and host1x (graphics/display hardware). Various AHB/APB-related clocks were added to the Tegra30 clock driver. The level 2 cache initialization is now driven by data from device tree, and the cache configuration tweaked. AUXDATA is added to support SPI controllers and host1x. Code to decode Tegra's "speedo" process identification fuses is added. This pull request is based on tegra-for-3.8-cleanup. * tag 'tegra-for-3.8-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (26 commits) ARM: tegra: Add Tegra30 host1x clock support ARM: tegra: Add AUXDATA for Tegra30 host1x ARM: tegra: Add Tegra20 host1x clock support ARM: tegra: Add AUXDATA for Tegra20 host1x ARM: tegra: Tegra30 speedo-based process identification ARM: tegra: Add speedo-based process identification ARM: tegra: flexible spare fuse read function ARM: tegra: Implement 6395/1 for Tegra ARM: tegra: Add OF_DEV_AUXDATA for sflash driver in board dt ARM: tegra: enable data prefetch on L2 ARM: tegra: Add OF_DEV_AUXDATA for SLINK driver in board dt ARM: tegra: common: using OF api for L2 cache init ARM: tegra: dt: add L2 cache controller ARM: tegra30: clocks: add AHB and APB clocks ARM: tegra: set up wlan clocks for tegra dt ARM: tegra: move irammap.h to mach-tegra ARM: tegra: move iomap.h to mach-tegra ARM: tegra: remove <mach/dma.h> ARM: tegra: move tegra-ahb.h out of arch/arm/mach-tegra/ ARM: tegra: remove unnecessary includes of <mach/*.h> ...
| * | | | | ARM: tegra: Add Tegra30 host1x clock supportThierry Reding2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setup the clock parents for the two display controllers and HDMI. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: tegra: Add AUXDATA for Tegra30 host1xThierry Reding2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the OF_DEV_AUXDATA table entries required to associate the proper names with host1x and its children. In turn, this allows the devices to find the required clocks. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: tegra: Add Tegra20 host1x clock supportThierry Reding2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the pll_d frequency table with a few entries to support common HDMI and LVDS display modes and setup the clock parents for the two display controllers and HDMI. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: tegra: Add AUXDATA for Tegra20 host1xThierry Reding2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the OF_DEV_AUXDATA table entries required to associate the proper names with host1x and its children. In turn, this allows the devices to find the required clocks. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: tegra: Tegra30 speedo-based process identificationDanny Huang2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds speedo-based process identification support for Tegra30. Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren s/Tegra3/Tegra30/ in log print, s/T30/Tegra30/ in commit description] Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | | | ARM: tegra: Add speedo-based process identificationDanny Huang2012-11-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Detect CPU and core process ID by checking speedo corner tables. This can provide a more accurate process ID. Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren s/Tegra2/Tegra20/ in log print] Signed-off-by: Stephen Warren <swarren@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-25 04:13:53 -0400