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* agp/uninorth: Fix oops caused by flushing too muchPaul Mackerras2010-06-02
| | | | | | | | | | | | This fixes a sporadic oops at boot on G5 Power Macs. The table_end variable has the address of the last byte of the table. Adding on PAGE_SIZE means we flush too much, and if the page after the table is not mapped for any reason, the kernel will oops. Instead we add on 1 because flush_dcache_range() interprets its second argument as the first byte past the range to be flushed. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/pasemi: Update MAINTAINERS fileOlof Johansson2010-06-02
| | | | | | | | | | PWRficient platform work is definitely in maintenance mode these days, update MAINTAINERS file to reflect reality. Website is long gone as well. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/cell: Fix integer constant warningDenis Kirjanov2010-06-02
| | | | | | | Fix smatch warning: warning: constant 0x800000000 is so big it is long Signed-off-by: Denis Kirjanov <dkirjanov@kernel.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/kprobes: Remove resume_execution() in kprobesAnanth N Mavinakayanahalli2010-06-02
| | | | | | | | | | | | | emulate_step() in kprobe_handler() would've already determined if the probed instruction can be emulated. We single-step in hardware only if the instruction couldn't be emulated. resume_execution() therefore is superfluous -- all we need is to fix up the instruction pointer after single-stepping. Thanks to Paul Mackerras for catching this. Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc/macio: Don't dereference pointer before null checkAndreas Schwab2010-06-02
| | | | | Signed-off-by: Andreas Schwab <schwab@linux-m68k.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* Merge branch 'next' of ↵Linus Torvalds2010-06-01
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: powerpc: Don't export cvt_fd & _df when CONFIG_PPC_FPU is not set powerpc/44x: icon: select SM502 and frame buffer console support powerpc/85xx: Add P1021MDS board support powerpc/85xx: Change MPC8572DS camp dtses for MSI sharing powerpc/fsl_msi: add removal path and probe failing path powerpc/fsl_msi: enable msi sharing through AMP OSes powerpc/fsl_msi: enable msi allocation in all banks powerpc/fsl_msi: fix the conflict of virt_msir's chip_data powerpc/fsl_msi: Add multiple MSI bank support powerpc/kexec: Add support for FSL-BookE powerpc/fsl-booke: Move the entry setup code into a seperate file powerpc/fsl-booke: fix the case where we are not in the first page powerpc/85xx: Enable support for ports 3 and 4 on 8548 CDS powerpc/fsl-booke: Add hibernation support for FSL BookE processors powerpc/e500mc: Implement machine check handler. powerpc/44x: Add basic ICON PPC440SPe board support powerpc/44x: Fix UART clocks on 440SPe powerpc/44x: Add reset-type to katmai.dts powerpc/44x: Adding PCI-E support for PowerPC 460SX based SOC.
| * powerpc: Don't export cvt_fd & _df when CONFIG_PPC_FPU is not setBenjamin Herrenschmidt2010-05-30
| | | | | | | | Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| * Merge commit 'kumar/next' into nextBenjamin Herrenschmidt2010-05-30
| |\ | | | | | | | | | | | | Conflicts: arch/powerpc/sysdev/fsl_msi.c
| | * powerpc/85xx: Add P1021MDS board supportHaiying Wang2010-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | P1021 is a dual e500v2 core based SOC with: * 3 eTSECs (eTSEC1/3 RGMII, eTSEC2 SGMII on this board) * 2 PCIe Controller * 1 USB2.0 controller * eSDHC, eSPI, I2C, DUART * eLBC (NAND, BCSR, PMC0/1) * Security Engine (SEC 3.3.2) * Quicc Engine (QE) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Yu Liu <Yu.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/85xx: Change MPC8572DS camp dtses for MSI sharingLi Yang2010-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the sharing of MSI interrupt through AMP OSes in the mpc8572ds dtses. Signed-off-by: Zhao Chenhui <b26998@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/fsl_msi: add removal path and probe failing pathLi Yang2010-05-24
| | | | | | | | | | | | | | | | | | | | | Also cleanup the probe function. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/fsl_msi: enable msi sharing through AMP OSesLi Yang2010-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make a single PCIe MSI bank shareable through CAMP OSes. The number of MSI used by each core can be configured by dts file. Signed-off-by: Zhao Chenhui <b26998@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/fsl_msi: enable msi allocation in all banksLi Yang2010-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Put all fsl_msi banks in a linked list. The list of banks then can be traversed when allocating new msi interrupts. Also fix failing path of fsl_setup_msi_irqs(). Signed-off-by: Zhao Chenhui <b26998@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/fsl_msi: fix the conflict of virt_msir's chip_dataLi Yang2010-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In fsl_of_msi_probe(), the virt_msir's chip_data have been stored the pointer to struct mpic. We add a struct fsl_msi_cascade_data to store the pointer to struct fsl_msi and msir_index in hanler_data. Otherwise, the pointer to struct mpic will be over-written, and will cause problem when calling eoi() of the irq. Signed-off-by: Zhao Chenhui <b26998@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/fsl_msi: Add multiple MSI bank supportLan Chunhe-B258062010-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale QorIQ P4080 has three MSI banks and the original code can not work well. This patch adds multiple MSI banks support for Freescale processor. Signed-off-by: Lan Chunhe-B25806 <b25806@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/kexec: Add support for FSL-BookESebastian Andrzej Siewior2010-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support kexec on FSL-BookE where the MMU can not be simply switched off. The code borrows the initial MMU-setup code to create the identical mapping mapping. The only difference to the original boot code is the size of the mapping(s) and the executeable address. The kexec code maps the first 2 GiB of memory in 256 MiB steps. This should work also on e500v1 boxes. SMP support is still not available. (Kumar: Added minor change to build to ifdef CONFIG_PPC_STD_MMU_64 some code that was PPC64 specific) Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/fsl-booke: Move the entry setup code into a seperate fileSebastian Andrzej Siewior2010-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch only moves the initial entry code which setups the mapping from what ever to KERNELBASE into a seperate file. No code change has been made here. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/fsl-booke: fix the case where we are not in the first pageSebastian Andrzej Siewior2010-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During boot we change the mapping a few times until we have a "defined" mapping. During this procedure a small 4KiB mapping is created and after that one a 64MiB. Currently the offset of the 4KiB page in that we run is zero because the complete startup up code is in first page which starts at RPN zero. If the code is recycled and moved to another location then its execution will fail because the start address in 64 MiB mapping is computed wrongly. It does not consider the offset to the page from the begin of the memory. This patch fixes this. Usually (system boot) r25 is zero so this does not change anything unless the code is recycled. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/85xx: Enable support for ports 3 and 4 on 8548 CDSAndy Fleming2010-05-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I believe support was disabled due to issues with earlier versions of the board/processor. At worst, adding the ports back into the device tree should result in enabling ports that don't work on older systems, so the default should be to enable them. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/fsl-booke: Add hibernation support for FSL BookE processorsAnton Vorontsov2010-05-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is started as swsusp_32.S modifications, but the amount of #ifdefs made the whole file horribly unreadable, so let's put the support into its own separate file. The code should be relatively easy to modify to support 44x BookEs as well, but since I don't have any 44x to test, let's confine the code to FSL BookE. (The only FSL-specific part so far is 'flush_dcache_L1'.) Signed-off-by: Anton Vorontsov <avorontsov@mvista.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * powerpc/e500mc: Implement machine check handler.Scott Wood2010-05-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the MSCR bit assigments are different in e500mc versus e500, and they are now write-one-to-clear. Some e500mc machine check conditions are made recoverable (as long as they aren't stuck on), most notably L1 instruction cache parity errors. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | Merge commit 'jwb/next' into nextBenjamin Herrenschmidt2010-05-30
| |\ \
| | * | powerpc/44x: icon: select SM502 and frame buffer console supportAnatolij Gustschin2010-05-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enables SM502 frame buffer and framebuffer console in the default config file Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
| | * | powerpc/44x: Add basic ICON PPC440SPe board supportStefan Roese2010-05-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ICON is based on the AppliedMicro 440SPe. It is equipped with 64MByte NOR FLASH, SODIMM, Gigabit ethernet, SM502 on PCI(X), LSI SAS1068E on PCIe0 and custom FPGA on PCIe1. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
| | * | powerpc/44x: Fix UART clocks on 440SPeBenjamin Herrenschmidt2010-05-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code to fixup the serial ports on 440SPe uses the incorrect addresses for these. This fixes it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
| | * | powerpc/44x: Add reset-type to katmai.dtsStefan Roese2010-05-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Katmai needs "reset-type" = "chip reset" (2) to correctly reboot the board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
| | * | powerpc/44x: Adding PCI-E support for PowerPC 460SX based SOC.Tirumala Marri2010-05-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for PCI-e on the AMCC 460SX boards Signed-off-by: Tirumala Marri <tmarri@amcc.com> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* | | | Merge branch 'drm-intel-next' of ↵Linus Torvalds2010-06-01
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel * 'drm-intel-next' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: (41 commits) drm/i915: add HAS_BSD check to i915_getparam drm/i915: Honor sync polarity from VBT panel timing descriptors drm/i915: Unmask interrupt for render engine on Sandybridge drm/i915: Fix PIPE_CONTROL command on Sandybridge drm/i915: Fix up address spaces in slow_kernel_write() drm/i915: Use non-atomic kmap for slow copy paths drm/i915: Avoid moving from CPU domain during pwrite drm/i915: Cleanup after failed initialization of ringbuffers drm/i915: Reject bind_to_gtt() early if object > aperture drm/i915: Check error code whilst moving buffer to GTT domain. drm/i915: Remove spurious warning "Failure to install fence" drm/i915: Rebind bo if currently bound with incorrect alignment. drm/i915: Include pitch in set_base debug statement. drm/i915: Only print "nothing to do" debug message as required. drm/i915: Propagate error from unbinding an unfenceable object. drm/i915: Avoid nesting of domain changes when setting display plane drm/i915: Hold the spinlock whilst resetting unpin_work along error path drm/i915: Only print an message if there was an error drm/i915: Clean up leftover bits from hws move to ring structure. drm/i915: Add CxSR support on Pineview DDR3 ...
| * | | | drm/i915: add HAS_BSD check to i915_getparamZou Nan hai2010-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will let userland only try to use the new media decode functionality when the appropriate kernel is present. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Honor sync polarity from VBT panel timing descriptorsAdam Jackson2010-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I'm actually kind of shocked that it works at all otherwise. Signed-off-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Unmask interrupt for render engine on SandybridgeZhenyu Wang2010-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With splitted engines on Sandybridge, each engine has its own interrupt control as well. This unmasks the interrupt to properly enable pipe control notify event for render engine. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Fix PIPE_CONTROL command on SandybridgeZhenyu Wang2010-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sandybridge(Gen6) has new format for PIPE_CONTROL command, the flush and post-op control are in dword 1 now. This changes command length field for difference between Ironlake and Sandybridge. I tried to test this with noop request and issue PIPE_CONTROL command for each sequence and track notify interrupts, which seems work fine. Hopefully we don't need workaround like on Ironlake for Sandybridge. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Fix up address spaces in slow_kernel_write()Chris Wilson2010-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we now get_user_pages() outside of the mutex prior to performing the copy, we kmap() the page inside the copy routine and so need to perform an ordinary memcpy() and not copy_from_user(). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Use non-atomic kmap for slow copy pathsChris Wilson2010-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we do not have a requirement to be atomic and avoid sleeping whilst performing the slow copy for shmem based pread and pwrite, we can use kmap instead, thus simplifying the code. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Avoid moving from CPU domain during pwriteChris Wilson2010-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can avoid an early clflush when pwriting if we use the current CPU write domain rather than moving the object to the GTT domain for the purposes of the pwrite. This has the advantage of not flushing the presumably hot data that we want to upload into the bo, and of ascribing the clflush to the execution when profiling. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Cleanup after failed initialization of ringbuffersChris Wilson2010-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The callers expect us to cleanup any partially initialised structures before reporting the error. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Reject bind_to_gtt() early if object > apertureChris Wilson2010-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the object is bigger than the entire aperture, reject it early before evicting everything in a vain attempt to find space. v2: Use E2BIG as suggested by Owain G. Ainsworth. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Check error code whilst moving buffer to GTT domain.Chris Wilson2010-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Remove spurious warning "Failure to install fence"Chris Wilson2010-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This particular warning is harmless as we emit during the normal pinning process where the batch buffer requires more fences than is available without eviction. Only if we fail to evict enough fences does this become a problem, so include the requested number of fences in the ultimate *error* message. v2: Remember to compile test even trial patches to remove warnings. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Rebind bo if currently bound with incorrect alignment.Chris Wilson2010-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Whilst pinning the buffer, check that that its current alignment matches the requested alignment. If it does not, rebind. This should clear up any final render errors whilst resuming, for reference: Bug 27070 - [i915] Page table errors with empty ringbuffer https://bugs.freedesktop.org/show_bug.cgi?id=27070 Bug 15502 - render error detected, EIR: 0x00000010 https://bugzilla.kernel.org/show_bug.cgi?id=15502 Bug 13844 - i915 error: "render error detected" https://bugzilla.kernel.org/show_bug.cgi?id=13844 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Include pitch in set_base debug statement.Chris Wilson2010-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the pitch that we about to write into the control register along with the base, offset and coordinates that go into the other control registers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Only print "nothing to do" debug message as required.Chris Wilson2010-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the FBC is already disabled, then we do not even attempt to disable FBC and so there is no point emitting a debug statement at that point, having already emitted one saying why we are disabling FBC. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Propagate error from unbinding an unfenceable object.Chris Wilson2010-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Avoid nesting of domain changes when setting display planeChris Wilson2010-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nesting domain changes will cause confusion when trying to interpret the tracepoints describing the sequence of changes for the object, as well as obscuring the order of operations for the reader of the code. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Hold the spinlock whilst resetting unpin_work along error pathChris Wilson2010-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Delay taking the mutex until we need to and ensure that we hold the spinlock when resetting unpin_work on the error path. Also defer the debugging print messages until after we have released the spinlock. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Only print an message if there was an errorChris Wilson2010-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only report an error if the GPU has actually detected one, otherwise we are just hung. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Clean up leftover bits from hws move to ring structure.Eric Anholt2010-05-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes /debug/dri/0/i915_gem_interrupt output for status page. Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | drm/i915: Add CxSR support on Pineview DDR3Li Peng2010-05-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pineview with DDR3 memory has different latencies to enable CxSR. This patch updates CxSR latency table to add Pineview DDR3 latency configuration. It also adds one flag "is_ddr3" for checking DDR3 setting in MCHBAR. Cc: Shaohua Li <shaohua.li@intel.com> Cc: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Li Peng <peng.li@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | i915: remove unneeded null checksDan Carpenter2010-05-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "encoder" variable can never be null because it is used as loop cursor in a list_for_each_entry() loop. Signed-off-by: Dan Carpenter <error27@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
| * | | | i915/intel_sdvo: remove unneeded null checkDan Carpenter2010-05-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "connector" variable is used as the cursor in a list_for_each_entry() and it's always non-null so we don't need to check it. Signed-off-by: Dan Carpenter <error27@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 22:30:51 -0400