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* ARM: tegra: don't hard-code USB ULPI PHY reset_gpioStephen Warren2012-04-25
| | | | | | | | | Not all boards use GPIO_PV0 as the ULPI PHY reset signal. Instead of hard-coding this GPIO into devices.c, make the board files set it explicitly. This will allow the PHY code to differentiate between set and unset values, and hence know when to read the value from device tree. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: change pll_p_out4's rate to 24MHzStephen Warren2012-04-25
| | | | | | | | | | | pll_p_out4 is used on all/most Tegra boards to drive the cdev2 output pin to provide a reference clock to a ULPI USB PHY. This reference clock must run at 24MHz, and the cdev2 output has no additional dividers. Remove board-paz00.c's now-duplicate initialization of this clock. Reported-by: Marc Dietrich <marvin24@gmx.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: fix pclk rateStephen Warren2012-04-25
| | | | | | | | | Commit 40f9cf0 "ARM: tegra: reparent sclk to pll_c_out1" changed the rate of hclk. Since pclk is derived from that, and only has integer dividers, the pclk rate needs to change in the same fashion, from 54MHz to 60MHz. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: reparent sclk to pll_c_out1Stephen Warren2012-04-25
| | | | | | | | | | pll_p_out4 needs to be used for other purposes. Reparent sclk so that it runs from pll_c. Change sclk's rate to 120MHz from 108MHz since this is the lowest precise rate that can be achieved by dividing the pll_c rate without reducing the sclk rate. (600/5=120, 600/5.5=109.0909..., 600/6=100). Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Add pllc clock init tableAllen Martin2012-04-25
| | | | | | | | | | | | | | | | | pll_c will be used as a clock source. Fill in tegra_pll_c_freq_table[] so that it's possible to explicitly initialize the PLL. NVIDIA's downstream nv-3.1 kernel and the ChromeOS kernel have different pll_c tables. nv-3.1 contains entries for 522MHz and 598MHz output, whereas the ChromeOS kernel contains entries for 600MHz output. I chose to upstream the ChromeOS values for now, since the 600MHz rate appears to match the default rate of this PLL when the HW boots, and it's not clear to me why 522 or 598MHz are more useful. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Olof Johansson <olofj@chromium.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> [swarren: wrote commit description]
* pinctrl: tegra: error reporting cleanupStephen Warren2012-04-25
| | | | | | | | | | Print an explicit error message in various failure cases to allow easier diagnosis. WARN_ON() some internal failures that users/clients shouldn't be able to trigger. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* pinctrl: tegra: debugfs enhancementsStephen Warren2012-04-18
| | | | | | | | | * Only provide debugfs-relates ops when CONFIG_DEBUG_FS is enabled. * Implement pin_config_group_dbg_show op. * Implement pin_config_config_dbg_show op. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: refactor probe handlingStephen Warren2012-04-18
| | | | | | | | | | | | | | Rather than having a single tegra-pinctrl driver that determines whether it's running on Tegra20 or Tegra30, instead have separate drivers for each that call into utility functions to implement the majority of the driver. This change is based on review feedback of the SPEAr pinctrl driver, which had originally copied to Tegra driver structure. This requires that the two drivers have unique names. Update a couple spots in arch/arm/mach-tegra for the name change. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: dt: tegra20: add pinmux to device treeStephen Warren2012-04-18
| | | | | | | | | | This adds a complete pinmux configuration to all Tegra20 device tree files. This allows removal of board-dt-tegra20.c's use of the pinmux board files, and the special device tree handling in board-pinmux.c. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Olof Johansson <olof@lixom.net>
* ARM: dt: tegra cardhu: add pinmux to device treeStephen Warren2012-04-18
| | | | | | | | This adds a minimal pinmux configuration to the Tegra Cardhu device tree. Initially, just the built-in eMMC and SD card slot are configured. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net
* ARM: tegra: Remove pre-pinctrl pinmux driverStephen Warren2012-04-18
| | | | | | | | | The pinctrl driver is now active and used by all boards. Remove the old pinmux driver. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Olof Johansson <olof@lixom.net>
* ARM: tegra: Switch to new pinctrl driverStephen Warren2012-04-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Rename old pinmux and new pinctrl platform driver and DT match table entries, so the new driver gets instantiated. * Re-write board-pinmux.c, so that it uses pinctrl APIs to configura the pinmux. * Re-write board-*-pinmux.c so that the pinmux configuration tables are in pinctrl format. Ventana's pin mux table needed some edits on top of the basic format conversion, since some mux options that were previously marked as reserved are now valid in the new pinctrl driver. Attempting to use the old reserved names will result in a failure. Specifically, groups lpw0, lpw2, lsc1, lsck, and lsda were changed from function rsvd4 to displaya, and group pta was changed from function rsvd2 to hdmi. All boards' pin mux tables needed some edits on top of the based format conversion, since function i2c was split into i2c1 (first general I2C controller) and i2cp (power I2C controller) to better align function definitions with HW blocks. Due to the split of mux tables into pure mux and pull/tristate tables, many entries in the separate Seaboard/Ventana tables could be merged into the common table, since the entries differed only in the portion in one of the tables, not both. Most pin groups allow configuration of mux, tri-state, and pull. However, some don't allow pull configuration, which is instead configured by new groups that only allow pull configuration. This is a reflection of the true HW capabilities, which weren't fully represented by the old pinmux driver. This required adding new pull table entries for those new groups, and setting many other entries' pull configuration to TEGRA_PINCONFIG_DONT_SET. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Olof Johansson <olof@lixom.net>
* gpio: tegra: Hide tegra_gpio_enable/disable()Stephen Warren2012-04-18
| | | | | | | | | | | | | | Recent pinctrl discussions concluded that gpiolib APIs should in fact do whatever is required to mux a GPIO onto pins, by calling pinctrl APIs if required. This change implements this for the Tegra GPIO driver, and removes calls to the Tegra-specific APIs from drivers and board files. Cc: Chris Ball <cjb@laptop.org> Cc: linux-mmc@vger.kernel.org Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Chris Ball <cjb@laptop.org> # for sdhci-tegra.c Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Olof Johansson <olof@lixom.net>
* ARM: tegra: seaboard: Don't gpio_request() ISL29018_IRQStephen Warren2012-04-18
| | | | | | | | | | Don't call gpio_request() or gpio_direction_input() for ISL29018_IRQ. This pin is only used as an IRQ, and hence no GPIO configuration should be necessary; the GPIO/IRQ driver should (and does) perform any required setup when the IRQ is requested. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
* gpio: tegra: configure pins during irq_set_typeStephen Warren2012-04-18
| | | | | | | | | | | When a Tegra GPIO is used as an IRQ, it should be enabled as a GPIO (so the pinmux module isn't driving it as an output) and configured as a GPIO input (so the GPIO module isn't driving it as an output). Set this up automatically whenever an IRQ is requested, so that users of IRQs don't need to do this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
* ARM: tegra: Remove VBUS_GPIO handling from board filesStephen Warren2012-04-18
| | | | | | | | Instead of having board files manually request and initialize USB VBUS GPIOs, fill in the USB driver's platform data and have it do it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
* usb: ehci-tegra: Add vbus_gpio to platform dataStephen Warren2012-04-18
| | | | | | | | | | | | | | | | | Add a vbus_gpio field to platform data. This mirrors the device tree property nvidia,vbus-gpio. This makes the VBUS GPIO handling identical between booting with board files and device tree; the driver always does it. This removes the need for board files to request and initialize the GPIO early during their boot process, perhaps even before the GPIO driver is ready to process the request. Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Alan Stern <stern@rowland.harvard.edu> Cc: linux-usb@vger.kernel.org Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
* pinctrl: show pin name for pingroups in sysfsDong Aisheng2012-04-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Pin name is more useful to users. After change, when cat pingroups in sysfs, it becomes: root@freescale /sys/kernel/debug/pinctrl/20e0000.iomuxc$ cat pingroups registered pin groups: group: uart4grp-1 pin 219 (MX6Q_PAD_KEY_ROW0) pin 218 (MX6Q_PAD_KEY_COL0) group: usdhc4grp-1 pin 305 (MX6Q_PAD_SD4_CMD) pin 306 (MX6Q_PAD_SD4_CLK) pin 315 (MX6Q_PAD_SD4_DAT0) pin 316 (MX6Q_PAD_SD4_DAT1) pin 317 (MX6Q_PAD_SD4_DAT2) pin 318 (MX6Q_PAD_SD4_DAT3) pin 319 (MX6Q_PAD_SD4_DAT4) pin 320 (MX6Q_PAD_SD4_DAT5) pin 321 (MX6Q_PAD_SD4_DAT6) pin 322 (MX6Q_PAD_SD4_DAT7) Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: show pin name when request pinsDong Aisheng2012-04-18
| | | | | | | | Pin name is more useful to users. Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: implement devm_pinctrl_get()/put()Stephen Warren2012-04-18
| | | | | | | | These functions allow the driver core to automatically clean up any allocations made by drivers, thus leading to simplified drivers. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: a minor fix of pin config debug informationDong Aisheng2012-04-18
| | | | | Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: pinconf: fix compilation error if PINCONF is not selectedViresh Kumar2012-04-18
| | | | | | | | | | | | | | | | | | | | | When we compile pinctrl layer for platforms without CONFIG_PINCONF, we get following compilation errors: drivers/built-in.o: In function `pinctrl_show': linux-2.6/drivers/pinctrl/core.c:1116: undefined reference to `pinconf_show_setting' drivers/built-in.o: In function `pinctrl_maps_show': linux-2.6/drivers/pinctrl/core.c:1071: undefined reference to `pinconf_show_map' drivers/built-in.o: In function `pinctrl_init_device_debugfs': linux-2.6/drivers/pinctrl/core.c:1224: undefined reference to `pinconf_init_device_debugfs' make[1]: *** [.tmp_vmlinux1] Error 1 This patch fixes this. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: allow pctldevs to decode pin config in debugfsStephen Warren2012-04-18
| | | | | | | | Add a pinconf op so that pin controller drivers can decode their pin config settings for debugfs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: ifdef CONFIG_DEBUG_FS cleanupStephen Warren2012-04-18
| | | | | | | | | Only provide prototypes for pin{mux,conf}.c debugfs-related functions when both CONFIG_PIN* /and/ CONFIG_DEBUG_FS are enabled, otherwise provide static inlines. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mark non-EXPERIMENTALLinus Walleij2012-04-18
| | | | | | | | | With the finalization of the external driver API and the device tree support, this subsystem is now mature and can be promoted to non-experimental status. Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: tegra: Add complete device tree supportStephen Warren2012-04-18
| | | | | | | | | | Implement pinctrl_ops dt_node_to_map() and dt_free_map(). These allow complete specification of the desired pinmux configuration using device tree. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* dt: Document Tegra20/30 pinctrl bindingStephen Warren2012-04-18
| | | | | | | | | | | | | | | | Define a new binding for the Tegra pin controller, which is capable of defining all aspects of desired pin multiplexing and pin configuration. This is all based on the new common pinctrl bindings. Add Tegra30 binding based on Tegra20 binding. Add some basic stuff that was missing before: * How many and what reg property entries must be provided. * An example. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* dt: Move Tegra20 pin mux binding into new pinctrl directoryStephen Warren2012-04-18
| | | | | | | | | | This places the file in the new location for all pin controller bindings. Also, rename the file using the full compatible value for easier avoidance of conflicts between multiple bindings. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* dt: pinctrl: Document device tree bindingStephen Warren2012-04-18
| | | | | | | | | | | | | | | | | | | | | The core pin controller bindings define: * The fact that pin controllers expose pin configurations as nodes in device tree. * That the bindings for those pin configuration nodes is defined by the individual pin controller drivers. * A standardized set of properties for client devices to define numbered or named pin configuration states, each referring to some number of the afore-mentioned pin configuration nodes. * That the bindings for the client devices determines the set of numbered or named states that must exist. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* dt: add property iteration helpersStephen Warren2012-04-18
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds macros of_property_for_each_u32() and of_property_for_each_string(), which iterate over an array of values within a device-tree property. Usage is for example: struct property *prop; const __be32 *p; u32 u; of_property_for_each_u32(np, "propname", prop, p, u) printk("U32 value: %x\n", u); struct property *prop; const char *s; of_property_for_each_string(np, "propname", prop, s) printk("String value: %s\n", s); Based on work by Rob Herring <robherring2@gmail.com> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: implement pinctrl deferred probingLinus Walleij2012-04-18
| | | | | | | | | | | | | | If drivers try to obtain pinctrl handles for a pin controller that has not yet registered to the subsystem, we need to be able to back out and retry with deferred probing. So let's return -EPROBE_DEFER whenever this location fails. Also downgrade the errors to info, maybe we will even set them to debug once the deferred probing is commonplace. Cc: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: add some error checking for user interfacesDong Aisheng2012-04-18
| | | | | | | | | This patch can avoid kernel oops in case the mux or config function is not supported by driver. Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: fix pinmux_check_ops error checkingDong Aisheng2012-04-18
| | | | | | | | Do not use get_functions_count before checking. Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: replace list_*() with get_*_count()Viresh Kumar2012-04-18
| | | | | | | | | | | | | | | | | | | | | | | | Most of the SoC drivers implement list_groups() and list_functions() routines for pinctrl and pinmux. These routines continue returning zero until the selector argument is greater than total count of available groups or functions. This patch replaces these list_*() routines with get_*_count() routines, which returns the number of available selection for SoC driver. pinctrl layer will use this value to check the range it can choose. This patch fixes all user drivers for this change. There are other routines in user drivers, which have checks to check validity of selector passed to them. It is also no more required and hence removed. Documentation updated as well. Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> [Folded in fix and fixed a minor merge artifact manually] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: mark const init data with __initconst instead of __initdataUwe Kleine-König2012-04-18
| | | | | | | | | | | | | | | As long as there is no other non-const variable marked __initdata in the same compilation unit it doesn't hurt. If there were one however compilation would fail with error: $variablename causes a section type conflict because a section containing const variables is marked read only and so cannot contain non-const variables. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Randy Dunlap <rdunlap@xenotime.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Documentation: pinctrl: add missing spi0_0 grp in exampleViresh Kumar2012-04-18
| | | | | | | Missed one group from the documentation when proofreading. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: fix build when CONFIG_OF && !CONFIG_PINCTRLStephen Warren2012-04-18
| | | | | | | | | | | pinctrl/devicetree.c won't compile when !CONFIG_PINCTRL, since the pinctrl headers don't declare some types when !PINCTRL. Make sure pinctrl/Makefile only attempts to compile devicetree.c when OF && PINCTRL. Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: core device tree mapping table parsing supportStephen Warren2012-04-18
| | | | | | | | | | | | | During pinctrl_get(), if the client device has a device tree node, look for the common pinctrl properties there. If found, parse the referenced device tree nodes, with the help of the pinctrl drivers, and generate mapping table entries from them. During pinctrl_put(), free any results of device tree parsing. Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: implement pinctrl_check_opsStephen Warren2012-04-18
| | | | | | | | | Most code assumes that the pinctrl ops are present. Validate this when registering a pinctrl driver. Remove the one place in the code that was checking whether one of these non-optional ops was present. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: include <linux/bug.h> to prevent compile errorsStephen Warren2012-04-18
| | | | | | | | | | Macros in <linux/pinctrl/machine.h> call ARRAY_SIZE(), the definition of which eventually calls BUILD_BUG_ON_ZERO(), which is defined in <linux/bug.h>. Include that so that every .c file using the pinctrl macros doesn't have to do that itself. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* pinctrl: fix compile error if not select PINMUX supportDong Aisheng2012-04-18
| | | | | | | | | | | | | | | | The pinctrl_register_mappings is defined in core.c, so change the dependent macro from CONFIG_MUX to CONFIG_PINCTRL. The compile error message is: drivers/pinctrl/core.c:886: error: redefinition of 'pinctrl_register_mappings' include/linux/pinctrl/machine.h:160: note: previous definition of 'pinctrl_register_mappings' was here make[2]: *** [drivers/pinctrl/core.o] Error 1 make[1]: *** [drivers/pinctrl] Error 2 make: *** [drivers] Error 2 Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Linux 3.4-rc3Linus Torvalds2012-04-15
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* Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds2012-04-15
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM fixes from Russell King: "Nothing too disasterous, the biggest thing being the removal of the regulator support for vcore in the AMBA driver; only one SoC was using this and it got broken during the last merge window, which then started causing problems for other people. Mutual agreement was reached for it to be removed." * 'fixes' of git://git.linaro.org/people/rmk/linux-arm: ARM: 7386/1: jump_label: fixup for rename to static_key ARM: 7384/1: ThumbEE: Disable userspace TEEHBR access for !CONFIG_ARM_THUMBEE ARM: 7382/1: mm: truncate memory banks to fit in 4GB space for classic MMU ARM: 7359/2: smp_twd: Only wait for reprogramming on active cpus ARM: 7383/1: nommu: populate vectors page from paging_init ARM: 7381/1: nommu: fix typo in mm/Kconfig ARM: 7380/1: DT: do not add a zero-sized memory property ARM: 7379/1: DT: fix atags_to_fdt() second call site ARM: 7366/3: amba: Remove AMBA level regulator support ARM: 7377/1: vic: re-read status register before dispatching each IRQ handler ARM: 7368/1: fault.c: correct how the tsk->[maj|min]_flt gets incremented
| * ARM: 7386/1: jump_label: fixup for rename to static_keyRabin Vincent2012-04-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | c5905afb0 ("static keys: Introduce 'struct static_key'...") renamed struct jump_label_key to struct static_key. Fixup ARM for this to eliminate these build warnings: include/linux/jump_label.h:113:2: warning: passing argument 1 of 'arch_static_branch' from incompatible pointer type include/asm/jump_label.h:17:82: note: expected 'struct jump_label_key *' but argument is of type 'struct static_key *' Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7384/1: ThumbEE: Disable userspace TEEHBR access for !CONFIG_ARM_THUMBEEJonathan Austin2012-04-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when ThumbEE is not enabled (!CONFIG_ARM_THUMBEE) the ThumbEE register states are not saved/restored at context switch. The default state of the ThumbEE Ctrl register (TEECR) allows userspace accesses to the ThumbEE Base Handler register (TEEHBR). This can cause unexpected behaviour when people use ThumbEE on !CONFIG_ARM_THUMBEE kernels, as well as allowing covert communication - eg between userspace tasks running inside chroot jails. This patch sets up TEECR in order to prevent user-space access to TEEHBR when !CONFIG_ARM_THUMBEE. In this case, tasks are sent SIGILL if they try to access TEEHBR. Cc: stable@vger.kernel.org Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Jonathan Austin <jonathan.austin@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7382/1: mm: truncate memory banks to fit in 4GB space for classic MMUWill Deacon2012-04-15
| | | | | | | | | | | | | | | | | | | | | | | | | | If a bank of memory spanning the 4GB boundary is added on a !CONFIG_LPAE kernel then we will hang early during boot since the memory bank will have wrapped around to zero. This patch truncates memory banks for !LPAE configurations when the end address is not representable in 32 bits. Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7359/2: smp_twd: Only wait for reprogramming on active cpusLinus Walleij2012-04-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During booting of cpu1, there is a short window where cpu1 is online, but not active where cpu1 is occupied by waiting to become active. If cpu0 then decides to schedule something on cpu1 and wait for it to complete, before cpu0 has set cpu1 active, we have a deadlock. Typically it's this CPU frequency transition that happens at this time, so let's just not wait for it to happen, it will happen whenever the CPU eventually comes online instead. Cc: Peter Zijlstra <peterz@infradead.org> Cc: stable@kernel.org Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Reviewed-by: Rickard Andersson <rickard.andersson@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7383/1: nommu: populate vectors page from paging_initWill Deacon2012-04-13
| | | | | | | | | | | | | | | | | | | | | | | | Commit 94e5a85b ("ARM: earlier initialization of vectors page") made it the responsibility of paging_init to initialise the vectors page. This patch adds a call to early_trap_init for the !CONFIG_MMU case, placing the vectors at CONFIG_VECTORS_BASE. Cc: Jonathan Austin <jonathan.austin@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7381/1: nommu: fix typo in mm/KconfigWill Deacon2012-04-13
| | | | | | | | | | | | | | | | | | | | The description for the CPU_HIGH_VECTOR Kconfig option for nommu builds doesn't make any sense. This patch fixes up the trivial grammatical error. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 7380/1: DT: do not add a zero-sized memory propertyMarc Zyngier2012-04-13
| | | | | | | | | | | | | | | | | | | | | | | | Some bootloaders are broken enough to expose an ATAG_MEM with a null size. Converting such tag to a memory node leads to an unbootable system. Skip over zero sized ATAG_MEM to avoid this situation. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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