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* ARM: tegra: build assembly files with -march=armv7-aArnd Bergmann2013-04-09
| | | | | | | | | | The tegra assembly files are written for ARMv7 and are not compatible with ARMv6, which leads to build warnings when compiling a dual ARMv6/v7 kernel. Since this code is only ever run on Tegra ARMv7 hardware, we can tell the assembler which architecture level to use. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: Push selects for TWD/SCU into machine entriesStephen Boyd2013-04-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TWD and SCU configs are selected by default as long as MSM_SCORPIONMP is false and/or MCT is false. Implementing the logic this way certainly saves lines in the Kconfig but it precludes those machines which select MSM_SCORPIONMP or MCT from participating in the single zImage effort because when those machines are combined with other SMP capable machines the TWD and SCU are no longer selected by default. Push the select out to the machine entries so that we can compile these machines together and still select the appropriate configs. Cc: Barry Song <baohua.song@csr.com> Acked-by: David Brown <davidb@codeaurora.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by: Pawel Moll <pawel.moll@arm.com> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Simon Horman <horms@verge.net.au> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Viresh Kumar <viresh.linux@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Merge tag 'tegra-for-3.10-multiplatform' of ↵Arnd Bergmann2013-04-09
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/multiplatform From Stephen Warren <swarren@wwwdotorg.org>: ARM: tegra: multi-platform conversion This branch converts Tegra to support multi-platform/single-zImage. One header is made accessible to drivers. The earlyprintk implementation is moved to the multi-platform location. Some Kconfig changes are made to enable multi-platform. Some dead files are deleted. The APIs exposed in the now-global tegra-powergate.h should be replaced with standard reset and power domain APIs in the future. This branch is based on (part of) the previous soc pull request. * tag 'tegra-for-3.10-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra: convert to multi-platform ARM: tegra: move <mach/powergate.h> to <linux/tegra-powergate.h> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * ARM: tegra: convert to multi-platformStephen Warren2013-03-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows Tegra be included in a kernel build that supports multiple SoCs at once, which is useful for distro kernels. This change: * Moves Tegra's Kconfig into its own directory, as seems typical for multi-platform conversions. * Stops selecting some ARM errata that are incompatible with multi- platform. This requires that you use a bootloader that enables the workaround! * Deletes some headers and Makefile.boot that aren't needed now that we support multi-platform. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: move <mach/powergate.h> to <linux/tegra-powergate.h>Stephen Warren2013-03-29
| | | | | | | | | | | | | | | | This is required so that code such as Tegra's PCIe and clock drivers can still access this header file once Tegra is converted to multiplatform, and <mach/> no longer exists. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | Merge branch 'tegra/soc' into next/multiplatformArnd Bergmann2013-04-09
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | This is a dependency for the tegra multiplatform series. Conflicts: drivers/clocksource/tegra20_timer.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | ARM: tegra: pm: remove duplicated include from pm.cWei Yongjun2013-04-05
| | | | | | | | | | | | | | | | | | | | | Remove duplicated include. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: cpuidle: remove redundant parameters for powered-down modeJoseph Lo2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | After the patch series for system suspending support, tegra_idle_lp2_last() no longer uses its parameters cpu_on_time or cpu_off_time, so remove them. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: pm: add platform suspend supportJoseph Lo2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding suspend to RAM support for Tegra platform. There are three suspend mode for Tegra. The difference were below. * LP2: CPU voltage off * LP1: CPU voltage off, DRAM in self-refresh * LP0: CPU + Core voltage off, DRAM in self-refresh After this patch, the LP2 suspend mode will be supported. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: dt: tegra: add bindings of power management configurations for PMCJoseph Lo2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PMC mostly controls the entry and exit of the system from different sleep modes. Different platform or system may have different configurations. The power management configurations of PMC is represented as some properties. The system needs to define the properties when the system supports deep sleep mode (i.e. suspend). Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: devicetree-discuss@lists.ozlabs.org Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: irq: add wake up handlingJoseph Lo2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the wake up handling for legacy irq controller, and using IRQCHIP_MASK_ON_SUSPEND for wake irq handling. Based on the work by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | gpio: tegra: add gpio wakeup source handlingJoseph Lo2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add the gpio wakeup source handling for the Tegra platform. It was be done by enabling the irq for the gpio in the gpio controller and enabling the bank irq of the gpio in the Tegra legacy irq controller when the system going to suspend. Based on the work by: Varun Wadekar <vwadekar@nvidia.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: moving the CPU power timer function to PMC driverJoseph Lo2013-04-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU power timer set up function was related to PMC register. Now moving it to PMC driver. And it also help to clean up the PM related code later. The timer was calculated based on the input clock of PMC. In this patch, we also get the clock from DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | ARM: tegra: add clock source of PMC to device treesJoseph Lo2013-04-03
| |/ | | | | | | | | | | | | Adding the bindings of the clock source of PMC in DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: add speedo-based process id for Tegra114Danny Huang2013-03-19
| | | | | | | | | | | | | | | | | | | | Add speedo-based process identification for Tegra114. Based on the work by: Alex Frid <afrid@nvidia.com> Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren: added include of bug.h] Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: expose chip ID and revisionDanny Huang2013-03-15
| | | | | | | | | | | | | | | | Expose Tegra chip ID and revision in /sys/devices/soc for user mode usage Signed-off-by: Danny Huang <dahuang@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: bring up secondary CPU for Tegra114Joseph Lo2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | The secondary CPU can be brought up by toggling the power in PMC. Then the flow controller will release CPU to go by clearing the reset and clamp signal automatically. Based on the work by: Bo Yan <byan@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: replace the CPU power on function with PMC callJoseph Lo2013-03-11
| | | | | | | | | | | | | | | | | | | | Using the CPU power on function in PMC driver to bring up secondary CPUs, because we are going to re-factor powergate driver to support generic power domain. It will be removed later and added the generic power domain support in PMC driver. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: pmc: add power on function for secondary CPUsJoseph Lo2013-03-11
| | | | | | | | | | | | | | | | | | Adding the power on function for secondary CPUs in PMC driver, this can help us to remove legacy powergate driver and add generic power domain support later. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: pmc: convert PMC driver to support DT onlyJoseph Lo2013-03-11
| | | | | | | | | | | | | | | | | | | | | | The Tegra kernel only support boot from DT now. Clean up the PMC driver to support DT only, that includes: * remove the ifdef of CONFIG_OF * replace the static mapping of PMC addr to map from DT Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: fix the PMC compatible string in DTJoseph Lo2013-03-11
| | | | | | | | | | | | | | | | The PMC HW is not 100% compatible across all Tegra series. We need to specify them in DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: pmc: add specific compatible DT string for Tegra30 and Tegra114Joseph Lo2013-03-11
| | | | | | | | | | | | | | | | The PMC HW is not 100% compatible across all Tegra series. We need to specify each of them in the DT match table. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: refactor tegra{20,30}_boot_secondaryHiroshi Doyu2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "tegra_boot_secondary()" has many condition branches for some Tegra SoC generations in a single function so that it's not easy to compile a kernel only for a single SoC if one wants with some reason, debug purpose(?). This patch provides SoC specific version of boot_secondary(), tegra{20,30}_boot_secondary(). This could allow any combination of SoC to be built. Those boot_secondary functions can be preparation when we ntroduce chip specific function pointers in the future without having chip dependent branches around. Also removed unused definition/prototpye. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> [josephl: remove the Tegra114 part of the original patch] Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * clocksource: tegra: move to of_clk_getPeter De Schrijver2013-03-11
| | | | | | | | | | | | | | | | | | | | The new clockframework introduced DT IDs for each clock. To be able to remove the device registrations, this driver needs to be updated to use the DT IDs. Note that the actual removal of the clk_register_clkdev() calls will be done in a later series. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Unify Device tree board filesHiroshi Doyu2013-03-11
| | | | | | | | | | | | | | Unify board-dt-tegra{30,114} to the Tegra20 DT board file, "tegra.c". Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Rename board-dt-tegra20.c to tegra.cHiroshi Doyu2013-03-11
| | | | | | | | | | | | | | | | This is the preparation to unify "board-dt-tegra{20,30,114}.c" to a single file "tegra.c". Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Unify tegra{20,30,114}_init_early()Hiroshi Doyu2013-03-11
| | | | | | | | | | | | | | | | Refactored tegra{20,30,114}_init_early() so that we have the unified tegra_init_early(). Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: fix ignored return value of regulator_enableStephen Warren2013-03-11
| | | | | | | | | | | | | | | | | | | | | | This fixes: arch/arm/mach-tegra/board-harmony-pcie.c: In function ‘harmony_pcie_init’: arch/arm/mach-tegra/board-harmony-pcie.c:65:18: warning: ignoring return value of ‘regulator_enable’, declared with attribute warn_unused_result [-Wunused-result] Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: fix the logical detection of power on sequence of warm boot CPUsJoseph Lo2013-03-11
| | | | | | | | | | | | | | | | | | | | The warm boot sequence of Tegra30 secondary CPUs should wait for the power ready then removing the clamps. This did not fix any known or unknown issue, but nice to have this fix. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Fix unchecked return valueHiroshi Doyu2013-03-11
| | | | | | | | | | | | | | | | Check a return value for tegra_powergate_remove_clamping(). Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: don't unlock MMIO access to DBGLARJoseph Lo2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to unlock MMIO access to the DBGLAR all the time. Doing so may even cause problems if a SW bug causes writes to that MMIO region. Cortex-A15 processors do not support the CP14 register write the code currently uses to unlock the DBGLAR; the instruction throws an undefined instruction exceptions. This prevents tegra_secondary_startup() from executing on Tegra114, and hence prevents SMP. Remove the code that unlocks this access. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * clk: tegra: No 7.1 super clk dividers on Tegra20Peter De Schrijver2013-03-11
| | | | | | | | | | | | | | | | Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk. Remove the clocks related to the divider. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: remove save/restore of CPU diag registerStephen Warren2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this change, {save,restore}_cpu_arch_register() collaborated to maintain the value of the CPU diagnostic register across power cycles. This was required to maintain any CPU errata workaround enable bits in that register. However, now that the Tegra reset vector code always enables all required workarounds, there is no need to save and restore the diagnostic register; it is always explicitly programmed in the required manner. Hence, remove the save/restore logic. This has the advantage that the kernel always directly controls the value of this register every boot, rather than relying on a bootloader or other kernel code having previously written the correct value into it. This makes CPU0 (which was previously saved/restored) and CPUn (which should have been set up by the reset vector) be controlled in exactly the same way, which is easier to debug/find/... In particular, when converting Tegra to a multi-platform kernel, the CPU0 diagnostic register value initially comes from the bootloader. Most Tegra bootloaders don't yet enable all required CPU bug workarounds. The previous commit updates the kernel to do so on any CPU power cycle. However, the save/restore code ends up over-writing the value with the old bootloader-driven value instead of the now more-likely-to-be-correct kernel value! Even irrespective of multi-platform conversion, this change limits the kernel's exposure to any WARs the bootloader didn't enable for CPU0: on the very first LP2 transition (CPU power-saving which power-cycles the CPU), the correct value will be enabled. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: add CPU errata WARs to Tegra reset handlerStephen Warren2013-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU cores in Tegra contain some errata. Workarounds must be applied for these every time a CPU boots. Implement those workarounds directly in the Tegra-specific CPU reset vector. Many of these workarounds duplicate code in the core ARM kernel. However, the core ARM kernel cannot enable those workarounds when building a multi-platform kernel, since they require writing to secure- only registers, and a multi-platform kernel often does not run in secure mode, and also cannot generically/architecturally detect whether it is running in secure mode, and hence cannot either unconditionally or conditionally apply these workarounds. Instead, the workarounds must be applied in architecture-specific reset code, which is able to have more direct knowledge of the secure/normal state. On Tegra, we will be able to detect this using a non-architected register in the future, although we currently assume the kernel runs only in secure mode. Other SoCs may never run the kernel in secure mode, and hence always rely on a secure monitor to enable the workarounds, and hence never implement them in the kernel. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: dts: tegra: fix the activate polarity of cd-gpio in mmc hostJoseph Lo2013-03-11
| | | | | | | | | | | | | | | | The GPIO pin of SD slot card detection should active low. Signed-off-by: Joseph Lo <josephl@nvidia.com> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | Merge tag 'mxs-multiplatform-3.10' of ↵Arnd Bergmann2013-04-09
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/shawnguo/linux-2.6 into next/multiplatform From Shawn Guo <shawn.guo@linaro.org>: The mxs multiplatform support for 3.10: * It enables the multiplatform build for mach-mxs platform. * tag 'mxs-multiplatform-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: mxs: enable multiplatform build ARM: mxs: rename debug-macro.S for multiplatform build ARM: mxs: call mxs_pm_init() as a machine_desc hook Conflicts: arch/arm/Kconfig.debug Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | ARM: mxs: enable multiplatform buildShawn Guo2013-04-04
| | | | | | | | | | | | | | | | | | | | | Remove files that are not needed by multiplatform build, and make necessary changes on Kconfig to enable multiplatform build. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mxs: rename debug-macro.S for multiplatform buildShawn Guo2013-04-04
| | | | | | | | | | | | | | | | | | | | | Rename arch/arm/mach-mxs/include/mach/debug-macro.S to arch/arm/include/debug/mxs.S for multiplatform build. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mxs: call mxs_pm_init() as a machine_desc hookShawn Guo2013-04-04
| | | | | | | | | | | | | | | | | | | | | The device_initcall is not a friend of multiplatform build. Call mxs_pm_init() as a machine_desc hook instead of device_initcall. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | | Merge branch 'mxs/cleanup' into next/multiplatformArnd Bergmann2013-04-09
|\| | | | | | | | | | | | | | | | | | | | | | | | | | This is a dependency for mxs/multiplatform Signed-off-by: Arnd Bergmann <arnd@arndb.de> Conflicts: drivers/clocksource/Makefile
| * | clocksource: mxs_timer: Add semicolon at end of lineFabio Estevam2013-04-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following build error: drivers/clocksource/mxs_timer.c:304:1: error: expected ',' or ';' at end of input Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mxs: remove unused headersShawn Guo2013-04-01
| | | | | | | | | | | | | | | | | | | | | Most of the stuff in the headers are used nowhere now. Move a few things that are useful for mach-mxs.c into there and remove the headers. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mxs: merge imx23 and imx28 into one machine_descShawn Guo2013-04-01
| | | | | | | | | | | | | | | | | | | | | Most of the function hooks are same between imx23 and imx28 machine_desc, so merge them into one. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mxs: remove common.hShawn Guo2013-04-01
| | | | | | | | | | | | | | | | | | | | | | | | All three remaining functions declared in common.h are implemented by clock driver. Create header include/linux/clk/mxs.h to contain them and remove common.h. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mxs: move mxs_get_ocotp() into mach-mxs.cShawn Guo2013-04-01
| | | | | | | | | | | | | | | | | | | | | All the users of mxs_get_ocotp() are in mach-mxs.c. Move the function into mach-mxs.c, make it a static function, and then remove ocotp.c. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mxs: remove mm.cShawn Guo2013-04-01
| | | | | | | | | | | | | | | | | | | | | The static mapping is used nowhere now. Hence mm.c can be removed completely. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mxs: use debug_ll_io_init for low-level debugShawn Guo2013-04-01
| | | | | | | | | | | | | | | | | | | | | | | | The only user of the static mapping done in mx23_map_io and mx28_map_io is low-level debug now. Use debug_ll_io_init() instead, so that the static mapping is used nowhere and can be removed completely later. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mxs: get ocotp base address from device treeShawn Guo2013-04-01
| | | | | | | | | | | | | | | | | | | | | Instead of using the static definitions, get ocotp base address from device tree with mapping. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mxs: remove system.cShawn Guo2013-04-01
| | | | | | | | | | | | | | | | | | | | | | | | There is no user of function mxs_reset_block() now. Let's move mxs_restart() into mach-mxs.c as a static function and remove system.c completely. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mxs: get reset address from device treeShawn Guo2013-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using static address definition, get reset address from device tree with mapping, so that core_initcall mxs_arch_reset_init() can be killed. The "rtc" clock code in mxs_arch_reset_init() seems to be zombie, since there is no clk lookup defined in clock driver at all. Remove it together. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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