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* Merge git://git.kernel.org/pub/scm/linux/kernel/git/nico/orion into devel-stableRussell King2011-05-16
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| * ARM: dove: Consolidate mpp code with platform mpp.Andrew Lunn2011-05-16
| | | | | | | | | | Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
| * ARM: orion5x: Refactor mpp code to use common orion platform mpp.Andrew Lunn2011-05-16
| | | | | | | | | | Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
| * ARM: orion: Refactor the MPP code common in the orion platformAndrew Lunn2011-05-16
| | | | | | | | | | | | | | | | | | | | mv78xx0 and kirkwood use identical mpp code. It should also be possible to rewrite the orion5x mpp to use this platform code. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
| * ARM: orion: Consolidate setup of the crypto engine.Andrew Lunn2011-05-16
| | | | | | | | | | Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
| * ARM: orion: Consolidate SATA platform setup.Andrew Lunn2011-05-16
| | | | | | | | | | Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
| * ARM: orion: Consolidate USB platform setup code.Andrew Lunn2011-05-16
| | | | | | | | | | Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
| * ARM: orion: Consolidate the XOR platform setup code.Andrew Lunn2011-05-16
| | | | | | | | | | Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
| * ARM: orion: Consolidate the platform data setup for the watchdog.Andrew Lunn2011-05-16
| | | | | | | | | | Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
| * ARM: orion: Consolidate SPI initialization.Andrew Lunn2011-05-16
| | | | | | | | | | | | | | | | This change removes the interrupt resource. The driver does not use it. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
| * ARM: orion: Consolidate I2C initialization.Andrew Lunn2011-05-16
| | | | | | | | | | Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
| * ARM: orion: Consolidate ethernet platform dataAndrew Lunn2011-05-16
| | | | | | | | | | Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
| * ARM: kirkwood: Add support for RTC interrupts which allows RTC alarms.Andrew Lunn2011-05-16
| | | | | | | | | | | | | | Tested using the test program in Documentation/rtc.txt Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
| * ARM: orion: Consolidate the creation of the RTC platform data.Andrew Lunn2011-05-16
| | | | | | | | | | Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
| * ARM: orion: Consolidate the creation of the uart platform data.Andrew Lunn2011-05-16
| | | | | | | | | | Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
| * ARM: orion: Rename some constants to macros to make code more identicalAndrew Lunn2011-05-16
| | | | | | | | | | | | | | | | Changing eg 0xffffffff to DMA_BIT_MASK(32) etc allows easier side by side comparision of identical code which can be consolidated. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
| * arm: orion: Use generic irq chipThomas Gleixner2011-05-16
| | | | | | | | | | | | | | | | | | | | The core interrupt chip is a straight forward conversion. The gpio chip is implemented with two instances of the irq_chip_type which can be switched with the irq_set_type function. That allows us to use the generic callbacks and avoids the conditionals in them. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* | Merge branch 'devel-genirq' of ↵Russell King2011-05-16
|\ \ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into devel-stable
| * | arm: omap2/3: Use generic irq chipTony Lindgren2011-05-16
| |/ | | | | | | | | | | | | | | | | | | | | | | | | Use generic irq chip for omap2 & 3. Note that this patch also leaves out the spurious IRQ warning for omap3. This warning should no longer be needed as the interrupt handlers for various devices have implemented the necessayr read-back of the posted write. Signed-off-by: Tony Lindgren <tony@atomide.com>
* | Merge branch 'samsung-irq' of ↵Russell King2011-05-11
|\ \ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc-2.6 into devel-stable
| * | ARM: SAMSUNG: Convert irq-uart to generic irq chipThomas Gleixner2011-05-09
| | | | | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
| * | ARM: SAMSUNG: Convert irq-vic-timer to generic irq chipThomas Gleixner2011-05-09
| | | | | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
| * | ARM: SAMSUNG: S5P: Convert irq-gpioint to generic irq chipThomas Gleixner2011-05-09
| |/ | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
* | Merge branch 'irq-davinci' of ↵Russell King2011-05-11
|\ \ | | | | | | | | | git://gitorious.org/linux-davinci/linux-davinci into devel-stable
| * | arm: davinci: Use generic irq chipThomas Gleixner2011-05-11
| |/ | | | | | | | | | | | | | | | | Simple conversion which simply uses the fact that the second irq chip base address has offset 0x04 to the first one. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-and-Tested-by: Kevin Hilman <khilman@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com>
| * genirq: Add chip suspend and resume callbacksThomas Gleixner2011-04-23
| | | | | | | | | | | | | | | | | | | | | | These callbacks are only called in the syscore suspend/resume code on interrupt chips which have been registered via the generic irq chip mechanism. Calling those callbacks per irq would be rather icky, but with the generic irq chip mechanism we can call this per registered chip. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-arm-kernel@lists.infradead.org
| * genirq: Implement a generic interrupt chipThomas Gleixner2011-04-23
| | | | | | | | | | | | | | | | | | | | | | Implement a generic interrupt chip, which is configurable and is able to handle the most common irq chip implementations. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-arm-kernel@lists.infradead.org Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Tested-by: Tony Lindgren <tony@atomide.com> Tested-by; Kevin Hilman <khilman@ti.com>
| * genirq: Support per-IRQ thread disabling.Paul Mundt2011-04-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for disabling threading on a per-IRQ basis via the IRQ status instead of the IRQ flow, which is necessary for interrupts that don't follow the natural IRQ flow channels, such as those that are virtually created. The new APIs added are simply: irq_set_thread() irq_set_nothread() which follow the rest of the IRQ status routines. Chained handlers also have IRQ_NOTHREAD set on them automatically, making the lack of threading explicit rather than implicit. Subsequently, the nothread flag can be viewed through the standard genirq debugging facilities. [ tglx: Fixed cleanup fallout ] Signed-off-by: Paul Mundt <lethal@linux-sh.org> Link: http://lkml.kernel.org/r/%3C20110406210135.GF18426%40linux-sh.org%3E Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * genirq: irq_desc: Document preflow_handler and affinity_hintGeert Uytterhoeven2011-04-23
| | | | | | | | | | | | | | | | [ tglx: Filled in the FIXME place holders ] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Link: http://lkml.kernel.org/r/%3C1302426113-13808-2-git-send-email-geert%40linux-m68k.org%3E Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * genirq: Update DocBook commentsGeert Uytterhoeven2011-04-23
| | | | | | | | | | | | | | | | | | | | | | Fix some parts to match the actual code. [ tglx: Resolved the FIXMEs Gerd put in ] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Link: http://lkml.kernel.org/r/%3C1302426113-13808-3-git-send-email-geert%40linux-m68k.org%3E Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-doc@vger.kernel.org
| * genirq: Forgotten updates/deletions after removal of compat codeGeert Uytterhoeven2011-04-23
| | | | | | | | | | | | | | | | | | | | commit 0c6f8a8b917ad361319c8ace3e9f28e69bfdb4c1 ("genirq: Remove compat code") removed the compat code, but forgot to update some references in comments and delete some of its documentation. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Link: http://lkml.kernel.org/r/%3C1302426113-13808-1-git-send-email-geert%40linux-m68k.org%3E Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* | Merge branch 'gic-fasteoi' of git://linux-arm.org/linux-2.6-wd into devel-stableRussell King2011-05-11
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| * | ARM: GIC: Convert GIC library to use the IO relaxed operationsSantosh Shilimkar2011-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GIC register accesses today make use of readl()/writel() which prove to be very expensive when used along with mandatory barriers. This mandatory barriers also introduces an un-necessary and expensive l2x0_sync() operation. On Cortex-A9 MP cores, GIC IO accesses from CPU are direct and doesn't go through L2X0 write buffer. A DSB before writel_relaxed() in gic_raise_softirq() is added to be compliant with the Barrier Litmus document - the mailbox scenario. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com>
| * | ARM: gic: use handle_fasteoi_irq for SPIsWill Deacon2011-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the gic uses handle_level_irq for handling SPIs (Shared Peripheral Interrupts), requiring active interrupts to be masked at the distributor level during IRQ handling. On a virtualised system, only the CPU interfaces are virtualised in hardware. Accesses to the distributor must be trapped by the hypervisor, adding latency to the critical interrupt path in Linux. This patch modifies the GIC code to use handle_fasteoi_irq for handling interrupts, which only requires us to signal EOI to the CPU interface when handling is complete. Cascaded IRQ handling is also updated to use the chained IRQ enter/exit functions to honour the flow control of the parent chip. Note that commit 846afbd1 ("GIC: Dont disable INT in ack callback") broke cascading interrupts by forgetting to add IRQ masking. This is no longer an issue because the unmask call is now unnecessary. Tested on Versatile Express and Realview EB (1176 w/ cascaded GICs). Tested-and-reviewed-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Tested-and-acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | ARM: tegra: irq: Add tegra_eoiColin Cross2011-05-11
| | | | | | | | | | | | | | | | | | | | | Implement irq_eoi to allow the GIC irq chip flow controller to be changed to fasteoi. Signed-off-by: Colin Cross <ccross@android.com>
| * | ARM: tegra: irq: Move legacy_irq.c into irq.cColin Cross2011-05-11
| | | | | | | | | | | | | | | | | | | | | | | | Now that irq.c is just an interface layer between the gic and legacy_irq.c, move the contents of legacy_irq.c into irq.c. Signed-off-by: Colin Cross <ccross@android.com>
| * | ARM: tegra: irq: Remove PM supportColin Cross2011-05-11
| | | | | | | | | | | | | | | | | | | | | Tegra PM irq support is being improved, remove it for now until the rest of the platform gets PM support. Signed-off-by: Colin Cross <ccross@android.com>
| * | ARM: tegra: irq: convert to gic arch extensionsColin Cross2011-05-11
| | | | | | | | | | | | | | | | | | | | | | | | Replace the ugly hack that inserts legacy irq controller calls into the irq call paths by reading and replacing the gic irq chip with the new gic arch extensions. Signed-off-by: Colin Cross <ccross@android.com>
| * | ARM: tegra: update GPIO chained IRQ handler to use entry/exit functionsWill Deacon2011-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the Tegra gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. This is required for the GIC to move to fasteoi interrupt handling. Acked-by: Colin Cross <ccross@android.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | ARM: nmk: update GPIO chained IRQ handler to entry/exit functionsWill Deacon2011-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the Nomadik gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. Cc: Rabin Vincent <rabin@rab.in> Cc: Grant Likely <grant.likely@secretlab.ca> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | ARM: msm: update GPIO chained IRQ handler to use entry/exit functionsWill Deacon2011-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the MSM gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. Tested-and-reviewed-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Acked-by: David Brown <davidb@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | ARM: s5pv310: update IRQ combiner to use chained entry/exit functionsWill Deacon2011-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the IRQ combiner chained IRQ handler code to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. This is required for the GIC to move to fasteoi interrupt handling. Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | ARM: omap: update GPIO chained IRQ handler to use entry/exit functionsWill Deacon2011-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the OMAP gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. Cc: Colin Cross <ccross@google.com> Cc: Tony Lindgren <tony@atomide.com> Tested-and-acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | Linux 2.6.39-rc7Linus Torvalds2011-05-09
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| * | vm: fix vm_pgoff wrap in upward expansionHugh Dickins2011-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a626ca6a6564 ("vm: fix vm_pgoff wrap in stack expansion") fixed the case of an expanding mapping causing vm_pgoff wrapping when you had downward stack expansion. But there was another case where IA64 and PA-RISC expand mappings: upward expansion. This fixes that case too. Signed-off-by: Hugh Dickins <hughd@google.com> Cc: stable@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * | Merge branch 'drm-intel-fixes' of ↵Linus Torvalds2011-05-09
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/keithp/linux-2.6 * 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/keithp/linux-2.6: drm/i915/lvds: Only act on lid notify when the device is on drm/i915: fix intel_crtc_clock_get pipe reads after "cleanup cleanup" drm/i915: Only enable the plane after setting the fb base (pre-ILK) drm/i915/dp: Be paranoid in case we disable a DP before it is attached drm/i915: Release object along create user fb error path
| | * | drm/i915/lvds: Only act on lid notify when the device is onAlex Williamson2011-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we're using vga switcheroo, the device may be turned off and poking it can return random state. This provokes an OOPS fixed separately by 8ff887c847 (drm/i915/dp: Be paranoid in case we disable a DP before it is attached). Trying to use and respond to events on a device that has been turned off by the user is in principle a silly thing to do. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org Signed-off-by: Keith Packard <keithp@keithp.com>
| | * | drm/i915: fix intel_crtc_clock_get pipe reads after "cleanup cleanup"Chris Wilson2011-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Despite the fixes in 548f245ba6a31 (drm/i915: fix per-pipe reads after "cleanup"), we missed one neighbouring read that was mistakenly replaced with the reg value in 9db4a9c (drm/i915: cleanup per-pipe reg usage). This was preventing us from correctly determining the mode the BIOS left the panel in for machines that neither have an OpRegion nor access to the VBT, (e.g. the EeePC 700). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: stable@kernel.org Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
| | * | drm/i915: Only enable the plane after setting the fb base (pre-ILK)Chris Wilson2011-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When enabling the plane, it is helpful to have already pointed that plane to valid memory or else we may incur the wrath of a PGTBL_ER. This code preserved the behaviour from the bad old days for unknown reasons... Found by assert_fb_bound_for_plane(). References: https://bugs.freedesktop.org/show_bug.cgi?id=36246 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
| | * | drm/i915/dp: Be paranoid in case we disable a DP before it is attachedChris Wilson2011-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Given that the hardware may be left in a random condition by the BIOS, it is conceivable that we then attempt to clear the DP_PIPEB_SELECT bit without us ever enabling/attaching the DP encoder to a pipe. Thus causing a NULL deference when we attempt to wait for a vblank on that crtc. Reported-and-tested-by: Bryan Christ <bryan.christ@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36314 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36456 Reported-and-tested-by: Bo Wang <bo.b.wang@intel.com> Cc: stable@kernel.org Signed-off-by: Keith Packard <keithp@keithp.com>
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