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* drm/radeon/dce6: fix display powergatingAlex Deucher2013-02-05
| | | | | | | | | | Only enable it when we disable the display rather than at DPMS time since enabling it requires a full modeset to restore the display state. Fixes blank screens in certain cases. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: add Oland pci idsAlex Deucher2013-02-01
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: radeon-asic updates for OlandAlex Deucher2013-02-01
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add ucode loading support for OlandAlex Deucher2013-02-01
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: fill in gpu init for OlandAlex Deucher2013-02-01
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add Oland chip familyAlex Deucher2013-02-01
| | | | | | Oland is a new asic in the SI family. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: switch back to using the DMA ring for VM PT updatesAlex Deucher2013-02-01
| | | | | | | Now that we have switched to using IBs for page table updates, we can switch back the using the DMA ring. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: use IBs for VM page table updates v2Alex Deucher2013-02-01
| | | | | | | | | | | | For very large page table updates, we can exceed the size of the ring. To avoid this, use an IB to perform the page table update. v2(ck): cleanup the IB infrastructure and the use it instead of filling the struct ourself. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com>
* drm/radeon: don't reset the MC on IGPs/APUsAlex Deucher2013-01-31
| | | | | | The MC isn't part of the GPU per se. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: use the reset mask to determine if rings are hungAlex Deucher2013-01-31
| | | | | | | fetch the reset mask and check if the relevant ring flags are set to determine whether the ring is hung or not. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: halt engines before disabling MC (si)Alex Deucher2013-01-31
| | | | | | It's better to halt the engines before we disable the MC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: halt engines before disabling MC (cayman/TN)Alex Deucher2013-01-31
| | | | | | It's better to halt the engines before we disable the MC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: halt engines before disabling MC (evergreen)Alex Deucher2013-01-31
| | | | | | It's better to halt the engines before we disable the MC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: halt engines before disabling MC (6xx/7xx)Alex Deucher2013-01-31
| | | | | | It's better to halt the engines before we disable the MC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: use status regs to determine what to reset (si)Alex Deucher2013-01-31
| | | | | | | When we attempt the reset the GPU, look at the status registers to determine what blocks need to be reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: use status regs to determine what to reset (cayman)Alex Deucher2013-01-31
| | | | | | | When we attempt the reset the GPU, look at the status registers to determine what blocks need to be reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: use status regs to determine what to reset (evergreen)Alex Deucher2013-01-31
| | | | | | | When we attempt the reset the GPU, look at the status registers to determine what blocks need to be reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: use status regs to determine what to reset (6xx/7xx)Alex Deucher2013-01-31
| | | | | | | When we attempt the reset the GPU, look at the status registers to determine what blocks need to be reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: rework GPU reset on cayman/TNAlex Deucher2013-01-31
| | | | | | | Update the code to better match the recommended programming sequence for soft reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: rework GPU reset on cayman/TNAlex Deucher2013-01-31
| | | | | | | Update the code to better match the recommended programming sequence for soft reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: rework GPU reset on evergreenAlex Deucher2013-01-31
| | | | | | | Update the code to better match the recommended programming sequence for soft reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: rework GPU reset on r6xx/r7xxAlex Deucher2013-01-31
| | | | | | | Update the code to better match the recommended programming sequence for soft reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add a bios scratch asic hung helperAlex Deucher2013-01-31
| | | | | | | | Used by all asic families from r600+. Flag for the vbios and later instances of the driver that the GPU is hung. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add additional reset flagsAlex Deucher2013-01-31
| | | | | | This adds further flags for fine grained reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: Deprecate UMS support v2Christian König2013-01-31
| | | | | | | | | | | | | KMS support is out and stable for a couple of years now and the userspace code has deprecated or abandoned the old UMS interface. So make the KMS interface the default and deprecate the UMS interface in the kernel as well. v2: rebased on alex/drm-next-3.9-wip Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* radeon/kms: cleanup async dma packet checkingJerome Glisse2013-01-31
| | | | | | | This simplify and cleanup the async dma checking. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: consolidate redundant macros and constantsIlija Hadzic2013-01-31
| | | | | | | | | | After refactoring the _cs logic, we ended up with many macros and constants that #define the same thing. Clean'em up. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: use common next_reloc functionIlija Hadzic2013-01-31
| | | | | | | | | This patch eliminates ASIC-specific ***_cs_packet_next_reloc functions and hooks up the new common function. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: pull out common next_reloc functionIlija Hadzic2013-01-31
| | | | | | | | | | next_reloc function does the same thing in all ASICs with the exception of R600 which has a special case in legacy mode. Pull out the common function in preparation for refactoring. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: rename r100_cs_dump_packet to radeon_cs_dump_packetIlija Hadzic2013-01-31
| | | | | | | | | | This function is not limited to r100, but it can dump a (raw) packet for any ASIC. Rename it accordingly and move its declaration to radeon.h Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add a check to wait_reg_mem commandIlija Hadzic2013-01-31
| | | | | | | | | | WAIT_REG_MEM on register does not allow the use of PFP. Enforce this restriction when checking packets sent from userland. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: refactor vline packet parsing functionIlija Hadzic2013-01-31
| | | | | | | | | | | | | | vline packet parsing function for R600 and Evergreen+ are the same, except that they use different registers. Factor out the algorithm into a common function that uses register table passed from ASIC-specific caller. This reduces ASIC-specific function to (trivial) setup of register table and call into the common function. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: factor out cs_next_is_pkt3_nop functionIlija Hadzic2013-01-31
| | | | | | | | | | | Once we factored out radeon_cs_packet_parse function, evergreen_cs_next_is_pkt3_nop and r600_cs_next_is_pkt3_nop functions became identical, so they can be factored out into a common function. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: use common cs packet parse functionIlija Hadzic2013-01-31
| | | | | | | | | | We now have a common radeon_cs_packet_parse function that is good for all ASICs. Hook it up and eliminate ASIC-specific versions. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: implement common cs packet parse functionIlija Hadzic2013-01-31
| | | | | | | | | | | | | CS packet parse functions have a lot of in common across all ASICs. Implement a common function and take care of small differences between families inside the function. This patch is a prep for major refactoring and consolidation of CS parsing code. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: fix formattingIlija Hadzic2013-01-31
| | | | | | | | | Preparatory patch: patches to follow will touch a piece of code that had broken indentication, so fix it before touching it. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: remove unused prototype from radeon_csIlija Hadzic2013-01-31
| | | | | | Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: remove unecessary assignmentIlija Hadzic2013-01-31
| | | | | | | | | | length_dw field was assigned twice. While at it, move user_ptr assignment together with all other assignments to p->chunks[i] structure to make the code more readable. Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: switch back to the CP ring for VM PT updatesAlex Deucher2013-01-31
| | | | | | | | | | | | | | For large VM page table updates, we can sometimes generate more packets than there is space on the ring. This happens more readily with the DMA ring since it is 64K (vs 1M for the CP). For now, switch back to the CP. For the next kernel, I have a patch to utilize IBs for VM PT updates which alleviates this problem. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=58354 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: prevent crash in the ring space allocationAlex Deucher2013-01-31
| | | | | | | | | | | | | | | | | If the requested number of DWs on the ring is larger than the size of the ring itself, return an error. In testing with large VM updates, we've seen crashes when we try and allocate more space on the ring than the total size of the ring without checking. This prevents the crash but for large VM updates or bo moves of very large buffers, we will need to break the transaction down into multiple batches. I have patches to use IBs for the next kernel. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: Calling object_unrefer() when creating fb failureliu chuansheng2013-01-31
| | | | | | | | | | When kzalloc() failed in radeon_user_framebuffer_create(), need to call object_unreference() to match the object_reference(). Signed-off-by: liu chuansheng <chuansheng.liu@intel.com> Signed-off-by: xueminsu <xuemin.su@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon/r5xx-r7xx: wait for the MC to settle after MC blackoutAlex Deucher2013-01-31
| | | | | | | | | Some chips seem to need a little delay after blacking out the MC before the requests actually stop. Stop DMAR errors reported by Shuah Khan. Reported-by: Shuah Khan <shuahkhan@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/evergreen+: wait for the MC to settle after MC blackoutAlex Deucher2013-01-31
| | | | | | | | | | | | Some chips seem to need a little delay after blacking out the MC before the requests actually stop. May fix: https://bugs.freedesktop.org/show_bug.cgi?id=56139 https://bugs.freedesktop.org/show_bug.cgi?id=57567 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: protect against div by 0 in backend setupMikko Tiihonen2013-01-30
| | | | | | | | | | | | Make sure at least one RB is enabled in r6xx_remap_render_backend() to avoid an division by zero in some corner cases. See: https://bugzilla.redhat.com/show_bug.cgi?id=892233 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: fix backend map setup on 1 RB sumo boardsAlex Deucher2013-01-30
| | | | | | | | | | | | Need to adjust the backend map depending on which RB is enabled. Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=892233 Reported-by: Mikko Tiihonen <mikko.tiihonen@iki.fi> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: add quirk for RV100 boardAlex Deucher2013-01-29
| | | | | | | | | | | vbios says external TMDS while the board is actually internal TMDS. fixes: https://bugs.freedesktop.org/show_bug.cgi?id=60037 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: add WAIT_UNTIL to the non-VM safe regs list for cayman/TNAlex Deucher2013-01-27
| | | | | | | Newer versions of mesa emit this. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: fix MC blackout on evergreen+Christopher Staite2013-01-27
| | | | | | | | | | | Force the crtc mem requests on/off immediately rather than waiting for the double buffered updates to kick in. Seems we miss the update in certain conditions. Also handle the DCE6 case. Signed-off-by: Christopher Staite <chris@yourdreamnet.co.uk> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intelDave Airlie2013-01-26
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just a few small things: - 2x workaround bits from Chris to fix up the new scanline waits enabled in 3.8 on snb. People who've been struck by this on dual-screen also need to upgrade the ddx. - Dump the kernel version into i915_error_state, we've had a few mixups there recently. - Disable gfx DMAR on gen4 devices, acked by David Woodhouse. * 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel: drm/i915: dump UTS_RELEASE into the error_state iommu/intel: disable DMAR for g4x integrated gfx drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waits drm/i915: Disable AsyncFlip performance optimisations
| * drm/i915: dump UTS_RELEASE into the error_stateDaniel Vetter2013-01-23
| | | | | | | | | | | | | | | | | | Useful for statistics or on overflowing bug reports to keep things all lined up. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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