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* [SPARC64]: Implement rest of generic interrupt hypervisor calls.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Move devino_to_sysino out of pci_sun4v_asm.SDavid S. Miller2006-03-20
| | | | | | It is not PCI specific, it is for all system interrupts. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Range check bus number in SUN4V PCI controller driver.David S. Miller2006-03-20
| | | | | | | It has to be somewhere in the range from pbm->pci_first_busno to pbm->pci_last_busno, inclusive. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Missing 'return' statement in sun4v_pci_init().David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Implement basic pci_sun4v_scan_bus().David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: PCI-SUN4V fixes.David S. Miller2006-03-20
| | | | | | | | | Clear top 8-bits of physical addresses in "ranges" property. This gives the actual physical address. Detect PBM-A vs. PBM-B by checking bit 0x40 of the devhandle. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Use inline patching for critical PTE operations.David S. Miller2006-03-20
| | | | | | | This handles the SUN4U vs SUN4V PTE layout differences with near zero performance cost. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Move PTE field definitions back into asm/pgtable.hDavid S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Don't expect cfg space in PCI PBM ranges on SUN4V.David S. Miller2006-03-20
| | | | | | | PCI cfg space is accessed transparently through the Hypervisor and not through direct cpu PIO operations. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix branch signedness bug in all code patching.David S. Miller2006-03-20
| | | | | | | The bug that hit SUN4V TLB patching exists elsewhere. Make sure we cure all such cases. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Recognize "virtual-console" as input and output console device.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Do not try to synchronize %stick registers on SUN4V.David S. Miller2006-03-20
| | | | | | Writes by privileged code are not allowed. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Do not try to write to %tick or %stick on SUN4V.David S. Miller2006-03-20
| | | | | | | Writes by privileged code are disallowed. The hypervisor manages the non-privileged bit. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix mondo queue allocations.David S. Miller2006-03-20
| | | | | | | | | | We have to use bootmem during init_IRQ and page alloc for sibling cpu calls. Also, fix incorrect hypervisor call return value checks in the hypervisor SMP cpu mondo send code. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Deal with PTE layout differences in SUN4V.David S. Miller2006-03-20
| | | | | | | | | | Yes, you heard it right, they changed the PTE layout for SUN4V. Ho hum... This is the simple and inefficient way to support this. It'll get optimized, don't worry. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Register kernel TSB with hypervisor.David S. Miller2006-03-20
| | | | | | We do this right after we take over the trap table from OBP. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix some SUN4V TLB miss bugs.David S. Miller2006-03-20
| | | | | | | | | | Code patching did not sign extend negative branch offsets correctly. Kernel TLB miss path needs patching and %g4 register preservation in order to handle SUN4V correctly. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix typo in sun4v_patch().David S. Miller2006-03-20
| | | | | | Second instruction offset is '4' not '3'. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix sun4v early bootup.David S. Miller2006-03-20
| | | | | | | | | | | | prom_sun4v_name should be "sun4v" not "SUNW,sun4v" Also, this is too early to make use of the .sun4v_Xinsn_patch code patching, so just check things manually. This gets us at least to prom_init() on Niagara. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix some Niagara memcpy() bugs.David S. Miller2006-03-20
| | | | | | | | | | | We need to restore the %asi register properly. For the kernel this means get_fs(), for user this means ASI_PNF. Also, NGcopy_to_user.S was including U3memcpy.S instead of NGmemcpy.S, oops :-) Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Handle hypervisor case correctly in copy_tsb().David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add SUN4V Hypervisor Console driver.David S. Miller2006-03-20
| | | | | | | | | | Since it can do things like BREAK and HUP, we implement this as a serial uart driver. This still needs interrupt probing code, as I haven't figured out how interrupts will work or be probed for on SUN4V yet. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fetch bootup time of day from Hypervisor.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Simplify sun4v TLB handling using macros.David S. Miller2006-03-20
| | | | | | | | | | | There was also a bug in sun4v_itlb_miss, it loaded the MMU Fault Status base into %g3 instead of %g2. This pointed out a fast path for TSB miss processing, since we have %g2 with the MMU Fault Status base, we can use that to quickly load up the PGD phys address. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.David S. Miller2006-03-20
| | | | | | | | | | | | | This is where the virtual address of the fault status area belongs. To set it up we don't make a hypervisor call, instead we call OBP's SUNW,set-trap-table with the real address of the fault status area as the second argument. And right before that call we write the virtual address into ASI_SCRATCHPAD vaddr 0x0. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: First cut at SUN4V PCI IOMMU handling.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix hypervisor call arg passing.David S. Miller2006-03-20
| | | | | | Function goes in %o5, args go in %o0 --> %o5. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add HV_PCI_TSBID() macro.David S. Miller2006-03-20
| | | | | | For constructing hypervisor PCI TSB IDs. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Implement SUN4V PCI config space access.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: More SUN4V PCI controller work.David S. Miller2006-03-20
| | | | | | | | | | Add assembler file for PCI hypervisor calls. Setup basic skeleton of SUN4V PCI controller driver. Add 32-bit devhandle to PBM struct, as this is needed for hypervisor calls. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Beginnings of SUN4V PCI controller support.David S. Miller2006-03-20
| | | | | | | | Abstract out IOMMU operations so that we can have a different set of calls on sun4v, which needs to do things through hypervisor calls. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fetch cpu mid properly on sun4v.David S. Miller2006-03-20
| | | | | | | If there is a "cpuid" property, use that. Else suck it out of the top bits of the "reg" property. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC]: Clean up idprom header files.David S. Miller2006-03-20
| | | | | | | Delete unused macros, and use fixed sized types in sparc32 header. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: SUN4V memory exception trap handlers.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Hypervisor TSB context switching.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Implement sun4v TSB miss handlers.David S. Miller2006-03-20
| | | | | | | | | | | When we register a TSB with the hypervisor, so that it or hardware can handle TLB misses and do the TSB walk for us, the hypervisor traps down to these trap when it incurs a TSB miss. Processing is simple, we load the missing virtual address and context, and do a full page table walk. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: kernel/cpu.c needs asm/spitfire.hDavid S. Miller2006-03-20
| | | | | | For 'tlb_type'. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Print ARCH as SUN4V when tlb_type is hypervisor.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Detect sun4v early in boot process.David S. Miller2006-03-20
| | | | | | | | | | | | | We look for "SUNW,sun4v" in the 'compatible' property of the root OBP device tree node. Protect every %ver register access, to make sure it is not touched on sun4v, as %ver is hyperprivileged there. Lock kernel TLB entries using hypervisor calls instead of calls into OBP. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sun4v cross-call sending support.David S. Miller2006-03-20
| | | | | | | | | | | Technically the hypervisor call supports sending in a list of all cpus to get the cross-call, but I only pass in one cpu at a time for now. The multi-cpu support is there, just ifdef'd out so it's easy to enable or delete it later. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Sun4v interrupt handling.David S. Miller2006-03-20
| | | | | | | | | | | | | | | | | Sun4v has 4 interrupt queues: cpu, device, resumable errors, and non-resumable errors. A set of head/tail offset pointers help maintain a work queue in physical memory. The entries are 64-bytes in size. Each queue is allocated then registered with the hypervisor as we bring cpus up. The two error queues each get a kernel side buffer that we use to quickly empty the main interrupt queue before we call up to C code to log the event and possibly take evasive action. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Allocate and register the 4 sun4v mondo queues at bootup.David S. Miller2006-03-20
| | | | | | Needs to occur before we enable PSTATE_IE in %pstate. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Verify all trap_per_cpu assembler offsets in trap_init()David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add sun4v mondo queue bases to struct trap_per_cpu.David S. Miller2006-03-20
| | | | | | | Also, correct TRAP_PER_CPU_FAULT_INFO define, it should be 0x40 not 0x20. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix some comment typos in asm/hypervisor.hDavid S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Patch up mmu context register writes for sun4v.David S. Miller2006-03-20
| | | | | | sun4v uses ASI_MMU instead of ASI_DMMU Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Register per-cpu fault status area with sun4v hypervisor.David S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: asm/cpudata.h needs asm/asi.hDavid S. Miller2006-03-20
| | | | | | For the expansion of __GET_CPUID() on SMP. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Niagara copy/clear page.David S. Miller2006-03-20
| | | | | | | | | | Happily we have no D-cache aliasing issues on these chips, so the implementation is very straightforward. Add a stub in bootup which will be where the patching calls will be made for niagara/sun4v/hypervisor. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patchDavid S. Miller2006-03-20
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
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