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* MIPS: TLB support for hugetlbfs.David Daney2009-06-17
| | | | | | | | | | | | | | | | | The TLB handlers need to check for huge pages and give them special handling. Huge pages consist of two contiguous sub-pages of physical memory. * Loading entrylo0 and entrylo1 need to be handled specially. * The page mask must be set for huge pages and then restored after writing the TLB entries. * The PTE for huge pages resides in the PMD, we halt traversal of the tables there. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add hugetlbfs page defines.David Daney2009-06-17
| | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add support files for hugetlbfs.David Daney2009-06-17
| | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove unused parameters from iPTE_LW.David Daney2009-06-17
| | | | | | | | The l parameter to iPTE_LW() is unused. Remove it and from some of its callers as well. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Staging: Add octeon-ethernet driver files.David Daney2009-06-17
| | | | | | | | | | | | | | | | | | The octeon-ethernet driver supports the sgmii, rgmii, spi, and xaui ports present on the Cavium OCTEON family of SOCs. These SOCs are multi-core mips64 processors with existing support over in arch/mips. The driver files can be categorized into three basic groups: 1) Register definitions, these are named cvmx-*-defs.h 2) Main driver code, these have names that don't start cvmx-. 3) Interface specific functions and other utility code, names starting with cvmx- Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Export erratum function needed by octeon-ethernet driver.David Daney2009-06-17
| | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Cavium-Octeon: Add more chip specific feature tests.David Daney2009-06-17
| | | | | | | | The octeon-ethernet driver needs to check for additional chip specific features, we add them to the octeon_has_feature() framework. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Cavium-Octeon: Add more board type constants.David Daney2009-06-17
| | | | | | | | The bootloader now uses additional board type constants. The octeon-ethernet driver needs some of the new values. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Export cvmx_sysinfo_get needed by octeon-ethernet driver.David Daney2009-06-17
| | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add named alloc functions to OCTEON boot monitor memory allocator.David Daney2009-06-17
| | | | | | | The various Octeon ethernet drivers use these new functions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: devboards: Convert to gpio calls.Manuel Lauss2009-06-17
| | | | | | | Replace a few open-coded GPIO register accesses with gpio calls. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: xxs1500: use linux gpio api.Manuel Lauss2009-06-17
| | | | | | | | Replace a few GPIO register accesses in the board init code with calls to the gpio api. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: MTX-1: Use linux gpio api.Manuel Lauss2009-06-17
| | | | | | | | Replace a few GPIO register accesses in the board init code with calls to the gpio api. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Rewrite GPIO support.Manuel Lauss2009-06-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current in-kernel Alchemy GPIO support is far too inflexible for all my use cases. To address this, the following changes are made: * create generic functions which deal with manipulating the on-chip GPIO1/2 blocks. Such functions are universally useful. * Macros for GPIO2 shared interrupt management and block control. * support for both built-in CONFIG_GPIOLIB and fast, inlined GPIO macros. If CONFIG_GPIOLIB is not enabled, provide linux gpio framework compatibility by directly inlining the GPIO1/2 functions. GPIO access is limited to on-chip ones and they can be accessed as documented in the datasheets (GPIO0-31 and 200-215). If CONFIG_GPIOLIB is selected, two (2) gpio_chip-s, one for GPIO1 and one for GPIO2, are registered. GPIOs can still be accessed by using the numberspace established in the databooks. However this is not yet flexible enough for my uses: My Alchemy systems have a documented "external" gpio interface (fixed, different numberspace) and can support a variety of baseboards, some of which are equipped with I2C gpio expanders. I want to be able to provide the default 16 GPIOs of the CPU board numbered as 0..15 and also support gpio expanders, if present, starting as gpio16. To achieve this, a new Kconfig symbol for Alchemy is introduced, CONFIG_ALCHEMY_GPIO_INDIRECT, which boards can enable to signal that they don't want the Alchemy numberspace exposed to the outside world, but instead want to provide their own. Boards are now respon- sible for providing the linux gpio interface glue code (either in a custom gpio.h header (in board include directory) or with gpio_chips). To make the board-specific inlined gpio functions work, the MIPS Makefile must be changed so that the mach-au1x00/gpio.h header is included _after_ the board headers, by moving the inclusion of the mach-au1x00/ to the end of the header list. See arch/mips/include/asm/mach-au1x00/gpio.h for more info. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Acked-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Remove unused au1000_gpio.h headerManuel Lauss2009-06-17
| | | | | Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47xx: Fix gpio_direction_outputMatthieu Castet2009-06-17
| | | | | | | | gpio_direction_output should also set an output value according to the API. Signed-off-by: Matthieu CASTET <castet.matthieu@free.fr> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ioctl.h: Cleanup.Ralf Baechle2009-06-17
| | | | | | | | | | o Rewrite to use <asm-generic/ioctl.h>. Cuts down the file from 40 to 16 lines. o Delete _IOC_VOID, _IOC_OUT, _IOC_IN and _IOC_INOUT. They were added for 2.1.14 but I was not able to find any user - not even historical ones. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: TXx9: Add TX4939 RNG supportAtsushi Nemoto2009-06-17
| | | | | | | Add platform support for RNG of TX4939 SoC. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: hwrng: Add TX4939 RNG driverAtsushi Nemoto2009-06-17
| | | | | | | | This patch adds support for the integrated RNG of the TX4939 SoC. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Acked-by: Matt Mackall <mpm@selenic.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: TXx9: Add SRAMC supportAtsushi Nemoto2009-06-17
| | | | | | | Add a sysdev to access SRAM in TXx9 SoCs via sysfs. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Sibyte: Remove standalone kernel supportImre Kaloz2009-06-17
| | | | | | | | | CFE is the only supported and used bootloader on the SiByte boards, the standalone kernel support has been never used outside Broadcom. Remove it and make the kernel use CFE by default. Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Sibyte: Remove simulator optionImre Kaloz2009-06-17
| | | | | | | | This patch removes the SiByte simulation Kconfig option, which only modified a printk. Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: RB532: Check irq number when handling GPIO interruptsFlorian Fainelli2009-06-17
| | | | | | | | | | This patch makes sure that we are not going to clear or change the interrupt status of a GPIO interrupt superior to 13 as this is the maximum number of GPIO interrupt source (p.232 of the RC32434 reference manual). Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: RB532: Cleanup cpu-features-overridesFlorian Fainelli2009-06-17
| | | | | | | Remove commented out definitions. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove dead case label.David Daney2009-06-17
| | | | | | | | | CPU_CAVIUM_OCTEON is mips_r2 which is handled before the switch. This label in the switch statement is dead code, so we remove it. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Reviewed by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove execution hazard barriers for Octeon.David Daney2009-06-17
| | | | | | | | | The Octeon has no execution hazards, so we can remove them and save an instruction per TLB handler invocation. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Reviewed by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.David Daney2009-06-17
| | | | | | | | | | Some CPUs do not need ehb instructions after writing CP0 registers. By allowing ehb generation to be overridden in cpu-feature-overrides.h, we can save a few instructions in the TLB handler hot paths. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fold the TLB refill at the vmalloc path if possible.David Daney2009-06-17
| | | | | | | | | | | | | Try to fold the 64-bit TLB refill handler opportunistically at the beginning of the vmalloc path so as to avoid splitting execution flow in half and wasting cycles for a branch required at that point then. Resort to doing the split if either of the newly created parts would not fit into its designated slot. Original-patch-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Replace some magic numbers with symbolic values in tlbex.cDavid Daney2009-06-17
| | | | | | | | | | | The logic used to split the r4000 refill handler is liberally sprinkled with magic numbers. We attempt to explain what they are and normalize them against a new symbolic value (MIPS64_REFILL_INSNS). CC: David VomLehn <dvomlehn@cisco.com> Reviewed-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: TXx9: Add ACLC supportAtsushi Nemoto2009-06-17
| | | | | | | | Add platform support for ACLC of TXx9 SoCs. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add Cavium OCTEON PCI support.David Daney2009-06-17
| | | | | | | | This patch adds support for PCI and PCIe to the base Cavium OCTEON processor support. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add register definitions for PCI.David Daney2009-06-17
| | | | | | | | Here we add the register definitions for the processor blocks used by the following PCI support patch. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: TXx9: Add DMAC supportAtsushi Nemoto2009-06-17
| | | | | | | Add platform support for DMAC of TXx9 SoCs. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* DMA: TXx9 Soc DMA Controller driverAtsushi Nemoto2009-06-17
| | | | | | | | This patch adds support for the integrated DMAC of the TXx9 family. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: TXx9: micro optimization for clocksource and clock_eventAtsushi Nemoto2009-06-17
| | | | | | | | | | Use container structure for clocksource, clock_event_device and hold a pointer to txx9_tmr_reg in it. This saves a few instructions in clocksource and clock_event handlers. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Support 64-byte D-cache line sizeKevin Cernekee2009-06-17
| | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Pass struct device to plat_dma_addr_to_phys()Kevin Cernekee2009-06-17
| | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add size and direction arguments to plat_unmap_dma_mem()Kevin Cernekee2009-06-17
| | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SB1250: Sort out merge mistake.Ralf Baechle2009-06-17
| | | | | | | | A wrong resolution of a merge conflict made the recently deleted wrong error check in sb1250_set_affinity. Send the zombie back to the empire of the undead. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix __ndelay build error and add 'ull' suffix for 32-bit kernelAtsushi Nemoto2009-06-17
| | | | | Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SMTC: Fix formatting difference to linux-mips.org codeRalf Baechle2009-06-17
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix typo resulting in far too long ndelay times.Ralf Baechle2009-06-17
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'next-i2c' of git://aeryn.fluff.org.uk/bjdooks/linuxLinus Torvalds2009-06-17
|\ | | | | | | | | | | | | | | | | * 'next-i2c' of git://aeryn.fluff.org.uk/bjdooks/linux: i2c-stu300: Make driver depend on MACH_U300 i2c-s3c2410: use resource_size() i2c: Use resource_size macro i2c: ST DDC I2C U300 bus driver v3 i2c-bfin-twi: pull in io.h for ioremap()
| * i2c-stu300: Make driver depend on MACH_U300Linus Walleij2009-06-16
| | | | | | | | | | | | | | | | | | | | This makes the stu300 driver for the ST Micro ST DDC I2C bus driver depend on MACH_U300, new platforms reusing this I2C driver will need to add in a similar dependency. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> [ben-linux@fluff.org: re-aranged subject line] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
| * i2c-s3c2410: use resource_size()Ben Dooks2009-06-16
| | | | | | | | | | | | | | Change the usage of res->end-res->start to resource_size(), missed by the last patch to change this. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
| * i2c: Use resource_size macroLinus Walleij2009-06-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This replace all instances in the i2c busses tree of res->end - res->start + 1 with the handy macro resource_size(res) from ioport.h (coming in from platform_device.h). This was created with a simple sed -i -e 's/\([a-z]*\)->end *- *[a-z]*->start *+ *1/resource_size(\1)/g' Then manually replacing the PXA redefiniton of the same kind of macro manually. Recompiled some ARM defconfigs I could find to make a rough test so it shouldn't break anything, though I couldn't see exactly which configs you need for all the drivers. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
| * i2c: ST DDC I2C U300 bus driver v3Linus Walleij2009-06-16
| | | | | | | | | | | | | | | | | | | | | | This adds support for the ST Microelectronics DDC I2C bus driver. This bus is used in the U300 architecture recently added to RMK:s ARM tree. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Reviewed-by: Ben Dooks <ben-linux@fluff.org> Reviewed-by: Jean Delvare <khali@linus-fr.org> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
| * i2c-bfin-twi: pull in io.h for ioremap()Mike Frysinger2009-06-16
| | | | | | | | | | | | | | | | Rather than relying on some of the headers implicitly pulling in io.h, pull it in explicitly our self for ioremap() and friends. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
* | Merge branch 'drm-linus' of ↵Linus Torvalds2009-06-17
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 * 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/radeon: switch to using late_initcall radeon legacy chips: tv dac bg/dac adj updates drm/radeon: introduce kernel modesetting for radeon hardware drm: Add the TTM GPU memory manager subsystem. drm: Memory fragmentation from lost alignment blocks drm/radeon: fix mobility flags on new PCI IDs.
| * | drm/radeon: switch to using late_initcallDave Airlie2009-06-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes an issue where we get inited before fbcon when built-in. Ideally this should work as a non late_initcall, but this fixes it for now. We also don't suggest people build this in (at least distro maintainers). Reported-by: Ryan Hope <rmh3093@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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