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* sched: Remove avg_wakeupMike Galbraith2010-03-11
| | | | | | | | | | | Testing the load which led to this heuristic (nfs4 kbuild) shows that it has outlived it's usefullness. With intervening load balancing changes, I cannot see any difference with/without, so recover there fastpath cycles. Signed-off-by: Mike Galbraith <efault@gmx.de> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1268301062.6785.29.camel@marge.simson.net> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* sched: Rate-limit nohzMike Galbraith2010-03-11
| | | | | | | | | | | | | | | Entering nohz code on every micro-idle is costing ~10% throughput for netperf TCP_RR when scheduling cross-cpu. Rate limiting entry fixes this, but raises ticks a bit. On my Q6600, an idle box goes from ~85 interrupts/sec to 128. The higher the context switch rate, the more nohz entry costs. With this patch and some cycle recovery patches in my tree, max cross cpu context switch rate is improved by ~16%, a large portion of which of which is this ratelimiting. Signed-off-by: Mike Galbraith <efault@gmx.de> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1268301003.6785.28.camel@marge.simson.net> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* sched: Implement group scheduler statistics in one structLucas De Marchi2010-03-11
| | | | | | | | | | | | | Put all statistic fields of sched_entity in one struct, sched_statistics, and embed it into sched_entity. This change allows to memset the sched_statistics to 0 when needed (for instance when forking), avoiding bugs of non initialized fields. Signed-off-by: Lucas De Marchi <lucas.de.marchi@gmail.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <1268275065-18542-1-git-send-email-lucas.de.marchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* sched: Fix pick_next_highest_task_rt() for cgroupsPeter Zijlstra2010-03-11
| | | | | | | | | | | Since pick_next_highest_task_rt() already iterates all the cgroups and is really only interested in tasks, skip over the !task entries. Reported-by: Dhaval Giani <dhaval.giani@gmail.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Tested-by: Dhaval Giani <dhaval.giani@gmail.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* sched: Cleanup: remove unused variable in try_to_wake_up()Dan Carpenter2010-03-11
| | | | | | | | | | | | | We haven't used the "orig_rq" variable since 055a00865d "Fix/add missing update_rq_clock() calls" Signed-off-by: Dan Carpenter <error27@gmail.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Andreas Herrmann <andreas.herrmann3@amd.com> Cc: Gautham R Shenoy <ego@in.ibm.com> Cc: efault@gmx.de LKML-Reference: <20100306111752.GL4958@bicker> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: Fix sched_clock_cpu for systems with unsynchronized TSCDimitri Sivanich2010-03-02
| | | | | | | | | | | | | | | | | | | | | | On UV systems, the TSC is not synchronized across blades. The sched_clock_cpu() function is returning values that can go backwards (I've seen as much as 8 seconds) when switching between cpus. As each cpu comes up, early_init_intel() will currently set the sched_clock_stable flag true. When mark_tsc_unstable() runs, it clears the flag, but this only occurs once (the first time a cpu comes up whose TSC is not synchronized with cpu 0). After this, early_init_intel() will set the flag again as the next cpu comes up. Only set sched_clock_stable if tsc has not been marked unstable. Signed-off-by: Dimitri Sivanich <sivanich@sgi.com> Acked-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <20100301174815.GC8224@sgi.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* Merge branch 'davinci-for-linus' of ↵Linus Torvalds2010-03-01
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci * 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci: (40 commits) DaVinci DM365: Adding support for SPI EEPROM DaVinci DM365: Adding DM365 SPI support DaVinci DM355: Modifications to DM355 SPI support DaVinci: SPI: Adding header file for SPI support. davinci: dm646x: CDCE clocks: davinci_clk converted to clk_lookup davinci: clkdev cleanup: remove clk_lookup wrapper, use clkdev_add_table() DaVinci: DM365: Voice codec support for the DM365 SoC davinci: clock: let clk->set_rate function sleep Add SDA and SCL pin numbers to i2c platform data davinci: da8xx/omap-l1xx: Add EDMA platform data for da850/omap-l138 davinci: build list of unused EDMA events dynamically davinci: Fix edma_alloc_channel api for EDMA_CHANNEL_ANY case davinci: Keep count of channel controllers on a platform davinci: Correct return value of edma_alloc_channel api davinci: add CDCE949 support on DM6467 EVM davinci: add support for CDCE949 clock synthesizer davinci: da850/omap-l138 EVM: register for suspend support davinci: da850/omap-l138: add support for SoC suspend davinci: add power management support DaVinci: DM365: Changing default queue for DM365. ...
| * DaVinci DM365: Adding support for SPI EEPROMSandeep Paulraj2010-03-01
| | | | | | | | | | | | | | | | | | The DM365 Spectrum Digital EVM comes with an EEPROM connected to SPI0. This patch adds support for the SPI EEPROM. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * DaVinci DM365: Adding DM365 SPI supportSandeep Paulraj2010-03-01
| | | | | | | | | | | | | | | | | | | | | | This patch adds SPI init for DM365. It does the following 1) Initializes SPI0 2) Defines resources to be used by SPI0 3) Adds platform data for SPI0 Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * DaVinci DM355: Modifications to DM355 SPI supportSandeep Paulraj2010-03-01
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following 1) Minor change to the SPI clocks making it similar to DM365. 2) Changing the interrupt used by SPI0 3) Adding EDMA resources that can be used by SPI0 4) Adding platform specific data. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * DaVinci: SPI: Adding header file for SPI support.Sandeep Paulraj2010-03-01
| | | | | | | | | | | | | | | | This patch adds "spi.h" header file that will be used by board and architecture specific code. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: dm646x: CDCE clocks: davinci_clk converted to clk_lookupKevin Hilman2010-03-01
| | | | | | | | | | | | | | Remove unneeded 'struct davinci_clk' wrapper around 'struct clk_lookup' and use clk_lookup directly. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: clkdev cleanup: remove clk_lookup wrapper, use clkdev_add_table()Kevin Hilman2010-02-04
| | | | | | | | | | | | | | Remove unneeded 'struct davinci_clk' wrapper around 'struct clk_lookup' and use clkdev_add_table() to add the list of clocks in one go. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * DaVinci: DM365: Voice codec support for the DM365 SoCMiguel Aguilar2010-02-04
| | | | | | | | | | | | | | | | | | This patch adds the generic Voice Codec support for the DM365 based platforms. Signed-off-by: Miguel Aguilar <miguel.aguilar@ridgerun.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: clock: let clk->set_rate function sleepSekhar Nori2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When supporting I2C/SPI based on-board PLLs like CDCE949, it is essential that clk->set_rate be able to sleep. Currently, this is not possible because clk->set_rate is called from within spin-lock in clk_set_rate This patch brings clk->set_rate outside of the spin-lock and lets the individual set_rate implementations achieve serialization through appropiate means. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * Add SDA and SCL pin numbers to i2c platform dataPhilby John2010-02-04
| | | | | | | | | | | | | | | | | | | | | | Patch adds SDA and SCL pin numbers to the i2c platform data structure for Davinci DM355 and DM6446. This at present is used for i2c bus recovery. TODO: Add SDA and SCL pin number information to include all Davinci platforms such as dm355-leopard, dm365, dm646x, da8xx etc. Signed-off-by: Philby John <pjohn@in.mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: da8xx/omap-l1xx: Add EDMA platform data for da850/omap-l138Sudhakar Rajashekhara2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | Currently da850/omap-l138 supports only one channel controller instance of EDMA though EDMA driver as such supports multiple channel controller instances. This patch adds platform data for the 2nd EDMA channel controller. As, the platform data differ between da830/omap-l137 and da850/omap-l138, existing code has been re-shuffled to accommodate this. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: build list of unused EDMA events dynamicallySudhakar Rajashekhara2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the edma_noevent list is passed from platform data. But on some architectures, there will be many EDMA channels which will not be used at all. This patch scans all the platform devices and then builds a list of events which are not being used. The unused event list will be used to allocate EDMA channels in case of EDMA_CHANNEL_ANY usage instead of the edma_noevent being used earlier for this purpose. This patch is based on David Brownells's suggestion at http://article.gmane.org/gmane.linux.davinci/15176. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: Fix edma_alloc_channel api for EDMA_CHANNEL_ANY caseSudhakar Rajashekhara2010-02-04
| | | | | | | | | | | | | | | | | | | | | | Though edma_alloc_channel api was looping through the available channel controllers in EDMA_CHANNEL_ANY case, it was never returning the channel for 2nd channel controller, if 1st channel controller had no free channels. This issue has been fixed with this patch. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: Keep count of channel controllers on a platformSudhakar Rajashekhara2010-02-04
| | | | | | | | | | | | | | | | | | | | | | Some architectures have only one channel controller, but the edma_alloc_channel api loops twice to findout the free channel available in EDMA_CHANNEL_ANY case. A new variable has been introduced to keep count of number of channel controllers being used on a particular architecture. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: Correct return value of edma_alloc_channel apiSudhakar Rajashekhara2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, edma_alloc_channel api is returning the channel number without prepending the controller on which the channel was allocated. So, if a channel is allocated on 2nd controller, calls subsequent to edma_alloc_channel would never know that channel was allocated on the 2nd controller, and continue to operate on 1st controller, resulting in edma failure. This patch fixes this issue. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: add CDCE949 support on DM6467 EVMNageswari Srinivasan2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the CDCE949 reference oscillator to the davinci clock list. On the DM6467T EVM, the CDCE949 is responsible for generating the pixel clock for display. On the DM6467 EVM, this pixel clock was being obtained from an internal source. This is not possible on the DM6467T EVM because of the presence of a 33MHz oscillator. The TSIF module also requires the CDCE949 to generate the data clocks. The actual clock definitions will be added by patches adding support for DM6467T VPIF and TSIF. This patch mearly lays the foundation for that work. Signed-off-by: Nageswari Srinivasan <nageswari@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: add support for CDCE949 clock synthesizerNageswari Srinivasan2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for TI's CDCE949 - a clock synthesizer with 4 PLLs and 9 outputs. It is used on DM6467 EVM. On the EVM, it generates clocks required for VPIF, TSIF and Audio modules. This patch adds it as part of the DaVinci clock framework. Testing: The various frequency outputs on Y1 have been tested using a out-of-tree VPIF video driver supporting HD video. The register values for Y5 frequency outputs have been derived from TSIF driver sources in MontaVista LSP kernel, but actual output has not been tested for lack of TSIF driver which actually works on the latest kernel. Signed-off-by: Nageswari Srinivasan <nageswari@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: da850/omap-l138 EVM: register for suspend supportSekhar Nori2010-02-04
| | | | | | | | | | Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: da850/omap-l138: add support for SoC suspendSekhar Nori2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for registering for suspend-to-RAM functionality on da850/omap-l138 SoCs. da850 supports wakeup based on external event and RTC alarm. Currently only RTC alarm based wakeup is supported. Support for wakeup based on external event will be added as later improvements. For scheduling an alarm event on RTC some useful code is present in Documentation/rtc.txt Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: add power management supportSekhar Nori2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds core power management (suspend-to-RAM) support for DaVinci SoCs. The code depends on the the "deepsleep" feature to suspend the SoC and saves power by gating the input clock. The wakeup can be based on an external event as supported by the SoC. Assembly code (in sleep.S) is added to aid gating DDR2 clocks. Code doing this work should not be accessing DDR2. The assembly code is relocated to SRAM by the code in pm.c The support has been validated on DA850/OMAP-L138 only though the code is (hopefully) generic enough that other SoCs supporting deepsleep feature simply requires SoC specific code to start using this driver. Note that all the device drivers don't support suspend/resume still and are being worked on. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * DaVinci: DM365: Changing default queue for DM365.Sandeep Paulraj2010-02-04
| | | | | | | | | | | | | | | | | | In DM365 Q0, Q1 and Q2 are used by codecs. LSP drivers should use Q3. This patch changes the default queue for DM365. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: clock: Check CLK_PSC flag before disabling PSCChaithrika U S2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | Some modules do not have PSC to control their clocks. The 'lpsc' field in the clk structure is 0 for such clocks. In the clock disable function check for CLK PSC flag before disabling the PSC. If this is not taken care of then it may so happen that module controlled by LPSC 0 is erroneously disabled. Signed-off-by: Chaithrika U S <chaithrika@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * TI Davinci EMAC : Abstract Buffer address translation logic.Sriramakrishnan2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | When programming the DMA engine, the next pointers must be programmed with physical address as seen from the DMA master address space. This address may be different from physical address of the buffer RAM area. This patch abstracts the buffer address translation logic. Signed-off-by: Sriramakrishnan <srk@ti.com> Acked-by: Chaithrika U S <chaithrika@ti.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * TI Davinci EMAC : add platform specific interrupt enable/disable logic.Sriramakrishnan2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | On certain SOCs, the EMAC controller is interfaced with a wrapper logic for handling interrupts. This patch implements a platform specific hook to cater to platforms that require custom interrupt handling logic Signed-off-by: Sriramakrishnan <srk@ti.com> Acked-by: Chaithrika U S <chaithrika@ti.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * TI Davinci EMAC : Re-use driver for other platforms.Sriramakrishnan2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | The davinci EMAC peripheral is also available on other TI platforms -notably TI AM3517 SoC. This patch modifies the config option and the platform structure header files so that the driver can be reused on non-davinci platforms as well. Signed-off-by: Sriramakrishnan <srk@ti.com> Acked-by: Chaithrika U S <chaithrika@ti.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: da850/omap-l138: Enable 4-bit eccSudhakar Rajashekhara2010-02-04
| | | | | | | | | | | | | | | | This patch initializes the platform data to enable 4-bit ecc support on DA850/OMAP-L138. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: da850/omap-l138: Modify NOR partition infoSudhakar Rajashekhara2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | On DA850/OMAP-L138, NOR flash partition was starting from offset ZERO erasing the UBL and u-boot when the complete NOR is erased. This patch moves the start of the partition to 512K, after the bootloaders and u-boot env variables. This patch also creates a new partition on NOR Flash to store Linux kernel image. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: move /proc/davinci_clocks to debugfsSekhar Nori2010-02-04
| | | | | | | | | | | | | | | | | | | | | | Move /proc/davinci_clocks to /sys/kernel/debug/davinci_clocks (debugfs). debugfs is more suited for this since the clock dump is debug information. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: make /proc/davinci_clocks display multi-rooted clock treeSekhar Nori2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | This patch modifies clock dump to take care of clock tress rooted at multiple oscillators. Current code assumes the entire tree is rooted on a single oscillator. When using off-chip clock synthesizers, some of the clocks can be obtained from a different on-board oscillator. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: add support for DM6467T EVMSekhar Nori2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DM6467T (T for Turbo) is a newer and faster DM6467 part from TI. The new part supports 1080p video and has the ARM running at 495MHz. More SoC information: http://focus.ti.com/docs/prod/folders/print/tms320dm6467t.html Spectrum Digital, Inc has a new EVM for this part. It is _mostly_ same as the older DM6467 EVM except for a 33MHz crystal input and THS8200 video encoder for 1080p support. The meat of this patch is dedicated to initializing the crystal frequency from EVM board file. Additional notes: I did consider some alternative ways to make the crystal input board specific including - (1) having board code initialize the crystal frequency using the first member of soc_info->cpu_clks array (2) introducing a new ref_clk_rate member in soc_info structure. But, the current way seems to be the simplest and least intruding considering that both the clock array and SoC info structure are actually private to the SoC file. Also the fact that davinci_common_init() initializes both the soc_info and clocks in one go. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: board-dm646x-evm.c: arrange related code togetherSekhar Nori2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently all the #defines and static variables in the board-dm646x-evm.c file are located right at the start of the file because of which the related code is not together - making reading the code difficult. This patch moves around the code keeping related code together. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: explain CLOCK_TICK_RATE of 27MHz in include/mach/timex.hSekhar Nori2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | Leave a comment explaining the constant value of 27Mhz used in include/mach/timex.h for all DaVinci platforms. Many of the platforms actually run at 24MHz timer frequency (Eg. EVMs of DM355, DM365 and OMAP-L1). The comment also serves as a porting alert. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: da850/omap-l138: create static map for SRAMSekhar Nori2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | Create static map for internal SRAM and populate SRAM base and size in soc_info structure to allow SRAM allocation functions from arch/arm/mach-davinci/sram.c to work. On DA850 SRAM is used for suspend-to-RAM implementation in places where DDR2 cannot be accessed as its clocks are stopped. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: da850/omap-l138: unlock PLL registers during initSekhar Nori2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On omap-l1 devices the PLL registers can be locked from writes. Currently the cpufreq rate setting code unlocks PLL0 before the write actually happens. With suspend support getting added PLL1 registers need be be unlocked as well. To facilitate this, unlock both PLLs during the init time itself. This also obviates the need to unlock PLL registers for each CPUFreq transtition. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: cpuidle: move mapping of DDR2 controller registers out of driverSekhar Nori2010-02-04
| | | | | | | | | | | | | | | | | | | | | | When suspend is supported, both cpuidle and suspend code need to work on DDR2 registers. Instead of mapping the DDR2 registers twice, do it once outside of cpuidle driver and let cpuidle driver get the virtual base address of DDR2 registers. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: make it possible to include clock.h and psc.h in assembly codeSekhar Nori2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | psc.h contains register defines for PSC module which need to be accessed in assembly code which helps the DA850/OMAP-L138 SoC go to sleep. Shutting down DDR clock using PSC is a part of the sleep procedure. Also, the PLL related hardware definitions in clock.h are needed in assembly code to bypass the DDR2 PLL. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: move PSC register definitions from psc.c to psc.hSekhar Nori2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The motivation behind the change is to use the same definitions in the assembly code responsible for suspending the SoC, a part of which is to clock gate the DDR2 clock. Note that the assembly code cannot invoke the C function meant for this. The main reason being that stack in DDR2 cannot be accessed while DDR2 clock is being clock gated. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: move DDR2 controller defines to memory.hSekhar Nori2010-02-04
| | | | | | | | | | | | | | | | | | | | | | Move defintions of DDR2 controller registers to memory.h from cpuidle.c. The motivation behind the change is to be able to use these defintions in assembly code that puts DDR2 in self-refresh and enables the SoC to enter suspend state. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: move PLL wait time values to clock.hSekhar Nori2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | As suspend support is added, the code supporting the suspend operation needs to bypass PLLs and needs to access the same wait time values as the PLL code in clock.c. To facilitate this, move the PLL wait times to clock.h where they can be accessed by suspend code. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * davinci: da8xx/omapl1: add support for the second sysconfig moduleSekhar Nori2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | OMAP-L138 adds a second SYSCFG region having useful functionality like deep sleep, pull up/down control and SATA clock stop. This patch makes provision for accessing registers from second SYSCFG region in da8xx code. Note that OMAP-L137 has a single SYSCFG region. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| * DaVinci - Adding platform & board changes for vpfe capture on DM365Murali Karicheri2010-02-04
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds following changes:- 1) add sub device configuration data for TVP5146 used by vpfe capture 2) registers platform devices for vpfe_capture, isif and vpss 3) defines hardware resources for the devices listed under 2) 4) defines clock aliase for isif driver 5) adding setup_pinmux() for isif Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* | Merge branch 'upstream-linus' of ↵Linus Torvalds2010-03-01
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev * 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev: (38 commits) sata_via: Delay on vt6420 when starting ATAPI DMA write ata: Detect Delkin Devices compact flash pata_efar: Enable parallel scanning pata_atiixp: enable parallel scan [libata] pata_atiixp: add locking for parallel scanning [libata] pata_efar: add locking for parallel scanning libata: Pass host flags into the pci helper [libata] pata_marvell: CONFIG_AHCI is really CONFIG_SATA_AHCI libata: Allow pata_legacy to be built on non-ISA but PCI systems pata_pdc202xx_old: fix UDMA mode for PDC2026x chipsets pata_pdc202xx_old: fix UDMA mode for Promise UDMA33 cards [libata] pata_at91: fix backslash-continued string pata_via: store UDMA masks in via_isa_bridges table pata_via: fix address setup timings underlocking pata_serverworks: fix error message pata_serverworks: fix PIO setup for the second channel pata_efar: fix secondary port support pata_cypress: fix PIO timings underclocking pata_cs5535: use correct values for PIO1 and PIO2 data timings pata_cmd64x: remove unused definitions ...
| * | sata_via: Delay on vt6420 when starting ATAPI DMA writeBart Hartgers2010-03-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When writing a disc on certain lite-on dvd-writers (also rebadged as optiarc/LG/...) connected to a vt6420, the ATAPI CDB ends up in the datastream and on the disc, causing silent corruption. Delaying between sending the CDB and starting DMA seems to prevent this. I do not know if there are burners that do not suffer from this, but the patch should be safe for those as well. There are many reports of this issue, but AFAICT no solution was found before. For example: http://lkml.indiana.edu/hypermail/linux/kernel/0802.3/0561.html Signed-off-by: Bart Hartgers <bart.hartgers@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
| * | ata: Detect Delkin Devices compact flashBen Gardner2010-03-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I have a Delkin Devices compact flash card that isn't being recognized using the SATA/PATA drivers. The card is recognized and works with the deprecated ATA drivers. The error I am seeing is: ata1.00: failed to IDENTIFY (device reports invalid type, err_mask=0x0) I tracked it down to ata_id_is_cfa() in include/linux/ata.h. The Delkin card has id[0] set to 0x844a and id[83] set to 0. This isn't what the kernel expects and is probably incorrect. The simplest work-around is to add a check for 0x844a to ata_id_is_cfa(). Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 10:47:43 -0500