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* irqchip: VIC: export vic_init_cascadedArnd Bergmann2014-02-25
| | | | | | | | vic_init_cascaded is called by integrator impd1 code that can be a loadable module, so the function has to be exported. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'mvebu-watchdog-3.15' of git://git.infradead.org/linux-mvebu into ↵Arnd Bergmann2014-02-25
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/drivers mvebu watchdog driver changes for v3.15 - orion watchdog - cleanup and extend driver to support Armada 370 and Armada XP Depends: - tags/irqchip-mvebu-fixes-3.14 (already pulled by tglx) - both are based on v3.14-rc1 * tag 'mvebu-watchdog-3.15' of git://git.infradead.org/linux-mvebu: watchdog: orion: Enable the build on ARCH_MVEBU watchdog: orion: Add support for Armada 370 and Armada XP SoC watchdog: orion: Add per-compatible watchdog start implementation watchdog: orion: Add per-compatible clock initialization watchdog: orion: Introduce per-compatible of_device_id data watchdog: orion: Introduce an orion_watchdog device structure watchdog: orion: Remove unneeded BRIDGE_CAUSE clear watchdog: orion: Make RSTOUT register a separate resource watchdog: orion: Handle the interrupt so it's properly acked watchdog: orion: Make sure the watchdog is initially stopped watchdog: orion: Remove unused macros watchdog: orion: Use atomic access for shared registers watchdog: orion: Add clock error handling Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * watchdog: orion: Enable the build on ARCH_MVEBUEzequiel Garcia2014-02-21
| | | | | | | | | | | | | | | | | | | | | | | | After adding support for Armada 370/XP SoC let's enable the build on these platforms. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * watchdog: orion: Add support for Armada 370 and Armada XP SoCEzequiel Garcia2014-02-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the added infrastructure for handling SoC differences, this commit adds support for the watchdog controller available in Armada 370 and Armada XP SoCs. Also, and because the AXP clock initialization uses of_clk_get_by_name, this commit changes the orion clock initialization to use clk_get() and adds a proper clk_put() on the common exit/error paths. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * watchdog: orion: Add per-compatible watchdog start implementationEzequiel Garcia2014-02-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | To handle differences between SoCs this commit adds per-compatible string start() function for the watchdog kick-off. This is preparation work and makes no functionality changes to the current driver. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * watchdog: orion: Add per-compatible clock initializationEzequiel Garcia2014-02-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Following the introduction of the compatible-data field, it's now possible to further abstract the clock initialization. This will allow to support SoC with a different clock setup. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * watchdog: orion: Introduce per-compatible of_device_id dataEzequiel Garcia2014-02-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds an orion_watchdog_data structure to hold compatible-data information. This allows to remove the driver-wide definition and to be able to add support for multiple compatible-strings in the future. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * watchdog: orion: Introduce an orion_watchdog device structureEzequiel Garcia2014-02-21
| | | | | | | | | | | | | | | | | | | | | | | | | | In order to prepare to support multiple compatible-strings, this commit adds a device structure to hold the driver's state. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * watchdog: orion: Remove unneeded BRIDGE_CAUSE clearEzequiel Garcia2014-02-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | After adding the IRQ request, the BRIDGE_CAUSE bit should be cleared by the bridge interrupt controller. There's no longer a need to do it in the watchdog driver, so we can simply remove it. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * watchdog: orion: Make RSTOUT register a separate resourceEzequiel Garcia2014-02-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support other SoC, it's required to distinguish the 'control' timer register, from the 'rstout' register that enables system reset on watchdog expiration. To prevent a compatibility break, this commit adds a fallback to a hardcoded RSTOUT address. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * watchdog: orion: Handle the interrupt so it's properly ackedEzequiel Garcia2014-02-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DT-enabled plaforms, where the irqchip driver for the brigde interrupt controller is available, can handle the watchdog IRQ properly. Therefore, request the interrupt and add a dummy handler that merely calls panic(). This is done in order to have an initial 'ack' of the interruption, which clears the watchdog state. Furthermore, since some platforms don't have such IRQ, this commit makes the interrupt specification optional. Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * watchdog: orion: Make sure the watchdog is initially stoppedEzequiel Garcia2014-02-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having the watchdog initially fully stopped is important to avoid any spurious watchdog triggers, in case the registers are not in its reset state. If the watchdog rstout is enabled and the watchdog counter running, this initial stop is not performed, to comply with the 'nowayout' parameter. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * watchdog: orion: Remove unused macrosEzequiel Garcia2014-02-21
| | | | | | | | | | | | | | | | | | | | | | | | These are not used anywhere so it's safe to remove them. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * watchdog: orion: Use atomic access for shared registersEzequiel Garcia2014-02-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the timer control register is shared with the clocksource driver, use the recently introduced atomic_io_clear_set() to access such register. Given the watchdog core already provides serialization for all the watchdog ops, this commit allows to remove the spinlock entirely. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * watchdog: orion: Add clock error handlingEzequiel Garcia2014-02-21
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a check for clk_prepare_enable success and introduces an error path to disable the clock properly. Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | Merge tag 'irqchip-mvebu-fixes-3.14' of git://git.infradead.org/linux-mvebu ↵Arnd Bergmann2014-02-25
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/drivers irqchip mvebu fixes for v3.14 - orion: - fixes for clearing bridge cause register, and clearing stale interrupts * tag 'irqchip-mvebu-fixes-3.14' of git://git.infradead.org/linux-mvebu: irqchip: orion: Fix getting generic chip pointer. irqchip: orion: clear stale interrupts in irq_startup irqchip: orion: use handle_edge_irq on bridge irqs irqchip: orion: clear bridge cause register on init This is a dependency for the mvebu watchdog changes. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * irqchip: orion: Fix getting generic chip pointer.Andrew Lunn2014-02-21
| | | | | | | | | | | | | | | | | | | | | | | | | | Enabling SPARSE_IRQ shows up a bug in the irq-orion bridge interrupt handler. The bridge interrupt is implemented using a single generic chip. Thus the parameter passed to irq_get_domain_generic_chip() should always be zero. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Fixes: 9dbd90f17e4f ("irqchip: Add support for Marvell Orion SoCs") Cc: <stable@vger.kernel.org> # v3.11+ Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * irqchip: orion: clear stale interrupts in irq_startupSebastian Hesselbarth2014-02-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Bridge IRQ_CAUSE bits are asserted regardless of the corresponding bit in IRQ_MASK register. To avoid interrupt events on stale irqs, we have to clear them before unmask. This installs an .irq_startup callback to ensure stale irqs are cleared before initial unmask. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Cc: <stable@vger.kernel.org>: f56c0738b5c2: "irqchip: orion: clear bridge cause register on init" Cc: <stable@vger.kernel.org>: 38bd80b84fca: "irqchip: orion: use handle_edge_irq on bridge irqs" Cc: <stable@vger.kernel.org> # v3.10+ Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * irqchip: orion: use handle_edge_irq on bridge irqsSebastian Hesselbarth2014-02-06
| | | | | | | | | | | | | | | | | | | | | | | | Bridge irqs are edge-triggered, i.e. they get asserted on low-to-high transitions and not on the level of the downstream interrupt line. This replaces handle_level_irq by the more appropriate handle_edge_irq. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Cc: <stable@vger.kernel.org>: f56c0738b5c2: "irqchip: orion: clear bridge cause register on init" Cc: <stable@vger.kernel.org> # v3.10+ Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * irqchip: orion: clear bridge cause register on initSebastian Hesselbarth2014-02-06
| | | | | | | | | | | | | | | | | | | | It is good practice to mask and clear pending irqs on init. We already mask all irqs, so also clear the bridge irq cause register. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.10+ Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | Merge tag 'davinci-for-v3.15/nand' of ↵Arnd Bergmann2014-02-25
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers A patch to break dependency of DaVinci NAND driver with mach-davinci. Required for reuse of driver on other platforms (keystone). * tag 'davinci-for-v3.15/nand' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: davinci: aemif: get rid of davinci-nand driver dependency on aemif Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | ARM: davinci: aemif: get rid of davinci-nand driver dependency on aemifIvan Khoronzhuk2014-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem that the set timings code contains the call of Davinci platform function davinci_aemif_setup_timing() which is not accessible if kernel is built for another platform like Keystone. The Keysone platform is going to use TI AEMIF driver. If TI AEMIF is used we don't need to set timings and bus width. It is done by AEMIF driver. To get rid of davinci-nand driver dependency on aemif platform code we moved aemif code to davinci platform. The platform AEMIF code (aemif.c) has to be removed once Davinci will be converted to DT and use ti-aemif.c driver. Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> [nsekhar@ti.com: fixed checkpatch error and a build breakage due to missing include, rebased onto l2-mtd/master] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
* | | Merge tag 'integrator-for-v3.15-1' of ↵Olof Johansson2014-02-21
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/drivers Merge "Integrator/Versatile base patch stack for the v3.15 series" from Linus Walleij: "this is a set of patches I have sent for review and failed to get ACKs from the proper subsystem maintainers after repeated pings. However I now need to have this rotated in linux-next as a base for multiplatform, so please pull it in, it is all ARM drivers anyway. Russell pointed out some things and these have been fixed and iterated in this series." - Move integrator clock definitions to the device tree, alter clock and timer drivers accordingly. - Alter the VIC irqchip driver to support cascaded VICs off a parent IRQ controller. - Update the IM-PD1 plugin code to use managed resources. - Register the VIC on the IM-PD1. - Select the PL061 GPIO block for the IM-PD1 on the Integrator/AP. * tag 'integrator-for-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM: integrator: select GPIO block ARM: integrator: register the IM-PD1 VIC ARM: integrator: use managed resources for the IM-PD1 irqchip: support cascaded VICs irqchip: vic: update the base IRQ member correctly clk: versatile: respect parent rate in ICST clock clk: versatile: pass a parent to the ICST clock ARM: integrator: switch to fetch clocks from device tree ARM: SP804: make Integrator/CP timer pick clock from DT ARM: integrator: define clocks in the device trees Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | ARM: integrator: select GPIO blockLinus Walleij2014-02-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Integrator/AP can be used with a logic module called IM-PD1, which contains a few AMBA PrimeCell devices, one of which is the PL061 GPIO controller. As the lines from this GPIO controller are looped back to devices on the board itself and provides resources back to it, we need to always have GPIO and the PL061 driver available for other devices to work. Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | ARM: integrator: register the IM-PD1 VICLinus Walleij2014-02-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The peripherals on the IM-PD1 has never really been able to properly fire their IRQs to the main FPGA IRQ controller. Cascade it properly and register interrupts for all the devices in the array. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | ARM: integrator: use managed resources for the IM-PD1Linus Walleij2014-02-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch the IM-PD1 driver to use managed resources and cut down on boilerplate. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | irqchip: support cascaded VICsLinus Walleij2014-02-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for a VIC to be cascaded off another IRQ. On the Integrator/AP logical module IM-PD1 there is a VIC cascaded off the central FPGA IRQ controller so this is needed for that to work out. In order for the plug-in board to be able to register all the devices with their IRQs relative to the offset of the base obtained for the cascaded VIC, the base IRQ number is passed back to the caller. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | irqchip: vic: update the base IRQ member correctlyLinus Walleij2014-02-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When passing 0 as the irq base the VIC driver will dynamically allocate a number of consecutive interrupt descriptors at some available number range. Make sure this number is recorded in the state container rather than the passed-in zero argument in this case. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | clk: versatile: respect parent rate in ICST clockLinus Walleij2014-02-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the ICST clock has a parent, respect the rate of the parent when calculating the clock frequency. As this involves modifying the ICST parameter struct, make a cloned copy (the divisor arrays should be safe) so we can update the .ref field. Do not define the reference clock on the Integrator as we have the reference clock from the device tree. Keep it everywhere else. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | clk: versatile: pass a parent to the ICST clockLinus Walleij2014-02-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we want to actually define the parent frequency in the device tree for the ICST clocks, modify the clock registration function to take a parent argument. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | ARM: integrator: switch to fetch clocks from device treeLinus Walleij2014-02-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This atomic commit changes the Integrator clock implementation and the machines to register clocks from the device tree and use these instead of the previous hard-coded clocks. In the clock implementation all hard-coded clocks and the special initialization function call goes away, and is replaced by two compatible strings for the two clocks available on the core module. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | ARM: SP804: make Integrator/CP timer pick clock from DTLinus Walleij2014-02-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This modifies the SP804 driver so that the clock will be taken from the device tree node for the timer. Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Rob Herring <rob.herring@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | ARM: integrator: define clocks in the device treesLinus Walleij2014-02-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the clock definitions to the Integrator/CP and Integrator/AP device trees. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | | | Merge tag 'renesas-soc-for-v3.15' of ↵Olof Johansson2014-02-20
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers Merge "Renesas ARM Based SoC Updates for v3.15" from Simon Horman: * r7s72100 SoC (RZ/A1H) - Add i2c clocks (portion missing from previous patch due to miss-merge) * r8a7791 (R-Car M2) - Add SATA clocks - Add ZS clock - Wait for status on all MSTP clocks -- Add I2C and VIN clocks * r8a7790 (R-Car H2) - Add PCI USB host clock support - Add Audio DMAC, SATA and VIN clocks - Add Audio DMAC support * r8a7779 (R-Car H1) - Wait for status on selected MSTP clocks * tag 'renesas-soc-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7790: Add PCI USB host clock support ARM: shmobile: r7s72100: really add i2c clocks ARM: shmobile: r8a7791: Add SATA clocks ARM: shmobile: r8a7791: Add ZS clock ARM: shmobile: r8a7790: Add SATA clocks ARM: shmobile: r8a7790: Add VIN clock support ARM: shmobile: r8a7790: add Audio DMAC support ARM: shmobile: r8a7790: add Audio DMAC clock ARM: shmobile: r8a7791: Wait for status on all MSTP clocks ARM: shmobile: r8a7791: Add VIN clocks ARM: shmobile: r8a7791: Add I2C clocks ARM: shmobile: r8a7790: Wait for status on all MSTP clocks ARM: shmobile: r8a7779: Wait for status on selected MSTP clocks ARM: shmobile: wait for MSTP clock status to toggle, when enabling it
| * | | | ARM: shmobile: r8a7790: Add PCI USB host clock supportValentine Barshak2014-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds internal PCI USB host clock support. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | ARM: shmobile: r7s72100: really add i2c clocksWolfram Sang2014-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to a merge conflict, addition of the clocks was lost. Tested with RIIC2 on a genmai board. Others untested but hopefully trivial enough to be added. Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> [horms+renesas@verge.net.au: Capitalised "ARM" in subject] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | ARM: shmobile: r8a7791: Add SATA clocksValentine Barshak2014-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds SATA[01] clock support to R8A7791 SoC. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | ARM: shmobile: r8a7791: Add ZS clockValentine Barshak2014-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds fixed ratio zs_clk to R8A7791 clocks. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | ARM: shmobile: r8a7790: Add SATA clocksValentine Barshak2014-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds SATA[01] clock support to R8A7790 SoC. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> [horms+renesas@verge.net.au: resolved trivial conflicts] Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | ARM: shmobile: r8a7790: Add VIN clock supportValentine Barshak2014-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds VIN[0-3] clock support to R8A7790 SoC. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> [horms+renesas@verge.net.au: manually applied] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | ARM: shmobile: r8a7790: add Audio DMAC supportKuninori Morimoto2014-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R-Car H2 has many DMACs (ex SYS-DMAC, 2D-DMAC, Audio-DMAC, USB-DMAC etc) and, these DMAEngine needs DMA slave IDs to use it. This patch adds new DMA slave ID list for r8a7790. There, common part has RCAR_DMA_xxx prefix, and Audio DMAC part has AUDIO_DMAC_SLAVE_xxx prefix. Audio DMAC can be controlled via sh-dma-engine Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | ARM: shmobile: r8a7790: add Audio DMAC clockKuninori Morimoto2014-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Audio DMAC can be controlled via sh-dma-engine Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | ARM: shmobile: r8a7791: Wait for status on all MSTP clocksShinya Kuribayashi2014-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When enabling a module clock by clearing its bit in the MSTP control register, the CPG requires waiting for the status register to signal that the clock has started. Failure to do so will result in returning from the clk_enable() call with the clock potentially still disabled, leading to various race conditions and difficult to debug errors. Enable status wait for all MSTP clocks on the r8a7791. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | ARM: shmobile: r8a7791: Add VIN clocksValentine Barshak2014-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds VIN[0-2] clock support to R8A7791 SoC. Changes in V2: * none. Changes in V3: * capitalized ARM in the subject. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | ARM: shmobile: r8a7791: Add I2C clocksValentine Barshak2014-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds I2C[0-5] clock support to R8A7791 SoC. Changes in V2: * Capitalized ARM in the subject. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | ARM: shmobile: r8a7790: Wait for status on all MSTP clocksShinya Kuribayashi2014-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When enabling a module clock by clearing its bit in the MSTP control register, the CPG requires waiting for the status register to signal that the clock has started. Failure to do so will result in returning from the clk_enable() call with the clock potentially still disabled, leading to various race conditions and difficult to debug errors. Enable status wait for all MSTP clocks on the r8a7790. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | ARM: shmobile: r8a7779: Wait for status on selected MSTP clocksLaurent Pinchart2014-02-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When enabling some of the module clocks by clearing stop bits in the MSTP control registers, the CPG requires waiting for the status registers to signal that the clocks have started. Failure to do so will result in returning from the clk_enable() call with the clock potentially still disabled, leading to various race conditions and difficult to debug errors. Enable status wait for all the r8a7779 MSTP clocks that report their status. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | ARM: shmobile: wait for MSTP clock status to toggle, when enabling itGuennadi Liakhovetski2014-02-03
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On r-/sh-mobile SoCs MSTP clocks are used by the runtime PM to dynamically enable and disable peripheral clocks. To make sure the clock has really started we have to read back its status register until it confirms success. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | | Merge tag 'ext4_for_linus_stable' of ↵Linus Torvalds2014-02-18
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4 Pull ext4 fixes from Ted Ts'o: "Miscellaneous ext4 bug fixes for v3.14" * tag 'ext4_for_linus_stable' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4: jbd2: fix use after free in jbd2_journal_start_reserved() ext4: don't leave i_crtime.tv_sec uninitialized ext4: fix online resize with a non-standard blocks per group setting ext4: fix online resize with very large inode tables ext4: don't try to modify s_flags if the the file system is read-only ext4: fix error paths in swap_inode_boot_loader() ext4: fix xfstest generic/299 block validity failures
| * | | | jbd2: fix use after free in jbd2_journal_start_reserved()Dan Carpenter2014-02-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If start_this_handle() fails then it leads to a use after free of "handle". Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: "Theodore Ts'o" <tytso@mit.edu> Cc: stable@vger.kernel.org
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 19:37:01 -0500