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* MXC: Add a digital audio multiplexer driverSascha Hauer2009-11-14
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* i.MX3: Add sound (ssi) resourcesSascha Hauer2009-11-14
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* i.MX2: Add sound (ssi) resourcesSascha Hauer2009-11-14
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pcm043: Add NAND supportSascha Hauer2009-11-14
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pca100: use correct irq initialisation functionSascha Hauer2009-11-14
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* pca100: Add board to uncompress.hSascha Hauer2009-11-14
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MXC NFC: Fix NFCs address area on i.MX35Juergen Beisert2009-11-14
| | | | | | | The address area of the NFC in the i.MX35 silicon is much larger than 4k. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MXC NFC: Add the clock resource to support NFC in i.MX35Juergen Beisert2009-11-14
| | | | | Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* imx/gpio: Use handle_level_irqUwe Kleine-König2009-11-14
| | | | | | | | | | | | | | | According to Russell King handle_edge_irq is only useful for "edge-based inputs where the controller does not remember transitions with the input masked." So using handle_edge_irq unconditionally for both edge and level irqs is wrong. Testing showed that the controller does remember transitions while the interrupt is masked. So use handle_level_irq unconditionally. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MXC: Add support for ULPI ViewportsDaniel Mack2009-11-14
| | | | | | | | | | | | The ARC USB OTG Core has support for accessing ULPI tranceivers through so called ULPI viewports. Export a set of function for use with the USB OTG framework. Signed-off-by: Daniel Mack <daniel@caiaq.de> Cc: Greg Kroah-Hartman <gregkh@suse.de> Cc: David Brownell <dbrownell@users.sourceforge.net> Cc: linux-usb@vger.kernel.org Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mx31moboard: camera supportValentin Longchamp2009-11-14
| | | | | | | | | We have two mt9t031 cameras that have a muxed bus on the robot. Only one is currently initialized because of limitations in soc_camera that should be removed later. Signed-off-by: Valentin Longchamp <valentin.longchamp@epfl.ch> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mx31moboard: initialize ipu device for all the boardsValentin Longchamp2009-11-14
| | | | | Signed-off-by: Valentin Longchamp <valentin.longchamp@epfl.ch> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mx31moboard: SPI and MC13783 voltage regulator supportValentin Longchamp2009-11-14
| | | | | Signed-off-by: Valentin Longchamp <valentin.longchamp@epfl.ch> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mx31moboard: support for pin linked for battery presence checkValentin Longchamp2009-11-14
| | | | | Signed-off-by: Valentin Longchamp <valentin.longchamp@epfl.ch> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mx31moboard: serial port fixValentin Longchamp2009-11-14
| | | | | | | | | | | | | | We get rid of CTS/RTS lines on uart0 on our platform. This is the port we use as main kernel console. We do not want it to be blocking because of CTS/RTS signals, not allowing the system to boot or print messages. However we often use it with a bluetooth module needing CTS/RTS lines as backup login in case of trouble. To be able to use it, we assert CTS low so that the module can always send chars. Signed-off-by: Valentin Longchamp <valentin.longchamp@epfl.ch> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mx31: various pins used for mx31moboardValentin Longchamp2009-11-14
| | | | | Signed-off-by: Valentin Longchamp <valentin.longchamp@epfl.ch> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Armadillo500 Add support for Seiko Instruments S-35390A rtc over i2c.Alberto Panizzo2009-11-14
| | | | | | | | The RTC chip Seiko Instruments S-35390A is connected to the Application Processor over the second bus i2c with the hard coded address 0x30. Signed-off-by: Alberto Panizzo <maramaopercheseimorto@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Armadillo500 Add i2c second bus support.Alberto Panizzo2009-11-14
| | | | | | | | This add pin allocation an device registration for the second bus i2c. Signed-off-by: Alberto Panizzo <maramaopercheseimorto@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Armadillo500 Correct bus length for SMSC9118 on board chip.Alberto Panizzo2009-11-14
| | | | | | | | | | Armadillo500 Correct bus length for SMSC9118 on board chip. The SMSC9118 network chip is connected to the data bus with a 16 bit interface, not 32 as early suggested. Signed-off-by: Alberto Panizzo <maramaopercheseimorto@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Armadillo500 Add support for onboard GPIO Buttons.Alberto Panizzo2009-11-14
| | | | | | | | There are two low active Buttons on boards. This patch connect those to the Input Subsystem over gpio-keys driver. Signed-off-by: Alberto Panizzo <maramaopercheseimorto@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: MX3: add MX3X_UART1_BASE_ADDR for uncompression on lilly1131Daniel Mack2009-11-14
| | | | | | Reported-by: Jörg Knobloch <knobloch@incostartec.com> Signed-off-by: Daniel Mack <daniel@caiaq.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: MX3: Add pad config for MMC pins on lilly-dbDaniel Mack2009-11-14
| | | | | Signed-off-by: Daniel Mack <daniel@caiaq.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: MX3: add support for mc13783 on lilly-dbDaniel Mack2009-11-14
| | | | | | | | | | The chip is actually located on the module, not on the base board. But other base boards might add more SPI devices, so the spi_board_info struct must be separated from the module code. Signed-off-by: Daniel Mack <daniel@caiaq.de> Cc: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: MX3: add SPI functions for lilly1131-dbDaniel Mack2009-11-14
| | | | | | | | This adds support for the two SPI busses found on the lilly1131 module. Signed-off-by: Daniel Mack <daniel@caiaq.de> Cc: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: MX3: remove I2C defintions from mx31lilly.cDaniel Mack2009-11-14
| | | | | | | | The module does not use these pins for I2C but for SPI. Signed-off-by: Daniel Mack <daniel@caiaq.de> Cc: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Linux 2.6.32-rc6v2.6.32-rc6Linus Torvalds2009-11-03
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* Merge branch 'for-linus' of git://github.com/at91linux/linux-2.6-at91Linus Torvalds2009-11-03
|\ | | | | | | | | | | * 'for-linus' of git://github.com/at91linux/linux-2.6-at91: at91: at91sam9g45 family: identify several chip versions avr32: add two new at91 to cpu.h definition
| * at91: at91sam9g45 family: identify several chip versionsNicolas Ferre2009-11-03
| | | | | | | | | | | | | | | | | | | | | | cpu_is_xxx() macros are identifying generic at91sam9g45 chip. This patch adds the capacity to differentiate Engineering Samples and final lots through the inclusion of at91_cpu_fully_identify() and the related chip IDs with chip version field preserved. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
| * avr32: add two new at91 to cpu.h definitionNicolas Ferre2009-11-03
| | | | | | | | | | | | | | | | | | Somme common drivers will need those at91 cpu_is_xxx() definitions. As at91sam9g10 and at91sam9g45 are on the way to linus' tree, here is the patch that adds those chips to cpu.h in AVR32 architecture. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* | Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2009-11-03
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits) MIPS: O32: Fix ppoll MIPS: Oprofile: Rename cpu_type from godson2 to loongson2 MIPS: Alchemy: Fix hang with high-frequency edge interrupts MIPS: TXx9: Fix spi-baseclk value MIPS: bcm63xx: Set the correct BCM3302 CPU name MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store MIPS: Avoid potential hazard on Context register MIPS: Octeon: Use lockless interrupt controller operations when possible. MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache MIPS: SMTC: Avoid queing multiple reschedule IPIs MIPS: GCMP: Avoid accessing registers when they are not present MIPS: GIC: Random fixes and enhancements. MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands MIPS: SPRAM: Clean up support code a little MIPS: 1004K: Enable SPRAM support. MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4 MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT. MIPS: MTI: Fix accesses to device registers on MIPS boards ...
| * MIPS: O32: Fix ppollArnaud Patard2009-11-02
| | | | | | | | | | | | | | | | sys_ppoll syscall needs to use a compat handler on 64bit kernels with o32 user-space. Signed-off-by: Arnaud Patard <apatard@mandriva.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Oprofile: Rename cpu_type from godson2 to loongson2Wu Zhangjin2009-11-02
| | | | | | | | | | | | | | | | | | | | Unify the naming method between kernel and the user-space oprofile tool. Because loongson is used instead of godson in most of the places, we agreed to use loongson instead, which will simplify future maintenance. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Acked-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Alchemy: Fix hang with high-frequency edge interruptsManuel Lauss2009-11-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The handle_edge_irq() flowhandler disables edge int sources which occur too fast (i.e. another edge comes in before the irq handler function had a chance to finish). Currently, the mask_ack() callback does not ack the edges in hardware, leading to an endless loop in the flowhandler where it tries to shut up the irq source. When I rewrote the alchemy IRQ code I wrongly assumed the mask_ack() callback was only used by the level flowhandler, hence it omitted the (at the time pointless) edge acks. Turned out I was wrong; so here is a complete mask_ack implementation for Alchemy IC, which fixes the above mentioned problem. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: TXx9: Fix spi-baseclk valueAtsushi Nemoto2009-11-02
| | | | | | | | | | | | | | | | | | | | TXx9 SPI bit rate is calculated by: fBR = fSPI / 2 / (n + 1) (fSPI is SPI master clock freq, i.e. imbusclk freq.) So use imbus_clk / 2 as a spi-baseclk. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: bcm63xx: Set the correct BCM3302 CPU nameFlorian Fainelli2009-11-02
| | | | | | | | | | | | | | | | For consistency with other BCM63xx SoC set the CPU name to "Broadcom BCM6338" when actually running on that system. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_storeZhang Le2009-11-02
| | | | | | | | | | | | | | | | | | | | Loongson 2 does not have dcache aliases when is using 16k pages. and the And because Loongson 2 doesn't do SMP , cpu_icache_snoops_remote_store does not matter here. Signed-off-by: Zhang Le <r0bertz@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Avoid potential hazard on Context registerRalf Baechle2009-11-02
| | | | | | | | | | | | | | | | | | | | set_saved_sp reads Context register. Avoid reading stale value from earlier incomplete write. Issue found and fixed for head.S by Chris Dearman <chris@mips.com>. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Octeon: Use lockless interrupt controller operations when possible.David Daney2009-11-02
| | | | | | | | | | | | | | | | Some newer Octeon chips have registers that allow lockless operation of the interrupt controller. Take advantage of them. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinityDavid Daney2009-11-02
| | | | | | | | | | | | | | | | Since the locks are used from interrupt context we need the irqsave/irqrestore versions of the locking functions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Set S-cache linesize to 64-bytes for MTI's S-cacheRalf Baechle2009-11-02
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: SMTC: Avoid queing multiple reschedule IPIsJaidev Patwardhan2009-11-02
| | | | | | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: GCMP: Avoid accessing registers when they are not presentJaidev Patwardhan2009-11-02
| | | | | | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: GIC: Random fixes and enhancements.Chris Dearman2009-11-02
| | | | | | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_startChris Dearman2009-11-02
| | | | | | | | | | Signed-off-by: Chris Dearman (chris@mips.com) Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operandsNigel Stephens2009-11-02
| | | | | | | | | | | | | | This patch ensures that the sign bit is always updated for NaN operands. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: SPRAM: Clean up support code a littleChris Dearman2009-11-02
| | | | | | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: 1004K: Enable SPRAM support.Ralf Baechle2009-11-02
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4Ralf Baechle2009-11-02
| | | | | | | | | | | | Based on original patch by Chris Dearman <chris@mips.com>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.Ralf Baechle2009-11-02
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: MTI: Fix accesses to device registers on MIPS boardsChris Dearman2009-11-02
| | | | | | | | | | | | | | | | | | This fixes the remaining problems introduced by f197465384bf7ef1af184c2ed1a4e268911a91e3 (incorrect access length & byteswapping in bigendian mode) Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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