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*---. Merge branches 'armv7', 'at91', 'misc' and 'omap' into develRussell King2007-05-09
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| | | * ARM: OMAP: Fix GCC-reported compile time bugDavid Brownell2007-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix GCC-reported compile time bug which prevents booting when the framebuffer code is disabled. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: OMAP: restore CONFIG_GENERIC_TIMEDavid Brownell2007-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Somehow this got lost in a merge ... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: OMAP: partial LED fixesDavid Brownell2007-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Partial fix for CONFIG_LEDS breakage ... at least allow platforms using the debug-leds support (H4 for now) to build with the generic LED support, and default the LED that would be the timer LED to trigger using the "heartbeat" (timer driven, rate depends on load). Right now only H2 and P2 seem to have working LED support; this at least makes H4 less broken. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: OMAP: add SoSSI clock (call propagate_rate for childrens)Imre Deak2007-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clocks with the follow parent rate mode were not updating their children at propagate rate time. Signed-off-by: Imre Deak <imre.deak@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: OMAP: FB sync with N800 tree (support for dynamic SRAM allocations)Imre Deak2007-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - in addition to fixed FB regions - as passed by the bootloader - allow dynamic allocations - do some more checking against overlapping / reserved regions - move the FB specific parts out from sram.c to fb.c Signed-off-by: Imre Deak <imre.deak@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: OMAP: Sync framebuffer headers with N800 treeKai Svahn2007-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch syncs framebuffer headers with N800 tree. Signed-off-by: Kai Svahn <kai.svahn@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: OMAP: Mostly cosmetic to sync up with linux-omap treeTony Lindgren2007-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Mostly cosmetic to sync up with linux-omap tree Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: OMAP: Fix gpmc headerTony Lindgren2007-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix gpmc header Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: OMAP: Add mailbox support for IVAHiroshi DOYU2007-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a generic mailbox interface for for DSP and IVA (Image Video Accelerator). This patch itself doesn't contain any IVA driver. Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: OMAP: Sync core code with linux-omapTony Lindgren2007-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch syncs omap specific core code with linux-omap. Most of the changes are needed to fix bitrot caused by driver updates in linux-omap tree. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: OMAP: Sync headers with linux-omapTony Lindgren2007-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch syncs omap specific headers with linux-omap. Most of the changes needed because of bitrot caused by driver changes in linux-omap tree. Integrating this is needed for adding support for various omap drivers. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: OMAP: h4 must have blinky leds!!David Brownell2007-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds generic support for the "debug board" LEDs used by most of TI's OMAP reference boards, and board-specific support for the H4. It's derived from the not-as-generic stuff used by OMAP1 H2/H3/P2. Those should be able to switch easily to this version, and clean up some of the omap1-specific code. In addition to H4 support, one key improvement is supporting not just the "old" ARM debug LED API (with timer and idle LEDs, plus four that can be handy for kernel debugging), but it also supports the "new" generic LED API (most useful for usermode stuff IMO). Either or both APIs can be enabled. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: OMAP: FB: add controller platform dataImre Deak2007-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add controller platform data Signed-off-by: Imre Deak <imre.deak@solidboot.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: OMAP: Add function to print clock usecountsJuha Yrjola2007-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Useful for debugging power management code. Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: OMAP: Add DMA IRQ sanity checksJuha Yrjola2007-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DMA IRQ sanity checks Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: OMAP: gpio init section cleanupsDavid Brownell2007-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Minor GPIO cleanups: remove needless #include, and omap_gpio_init() should be __init, as well as all the board init code calling it. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | [ARM] Fix ARM branch relocation rangeKevin Welton2007-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Branches in the ARM architecture are restricted to a range of +/- 32MB. However, the code in .../arch/arm/kernel/module.c::apply_relocate() was checking offset against a range of +/- 64MB. Signed-off-by: Kevin Welton <Kevin.Welton@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | [ARM] Fix ASID version switchRussell King2007-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Close a hole in the ASID version switch, particularly the following scenario: CPU0 MM PID CPU1 MM PID idle A pid(A) A idle(lazy tlb) * new asid version triggered by B * B pid(B) A pid(A) * MM A gets new asid version * A idle(lazy tlb) A pid(A) * CPU1 doesn't see the new ASID * The result is that CPU1 continues running with the hardware set for the original (stale) ASID value, but mm->context.id contains the new ASID value. The result is that the next MM fault on CPU1 updates the page table entries, but flush_tlb_page() fails due to wrong ASID. There is a related case with a threaded application is allocated a new ASID on one CPU while another of its threads is running on some different CPU. This scenario is not fixed by this commit. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | [ARM] Ensure head text is always placed at the start of kernelRussell King2007-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 86c0baf123e474b6eb404798926ecf62b426bf3a highlighted that we may end up with the head text placed elsewhere in the kernel image. Introduce a new .text.head section to contain the initial kernel startup code, and always place this section at the beginning of the kernel image. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | [ARM] Shut up warning about init_thread_unionRussell King2007-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix false warning: WARNING: arch/arm/kernel/init_task.o - Section mismatch: reference to .init.task:init_thread_union from .data between 'init_task' (at offset 0x4) and 'init_sighand' caused by the section name starting with ".init". Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | * | [ARM] Mark SMP local timer and IPI as exception entriesRussell King2007-05-08
| | | | | | | | | | | | | | | | | | | | | | | | This allows the backtrace to dump the exception stack contents. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | [ARM] 4363/1: AT91: Remove legacy PIO definitionsAndrew Victor2007-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the legacy PIO pin definitions for the AT91 processors. The standard (and portable between the different AT91 processors) method is to use the AT91_PIN_* defines and the GPIO API. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | [ARM] 4361/1: AT91: Build errorAndrew Victor2007-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a build error due to a missing semicolon. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | [ARM] armv7: add Makefile and Kconfig entriesCatalin Marinas2007-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the necessary lines to the Makefile and Kconfig files for enabling the compilation of the ARMv7 CPU support. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | [ARM] armv7: add support for asid-tagged VIVT I-cacheCatalin Marinas2007-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv7 can have VIPT, PIPT or ASID-tagged VIVT I-cache. This patch adds the necessary invalidation of the I-cache when the ASID numbers are re-used. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | [ARM] armv7: add dedicated ARMv7 barrier instructionsCatalin Marinas2007-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting with ARMv7, there are dedicated instruction for the ISB, DSB and DMB barriers and there is no need to execute them as CP15 operations. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | [ARM] armv7: Add ARMv7 cacheid macrosCatalin Marinas2007-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch renames the old __cacheid_* macros to __cacheid_*_prev7 and adds support for the new format. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | [ARM] armv7: add support for ARMv7 cores.Catalin Marinas2007-05-08
| |/ / |/| | | | | | | | | | | | | | | | | This patch adds support for the ARMv7 cores. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6Linus Torvalds2007-05-07
|\ \ \ | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6: [SCSI] esp_scsi: Fix section mismatch warnings. [VIDEO] sunxvr2500: Fix PCI device ID table.
| * | | [SCSI] esp_scsi: Fix section mismatch warnings.Martin Habets2007-05-07
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Martin Habets <errandir_news@mph.eclipse.co.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
| * | | [VIDEO] sunxvr2500: Fix PCI device ID table.David S. Miller2007-05-07
| | | | | | | | | | | | | | | | | | | | | | | | Noticed by Meelis Roos. Signed-off-by: David S. Miller <davem@davemloft.net>
* | | | Fix bluetooth HCI sysfs compileLinus Torvalds2007-05-07
|/ / / | | | | | | | | | | | | | | | | | | More fallout from the removal of "struct subsystem" from the core device model. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | Merge git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6Linus Torvalds2007-05-07
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6: [IA64] update memory attribute aliasing documentation & test cases [IA64] fail mmaps that span areas with incompatible attributes [IA64] allow WB /sys/.../legacy_mem mmaps [IA64] make ioremap avoid unsupported attributes [IA64] rename ioremap variables to match i386 [IA64] relax per-cpu TLB requirement to DTC [IA64] remove per-cpu ia64_phys_stacked_size_p8 [IA64] Fix example error injection program [IA64] Itanium MC Error Injection Tool: pal_mc_error_inject() interface [IA64] Itanium MC Error Injection Tool: Makefile changes [IA64] Itanium MC Error Injection Tool: Driver sysfs interface [IA64] Itanium MC Error Injection Tool: Doc and sample application [IA64] Itanium MC Error Injection Tool: Kernel configuration
| * \ \ Pull mem-attribute into release branchTony Luck2007-04-30
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| | * | | [IA64] update memory attribute aliasing documentation & test casesBjorn Helgaas2007-03-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updates documentation and adds some test cases. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | [IA64] fail mmaps that span areas with incompatible attributesBjorn Helgaas2007-03-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Example memory map (from HP sx1000 with VGA enabled): 0x00000 - 0x9FFFF supports only WB (cacheable) access 0xA0000 - 0xBFFFF supports only UC (uncacheable) access 0xC0000 - 0xFFFFF supports only WB (cacheable) access Some versions of X map the entire 0x00000-0xFFFFF area at once. With the example above, this mmap must fail because there's no memory attribute that's safe for the entire area. Prior to this patch, we performed the mmap with a UC mapping. When X accessed the WB memory at 0xC0000, it caused an MCA. The crash can happen when mapping 0xC0000 from either /dev/mem or a /sys/.../legacy_mem file. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | [IA64] allow WB /sys/.../legacy_mem mmapsBjorn Helgaas2007-03-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow cacheable mmaps of legacy_mem if WB access is supported for the region. The "legacy_mem" file often contains a shadow option ROM, and some versions of X depend on this. Tim Yamin <plasm@roo.me.uk> reported that this change fixes X on a Dell PowerEdge 3250. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | [IA64] make ioremap avoid unsupported attributesBjorn Helgaas2007-03-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Example memory map (from HP sx1000 with VGA enabled): 0x00000 - 0x9FFFF supports only WB (cacheable) access 0xA0000 - 0xBFFFF supports only UC (uncacheable) access 0xC0000 - 0xFFFFF supports only WB (cacheable) access pci_read_rom() indirectly uses ioremap(0xC0000) to read the shadow VGA option ROM. ioremap() used to default to a 16MB or 64MB UC kernel identity mapping, which would cause an MCA when reading 0xC0000 since only WB is supported there. X uses reads the option ROM to initialize devices. A smaller test case is: # echo 1 > /sys/bus/pci/devices/0000:aa:03.0/rom # cp /sys/bus/pci/devices/0000:aa:03.0/rom x To avoid this, we can use the same ioremap_page_range() strategy that most architectures use for all ioremaps. These page table mappings come out of the vmalloc area. On ia64, these are in region 5 (0xA... addresses) and typically use 16KB or 64KB mappings instead of 16MB or 64MB mappings. The smaller mappings give more flexibility to use the correct attributes. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | [IA64] rename ioremap variables to match i386Bjorn Helgaas2007-03-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No functional change, just use the same names as i386. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | | | Pull percpu-dtc into release branchTony Luck2007-04-30
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| | * | | | [IA64] relax per-cpu TLB requirement to DTCChen, Kenneth W2007-02-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of pinning per-cpu TLB into a DTR, use DTC. This will free up one TLB entry for application, or even kernel if access pattern to per-cpu data area has high temporal locality. Since per-cpu is mapped at the top of region 7 address, we just need to add special case in alt_dtlb_miss. The physical address of per-cpu data is already conveniently stored in IA64_KR(PER_CPU_DATA). Latency for alt_dtlb_miss is not affected as we can hide all the latency. It was measured that alt_dtlb_miss handler has 23 cycles latency before and after the patch. The performance effect is massive for applications that put lots of tlb pressure on CPU. Workload environment like database online transaction processing or application uses tera-byte of memory would benefit the most. Measurement with industry standard database benchmark shown an upward of 1.6% gain. While smaller workloads like cpu, java also showing small improvement. Signed-off-by: Ken Chen <kenneth.w.chen@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | [IA64] remove per-cpu ia64_phys_stacked_size_p8Chen, Kenneth W2007-02-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's not efficient to use a per-cpu variable just to store how many physical stack register a cpu has. Ever since the incarnation of ia64 up till upcoming Montecito processor, that variable has "glued" to 96. Having a variable in memory means that the kernel is burning an extra cacheline access on every syscall and kernel exit path. Such "static" value is better served with the instruction patching utility exists today. Convert ia64_phys_stacked_size_p8 into dynamic insn patching. This also has a pleasant side effect of eliminating access to per-cpu area while psr.ic=0 in the kernel exit path. (fixable for per-cpu DTC work, but why bother?) There are some concerns with the default value that the instruc- tion encoded in the kernel image. It shouldn't be concerned. The reasons are: (1) cpu_init() is called at CPU initialization. In there, we find out physical stack register size from PAL and patch two instructions in kernel exit code. The code in question can not be executed before the patching is done. (2) current implementation stores zero in ia64_phys_stacked_size_p8, and that's what the current kernel exit path loads the value with. With the new code, it is equivalent that we store reg size 96 in ia64_phys_stacked_size_p8, thus creating a better safety net. Given (1) above can never fail, having (2) is just a bonus. All in all, this patch allow one less memory reference in the kernel exit path, thus reducing syscall and interrupt return latency; and avoid polluting potential useful data in the CPU cache. Signed-off-by: Ken Chen <kenneth.w.chen@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | | | | Pull error-inject into release branchTony Luck2007-04-30
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| | * | | | | [IA64] Fix example error injection programTony Luck2007-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Progam accessed using /sys/devices/system/node/node0/cpu%d/err_inject/ This path only exists for CONFIG_NUMA=y systems. Better to use /sys/devices/system/cpu/cpu%d/err_inject/ which is available on all systems. Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64] Itanium MC Error Injection Tool: pal_mc_error_inject() interfaceFenghua Yu2007-01-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements pal_mc_error_inject() interface in kernel. Both physical mode and virtual mode are supported. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64] Itanium MC Error Injection Tool: Makefile changesFenghua Yu2007-01-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch has Makefile changes. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64] Itanium MC Error Injection Tool: Driver sysfs interfaceFenghua Yu2007-01-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This kernel driver patch provides sysfs interface for user application to call pal_mc_error_inject() procedure. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64] Itanium MC Error Injection Tool: Doc and sample applicationFenghua Yu2007-01-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains a documention and sample application. Since the sample application has ~1000 lines of code, it might not be suitable in a kernel documention in kenrel tree. If you think this is not good place to hold the sample application, please let me know and I'm open to other choices e.g. sourceforge etc. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * | | | | [IA64] Itanium MC Error Injection Tool: Kernel configurationFenghua Yu2007-01-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch has kenrel configuration changes for the MC Error Injection Tool. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-14 02:53:23 -0500