aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAge
* KVM: Hoist kvm_mmu_reload() out of the critical sectionShaohua Li2007-10-13
| | | | | | | | vmx_cpu_run doesn't handle error correctly and kvm_mmu_reload might sleep with mutex changes, so I move it above. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: Return if the pdptrs are invalid when the guest turns on PAE.Rusty Russell2007-10-13
| | | | | | | Don't fall through and turn on PAE in this case. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: x86 emulator: fix faulty check for two-byte opcodeAvi Kivity2007-10-13
| | | | | | | | | Right now, the bug is harmless as we never emulate one-byte 0xb6 or 0xb7. But things may change. Noted by the mysterious Gabriel C. Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: x86 emulator: fix cmov for writeback changesAvi Kivity2007-10-13
| | | | | | | The writeback fixes (02c03a326a5df825cc01de426f72e160db2b9538) broke cmov emulation. Fix. Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: Use standard CR8 flags, and fix TPR definitionRusty Russell2007-10-13
| | | | | | | | | Intel manual (and KVM definition) say the TPR is 4 bits wide. Also fix CR8_RESEVED_BITS typo. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Acked-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: Set exit_reason to KVM_EXIT_MMIO where run->mmio is initialized.Jeff Dike2007-10-13
| | | | | Signed-off-by: Jeff Dike <jdike@linux.intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: Trivial: Use standard BITMAP macros, open-code userspace-exposed headerRusty Russell2007-10-13
| | | | | | | | | Creating one's own BITMAP macro seems suboptimal: if we use manual arithmetic in the one place exposed to userspace, we can use standard macros elsewhere. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: Use standard CR4 flags, tighten checkingRusty Russell2007-10-13
| | | | | | | | | | | On this machine (Intel), writing to the CR4 bits 0x00000800 and 0x00001000 cause a GPF. The Intel manual is a little unclear, but AFIACT they're reserved, too. Also fix spelling of CR4_RESEVED_BITS. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: Use standard CR3 flags, tighten checkingRusty Russell2007-10-13
| | | | | | | | | | | The kernel now has asm/cpu-features.h: use those macros instead of inventing our own. Also spell out definition of CR3_RESEVED_BITS, fix spelling and tighten it for the non-PAE case. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: Trivial: Use standard CR0 flags macros from asm/cpu-features.hRusty Russell2007-10-13
| | | | | | | | | | The kernel now has asm/cpu-features.h: use those macros instead of inventing our own. Also spell out definition of CR0_RESEVED_BITS (no code change) and fix typo. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: Trivial: Avoid hardware_disable predeclarationRusty Russell2007-10-13
| | | | | | | Don't pre-declare hardware_disable: shuffle the reboot hook down. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: Trivial: Comment spelling may escape grepRusty Russell2007-10-13
| | | | | | | Speling error in comment. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: Trivial: Make decode_register() staticRusty Russell2007-10-13
| | | | | | | | | I have shied away from touching x86_emulate.c (it could definitely use some love, but it is forked from the Xen code, and it would be more productive to cross-merge fixes). Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: Trivial: Remove unused struct cpu_user_regs declarationRusty Russell2007-10-13
| | | | | Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: Trivial: /dev/kvm interface is no longer experimental.Rusty Russell2007-10-13
| | | | | | | KVM interface is no longer experimental. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: In-kernel string pio write supportEddie Dong2007-10-13
| | | | | | | Add string pio write support to support some version of Windows. Signed-off-by: Yaozu (Eddie) Dong <eddie.dong@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: Future-proof the exit information union ABIAvi Kivity2007-10-13
| | | | | | | Note that as the size of struct kvm_run is not part of the ABI, we can add things at the end. Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: SMP: Add vcpu_id field in struct vcpuQing He2007-10-13
| | | | | | | | This patch adds a `vcpu_id' field in `struct vcpu', so we can differentiate BSP and APs without pointer comparison or arithmetic. Signed-off-by: Qing He <qing.he@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* KVM: Fix *nopage() in kvm_main.cNguyen Anh Quynh2007-10-13
| | | | | | | | *nopage() in kvm_main.c should only store the type of mmap() fault if the pointers are not NULL. This patch fixes the problem. Signed-off-by: Nguyen Anh Quynh <aquynh@gmail.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
* i386: Expose IOAPIC register definitions even if CONFIG_X86_IO_APIC is not setAvi Kivity2007-10-13
| | | | | | | | | KVM reuses the IOAPIC register definitions, and needs them even if the host is not compiled with IOAPIC support. Move the #ifdef below so that only the IOAPIC variables and functions are protected, and the register definitions are available to all. Signed-off-by: Avi Kivity <avi@qumranet.com>
* x86/pci/acpi: fix DMI const-ification falloutJeff Garzik2007-10-12
| | | | | | | | Fix DMI const-ification fallout that appeared when merging subsystem trees. Signed-off-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* x86: optimise barriersNick Piggin2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to latest memory ordering specification documents from Intel and AMD, both manufacturers are committed to in-order loads from cacheable memory for the x86 architecture. Hence, smp_rmb() may be a simple barrier. Also according to those documents, and according to existing practice in Linux (eg. spin_unlock doesn't enforce ordering), stores to cacheable memory are visible in program order too. Special string stores are safe -- their constituent stores may be out of order, but they must complete in order WRT surrounding stores. Nontemporal stores to WB memory can go out of order, and so they should be fenced explicitly to make them appear in-order WRT other stores. Hence, smp_wmb() may be a simple barrier. http://developer.intel.com/products/processor/manuals/318147.pdf http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24593.pdf In userspace microbenchmarks on a core2 system, fence instructions range anywhere from around 15 cycles to 50, which may not be totally insignificant in performance critical paths (code size will go down too). However the primary motivation for this is to have the canonical barrier implementation for x86 architecture. smp_rmb on buggy pentium pros remains a locked op, which is apparently required. Signed-off-by: Nick Piggin <npiggin@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* x86: fix IO write barrierNick Piggin2007-10-12
| | | | | | | | wmb() on x86 must always include a barrier, because stores can go out of order in many cases when dealing with devices (eg. WC memory). Signed-off-by: Nick Piggin <npiggin@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* x86: fence oostores on 64-bitNick Piggin2007-10-12
| | | | | | | | | | | | | movnt* instructions are not strongly ordered with respect to other stores, so if we are to assume stores are strongly ordered in the rest of the 64 bit code, we must fence these off (see similar examples in 32 bit code). [ The AMD memory ordering document seems to say that nontemporal stores can also pass earlier regular stores, so maybe we need sfences _before_ movnt* everywhere too? ] Signed-off-by: Nick Piggin <npiggin@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Only enable BLOCK_COMPAT if COMPAT is neededLinus Torvalds2007-10-12
| | | | | | IOW, it needs to depend on both CONFIG_BLOCK and CONFIG_COMPAT. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'upstream' of ↵Linus Torvalds2007-10-12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev * 'upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev: (119 commits) [libata] struct pci_dev related cleanups libata: use ata_exec_internal() for PMP register access libata: implement ATA_PFLAG_RESETTING libata: add @timeout to ata_exec_internal[_sg]() ahci: fix notification handling ahci: clean up PORT_IRQ_BAD_PMP enabling ahci: kill leftover from enabling NCQ over PMP libata: wrap schedule_timeout_uninterruptible() in loop libata: skip suppress reporting if ATA_EHI_QUIET libata: clear ehi description after initial host report pata_jmicron: match vendor and class code only libata: add ST9160821AS / 3.ALD to NCQ blacklist pata_acpi: ACPI driver support libata-core: Expose gtm methods for driver use libata: add HDT722516DLA380 to NCQ blacklist libata: blacklist NCQ on Seagate Barracuda ST380817AS [libata] Turn on ACPI by default libata_scsi: Fix ATAPI transfer lengths libata: correct handling of SRST reset sequences libata: Integrate ACPI-based PATA/SATA hotplug - version 5 ...
| * [libata] struct pci_dev related cleanupsJeff Garzik2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * remove pointless pci_dev_to_dev() wrapper. Just directly reference the embedded struct device like everyone else does. * pata_cs5520: delete cs5520_remove_one(), it was a duplicate of ata_pci_remove_one() * linux/libata.h: don't bother including linux/pci.h, we don't need it. Simply declare 'struct pci_dev' and assume interested parties will include the header, as they should be doing anyway. * linux/libata.h: consolidate all CONFIG_PCI declarations into a single location in the header. Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
| * libata: use ata_exec_internal() for PMP register accessTejun Heo2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PMP registers used to be accessed with dedicated accessors ->pmp_read and ->pmp_write. During reset, those callbacks are called with the port frozen so they should be able to run without depending on interrupt delivery. To achieve this, they were implemented polling. However, as resetting the host port makes the PMP to isolate fan-out ports until SError.X is cleared, resetting fan-out ports while port is frozen doesn't buy much additional safety. This patch updates libata PMP support such that PMP registers are accessed using regular ata_exec_internal() mechanism and kills ->pmp_read/write() callbacks. The following changes are made. * PMP access helpers - sata_pmp_read_init_tf(), sata_pmp_read_val(), sata_pmp_write_init_tf() are folded into sata_pmp_read/write() which are now standalone PMP register access functions. * sata_pmp_read/write() returns err_mask instead of rc. This is consistent with other functions which issue internal commands and allows more detailed error reporting. * ahci interrupt handler is modified to ignore BAD_PMP and spurious/illegal completion IRQs while reset is in progress. These conditions are expected during reset. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * libata: implement ATA_PFLAG_RESETTINGTejun Heo2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement ATA_PFLAG_RESETTING. This flag is set while reset is in progress. It's set before prereset is called and cleared after reset fails or postreset is finished. This flag itself doesn't have any function. It will be used by LLDs to tell whether reset is in progress if it needs to behave differently during reset. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * libata: add @timeout to ata_exec_internal[_sg]()Tejun Heo2007-10-12
| | | | | | | | | | | | | | | | Add @timeout argument to ata_exec_internal[_sg](). If 0, default timeout ata_probe_timeout is used. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * ahci: fix notification handlingTejun Heo2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | Asynchronous notification on ICH9 didn't work because it didn't write AN FIS into the RX area - it only updates SNotification. Also, snooping SDB_FIS RX area is racy against further SDB FIS receptions. Let sata_async_notification() determine using SNTF if it's available and snoop RX area iff SNTF isn't available Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * ahci: clean up PORT_IRQ_BAD_PMP enablingTejun Heo2007-10-12
| | | | | | | | | | | | | | | | Now that we have pp->intr_mask, move PORT_IRQ_BAD_PMP enabling to ahci_pmp_attach/detach() where it belongs. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * ahci: kill leftover from enabling NCQ over PMPTejun Heo2007-10-12
| | | | | | | | | | | | | | | | | | ahci had problems with NCQ over PMP and NCQ used to be disabled while PMP was attached. After fixing the problem, the temporary NCQ disabling code wasn't removed completely. Kill the remaining piece. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * libata: wrap schedule_timeout_uninterruptible() in loopTejun Heo2007-10-12
| | | | | | | | | | | | | | | | | | | | Tasks in uninterruptible sleep might be woken up by unrelated events and should check whether the condition it was waiting for has actually triggered. Wrap schedule_timeout_uninterruptible() in loop to achieve it. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * libata: skip suppress reporting if ATA_EHI_QUIETTejun Heo2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ATA_EHI_NO_AUTOPSY and ATA_EHI_QUIET are used during initial probing to skip exception analysis and reporting. Usually, there's nothing to report but on some allowed but rare corner cases (e.g. phy status changed interrupt when IRQ is enabled on frozen port - this happens if IRQ pending status isn't cleared in the IRQ router or controller) exception messages get printed. Skip reporting if ATA_EHI_QUIET is set. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * libata: clear ehi description after initial host reportTejun Heo2007-10-12
| | | | | | | | | | | | | | | | | | | | ehi description field is used to carry LLD specific controller description. Sometimes, it's used without clearing before and LLD description gets printed with exception information one more time. Clear after printing. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * pata_jmicron: match vendor and class code onlyTejun Heo2007-10-12
| | | | | | | | | | | | | | | | | | | | | | PATA part of all current JMB controllers behave the same way and JMicron confirms that all future ones will stay compatible. Drop device matching and match only vendor and class. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Ethan Hsiao <ethanhsiao@jmicron.com> Cc: Justin Tsai <justin@jmicron.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * libata: add ST9160821AS / 3.ALD to NCQ blacklistTejun Heo2007-10-12
| | | | | | | | | | | | | | ST9160821AS / 3.ALD also does spurious NCQ completions. Disable NCQ. Signed-off-by: Tejun Heo <teheo@suse.de> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * pata_acpi: ACPI driver supportAlan Cox2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On a cable there may be eighty wires or perhaps forty and we learn about its type In the world of ACPI So we call the GTM And we find the the timing rate And we look through it to see If eighty wire it must be Timing lives in ACPI routines ACPI routines, ACPI routines Timing lives in ACPI routines ACPI routes ACPI routines And the drivers last you see Picking up unknown pci ids and the code begins to work Timing lives in ACPI routines ACPI routines, ACPI routines Timing lives in ACPI routines ACPI routes ACPI routines [Full speed ahead, Mr Hacker, full speed ahead] Full speed over here sir! Checking Cable, checking cable Aye aye, 80 wire, Heaven heaven] If we use ACPI (ACPI) Every box (every box) has all we need (has all we need) Cable type (cable type) and mode timing (mode timing) In our ATA (in our ATA) subroutines (subroutines, ha ha) Timing lives in ACPI routines ACPI routines, ACPI routines Timing lives in ACPI routines ACPI routes ACPI routines Timing lives in ACPI routines ACPI routines, ACPI routines Timing lives in ACPI routines ACPI routes ACPI routines Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * libata-core: Expose gtm methods for driver useAlan Cox2007-10-12
| | | | | | | | | | | | | | | | | | | | | | Talk to the dark side our driver has to, yes. Much misleading is the data. Store it in a structure we do so that it may be parsed. Signed-off-by: Alan Cox <alan@redhat.com> -- Whats small, old and shouts phrases out of order across mountains ? Yodla.. Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * libata: add HDT722516DLA380 to NCQ blacklistTejun Heo2007-10-12
| | | | | | | | | | | | | | | | | | HDT722516DLA380 does spurious completion of NCQ commands. Blacklist it. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Frans Pop <elendil@planet.nl> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * libata: blacklist NCQ on Seagate Barracuda ST380817ASPaolo Ornati2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Seagate Barracuda ST380817AS has troubles with NCQ. For example, unpacking a tarball on an XFS filesystem gives this: ata1.00: exception Emask 0x0 SAct 0x1 SErr 0x0 action 0x2 frozen ata1.00: cmd 61/40:00:29:a3:98/00:00:00:00:00/40 tag 0 cdb 0x0 data 32768 out res 40/00:00:00:00:00/00:00:00:00:00/00 Emask 0x4 (timeout) More info here: http://lkml.org/lkml/2007/1/21/76 Blacklist it! Signed-off-by: Paolo Ornati <ornati@fastwebnet.it> Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * [libata] Turn on ACPI by defaultJeff Garzik2007-10-12
| | | | | | | | | | | | Let's see what explodes. Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
| * libata_scsi: Fix ATAPI transfer lengthsAlan Cox2007-10-12
| | | | | | | | | | | | | | | | | | | | Some controller variants snoop the ATAPI length value for Packet transfers to do state machine and FIFO management. Thus we want to set it properly, even for cases where it is otherwise meaningless. Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * libata: correct handling of SRST reset sequencesAlan Cox2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct handling of SRST reset sequences. After an SRST it is undefined whether the drive has gone back to PIO0. In order to talk safely we should talk slowly and carefully until we know. Thus when we do the reset if the controller has a pio setup method we call it to flip back to PIO 0 and a known state. After the reset completes the identify will then be done at the safe speed and the drive/controller will pick suitable faster modes and reconfigure the controller to these timings. As a side effect it means we force the controller to PIO 0 as we bring it up which fixes funnies on a few systems where the BIOS firmware leaves us in an interesting choice of modes, or embedded boxes with no firmware which come up in random states. For smart controllers there is nothing to do - they know about this internally. Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * libata: Integrate ACPI-based PATA/SATA hotplug - version 5Matthew Garrett2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Modern laptops with hotswap bays still tend to utilise a PATA interface on a SATA bridge, generally with the host controller in some legacy emulation mode rather than AHCI. This means that the existing hotplug code in libata is unable to work. The ACPI specification states that these devices can send notifications when hotswapped, which avoids the need to obtain notification from the controller. This patch uses the existing libata-acpi code and simply registers a notification in order to trigger a rescan whenever the firmware signals an event. Signed-off-by: Matthew Garrett <mjg59@srcf.ucam.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * libata: Add a drivers/ide style DMA disableAlan Cox2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is useful when debugging, handling problem systems, or for distributions just to get the system installed so it can be sorted out later. This is a bit smarter than the old IDE one and lets you do libata.dma=0 Disable all PATA DMA like old IDE libata.dma=1 Disk DMA only libata.dma=2 ATAPI DMA only libata.dma=4 CF DMA only (or combinations thereof - 0,1,3 being the useful ones I suspect) (I've split CF as it seems to be a seperate case of pain and suffering different to the others and caused by assorted PIO wired adapters etc) Signed-off-by: Alan Cox <alan@redhat.com> [edited to work on SATA too, changing name from 'pata_dma' to 'dma'] Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
| * ahci: Add MCP79 support to AHCI driverPeer Chen2007-10-12
| | | | | | | | | | Signed-off-by: Peer Chen <peerchen@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * libata: add human-readable error value decodingRobert Hancock2007-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds human-readable decoding of the ATA status and error registers (similar to what drivers/ide does) as well as the SATA Serror register to libata error handling output. This prevents the need to pore through standards documents to figure out the meaning of the bits in these registers when looking at error reports. Some bits that drivers/ide decoded are not decoded here, since the bits are either command-dependent or obsolete, and properly parsing them would add too much complexity. Signed-off-by: Robert Hancock <hancockr@shaw.ca> [edited slightly to make output a bit more symmetric] Signed-off-by: Jeff Garzik <jeff@garzik.org>
| * ahci: implement AHCI_HFLAG_NO_PMPTejun Heo2007-10-12
| | | | | | | | | | | | | | Of course some controllers lie about PMP support. Black list them. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-25 13:39:19 -0500