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* Merge branch 'v6v7' into develRussell King2011-03-16
|\ | | | | | | | | | | | | Conflicts: arch/arm/include/asm/cacheflush.h arch/arm/include/asm/proc-fns.h arch/arm/mm/Kconfig
| * ARM: 6653/1: bitops: Use BX instead of MOV PC,LRDave Martin2011-02-19
| | | | | | | | | | | | | | | | | | | | | | | | | | The kernel doesn't officially need to interwork, but using BX wherever appropriate will help educate people into good assembler coding habits. BX is appropriate here because this code is predicated on __LINUX_ARM_ARCH__ >= 6 Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 6655/1: Correct WFE() in asm/spinlock.h for Thumb-2Dave Martin2011-02-10
| | | | | | | | | | | | | | | | | | | | | | | | | | The content for ALT_SMP() in the definition of WFE() expands to 6 bytes (IT cc ; WFEcc.W), which breaks the assumptions of the fixup code, leading to lockups when the affected code gets run. This patch works around the problem by explicitly using an IT + WFEcc.N pair. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: v6/v7 cache: allow cache calls to be optimizedRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | | | | | | | The v6 cache call optimization was disabled to allow the optional block cache operations to be subsituted on CPUs which supported those operations. However, as that functionality was removed, we no longer need to prevent this optimization being taken advantage of. The v7 cache call optimization was just a copy of the v6, so also fix that too. Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: v6k: DMA_CACHE_RWFO isn't appropriate for non-v6k CPUsRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | Limit DMA_CACHE_RWFO to only v6k SMP CPUs - V6 CPUs aren't SMP capable, so the read/write for ownership work-around doesn't apply to them. Acked-by: Will Deacon <will.deacon@arm.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: v6k: only allow SMP if we have v6k or v7 CPURussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | SMP extensions are only supported on ARMv6k or ARMv7 architectures, so only offer the option if we're building for such an architecture. Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: v6k: allow swp emulation again when ARMv7 is enabledRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | | | Now that we build a v6+v6k+v7 kernel with -march=armv6k for everything, we don't need to disable swp emulation to work around the build problem with OMAP. Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: v6k: do not disable CPU_32v6K based on platform selectionRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPU_32v6K controls whether we use the ARMv6K extension instructions in the kernel, and in some places whether we use SMP-safe code sequences (eg, bitops.) MX3 prevents the selection of this option to ensure that it is not enabled for their CPU, which is ARMv6 only. Now that we've split the CPU_V6 option, V6K support won't be offered for MX3 anymore. OMAP prevents the selection of this option in an attempt to produce a kernel which runs on architectures from ARMv6 to ARMv7 MPCore. We now achieve this in a different way (see the previous patches). As such, we no longer need to offer this as a configuration option to the user. Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: v6k: use CPU domain feature if we include support for arch < ARMv6KRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | | | | | Rather than turning off CPU domain switching when the build architecture includes ARMv6K, thereby causing problems for ARMv6-supporting kernels, turn it on when it's required to support a CPU architecture. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: v6k: select TLS register code according to V6 variantsRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_CPU_V6 is enabled, we may or may not have the TLS register. Use the conditional code which copes with this variability. Otherwise, if CONFIG_CPU_32v6K is set, we know we have the TLS register on all supported CPUs, so use it unconditionally. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: v6k: select generic atomic64 code according to V6 variantsRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_CPU_V6 is enabled, avoid using the double-word exclusive instructions in the kernel's atomic implementations as these are not supported. Fall back to the generic spinlock code instead. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Will Deacon <will.deacon@arm.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: v6k: select cmpxchg code sequences according to V6 variantsRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_CPU_V6 is enabled, we must avoid the byte/halfword/doubleword exclusive operations, which aren't implemented before V6K. Use the generic versions (or omit them) instead. If CONFIG_CPU_V6 is not set, but CONFIG_CPU_32v6K is enabled, we have the K extnesions, so use these new instructions. Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: v6k: select clear exclusive code seqences according to V6 variantsRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_CPU_V6 is enabled, then the kernel must support ARMv6 CPUs which don't have the V6K extensions implemented. Always use the dummy store-exclusive method to ensure that the exclusive monitors are cleared. If CONFIG_CPU_V6 is not set, but CONFIG_CPU_32v6K is enabled, then we have the K extensions available on all CPUs we're building support for, so we can use the new clear-exclusive instruction. Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: v6k: Dove platforms use V6K architecture CPUsRussell King2011-02-02
| | | | | | | | | | | | | | Make Dove platforms select the new V6K CPU option. Tested-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: v6k: Realview EB 11MPCore and PB11MPCore use V6K architecture CPUsRussell King2011-02-02
| | | | | | | | | | | | | | | | Make Realview EB ARM11MPCore and PB11MPCore select the new V6K CPU option. Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: v6k: introduce CPU_V6K optionRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a CPU_V6K configuration option for platforms to select if they have a V6K CPU core. This allows us to identify whether we need to support ARMv6 CPUs without the V6K SMP extensions at build time. Currently CPU_V6K is just an alias for CPU_V6, and all places which reference CPU_V6 are replaced by (CPU_V6 || CPU_V6K). Select CPU_V6K from platforms which are known to be V6K-only. Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: v6k: remove CPU_32v6K dependencies in asm/spinlock.hRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SMP requires at least the ARMv6K extensions to be present, so if we're running on SMP, the WFE and SEV instructions must be available. However, when we run on UP, the v6K extensions may not be available, and so we don't want WFE/SEV to be in the instruction stream. Use the SMP alternatives infrastructure to replace these instructions with NOPs if we build for SMP but run on UP. Tested-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: bitops: switch set/clear/change bitops to use ldrex/strexRussell King2011-02-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch the set/clear/change bitops to use the word-based exclusive operations, which are only present in a wider range of ARM architectures than the byte-based exclusive operations. Tested record: - Nicolas Pitre: ext3,rw,le - Sourav Poddar: nfs,le - Will Deacon: ext3,rw,le - Tony Lindgren: ext3+nfs,le Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: bitops: ensure set/clear/change bitops take a word-aligned pointerRussell King2011-02-02
| | | | | | | | | | | | | | | | | | Add additional instructions to our assembly bitops functions to ensure that they only operate on word-aligned pointers. This will be necessary when we switch these operations to use the word-based exclusive operations. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge branch 'misc' into develRussell King2011-03-16
|\ \ | | | | | | | | | | | | Conflicts: arch/arm/Kconfig
| * | ARM: 6806/1: irq: introduce entry and exit functions for chained handlersWill Deacon2011-03-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some chained IRQ handlers are written to cope with primary chips of potentially different flow types. Whether this a sensible thing to do is a point of contention. This patch introduces entry/exit functions for chained handlers which infer the flow type of the primary chip as fasteoi or level-type by checking whether or not the ->irq_eoi function pointer is present and calling back to the primary chip as necessary. Other methods of flow control are not considered. Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6781/1: Thumb-2: Work around buggy Thumb-2 short branch relocations in gasDave Martin2011-03-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Various binutils versions can resolve Thumb-2 branches to locally-defined, preemptible global symbols as short-range "b.n" branch instructions. This is a problem, because there's no guarantee the final destination of the symbol, or any candidate locations for a trampoline, are within range of the branch. For this reason, the kernel does not support fixing up the R_ARM_THM_JUMP11 (102) relocation in modules at all, and it makes little sense to add support. The symptom is that the kernel fails with an "unsupported relocation" error when loading some modules. Until fixed tools are available, passing -fno-optimize-sibling-calls to gcc should prevent gcc generating code which hits this problem, at the cost of a bit of extra runtime stack usage in some cases. The problem is described in more detail at: https://bugs.launchpad.net/binutils-linaro/+bug/725126 Only Thumb-2 kernels are affected. This patch adds a new CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11 config option which adds -fno-optimize-sibling-calls to CFLAGS_MODULE when building a Thumb-2 kernel. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6798/1: aout-core: zero thread debug registers in a.out core dumpWill Deacon2011-03-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The removal of the single-step emulation from ptrace on ARM means that thread_struct no longer has software breakpoint fields in its debug member. This patch fixes the a.out core dump code so that the debug registers are zeroed rather than trying to copy from non-existent fields. Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Bryan Wu <bryan.wu@canonical.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6796/1: Footbridge: Fix I/O mappings for NOMMU modeStepan Moskovchenko2011-03-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use the correct I/O address definitions for Footbridge peripherals when the kernel is compiled without MMU support. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6786/1: enable CONFIG_KTIME_SCALARRob Herring2011-03-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use straight 64-bit values as 64-bit operations are fairly efficient on ARM. Comparing the asm output with and without KTIME_SCALAR, using 64-bit math generates clearly better code. Comparing kernel/hrtimer.c .text size, it goes from 0x1414 to 0x119c with this change. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6778/1: compressed/head.S: make LDFLAGS_vmlinux into a recursively ↵Nicolas Pitre2011-03-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | expanded variable The simply expanded variable may be evaluated before the target file for the stat command is up to date or even exists. Switching to a recursively expanded variable move the execution of the stat command to the location where LDFLAGS_vmlinux is actually used, fixing the dependency issue introduced by patch #6746/1. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6777/1: gic: Add hooks for architecture specific extensionsSantosh Shilimkar2011-03-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Few architectures combine the GIC with an external interrupt controller. On such systems it may be necessary to update both the GIC registers and the external controller's registers to control IRQ behavior. This can be addressed in couple of possible methods. 1. Export common GIC routines along with 'struct irq_chip gic_chip' and allow architectures to have custom function by override. 2. Provide architecture specific function pointer hooks within GIC library and leave platforms to add the necessary code as part of these hooks. First one might be non-intrusive but have few shortcomings like arch needs to have there own custom gic library. Locks used should be common since it caters to same IRQs etc. Maintenance point of view also it leads to multiple file fixes. The second probably is cleaner and portable. It ensures that all the common GIC infrastructure is not touched and also provides archs to address their specific issue. Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Colin Cross <ccross@android.com> Tested-by: Colin Cross <ccross@android.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6755/1: omap4: l2x0: Populate set_debug() function and enable Errata 727915Santosh Shilimkar2011-03-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Populate the l2x0 set_debug function pointer with OMAP secure call and enable the PL310 Errata 727915 This patch has dependency on the earlier patch ARM: l2x0: Errata fix for flush by Way operation can cause data corruption Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6795/1: l2x0: Errata fix for flush by Way operation can cause data corruptiSantosh Shilimkar2011-03-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PL310 implements the Clean & Invalidate by Way L2 cache maintenance operation (offset 0x7FC). This operation runs in background so that PL310 can handle normal accesses while it is in progress. Under very rare circumstances, due to this erratum, write data can be lost when PL310 treats a cacheable write transaction during a Clean & Invalidate by Way operation. Workaround: Disable Write-Back and Cache Linefill (Debug Control Register) Clean & Invalidate by Way (0x7FC) Re-enable Write-Back and Cache Linefill (Debug Control Register) This patch also removes any OMAP dependency on PL310 Errata's Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6746/1: remove the 4x expansion presumption while decompressing the kernelNicolas Pitre2011-02-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently presume a 4x expansion to guess the decompressed kernel size in order to determine if the decompressed kernel is in conflict with the location where zImage is loaded. This guess may cause many issues by overestimating the final kernel image size: - This may force a needless relocation if the location of zImage was fine, wasting some precious microseconds of boot time. - The relocation may be located way too far, possibly overwriting the initrd image in RAM. - If the kernel image includes a large already-compressed initramfs image then the problem is even more exacerbated. And if by some strange means the 4x guess is too low then we may overwrite ourselves with the decompressed image. So let's use the exact decompressed kernel image size instead. For that we need to rely on the stat command, but this is hardly a new build dependency as the kernel already depends on many external commands to be built provided by the coreutils package where stat is found. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6750/1: improvements to compressed/head.SNicolas Pitre2011-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the case of a conflict between the memory used by the compressed kernel with its decompressor code and the memory used for the decompressed kernel, we currently store the later after the former and relocate it afterwards. This would be more efficient to do this the other way around i.e. relocate the compressed data up front instead, resulting in a smaller copy. That also has the advantage of making the code smaller and more straight forward. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6668/1: ptrace: remove single-step emulation codeWill Deacon2011-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PTRACE_SINGLESTEP is a ptrace request designed to offer single-stepping support to userspace when the underlying architecture has hardware support for this operation. On ARM, we set arch_has_single_step() to 1 and attempt to emulate hardware single-stepping by disassembling the current instruction to determine the next pc and placing a software breakpoint on that location. Unfortunately this has the following problems: 1.) Only a subset of ARMv7 instructions are supported 2.) Thumb-2 is unsupported 3.) The code is not SMP safe We could try to fix this code, but it turns out that because of the above issues it is rarely used in practice. GDB, for example, uses PTRACE_POKETEXT and PTRACE_PEEKTEXT to manage breakpoints itself and does not require any kernel assistance. This patch removes the single-step emulation code from ptrace meaning that the PTRACE_SINGLESTEP request will return -EIO on ARM. Portable code must check the return value from a ptrace call and handle the failure gracefully. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: move L1_CACHE_SHIFT_6 to mm/KconfigRussell King2011-02-23
| | | | | | | | | | | | | | | | | | | | | Move L1_CACHE_SHIFT related options together, rather than spreading them across two separate Kconfig files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6663/1: make Thumb2 kernel entry point more similar to the ARM oneNicolas Pitre2011-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some installers would binary patch the kernel zImage to replace the first few nops with custom instructions. This breaks the Thumb2 kernel as the mode switch is right at the beginning. Let's move it towards the end of the nop sequence instead. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: vfp: improve commentry for hotplug eventsRussell King2011-02-23
| | | | | | | | | | | | | | | | | | | | | | | | Improve the documentation for the VFP hotplug notifier handler, so that people better understand what's going on there and what has been done for them. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6639/1: allow highmem on SMP platforms without h/w TLB ops broadcastNicolas Pitre2011-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit e616c591405c168f6dc3dfd1221e105adfe49b8d, highmem support was deactivated for SMP platforms without hardware TLB ops broadcast because usage of kmap_high_get() requires that IRQs be disabled when kmap_lock is locked which is incompatible with the IPI mechanism used by the software TLB ops broadcast invoked through flush_all_zero_pkmaps(). The reason for kmap_high_get() is to ensure that the currently kmap'd page usage count does not decrease to zero while we're using its existing virtual mapping in an atomic context. With a VIVT cache this is essential to do due to cache coherency issues, but with a VIPT cache this is only an optimization so not to pay the price of establishing a second mapping if an existing one can be used. However, on VIPT platforms without hardware TLB maintenance we can give up on that optimization in order to be able to use highmem. From ARMv7 onwards the TLB ops are broadcasted in hardware, so let's disable ARCH_NEEDS_KMAP_HIGH_GET only when CONFIG_SMP and CONFIG_CPU_TLB_V6 are defined. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Saeed Bishara <saeed.bishara@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: irq migration: update GIC migration codeRussell King2011-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | This cleans up after the conversion to irq_data. Rename the function to match the method, and remove the now useless lookup of the irq descriptor which is never used. Move the bitmask calculation out of the irq_controller_lock region. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: irq migration: ensure migration is handled safelyRussell King2011-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure appropriate locks are taken to ensure that IRQ migration off the current CPU is race-free. We may have a concurrent set_affinity via procfs running on another CPU in parallel with the IRQ migration, resulting in unpredictable results. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: irq migration: force migration off CPU going downRussell King2011-02-23
| | | | | | | | | | | | | | | | | | | | | | | | The force argument to irq_set_affinity really should be 'true' as moving IRQs off a CPU which is going down isn't optional. Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 6608/1: enable bridges in pci_common_init.Colin Tuckley2011-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a missing call to pci_enable_bridges() so that devices behind bridges get found by the pci bus scan. Signed-off-by: Chris Partington <chris.partington@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: improve module relocation fixup diagnosticsRussell King2011-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current diagnostics are rather poor when things go wrong: ipv6: relocation out of range, section 2 reloc 0 sym 'snmp_mib_free' Let's include a little more information about the problem: ipv6: section 2 reloc 0 sym 'snmp_mib_free': relocation 28 out of range (0xbf0000a4 -> 0xc11b4858) so that we show exactly what the problem is - not only what type of relocation but also the offending address range too. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: add 'uinstall' target for installing uboot kernelsRussell King2011-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have 'install' and 'zinstall' for installing Image and zImage kernels, so add 'uinstall' to complete the set. This allows developers to have a ~/bin/installkernel script which (eg) copies the kernel to the tftp server automatically once the kernel has built, resulting in a better workflow. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: fix some sparse errors in generic ARM codeRussell King2011-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | arch/arm/kernel/return_address.c:37:6: warning: symbol 'return_address' was not declared. Should it be static? arch/arm/kernel/setup.c:76:14: warning: symbol 'processor_id' was not declared. Should it be static? arch/arm/kernel/traps.c:259:1: warning: symbol 'die_lock' was not declared. Should it be static? arch/arm/vfp/vfpmodule.c:156:6: warning: symbol 'vfp_raise_sigfpe' was not declared. Should it be static? Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: DMA: top-down allocation in DMA coherent regionRussell King2011-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Achieve better usage of the DMA coherent region by doing top-down allocation rather than bottom up. If we ask for a 128kB allocation, this will be aligned to 128kB and satisfied from the very bottom address. If we then ask for a 600kB allocation, this will be aligned to 1MB, and we will have a 896kB hole. Performing top-down allocation resolves this by allocating the 128kB at the very top, and then the 600kB can come in below it without any unnecessary wastage. This problem was reported by Janusz Krzysztofik, who had 2 x 128kB + 1 x 640kB allocations which wouldn't fit into 1MB. Tested-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: Defer lookup of machine_type to setup.cRussell King2011-02-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the debug macros no longer depend on the machine type information, the machine type lookup can be deferred to setup_arch() in setup.c which simplifies the code somewhat. We also move the __error_a functionality into setup.c for displaying a message when a bad machine ID is passed to the kernel via the LL debug code. We also log this into the kernel ring buffer which makes it possible to retrieve the message via a debugger. Original idea from Grant Likely. Acked-by: Grant Likely <grant.likely@secretlab.ca> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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*-------------------. \ \ Merge branches 'at91', 'ep93xx', 'errata', 'footbridge', 'fncpy', 'gemini', ↵Russell King2011-03-16
|\ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'irqdata', 'pm', 'sh', 'smp', 'spear', 'ux500' and 'via' into devel
| | | | | | | | | | | * | | ARM: 6597/1: Add basic architecture support for VIA/WonderMedia 85xx SoC'sAlexey Charkov2011-01-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the family of Systems-on-Chip produced initially by VIA and now its subsidiary WonderMedia that have recently become widespread in lower-end Chinese ARM-based tablets and netbooks. Support is included for both VT8500 and WM8505, selectable by a configuration switch at kernel build time. Included are basic machine initialization files, register and interrupt definitions, support for the on-chip interrupt controller, high-precision OS timer, GPIO lines, necessary macros for early debug, pulse-width-modulated outputs control, as well as platform device configurations for the specific drivers implemented elsewhere. Signed-off-by: Alexey Charkov <alchark@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | | | * | | | ARM: 6776/1: mach-ux500: activate fix for errata 753970Linus Walleij2011-03-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This applies errata fix 753970 for all ux500 platforms. All current ASICs suffer from this. If the problem is resolved in later ASICs, the errata selection can be pushed down to other Kconfig options. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | | * | | | | ARM: 6794/1: SPEAr: Append UL to device address macros.Shiraz Hashim2011-03-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reviewed-by: Stanley Miao <stanley.miao@windriver.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | | * | | | | ARM: 6793/1: SPEAr: Remove unused *_SIZE macros from spear*.h filesviresh kumar2011-03-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now we used standard SZ_* macros instead of self defined *_SIZE macros. This patch removes all such unused *_SIZE macros for spear3xx & 6xx. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 06:14:48 -0500