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-rw-r--r--virt/kvm/ioapic.c403
-rw-r--r--virt/kvm/ioapic.h95
2 files changed, 498 insertions, 0 deletions
diff --git a/virt/kvm/ioapic.c b/virt/kvm/ioapic.c
new file mode 100644
index 000000000000..317f8e211cd2
--- /dev/null
+++ b/virt/kvm/ioapic.c
@@ -0,0 +1,403 @@
1/*
2 * Copyright (C) 2001 MandrakeSoft S.A.
3 *
4 * MandrakeSoft S.A.
5 * 43, rue d'Aboukir
6 * 75002 Paris - France
7 * http://www.linux-mandrake.com/
8 * http://www.mandrakesoft.com/
9 *
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * Yunhong Jiang <yunhong.jiang@intel.com>
25 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
26 * Based on Xen 3.1 code.
27 */
28
29#include <linux/kvm_host.h>
30#include <linux/kvm.h>
31#include <linux/mm.h>
32#include <linux/highmem.h>
33#include <linux/smp.h>
34#include <linux/hrtimer.h>
35#include <linux/io.h>
36#include <asm/processor.h>
37#include <asm/page.h>
38#include <asm/current.h>
39
40#include "ioapic.h"
41#include "lapic.h"
42
43#if 0
44#define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
45#else
46#define ioapic_debug(fmt, arg...)
47#endif
48static void ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
49
50static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
51 unsigned long addr,
52 unsigned long length)
53{
54 unsigned long result = 0;
55
56 switch (ioapic->ioregsel) {
57 case IOAPIC_REG_VERSION:
58 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
59 | (IOAPIC_VERSION_ID & 0xff));
60 break;
61
62 case IOAPIC_REG_APIC_ID:
63 case IOAPIC_REG_ARB_ID:
64 result = ((ioapic->id & 0xf) << 24);
65 break;
66
67 default:
68 {
69 u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
70 u64 redir_content;
71
72 ASSERT(redir_index < IOAPIC_NUM_PINS);
73
74 redir_content = ioapic->redirtbl[redir_index].bits;
75 result = (ioapic->ioregsel & 0x1) ?
76 (redir_content >> 32) & 0xffffffff :
77 redir_content & 0xffffffff;
78 break;
79 }
80 }
81
82 return result;
83}
84
85static void ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
86{
87 union ioapic_redir_entry *pent;
88
89 pent = &ioapic->redirtbl[idx];
90
91 if (!pent->fields.mask) {
92 ioapic_deliver(ioapic, idx);
93 if (pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
94 pent->fields.remote_irr = 1;
95 }
96 if (!pent->fields.trig_mode)
97 ioapic->irr &= ~(1 << idx);
98}
99
100static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
101{
102 unsigned index;
103
104 switch (ioapic->ioregsel) {
105 case IOAPIC_REG_VERSION:
106 /* Writes are ignored. */
107 break;
108
109 case IOAPIC_REG_APIC_ID:
110 ioapic->id = (val >> 24) & 0xf;
111 break;
112
113 case IOAPIC_REG_ARB_ID:
114 break;
115
116 default:
117 index = (ioapic->ioregsel - 0x10) >> 1;
118
119 ioapic_debug("change redir index %x val %x\n", index, val);
120 if (index >= IOAPIC_NUM_PINS)
121 return;
122 if (ioapic->ioregsel & 1) {
123 ioapic->redirtbl[index].bits &= 0xffffffff;
124 ioapic->redirtbl[index].bits |= (u64) val << 32;
125 } else {
126 ioapic->redirtbl[index].bits &= ~0xffffffffULL;
127 ioapic->redirtbl[index].bits |= (u32) val;
128 ioapic->redirtbl[index].fields.remote_irr = 0;
129 }
130 if (ioapic->irr & (1 << index))
131 ioapic_service(ioapic, index);
132 break;
133 }
134}
135
136static void ioapic_inj_irq(struct kvm_ioapic *ioapic,
137 struct kvm_vcpu *vcpu,
138 u8 vector, u8 trig_mode, u8 delivery_mode)
139{
140 ioapic_debug("irq %d trig %d deliv %d\n", vector, trig_mode,
141 delivery_mode);
142
143 ASSERT((delivery_mode == IOAPIC_FIXED) ||
144 (delivery_mode == IOAPIC_LOWEST_PRIORITY));
145
146 kvm_apic_set_irq(vcpu, vector, trig_mode);
147}
148
149static u32 ioapic_get_delivery_bitmask(struct kvm_ioapic *ioapic, u8 dest,
150 u8 dest_mode)
151{
152 u32 mask = 0;
153 int i;
154 struct kvm *kvm = ioapic->kvm;
155 struct kvm_vcpu *vcpu;
156
157 ioapic_debug("dest %d dest_mode %d\n", dest, dest_mode);
158
159 if (dest_mode == 0) { /* Physical mode. */
160 if (dest == 0xFF) { /* Broadcast. */
161 for (i = 0; i < KVM_MAX_VCPUS; ++i)
162 if (kvm->vcpus[i] && kvm->vcpus[i]->arch.apic)
163 mask |= 1 << i;
164 return mask;
165 }
166 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
167 vcpu = kvm->vcpus[i];
168 if (!vcpu)
169 continue;
170 if (kvm_apic_match_physical_addr(vcpu->arch.apic, dest)) {
171 if (vcpu->arch.apic)
172 mask = 1 << i;
173 break;
174 }
175 }
176 } else if (dest != 0) /* Logical mode, MDA non-zero. */
177 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
178 vcpu = kvm->vcpus[i];
179 if (!vcpu)
180 continue;
181 if (vcpu->arch.apic &&
182 kvm_apic_match_logical_addr(vcpu->arch.apic, dest))
183 mask |= 1 << vcpu->vcpu_id;
184 }
185 ioapic_debug("mask %x\n", mask);
186 return mask;
187}
188
189static void ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
190{
191 u8 dest = ioapic->redirtbl[irq].fields.dest_id;
192 u8 dest_mode = ioapic->redirtbl[irq].fields.dest_mode;
193 u8 delivery_mode = ioapic->redirtbl[irq].fields.delivery_mode;
194 u8 vector = ioapic->redirtbl[irq].fields.vector;
195 u8 trig_mode = ioapic->redirtbl[irq].fields.trig_mode;
196 u32 deliver_bitmask;
197 struct kvm_vcpu *vcpu;
198 int vcpu_id;
199
200 ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
201 "vector=%x trig_mode=%x\n",
202 dest, dest_mode, delivery_mode, vector, trig_mode);
203
204 deliver_bitmask = ioapic_get_delivery_bitmask(ioapic, dest, dest_mode);
205 if (!deliver_bitmask) {
206 ioapic_debug("no target on destination\n");
207 return;
208 }
209
210 switch (delivery_mode) {
211 case IOAPIC_LOWEST_PRIORITY:
212 vcpu = kvm_get_lowest_prio_vcpu(ioapic->kvm, vector,
213 deliver_bitmask);
214 if (vcpu != NULL)
215 ioapic_inj_irq(ioapic, vcpu, vector,
216 trig_mode, delivery_mode);
217 else
218 ioapic_debug("null lowest prio vcpu: "
219 "mask=%x vector=%x delivery_mode=%x\n",
220 deliver_bitmask, vector, IOAPIC_LOWEST_PRIORITY);
221 break;
222 case IOAPIC_FIXED:
223 for (vcpu_id = 0; deliver_bitmask != 0; vcpu_id++) {
224 if (!(deliver_bitmask & (1 << vcpu_id)))
225 continue;
226 deliver_bitmask &= ~(1 << vcpu_id);
227 vcpu = ioapic->kvm->vcpus[vcpu_id];
228 if (vcpu) {
229 ioapic_inj_irq(ioapic, vcpu, vector,
230 trig_mode, delivery_mode);
231 }
232 }
233 break;
234
235 /* TODO: NMI */
236 default:
237 printk(KERN_WARNING "Unsupported delivery mode %d\n",
238 delivery_mode);
239 break;
240 }
241}
242
243void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
244{
245 u32 old_irr = ioapic->irr;
246 u32 mask = 1 << irq;
247 union ioapic_redir_entry entry;
248
249 if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
250 entry = ioapic->redirtbl[irq];
251 level ^= entry.fields.polarity;
252 if (!level)
253 ioapic->irr &= ~mask;
254 else {
255 ioapic->irr |= mask;
256 if ((!entry.fields.trig_mode && old_irr != ioapic->irr)
257 || !entry.fields.remote_irr)
258 ioapic_service(ioapic, irq);
259 }
260 }
261}
262
263static int get_eoi_gsi(struct kvm_ioapic *ioapic, int vector)
264{
265 int i;
266
267 for (i = 0; i < IOAPIC_NUM_PINS; i++)
268 if (ioapic->redirtbl[i].fields.vector == vector)
269 return i;
270 return -1;
271}
272
273void kvm_ioapic_update_eoi(struct kvm *kvm, int vector)
274{
275 struct kvm_ioapic *ioapic = kvm->arch.vioapic;
276 union ioapic_redir_entry *ent;
277 int gsi;
278
279 gsi = get_eoi_gsi(ioapic, vector);
280 if (gsi == -1) {
281 printk(KERN_WARNING "Can't find redir item for %d EOI\n",
282 vector);
283 return;
284 }
285
286 ent = &ioapic->redirtbl[gsi];
287 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
288
289 ent->fields.remote_irr = 0;
290 if (!ent->fields.mask && (ioapic->irr & (1 << gsi)))
291 ioapic_deliver(ioapic, gsi);
292}
293
294static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr)
295{
296 struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
297
298 return ((addr >= ioapic->base_address &&
299 (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
300}
301
302static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
303 void *val)
304{
305 struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
306 u32 result;
307
308 ioapic_debug("addr %lx\n", (unsigned long)addr);
309 ASSERT(!(addr & 0xf)); /* check alignment */
310
311 addr &= 0xff;
312 switch (addr) {
313 case IOAPIC_REG_SELECT:
314 result = ioapic->ioregsel;
315 break;
316
317 case IOAPIC_REG_WINDOW:
318 result = ioapic_read_indirect(ioapic, addr, len);
319 break;
320
321 default:
322 result = 0;
323 break;
324 }
325 switch (len) {
326 case 8:
327 *(u64 *) val = result;
328 break;
329 case 1:
330 case 2:
331 case 4:
332 memcpy(val, (char *)&result, len);
333 break;
334 default:
335 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
336 }
337}
338
339static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
340 const void *val)
341{
342 struct kvm_ioapic *ioapic = (struct kvm_ioapic *)this->private;
343 u32 data;
344
345 ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
346 (void*)addr, len, val);
347 ASSERT(!(addr & 0xf)); /* check alignment */
348 if (len == 4 || len == 8)
349 data = *(u32 *) val;
350 else {
351 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
352 return;
353 }
354
355 addr &= 0xff;
356 switch (addr) {
357 case IOAPIC_REG_SELECT:
358 ioapic->ioregsel = data;
359 break;
360
361 case IOAPIC_REG_WINDOW:
362 ioapic_write_indirect(ioapic, data);
363 break;
364#ifdef CONFIG_IA64
365 case IOAPIC_REG_EOI:
366 kvm_ioapic_update_eoi(ioapic->kvm, data);
367 break;
368#endif
369
370 default:
371 break;
372 }
373}
374
375void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
376{
377 int i;
378
379 for (i = 0; i < IOAPIC_NUM_PINS; i++)
380 ioapic->redirtbl[i].fields.mask = 1;
381 ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
382 ioapic->ioregsel = 0;
383 ioapic->irr = 0;
384 ioapic->id = 0;
385}
386
387int kvm_ioapic_init(struct kvm *kvm)
388{
389 struct kvm_ioapic *ioapic;
390
391 ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
392 if (!ioapic)
393 return -ENOMEM;
394 kvm->arch.vioapic = ioapic;
395 kvm_ioapic_reset(ioapic);
396 ioapic->dev.read = ioapic_mmio_read;
397 ioapic->dev.write = ioapic_mmio_write;
398 ioapic->dev.in_range = ioapic_in_range;
399 ioapic->dev.private = ioapic;
400 ioapic->kvm = kvm;
401 kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
402 return 0;
403}
diff --git a/virt/kvm/ioapic.h b/virt/kvm/ioapic.h
new file mode 100644
index 000000000000..7f16675fe783
--- /dev/null
+++ b/virt/kvm/ioapic.h
@@ -0,0 +1,95 @@
1#ifndef __KVM_IO_APIC_H
2#define __KVM_IO_APIC_H
3
4#include <linux/kvm_host.h>
5
6#include "iodev.h"
7
8struct kvm;
9struct kvm_vcpu;
10
11#define IOAPIC_NUM_PINS KVM_IOAPIC_NUM_PINS
12#define IOAPIC_VERSION_ID 0x11 /* IOAPIC version */
13#define IOAPIC_EDGE_TRIG 0
14#define IOAPIC_LEVEL_TRIG 1
15
16#define IOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000
17#define IOAPIC_MEM_LENGTH 0x100
18
19/* Direct registers. */
20#define IOAPIC_REG_SELECT 0x00
21#define IOAPIC_REG_WINDOW 0x10
22#define IOAPIC_REG_EOI 0x40 /* IA64 IOSAPIC only */
23
24/* Indirect registers. */
25#define IOAPIC_REG_APIC_ID 0x00 /* x86 IOAPIC only */
26#define IOAPIC_REG_VERSION 0x01
27#define IOAPIC_REG_ARB_ID 0x02 /* x86 IOAPIC only */
28
29/*ioapic delivery mode*/
30#define IOAPIC_FIXED 0x0
31#define IOAPIC_LOWEST_PRIORITY 0x1
32#define IOAPIC_PMI 0x2
33#define IOAPIC_NMI 0x4
34#define IOAPIC_INIT 0x5
35#define IOAPIC_EXTINT 0x7
36
37struct kvm_ioapic {
38 u64 base_address;
39 u32 ioregsel;
40 u32 id;
41 u32 irr;
42 u32 pad;
43 union ioapic_redir_entry {
44 u64 bits;
45 struct {
46 u8 vector;
47 u8 delivery_mode:3;
48 u8 dest_mode:1;
49 u8 delivery_status:1;
50 u8 polarity:1;
51 u8 remote_irr:1;
52 u8 trig_mode:1;
53 u8 mask:1;
54 u8 reserve:7;
55 u8 reserved[4];
56 u8 dest_id;
57 } fields;
58 } redirtbl[IOAPIC_NUM_PINS];
59 struct kvm_io_device dev;
60 struct kvm *kvm;
61};
62
63#ifdef DEBUG
64#define ASSERT(x) \
65do { \
66 if (!(x)) { \
67 printk(KERN_EMERG "assertion failed %s: %d: %s\n", \
68 __FILE__, __LINE__, #x); \
69 BUG(); \
70 } \
71} while (0)
72#else
73#define ASSERT(x) do { } while (0)
74#endif
75
76static inline struct kvm_ioapic *ioapic_irqchip(struct kvm *kvm)
77{
78 return kvm->arch.vioapic;
79}
80
81#ifdef CONFIG_IA64
82static inline int irqchip_in_kernel(struct kvm *kvm)
83{
84 return 1;
85}
86#endif
87
88struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector,
89 unsigned long bitmap);
90void kvm_ioapic_update_eoi(struct kvm *kvm, int vector);
91int kvm_ioapic_init(struct kvm *kvm);
92void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level);
93void kvm_ioapic_reset(struct kvm_ioapic *ioapic);
94
95#endif
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