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-rw-r--r--sound/oss/ad1889.c198
-rw-r--r--sound/oss/ad1889.h101
2 files changed, 150 insertions, 149 deletions
diff --git a/sound/oss/ad1889.c b/sound/oss/ad1889.c
index 54dabf862802..a4ca7569e700 100644
--- a/sound/oss/ad1889.c
+++ b/sound/oss/ad1889.c
@@ -75,7 +75,7 @@ static inline void ad1889_set_wav_rate(ad1889_dev_t *dev, int rate)
75 75
76 DBG("Setting WAV rate to %d\n", rate); 76 DBG("Setting WAV rate to %d\n", rate);
77 dev->state[AD_WAV_STATE].dmabuf.rate = rate; 77 dev->state[AD_WAV_STATE].dmabuf.rate = rate;
78 AD1889_WRITEW(dev, AD_DSWAS, rate); 78 AD1889_WRITEW(dev, AD_DS_WAS, rate);
79 79
80 /* Cycle the DAC to enable the new rate */ 80 /* Cycle the DAC to enable the new rate */
81 ac97_codec->codec_write(dev->ac97_codec, AC97_POWER_CONTROL, 0x0200); 81 ac97_codec->codec_write(dev->ac97_codec, AC97_POWER_CONTROL, 0x0200);
@@ -89,14 +89,14 @@ static inline void ad1889_set_wav_fmt(ad1889_dev_t *dev, int fmt)
89 89
90 DBG("Setting WAV format to 0x%x\n", fmt); 90 DBG("Setting WAV format to 0x%x\n", fmt);
91 91
92 tmp = AD1889_READW(ad1889_dev, AD_DSWSMC); 92 tmp = AD1889_READW(ad1889_dev, AD_DS_WSMC);
93 if (fmt & AFMT_S16_LE) { 93 if (fmt & AFMT_S16_LE) {
94 //tmp |= 0x0100; /* set WA16 */ 94 //tmp |= 0x0100; /* set WA16 */
95 tmp |= 0x0300; /* set WA16 stereo */ 95 tmp |= 0x0300; /* set WA16 stereo */
96 } else if (fmt & AFMT_U8) { 96 } else if (fmt & AFMT_U8) {
97 tmp &= ~0x0100; /* clear WA16 */ 97 tmp &= ~0x0100; /* clear WA16 */
98 } 98 }
99 AD1889_WRITEW(ad1889_dev, AD_DSWSMC, tmp); 99 AD1889_WRITEW(ad1889_dev, AD_DS_WSMC, tmp);
100} 100}
101 101
102static inline void ad1889_set_adc_fmt(ad1889_dev_t *dev, int fmt) 102static inline void ad1889_set_adc_fmt(ad1889_dev_t *dev, int fmt)
@@ -105,13 +105,13 @@ static inline void ad1889_set_adc_fmt(ad1889_dev_t *dev, int fmt)
105 105
106 DBG("Setting ADC format to 0x%x\n", fmt); 106 DBG("Setting ADC format to 0x%x\n", fmt);
107 107
108 tmp = AD1889_READW(ad1889_dev, AD_DSRAMC); 108 tmp = AD1889_READW(ad1889_dev, AD_DS_RAMC);
109 if (fmt & AFMT_S16_LE) { 109 if (fmt & AFMT_S16_LE) {
110 tmp |= 0x0100; /* set WA16 */ 110 tmp |= 0x0100; /* set WA16 */
111 } else if (fmt & AFMT_U8) { 111 } else if (fmt & AFMT_U8) {
112 tmp &= ~0x0100; /* clear WA16 */ 112 tmp &= ~0x0100; /* clear WA16 */
113 } 113 }
114 AD1889_WRITEW(ad1889_dev, AD_DSRAMC, tmp); 114 AD1889_WRITEW(ad1889_dev, AD_DS_RAMC, tmp);
115} 115}
116 116
117static void ad1889_start_wav(ad1889_state_t *state) 117static void ad1889_start_wav(ad1889_state_t *state)
@@ -145,21 +145,21 @@ static void ad1889_start_wav(ad1889_state_t *state)
145 dmabuf->rd_ptr, dmabuf->dma_len); 145 dmabuf->rd_ptr, dmabuf->dma_len);
146 146
147 /* load up the current register set */ 147 /* load up the current register set */
148 AD1889_WRITEL(ad1889_dev, AD_DMAWAVCC, cnt); 148 AD1889_WRITEL(ad1889_dev, AD_DMA_WAVCC, cnt);
149 AD1889_WRITEL(ad1889_dev, AD_DMAWAVICC, cnt); 149 AD1889_WRITEL(ad1889_dev, AD_DMA_WAVICC, cnt);
150 AD1889_WRITEL(ad1889_dev, AD_DMAWAVCA, dmabuf->dma_handle); 150 AD1889_WRITEL(ad1889_dev, AD_DMA_WAVCA, dmabuf->dma_handle);
151 151
152 /* TODO: for now we load the base registers with the same thing */ 152 /* TODO: for now we load the base registers with the same thing */
153 AD1889_WRITEL(ad1889_dev, AD_DMAWAVBC, cnt); 153 AD1889_WRITEL(ad1889_dev, AD_DMA_WAVBC, cnt);
154 AD1889_WRITEL(ad1889_dev, AD_DMAWAVIBC, cnt); 154 AD1889_WRITEL(ad1889_dev, AD_DMA_WAVIBC, cnt);
155 AD1889_WRITEL(ad1889_dev, AD_DMAWAVBA, dmabuf->dma_handle); 155 AD1889_WRITEL(ad1889_dev, AD_DMA_WAVBA, dmabuf->dma_handle);
156 156
157 /* and we're off to the races... */ 157 /* and we're off to the races... */
158 AD1889_WRITEL(ad1889_dev, AD_DMACHSS, 0x8); 158 AD1889_WRITEL(ad1889_dev, AD_DMA_CHSS, 0x8);
159 tmp = AD1889_READW(ad1889_dev, AD_DSWSMC); 159 tmp = AD1889_READW(ad1889_dev, AD_DS_WSMC);
160 tmp |= 0x0400; /* set WAEN */ 160 tmp |= 0x0400; /* set WAEN */
161 AD1889_WRITEW(ad1889_dev, AD_DSWSMC, tmp); 161 AD1889_WRITEW(ad1889_dev, AD_DS_WSMC, tmp);
162 (void) AD1889_READW(ad1889_dev, AD_DSWSMC); /* flush posted PCI write */ 162 (void) AD1889_READW(ad1889_dev, AD_DS_WSMC); /* flush posted PCI write */
163 163
164 dmabuf->enable |= DAC_RUNNING; 164 dmabuf->enable |= DAC_RUNNING;
165 165
@@ -179,10 +179,10 @@ static void ad1889_stop_wav(ad1889_state_t *state)
179 u16 tmp; 179 u16 tmp;
180 unsigned long cnt = dmabuf->dma_len; 180 unsigned long cnt = dmabuf->dma_len;
181 181
182 tmp = AD1889_READW(ad1889_dev, AD_DSWSMC); 182 tmp = AD1889_READW(ad1889_dev, AD_DS_WSMC);
183 tmp &= ~0x0400; /* clear WAEN */ 183 tmp &= ~0x0400; /* clear WAEN */
184 AD1889_WRITEW(ad1889_dev, AD_DSWSMC, tmp); 184 AD1889_WRITEW(ad1889_dev, AD_DS_WSMC, tmp);
185 (void) AD1889_READW(ad1889_dev, AD_DSWSMC); /* flush posted PCI write */ 185 (void) AD1889_READW(ad1889_dev, AD_DS_WSMC); /* flush posted PCI write */
186 pci_unmap_single(ad1889_dev->pci, dmabuf->dma_handle, 186 pci_unmap_single(ad1889_dev->pci, dmabuf->dma_handle,
187 cnt, PCI_DMA_TODEVICE); 187 cnt, PCI_DMA_TODEVICE);
188 188
@@ -211,7 +211,7 @@ static void ad1889_startstop_adc(ad1889_state_t *state, int start)
211 211
212 spin_lock_irqsave(&state->card->lock, flags); 212 spin_lock_irqsave(&state->card->lock, flags);
213 213
214 tmp = AD1889_READW(ad1889_dev, AD_DSRAMC); 214 tmp = AD1889_READW(ad1889_dev, AD_DS_RAMC);
215 if (start) { 215 if (start) {
216 state->dmabuf.enable |= ADC_RUNNING; 216 state->dmabuf.enable |= ADC_RUNNING;
217 tmp |= 0x0004; /* set ADEN */ 217 tmp |= 0x0004; /* set ADEN */
@@ -219,7 +219,7 @@ static void ad1889_startstop_adc(ad1889_state_t *state, int start)
219 state->dmabuf.enable &= ~ADC_RUNNING; 219 state->dmabuf.enable &= ~ADC_RUNNING;
220 tmp &= ~0x0004; /* clear ADEN */ 220 tmp &= ~0x0004; /* clear ADEN */
221 } 221 }
222 AD1889_WRITEW(ad1889_dev, AD_DSRAMC, tmp); 222 AD1889_WRITEW(ad1889_dev, AD_DS_RAMC, tmp);
223 223
224 spin_unlock_irqrestore(&state->card->lock, flags); 224 spin_unlock_irqrestore(&state->card->lock, flags);
225} 225}
@@ -301,53 +301,53 @@ static int ad1889_read_proc (char *page, char **start, off_t off,
301 int len, i; 301 int len, i;
302 ad1889_dev_t *dev = data; 302 ad1889_dev_t *dev = data;
303 ad1889_reg_t regs[] = { 303 ad1889_reg_t regs[] = {
304 { "WSMC", AD_DSWSMC, 16 }, 304 { "WSMC", AD_DS_WSMC, 16 },
305 { "RAMC", AD_DSRAMC, 16 }, 305 { "RAMC", AD_DS_RAMC, 16 },
306 { "WADA", AD_DSWADA, 16 }, 306 { "WADA", AD_DS_WADA, 16 },
307 { "SYDA", AD_DSSYDA, 16 }, 307 { "SYDA", AD_DS_SYDA, 16 },
308 { "WAS", AD_DSWAS, 16 }, 308 { "WAS", AD_DS_WAS, 16 },
309 { "RES", AD_DSRES, 16 }, 309 { "RES", AD_DS_RES, 16 },
310 { "CCS", AD_DSCCS, 16 }, 310 { "CCS", AD_DS_CCS, 16 },
311 { "ADCBA", AD_DMAADCBA, 32 }, 311 { "ADCBA", AD_DMA_ADCBA, 32 },
312 { "ADCCA", AD_DMAADCCA, 32 }, 312 { "ADCCA", AD_DMA_ADCCA, 32 },
313 { "ADCBC", AD_DMAADCBC, 32 }, 313 { "ADCBC", AD_DMA_ADCBC, 32 },
314 { "ADCCC", AD_DMAADCCC, 32 }, 314 { "ADCCC", AD_DMA_ADCCC, 32 },
315 { "ADCIBC", AD_DMAADCIBC, 32 }, 315 { "ADCIBC", AD_DMA_ADCIBC, 32 },
316 { "ADCICC", AD_DMAADCICC, 32 }, 316 { "ADCICC", AD_DMA_ADCICC, 32 },
317 { "ADCCTRL", AD_DMAADCCTRL, 16 }, 317 { "ADCCTRL", AD_DMA_ADCCTRL, 16 },
318 { "WAVBA", AD_DMAWAVBA, 32 }, 318 { "WAVBA", AD_DMA_WAVBA, 32 },
319 { "WAVCA", AD_DMAWAVCA, 32 }, 319 { "WAVCA", AD_DMA_WAVCA, 32 },
320 { "WAVBC", AD_DMAWAVBC, 32 }, 320 { "WAVBC", AD_DMA_WAVBC, 32 },
321 { "WAVCC", AD_DMAWAVCC, 32 }, 321 { "WAVCC", AD_DMA_WAVCC, 32 },
322 { "WAVIBC", AD_DMAWAVIBC, 32 }, 322 { "WAVIBC", AD_DMA_WAVIBC, 32 },
323 { "WAVICC", AD_DMAWAVICC, 32 }, 323 { "WAVICC", AD_DMA_WAVICC, 32 },
324 { "WAVCTRL", AD_DMAWAVCTRL, 16 }, 324 { "WAVCTRL", AD_DMA_WAVCTRL, 16 },
325 { "DISR", AD_DMADISR, 32 }, 325 { "DISR", AD_DMA_DISR, 32 },
326 { "CHSS", AD_DMACHSS, 32 }, 326 { "CHSS", AD_DMA_CHSS, 32 },
327 { "IPC", AD_GPIOIPC, 16 }, 327 { "IPC", AD_GPIO_IPC, 16 },
328 { "OP", AD_GPIOOP, 16 }, 328 { "OP", AD_GPIO_OP, 16 },
329 { "IP", AD_GPIOIP, 16 }, 329 { "IP", AD_GPIO_IP, 16 },
330 { "ACIC", AD_ACIC, 16 }, 330 { "ACIC", AD_AC97_ACIC, 16 },
331 { "AC97_RESET", 0x100 + AC97_RESET, 16 }, 331 { "AC97_RESET", AD_AC97_BASE + AC97_RESET, 16 },
332 { "AC97_MASTER_VOL_STEREO", 0x100 + AC97_MASTER_VOL_STEREO, 16 }, 332 { "AC97_MASTER_VOL_STEREO", AD_AC97_BASE + AC97_MASTER_VOL_STEREO, 16 },
333 { "AC97_HEADPHONE_VOL", 0x100 + AC97_HEADPHONE_VOL, 16 }, 333 { "AC97_HEADPHONE_VOL", AD_AC97_BASE + AC97_HEADPHONE_VOL, 16 },
334 { "AC97_MASTER_VOL_MONO", 0x100 + AC97_MASTER_VOL_MONO, 16 }, 334 { "AC97_MASTER_VOL_MONO", AD_AC97_BASE + AC97_MASTER_VOL_MONO, 16 },
335 { "AC97_MASTER_TONE", 0x100 + AC97_MASTER_TONE, 16 }, 335 { "AC97_MASTER_TONE", AD_AC97_BASE + AC97_MASTER_TONE, 16 },
336 { "AC97_PCBEEP_VOL", 0x100 + AC97_PCBEEP_VOL, 16 }, 336 { "AC97_PCBEEP_VOL", AD_AC97_BASE + AC97_PCBEEP_VOL, 16 },
337 { "AC97_PHONE_VOL", 0x100 + AC97_PHONE_VOL, 16 }, 337 { "AC97_PHONE_VOL", AD_AC97_BASE + AC97_PHONE_VOL, 16 },
338 { "AC97_MIC_VOL", 0x100 + AC97_MIC_VOL, 16 }, 338 { "AC97_MIC_VOL", AD_AC97_BASE + AC97_MIC_VOL, 16 },
339 { "AC97_LINEIN_VOL", 0x100 + AC97_LINEIN_VOL, 16 }, 339 { "AC97_LINEIN_VOL", AD_AC97_BASE + AC97_LINEIN_VOL, 16 },
340 { "AC97_CD_VOL", 0x100 + AC97_CD_VOL, 16 }, 340 { "AC97_CD_VOL", AD_AC97_BASE + AC97_CD_VOL, 16 },
341 { "AC97_VIDEO_VOL", 0x100 + AC97_VIDEO_VOL, 16 }, 341 { "AC97_VIDEO_VOL", AD_AC97_BASE + AC97_VIDEO_VOL, 16 },
342 { "AC97_AUX_VOL", 0x100 + AC97_AUX_VOL, 16 }, 342 { "AC97_AUX_VOL", AD_AC97_BASE + AC97_AUX_VOL, 16 },
343 { "AC97_PCMOUT_VOL", 0x100 + AC97_PCMOUT_VOL, 16 }, 343 { "AC97_PCMOUT_VOL", AD_AC97_BASE + AC97_PCMOUT_VOL, 16 },
344 { "AC97_RECORD_SELECT", 0x100 + AC97_RECORD_SELECT, 16 }, 344 { "AC97_RECORD_SELECT", AD_AC97_BASE + AC97_RECORD_SELECT, 16 },
345 { "AC97_RECORD_GAIN", 0x100 + AC97_RECORD_GAIN, 16 }, 345 { "AC97_RECORD_GAIN", AD_AC97_BASE + AC97_RECORD_GAIN, 16 },
346 { "AC97_RECORD_GAIN_MIC", 0x100 + AC97_RECORD_GAIN_MIC, 16 }, 346 { "AC97_RECORD_GAIN_MIC", AD_AC97_BASE + AC97_RECORD_GAIN_MIC, 16 },
347 { "AC97_GENERAL_PURPOSE", 0x100 + AC97_GENERAL_PURPOSE, 16 }, 347 { "AC97_GENERAL_PURPOSE", AD_AC97_BASE + AC97_GENERAL_PURPOSE, 16 },
348 { "AC97_3D_CONTROL", 0x100 + AC97_3D_CONTROL, 16 }, 348 { "AC97_3D_CONTROL", AD_AC97_BASE + AC97_3D_CONTROL, 16 },
349 { "AC97_MODEM_RATE", 0x100 + AC97_MODEM_RATE, 16 }, 349 { "AC97_MODEM_RATE", AD_AC97_BASE + AC97_MODEM_RATE, 16 },
350 { "AC97_POWER_CONTROL", 0x100 + AC97_POWER_CONTROL, 16 }, 350 { "AC97_POWER_CONTROL", AD_AC97_BASE + AC97_POWER_CONTROL, 16 },
351 { NULL } 351 { NULL }
352 }; 352 };
353 353
@@ -400,9 +400,9 @@ static inline unsigned long ad1889_get_dma_addr(ad1889_state_t *state)
400 } 400 }
401 401
402 if (dmabuf->enable & DAC_RUNNING) 402 if (dmabuf->enable & DAC_RUNNING)
403 offset = le32_to_cpu(AD1889_READL(state->card, AD_DMAWAVBA)); 403 offset = le32_to_cpu(AD1889_READL(state->card, AD_DMA_WAVBA));
404 else 404 else
405 offset = le32_to_cpu(AD1889_READL(state->card, AD_DMAADCBA)); 405 offset = le32_to_cpu(AD1889_READL(state->card, AD_DMA_ADCBA));
406 406
407 return (unsigned long)bus_to_virt((unsigned long)offset) - (unsigned long)dmabuf->rawbuf; 407 return (unsigned long)bus_to_virt((unsigned long)offset) - (unsigned long)dmabuf->rawbuf;
408} 408}
@@ -639,9 +639,9 @@ static int ad1889_ioctl(struct inode *inode, struct file *file, unsigned int cmd
639 if (val > 5400 && val < 48000) 639 if (val > 5400 && val < 48000)
640 { 640 {
641 if (file->f_mode & FMODE_WRITE) 641 if (file->f_mode & FMODE_WRITE)
642 AD1889_WRITEW(ad1889_dev, AD_DSWAS, val); 642 AD1889_WRITEW(ad1889_dev, AD_DS_WAS, val);
643 if (file->f_mode & FMODE_READ) 643 if (file->f_mode & FMODE_READ)
644 AD1889_WRITEW(ad1889_dev, AD_DSRES, val); 644 AD1889_WRITEW(ad1889_dev, AD_DS_RES, val);
645 } 645 }
646 return 0; 646 return 0;
647 647
@@ -649,22 +649,22 @@ static int ad1889_ioctl(struct inode *inode, struct file *file, unsigned int cmd
649 if (get_user(val, p)) 649 if (get_user(val, p))
650 return -EFAULT; 650 return -EFAULT;
651 if (file->f_mode & FMODE_READ) { 651 if (file->f_mode & FMODE_READ) {
652 val = AD1889_READW(ad1889_dev, AD_DSWSMC); 652 val = AD1889_READW(ad1889_dev, AD_DS_WSMC);
653 if (val) { 653 if (val) {
654 val |= 0x0200; /* set WAST */ 654 val |= 0x0200; /* set WAST */
655 } else { 655 } else {
656 val &= ~0x0200; /* clear WAST */ 656 val &= ~0x0200; /* clear WAST */
657 } 657 }
658 AD1889_WRITEW(ad1889_dev, AD_DSWSMC, val); 658 AD1889_WRITEW(ad1889_dev, AD_DS_WSMC, val);
659 } 659 }
660 if (file->f_mode & FMODE_WRITE) { 660 if (file->f_mode & FMODE_WRITE) {
661 val = AD1889_READW(ad1889_dev, AD_DSRAMC); 661 val = AD1889_READW(ad1889_dev, AD_DS_RAMC);
662 if (val) { 662 if (val) {
663 val |= 0x0002; /* set ADST */ 663 val |= 0x0002; /* set ADST */
664 } else { 664 } else {
665 val &= ~0x0002; /* clear ADST */ 665 val &= ~0x0002; /* clear ADST */
666 } 666 }
667 AD1889_WRITEW(ad1889_dev, AD_DSRAMC, val); 667 AD1889_WRITEW(ad1889_dev, AD_DS_RAMC, val);
668 } 668 }
669 669
670 return 0; 670 return 0;
@@ -739,7 +739,7 @@ static int ad1889_ioctl(struct inode *inode, struct file *file, unsigned int cmd
739 break; 739 break;
740 740
741 case SOUND_PCM_READ_RATE: 741 case SOUND_PCM_READ_RATE:
742 return put_user(AD1889_READW(ad1889_dev, AD_DSWAS), p); 742 return put_user(AD1889_READW(ad1889_dev, AD_DS_WAS), p);
743 743
744 case SOUND_PCM_READ_CHANNELS: 744 case SOUND_PCM_READ_CHANNELS:
745 case SOUND_PCM_READ_BITS: 745 case SOUND_PCM_READ_BITS:
@@ -769,7 +769,7 @@ static int ad1889_open(struct inode *inode, struct file *file)
769 769
770 ad1889_set_wav_rate(ad1889_dev, 48000); 770 ad1889_set_wav_rate(ad1889_dev, 48000);
771 ad1889_set_wav_fmt(ad1889_dev, AFMT_S16_LE); 771 ad1889_set_wav_fmt(ad1889_dev, AFMT_S16_LE);
772 AD1889_WRITEW(ad1889_dev, AD_DSWADA, 0x0404); /* attenuation */ 772 AD1889_WRITEW(ad1889_dev, AD_DS_WADA, 0x0404); /* attenuation */
773 return nonseekable_open(inode, file); 773 return nonseekable_open(inode, file);
774} 774}
775 775
@@ -826,15 +826,15 @@ static void ad1889_codec_write(struct ac97_codec *ac97, u8 reg, u16 val)
826{ 826{
827 ad1889_dev_t *dev = ac97->private_data; 827 ad1889_dev_t *dev = ac97->private_data;
828 828
829 //DBG("Writing 0x%x to 0x%lx\n", val, dev->regbase + 0x100 + reg); 829 //DBG("Writing 0x%x to 0x%lx\n", val, dev->regbase + AD_AC97_BASE + reg);
830 AD1889_WRITEW(dev, 0x100 + reg, val); 830 AD1889_WRITEW(dev, AD_AC97_BASE + reg, val);
831} 831}
832 832
833static u16 ad1889_codec_read(struct ac97_codec *ac97, u8 reg) 833static u16 ad1889_codec_read(struct ac97_codec *ac97, u8 reg)
834{ 834{
835 ad1889_dev_t *dev = ac97->private_data; 835 ad1889_dev_t *dev = ac97->private_data;
836 //DBG("Reading from 0x%lx\n", dev->regbase + 0x100 + reg); 836 //DBG("Reading from 0x%lx\n", dev->regbase + AD_AC97_BASE + reg);
837 return AD1889_READW(dev, 0x100 + reg); 837 return AD1889_READW(dev, AD_AC97_BASE + reg);
838} 838}
839 839
840static int ad1889_ac97_init(ad1889_dev_t *dev, int id) 840static int ad1889_ac97_init(ad1889_dev_t *dev, int id)
@@ -883,24 +883,24 @@ static int ad1889_aclink_reset(struct pci_dev * pcidev)
883 int retry = 200; 883 int retry = 200;
884 ad1889_dev_t *dev = pci_get_drvdata(pcidev); 884 ad1889_dev_t *dev = pci_get_drvdata(pcidev);
885 885
886 AD1889_WRITEW(dev, AD_DSCCS, 0x8000); /* turn on clock */ 886 AD1889_WRITEW(dev, AD_DS_CCS, 0x8000); /* turn on clock */
887 AD1889_READW(dev, AD_DSCCS); 887 AD1889_READW(dev, AD_DS_CCS);
888 888
889 WAIT_10MS(); 889 WAIT_10MS();
890 890
891 stat = AD1889_READW(dev, AD_ACIC); 891 stat = AD1889_READW(dev, AD_AC97_ACIC);
892 stat |= 0x0002; /* Reset Disable */ 892 stat |= 0x0002; /* Reset Disable */
893 AD1889_WRITEW(dev, AD_ACIC, stat); 893 AD1889_WRITEW(dev, AD_AC97_ACIC, stat);
894 (void) AD1889_READW(dev, AD_ACIC); /* flush posted write */ 894 (void) AD1889_READW(dev, AD_AC97_ACIC); /* flush posted write */
895 895
896 udelay(10); 896 udelay(10);
897 897
898 stat = AD1889_READW(dev, AD_ACIC); 898 stat = AD1889_READW(dev, AD_AC97_ACIC);
899 stat |= 0x0001; /* Interface Enable */ 899 stat |= 0x0001; /* Interface Enable */
900 AD1889_WRITEW(dev, AD_ACIC, stat); 900 AD1889_WRITEW(dev, AD_AC97_ACIC, stat);
901 901
902 do { 902 do {
903 if (AD1889_READW(dev, AD_ACIC) & 0x8000) /* Ready */ 903 if (AD1889_READW(dev, AD_AC97_ACIC) & 0x8000) /* Ready */
904 break; 904 break;
905 WAIT_10MS(); 905 WAIT_10MS();
906 retry--; 906 retry--;
@@ -908,16 +908,16 @@ static int ad1889_aclink_reset(struct pci_dev * pcidev)
908 908
909 if (!retry) { 909 if (!retry) {
910 printk(KERN_ERR "ad1889_aclink_reset: codec is not ready [0x%x]\n", 910 printk(KERN_ERR "ad1889_aclink_reset: codec is not ready [0x%x]\n",
911 AD1889_READW(dev, AD_ACIC)); 911 AD1889_READW(dev, AD_AC97_ACIC));
912 return -EBUSY; 912 return -EBUSY;
913 } 913 }
914 914
915 /* TODO reset AC97 codec */ 915 /* TODO reset AC97 codec */
916 /* TODO set wave/adc pci ctrl status */ 916 /* TODO set wave/adc pci ctrl status */
917 917
918 stat = AD1889_READW(dev, AD_ACIC); 918 stat = AD1889_READW(dev, AD_AC97_ACIC);
919 stat |= 0x0004; /* Audio Stream Output Enable */ 919 stat |= 0x0004; /* Audio Stream Output Enable */
920 AD1889_WRITEW(dev, AD_ACIC, stat); 920 AD1889_WRITEW(dev, AD_AC97_ACIC, stat);
921 return 0; 921 return 0;
922} 922}
923 923
@@ -935,10 +935,10 @@ static irqreturn_t ad1889_interrupt(int irq, void *dev_id, struct pt_regs *regs)
935 u32 stat; 935 u32 stat;
936 ad1889_dev_t *dev = (ad1889_dev_t *)dev_id; 936 ad1889_dev_t *dev = (ad1889_dev_t *)dev_id;
937 937
938 stat = AD1889_READL(dev, AD_DMADISR); 938 stat = AD1889_READL(dev, AD_DMA_DISR);
939 939
940 /* clear ISR */ 940 /* clear ISR */
941 AD1889_WRITEL(dev, AD_DMADISR, stat); 941 AD1889_WRITEL(dev, AD_DMA_DISR, stat);
942 942
943 if (stat & 0x8) { /* WAVI */ 943 if (stat & 0x8) { /* WAVI */
944 DBG("WAV interrupt\n"); 944 DBG("WAV interrupt\n");
@@ -964,15 +964,15 @@ static void ad1889_initcfg(ad1889_dev_t *dev)
964 u32 tmp32; 964 u32 tmp32;
965 965
966 /* make sure the interrupt bits are setup the way we want */ 966 /* make sure the interrupt bits are setup the way we want */
967 tmp32 = AD1889_READL(dev, AD_DMAWAVCTRL); 967 tmp32 = AD1889_READL(dev, AD_DMA_WAVCTRL);
968 tmp32 &= ~0xff; /* flat dma, no sg, mask out the intr bits */ 968 tmp32 &= ~0xff; /* flat dma, no sg, mask out the intr bits */
969 tmp32 |= 0x6; /* intr on count, loop */ 969 tmp32 |= 0x6; /* intr on count, loop */
970 AD1889_WRITEL(dev, AD_DMAWAVCTRL, tmp32); 970 AD1889_WRITEL(dev, AD_DMA_WAVCTRL, tmp32);
971 971
972 /* unmute... */ 972 /* unmute... */
973 tmp16 = AD1889_READW(dev, AD_DSWADA); 973 tmp16 = AD1889_READW(dev, AD_DS_WADA);
974 tmp16 &= ~0x8080; 974 tmp16 &= ~0x8080;
975 AD1889_WRITEW(dev, AD_DSWADA, tmp16); 975 AD1889_WRITEW(dev, AD_DS_WADA, tmp16);
976} 976}
977 977
978static int __devinit ad1889_probe(struct pci_dev *pcidev, const struct pci_device_id *ent) 978static int __devinit ad1889_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
@@ -1005,7 +1005,7 @@ static int __devinit ad1889_probe(struct pci_dev *pcidev, const struct pci_devic
1005 goto out1; 1005 goto out1;
1006 } 1006 }
1007 1007
1008 dev->regbase = ioremap_nocache(bar, AD_DSIOMEMSIZE); 1008 dev->regbase = ioremap_nocache(bar, AD_DS_IOMEMSIZE);
1009 if (!dev->regbase) { 1009 if (!dev->regbase) {
1010 printk(KERN_ERR DEVNAME ": unable to remap iomem\n"); 1010 printk(KERN_ERR DEVNAME ": unable to remap iomem\n");
1011 goto out2; 1011 goto out2;
diff --git a/sound/oss/ad1889.h b/sound/oss/ad1889.h
index 861b3213f30b..09913765967a 100644
--- a/sound/oss/ad1889.h
+++ b/sound/oss/ad1889.h
@@ -1,57 +1,58 @@
1#ifndef _AD1889_H_ 1#ifndef _AD1889_H_
2#define _AD1889_H_ 2#define _AD1889_H_
3 3
4#define AD_DSWSMC 0x00 /* DMA input wave/syn mixer control */ 4#define AD_DS_WSMC 0x00 /* DMA input wave/syn mixer control */
5#define AD_DSRAMC 0x02 /* DMA output resamp/ADC mixer control */ 5#define AD_DS_RAMC 0x02 /* DMA output resamp/ADC mixer control */
6#define AD_DSWADA 0x04 /* DMA input wave attenuation */ 6#define AD_DS_WADA 0x04 /* DMA input wave attenuation */
7#define AD_DSSYDA 0x06 /* DMA input syn attentuation */ 7#define AD_DS_SYDA 0x06 /* DMA input syn attentuation */
8#define AD_DSWAS 0x08 /* wave input sample rate */ 8#define AD_DS_WAS 0x08 /* wave input sample rate */
9#define AD_DSRES 0x0a /* resampler output sample rate */ 9#define AD_DS_RES 0x0a /* resampler output sample rate */
10#define AD_DSCCS 0x0c /* chip control/status */ 10#define AD_DS_CCS 0x0c /* chip control/status */
11 11
12#define AD_DMARESBA 0x40 /* RES base addr */ 12#define AD_DMA_RESBA 0x40 /* RES base addr */
13#define AD_DMARESCA 0x44 /* RES current addr */ 13#define AD_DMA_RESCA 0x44 /* RES current addr */
14#define AD_DMARESBC 0x48 /* RES base cnt */ 14#define AD_DMA_RESBC 0x48 /* RES base cnt */
15#define AD_DMARESCC 0x4c /* RES current count */ 15#define AD_DMA_RESCC 0x4c /* RES current count */
16#define AD_DMAADCBA 0x50 /* ADC */ 16#define AD_DMA_ADCBA 0x50 /* ADC */
17#define AD_DMAADCCA 0x54 17#define AD_DMA_ADCCA 0x54
18#define AD_DMAADCBC 0x58 18#define AD_DMA_ADCBC 0x58
19#define AD_DMAADCCC 0x5c 19#define AD_DMA_ADCCC 0x5c
20#define AD_DMASYNBA 0x60 /* SYN */ 20#define AD_DMA_SYNBA 0x60 /* SYN */
21#define AD_DMASYNCA 0x64 21#define AD_DMA_SYNCA 0x64
22#define AD_DMASYNBC 0x68 22#define AD_DMA_SYNBC 0x68
23#define AD_DMASYNCC 0x6c 23#define AD_DMA_SYNCC 0x6c
24#define AD_DMAWAVBA 0x70 /* WAV */ 24#define AD_DMA_WAVBA 0x70 /* WAV */
25#define AD_DMAWAVCA 0x74 25#define AD_DMA_WAVCA 0x74
26#define AD_DMAWAVBC 0x78 26#define AD_DMA_WAVBC 0x78
27#define AD_DMAWAVCC 0x7c 27#define AD_DMA_WAVCC 0x7c
28#define AD_DMARESICC 0x80 /* RES interrupt current count */ 28#define AD_DMA_RESICC 0x80 /* RES interrupt current count */
29#define AD_DMARESIBC 0x84 /* RES interrupt base count */ 29#define AD_DMA_RESIBC 0x84 /* RES interrupt base count */
30#define AD_DMAADCICC 0x88 /* ADC interrupt current count */ 30#define AD_DMA_ADCICC 0x88 /* ADC interrupt current count */
31#define AD_DMAADCIBC 0x8c /* ADC interrupt base count */ 31#define AD_DMA_ADCIBC 0x8c /* ADC interrupt base count */
32#define AD_DMASYNICC 0x90 /* SYN interrupt current count */ 32#define AD_DMA_SYNICC 0x90 /* SYN interrupt current count */
33#define AD_DMASYNIBC 0x94 /* SYN interrupt base count */ 33#define AD_DMA_SYNIBC 0x94 /* SYN interrupt base count */
34#define AD_DMAWAVICC 0x98 /* WAV interrupt current count */ 34#define AD_DMA_WAVICC 0x98 /* WAV interrupt current count */
35#define AD_DMAWAVIBC 0x9c /* WAV interrupt base count */ 35#define AD_DMA_WAVIBC 0x9c /* WAV interrupt base count */
36#define AD_DMARESCTRL 0xa0 /* RES PCI control/status */ 36#define AD_DMA_RESCTRL 0xa0 /* RES PCI control/status */
37#define AD_DMAADCCTRL 0xa8 /* ADC PCI control/status */ 37#define AD_DMA_ADCCTRL 0xa8 /* ADC PCI control/status */
38#define AD_DMASYNCTRL 0xb0 /* SYN PCI control/status */ 38#define AD_DMA_SYNCTRL 0xb0 /* SYN PCI control/status */
39#define AD_DMAWAVCTRL 0xb8 /* WAV PCI control/status */ 39#define AD_DMA_WAVCTRL 0xb8 /* WAV PCI control/status */
40#define AD_DMADISR 0xc0 /* PCI DMA intr status */ 40#define AD_DMA_DISR 0xc0 /* PCI DMA intr status */
41#define AD_DMACHSS 0xc4 /* PCI DMA channel stop status */ 41#define AD_DMA_CHSS 0xc4 /* PCI DMA channel stop status */
42 42
43#define AD_GPIOIPC 0xc8 /* IO port ctrl */ 43#define AD_GPIO_IPC 0xc8 /* IO port ctrl */
44#define AD_GPIOOP 0xca /* IO output status */ 44#define AD_GPIO_OP 0xca /* IO output status */
45#define AD_GPIOIP 0xcc /* IO input status */ 45#define AD_GPIO_IP 0xcc /* IO input status */
46 46
47/* AC97 registers, 0x100 - 0x17f; see ac97.h */ 47/* AC97 registers, 0x100 - 0x17f; see ac97.h */
48#define AD_ACIC 0x180 /* AC Link interface ctrl */ 48#define AD_AC97_BASE 0x100 /* ac97 base register */
49#define AD_AC97_ACIC 0x180 /* AC Link interface ctrl */
49 50
50/* OPL3; BAR1 */ 51/* OPL3; BAR1 */
51#define AD_OPLM0AS 0x00 /* Music0 address/status */ 52#define AD_OPL_M0AS 0x00 /* Music0 address/status */
52#define AD_OPLM0DATA 0x01 /* Music0 data */ 53#define AD_OPL_M0DATA 0x01 /* Music0 data */
53#define AD_OPLM1A 0x02 /* Music1 address */ 54#define AD_OPL_M1A 0x02 /* Music1 address */
54#define AD_OPLM1DATA 0x03 /* Music1 data */ 55#define AD_OPL_M1DATA 0x03 /* Music1 data */
55/* 0x04-0x0f reserved */ 56/* 0x04-0x0f reserved */
56 57
57/* MIDI; BAR2 */ 58/* MIDI; BAR2 */
@@ -59,9 +60,9 @@
59#define AD_MISC 0x01 /* MIDI status/cmd */ 60#define AD_MISC 0x01 /* MIDI status/cmd */
60/* 0x02-0xff reserved */ 61/* 0x02-0xff reserved */
61 62
62#define AD_DSIOMEMSIZE 512 63#define AD_DS_IOMEMSIZE 512
63#define AD_OPLMEMSIZE 16 64#define AD_OPL_MEMSIZE 16
64#define AD_MIDIMEMSIZE 16 65#define AD_MIDI_MEMSIZE 16
65 66
66#define AD_WAV_STATE 0 67#define AD_WAV_STATE 0
67#define AD_ADC_STATE 1 68#define AD_ADC_STATE 1
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 06:12:16 -0500