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-rw-r--r--sound/pci/cs4281.c41
1 files changed, 10 insertions, 31 deletions
diff --git a/sound/pci/cs4281.c b/sound/pci/cs4281.c
index a4b4608034b6..c99bb1f2bfa8 100644
--- a/sound/pci/cs4281.c
+++ b/sound/pci/cs4281.c
@@ -514,27 +514,6 @@ MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
514 * common I/O routines 514 * common I/O routines
515 */ 515 */
516 516
517static void snd_cs4281_delay(unsigned int delay)
518{
519 if (delay > 999) {
520 unsigned long end_time;
521 delay = (delay * HZ) / 1000000;
522 if (delay < 1)
523 delay = 1;
524 end_time = jiffies + delay;
525 do {
526 schedule_timeout_uninterruptible(1);
527 } while (time_after_eq(end_time, jiffies));
528 } else {
529 udelay(delay);
530 }
531}
532
533static inline void snd_cs4281_delay_long(void)
534{
535 schedule_timeout_uninterruptible(1);
536}
537
538static inline void snd_cs4281_pokeBA0(cs4281_t *chip, unsigned long offset, unsigned int val) 517static inline void snd_cs4281_pokeBA0(cs4281_t *chip, unsigned long offset, unsigned int val)
539{ 518{
540 writel(val, chip->ba0 + offset); 519 writel(val, chip->ba0 + offset);
@@ -1493,7 +1472,7 @@ static int snd_cs4281_chip_init(cs4281_t *chip)
1493 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0); 1472 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1494 udelay(50); 1473 udelay(50);
1495 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN); 1474 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1496 snd_cs4281_delay(50000); 1475 msleep(50);
1497 1476
1498 if (chip->dual_codec) 1477 if (chip->dual_codec)
1499 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E); 1478 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
@@ -1509,13 +1488,13 @@ static int snd_cs4281_chip_init(cs4281_t *chip)
1509 * Start the DLL Clock logic. 1488 * Start the DLL Clock logic.
1510 */ 1489 */
1511 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP); 1490 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1512 snd_cs4281_delay(50000); 1491 msleep(50);
1513 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP); 1492 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1514 1493
1515 /* 1494 /*
1516 * Wait for the DLL ready signal from the clock logic. 1495 * Wait for the DLL ready signal from the clock logic.
1517 */ 1496 */
1518 timeout = HZ; 1497 timeout = 100;
1519 do { 1498 do {
1520 /* 1499 /*
1521 * Read the AC97 status register to see if we've seen a CODEC 1500 * Read the AC97 status register to see if we've seen a CODEC
@@ -1523,7 +1502,7 @@ static int snd_cs4281_chip_init(cs4281_t *chip)
1523 */ 1502 */
1524 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY) 1503 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1525 goto __ok0; 1504 goto __ok0;
1526 snd_cs4281_delay_long(); 1505 msleep(1);
1527 } while (timeout-- > 0); 1506 } while (timeout-- > 0);
1528 1507
1529 snd_printk(KERN_ERR "DLLRDY not seen\n"); 1508 snd_printk(KERN_ERR "DLLRDY not seen\n");
@@ -1541,7 +1520,7 @@ static int snd_cs4281_chip_init(cs4281_t *chip)
1541 /* 1520 /*
1542 * Wait for the codec ready signal from the AC97 codec. 1521 * Wait for the codec ready signal from the AC97 codec.
1543 */ 1522 */
1544 timeout = HZ; 1523 timeout = 100;
1545 do { 1524 do {
1546 /* 1525 /*
1547 * Read the AC97 status register to see if we've seen a CODEC 1526 * Read the AC97 status register to see if we've seen a CODEC
@@ -1549,7 +1528,7 @@ static int snd_cs4281_chip_init(cs4281_t *chip)
1549 */ 1528 */
1550 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY) 1529 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1551 goto __ok1; 1530 goto __ok1;
1552 snd_cs4281_delay_long(); 1531 msleep(1);
1553 } while (timeout-- > 0); 1532 } while (timeout-- > 0);
1554 1533
1555 snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS)); 1534 snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
@@ -1557,11 +1536,11 @@ static int snd_cs4281_chip_init(cs4281_t *chip)
1557 1536
1558 __ok1: 1537 __ok1:
1559 if (chip->dual_codec) { 1538 if (chip->dual_codec) {
1560 timeout = HZ; 1539 timeout = 100;
1561 do { 1540 do {
1562 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY) 1541 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1563 goto __codec2_ok; 1542 goto __codec2_ok;
1564 snd_cs4281_delay_long(); 1543 msleep(1);
1565 } while (timeout-- > 0); 1544 } while (timeout-- > 0);
1566 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n"); 1545 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
1567 chip->dual_codec = 0; 1546 chip->dual_codec = 0;
@@ -1580,7 +1559,7 @@ static int snd_cs4281_chip_init(cs4281_t *chip)
1580 * the codec is pumping ADC data across the AC-link. 1559 * the codec is pumping ADC data across the AC-link.
1581 */ 1560 */
1582 1561
1583 timeout = HZ; 1562 timeout = 100;
1584 do { 1563 do {
1585 /* 1564 /*
1586 * Read the input slot valid register and see if input slots 3 1565 * Read the input slot valid register and see if input slots 3
@@ -1588,7 +1567,7 @@ static int snd_cs4281_chip_init(cs4281_t *chip)
1588 */ 1567 */
1589 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) 1568 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1590 goto __ok2; 1569 goto __ok2;
1591 snd_cs4281_delay_long(); 1570 msleep(1);
1592 } while (timeout-- > 0); 1571 } while (timeout-- > 0);
1593 1572
1594 if (--retry_count > 0) 1573 if (--retry_count > 0)