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-rw-r--r--sound/soc/Makefile2
-rw-r--r--sound/soc/codecs/tlv320aic3x.c11
-rw-r--r--sound/soc/codecs/wm8510.c174
-rw-r--r--sound/soc/codecs/wm8523.c98
-rw-r--r--sound/soc/codecs/wm8580.c154
-rw-r--r--sound/soc/codecs/wm8728.c111
-rw-r--r--sound/soc/codecs/wm8731.c141
-rw-r--r--sound/soc/codecs/wm8750.c154
-rw-r--r--sound/soc/codecs/wm8900.c319
-rw-r--r--sound/soc/codecs/wm8903.c244
-rw-r--r--sound/soc/codecs/wm8940.c143
-rw-r--r--sound/soc/codecs/wm8960.c200
-rw-r--r--sound/soc/codecs/wm8961.c231
-rw-r--r--sound/soc/codecs/wm8971.c127
-rw-r--r--sound/soc/codecs/wm8988.c138
-rw-r--r--sound/soc/codecs/wm8990.c194
-rw-r--r--sound/soc/codecs/wm9081.c229
-rw-r--r--sound/soc/soc-cache.c218
18 files changed, 1104 insertions, 1784 deletions
diff --git a/sound/soc/Makefile b/sound/soc/Makefile
index 6f1e28de23cf..4eaf48aab0fa 100644
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
@@ -1,4 +1,4 @@
1snd-soc-core-objs := soc-core.o soc-dapm.o soc-jack.o 1snd-soc-core-objs := soc-core.o soc-dapm.o soc-jack.o soc-cache.o
2 2
3obj-$(CONFIG_SND_SOC) += snd-soc-core.o 3obj-$(CONFIG_SND_SOC) += snd-soc-core.o
4obj-$(CONFIG_SND_SOC) += codecs/ 4obj-$(CONFIG_SND_SOC) += codecs/
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index cb0d1bf34b57..126b15b18aeb 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -145,8 +145,8 @@ static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
145 u8 *value) 145 u8 *value)
146{ 146{
147 *value = reg & 0xff; 147 *value = reg & 0xff;
148 if (codec->hw_read(codec->control_data, value, 1) != 1) 148
149 return -EIO; 149 value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]);
150 150
151 aic3x_write_reg_cache(codec, reg, *value); 151 aic3x_write_reg_cache(codec, reg, *value);
152 return 0; 152 return 0;
@@ -1325,12 +1325,6 @@ static struct i2c_driver aic3x_i2c_driver = {
1325 .id_table = aic3x_i2c_id, 1325 .id_table = aic3x_i2c_id,
1326}; 1326};
1327 1327
1328static int aic3x_i2c_read(struct i2c_client *client, u8 *value, int len)
1329{
1330 value[0] = i2c_smbus_read_byte_data(client, value[0]);
1331 return (len == 1);
1332}
1333
1334static int aic3x_add_i2c_device(struct platform_device *pdev, 1328static int aic3x_add_i2c_device(struct platform_device *pdev,
1335 const struct aic3x_setup_data *setup) 1329 const struct aic3x_setup_data *setup)
1336{ 1330{
@@ -1403,7 +1397,6 @@ static int aic3x_probe(struct platform_device *pdev)
1403#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1397#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1404 if (setup->i2c_address) { 1398 if (setup->i2c_address) {
1405 codec->hw_write = (hw_write_t) i2c_master_send; 1399 codec->hw_write = (hw_write_t) i2c_master_send;
1406 codec->hw_read = (hw_read_t) aic3x_i2c_read;
1407 ret = aic3x_add_i2c_device(pdev, setup); 1400 ret = aic3x_add_i2c_device(pdev, setup);
1408 } 1401 }
1409#else 1402#else
diff --git a/sound/soc/codecs/wm8510.c b/sound/soc/codecs/wm8510.c
index 261d4cb75964..060d5d06ba95 100644
--- a/sound/soc/codecs/wm8510.c
+++ b/sound/soc/codecs/wm8510.c
@@ -58,55 +58,7 @@ static const u16 wm8510_reg[WM8510_CACHEREGNUM] = {
58#define WM8510_POWER1_BIASEN 0x08 58#define WM8510_POWER1_BIASEN 0x08
59#define WM8510_POWER1_BUFIOEN 0x10 59#define WM8510_POWER1_BUFIOEN 0x10
60 60
61/* 61#define wm8510_reset(c) snd_soc_write(c, WM8510_RESET, 0)
62 * read wm8510 register cache
63 */
64static inline unsigned int wm8510_read_reg_cache(struct snd_soc_codec *codec,
65 unsigned int reg)
66{
67 u16 *cache = codec->reg_cache;
68 if (reg == WM8510_RESET)
69 return 0;
70 if (reg >= WM8510_CACHEREGNUM)
71 return -1;
72 return cache[reg];
73}
74
75/*
76 * write wm8510 register cache
77 */
78static inline void wm8510_write_reg_cache(struct snd_soc_codec *codec,
79 u16 reg, unsigned int value)
80{
81 u16 *cache = codec->reg_cache;
82 if (reg >= WM8510_CACHEREGNUM)
83 return;
84 cache[reg] = value;
85}
86
87/*
88 * write to the WM8510 register space
89 */
90static int wm8510_write(struct snd_soc_codec *codec, unsigned int reg,
91 unsigned int value)
92{
93 u8 data[2];
94
95 /* data is
96 * D15..D9 WM8510 register offset
97 * D8...D0 register data
98 */
99 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
100 data[1] = value & 0x00ff;
101
102 wm8510_write_reg_cache(codec, reg, value);
103 if (codec->hw_write(codec->control_data, data, 2) == 2)
104 return 0;
105 else
106 return -EIO;
107}
108
109#define wm8510_reset(c) wm8510_write(c, WM8510_RESET, 0)
110 62
111static const char *wm8510_companding[] = { "Off", "NC", "u-law", "A-law" }; 63static const char *wm8510_companding[] = { "Off", "NC", "u-law", "A-law" };
112static const char *wm8510_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" }; 64static const char *wm8510_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
@@ -327,27 +279,27 @@ static int wm8510_set_dai_pll(struct snd_soc_dai *codec_dai,
327 279
328 if (freq_in == 0 || freq_out == 0) { 280 if (freq_in == 0 || freq_out == 0) {
329 /* Clock CODEC directly from MCLK */ 281 /* Clock CODEC directly from MCLK */
330 reg = wm8510_read_reg_cache(codec, WM8510_CLOCK); 282 reg = snd_soc_read(codec, WM8510_CLOCK);
331 wm8510_write(codec, WM8510_CLOCK, reg & 0x0ff); 283 snd_soc_write(codec, WM8510_CLOCK, reg & 0x0ff);
332 284
333 /* Turn off PLL */ 285 /* Turn off PLL */
334 reg = wm8510_read_reg_cache(codec, WM8510_POWER1); 286 reg = snd_soc_read(codec, WM8510_POWER1);
335 wm8510_write(codec, WM8510_POWER1, reg & 0x1df); 287 snd_soc_write(codec, WM8510_POWER1, reg & 0x1df);
336 return 0; 288 return 0;
337 } 289 }
338 290
339 pll_factors(freq_out*4, freq_in); 291 pll_factors(freq_out*4, freq_in);
340 292
341 wm8510_write(codec, WM8510_PLLN, (pll_div.pre_div << 4) | pll_div.n); 293 snd_soc_write(codec, WM8510_PLLN, (pll_div.pre_div << 4) | pll_div.n);
342 wm8510_write(codec, WM8510_PLLK1, pll_div.k >> 18); 294 snd_soc_write(codec, WM8510_PLLK1, pll_div.k >> 18);
343 wm8510_write(codec, WM8510_PLLK2, (pll_div.k >> 9) & 0x1ff); 295 snd_soc_write(codec, WM8510_PLLK2, (pll_div.k >> 9) & 0x1ff);
344 wm8510_write(codec, WM8510_PLLK3, pll_div.k & 0x1ff); 296 snd_soc_write(codec, WM8510_PLLK3, pll_div.k & 0x1ff);
345 reg = wm8510_read_reg_cache(codec, WM8510_POWER1); 297 reg = snd_soc_read(codec, WM8510_POWER1);
346 wm8510_write(codec, WM8510_POWER1, reg | 0x020); 298 snd_soc_write(codec, WM8510_POWER1, reg | 0x020);
347 299
348 /* Run CODEC from PLL instead of MCLK */ 300 /* Run CODEC from PLL instead of MCLK */
349 reg = wm8510_read_reg_cache(codec, WM8510_CLOCK); 301 reg = snd_soc_read(codec, WM8510_CLOCK);
350 wm8510_write(codec, WM8510_CLOCK, reg | 0x100); 302 snd_soc_write(codec, WM8510_CLOCK, reg | 0x100);
351 303
352 return 0; 304 return 0;
353} 305}
@@ -363,24 +315,24 @@ static int wm8510_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
363 315
364 switch (div_id) { 316 switch (div_id) {
365 case WM8510_OPCLKDIV: 317 case WM8510_OPCLKDIV:
366 reg = wm8510_read_reg_cache(codec, WM8510_GPIO) & 0x1cf; 318 reg = snd_soc_read(codec, WM8510_GPIO) & 0x1cf;
367 wm8510_write(codec, WM8510_GPIO, reg | div); 319 snd_soc_write(codec, WM8510_GPIO, reg | div);
368 break; 320 break;
369 case WM8510_MCLKDIV: 321 case WM8510_MCLKDIV:
370 reg = wm8510_read_reg_cache(codec, WM8510_CLOCK) & 0x11f; 322 reg = snd_soc_read(codec, WM8510_CLOCK) & 0x11f;
371 wm8510_write(codec, WM8510_CLOCK, reg | div); 323 snd_soc_write(codec, WM8510_CLOCK, reg | div);
372 break; 324 break;
373 case WM8510_ADCCLK: 325 case WM8510_ADCCLK:
374 reg = wm8510_read_reg_cache(codec, WM8510_ADC) & 0x1f7; 326 reg = snd_soc_read(codec, WM8510_ADC) & 0x1f7;
375 wm8510_write(codec, WM8510_ADC, reg | div); 327 snd_soc_write(codec, WM8510_ADC, reg | div);
376 break; 328 break;
377 case WM8510_DACCLK: 329 case WM8510_DACCLK:
378 reg = wm8510_read_reg_cache(codec, WM8510_DAC) & 0x1f7; 330 reg = snd_soc_read(codec, WM8510_DAC) & 0x1f7;
379 wm8510_write(codec, WM8510_DAC, reg | div); 331 snd_soc_write(codec, WM8510_DAC, reg | div);
380 break; 332 break;
381 case WM8510_BCLKDIV: 333 case WM8510_BCLKDIV:
382 reg = wm8510_read_reg_cache(codec, WM8510_CLOCK) & 0x1e3; 334 reg = snd_soc_read(codec, WM8510_CLOCK) & 0x1e3;
383 wm8510_write(codec, WM8510_CLOCK, reg | div); 335 snd_soc_write(codec, WM8510_CLOCK, reg | div);
384 break; 336 break;
385 default: 337 default:
386 return -EINVAL; 338 return -EINVAL;
@@ -394,7 +346,7 @@ static int wm8510_set_dai_fmt(struct snd_soc_dai *codec_dai,
394{ 346{
395 struct snd_soc_codec *codec = codec_dai->codec; 347 struct snd_soc_codec *codec = codec_dai->codec;
396 u16 iface = 0; 348 u16 iface = 0;
397 u16 clk = wm8510_read_reg_cache(codec, WM8510_CLOCK) & 0x1fe; 349 u16 clk = snd_soc_read(codec, WM8510_CLOCK) & 0x1fe;
398 350
399 /* set master/slave audio interface */ 351 /* set master/slave audio interface */
400 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 352 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -441,8 +393,8 @@ static int wm8510_set_dai_fmt(struct snd_soc_dai *codec_dai,
441 return -EINVAL; 393 return -EINVAL;
442 } 394 }
443 395
444 wm8510_write(codec, WM8510_IFACE, iface); 396 snd_soc_write(codec, WM8510_IFACE, iface);
445 wm8510_write(codec, WM8510_CLOCK, clk); 397 snd_soc_write(codec, WM8510_CLOCK, clk);
446 return 0; 398 return 0;
447} 399}
448 400
@@ -453,8 +405,8 @@ static int wm8510_pcm_hw_params(struct snd_pcm_substream *substream,
453 struct snd_soc_pcm_runtime *rtd = substream->private_data; 405 struct snd_soc_pcm_runtime *rtd = substream->private_data;
454 struct snd_soc_device *socdev = rtd->socdev; 406 struct snd_soc_device *socdev = rtd->socdev;
455 struct snd_soc_codec *codec = socdev->card->codec; 407 struct snd_soc_codec *codec = socdev->card->codec;
456 u16 iface = wm8510_read_reg_cache(codec, WM8510_IFACE) & 0x19f; 408 u16 iface = snd_soc_read(codec, WM8510_IFACE) & 0x19f;
457 u16 adn = wm8510_read_reg_cache(codec, WM8510_ADD) & 0x1f1; 409 u16 adn = snd_soc_read(codec, WM8510_ADD) & 0x1f1;
458 410
459 /* bit size */ 411 /* bit size */
460 switch (params_format(params)) { 412 switch (params_format(params)) {
@@ -493,20 +445,20 @@ static int wm8510_pcm_hw_params(struct snd_pcm_substream *substream,
493 break; 445 break;
494 } 446 }
495 447
496 wm8510_write(codec, WM8510_IFACE, iface); 448 snd_soc_write(codec, WM8510_IFACE, iface);
497 wm8510_write(codec, WM8510_ADD, adn); 449 snd_soc_write(codec, WM8510_ADD, adn);
498 return 0; 450 return 0;
499} 451}
500 452
501static int wm8510_mute(struct snd_soc_dai *dai, int mute) 453static int wm8510_mute(struct snd_soc_dai *dai, int mute)
502{ 454{
503 struct snd_soc_codec *codec = dai->codec; 455 struct snd_soc_codec *codec = dai->codec;
504 u16 mute_reg = wm8510_read_reg_cache(codec, WM8510_DAC) & 0xffbf; 456 u16 mute_reg = snd_soc_read(codec, WM8510_DAC) & 0xffbf;
505 457
506 if (mute) 458 if (mute)
507 wm8510_write(codec, WM8510_DAC, mute_reg | 0x40); 459 snd_soc_write(codec, WM8510_DAC, mute_reg | 0x40);
508 else 460 else
509 wm8510_write(codec, WM8510_DAC, mute_reg); 461 snd_soc_write(codec, WM8510_DAC, mute_reg);
510 return 0; 462 return 0;
511} 463}
512 464
@@ -514,13 +466,13 @@ static int wm8510_mute(struct snd_soc_dai *dai, int mute)
514static int wm8510_set_bias_level(struct snd_soc_codec *codec, 466static int wm8510_set_bias_level(struct snd_soc_codec *codec,
515 enum snd_soc_bias_level level) 467 enum snd_soc_bias_level level)
516{ 468{
517 u16 power1 = wm8510_read_reg_cache(codec, WM8510_POWER1) & ~0x3; 469 u16 power1 = snd_soc_read(codec, WM8510_POWER1) & ~0x3;
518 470
519 switch (level) { 471 switch (level) {
520 case SND_SOC_BIAS_ON: 472 case SND_SOC_BIAS_ON:
521 case SND_SOC_BIAS_PREPARE: 473 case SND_SOC_BIAS_PREPARE:
522 power1 |= 0x1; /* VMID 50k */ 474 power1 |= 0x1; /* VMID 50k */
523 wm8510_write(codec, WM8510_POWER1, power1); 475 snd_soc_write(codec, WM8510_POWER1, power1);
524 break; 476 break;
525 477
526 case SND_SOC_BIAS_STANDBY: 478 case SND_SOC_BIAS_STANDBY:
@@ -528,18 +480,18 @@ static int wm8510_set_bias_level(struct snd_soc_codec *codec,
528 480
529 if (codec->bias_level == SND_SOC_BIAS_OFF) { 481 if (codec->bias_level == SND_SOC_BIAS_OFF) {
530 /* Initial cap charge at VMID 5k */ 482 /* Initial cap charge at VMID 5k */
531 wm8510_write(codec, WM8510_POWER1, power1 | 0x3); 483 snd_soc_write(codec, WM8510_POWER1, power1 | 0x3);
532 mdelay(100); 484 mdelay(100);
533 } 485 }
534 486
535 power1 |= 0x2; /* VMID 500k */ 487 power1 |= 0x2; /* VMID 500k */
536 wm8510_write(codec, WM8510_POWER1, power1); 488 snd_soc_write(codec, WM8510_POWER1, power1);
537 break; 489 break;
538 490
539 case SND_SOC_BIAS_OFF: 491 case SND_SOC_BIAS_OFF:
540 wm8510_write(codec, WM8510_POWER1, 0); 492 snd_soc_write(codec, WM8510_POWER1, 0);
541 wm8510_write(codec, WM8510_POWER2, 0); 493 snd_soc_write(codec, WM8510_POWER2, 0);
542 wm8510_write(codec, WM8510_POWER3, 0); 494 snd_soc_write(codec, WM8510_POWER3, 0);
543 break; 495 break;
544 } 496 }
545 497
@@ -613,15 +565,14 @@ static int wm8510_resume(struct platform_device *pdev)
613 * initialise the WM8510 driver 565 * initialise the WM8510 driver
614 * register the mixer and dsp interfaces with the kernel 566 * register the mixer and dsp interfaces with the kernel
615 */ 567 */
616static int wm8510_init(struct snd_soc_device *socdev) 568static int wm8510_init(struct snd_soc_device *socdev,
569 enum snd_soc_control_type control)
617{ 570{
618 struct snd_soc_codec *codec = socdev->card->codec; 571 struct snd_soc_codec *codec = socdev->card->codec;
619 int ret = 0; 572 int ret = 0;
620 573
621 codec->name = "WM8510"; 574 codec->name = "WM8510";
622 codec->owner = THIS_MODULE; 575 codec->owner = THIS_MODULE;
623 codec->read = wm8510_read_reg_cache;
624 codec->write = wm8510_write;
625 codec->set_bias_level = wm8510_set_bias_level; 576 codec->set_bias_level = wm8510_set_bias_level;
626 codec->dai = &wm8510_dai; 577 codec->dai = &wm8510_dai;
627 codec->num_dai = 1; 578 codec->num_dai = 1;
@@ -631,13 +582,20 @@ static int wm8510_init(struct snd_soc_device *socdev)
631 if (codec->reg_cache == NULL) 582 if (codec->reg_cache == NULL)
632 return -ENOMEM; 583 return -ENOMEM;
633 584
585 ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
586 if (ret < 0) {
587 printk(KERN_ERR "wm8510: failed to set cache I/O: %d\n",
588 ret);
589 goto err;
590 }
591
634 wm8510_reset(codec); 592 wm8510_reset(codec);
635 593
636 /* register pcms */ 594 /* register pcms */
637 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 595 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
638 if (ret < 0) { 596 if (ret < 0) {
639 printk(KERN_ERR "wm8510: failed to create pcms\n"); 597 printk(KERN_ERR "wm8510: failed to create pcms\n");
640 goto pcm_err; 598 goto err;
641 } 599 }
642 600
643 /* power on device */ 601 /* power on device */
@@ -656,7 +614,7 @@ static int wm8510_init(struct snd_soc_device *socdev)
656card_err: 614card_err:
657 snd_soc_free_pcms(socdev); 615 snd_soc_free_pcms(socdev);
658 snd_soc_dapm_free(socdev); 616 snd_soc_dapm_free(socdev);
659pcm_err: 617err:
660 kfree(codec->reg_cache); 618 kfree(codec->reg_cache);
661 return ret; 619 return ret;
662} 620}
@@ -679,7 +637,7 @@ static int wm8510_i2c_probe(struct i2c_client *i2c,
679 i2c_set_clientdata(i2c, codec); 637 i2c_set_clientdata(i2c, codec);
680 codec->control_data = i2c; 638 codec->control_data = i2c;
681 639
682 ret = wm8510_init(socdev); 640 ret = wm8510_init(socdev, SND_SOC_I2C);
683 if (ret < 0) 641 if (ret < 0)
684 pr_err("failed to initialise WM8510\n"); 642 pr_err("failed to initialise WM8510\n");
685 643
@@ -759,7 +717,7 @@ static int __devinit wm8510_spi_probe(struct spi_device *spi)
759 717
760 codec->control_data = spi; 718 codec->control_data = spi;
761 719
762 ret = wm8510_init(socdev); 720 ret = wm8510_init(socdev, SND_SOC_SPI);
763 if (ret < 0) 721 if (ret < 0)
764 dev_err(&spi->dev, "failed to initialise WM8510\n"); 722 dev_err(&spi->dev, "failed to initialise WM8510\n");
765 723
@@ -780,30 +738,6 @@ static struct spi_driver wm8510_spi_driver = {
780 .probe = wm8510_spi_probe, 738 .probe = wm8510_spi_probe,
781 .remove = __devexit_p(wm8510_spi_remove), 739 .remove = __devexit_p(wm8510_spi_remove),
782}; 740};
783
784static int wm8510_spi_write(struct spi_device *spi, const char *data, int len)
785{
786 struct spi_transfer t;
787 struct spi_message m;
788 u8 msg[2];
789
790 if (len <= 0)
791 return 0;
792
793 msg[0] = data[0];
794 msg[1] = data[1];
795
796 spi_message_init(&m);
797 memset(&t, 0, (sizeof t));
798
799 t.tx_buf = &msg[0];
800 t.len = len;
801
802 spi_message_add_tail(&t, &m);
803 spi_sync(spi, &m);
804
805 return len;
806}
807#endif /* CONFIG_SPI_MASTER */ 741#endif /* CONFIG_SPI_MASTER */
808 742
809static int wm8510_probe(struct platform_device *pdev) 743static int wm8510_probe(struct platform_device *pdev)
@@ -828,13 +762,11 @@ static int wm8510_probe(struct platform_device *pdev)
828 wm8510_socdev = socdev; 762 wm8510_socdev = socdev;
829#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 763#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
830 if (setup->i2c_address) { 764 if (setup->i2c_address) {
831 codec->hw_write = (hw_write_t)i2c_master_send;
832 ret = wm8510_add_i2c_device(pdev, setup); 765 ret = wm8510_add_i2c_device(pdev, setup);
833 } 766 }
834#endif 767#endif
835#if defined(CONFIG_SPI_MASTER) 768#if defined(CONFIG_SPI_MASTER)
836 if (setup->spi) { 769 if (setup->spi) {
837 codec->hw_write = (hw_write_t)wm8510_spi_write;
838 ret = spi_register_driver(&wm8510_spi_driver); 770 ret = spi_register_driver(&wm8510_spi_driver);
839 if (ret != 0) 771 if (ret != 0)
840 printk(KERN_ERR "can't add spi driver"); 772 printk(KERN_ERR "can't add spi driver");
diff --git a/sound/soc/codecs/wm8523.c b/sound/soc/codecs/wm8523.c
index 3b499ae7ce6c..25870a4652fb 100644
--- a/sound/soc/codecs/wm8523.c
+++ b/sound/soc/codecs/wm8523.c
@@ -62,7 +62,7 @@ static const u16 wm8523_reg[WM8523_REGISTER_COUNT] = {
62 0x0000, /* R8 - ZERO_DETECT */ 62 0x0000, /* R8 - ZERO_DETECT */
63}; 63};
64 64
65static int wm8523_volatile(unsigned int reg) 65static int wm8523_volatile_register(unsigned int reg)
66{ 66{
67 switch (reg) { 67 switch (reg) {
68 case WM8523_DEVICE_ID: 68 case WM8523_DEVICE_ID:
@@ -73,71 +73,9 @@ static int wm8523_volatile(unsigned int reg)
73 } 73 }
74} 74}
75 75
76static int wm8523_write(struct snd_soc_codec *codec, unsigned int reg,
77 unsigned int value)
78{
79 struct wm8523_priv *wm8523 = codec->private_data;
80 u8 data[3];
81
82 BUG_ON(reg > WM8523_MAX_REGISTER);
83
84 data[0] = reg;
85 data[1] = (value >> 8) & 0x00ff;
86 data[2] = value & 0x00ff;
87
88 if (!wm8523_volatile(reg))
89 wm8523->reg_cache[reg] = value;
90 if (codec->hw_write(codec->control_data, data, 3) == 3)
91 return 0;
92 else
93 return -EIO;
94}
95
96static int wm8523_reset(struct snd_soc_codec *codec) 76static int wm8523_reset(struct snd_soc_codec *codec)
97{ 77{
98 return wm8523_write(codec, WM8523_DEVICE_ID, 0); 78 return snd_soc_write(codec, WM8523_DEVICE_ID, 0);
99}
100
101static unsigned int wm8523_read_hw(struct snd_soc_codec *codec, u8 reg)
102{
103 struct i2c_msg xfer[2];
104 u16 data;
105 int ret;
106 struct i2c_client *i2c = codec->control_data;
107
108 /* Write register */
109 xfer[0].addr = i2c->addr;
110 xfer[0].flags = 0;
111 xfer[0].len = 1;
112 xfer[0].buf = &reg;
113
114 /* Read data */
115 xfer[1].addr = i2c->addr;
116 xfer[1].flags = I2C_M_RD;
117 xfer[1].len = 2;
118 xfer[1].buf = (u8 *)&data;
119
120 ret = i2c_transfer(i2c->adapter, xfer, 2);
121 if (ret != 2) {
122 dev_err(codec->dev, "Failed to read 0x%x: %d\n", reg, ret);
123 return 0;
124 }
125
126 return (data >> 8) | ((data & 0xff) << 8);
127}
128
129
130static unsigned int wm8523_read(struct snd_soc_codec *codec,
131 unsigned int reg)
132{
133 u16 *reg_cache = codec->reg_cache;
134
135 BUG_ON(reg > WM8523_MAX_REGISTER);
136
137 if (wm8523_volatile(reg))
138 return wm8523_read_hw(codec, reg);
139 else
140 return reg_cache[reg];
141} 79}
142 80
143static const DECLARE_TLV_DB_SCALE(dac_tlv, -10000, 25, 0); 81static const DECLARE_TLV_DB_SCALE(dac_tlv, -10000, 25, 0);
@@ -228,8 +166,8 @@ static int wm8523_hw_params(struct snd_pcm_substream *substream,
228 struct snd_soc_codec *codec = socdev->card->codec; 166 struct snd_soc_codec *codec = socdev->card->codec;
229 struct wm8523_priv *wm8523 = codec->private_data; 167 struct wm8523_priv *wm8523 = codec->private_data;
230 int i; 168 int i;
231 u16 aifctrl1 = wm8523_read(codec, WM8523_AIF_CTRL1); 169 u16 aifctrl1 = snd_soc_read(codec, WM8523_AIF_CTRL1);
232 u16 aifctrl2 = wm8523_read(codec, WM8523_AIF_CTRL2); 170 u16 aifctrl2 = snd_soc_read(codec, WM8523_AIF_CTRL2);
233 171
234 /* Find a supported LRCLK ratio */ 172 /* Find a supported LRCLK ratio */
235 for (i = 0; i < ARRAY_SIZE(lrclk_ratios); i++) { 173 for (i = 0; i < ARRAY_SIZE(lrclk_ratios); i++) {
@@ -263,8 +201,8 @@ static int wm8523_hw_params(struct snd_pcm_substream *substream,
263 break; 201 break;
264 } 202 }
265 203
266 wm8523_write(codec, WM8523_AIF_CTRL1, aifctrl1); 204 snd_soc_write(codec, WM8523_AIF_CTRL1, aifctrl1);
267 wm8523_write(codec, WM8523_AIF_CTRL2, aifctrl2); 205 snd_soc_write(codec, WM8523_AIF_CTRL2, aifctrl2);
268 206
269 return 0; 207 return 0;
270} 208}
@@ -322,7 +260,7 @@ static int wm8523_set_dai_fmt(struct snd_soc_dai *codec_dai,
322 unsigned int fmt) 260 unsigned int fmt)
323{ 261{
324 struct snd_soc_codec *codec = codec_dai->codec; 262 struct snd_soc_codec *codec = codec_dai->codec;
325 u16 aifctrl1 = wm8523_read(codec, WM8523_AIF_CTRL1); 263 u16 aifctrl1 = snd_soc_read(codec, WM8523_AIF_CTRL1);
326 264
327 aifctrl1 &= ~(WM8523_BCLK_INV_MASK | WM8523_LRCLK_INV_MASK | 265 aifctrl1 &= ~(WM8523_BCLK_INV_MASK | WM8523_LRCLK_INV_MASK |
328 WM8523_FMT_MASK | WM8523_AIF_MSTR_MASK); 266 WM8523_FMT_MASK | WM8523_AIF_MSTR_MASK);
@@ -372,7 +310,7 @@ static int wm8523_set_dai_fmt(struct snd_soc_dai *codec_dai,
372 return -EINVAL; 310 return -EINVAL;
373 } 311 }
374 312
375 wm8523_write(codec, WM8523_AIF_CTRL1, aifctrl1); 313 snd_soc_write(codec, WM8523_AIF_CTRL1, aifctrl1);
376 314
377 return 0; 315 return 0;
378} 316}
@@ -411,7 +349,7 @@ static int wm8523_set_bias_level(struct snd_soc_codec *codec,
411 /* Sync back default/cached values */ 349 /* Sync back default/cached values */
412 for (i = WM8523_AIF_CTRL1; 350 for (i = WM8523_AIF_CTRL1;
413 i < WM8523_MAX_REGISTER; i++) 351 i < WM8523_MAX_REGISTER; i++)
414 wm8523_write(codec, i, wm8523->reg_cache[i]); 352 snd_soc_write(codec, i, wm8523->reg_cache[i]);
415 353
416 354
417 msleep(100); 355 msleep(100);
@@ -543,7 +481,8 @@ struct snd_soc_codec_device soc_codec_dev_wm8523 = {
543}; 481};
544EXPORT_SYMBOL_GPL(soc_codec_dev_wm8523); 482EXPORT_SYMBOL_GPL(soc_codec_dev_wm8523);
545 483
546static int wm8523_register(struct wm8523_priv *wm8523) 484static int wm8523_register(struct wm8523_priv *wm8523,
485 enum snd_soc_control_type control)
547{ 486{
548 int ret; 487 int ret;
549 struct snd_soc_codec *codec = &wm8523->codec; 488 struct snd_soc_codec *codec = &wm8523->codec;
@@ -561,14 +500,13 @@ static int wm8523_register(struct wm8523_priv *wm8523)
561 codec->private_data = wm8523; 500 codec->private_data = wm8523;
562 codec->name = "WM8523"; 501 codec->name = "WM8523";
563 codec->owner = THIS_MODULE; 502 codec->owner = THIS_MODULE;
564 codec->read = wm8523_read;
565 codec->write = wm8523_write;
566 codec->bias_level = SND_SOC_BIAS_OFF; 503 codec->bias_level = SND_SOC_BIAS_OFF;
567 codec->set_bias_level = wm8523_set_bias_level; 504 codec->set_bias_level = wm8523_set_bias_level;
568 codec->dai = &wm8523_dai; 505 codec->dai = &wm8523_dai;
569 codec->num_dai = 1; 506 codec->num_dai = 1;
570 codec->reg_cache_size = WM8523_REGISTER_COUNT; 507 codec->reg_cache_size = WM8523_REGISTER_COUNT;
571 codec->reg_cache = &wm8523->reg_cache; 508 codec->reg_cache = &wm8523->reg_cache;
509 codec->volatile_register = wm8523_volatile_register;
572 510
573 wm8523->rate_constraint.list = &wm8523->rate_constraint_list[0]; 511 wm8523->rate_constraint.list = &wm8523->rate_constraint_list[0];
574 wm8523->rate_constraint.count = 512 wm8523->rate_constraint.count =
@@ -576,6 +514,12 @@ static int wm8523_register(struct wm8523_priv *wm8523)
576 514
577 memcpy(codec->reg_cache, wm8523_reg, sizeof(wm8523_reg)); 515 memcpy(codec->reg_cache, wm8523_reg, sizeof(wm8523_reg));
578 516
517 ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
518 if (ret != 0) {
519 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
520 goto err;
521 }
522
579 for (i = 0; i < ARRAY_SIZE(wm8523->supplies); i++) 523 for (i = 0; i < ARRAY_SIZE(wm8523->supplies); i++)
580 wm8523->supplies[i].supply = wm8523_supply_names[i]; 524 wm8523->supplies[i].supply = wm8523_supply_names[i];
581 525
@@ -593,7 +537,7 @@ static int wm8523_register(struct wm8523_priv *wm8523)
593 goto err_get; 537 goto err_get;
594 } 538 }
595 539
596 ret = wm8523_read(codec, WM8523_DEVICE_ID); 540 ret = snd_soc_read(codec, WM8523_DEVICE_ID);
597 if (ret < 0) { 541 if (ret < 0) {
598 dev_err(codec->dev, "Failed to read ID register\n"); 542 dev_err(codec->dev, "Failed to read ID register\n");
599 goto err_enable; 543 goto err_enable;
@@ -604,7 +548,7 @@ static int wm8523_register(struct wm8523_priv *wm8523)
604 goto err_enable; 548 goto err_enable;
605 } 549 }
606 550
607 ret = wm8523_read(codec, WM8523_REVISION); 551 ret = snd_soc_read(codec, WM8523_REVISION);
608 if (ret < 0) { 552 if (ret < 0) {
609 dev_err(codec->dev, "Failed to read revision register\n"); 553 dev_err(codec->dev, "Failed to read revision register\n");
610 goto err_enable; 554 goto err_enable;
@@ -684,7 +628,7 @@ static __devinit int wm8523_i2c_probe(struct i2c_client *i2c,
684 628
685 codec->dev = &i2c->dev; 629 codec->dev = &i2c->dev;
686 630
687 return wm8523_register(wm8523); 631 return wm8523_register(wm8523, SND_SOC_I2C);
688} 632}
689 633
690static __devexit int wm8523_i2c_remove(struct i2c_client *client) 634static __devexit int wm8523_i2c_remove(struct i2c_client *client)
diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c
index 97b9ed95d289..d5473473a1e3 100644
--- a/sound/soc/codecs/wm8580.c
+++ b/sound/soc/codecs/wm8580.c
@@ -205,73 +205,6 @@ struct wm8580_priv {
205 struct pll_state b; 205 struct pll_state b;
206}; 206};
207 207
208/*
209 * read wm8580 register cache
210 */
211static inline unsigned int wm8580_read_reg_cache(struct snd_soc_codec *codec,
212 unsigned int reg)
213{
214 u16 *cache = codec->reg_cache;
215 BUG_ON(reg >= ARRAY_SIZE(wm8580_reg));
216 return cache[reg];
217}
218
219/*
220 * write wm8580 register cache
221 */
222static inline void wm8580_write_reg_cache(struct snd_soc_codec *codec,
223 unsigned int reg, unsigned int value)
224{
225 u16 *cache = codec->reg_cache;
226
227 cache[reg] = value;
228}
229
230/*
231 * write to the WM8580 register space
232 */
233static int wm8580_write(struct snd_soc_codec *codec, unsigned int reg,
234 unsigned int value)
235{
236 u8 data[2];
237
238 BUG_ON(reg >= ARRAY_SIZE(wm8580_reg));
239
240 /* Registers are 9 bits wide */
241 value &= 0x1ff;
242
243 switch (reg) {
244 case WM8580_RESET:
245 /* Uncached */
246 break;
247 default:
248 if (value == wm8580_read_reg_cache(codec, reg))
249 return 0;
250 }
251
252 /* data is
253 * D15..D9 WM8580 register offset
254 * D8...D0 register data
255 */
256 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
257 data[1] = value & 0x00ff;
258
259 wm8580_write_reg_cache(codec, reg, value);
260 if (codec->hw_write(codec->control_data, data, 2) == 2)
261 return 0;
262 else
263 return -EIO;
264}
265
266static inline unsigned int wm8580_read(struct snd_soc_codec *codec,
267 unsigned int reg)
268{
269 switch (reg) {
270 default:
271 return wm8580_read_reg_cache(codec, reg);
272 }
273}
274
275static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1); 208static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
276 209
277static int wm8580_out_vu(struct snd_kcontrol *kcontrol, 210static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
@@ -280,25 +213,22 @@ static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
280 struct soc_mixer_control *mc = 213 struct soc_mixer_control *mc =
281 (struct soc_mixer_control *)kcontrol->private_value; 214 (struct soc_mixer_control *)kcontrol->private_value;
282 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 215 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
216 u16 *reg_cache = codec->reg_cache;
283 unsigned int reg = mc->reg; 217 unsigned int reg = mc->reg;
284 unsigned int reg2 = mc->rreg; 218 unsigned int reg2 = mc->rreg;
285 int ret; 219 int ret;
286 u16 val;
287 220
288 /* Clear the register cache so we write without VU set */ 221 /* Clear the register cache so we write without VU set */
289 wm8580_write_reg_cache(codec, reg, 0); 222 reg_cache[reg] = 0;
290 wm8580_write_reg_cache(codec, reg2, 0); 223 reg_cache[reg2] = 0;
291 224
292 ret = snd_soc_put_volsw_2r(kcontrol, ucontrol); 225 ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
293 if (ret < 0) 226 if (ret < 0)
294 return ret; 227 return ret;
295 228
296 /* Now write again with the volume update bit set */ 229 /* Now write again with the volume update bit set */
297 val = wm8580_read_reg_cache(codec, reg); 230 snd_soc_update_bits(codec, reg, 0x100, 0x100);
298 wm8580_write(codec, reg, val | 0x0100); 231 snd_soc_update_bits(codec, reg2, 0x100, 0x100);
299
300 val = wm8580_read_reg_cache(codec, reg2);
301 wm8580_write(codec, reg2, val | 0x0100);
302 232
303 return 0; 233 return 0;
304} 234}
@@ -521,27 +451,27 @@ static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai,
521 /* Always disable the PLL - it is not safe to leave it running 451 /* Always disable the PLL - it is not safe to leave it running
522 * while reprogramming it. 452 * while reprogramming it.
523 */ 453 */
524 reg = wm8580_read(codec, WM8580_PWRDN2); 454 reg = snd_soc_read(codec, WM8580_PWRDN2);
525 wm8580_write(codec, WM8580_PWRDN2, reg | pwr_mask); 455 snd_soc_write(codec, WM8580_PWRDN2, reg | pwr_mask);
526 456
527 if (!freq_in || !freq_out) 457 if (!freq_in || !freq_out)
528 return 0; 458 return 0;
529 459
530 wm8580_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff); 460 snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
531 wm8580_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0xff); 461 snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0xff);
532 wm8580_write(codec, WM8580_PLLA3 + offset, 462 snd_soc_write(codec, WM8580_PLLA3 + offset,
533 (pll_div.k >> 18 & 0xf) | (pll_div.n << 4)); 463 (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
534 464
535 reg = wm8580_read(codec, WM8580_PLLA4 + offset); 465 reg = snd_soc_read(codec, WM8580_PLLA4 + offset);
536 reg &= ~0x3f; 466 reg &= ~0x3f;
537 reg |= pll_div.prescale | pll_div.postscale << 1 | 467 reg |= pll_div.prescale | pll_div.postscale << 1 |
538 pll_div.freqmode << 3; 468 pll_div.freqmode << 3;
539 469
540 wm8580_write(codec, WM8580_PLLA4 + offset, reg); 470 snd_soc_write(codec, WM8580_PLLA4 + offset, reg);
541 471
542 /* All done, turn it on */ 472 /* All done, turn it on */
543 reg = wm8580_read(codec, WM8580_PWRDN2); 473 reg = snd_soc_read(codec, WM8580_PWRDN2);
544 wm8580_write(codec, WM8580_PWRDN2, reg & ~pwr_mask); 474 snd_soc_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
545 475
546 return 0; 476 return 0;
547} 477}
@@ -556,7 +486,7 @@ static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
556 struct snd_soc_pcm_runtime *rtd = substream->private_data; 486 struct snd_soc_pcm_runtime *rtd = substream->private_data;
557 struct snd_soc_device *socdev = rtd->socdev; 487 struct snd_soc_device *socdev = rtd->socdev;
558 struct snd_soc_codec *codec = socdev->card->codec; 488 struct snd_soc_codec *codec = socdev->card->codec;
559 u16 paifb = wm8580_read(codec, WM8580_PAIF3 + dai->id); 489 u16 paifb = snd_soc_read(codec, WM8580_PAIF3 + dai->id);
560 490
561 paifb &= ~WM8580_AIF_LENGTH_MASK; 491 paifb &= ~WM8580_AIF_LENGTH_MASK;
562 /* bit size */ 492 /* bit size */
@@ -576,7 +506,7 @@ static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
576 return -EINVAL; 506 return -EINVAL;
577 } 507 }
578 508
579 wm8580_write(codec, WM8580_PAIF3 + dai->id, paifb); 509 snd_soc_write(codec, WM8580_PAIF3 + dai->id, paifb);
580 return 0; 510 return 0;
581} 511}
582 512
@@ -588,8 +518,8 @@ static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
588 unsigned int aifb; 518 unsigned int aifb;
589 int can_invert_lrclk; 519 int can_invert_lrclk;
590 520
591 aifa = wm8580_read(codec, WM8580_PAIF1 + codec_dai->id); 521 aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->id);
592 aifb = wm8580_read(codec, WM8580_PAIF3 + codec_dai->id); 522 aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->id);
593 523
594 aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP); 524 aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
595 525
@@ -655,8 +585,8 @@ static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
655 return -EINVAL; 585 return -EINVAL;
656 } 586 }
657 587
658 wm8580_write(codec, WM8580_PAIF1 + codec_dai->id, aifa); 588 snd_soc_write(codec, WM8580_PAIF1 + codec_dai->id, aifa);
659 wm8580_write(codec, WM8580_PAIF3 + codec_dai->id, aifb); 589 snd_soc_write(codec, WM8580_PAIF3 + codec_dai->id, aifb);
660 590
661 return 0; 591 return 0;
662} 592}
@@ -669,7 +599,7 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
669 599
670 switch (div_id) { 600 switch (div_id) {
671 case WM8580_MCLK: 601 case WM8580_MCLK:
672 reg = wm8580_read(codec, WM8580_PLLB4); 602 reg = snd_soc_read(codec, WM8580_PLLB4);
673 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK; 603 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
674 604
675 switch (div) { 605 switch (div) {
@@ -691,11 +621,11 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
691 default: 621 default:
692 return -EINVAL; 622 return -EINVAL;
693 } 623 }
694 wm8580_write(codec, WM8580_PLLB4, reg); 624 snd_soc_write(codec, WM8580_PLLB4, reg);
695 break; 625 break;
696 626
697 case WM8580_DAC_CLKSEL: 627 case WM8580_DAC_CLKSEL:
698 reg = wm8580_read(codec, WM8580_CLKSEL); 628 reg = snd_soc_read(codec, WM8580_CLKSEL);
699 reg &= ~WM8580_CLKSEL_DAC_CLKSEL_MASK; 629 reg &= ~WM8580_CLKSEL_DAC_CLKSEL_MASK;
700 630
701 switch (div) { 631 switch (div) {
@@ -713,11 +643,11 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
713 default: 643 default:
714 return -EINVAL; 644 return -EINVAL;
715 } 645 }
716 wm8580_write(codec, WM8580_CLKSEL, reg); 646 snd_soc_write(codec, WM8580_CLKSEL, reg);
717 break; 647 break;
718 648
719 case WM8580_CLKOUTSRC: 649 case WM8580_CLKOUTSRC:
720 reg = wm8580_read(codec, WM8580_PLLB4); 650 reg = snd_soc_read(codec, WM8580_PLLB4);
721 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK; 651 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
722 652
723 switch (div) { 653 switch (div) {
@@ -739,7 +669,7 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
739 default: 669 default:
740 return -EINVAL; 670 return -EINVAL;
741 } 671 }
742 wm8580_write(codec, WM8580_PLLB4, reg); 672 snd_soc_write(codec, WM8580_PLLB4, reg);
743 break; 673 break;
744 674
745 default: 675 default:
@@ -754,14 +684,14 @@ static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
754 struct snd_soc_codec *codec = codec_dai->codec; 684 struct snd_soc_codec *codec = codec_dai->codec;
755 unsigned int reg; 685 unsigned int reg;
756 686
757 reg = wm8580_read(codec, WM8580_DAC_CONTROL5); 687 reg = snd_soc_read(codec, WM8580_DAC_CONTROL5);
758 688
759 if (mute) 689 if (mute)
760 reg |= WM8580_DAC_CONTROL5_MUTEALL; 690 reg |= WM8580_DAC_CONTROL5_MUTEALL;
761 else 691 else
762 reg &= ~WM8580_DAC_CONTROL5_MUTEALL; 692 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
763 693
764 wm8580_write(codec, WM8580_DAC_CONTROL5, reg); 694 snd_soc_write(codec, WM8580_DAC_CONTROL5, reg);
765 695
766 return 0; 696 return 0;
767} 697}
@@ -778,20 +708,20 @@ static int wm8580_set_bias_level(struct snd_soc_codec *codec,
778 case SND_SOC_BIAS_STANDBY: 708 case SND_SOC_BIAS_STANDBY:
779 if (codec->bias_level == SND_SOC_BIAS_OFF) { 709 if (codec->bias_level == SND_SOC_BIAS_OFF) {
780 /* Power up and get individual control of the DACs */ 710 /* Power up and get individual control of the DACs */
781 reg = wm8580_read(codec, WM8580_PWRDN1); 711 reg = snd_soc_read(codec, WM8580_PWRDN1);
782 reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD); 712 reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD);
783 wm8580_write(codec, WM8580_PWRDN1, reg); 713 snd_soc_write(codec, WM8580_PWRDN1, reg);
784 714
785 /* Make VMID high impedence */ 715 /* Make VMID high impedence */
786 reg = wm8580_read(codec, WM8580_ADC_CONTROL1); 716 reg = snd_soc_read(codec, WM8580_ADC_CONTROL1);
787 reg &= ~0x100; 717 reg &= ~0x100;
788 wm8580_write(codec, WM8580_ADC_CONTROL1, reg); 718 snd_soc_write(codec, WM8580_ADC_CONTROL1, reg);
789 } 719 }
790 break; 720 break;
791 721
792 case SND_SOC_BIAS_OFF: 722 case SND_SOC_BIAS_OFF:
793 reg = wm8580_read(codec, WM8580_PWRDN1); 723 reg = snd_soc_read(codec, WM8580_PWRDN1);
794 wm8580_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN); 724 snd_soc_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
795 break; 725 break;
796 } 726 }
797 codec->bias_level = level; 727 codec->bias_level = level;
@@ -902,7 +832,8 @@ struct snd_soc_codec_device soc_codec_dev_wm8580 = {
902}; 832};
903EXPORT_SYMBOL_GPL(soc_codec_dev_wm8580); 833EXPORT_SYMBOL_GPL(soc_codec_dev_wm8580);
904 834
905static int wm8580_register(struct wm8580_priv *wm8580) 835static int wm8580_register(struct wm8580_priv *wm8580,
836 enum snd_soc_control_type control)
906{ 837{
907 int ret, i; 838 int ret, i;
908 struct snd_soc_codec *codec = &wm8580->codec; 839 struct snd_soc_codec *codec = &wm8580->codec;
@@ -920,8 +851,6 @@ static int wm8580_register(struct wm8580_priv *wm8580)
920 codec->private_data = wm8580; 851 codec->private_data = wm8580;
921 codec->name = "WM8580"; 852 codec->name = "WM8580";
922 codec->owner = THIS_MODULE; 853 codec->owner = THIS_MODULE;
923 codec->read = wm8580_read_reg_cache;
924 codec->write = wm8580_write;
925 codec->bias_level = SND_SOC_BIAS_OFF; 854 codec->bias_level = SND_SOC_BIAS_OFF;
926 codec->set_bias_level = wm8580_set_bias_level; 855 codec->set_bias_level = wm8580_set_bias_level;
927 codec->dai = wm8580_dai; 856 codec->dai = wm8580_dai;
@@ -931,6 +860,12 @@ static int wm8580_register(struct wm8580_priv *wm8580)
931 860
932 memcpy(codec->reg_cache, wm8580_reg, sizeof(wm8580_reg)); 861 memcpy(codec->reg_cache, wm8580_reg, sizeof(wm8580_reg));
933 862
863 ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
864 if (ret < 0) {
865 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
866 goto err;
867 }
868
934 for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++) 869 for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
935 wm8580->supplies[i].supply = wm8580_supply_names[i]; 870 wm8580->supplies[i].supply = wm8580_supply_names[i];
936 871
@@ -949,7 +884,7 @@ static int wm8580_register(struct wm8580_priv *wm8580)
949 } 884 }
950 885
951 /* Get the codec into a known state */ 886 /* Get the codec into a known state */
952 ret = wm8580_write(codec, WM8580_RESET, 0); 887 ret = snd_soc_write(codec, WM8580_RESET, 0);
953 if (ret != 0) { 888 if (ret != 0) {
954 dev_err(codec->dev, "Failed to reset codec: %d\n", ret); 889 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
955 goto err_regulator_enable; 890 goto err_regulator_enable;
@@ -1010,14 +945,13 @@ static int wm8580_i2c_probe(struct i2c_client *i2c,
1010 return -ENOMEM; 945 return -ENOMEM;
1011 946
1012 codec = &wm8580->codec; 947 codec = &wm8580->codec;
1013 codec->hw_write = (hw_write_t)i2c_master_send;
1014 948
1015 i2c_set_clientdata(i2c, wm8580); 949 i2c_set_clientdata(i2c, wm8580);
1016 codec->control_data = i2c; 950 codec->control_data = i2c;
1017 951
1018 codec->dev = &i2c->dev; 952 codec->dev = &i2c->dev;
1019 953
1020 return wm8580_register(wm8580); 954 return wm8580_register(wm8580, SND_SOC_I2C);
1021} 955}
1022 956
1023static int wm8580_i2c_remove(struct i2c_client *client) 957static int wm8580_i2c_remove(struct i2c_client *client)
diff --git a/sound/soc/codecs/wm8728.c b/sound/soc/codecs/wm8728.c
index e7ff2121ede9..16e969a762c3 100644
--- a/sound/soc/codecs/wm8728.c
+++ b/sound/soc/codecs/wm8728.c
@@ -43,45 +43,6 @@ static const u16 wm8728_reg_defaults[] = {
43 0x100, 43 0x100,
44}; 44};
45 45
46static inline unsigned int wm8728_read_reg_cache(struct snd_soc_codec *codec,
47 unsigned int reg)
48{
49 u16 *cache = codec->reg_cache;
50 BUG_ON(reg >= ARRAY_SIZE(wm8728_reg_defaults));
51 return cache[reg];
52}
53
54static inline void wm8728_write_reg_cache(struct snd_soc_codec *codec,
55 u16 reg, unsigned int value)
56{
57 u16 *cache = codec->reg_cache;
58 BUG_ON(reg >= ARRAY_SIZE(wm8728_reg_defaults));
59 cache[reg] = value;
60}
61
62/*
63 * write to the WM8728 register space
64 */
65static int wm8728_write(struct snd_soc_codec *codec, unsigned int reg,
66 unsigned int value)
67{
68 u8 data[2];
69
70 /* data is
71 * D15..D9 WM8728 register offset
72 * D8...D0 register data
73 */
74 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
75 data[1] = value & 0x00ff;
76
77 wm8728_write_reg_cache(codec, reg, value);
78
79 if (codec->hw_write(codec->control_data, data, 2) == 2)
80 return 0;
81 else
82 return -EIO;
83}
84
85static const DECLARE_TLV_DB_SCALE(wm8728_tlv, -12750, 50, 1); 46static const DECLARE_TLV_DB_SCALE(wm8728_tlv, -12750, 50, 1);
86 47
87static const struct snd_kcontrol_new wm8728_snd_controls[] = { 48static const struct snd_kcontrol_new wm8728_snd_controls[] = {
@@ -121,12 +82,12 @@ static int wm8728_add_widgets(struct snd_soc_codec *codec)
121static int wm8728_mute(struct snd_soc_dai *dai, int mute) 82static int wm8728_mute(struct snd_soc_dai *dai, int mute)
122{ 83{
123 struct snd_soc_codec *codec = dai->codec; 84 struct snd_soc_codec *codec = dai->codec;
124 u16 mute_reg = wm8728_read_reg_cache(codec, WM8728_DACCTL); 85 u16 mute_reg = snd_soc_read(codec, WM8728_DACCTL);
125 86
126 if (mute) 87 if (mute)
127 wm8728_write(codec, WM8728_DACCTL, mute_reg | 1); 88 snd_soc_write(codec, WM8728_DACCTL, mute_reg | 1);
128 else 89 else
129 wm8728_write(codec, WM8728_DACCTL, mute_reg & ~1); 90 snd_soc_write(codec, WM8728_DACCTL, mute_reg & ~1);
130 91
131 return 0; 92 return 0;
132} 93}
@@ -138,7 +99,7 @@ static int wm8728_hw_params(struct snd_pcm_substream *substream,
138 struct snd_soc_pcm_runtime *rtd = substream->private_data; 99 struct snd_soc_pcm_runtime *rtd = substream->private_data;
139 struct snd_soc_device *socdev = rtd->socdev; 100 struct snd_soc_device *socdev = rtd->socdev;
140 struct snd_soc_codec *codec = socdev->card->codec; 101 struct snd_soc_codec *codec = socdev->card->codec;
141 u16 dac = wm8728_read_reg_cache(codec, WM8728_DACCTL); 102 u16 dac = snd_soc_read(codec, WM8728_DACCTL);
142 103
143 dac &= ~0x18; 104 dac &= ~0x18;
144 105
@@ -155,7 +116,7 @@ static int wm8728_hw_params(struct snd_pcm_substream *substream,
155 return -EINVAL; 116 return -EINVAL;
156 } 117 }
157 118
158 wm8728_write(codec, WM8728_DACCTL, dac); 119 snd_soc_write(codec, WM8728_DACCTL, dac);
159 120
160 return 0; 121 return 0;
161} 122}
@@ -164,7 +125,7 @@ static int wm8728_set_dai_fmt(struct snd_soc_dai *codec_dai,
164 unsigned int fmt) 125 unsigned int fmt)
165{ 126{
166 struct snd_soc_codec *codec = codec_dai->codec; 127 struct snd_soc_codec *codec = codec_dai->codec;
167 u16 iface = wm8728_read_reg_cache(codec, WM8728_IFCTL); 128 u16 iface = snd_soc_read(codec, WM8728_IFCTL);
168 129
169 /* Currently only I2S is supported by the driver, though the 130 /* Currently only I2S is supported by the driver, though the
170 * hardware is more flexible. 131 * hardware is more flexible.
@@ -204,7 +165,7 @@ static int wm8728_set_dai_fmt(struct snd_soc_dai *codec_dai,
204 return -EINVAL; 165 return -EINVAL;
205 } 166 }
206 167
207 wm8728_write(codec, WM8728_IFCTL, iface); 168 snd_soc_write(codec, WM8728_IFCTL, iface);
208 return 0; 169 return 0;
209} 170}
210 171
@@ -220,19 +181,19 @@ static int wm8728_set_bias_level(struct snd_soc_codec *codec,
220 case SND_SOC_BIAS_STANDBY: 181 case SND_SOC_BIAS_STANDBY:
221 if (codec->bias_level == SND_SOC_BIAS_OFF) { 182 if (codec->bias_level == SND_SOC_BIAS_OFF) {
222 /* Power everything up... */ 183 /* Power everything up... */
223 reg = wm8728_read_reg_cache(codec, WM8728_DACCTL); 184 reg = snd_soc_read(codec, WM8728_DACCTL);
224 wm8728_write(codec, WM8728_DACCTL, reg & ~0x4); 185 snd_soc_write(codec, WM8728_DACCTL, reg & ~0x4);
225 186
226 /* ..then sync in the register cache. */ 187 /* ..then sync in the register cache. */
227 for (i = 0; i < ARRAY_SIZE(wm8728_reg_defaults); i++) 188 for (i = 0; i < ARRAY_SIZE(wm8728_reg_defaults); i++)
228 wm8728_write(codec, i, 189 snd_soc_write(codec, i,
229 wm8728_read_reg_cache(codec, i)); 190 snd_soc_read(codec, i));
230 } 191 }
231 break; 192 break;
232 193
233 case SND_SOC_BIAS_OFF: 194 case SND_SOC_BIAS_OFF:
234 reg = wm8728_read_reg_cache(codec, WM8728_DACCTL); 195 reg = snd_soc_read(codec, WM8728_DACCTL);
235 wm8728_write(codec, WM8728_DACCTL, reg | 0x4); 196 snd_soc_write(codec, WM8728_DACCTL, reg | 0x4);
236 break; 197 break;
237 } 198 }
238 codec->bias_level = level; 199 codec->bias_level = level;
@@ -287,15 +248,14 @@ static int wm8728_resume(struct platform_device *pdev)
287 * initialise the WM8728 driver 248 * initialise the WM8728 driver
288 * register the mixer and dsp interfaces with the kernel 249 * register the mixer and dsp interfaces with the kernel
289 */ 250 */
290static int wm8728_init(struct snd_soc_device *socdev) 251static int wm8728_init(struct snd_soc_device *socdev,
252 enum snd_soc_control_type control)
291{ 253{
292 struct snd_soc_codec *codec = socdev->card->codec; 254 struct snd_soc_codec *codec = socdev->card->codec;
293 int ret = 0; 255 int ret = 0;
294 256
295 codec->name = "WM8728"; 257 codec->name = "WM8728";
296 codec->owner = THIS_MODULE; 258 codec->owner = THIS_MODULE;
297 codec->read = wm8728_read_reg_cache;
298 codec->write = wm8728_write;
299 codec->set_bias_level = wm8728_set_bias_level; 259 codec->set_bias_level = wm8728_set_bias_level;
300 codec->dai = &wm8728_dai; 260 codec->dai = &wm8728_dai;
301 codec->num_dai = 1; 261 codec->num_dai = 1;
@@ -307,11 +267,18 @@ static int wm8728_init(struct snd_soc_device *socdev)
307 if (codec->reg_cache == NULL) 267 if (codec->reg_cache == NULL)
308 return -ENOMEM; 268 return -ENOMEM;
309 269
270 ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
271 if (ret < 0) {
272 printk(KERN_ERR "wm8728: failed to configure cache I/O: %d\n",
273 ret);
274 goto err;
275 }
276
310 /* register pcms */ 277 /* register pcms */
311 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 278 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
312 if (ret < 0) { 279 if (ret < 0) {
313 printk(KERN_ERR "wm8728: failed to create pcms\n"); 280 printk(KERN_ERR "wm8728: failed to create pcms\n");
314 goto pcm_err; 281 goto err;
315 } 282 }
316 283
317 /* power on device */ 284 /* power on device */
@@ -331,7 +298,7 @@ static int wm8728_init(struct snd_soc_device *socdev)
331card_err: 298card_err:
332 snd_soc_free_pcms(socdev); 299 snd_soc_free_pcms(socdev);
333 snd_soc_dapm_free(socdev); 300 snd_soc_dapm_free(socdev);
334pcm_err: 301err:
335 kfree(codec->reg_cache); 302 kfree(codec->reg_cache);
336 return ret; 303 return ret;
337} 304}
@@ -357,7 +324,7 @@ static int wm8728_i2c_probe(struct i2c_client *i2c,
357 i2c_set_clientdata(i2c, codec); 324 i2c_set_clientdata(i2c, codec);
358 codec->control_data = i2c; 325 codec->control_data = i2c;
359 326
360 ret = wm8728_init(socdev); 327 ret = wm8728_init(socdev, SND_SOC_I2C);
361 if (ret < 0) 328 if (ret < 0)
362 pr_err("failed to initialise WM8728\n"); 329 pr_err("failed to initialise WM8728\n");
363 330
@@ -437,7 +404,7 @@ static int __devinit wm8728_spi_probe(struct spi_device *spi)
437 404
438 codec->control_data = spi; 405 codec->control_data = spi;
439 406
440 ret = wm8728_init(socdev); 407 ret = wm8728_init(socdev, SND_SOC_SPI);
441 if (ret < 0) 408 if (ret < 0)
442 dev_err(&spi->dev, "failed to initialise WM8728\n"); 409 dev_err(&spi->dev, "failed to initialise WM8728\n");
443 410
@@ -458,30 +425,6 @@ static struct spi_driver wm8728_spi_driver = {
458 .probe = wm8728_spi_probe, 425 .probe = wm8728_spi_probe,
459 .remove = __devexit_p(wm8728_spi_remove), 426 .remove = __devexit_p(wm8728_spi_remove),
460}; 427};
461
462static int wm8728_spi_write(struct spi_device *spi, const char *data, int len)
463{
464 struct spi_transfer t;
465 struct spi_message m;
466 u8 msg[2];
467
468 if (len <= 0)
469 return 0;
470
471 msg[0] = data[0];
472 msg[1] = data[1];
473
474 spi_message_init(&m);
475 memset(&t, 0, (sizeof t));
476
477 t.tx_buf = &msg[0];
478 t.len = len;
479
480 spi_message_add_tail(&t, &m);
481 spi_sync(spi, &m);
482
483 return len;
484}
485#endif /* CONFIG_SPI_MASTER */ 428#endif /* CONFIG_SPI_MASTER */
486 429
487static int wm8728_probe(struct platform_device *pdev) 430static int wm8728_probe(struct platform_device *pdev)
@@ -506,13 +449,11 @@ static int wm8728_probe(struct platform_device *pdev)
506 449
507#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 450#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
508 if (setup->i2c_address) { 451 if (setup->i2c_address) {
509 codec->hw_write = (hw_write_t)i2c_master_send;
510 ret = wm8728_add_i2c_device(pdev, setup); 452 ret = wm8728_add_i2c_device(pdev, setup);
511 } 453 }
512#endif 454#endif
513#if defined(CONFIG_SPI_MASTER) 455#if defined(CONFIG_SPI_MASTER)
514 if (setup->spi) { 456 if (setup->spi) {
515 codec->hw_write = (hw_write_t)wm8728_spi_write;
516 ret = spi_register_driver(&wm8728_spi_driver); 457 ret = spi_register_driver(&wm8728_spi_driver);
517 if (ret != 0) 458 if (ret != 0)
518 printk(KERN_ERR "can't add spi driver"); 459 printk(KERN_ERR "can't add spi driver");
diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c
index 156002852078..2b980ccb6032 100644
--- a/sound/soc/codecs/wm8731.c
+++ b/sound/soc/codecs/wm8731.c
@@ -51,60 +51,12 @@ static int wm8731_spi_write(struct spi_device *spi, const char *data, int len);
51 * There is no point in caching the reset register 51 * There is no point in caching the reset register
52 */ 52 */
53static const u16 wm8731_reg[WM8731_CACHEREGNUM] = { 53static const u16 wm8731_reg[WM8731_CACHEREGNUM] = {
54 0x0097, 0x0097, 0x0079, 0x0079, 54 0x0097, 0x0097, 0x0079, 0x0079,
55 0x000a, 0x0008, 0x009f, 0x000a, 55 0x000a, 0x0008, 0x009f, 0x000a,
56 0x0000, 0x0000 56 0x0000, 0x0000
57}; 57};
58 58
59/* 59#define wm8731_reset(c) snd_soc_write(c, WM8731_RESET, 0)
60 * read wm8731 register cache
61 */
62static inline unsigned int wm8731_read_reg_cache(struct snd_soc_codec *codec,
63 unsigned int reg)
64{
65 u16 *cache = codec->reg_cache;
66 if (reg == WM8731_RESET)
67 return 0;
68 if (reg >= WM8731_CACHEREGNUM)
69 return -1;
70 return cache[reg];
71}
72
73/*
74 * write wm8731 register cache
75 */
76static inline void wm8731_write_reg_cache(struct snd_soc_codec *codec,
77 u16 reg, unsigned int value)
78{
79 u16 *cache = codec->reg_cache;
80 if (reg >= WM8731_CACHEREGNUM)
81 return;
82 cache[reg] = value;
83}
84
85/*
86 * write to the WM8731 register space
87 */
88static int wm8731_write(struct snd_soc_codec *codec, unsigned int reg,
89 unsigned int value)
90{
91 u8 data[2];
92
93 /* data is
94 * D15..D9 WM8731 register offset
95 * D8...D0 register data
96 */
97 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
98 data[1] = value & 0x00ff;
99
100 wm8731_write_reg_cache(codec, reg, value);
101 if (codec->hw_write(codec->control_data, data, 2) == 2)
102 return 0;
103 else
104 return -EIO;
105}
106
107#define wm8731_reset(c) wm8731_write(c, WM8731_RESET, 0)
108 60
109static const char *wm8731_input_select[] = {"Line In", "Mic"}; 61static const char *wm8731_input_select[] = {"Line In", "Mic"};
110static const char *wm8731_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"}; 62static const char *wm8731_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
@@ -267,12 +219,12 @@ static int wm8731_hw_params(struct snd_pcm_substream *substream,
267 struct snd_soc_device *socdev = rtd->socdev; 219 struct snd_soc_device *socdev = rtd->socdev;
268 struct snd_soc_codec *codec = socdev->card->codec; 220 struct snd_soc_codec *codec = socdev->card->codec;
269 struct wm8731_priv *wm8731 = codec->private_data; 221 struct wm8731_priv *wm8731 = codec->private_data;
270 u16 iface = wm8731_read_reg_cache(codec, WM8731_IFACE) & 0xfff3; 222 u16 iface = snd_soc_read(codec, WM8731_IFACE) & 0xfff3;
271 int i = get_coeff(wm8731->sysclk, params_rate(params)); 223 int i = get_coeff(wm8731->sysclk, params_rate(params));
272 u16 srate = (coeff_div[i].sr << 2) | 224 u16 srate = (coeff_div[i].sr << 2) |
273 (coeff_div[i].bosr << 1) | coeff_div[i].usb; 225 (coeff_div[i].bosr << 1) | coeff_div[i].usb;
274 226
275 wm8731_write(codec, WM8731_SRATE, srate); 227 snd_soc_write(codec, WM8731_SRATE, srate);
276 228
277 /* bit size */ 229 /* bit size */
278 switch (params_format(params)) { 230 switch (params_format(params)) {
@@ -286,7 +238,7 @@ static int wm8731_hw_params(struct snd_pcm_substream *substream,
286 break; 238 break;
287 } 239 }
288 240
289 wm8731_write(codec, WM8731_IFACE, iface); 241 snd_soc_write(codec, WM8731_IFACE, iface);
290 return 0; 242 return 0;
291} 243}
292 244
@@ -298,7 +250,7 @@ static int wm8731_pcm_prepare(struct snd_pcm_substream *substream,
298 struct snd_soc_codec *codec = socdev->card->codec; 250 struct snd_soc_codec *codec = socdev->card->codec;
299 251
300 /* set active */ 252 /* set active */
301 wm8731_write(codec, WM8731_ACTIVE, 0x0001); 253 snd_soc_write(codec, WM8731_ACTIVE, 0x0001);
302 254
303 return 0; 255 return 0;
304} 256}
@@ -313,19 +265,19 @@ static void wm8731_shutdown(struct snd_pcm_substream *substream,
313 /* deactivate */ 265 /* deactivate */
314 if (!codec->active) { 266 if (!codec->active) {
315 udelay(50); 267 udelay(50);
316 wm8731_write(codec, WM8731_ACTIVE, 0x0); 268 snd_soc_write(codec, WM8731_ACTIVE, 0x0);
317 } 269 }
318} 270}
319 271
320static int wm8731_mute(struct snd_soc_dai *dai, int mute) 272static int wm8731_mute(struct snd_soc_dai *dai, int mute)
321{ 273{
322 struct snd_soc_codec *codec = dai->codec; 274 struct snd_soc_codec *codec = dai->codec;
323 u16 mute_reg = wm8731_read_reg_cache(codec, WM8731_APDIGI) & 0xfff7; 275 u16 mute_reg = snd_soc_read(codec, WM8731_APDIGI) & 0xfff7;
324 276
325 if (mute) 277 if (mute)
326 wm8731_write(codec, WM8731_APDIGI, mute_reg | 0x8); 278 snd_soc_write(codec, WM8731_APDIGI, mute_reg | 0x8);
327 else 279 else
328 wm8731_write(codec, WM8731_APDIGI, mute_reg); 280 snd_soc_write(codec, WM8731_APDIGI, mute_reg);
329 return 0; 281 return 0;
330} 282}
331 283
@@ -403,7 +355,7 @@ static int wm8731_set_dai_fmt(struct snd_soc_dai *codec_dai,
403 } 355 }
404 356
405 /* set iface */ 357 /* set iface */
406 wm8731_write(codec, WM8731_IFACE, iface); 358 snd_soc_write(codec, WM8731_IFACE, iface);
407 return 0; 359 return 0;
408} 360}
409 361
@@ -419,12 +371,12 @@ static int wm8731_set_bias_level(struct snd_soc_codec *codec,
419 break; 371 break;
420 case SND_SOC_BIAS_STANDBY: 372 case SND_SOC_BIAS_STANDBY:
421 /* Clear PWROFF, gate CLKOUT, everything else as-is */ 373 /* Clear PWROFF, gate CLKOUT, everything else as-is */
422 reg = wm8731_read_reg_cache(codec, WM8731_PWR) & 0xff7f; 374 reg = snd_soc_read(codec, WM8731_PWR) & 0xff7f;
423 wm8731_write(codec, WM8731_PWR, reg | 0x0040); 375 snd_soc_write(codec, WM8731_PWR, reg | 0x0040);
424 break; 376 break;
425 case SND_SOC_BIAS_OFF: 377 case SND_SOC_BIAS_OFF:
426 wm8731_write(codec, WM8731_ACTIVE, 0x0); 378 snd_soc_write(codec, WM8731_ACTIVE, 0x0);
427 wm8731_write(codec, WM8731_PWR, 0xffff); 379 snd_soc_write(codec, WM8731_PWR, 0xffff);
428 break; 380 break;
429 } 381 }
430 codec->bias_level = level; 382 codec->bias_level = level;
@@ -474,7 +426,7 @@ static int wm8731_suspend(struct platform_device *pdev, pm_message_t state)
474 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 426 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
475 struct snd_soc_codec *codec = socdev->card->codec; 427 struct snd_soc_codec *codec = socdev->card->codec;
476 428
477 wm8731_write(codec, WM8731_ACTIVE, 0x0); 429 snd_soc_write(codec, WM8731_ACTIVE, 0x0);
478 wm8731_set_bias_level(codec, SND_SOC_BIAS_OFF); 430 wm8731_set_bias_level(codec, SND_SOC_BIAS_OFF);
479 return 0; 431 return 0;
480} 432}
@@ -560,11 +512,11 @@ struct snd_soc_codec_device soc_codec_dev_wm8731 = {
560}; 512};
561EXPORT_SYMBOL_GPL(soc_codec_dev_wm8731); 513EXPORT_SYMBOL_GPL(soc_codec_dev_wm8731);
562 514
563static int wm8731_register(struct wm8731_priv *wm8731) 515static int wm8731_register(struct wm8731_priv *wm8731,
516 enum snd_soc_control_type control)
564{ 517{
565 int ret; 518 int ret;
566 struct snd_soc_codec *codec = &wm8731->codec; 519 struct snd_soc_codec *codec = &wm8731->codec;
567 u16 reg;
568 520
569 if (wm8731_codec) { 521 if (wm8731_codec) {
570 dev_err(codec->dev, "Another WM8731 is registered\n"); 522 dev_err(codec->dev, "Another WM8731 is registered\n");
@@ -579,8 +531,6 @@ static int wm8731_register(struct wm8731_priv *wm8731)
579 codec->private_data = wm8731; 531 codec->private_data = wm8731;
580 codec->name = "WM8731"; 532 codec->name = "WM8731";
581 codec->owner = THIS_MODULE; 533 codec->owner = THIS_MODULE;
582 codec->read = wm8731_read_reg_cache;
583 codec->write = wm8731_write;
584 codec->bias_level = SND_SOC_BIAS_OFF; 534 codec->bias_level = SND_SOC_BIAS_OFF;
585 codec->set_bias_level = wm8731_set_bias_level; 535 codec->set_bias_level = wm8731_set_bias_level;
586 codec->dai = &wm8731_dai; 536 codec->dai = &wm8731_dai;
@@ -590,6 +540,12 @@ static int wm8731_register(struct wm8731_priv *wm8731)
590 540
591 memcpy(codec->reg_cache, wm8731_reg, sizeof(wm8731_reg)); 541 memcpy(codec->reg_cache, wm8731_reg, sizeof(wm8731_reg));
592 542
543 ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
544 if (ret < 0) {
545 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
546 goto err;
547 }
548
593 ret = wm8731_reset(codec); 549 ret = wm8731_reset(codec);
594 if (ret < 0) { 550 if (ret < 0) {
595 dev_err(codec->dev, "Failed to issue reset: %d\n", ret); 551 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
@@ -601,18 +557,13 @@ static int wm8731_register(struct wm8731_priv *wm8731)
601 wm8731_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 557 wm8731_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
602 558
603 /* Latch the update bits */ 559 /* Latch the update bits */
604 reg = wm8731_read_reg_cache(codec, WM8731_LOUT1V); 560 snd_soc_update_bits(codec, WM8731_LOUT1V, 0x100, 0);
605 wm8731_write(codec, WM8731_LOUT1V, reg & ~0x0100); 561 snd_soc_update_bits(codec, WM8731_ROUT1V, 0x100, 0);
606 reg = wm8731_read_reg_cache(codec, WM8731_ROUT1V); 562 snd_soc_update_bits(codec, WM8731_LINVOL, 0x100, 0);
607 wm8731_write(codec, WM8731_ROUT1V, reg & ~0x0100); 563 snd_soc_update_bits(codec, WM8731_RINVOL, 0x100, 0);
608 reg = wm8731_read_reg_cache(codec, WM8731_LINVOL);
609 wm8731_write(codec, WM8731_LINVOL, reg & ~0x0100);
610 reg = wm8731_read_reg_cache(codec, WM8731_RINVOL);
611 wm8731_write(codec, WM8731_RINVOL, reg & ~0x0100);
612 564
613 /* Disable bypass path by default */ 565 /* Disable bypass path by default */
614 reg = wm8731_read_reg_cache(codec, WM8731_APANA); 566 snd_soc_update_bits(codec, WM8731_APANA, 0x4, 0);
615 wm8731_write(codec, WM8731_APANA, reg & ~0x4);
616 567
617 wm8731_codec = codec; 568 wm8731_codec = codec;
618 569
@@ -648,30 +599,6 @@ static void wm8731_unregister(struct wm8731_priv *wm8731)
648} 599}
649 600
650#if defined(CONFIG_SPI_MASTER) 601#if defined(CONFIG_SPI_MASTER)
651static int wm8731_spi_write(struct spi_device *spi, const char *data, int len)
652{
653 struct spi_transfer t;
654 struct spi_message m;
655 u8 msg[2];
656
657 if (len <= 0)
658 return 0;
659
660 msg[0] = data[0];
661 msg[1] = data[1];
662
663 spi_message_init(&m);
664 memset(&t, 0, (sizeof t));
665
666 t.tx_buf = &msg[0];
667 t.len = len;
668
669 spi_message_add_tail(&t, &m);
670 spi_sync(spi, &m);
671
672 return len;
673}
674
675static int __devinit wm8731_spi_probe(struct spi_device *spi) 602static int __devinit wm8731_spi_probe(struct spi_device *spi)
676{ 603{
677 struct snd_soc_codec *codec; 604 struct snd_soc_codec *codec;
@@ -683,12 +610,11 @@ static int __devinit wm8731_spi_probe(struct spi_device *spi)
683 610
684 codec = &wm8731->codec; 611 codec = &wm8731->codec;
685 codec->control_data = spi; 612 codec->control_data = spi;
686 codec->hw_write = (hw_write_t)wm8731_spi_write;
687 codec->dev = &spi->dev; 613 codec->dev = &spi->dev;
688 614
689 dev_set_drvdata(&spi->dev, wm8731); 615 dev_set_drvdata(&spi->dev, wm8731);
690 616
691 return wm8731_register(wm8731); 617 return wm8731_register(wm8731, SND_SOC_SPI);
692} 618}
693 619
694static int __devexit wm8731_spi_remove(struct spi_device *spi) 620static int __devexit wm8731_spi_remove(struct spi_device *spi)
@@ -740,14 +666,13 @@ static __devinit int wm8731_i2c_probe(struct i2c_client *i2c,
740 return -ENOMEM; 666 return -ENOMEM;
741 667
742 codec = &wm8731->codec; 668 codec = &wm8731->codec;
743 codec->hw_write = (hw_write_t)i2c_master_send;
744 669
745 i2c_set_clientdata(i2c, wm8731); 670 i2c_set_clientdata(i2c, wm8731);
746 codec->control_data = i2c; 671 codec->control_data = i2c;
747 672
748 codec->dev = &i2c->dev; 673 codec->dev = &i2c->dev;
749 674
750 return wm8731_register(wm8731); 675 return wm8731_register(wm8731, SND_SOC_I2C);
751} 676}
752 677
753static __devexit int wm8731_i2c_remove(struct i2c_client *client) 678static __devexit int wm8731_i2c_remove(struct i2c_client *client)
diff --git a/sound/soc/codecs/wm8750.c b/sound/soc/codecs/wm8750.c
index b64509b01a49..4ba1e7e93fb4 100644
--- a/sound/soc/codecs/wm8750.c
+++ b/sound/soc/codecs/wm8750.c
@@ -55,50 +55,7 @@ static const u16 wm8750_reg[] = {
55 0x0079, 0x0079, 0x0079, /* 40 */ 55 0x0079, 0x0079, 0x0079, /* 40 */
56}; 56};
57 57
58/* 58#define wm8750_reset(c) snd_soc_write(c, WM8750_RESET, 0)
59 * read wm8750 register cache
60 */
61static inline unsigned int wm8750_read_reg_cache(struct snd_soc_codec *codec,
62 unsigned int reg)
63{
64 u16 *cache = codec->reg_cache;
65 if (reg > WM8750_CACHE_REGNUM)
66 return -1;
67 return cache[reg];
68}
69
70/*
71 * write wm8750 register cache
72 */
73static inline void wm8750_write_reg_cache(struct snd_soc_codec *codec,
74 unsigned int reg, unsigned int value)
75{
76 u16 *cache = codec->reg_cache;
77 if (reg > WM8750_CACHE_REGNUM)
78 return;
79 cache[reg] = value;
80}
81
82static int wm8750_write(struct snd_soc_codec *codec, unsigned int reg,
83 unsigned int value)
84{
85 u8 data[2];
86
87 /* data is
88 * D15..D9 WM8753 register offset
89 * D8...D0 register data
90 */
91 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
92 data[1] = value & 0x00ff;
93
94 wm8750_write_reg_cache(codec, reg, value);
95 if (codec->hw_write(codec->control_data, data, 2) == 2)
96 return 0;
97 else
98 return -EIO;
99}
100
101#define wm8750_reset(c) wm8750_write(c, WM8750_RESET, 0)
102 59
103/* 60/*
104 * WM8750 Controls 61 * WM8750 Controls
@@ -594,7 +551,7 @@ static int wm8750_set_dai_fmt(struct snd_soc_dai *codec_dai,
594 return -EINVAL; 551 return -EINVAL;
595 } 552 }
596 553
597 wm8750_write(codec, WM8750_IFACE, iface); 554 snd_soc_write(codec, WM8750_IFACE, iface);
598 return 0; 555 return 0;
599} 556}
600 557
@@ -606,8 +563,8 @@ static int wm8750_pcm_hw_params(struct snd_pcm_substream *substream,
606 struct snd_soc_device *socdev = rtd->socdev; 563 struct snd_soc_device *socdev = rtd->socdev;
607 struct snd_soc_codec *codec = socdev->card->codec; 564 struct snd_soc_codec *codec = socdev->card->codec;
608 struct wm8750_priv *wm8750 = codec->private_data; 565 struct wm8750_priv *wm8750 = codec->private_data;
609 u16 iface = wm8750_read_reg_cache(codec, WM8750_IFACE) & 0x1f3; 566 u16 iface = snd_soc_read(codec, WM8750_IFACE) & 0x1f3;
610 u16 srate = wm8750_read_reg_cache(codec, WM8750_SRATE) & 0x1c0; 567 u16 srate = snd_soc_read(codec, WM8750_SRATE) & 0x1c0;
611 int coeff = get_coeff(wm8750->sysclk, params_rate(params)); 568 int coeff = get_coeff(wm8750->sysclk, params_rate(params));
612 569
613 /* bit size */ 570 /* bit size */
@@ -626,9 +583,9 @@ static int wm8750_pcm_hw_params(struct snd_pcm_substream *substream,
626 } 583 }
627 584
628 /* set iface & srate */ 585 /* set iface & srate */
629 wm8750_write(codec, WM8750_IFACE, iface); 586 snd_soc_write(codec, WM8750_IFACE, iface);
630 if (coeff >= 0) 587 if (coeff >= 0)
631 wm8750_write(codec, WM8750_SRATE, srate | 588 snd_soc_write(codec, WM8750_SRATE, srate |
632 (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb); 589 (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
633 590
634 return 0; 591 return 0;
@@ -637,35 +594,35 @@ static int wm8750_pcm_hw_params(struct snd_pcm_substream *substream,
637static int wm8750_mute(struct snd_soc_dai *dai, int mute) 594static int wm8750_mute(struct snd_soc_dai *dai, int mute)
638{ 595{
639 struct snd_soc_codec *codec = dai->codec; 596 struct snd_soc_codec *codec = dai->codec;
640 u16 mute_reg = wm8750_read_reg_cache(codec, WM8750_ADCDAC) & 0xfff7; 597 u16 mute_reg = snd_soc_read(codec, WM8750_ADCDAC) & 0xfff7;
641 598
642 if (mute) 599 if (mute)
643 wm8750_write(codec, WM8750_ADCDAC, mute_reg | 0x8); 600 snd_soc_write(codec, WM8750_ADCDAC, mute_reg | 0x8);
644 else 601 else
645 wm8750_write(codec, WM8750_ADCDAC, mute_reg); 602 snd_soc_write(codec, WM8750_ADCDAC, mute_reg);
646 return 0; 603 return 0;
647} 604}
648 605
649static int wm8750_set_bias_level(struct snd_soc_codec *codec, 606static int wm8750_set_bias_level(struct snd_soc_codec *codec,
650 enum snd_soc_bias_level level) 607 enum snd_soc_bias_level level)
651{ 608{
652 u16 pwr_reg = wm8750_read_reg_cache(codec, WM8750_PWR1) & 0xfe3e; 609 u16 pwr_reg = snd_soc_read(codec, WM8750_PWR1) & 0xfe3e;
653 610
654 switch (level) { 611 switch (level) {
655 case SND_SOC_BIAS_ON: 612 case SND_SOC_BIAS_ON:
656 /* set vmid to 50k and unmute dac */ 613 /* set vmid to 50k and unmute dac */
657 wm8750_write(codec, WM8750_PWR1, pwr_reg | 0x00c0); 614 snd_soc_write(codec, WM8750_PWR1, pwr_reg | 0x00c0);
658 break; 615 break;
659 case SND_SOC_BIAS_PREPARE: 616 case SND_SOC_BIAS_PREPARE:
660 /* set vmid to 5k for quick power up */ 617 /* set vmid to 5k for quick power up */
661 wm8750_write(codec, WM8750_PWR1, pwr_reg | 0x01c1); 618 snd_soc_write(codec, WM8750_PWR1, pwr_reg | 0x01c1);
662 break; 619 break;
663 case SND_SOC_BIAS_STANDBY: 620 case SND_SOC_BIAS_STANDBY:
664 /* mute dac and set vmid to 500k, enable VREF */ 621 /* mute dac and set vmid to 500k, enable VREF */
665 wm8750_write(codec, WM8750_PWR1, pwr_reg | 0x0141); 622 snd_soc_write(codec, WM8750_PWR1, pwr_reg | 0x0141);
666 break; 623 break;
667 case SND_SOC_BIAS_OFF: 624 case SND_SOC_BIAS_OFF:
668 wm8750_write(codec, WM8750_PWR1, 0x0001); 625 snd_soc_write(codec, WM8750_PWR1, 0x0001);
669 break; 626 break;
670 } 627 }
671 codec->bias_level = level; 628 codec->bias_level = level;
@@ -754,15 +711,14 @@ static int wm8750_resume(struct platform_device *pdev)
754 * initialise the WM8750 driver 711 * initialise the WM8750 driver
755 * register the mixer and dsp interfaces with the kernel 712 * register the mixer and dsp interfaces with the kernel
756 */ 713 */
757static int wm8750_init(struct snd_soc_device *socdev) 714static int wm8750_init(struct snd_soc_device *socdev,
715 enum snd_soc_control_type control)
758{ 716{
759 struct snd_soc_codec *codec = socdev->card->codec; 717 struct snd_soc_codec *codec = socdev->card->codec;
760 int reg, ret = 0; 718 int reg, ret = 0;
761 719
762 codec->name = "WM8750"; 720 codec->name = "WM8750";
763 codec->owner = THIS_MODULE; 721 codec->owner = THIS_MODULE;
764 codec->read = wm8750_read_reg_cache;
765 codec->write = wm8750_write;
766 codec->set_bias_level = wm8750_set_bias_level; 722 codec->set_bias_level = wm8750_set_bias_level;
767 codec->dai = &wm8750_dai; 723 codec->dai = &wm8750_dai;
768 codec->num_dai = 1; 724 codec->num_dai = 1;
@@ -771,13 +727,23 @@ static int wm8750_init(struct snd_soc_device *socdev)
771 if (codec->reg_cache == NULL) 727 if (codec->reg_cache == NULL)
772 return -ENOMEM; 728 return -ENOMEM;
773 729
774 wm8750_reset(codec); 730 ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
731 if (ret < 0) {
732 printk(KERN_ERR "wm8750: failed to set cache I/O: %d\n", ret);
733 goto err;
734 }
735
736 ret = wm8750_reset(codec);
737 if (ret < 0) {
738 printk(KERN_ERR "wm8750: failed to reset: %d\n", ret);
739 goto err;
740 }
775 741
776 /* register pcms */ 742 /* register pcms */
777 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 743 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
778 if (ret < 0) { 744 if (ret < 0) {
779 printk(KERN_ERR "wm8750: failed to create pcms\n"); 745 printk(KERN_ERR "wm8750: failed to create pcms\n");
780 goto pcm_err; 746 goto err;
781 } 747 }
782 748
783 /* charge output caps */ 749 /* charge output caps */
@@ -786,22 +752,22 @@ static int wm8750_init(struct snd_soc_device *socdev)
786 schedule_delayed_work(&codec->delayed_work, msecs_to_jiffies(1000)); 752 schedule_delayed_work(&codec->delayed_work, msecs_to_jiffies(1000));
787 753
788 /* set the update bits */ 754 /* set the update bits */
789 reg = wm8750_read_reg_cache(codec, WM8750_LDAC); 755 reg = snd_soc_read(codec, WM8750_LDAC);
790 wm8750_write(codec, WM8750_LDAC, reg | 0x0100); 756 snd_soc_write(codec, WM8750_LDAC, reg | 0x0100);
791 reg = wm8750_read_reg_cache(codec, WM8750_RDAC); 757 reg = snd_soc_read(codec, WM8750_RDAC);
792 wm8750_write(codec, WM8750_RDAC, reg | 0x0100); 758 snd_soc_write(codec, WM8750_RDAC, reg | 0x0100);
793 reg = wm8750_read_reg_cache(codec, WM8750_LOUT1V); 759 reg = snd_soc_read(codec, WM8750_LOUT1V);
794 wm8750_write(codec, WM8750_LOUT1V, reg | 0x0100); 760 snd_soc_write(codec, WM8750_LOUT1V, reg | 0x0100);
795 reg = wm8750_read_reg_cache(codec, WM8750_ROUT1V); 761 reg = snd_soc_read(codec, WM8750_ROUT1V);
796 wm8750_write(codec, WM8750_ROUT1V, reg | 0x0100); 762 snd_soc_write(codec, WM8750_ROUT1V, reg | 0x0100);
797 reg = wm8750_read_reg_cache(codec, WM8750_LOUT2V); 763 reg = snd_soc_read(codec, WM8750_LOUT2V);
798 wm8750_write(codec, WM8750_LOUT2V, reg | 0x0100); 764 snd_soc_write(codec, WM8750_LOUT2V, reg | 0x0100);
799 reg = wm8750_read_reg_cache(codec, WM8750_ROUT2V); 765 reg = snd_soc_read(codec, WM8750_ROUT2V);
800 wm8750_write(codec, WM8750_ROUT2V, reg | 0x0100); 766 snd_soc_write(codec, WM8750_ROUT2V, reg | 0x0100);
801 reg = wm8750_read_reg_cache(codec, WM8750_LINVOL); 767 reg = snd_soc_read(codec, WM8750_LINVOL);
802 wm8750_write(codec, WM8750_LINVOL, reg | 0x0100); 768 snd_soc_write(codec, WM8750_LINVOL, reg | 0x0100);
803 reg = wm8750_read_reg_cache(codec, WM8750_RINVOL); 769 reg = snd_soc_read(codec, WM8750_RINVOL);
804 wm8750_write(codec, WM8750_RINVOL, reg | 0x0100); 770 snd_soc_write(codec, WM8750_RINVOL, reg | 0x0100);
805 771
806 snd_soc_add_controls(codec, wm8750_snd_controls, 772 snd_soc_add_controls(codec, wm8750_snd_controls,
807 ARRAY_SIZE(wm8750_snd_controls)); 773 ARRAY_SIZE(wm8750_snd_controls));
@@ -816,7 +782,7 @@ static int wm8750_init(struct snd_soc_device *socdev)
816card_err: 782card_err:
817 snd_soc_free_pcms(socdev); 783 snd_soc_free_pcms(socdev);
818 snd_soc_dapm_free(socdev); 784 snd_soc_dapm_free(socdev);
819pcm_err: 785err:
820 kfree(codec->reg_cache); 786 kfree(codec->reg_cache);
821 return ret; 787 return ret;
822} 788}
@@ -844,7 +810,7 @@ static int wm8750_i2c_probe(struct i2c_client *i2c,
844 i2c_set_clientdata(i2c, codec); 810 i2c_set_clientdata(i2c, codec);
845 codec->control_data = i2c; 811 codec->control_data = i2c;
846 812
847 ret = wm8750_init(socdev); 813 ret = wm8750_init(socdev, SND_SOC_I2C);
848 if (ret < 0) 814 if (ret < 0)
849 pr_err("failed to initialise WM8750\n"); 815 pr_err("failed to initialise WM8750\n");
850 816
@@ -924,7 +890,7 @@ static int __devinit wm8750_spi_probe(struct spi_device *spi)
924 890
925 codec->control_data = spi; 891 codec->control_data = spi;
926 892
927 ret = wm8750_init(socdev); 893 ret = wm8750_init(socdev, SND_SOC_SPI);
928 if (ret < 0) 894 if (ret < 0)
929 dev_err(&spi->dev, "failed to initialise WM8750\n"); 895 dev_err(&spi->dev, "failed to initialise WM8750\n");
930 896
@@ -945,30 +911,6 @@ static struct spi_driver wm8750_spi_driver = {
945 .probe = wm8750_spi_probe, 911 .probe = wm8750_spi_probe,
946 .remove = __devexit_p(wm8750_spi_remove), 912 .remove = __devexit_p(wm8750_spi_remove),
947}; 913};
948
949static int wm8750_spi_write(struct spi_device *spi, const char *data, int len)
950{
951 struct spi_transfer t;
952 struct spi_message m;
953 u8 msg[2];
954
955 if (len <= 0)
956 return 0;
957
958 msg[0] = data[0];
959 msg[1] = data[1];
960
961 spi_message_init(&m);
962 memset(&t, 0, (sizeof t));
963
964 t.tx_buf = &msg[0];
965 t.len = len;
966
967 spi_message_add_tail(&t, &m);
968 spi_sync(spi, &m);
969
970 return len;
971}
972#endif 914#endif
973 915
974static int wm8750_probe(struct platform_device *pdev) 916static int wm8750_probe(struct platform_device *pdev)
@@ -1002,13 +944,11 @@ static int wm8750_probe(struct platform_device *pdev)
1002 944
1003#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 945#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1004 if (setup->i2c_address) { 946 if (setup->i2c_address) {
1005 codec->hw_write = (hw_write_t)i2c_master_send;
1006 ret = wm8750_add_i2c_device(pdev, setup); 947 ret = wm8750_add_i2c_device(pdev, setup);
1007 } 948 }
1008#endif 949#endif
1009#if defined(CONFIG_SPI_MASTER) 950#if defined(CONFIG_SPI_MASTER)
1010 if (setup->spi) { 951 if (setup->spi) {
1011 codec->hw_write = (hw_write_t)wm8750_spi_write;
1012 ret = spi_register_driver(&wm8750_spi_driver); 952 ret = spi_register_driver(&wm8750_spi_driver);
1013 if (ret != 0) 953 if (ret != 0)
1014 printk(KERN_ERR "can't add spi driver"); 954 printk(KERN_ERR "can't add spi driver");
diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c
index ac308993ac5a..5e9c855c0036 100644
--- a/sound/soc/codecs/wm8900.c
+++ b/sound/soc/codecs/wm8900.c
@@ -183,111 +183,20 @@ static const u16 wm8900_reg_defaults[WM8900_MAXREG] = {
183 /* Remaining registers all zero */ 183 /* Remaining registers all zero */
184}; 184};
185 185
186/* 186static int wm8900_volatile_register(unsigned int reg)
187 * read wm8900 register cache
188 */
189static inline unsigned int wm8900_read_reg_cache(struct snd_soc_codec *codec,
190 unsigned int reg)
191{
192 u16 *cache = codec->reg_cache;
193
194 BUG_ON(reg >= WM8900_MAXREG);
195
196 if (reg == WM8900_REG_ID)
197 return 0;
198
199 return cache[reg];
200}
201
202/*
203 * write wm8900 register cache
204 */
205static inline void wm8900_write_reg_cache(struct snd_soc_codec *codec,
206 u16 reg, unsigned int value)
207{
208 u16 *cache = codec->reg_cache;
209
210 BUG_ON(reg >= WM8900_MAXREG);
211
212 cache[reg] = value;
213}
214
215/*
216 * write to the WM8900 register space
217 */
218static int wm8900_write(struct snd_soc_codec *codec, unsigned int reg,
219 unsigned int value)
220{
221 u8 data[3];
222
223 if (value == wm8900_read_reg_cache(codec, reg))
224 return 0;
225
226 /* data is
227 * D15..D9 WM8900 register offset
228 * D8...D0 register data
229 */
230 data[0] = reg;
231 data[1] = value >> 8;
232 data[2] = value & 0x00ff;
233
234 wm8900_write_reg_cache(codec, reg, value);
235 if (codec->hw_write(codec->control_data, data, 3) == 3)
236 return 0;
237 else
238 return -EIO;
239}
240
241/*
242 * Read from the wm8900.
243 */
244static unsigned int wm8900_chip_read(struct snd_soc_codec *codec, u8 reg)
245{
246 struct i2c_msg xfer[2];
247 u16 data;
248 int ret;
249 struct i2c_client *client = codec->control_data;
250
251 BUG_ON(reg != WM8900_REG_ID && reg != WM8900_REG_POWER1);
252
253 /* Write register */
254 xfer[0].addr = client->addr;
255 xfer[0].flags = 0;
256 xfer[0].len = 1;
257 xfer[0].buf = &reg;
258
259 /* Read data */
260 xfer[1].addr = client->addr;
261 xfer[1].flags = I2C_M_RD;
262 xfer[1].len = 2;
263 xfer[1].buf = (u8 *)&data;
264
265 ret = i2c_transfer(client->adapter, xfer, 2);
266 if (ret != 2) {
267 printk(KERN_CRIT "i2c_transfer returned %d\n", ret);
268 return 0;
269 }
270
271 return (data >> 8) | ((data & 0xff) << 8);
272}
273
274/*
275 * Read from the WM8900 register space. Most registers can't be read
276 * and are therefore supplied from cache.
277 */
278static unsigned int wm8900_read(struct snd_soc_codec *codec, unsigned int reg)
279{ 187{
280 switch (reg) { 188 switch (reg) {
281 case WM8900_REG_ID: 189 case WM8900_REG_ID:
282 return wm8900_chip_read(codec, reg); 190 case WM8900_REG_POWER1:
191 return 1;
283 default: 192 default:
284 return wm8900_read_reg_cache(codec, reg); 193 return 0;
285 } 194 }
286} 195}
287 196
288static void wm8900_reset(struct snd_soc_codec *codec) 197static void wm8900_reset(struct snd_soc_codec *codec)
289{ 198{
290 wm8900_write(codec, WM8900_REG_RESET, 0); 199 snd_soc_write(codec, WM8900_REG_RESET, 0);
291 200
292 memcpy(codec->reg_cache, wm8900_reg_defaults, 201 memcpy(codec->reg_cache, wm8900_reg_defaults,
293 sizeof(codec->reg_cache)); 202 sizeof(codec->reg_cache));
@@ -297,14 +206,14 @@ static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
297 struct snd_kcontrol *kcontrol, int event) 206 struct snd_kcontrol *kcontrol, int event)
298{ 207{
299 struct snd_soc_codec *codec = w->codec; 208 struct snd_soc_codec *codec = w->codec;
300 u16 hpctl1 = wm8900_read(codec, WM8900_REG_HPCTL1); 209 u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
301 210
302 switch (event) { 211 switch (event) {
303 case SND_SOC_DAPM_PRE_PMU: 212 case SND_SOC_DAPM_PRE_PMU:
304 /* Clamp headphone outputs */ 213 /* Clamp headphone outputs */
305 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP | 214 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
306 WM8900_REG_HPCTL1_HP_CLAMP_OP; 215 WM8900_REG_HPCTL1_HP_CLAMP_OP;
307 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 216 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
308 break; 217 break;
309 218
310 case SND_SOC_DAPM_POST_PMU: 219 case SND_SOC_DAPM_POST_PMU:
@@ -313,41 +222,41 @@ static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
313 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT | 222 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
314 WM8900_REG_HPCTL1_HP_SHORT2 | 223 WM8900_REG_HPCTL1_HP_SHORT2 |
315 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA; 224 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
316 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 225 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
317 226
318 msleep(400); 227 msleep(400);
319 228
320 /* Enable the output stage */ 229 /* Enable the output stage */
321 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP; 230 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
322 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA; 231 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
323 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 232 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
324 233
325 /* Remove the shorts */ 234 /* Remove the shorts */
326 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2; 235 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
327 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 236 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
328 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT; 237 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
329 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 238 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
330 break; 239 break;
331 240
332 case SND_SOC_DAPM_PRE_PMD: 241 case SND_SOC_DAPM_PRE_PMD:
333 /* Short the output */ 242 /* Short the output */
334 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT; 243 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
335 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 244 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
336 245
337 /* Disable the output stage */ 246 /* Disable the output stage */
338 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA; 247 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
339 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 248 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
340 249
341 /* Clamp the outputs and power down input */ 250 /* Clamp the outputs and power down input */
342 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP | 251 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
343 WM8900_REG_HPCTL1_HP_CLAMP_OP; 252 WM8900_REG_HPCTL1_HP_CLAMP_OP;
344 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA; 253 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
345 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1); 254 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
346 break; 255 break;
347 256
348 case SND_SOC_DAPM_POST_PMD: 257 case SND_SOC_DAPM_POST_PMD:
349 /* Disable everything */ 258 /* Disable everything */
350 wm8900_write(codec, WM8900_REG_HPCTL1, 0); 259 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
351 break; 260 break;
352 261
353 default: 262 default:
@@ -723,7 +632,7 @@ static int wm8900_hw_params(struct snd_pcm_substream *substream,
723 struct snd_soc_codec *codec = socdev->card->codec; 632 struct snd_soc_codec *codec = socdev->card->codec;
724 u16 reg; 633 u16 reg;
725 634
726 reg = wm8900_read(codec, WM8900_REG_AUDIO1) & ~0x60; 635 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
727 636
728 switch (params_format(params)) { 637 switch (params_format(params)) {
729 case SNDRV_PCM_FORMAT_S16_LE: 638 case SNDRV_PCM_FORMAT_S16_LE:
@@ -741,17 +650,17 @@ static int wm8900_hw_params(struct snd_pcm_substream *substream,
741 return -EINVAL; 650 return -EINVAL;
742 } 651 }
743 652
744 wm8900_write(codec, WM8900_REG_AUDIO1, reg); 653 snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
745 654
746 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 655 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
747 reg = wm8900_read(codec, WM8900_REG_DACCTRL); 656 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
748 657
749 if (params_rate(params) <= 24000) 658 if (params_rate(params) <= 24000)
750 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT; 659 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
751 else 660 else
752 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT; 661 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
753 662
754 wm8900_write(codec, WM8900_REG_DACCTRL, reg); 663 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
755 } 664 }
756 665
757 return 0; 666 return 0;
@@ -845,18 +754,18 @@ static int wm8900_set_fll(struct snd_soc_codec *codec,
845 return 0; 754 return 0;
846 755
847 /* The digital side should be disabled during any change. */ 756 /* The digital side should be disabled during any change. */
848 reg = wm8900_read(codec, WM8900_REG_POWER1); 757 reg = snd_soc_read(codec, WM8900_REG_POWER1);
849 wm8900_write(codec, WM8900_REG_POWER1, 758 snd_soc_write(codec, WM8900_REG_POWER1,
850 reg & (~WM8900_REG_POWER1_FLL_ENA)); 759 reg & (~WM8900_REG_POWER1_FLL_ENA));
851 760
852 /* Disable the FLL? */ 761 /* Disable the FLL? */
853 if (!freq_in || !freq_out) { 762 if (!freq_in || !freq_out) {
854 reg = wm8900_read(codec, WM8900_REG_CLOCKING1); 763 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
855 wm8900_write(codec, WM8900_REG_CLOCKING1, 764 snd_soc_write(codec, WM8900_REG_CLOCKING1,
856 reg & (~WM8900_REG_CLOCKING1_MCLK_SRC)); 765 reg & (~WM8900_REG_CLOCKING1_MCLK_SRC));
857 766
858 reg = wm8900_read(codec, WM8900_REG_FLLCTL1); 767 reg = snd_soc_read(codec, WM8900_REG_FLLCTL1);
859 wm8900_write(codec, WM8900_REG_FLLCTL1, 768 snd_soc_write(codec, WM8900_REG_FLLCTL1,
860 reg & (~WM8900_REG_FLLCTL1_OSC_ENA)); 769 reg & (~WM8900_REG_FLLCTL1_OSC_ENA));
861 770
862 wm8900->fll_in = freq_in; 771 wm8900->fll_in = freq_in;
@@ -873,33 +782,33 @@ static int wm8900_set_fll(struct snd_soc_codec *codec,
873 782
874 /* The osclilator *MUST* be enabled before we enable the 783 /* The osclilator *MUST* be enabled before we enable the
875 * digital circuit. */ 784 * digital circuit. */
876 wm8900_write(codec, WM8900_REG_FLLCTL1, 785 snd_soc_write(codec, WM8900_REG_FLLCTL1,
877 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA); 786 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
878 787
879 wm8900_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5); 788 snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
880 wm8900_write(codec, WM8900_REG_FLLCTL5, 789 snd_soc_write(codec, WM8900_REG_FLLCTL5,
881 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f)); 790 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
882 791
883 if (fll_div.k) { 792 if (fll_div.k) {
884 wm8900_write(codec, WM8900_REG_FLLCTL2, 793 snd_soc_write(codec, WM8900_REG_FLLCTL2,
885 (fll_div.k >> 8) | 0x100); 794 (fll_div.k >> 8) | 0x100);
886 wm8900_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff); 795 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
887 } else 796 } else
888 wm8900_write(codec, WM8900_REG_FLLCTL2, 0); 797 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
889 798
890 if (fll_div.fll_slow_lock_ref) 799 if (fll_div.fll_slow_lock_ref)
891 wm8900_write(codec, WM8900_REG_FLLCTL6, 800 snd_soc_write(codec, WM8900_REG_FLLCTL6,
892 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF); 801 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
893 else 802 else
894 wm8900_write(codec, WM8900_REG_FLLCTL6, 0); 803 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
895 804
896 reg = wm8900_read(codec, WM8900_REG_POWER1); 805 reg = snd_soc_read(codec, WM8900_REG_POWER1);
897 wm8900_write(codec, WM8900_REG_POWER1, 806 snd_soc_write(codec, WM8900_REG_POWER1,
898 reg | WM8900_REG_POWER1_FLL_ENA); 807 reg | WM8900_REG_POWER1_FLL_ENA);
899 808
900reenable: 809reenable:
901 reg = wm8900_read(codec, WM8900_REG_CLOCKING1); 810 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
902 wm8900_write(codec, WM8900_REG_CLOCKING1, 811 snd_soc_write(codec, WM8900_REG_CLOCKING1,
903 reg | WM8900_REG_CLOCKING1_MCLK_SRC); 812 reg | WM8900_REG_CLOCKING1_MCLK_SRC);
904 813
905 return 0; 814 return 0;
@@ -919,38 +828,38 @@ static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
919 828
920 switch (div_id) { 829 switch (div_id) {
921 case WM8900_BCLK_DIV: 830 case WM8900_BCLK_DIV:
922 reg = wm8900_read(codec, WM8900_REG_CLOCKING1); 831 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
923 wm8900_write(codec, WM8900_REG_CLOCKING1, 832 snd_soc_write(codec, WM8900_REG_CLOCKING1,
924 div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK)); 833 div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK));
925 break; 834 break;
926 case WM8900_OPCLK_DIV: 835 case WM8900_OPCLK_DIV:
927 reg = wm8900_read(codec, WM8900_REG_CLOCKING1); 836 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
928 wm8900_write(codec, WM8900_REG_CLOCKING1, 837 snd_soc_write(codec, WM8900_REG_CLOCKING1,
929 div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK)); 838 div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK));
930 break; 839 break;
931 case WM8900_DAC_LRCLK: 840 case WM8900_DAC_LRCLK:
932 reg = wm8900_read(codec, WM8900_REG_AUDIO4); 841 reg = snd_soc_read(codec, WM8900_REG_AUDIO4);
933 wm8900_write(codec, WM8900_REG_AUDIO4, 842 snd_soc_write(codec, WM8900_REG_AUDIO4,
934 div | (reg & WM8900_LRC_MASK)); 843 div | (reg & WM8900_LRC_MASK));
935 break; 844 break;
936 case WM8900_ADC_LRCLK: 845 case WM8900_ADC_LRCLK:
937 reg = wm8900_read(codec, WM8900_REG_AUDIO3); 846 reg = snd_soc_read(codec, WM8900_REG_AUDIO3);
938 wm8900_write(codec, WM8900_REG_AUDIO3, 847 snd_soc_write(codec, WM8900_REG_AUDIO3,
939 div | (reg & WM8900_LRC_MASK)); 848 div | (reg & WM8900_LRC_MASK));
940 break; 849 break;
941 case WM8900_DAC_CLKDIV: 850 case WM8900_DAC_CLKDIV:
942 reg = wm8900_read(codec, WM8900_REG_CLOCKING2); 851 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
943 wm8900_write(codec, WM8900_REG_CLOCKING2, 852 snd_soc_write(codec, WM8900_REG_CLOCKING2,
944 div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV)); 853 div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV));
945 break; 854 break;
946 case WM8900_ADC_CLKDIV: 855 case WM8900_ADC_CLKDIV:
947 reg = wm8900_read(codec, WM8900_REG_CLOCKING2); 856 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
948 wm8900_write(codec, WM8900_REG_CLOCKING2, 857 snd_soc_write(codec, WM8900_REG_CLOCKING2,
949 div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV)); 858 div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV));
950 break; 859 break;
951 case WM8900_LRCLK_MODE: 860 case WM8900_LRCLK_MODE:
952 reg = wm8900_read(codec, WM8900_REG_DACCTRL); 861 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
953 wm8900_write(codec, WM8900_REG_DACCTRL, 862 snd_soc_write(codec, WM8900_REG_DACCTRL,
954 div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE)); 863 div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE));
955 break; 864 break;
956 default: 865 default:
@@ -967,10 +876,10 @@ static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
967 struct snd_soc_codec *codec = codec_dai->codec; 876 struct snd_soc_codec *codec = codec_dai->codec;
968 unsigned int clocking1, aif1, aif3, aif4; 877 unsigned int clocking1, aif1, aif3, aif4;
969 878
970 clocking1 = wm8900_read(codec, WM8900_REG_CLOCKING1); 879 clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
971 aif1 = wm8900_read(codec, WM8900_REG_AUDIO1); 880 aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
972 aif3 = wm8900_read(codec, WM8900_REG_AUDIO3); 881 aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
973 aif4 = wm8900_read(codec, WM8900_REG_AUDIO4); 882 aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
974 883
975 /* set master/slave audio interface */ 884 /* set master/slave audio interface */
976 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 885 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -1066,10 +975,10 @@ static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
1066 return -EINVAL; 975 return -EINVAL;
1067 } 976 }
1068 977
1069 wm8900_write(codec, WM8900_REG_CLOCKING1, clocking1); 978 snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
1070 wm8900_write(codec, WM8900_REG_AUDIO1, aif1); 979 snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
1071 wm8900_write(codec, WM8900_REG_AUDIO3, aif3); 980 snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
1072 wm8900_write(codec, WM8900_REG_AUDIO4, aif4); 981 snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
1073 982
1074 return 0; 983 return 0;
1075} 984}
@@ -1079,14 +988,14 @@ static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1079 struct snd_soc_codec *codec = codec_dai->codec; 988 struct snd_soc_codec *codec = codec_dai->codec;
1080 u16 reg; 989 u16 reg;
1081 990
1082 reg = wm8900_read(codec, WM8900_REG_DACCTRL); 991 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
1083 992
1084 if (mute) 993 if (mute)
1085 reg |= WM8900_REG_DACCTRL_MUTE; 994 reg |= WM8900_REG_DACCTRL_MUTE;
1086 else 995 else
1087 reg &= ~WM8900_REG_DACCTRL_MUTE; 996 reg &= ~WM8900_REG_DACCTRL_MUTE;
1088 997
1089 wm8900_write(codec, WM8900_REG_DACCTRL, reg); 998 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
1090 999
1091 return 0; 1000 return 0;
1092} 1001}
@@ -1135,11 +1044,11 @@ static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1135 switch (level) { 1044 switch (level) {
1136 case SND_SOC_BIAS_ON: 1045 case SND_SOC_BIAS_ON:
1137 /* Enable thermal shutdown */ 1046 /* Enable thermal shutdown */
1138 reg = wm8900_read(codec, WM8900_REG_GPIO); 1047 reg = snd_soc_read(codec, WM8900_REG_GPIO);
1139 wm8900_write(codec, WM8900_REG_GPIO, 1048 snd_soc_write(codec, WM8900_REG_GPIO,
1140 reg | WM8900_REG_GPIO_TEMP_ENA); 1049 reg | WM8900_REG_GPIO_TEMP_ENA);
1141 reg = wm8900_read(codec, WM8900_REG_ADDCTL); 1050 reg = snd_soc_read(codec, WM8900_REG_ADDCTL);
1142 wm8900_write(codec, WM8900_REG_ADDCTL, 1051 snd_soc_write(codec, WM8900_REG_ADDCTL,
1143 reg | WM8900_REG_ADDCTL_TEMP_SD); 1052 reg | WM8900_REG_ADDCTL_TEMP_SD);
1144 break; 1053 break;
1145 1054
@@ -1150,69 +1059,69 @@ static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1150 /* Charge capacitors if initial power up */ 1059 /* Charge capacitors if initial power up */
1151 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1060 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1152 /* STARTUP_BIAS_ENA on */ 1061 /* STARTUP_BIAS_ENA on */
1153 wm8900_write(codec, WM8900_REG_POWER1, 1062 snd_soc_write(codec, WM8900_REG_POWER1,
1154 WM8900_REG_POWER1_STARTUP_BIAS_ENA); 1063 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1155 1064
1156 /* Startup bias mode */ 1065 /* Startup bias mode */
1157 wm8900_write(codec, WM8900_REG_ADDCTL, 1066 snd_soc_write(codec, WM8900_REG_ADDCTL,
1158 WM8900_REG_ADDCTL_BIAS_SRC | 1067 WM8900_REG_ADDCTL_BIAS_SRC |
1159 WM8900_REG_ADDCTL_VMID_SOFTST); 1068 WM8900_REG_ADDCTL_VMID_SOFTST);
1160 1069
1161 /* VMID 2x50k */ 1070 /* VMID 2x50k */
1162 wm8900_write(codec, WM8900_REG_POWER1, 1071 snd_soc_write(codec, WM8900_REG_POWER1,
1163 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1); 1072 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1164 1073
1165 /* Allow capacitors to charge */ 1074 /* Allow capacitors to charge */
1166 schedule_timeout_interruptible(msecs_to_jiffies(400)); 1075 schedule_timeout_interruptible(msecs_to_jiffies(400));
1167 1076
1168 /* Enable bias */ 1077 /* Enable bias */
1169 wm8900_write(codec, WM8900_REG_POWER1, 1078 snd_soc_write(codec, WM8900_REG_POWER1,
1170 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 1079 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1171 WM8900_REG_POWER1_BIAS_ENA | 0x1); 1080 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1172 1081
1173 wm8900_write(codec, WM8900_REG_ADDCTL, 0); 1082 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1174 1083
1175 wm8900_write(codec, WM8900_REG_POWER1, 1084 snd_soc_write(codec, WM8900_REG_POWER1,
1176 WM8900_REG_POWER1_BIAS_ENA | 0x1); 1085 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1177 } 1086 }
1178 1087
1179 reg = wm8900_read(codec, WM8900_REG_POWER1); 1088 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1180 wm8900_write(codec, WM8900_REG_POWER1, 1089 snd_soc_write(codec, WM8900_REG_POWER1,
1181 (reg & WM8900_REG_POWER1_FLL_ENA) | 1090 (reg & WM8900_REG_POWER1_FLL_ENA) |
1182 WM8900_REG_POWER1_BIAS_ENA | 0x1); 1091 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1183 wm8900_write(codec, WM8900_REG_POWER2, 1092 snd_soc_write(codec, WM8900_REG_POWER2,
1184 WM8900_REG_POWER2_SYSCLK_ENA); 1093 WM8900_REG_POWER2_SYSCLK_ENA);
1185 wm8900_write(codec, WM8900_REG_POWER3, 0); 1094 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1186 break; 1095 break;
1187 1096
1188 case SND_SOC_BIAS_OFF: 1097 case SND_SOC_BIAS_OFF:
1189 /* Startup bias enable */ 1098 /* Startup bias enable */
1190 reg = wm8900_read(codec, WM8900_REG_POWER1); 1099 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1191 wm8900_write(codec, WM8900_REG_POWER1, 1100 snd_soc_write(codec, WM8900_REG_POWER1,
1192 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA); 1101 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1193 wm8900_write(codec, WM8900_REG_ADDCTL, 1102 snd_soc_write(codec, WM8900_REG_ADDCTL,
1194 WM8900_REG_ADDCTL_BIAS_SRC | 1103 WM8900_REG_ADDCTL_BIAS_SRC |
1195 WM8900_REG_ADDCTL_VMID_SOFTST); 1104 WM8900_REG_ADDCTL_VMID_SOFTST);
1196 1105
1197 /* Discharge caps */ 1106 /* Discharge caps */
1198 wm8900_write(codec, WM8900_REG_POWER1, 1107 snd_soc_write(codec, WM8900_REG_POWER1,
1199 WM8900_REG_POWER1_STARTUP_BIAS_ENA); 1108 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1200 schedule_timeout_interruptible(msecs_to_jiffies(500)); 1109 schedule_timeout_interruptible(msecs_to_jiffies(500));
1201 1110
1202 /* Remove clamp */ 1111 /* Remove clamp */
1203 wm8900_write(codec, WM8900_REG_HPCTL1, 0); 1112 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
1204 1113
1205 /* Power down */ 1114 /* Power down */
1206 wm8900_write(codec, WM8900_REG_ADDCTL, 0); 1115 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1207 wm8900_write(codec, WM8900_REG_POWER1, 0); 1116 snd_soc_write(codec, WM8900_REG_POWER1, 0);
1208 wm8900_write(codec, WM8900_REG_POWER2, 0); 1117 snd_soc_write(codec, WM8900_REG_POWER2, 0);
1209 wm8900_write(codec, WM8900_REG_POWER3, 0); 1118 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1210 1119
1211 /* Need to let things settle before stopping the clock 1120 /* Need to let things settle before stopping the clock
1212 * to ensure that restart works, see "Stopping the 1121 * to ensure that restart works, see "Stopping the
1213 * master clock" in the datasheet. */ 1122 * master clock" in the datasheet. */
1214 schedule_timeout_interruptible(msecs_to_jiffies(1)); 1123 schedule_timeout_interruptible(msecs_to_jiffies(1));
1215 wm8900_write(codec, WM8900_REG_POWER2, 1124 snd_soc_write(codec, WM8900_REG_POWER2,
1216 WM8900_REG_POWER2_SYSCLK_ENA); 1125 WM8900_REG_POWER2_SYSCLK_ENA);
1217 break; 1126 break;
1218 } 1127 }
@@ -1275,7 +1184,7 @@ static int wm8900_resume(struct platform_device *pdev)
1275 1184
1276 if (cache) { 1185 if (cache) {
1277 for (i = 0; i < WM8900_MAXREG; i++) 1186 for (i = 0; i < WM8900_MAXREG; i++)
1278 wm8900_write(codec, i, cache[i]); 1187 snd_soc_write(codec, i, cache[i]);
1279 kfree(cache); 1188 kfree(cache);
1280 } else 1189 } else
1281 dev_err(&pdev->dev, "Unable to allocate register cache\n"); 1190 dev_err(&pdev->dev, "Unable to allocate register cache\n");
@@ -1308,16 +1217,20 @@ static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1308 1217
1309 codec->name = "WM8900"; 1218 codec->name = "WM8900";
1310 codec->owner = THIS_MODULE; 1219 codec->owner = THIS_MODULE;
1311 codec->read = wm8900_read;
1312 codec->write = wm8900_write;
1313 codec->dai = &wm8900_dai; 1220 codec->dai = &wm8900_dai;
1314 codec->num_dai = 1; 1221 codec->num_dai = 1;
1315 codec->hw_write = (hw_write_t)i2c_master_send;
1316 codec->control_data = i2c; 1222 codec->control_data = i2c;
1317 codec->set_bias_level = wm8900_set_bias_level; 1223 codec->set_bias_level = wm8900_set_bias_level;
1224 codec->volatile_register = wm8900_volatile_register;
1318 codec->dev = &i2c->dev; 1225 codec->dev = &i2c->dev;
1319 1226
1320 reg = wm8900_read(codec, WM8900_REG_ID); 1227 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1228 if (ret != 0) {
1229 dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret);
1230 goto err;
1231 }
1232
1233 reg = snd_soc_read(codec, WM8900_REG_ID);
1321 if (reg != 0x8900) { 1234 if (reg != 0x8900) {
1322 dev_err(&i2c->dev, "Device is not a WM8900 - ID %x\n", reg); 1235 dev_err(&i2c->dev, "Device is not a WM8900 - ID %x\n", reg);
1323 ret = -ENODEV; 1236 ret = -ENODEV;
@@ -1325,7 +1238,7 @@ static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1325 } 1238 }
1326 1239
1327 /* Read back from the chip */ 1240 /* Read back from the chip */
1328 reg = wm8900_chip_read(codec, WM8900_REG_POWER1); 1241 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1329 reg = (reg >> 12) & 0xf; 1242 reg = (reg >> 12) & 0xf;
1330 dev_info(&i2c->dev, "WM8900 revision %d\n", reg); 1243 dev_info(&i2c->dev, "WM8900 revision %d\n", reg);
1331 1244
@@ -1335,29 +1248,29 @@ static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1335 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1248 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1336 1249
1337 /* Latch the volume update bits */ 1250 /* Latch the volume update bits */
1338 wm8900_write(codec, WM8900_REG_LINVOL, 1251 snd_soc_write(codec, WM8900_REG_LINVOL,
1339 wm8900_read(codec, WM8900_REG_LINVOL) | 0x100); 1252 snd_soc_read(codec, WM8900_REG_LINVOL) | 0x100);
1340 wm8900_write(codec, WM8900_REG_RINVOL, 1253 snd_soc_write(codec, WM8900_REG_RINVOL,
1341 wm8900_read(codec, WM8900_REG_RINVOL) | 0x100); 1254 snd_soc_read(codec, WM8900_REG_RINVOL) | 0x100);
1342 wm8900_write(codec, WM8900_REG_LOUT1CTL, 1255 snd_soc_write(codec, WM8900_REG_LOUT1CTL,
1343 wm8900_read(codec, WM8900_REG_LOUT1CTL) | 0x100); 1256 snd_soc_read(codec, WM8900_REG_LOUT1CTL) | 0x100);
1344 wm8900_write(codec, WM8900_REG_ROUT1CTL, 1257 snd_soc_write(codec, WM8900_REG_ROUT1CTL,
1345 wm8900_read(codec, WM8900_REG_ROUT1CTL) | 0x100); 1258 snd_soc_read(codec, WM8900_REG_ROUT1CTL) | 0x100);
1346 wm8900_write(codec, WM8900_REG_LOUT2CTL, 1259 snd_soc_write(codec, WM8900_REG_LOUT2CTL,
1347 wm8900_read(codec, WM8900_REG_LOUT2CTL) | 0x100); 1260 snd_soc_read(codec, WM8900_REG_LOUT2CTL) | 0x100);
1348 wm8900_write(codec, WM8900_REG_ROUT2CTL, 1261 snd_soc_write(codec, WM8900_REG_ROUT2CTL,
1349 wm8900_read(codec, WM8900_REG_ROUT2CTL) | 0x100); 1262 snd_soc_read(codec, WM8900_REG_ROUT2CTL) | 0x100);
1350 wm8900_write(codec, WM8900_REG_LDAC_DV, 1263 snd_soc_write(codec, WM8900_REG_LDAC_DV,
1351 wm8900_read(codec, WM8900_REG_LDAC_DV) | 0x100); 1264 snd_soc_read(codec, WM8900_REG_LDAC_DV) | 0x100);
1352 wm8900_write(codec, WM8900_REG_RDAC_DV, 1265 snd_soc_write(codec, WM8900_REG_RDAC_DV,
1353 wm8900_read(codec, WM8900_REG_RDAC_DV) | 0x100); 1266 snd_soc_read(codec, WM8900_REG_RDAC_DV) | 0x100);
1354 wm8900_write(codec, WM8900_REG_LADC_DV, 1267 snd_soc_write(codec, WM8900_REG_LADC_DV,
1355 wm8900_read(codec, WM8900_REG_LADC_DV) | 0x100); 1268 snd_soc_read(codec, WM8900_REG_LADC_DV) | 0x100);
1356 wm8900_write(codec, WM8900_REG_RADC_DV, 1269 snd_soc_write(codec, WM8900_REG_RADC_DV,
1357 wm8900_read(codec, WM8900_REG_RADC_DV) | 0x100); 1270 snd_soc_read(codec, WM8900_REG_RADC_DV) | 0x100);
1358 1271
1359 /* Set the DAC and mixer output bias */ 1272 /* Set the DAC and mixer output bias */
1360 wm8900_write(codec, WM8900_REG_OUTBIASCTL, 0x81); 1273 snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
1361 1274
1362 wm8900_dai.dev = &i2c->dev; 1275 wm8900_dai.dev = &i2c->dev;
1363 1276
diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c
index c9baeae3e275..fe1307b500cf 100644
--- a/sound/soc/codecs/wm8903.c
+++ b/sound/soc/codecs/wm8903.c
@@ -225,94 +225,18 @@ struct wm8903_priv {
225 struct snd_pcm_substream *slave_substream; 225 struct snd_pcm_substream *slave_substream;
226}; 226};
227 227
228 228static int wm8903_volatile_register(unsigned int reg)
229static unsigned int wm8903_read_reg_cache(struct snd_soc_codec *codec,
230 unsigned int reg)
231{
232 u16 *cache = codec->reg_cache;
233
234 BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
235
236 return cache[reg];
237}
238
239static unsigned int wm8903_hw_read(struct snd_soc_codec *codec, u8 reg)
240{
241 struct i2c_msg xfer[2];
242 u16 data;
243 int ret;
244 struct i2c_client *client = codec->control_data;
245
246 /* Write register */
247 xfer[0].addr = client->addr;
248 xfer[0].flags = 0;
249 xfer[0].len = 1;
250 xfer[0].buf = &reg;
251
252 /* Read data */
253 xfer[1].addr = client->addr;
254 xfer[1].flags = I2C_M_RD;
255 xfer[1].len = 2;
256 xfer[1].buf = (u8 *)&data;
257
258 ret = i2c_transfer(client->adapter, xfer, 2);
259 if (ret != 2) {
260 pr_err("i2c_transfer returned %d\n", ret);
261 return 0;
262 }
263
264 return (data >> 8) | ((data & 0xff) << 8);
265}
266
267static unsigned int wm8903_read(struct snd_soc_codec *codec,
268 unsigned int reg)
269{ 229{
270 switch (reg) { 230 switch (reg) {
271 case WM8903_SW_RESET_AND_ID: 231 case WM8903_SW_RESET_AND_ID:
272 case WM8903_REVISION_NUMBER: 232 case WM8903_REVISION_NUMBER:
273 case WM8903_INTERRUPT_STATUS_1: 233 case WM8903_INTERRUPT_STATUS_1:
274 case WM8903_WRITE_SEQUENCER_4: 234 case WM8903_WRITE_SEQUENCER_4:
275 return wm8903_hw_read(codec, reg); 235 return 1;
276 236
277 default: 237 default:
278 return wm8903_read_reg_cache(codec, reg);
279 }
280}
281
282static void wm8903_write_reg_cache(struct snd_soc_codec *codec,
283 u16 reg, unsigned int value)
284{
285 u16 *cache = codec->reg_cache;
286
287 BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
288
289 switch (reg) {
290 case WM8903_SW_RESET_AND_ID:
291 case WM8903_REVISION_NUMBER:
292 break;
293
294 default:
295 cache[reg] = value;
296 break;
297 }
298}
299
300static int wm8903_write(struct snd_soc_codec *codec, unsigned int reg,
301 unsigned int value)
302{
303 u8 data[3];
304
305 wm8903_write_reg_cache(codec, reg, value);
306
307 /* Data format is 1 byte of address followed by 2 bytes of data */
308 data[0] = reg;
309 data[1] = (value >> 8) & 0xff;
310 data[2] = value & 0xff;
311
312 if (codec->hw_write(codec->control_data, data, 3) == 2)
313 return 0; 238 return 0;
314 else 239 }
315 return -EIO;
316} 240}
317 241
318static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start) 242static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
@@ -323,13 +247,13 @@ static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
323 BUG_ON(start > 48); 247 BUG_ON(start > 48);
324 248
325 /* Enable the sequencer */ 249 /* Enable the sequencer */
326 reg[0] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_0); 250 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
327 reg[0] |= WM8903_WSEQ_ENA; 251 reg[0] |= WM8903_WSEQ_ENA;
328 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]); 252 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
329 253
330 dev_dbg(&i2c->dev, "Starting sequence at %d\n", start); 254 dev_dbg(&i2c->dev, "Starting sequence at %d\n", start);
331 255
332 wm8903_write(codec, WM8903_WRITE_SEQUENCER_3, 256 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
333 start | WM8903_WSEQ_START); 257 start | WM8903_WSEQ_START);
334 258
335 /* Wait for it to complete. If we have the interrupt wired up then 259 /* Wait for it to complete. If we have the interrupt wired up then
@@ -339,13 +263,13 @@ static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
339 do { 263 do {
340 msleep(10); 264 msleep(10);
341 265
342 reg[4] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_4); 266 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
343 } while (reg[4] & WM8903_WSEQ_BUSY); 267 } while (reg[4] & WM8903_WSEQ_BUSY);
344 268
345 dev_dbg(&i2c->dev, "Sequence complete\n"); 269 dev_dbg(&i2c->dev, "Sequence complete\n");
346 270
347 /* Disable the sequencer again */ 271 /* Disable the sequencer again */
348 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, 272 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
349 reg[0] & ~WM8903_WSEQ_ENA); 273 reg[0] & ~WM8903_WSEQ_ENA);
350 274
351 return 0; 275 return 0;
@@ -357,12 +281,12 @@ static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
357 281
358 /* There really ought to be something better we can do here :/ */ 282 /* There really ought to be something better we can do here :/ */
359 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++) 283 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
360 cache[i] = wm8903_hw_read(codec, i); 284 cache[i] = codec->hw_read(codec, i);
361} 285}
362 286
363static void wm8903_reset(struct snd_soc_codec *codec) 287static void wm8903_reset(struct snd_soc_codec *codec)
364{ 288{
365 wm8903_write(codec, WM8903_SW_RESET_AND_ID, 0); 289 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
366 memcpy(codec->reg_cache, wm8903_reg_defaults, 290 memcpy(codec->reg_cache, wm8903_reg_defaults,
367 sizeof(wm8903_reg_defaults)); 291 sizeof(wm8903_reg_defaults));
368} 292}
@@ -423,52 +347,52 @@ static int wm8903_output_event(struct snd_soc_dapm_widget *w,
423 } 347 }
424 348
425 if (event & SND_SOC_DAPM_PRE_PMU) { 349 if (event & SND_SOC_DAPM_PRE_PMU) {
426 val = wm8903_read(codec, reg); 350 val = snd_soc_read(codec, reg);
427 351
428 /* Short the output */ 352 /* Short the output */
429 val &= ~(WM8903_OUTPUT_SHORT << shift); 353 val &= ~(WM8903_OUTPUT_SHORT << shift);
430 wm8903_write(codec, reg, val); 354 snd_soc_write(codec, reg, val);
431 } 355 }
432 356
433 if (event & SND_SOC_DAPM_POST_PMU) { 357 if (event & SND_SOC_DAPM_POST_PMU) {
434 val = wm8903_read(codec, reg); 358 val = snd_soc_read(codec, reg);
435 359
436 val |= (WM8903_OUTPUT_IN << shift); 360 val |= (WM8903_OUTPUT_IN << shift);
437 wm8903_write(codec, reg, val); 361 snd_soc_write(codec, reg, val);
438 362
439 val |= (WM8903_OUTPUT_INT << shift); 363 val |= (WM8903_OUTPUT_INT << shift);
440 wm8903_write(codec, reg, val); 364 snd_soc_write(codec, reg, val);
441 365
442 /* Turn on the output ENA_OUTP */ 366 /* Turn on the output ENA_OUTP */
443 val |= (WM8903_OUTPUT_OUT << shift); 367 val |= (WM8903_OUTPUT_OUT << shift);
444 wm8903_write(codec, reg, val); 368 snd_soc_write(codec, reg, val);
445 369
446 /* Enable the DC servo */ 370 /* Enable the DC servo */
447 dcs_reg = wm8903_read(codec, WM8903_DC_SERVO_0); 371 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
448 dcs_reg |= dcs_bit; 372 dcs_reg |= dcs_bit;
449 wm8903_write(codec, WM8903_DC_SERVO_0, dcs_reg); 373 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
450 374
451 /* Remove the short */ 375 /* Remove the short */
452 val |= (WM8903_OUTPUT_SHORT << shift); 376 val |= (WM8903_OUTPUT_SHORT << shift);
453 wm8903_write(codec, reg, val); 377 snd_soc_write(codec, reg, val);
454 } 378 }
455 379
456 if (event & SND_SOC_DAPM_PRE_PMD) { 380 if (event & SND_SOC_DAPM_PRE_PMD) {
457 val = wm8903_read(codec, reg); 381 val = snd_soc_read(codec, reg);
458 382
459 /* Short the output */ 383 /* Short the output */
460 val &= ~(WM8903_OUTPUT_SHORT << shift); 384 val &= ~(WM8903_OUTPUT_SHORT << shift);
461 wm8903_write(codec, reg, val); 385 snd_soc_write(codec, reg, val);
462 386
463 /* Disable the DC servo */ 387 /* Disable the DC servo */
464 dcs_reg = wm8903_read(codec, WM8903_DC_SERVO_0); 388 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
465 dcs_reg &= ~dcs_bit; 389 dcs_reg &= ~dcs_bit;
466 wm8903_write(codec, WM8903_DC_SERVO_0, dcs_reg); 390 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
467 391
468 /* Then disable the intermediate and output stages */ 392 /* Then disable the intermediate and output stages */
469 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT | 393 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
470 WM8903_OUTPUT_IN) << shift); 394 WM8903_OUTPUT_IN) << shift);
471 wm8903_write(codec, reg, val); 395 snd_soc_write(codec, reg, val);
472 } 396 }
473 397
474 return 0; 398 return 0;
@@ -492,13 +416,13 @@ static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
492 u16 reg; 416 u16 reg;
493 int ret; 417 int ret;
494 418
495 reg = wm8903_read(codec, WM8903_CLASS_W_0); 419 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
496 420
497 /* Turn it off if we're about to enable bypass */ 421 /* Turn it off if we're about to enable bypass */
498 if (ucontrol->value.integer.value[0]) { 422 if (ucontrol->value.integer.value[0]) {
499 if (wm8903->class_w_users == 0) { 423 if (wm8903->class_w_users == 0) {
500 dev_dbg(&i2c->dev, "Disabling Class W\n"); 424 dev_dbg(&i2c->dev, "Disabling Class W\n");
501 wm8903_write(codec, WM8903_CLASS_W_0, reg & 425 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
502 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V)); 426 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
503 } 427 }
504 wm8903->class_w_users++; 428 wm8903->class_w_users++;
@@ -511,7 +435,7 @@ static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
511 if (!ucontrol->value.integer.value[0]) { 435 if (!ucontrol->value.integer.value[0]) {
512 if (wm8903->class_w_users == 1) { 436 if (wm8903->class_w_users == 1) {
513 dev_dbg(&i2c->dev, "Enabling Class W\n"); 437 dev_dbg(&i2c->dev, "Enabling Class W\n");
514 wm8903_write(codec, WM8903_CLASS_W_0, reg | 438 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
515 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 439 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
516 } 440 }
517 wm8903->class_w_users--; 441 wm8903->class_w_users--;
@@ -1009,55 +933,55 @@ static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1009 switch (level) { 933 switch (level) {
1010 case SND_SOC_BIAS_ON: 934 case SND_SOC_BIAS_ON:
1011 case SND_SOC_BIAS_PREPARE: 935 case SND_SOC_BIAS_PREPARE:
1012 reg = wm8903_read(codec, WM8903_VMID_CONTROL_0); 936 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
1013 reg &= ~(WM8903_VMID_RES_MASK); 937 reg &= ~(WM8903_VMID_RES_MASK);
1014 reg |= WM8903_VMID_RES_50K; 938 reg |= WM8903_VMID_RES_50K;
1015 wm8903_write(codec, WM8903_VMID_CONTROL_0, reg); 939 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
1016 break; 940 break;
1017 941
1018 case SND_SOC_BIAS_STANDBY: 942 case SND_SOC_BIAS_STANDBY:
1019 if (codec->bias_level == SND_SOC_BIAS_OFF) { 943 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1020 wm8903_write(codec, WM8903_CLOCK_RATES_2, 944 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
1021 WM8903_CLK_SYS_ENA); 945 WM8903_CLK_SYS_ENA);
1022 946
1023 /* Change DC servo dither level in startup sequence */ 947 /* Change DC servo dither level in startup sequence */
1024 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11); 948 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
1025 wm8903_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257); 949 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
1026 wm8903_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2); 950 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
1027 951
1028 wm8903_run_sequence(codec, 0); 952 wm8903_run_sequence(codec, 0);
1029 wm8903_sync_reg_cache(codec, codec->reg_cache); 953 wm8903_sync_reg_cache(codec, codec->reg_cache);
1030 954
1031 /* Enable low impedence charge pump output */ 955 /* Enable low impedence charge pump output */
1032 reg = wm8903_read(codec, 956 reg = snd_soc_read(codec,
1033 WM8903_CONTROL_INTERFACE_TEST_1); 957 WM8903_CONTROL_INTERFACE_TEST_1);
1034 wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, 958 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
1035 reg | WM8903_TEST_KEY); 959 reg | WM8903_TEST_KEY);
1036 reg2 = wm8903_read(codec, WM8903_CHARGE_PUMP_TEST_1); 960 reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1);
1037 wm8903_write(codec, WM8903_CHARGE_PUMP_TEST_1, 961 snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1,
1038 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK); 962 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
1039 wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, 963 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
1040 reg); 964 reg);
1041 965
1042 /* By default no bypass paths are enabled so 966 /* By default no bypass paths are enabled so
1043 * enable Class W support. 967 * enable Class W support.
1044 */ 968 */
1045 dev_dbg(&i2c->dev, "Enabling Class W\n"); 969 dev_dbg(&i2c->dev, "Enabling Class W\n");
1046 wm8903_write(codec, WM8903_CLASS_W_0, reg | 970 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
1047 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 971 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
1048 } 972 }
1049 973
1050 reg = wm8903_read(codec, WM8903_VMID_CONTROL_0); 974 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
1051 reg &= ~(WM8903_VMID_RES_MASK); 975 reg &= ~(WM8903_VMID_RES_MASK);
1052 reg |= WM8903_VMID_RES_250K; 976 reg |= WM8903_VMID_RES_250K;
1053 wm8903_write(codec, WM8903_VMID_CONTROL_0, reg); 977 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
1054 break; 978 break;
1055 979
1056 case SND_SOC_BIAS_OFF: 980 case SND_SOC_BIAS_OFF:
1057 wm8903_run_sequence(codec, 32); 981 wm8903_run_sequence(codec, 32);
1058 reg = wm8903_read(codec, WM8903_CLOCK_RATES_2); 982 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
1059 reg &= ~WM8903_CLK_SYS_ENA; 983 reg &= ~WM8903_CLK_SYS_ENA;
1060 wm8903_write(codec, WM8903_CLOCK_RATES_2, reg); 984 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
1061 break; 985 break;
1062 } 986 }
1063 987
@@ -1081,7 +1005,7 @@ static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1081 unsigned int fmt) 1005 unsigned int fmt)
1082{ 1006{
1083 struct snd_soc_codec *codec = codec_dai->codec; 1007 struct snd_soc_codec *codec = codec_dai->codec;
1084 u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1); 1008 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1085 1009
1086 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK | 1010 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1087 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV); 1011 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
@@ -1159,7 +1083,7 @@ static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1159 return -EINVAL; 1083 return -EINVAL;
1160 } 1084 }
1161 1085
1162 wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1086 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1163 1087
1164 return 0; 1088 return 0;
1165} 1089}
@@ -1169,14 +1093,14 @@ static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1169 struct snd_soc_codec *codec = codec_dai->codec; 1093 struct snd_soc_codec *codec = codec_dai->codec;
1170 u16 reg; 1094 u16 reg;
1171 1095
1172 reg = wm8903_read(codec, WM8903_DAC_DIGITAL_1); 1096 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1173 1097
1174 if (mute) 1098 if (mute)
1175 reg |= WM8903_DAC_MUTE; 1099 reg |= WM8903_DAC_MUTE;
1176 else 1100 else
1177 reg &= ~WM8903_DAC_MUTE; 1101 reg &= ~WM8903_DAC_MUTE;
1178 1102
1179 wm8903_write(codec, WM8903_DAC_DIGITAL_1, reg); 1103 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
1180 1104
1181 return 0; 1105 return 0;
1182} 1106}
@@ -1366,12 +1290,12 @@ static int wm8903_hw_params(struct snd_pcm_substream *substream,
1366 int cur_val; 1290 int cur_val;
1367 int clk_sys; 1291 int clk_sys;
1368 1292
1369 u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1); 1293 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1370 u16 aif2 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_2); 1294 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1371 u16 aif3 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_3); 1295 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1372 u16 clock0 = wm8903_read(codec, WM8903_CLOCK_RATES_0); 1296 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1373 u16 clock1 = wm8903_read(codec, WM8903_CLOCK_RATES_1); 1297 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1374 u16 dac_digital1 = wm8903_read(codec, WM8903_DAC_DIGITAL_1); 1298 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1375 1299
1376 if (substream == wm8903->slave_substream) { 1300 if (substream == wm8903->slave_substream) {
1377 dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n"); 1301 dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
@@ -1503,12 +1427,12 @@ static int wm8903_hw_params(struct snd_pcm_substream *substream,
1503 aif2 |= bclk_divs[bclk_div].div; 1427 aif2 |= bclk_divs[bclk_div].div;
1504 aif3 |= bclk / fs; 1428 aif3 |= bclk / fs;
1505 1429
1506 wm8903_write(codec, WM8903_CLOCK_RATES_0, clock0); 1430 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1507 wm8903_write(codec, WM8903_CLOCK_RATES_1, clock1); 1431 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1508 wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1432 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1509 wm8903_write(codec, WM8903_AUDIO_INTERFACE_2, aif2); 1433 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1510 wm8903_write(codec, WM8903_AUDIO_INTERFACE_3, aif3); 1434 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1511 wm8903_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1); 1435 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
1512 1436
1513 return 0; 1437 return 0;
1514} 1438}
@@ -1593,7 +1517,7 @@ static int wm8903_resume(struct platform_device *pdev)
1593 if (tmp_cache) { 1517 if (tmp_cache) {
1594 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++) 1518 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1595 if (tmp_cache[i] != reg_cache[i]) 1519 if (tmp_cache[i] != reg_cache[i])
1596 wm8903_write(codec, i, tmp_cache[i]); 1520 snd_soc_write(codec, i, tmp_cache[i]);
1597 } else { 1521 } else {
1598 dev_err(&i2c->dev, "Failed to allocate temporary cache\n"); 1522 dev_err(&i2c->dev, "Failed to allocate temporary cache\n");
1599 } 1523 }
@@ -1624,9 +1548,6 @@ static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1624 codec->dev = &i2c->dev; 1548 codec->dev = &i2c->dev;
1625 codec->name = "WM8903"; 1549 codec->name = "WM8903";
1626 codec->owner = THIS_MODULE; 1550 codec->owner = THIS_MODULE;
1627 codec->read = wm8903_read;
1628 codec->write = wm8903_write;
1629 codec->hw_write = (hw_write_t)i2c_master_send;
1630 codec->bias_level = SND_SOC_BIAS_OFF; 1551 codec->bias_level = SND_SOC_BIAS_OFF;
1631 codec->set_bias_level = wm8903_set_bias_level; 1552 codec->set_bias_level = wm8903_set_bias_level;
1632 codec->dai = &wm8903_dai; 1553 codec->dai = &wm8903_dai;
@@ -1634,18 +1555,25 @@ static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1634 codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache); 1555 codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache);
1635 codec->reg_cache = &wm8903->reg_cache[0]; 1556 codec->reg_cache = &wm8903->reg_cache[0];
1636 codec->private_data = wm8903; 1557 codec->private_data = wm8903;
1558 codec->volatile_register = wm8903_volatile_register;
1637 1559
1638 i2c_set_clientdata(i2c, codec); 1560 i2c_set_clientdata(i2c, codec);
1639 codec->control_data = i2c; 1561 codec->control_data = i2c;
1640 1562
1641 val = wm8903_hw_read(codec, WM8903_SW_RESET_AND_ID); 1563 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1564 if (ret != 0) {
1565 dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret);
1566 goto err;
1567 }
1568
1569 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
1642 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) { 1570 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
1643 dev_err(&i2c->dev, 1571 dev_err(&i2c->dev,
1644 "Device with ID register %x is not a WM8903\n", val); 1572 "Device with ID register %x is not a WM8903\n", val);
1645 return -ENODEV; 1573 return -ENODEV;
1646 } 1574 }
1647 1575
1648 val = wm8903_read(codec, WM8903_REVISION_NUMBER); 1576 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
1649 dev_info(&i2c->dev, "WM8903 revision %d\n", 1577 dev_info(&i2c->dev, "WM8903 revision %d\n",
1650 val & WM8903_CHIP_REV_MASK); 1578 val & WM8903_CHIP_REV_MASK);
1651 1579
@@ -1655,35 +1583,35 @@ static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1655 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1583 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1656 1584
1657 /* Latch volume update bits */ 1585 /* Latch volume update bits */
1658 val = wm8903_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT); 1586 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
1659 val |= WM8903_ADCVU; 1587 val |= WM8903_ADCVU;
1660 wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val); 1588 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1661 wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val); 1589 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
1662 1590
1663 val = wm8903_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT); 1591 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
1664 val |= WM8903_DACVU; 1592 val |= WM8903_DACVU;
1665 wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val); 1593 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1666 wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val); 1594 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
1667 1595
1668 val = wm8903_read(codec, WM8903_ANALOGUE_OUT1_LEFT); 1596 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
1669 val |= WM8903_HPOUTVU; 1597 val |= WM8903_HPOUTVU;
1670 wm8903_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val); 1598 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1671 wm8903_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val); 1599 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
1672 1600
1673 val = wm8903_read(codec, WM8903_ANALOGUE_OUT2_LEFT); 1601 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
1674 val |= WM8903_LINEOUTVU; 1602 val |= WM8903_LINEOUTVU;
1675 wm8903_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val); 1603 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1676 wm8903_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val); 1604 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
1677 1605
1678 val = wm8903_read(codec, WM8903_ANALOGUE_OUT3_LEFT); 1606 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
1679 val |= WM8903_SPKVU; 1607 val |= WM8903_SPKVU;
1680 wm8903_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val); 1608 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1681 wm8903_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val); 1609 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
1682 1610
1683 /* Enable DAC soft mute by default */ 1611 /* Enable DAC soft mute by default */
1684 val = wm8903_read(codec, WM8903_DAC_DIGITAL_1); 1612 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1685 val |= WM8903_DAC_MUTEMODE; 1613 val |= WM8903_DAC_MUTEMODE;
1686 wm8903_write(codec, WM8903_DAC_DIGITAL_1, val); 1614 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
1687 1615
1688 wm8903_dai.dev = &i2c->dev; 1616 wm8903_dai.dev = &i2c->dev;
1689 wm8903_codec = codec; 1617 wm8903_codec = codec;
diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c
index b69210a77423..da97aae475a2 100644
--- a/sound/soc/codecs/wm8940.c
+++ b/sound/soc/codecs/wm8940.c
@@ -106,50 +106,6 @@ static u16 wm8940_reg_defaults[] = {
106 0x0000, /* Mono Mixer Control */ 106 0x0000, /* Mono Mixer Control */
107}; 107};
108 108
109static inline unsigned int wm8940_read_reg_cache(struct snd_soc_codec *codec,
110 unsigned int reg)
111{
112 u16 *cache = codec->reg_cache;
113
114 if (reg >= ARRAY_SIZE(wm8940_reg_defaults))
115 return -1;
116
117 return cache[reg];
118}
119
120static inline int wm8940_write_reg_cache(struct snd_soc_codec *codec,
121 u16 reg, unsigned int value)
122{
123 u16 *cache = codec->reg_cache;
124
125 if (reg >= ARRAY_SIZE(wm8940_reg_defaults))
126 return -1;
127
128 cache[reg] = value;
129
130 return 0;
131}
132
133static int wm8940_write(struct snd_soc_codec *codec, unsigned int reg,
134 unsigned int value)
135{
136 int ret;
137 u8 data[3] = { reg,
138 (value & 0xff00) >> 8,
139 (value & 0x00ff)
140 };
141
142 wm8940_write_reg_cache(codec, reg, value);
143
144 ret = codec->hw_write(codec->control_data, data, 3);
145
146 if (ret < 0)
147 return ret;
148 else if (ret != 3)
149 return -EIO;
150 return 0;
151}
152
153static const char *wm8940_companding[] = { "Off", "NC", "u-law", "A-law" }; 109static const char *wm8940_companding[] = { "Off", "NC", "u-law", "A-law" };
154static const struct soc_enum wm8940_adc_companding_enum 110static const struct soc_enum wm8940_adc_companding_enum
155= SOC_ENUM_SINGLE(WM8940_COMPANDINGCTL, 1, 4, wm8940_companding); 111= SOC_ENUM_SINGLE(WM8940_COMPANDINGCTL, 1, 4, wm8940_companding);
@@ -348,14 +304,14 @@ error_ret:
348 return ret; 304 return ret;
349} 305}
350 306
351#define wm8940_reset(c) wm8940_write(c, WM8940_SOFTRESET, 0); 307#define wm8940_reset(c) snd_soc_write(c, WM8940_SOFTRESET, 0);
352 308
353static int wm8940_set_dai_fmt(struct snd_soc_dai *codec_dai, 309static int wm8940_set_dai_fmt(struct snd_soc_dai *codec_dai,
354 unsigned int fmt) 310 unsigned int fmt)
355{ 311{
356 struct snd_soc_codec *codec = codec_dai->codec; 312 struct snd_soc_codec *codec = codec_dai->codec;
357 u16 iface = wm8940_read_reg_cache(codec, WM8940_IFACE) & 0xFE67; 313 u16 iface = snd_soc_read(codec, WM8940_IFACE) & 0xFE67;
358 u16 clk = wm8940_read_reg_cache(codec, WM8940_CLOCK) & 0x1fe; 314 u16 clk = snd_soc_read(codec, WM8940_CLOCK) & 0x1fe;
359 315
360 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 316 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
361 case SND_SOC_DAIFMT_CBM_CFM: 317 case SND_SOC_DAIFMT_CBM_CFM:
@@ -366,7 +322,7 @@ static int wm8940_set_dai_fmt(struct snd_soc_dai *codec_dai,
366 default: 322 default:
367 return -EINVAL; 323 return -EINVAL;
368 } 324 }
369 wm8940_write(codec, WM8940_CLOCK, clk); 325 snd_soc_write(codec, WM8940_CLOCK, clk);
370 326
371 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 327 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
372 case SND_SOC_DAIFMT_I2S: 328 case SND_SOC_DAIFMT_I2S:
@@ -399,7 +355,7 @@ static int wm8940_set_dai_fmt(struct snd_soc_dai *codec_dai,
399 break; 355 break;
400 } 356 }
401 357
402 wm8940_write(codec, WM8940_IFACE, iface); 358 snd_soc_write(codec, WM8940_IFACE, iface);
403 359
404 return 0; 360 return 0;
405} 361}
@@ -411,9 +367,9 @@ static int wm8940_i2s_hw_params(struct snd_pcm_substream *substream,
411 struct snd_soc_pcm_runtime *rtd = substream->private_data; 367 struct snd_soc_pcm_runtime *rtd = substream->private_data;
412 struct snd_soc_device *socdev = rtd->socdev; 368 struct snd_soc_device *socdev = rtd->socdev;
413 struct snd_soc_codec *codec = socdev->card->codec; 369 struct snd_soc_codec *codec = socdev->card->codec;
414 u16 iface = wm8940_read_reg_cache(codec, WM8940_IFACE) & 0xFD9F; 370 u16 iface = snd_soc_read(codec, WM8940_IFACE) & 0xFD9F;
415 u16 addcntrl = wm8940_read_reg_cache(codec, WM8940_ADDCNTRL) & 0xFFF1; 371 u16 addcntrl = snd_soc_read(codec, WM8940_ADDCNTRL) & 0xFFF1;
416 u16 companding = wm8940_read_reg_cache(codec, 372 u16 companding = snd_soc_read(codec,
417 WM8940_COMPANDINGCTL) & 0xFFDF; 373 WM8940_COMPANDINGCTL) & 0xFFDF;
418 int ret; 374 int ret;
419 375
@@ -442,7 +398,7 @@ static int wm8940_i2s_hw_params(struct snd_pcm_substream *substream,
442 case SNDRV_PCM_RATE_48000: 398 case SNDRV_PCM_RATE_48000:
443 break; 399 break;
444 } 400 }
445 ret = wm8940_write(codec, WM8940_ADDCNTRL, addcntrl); 401 ret = snd_soc_write(codec, WM8940_ADDCNTRL, addcntrl);
446 if (ret) 402 if (ret)
447 goto error_ret; 403 goto error_ret;
448 404
@@ -462,10 +418,10 @@ static int wm8940_i2s_hw_params(struct snd_pcm_substream *substream,
462 iface |= (3 << 5); 418 iface |= (3 << 5);
463 break; 419 break;
464 } 420 }
465 ret = wm8940_write(codec, WM8940_COMPANDINGCTL, companding); 421 ret = snd_soc_write(codec, WM8940_COMPANDINGCTL, companding);
466 if (ret) 422 if (ret)
467 goto error_ret; 423 goto error_ret;
468 ret = wm8940_write(codec, WM8940_IFACE, iface); 424 ret = snd_soc_write(codec, WM8940_IFACE, iface);
469 425
470error_ret: 426error_ret:
471 return ret; 427 return ret;
@@ -474,19 +430,19 @@ error_ret:
474static int wm8940_mute(struct snd_soc_dai *dai, int mute) 430static int wm8940_mute(struct snd_soc_dai *dai, int mute)
475{ 431{
476 struct snd_soc_codec *codec = dai->codec; 432 struct snd_soc_codec *codec = dai->codec;
477 u16 mute_reg = wm8940_read_reg_cache(codec, WM8940_DAC) & 0xffbf; 433 u16 mute_reg = snd_soc_read(codec, WM8940_DAC) & 0xffbf;
478 434
479 if (mute) 435 if (mute)
480 mute_reg |= 0x40; 436 mute_reg |= 0x40;
481 437
482 return wm8940_write(codec, WM8940_DAC, mute_reg); 438 return snd_soc_write(codec, WM8940_DAC, mute_reg);
483} 439}
484 440
485static int wm8940_set_bias_level(struct snd_soc_codec *codec, 441static int wm8940_set_bias_level(struct snd_soc_codec *codec,
486 enum snd_soc_bias_level level) 442 enum snd_soc_bias_level level)
487{ 443{
488 u16 val; 444 u16 val;
489 u16 pwr_reg = wm8940_read_reg_cache(codec, WM8940_POWER1) & 0x1F0; 445 u16 pwr_reg = snd_soc_read(codec, WM8940_POWER1) & 0x1F0;
490 int ret = 0; 446 int ret = 0;
491 447
492 switch (level) { 448 switch (level) {
@@ -494,26 +450,26 @@ static int wm8940_set_bias_level(struct snd_soc_codec *codec,
494 /* ensure bufioen and biasen */ 450 /* ensure bufioen and biasen */
495 pwr_reg |= (1 << 2) | (1 << 3); 451 pwr_reg |= (1 << 2) | (1 << 3);
496 /* Enable thermal shutdown */ 452 /* Enable thermal shutdown */
497 val = wm8940_read_reg_cache(codec, WM8940_OUTPUTCTL); 453 val = snd_soc_read(codec, WM8940_OUTPUTCTL);
498 ret = wm8940_write(codec, WM8940_OUTPUTCTL, val | 0x2); 454 ret = snd_soc_write(codec, WM8940_OUTPUTCTL, val | 0x2);
499 if (ret) 455 if (ret)
500 break; 456 break;
501 /* set vmid to 75k */ 457 /* set vmid to 75k */
502 ret = wm8940_write(codec, WM8940_POWER1, pwr_reg | 0x1); 458 ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg | 0x1);
503 break; 459 break;
504 case SND_SOC_BIAS_PREPARE: 460 case SND_SOC_BIAS_PREPARE:
505 /* ensure bufioen and biasen */ 461 /* ensure bufioen and biasen */
506 pwr_reg |= (1 << 2) | (1 << 3); 462 pwr_reg |= (1 << 2) | (1 << 3);
507 ret = wm8940_write(codec, WM8940_POWER1, pwr_reg | 0x1); 463 ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg | 0x1);
508 break; 464 break;
509 case SND_SOC_BIAS_STANDBY: 465 case SND_SOC_BIAS_STANDBY:
510 /* ensure bufioen and biasen */ 466 /* ensure bufioen and biasen */
511 pwr_reg |= (1 << 2) | (1 << 3); 467 pwr_reg |= (1 << 2) | (1 << 3);
512 /* set vmid to 300k for standby */ 468 /* set vmid to 300k for standby */
513 ret = wm8940_write(codec, WM8940_POWER1, pwr_reg | 0x2); 469 ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg | 0x2);
514 break; 470 break;
515 case SND_SOC_BIAS_OFF: 471 case SND_SOC_BIAS_OFF:
516 ret = wm8940_write(codec, WM8940_POWER1, pwr_reg); 472 ret = snd_soc_write(codec, WM8940_POWER1, pwr_reg);
517 break; 473 break;
518 } 474 }
519 475
@@ -587,36 +543,36 @@ static int wm8940_set_dai_pll(struct snd_soc_dai *codec_dai,
587 u16 reg; 543 u16 reg;
588 544
589 /* Turn off PLL */ 545 /* Turn off PLL */
590 reg = wm8940_read_reg_cache(codec, WM8940_POWER1); 546 reg = snd_soc_read(codec, WM8940_POWER1);
591 wm8940_write(codec, WM8940_POWER1, reg & 0x1df); 547 snd_soc_write(codec, WM8940_POWER1, reg & 0x1df);
592 548
593 if (freq_in == 0 || freq_out == 0) { 549 if (freq_in == 0 || freq_out == 0) {
594 /* Clock CODEC directly from MCLK */ 550 /* Clock CODEC directly from MCLK */
595 reg = wm8940_read_reg_cache(codec, WM8940_CLOCK); 551 reg = snd_soc_read(codec, WM8940_CLOCK);
596 wm8940_write(codec, WM8940_CLOCK, reg & 0x0ff); 552 snd_soc_write(codec, WM8940_CLOCK, reg & 0x0ff);
597 /* Pll power down */ 553 /* Pll power down */
598 wm8940_write(codec, WM8940_PLLN, (1 << 7)); 554 snd_soc_write(codec, WM8940_PLLN, (1 << 7));
599 return 0; 555 return 0;
600 } 556 }
601 557
602 /* Pll is followed by a frequency divide by 4 */ 558 /* Pll is followed by a frequency divide by 4 */
603 pll_factors(freq_out*4, freq_in); 559 pll_factors(freq_out*4, freq_in);
604 if (pll_div.k) 560 if (pll_div.k)
605 wm8940_write(codec, WM8940_PLLN, 561 snd_soc_write(codec, WM8940_PLLN,
606 (pll_div.pre_scale << 4) | pll_div.n | (1 << 6)); 562 (pll_div.pre_scale << 4) | pll_div.n | (1 << 6));
607 else /* No factional component */ 563 else /* No factional component */
608 wm8940_write(codec, WM8940_PLLN, 564 snd_soc_write(codec, WM8940_PLLN,
609 (pll_div.pre_scale << 4) | pll_div.n); 565 (pll_div.pre_scale << 4) | pll_div.n);
610 wm8940_write(codec, WM8940_PLLK1, pll_div.k >> 18); 566 snd_soc_write(codec, WM8940_PLLK1, pll_div.k >> 18);
611 wm8940_write(codec, WM8940_PLLK2, (pll_div.k >> 9) & 0x1ff); 567 snd_soc_write(codec, WM8940_PLLK2, (pll_div.k >> 9) & 0x1ff);
612 wm8940_write(codec, WM8940_PLLK3, pll_div.k & 0x1ff); 568 snd_soc_write(codec, WM8940_PLLK3, pll_div.k & 0x1ff);
613 /* Enable the PLL */ 569 /* Enable the PLL */
614 reg = wm8940_read_reg_cache(codec, WM8940_POWER1); 570 reg = snd_soc_read(codec, WM8940_POWER1);
615 wm8940_write(codec, WM8940_POWER1, reg | 0x020); 571 snd_soc_write(codec, WM8940_POWER1, reg | 0x020);
616 572
617 /* Run CODEC from PLL instead of MCLK */ 573 /* Run CODEC from PLL instead of MCLK */
618 reg = wm8940_read_reg_cache(codec, WM8940_CLOCK); 574 reg = snd_soc_read(codec, WM8940_CLOCK);
619 wm8940_write(codec, WM8940_CLOCK, reg | 0x100); 575 snd_soc_write(codec, WM8940_CLOCK, reg | 0x100);
620 576
621 return 0; 577 return 0;
622} 578}
@@ -648,16 +604,16 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
648 604
649 switch (div_id) { 605 switch (div_id) {
650 case WM8940_BCLKDIV: 606 case WM8940_BCLKDIV:
651 reg = wm8940_read_reg_cache(codec, WM8940_CLOCK) & 0xFFEF3; 607 reg = snd_soc_read(codec, WM8940_CLOCK) & 0xFFEF3;
652 ret = wm8940_write(codec, WM8940_CLOCK, reg | (div << 2)); 608 ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 2));
653 break; 609 break;
654 case WM8940_MCLKDIV: 610 case WM8940_MCLKDIV:
655 reg = wm8940_read_reg_cache(codec, WM8940_CLOCK) & 0xFF1F; 611 reg = snd_soc_read(codec, WM8940_CLOCK) & 0xFF1F;
656 ret = wm8940_write(codec, WM8940_CLOCK, reg | (div << 5)); 612 ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 5));
657 break; 613 break;
658 case WM8940_OPCLKDIV: 614 case WM8940_OPCLKDIV:
659 reg = wm8940_read_reg_cache(codec, WM8940_ADDCNTRL) & 0xFFCF; 615 reg = snd_soc_read(codec, WM8940_ADDCNTRL) & 0xFFCF;
660 ret = wm8940_write(codec, WM8940_ADDCNTRL, reg | (div << 4)); 616 ret = snd_soc_write(codec, WM8940_ADDCNTRL, reg | (div << 4));
661 break; 617 break;
662 } 618 }
663 return ret; 619 return ret;
@@ -808,7 +764,8 @@ struct snd_soc_codec_device soc_codec_dev_wm8940 = {
808}; 764};
809EXPORT_SYMBOL_GPL(soc_codec_dev_wm8940); 765EXPORT_SYMBOL_GPL(soc_codec_dev_wm8940);
810 766
811static int wm8940_register(struct wm8940_priv *wm8940) 767static int wm8940_register(struct wm8940_priv *wm8940,
768 enum snd_soc_control_type control)
812{ 769{
813 struct wm8940_setup_data *pdata = wm8940->codec.dev->platform_data; 770 struct wm8940_setup_data *pdata = wm8940->codec.dev->platform_data;
814 struct snd_soc_codec *codec = &wm8940->codec; 771 struct snd_soc_codec *codec = &wm8940->codec;
@@ -825,8 +782,6 @@ static int wm8940_register(struct wm8940_priv *wm8940)
825 codec->private_data = wm8940; 782 codec->private_data = wm8940;
826 codec->name = "WM8940"; 783 codec->name = "WM8940";
827 codec->owner = THIS_MODULE; 784 codec->owner = THIS_MODULE;
828 codec->read = wm8940_read_reg_cache;
829 codec->write = wm8940_write;
830 codec->bias_level = SND_SOC_BIAS_OFF; 785 codec->bias_level = SND_SOC_BIAS_OFF;
831 codec->set_bias_level = wm8940_set_bias_level; 786 codec->set_bias_level = wm8940_set_bias_level;
832 codec->dai = &wm8940_dai; 787 codec->dai = &wm8940_dai;
@@ -834,6 +789,12 @@ static int wm8940_register(struct wm8940_priv *wm8940)
834 codec->reg_cache_size = ARRAY_SIZE(wm8940_reg_defaults); 789 codec->reg_cache_size = ARRAY_SIZE(wm8940_reg_defaults);
835 codec->reg_cache = &wm8940->reg_cache; 790 codec->reg_cache = &wm8940->reg_cache;
836 791
792 ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
793 if (ret == 0) {
794 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
795 return ret;
796 }
797
837 memcpy(codec->reg_cache, wm8940_reg_defaults, 798 memcpy(codec->reg_cache, wm8940_reg_defaults,
838 sizeof(wm8940_reg_defaults)); 799 sizeof(wm8940_reg_defaults));
839 800
@@ -847,15 +808,15 @@ static int wm8940_register(struct wm8940_priv *wm8940)
847 808
848 wm8940_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 809 wm8940_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
849 810
850 ret = wm8940_write(codec, WM8940_POWER1, 0x180); 811 ret = snd_soc_write(codec, WM8940_POWER1, 0x180);
851 if (ret < 0) 812 if (ret < 0)
852 return ret; 813 return ret;
853 814
854 if (!pdata) 815 if (!pdata)
855 dev_warn(codec->dev, "No platform data supplied\n"); 816 dev_warn(codec->dev, "No platform data supplied\n");
856 else { 817 else {
857 reg = wm8940_read_reg_cache(codec, WM8940_OUTPUTCTL); 818 reg = snd_soc_read(codec, WM8940_OUTPUTCTL);
858 ret = wm8940_write(codec, WM8940_OUTPUTCTL, reg | pdata->vroi); 819 ret = snd_soc_write(codec, WM8940_OUTPUTCTL, reg | pdata->vroi);
859 if (ret < 0) 820 if (ret < 0)
860 return ret; 821 return ret;
861 } 822 }
@@ -904,7 +865,7 @@ static int wm8940_i2c_probe(struct i2c_client *i2c,
904 codec->control_data = i2c; 865 codec->control_data = i2c;
905 codec->dev = &i2c->dev; 866 codec->dev = &i2c->dev;
906 867
907 return wm8940_register(wm8940); 868 return wm8940_register(wm8940, SND_SOC_I2C);
908} 869}
909 870
910static int __devexit wm8940_i2c_remove(struct i2c_client *client) 871static int __devexit wm8940_i2c_remove(struct i2c_client *client)
diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c
index d1769e6c0c44..f59703be61c8 100644
--- a/sound/soc/codecs/wm8960.c
+++ b/sound/soc/codecs/wm8960.c
@@ -69,61 +69,7 @@ struct wm8960_priv {
69 struct snd_soc_codec codec; 69 struct snd_soc_codec codec;
70}; 70};
71 71
72/* 72#define wm8960_reset(c) snd_soc_write(c, WM8960_RESET, 0)
73 * read wm8960 register cache
74 */
75static inline unsigned int wm8960_read_reg_cache(struct snd_soc_codec *codec,
76 unsigned int reg)
77{
78 u16 *cache = codec->reg_cache;
79 if (reg == WM8960_RESET)
80 return 0;
81 if (reg >= WM8960_CACHEREGNUM)
82 return -1;
83 return cache[reg];
84}
85
86/*
87 * write wm8960 register cache
88 */
89static inline void wm8960_write_reg_cache(struct snd_soc_codec *codec,
90 u16 reg, unsigned int value)
91{
92 u16 *cache = codec->reg_cache;
93 if (reg >= WM8960_CACHEREGNUM)
94 return;
95 cache[reg] = value;
96}
97
98static inline unsigned int wm8960_read(struct snd_soc_codec *codec,
99 unsigned int reg)
100{
101 return wm8960_read_reg_cache(codec, reg);
102}
103
104/*
105 * write to the WM8960 register space
106 */
107static int wm8960_write(struct snd_soc_codec *codec, unsigned int reg,
108 unsigned int value)
109{
110 u8 data[2];
111
112 /* data is
113 * D15..D9 WM8960 register offset
114 * D8...D0 register data
115 */
116 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
117 data[1] = value & 0x00ff;
118
119 wm8960_write_reg_cache(codec, reg, value);
120 if (codec->hw_write(codec->control_data, data, 2) == 2)
121 return 0;
122 else
123 return -EIO;
124}
125
126#define wm8960_reset(c) wm8960_write(c, WM8960_RESET, 0)
127 73
128/* enumerated controls */ 74/* enumerated controls */
129static const char *wm8960_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"}; 75static const char *wm8960_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
@@ -420,7 +366,7 @@ static int wm8960_set_dai_fmt(struct snd_soc_dai *codec_dai,
420 } 366 }
421 367
422 /* set iface */ 368 /* set iface */
423 wm8960_write(codec, WM8960_IFACE1, iface); 369 snd_soc_write(codec, WM8960_IFACE1, iface);
424 return 0; 370 return 0;
425} 371}
426 372
@@ -431,7 +377,7 @@ static int wm8960_hw_params(struct snd_pcm_substream *substream,
431 struct snd_soc_pcm_runtime *rtd = substream->private_data; 377 struct snd_soc_pcm_runtime *rtd = substream->private_data;
432 struct snd_soc_device *socdev = rtd->socdev; 378 struct snd_soc_device *socdev = rtd->socdev;
433 struct snd_soc_codec *codec = socdev->card->codec; 379 struct snd_soc_codec *codec = socdev->card->codec;
434 u16 iface = wm8960_read(codec, WM8960_IFACE1) & 0xfff3; 380 u16 iface = snd_soc_read(codec, WM8960_IFACE1) & 0xfff3;
435 381
436 /* bit size */ 382 /* bit size */
437 switch (params_format(params)) { 383 switch (params_format(params)) {
@@ -446,19 +392,19 @@ static int wm8960_hw_params(struct snd_pcm_substream *substream,
446 } 392 }
447 393
448 /* set iface */ 394 /* set iface */
449 wm8960_write(codec, WM8960_IFACE1, iface); 395 snd_soc_write(codec, WM8960_IFACE1, iface);
450 return 0; 396 return 0;
451} 397}
452 398
453static int wm8960_mute(struct snd_soc_dai *dai, int mute) 399static int wm8960_mute(struct snd_soc_dai *dai, int mute)
454{ 400{
455 struct snd_soc_codec *codec = dai->codec; 401 struct snd_soc_codec *codec = dai->codec;
456 u16 mute_reg = wm8960_read(codec, WM8960_DACCTL1) & 0xfff7; 402 u16 mute_reg = snd_soc_read(codec, WM8960_DACCTL1) & 0xfff7;
457 403
458 if (mute) 404 if (mute)
459 wm8960_write(codec, WM8960_DACCTL1, mute_reg | 0x8); 405 snd_soc_write(codec, WM8960_DACCTL1, mute_reg | 0x8);
460 else 406 else
461 wm8960_write(codec, WM8960_DACCTL1, mute_reg); 407 snd_soc_write(codec, WM8960_DACCTL1, mute_reg);
462 return 0; 408 return 0;
463} 409}
464 410
@@ -474,16 +420,16 @@ static int wm8960_set_bias_level(struct snd_soc_codec *codec,
474 420
475 case SND_SOC_BIAS_PREPARE: 421 case SND_SOC_BIAS_PREPARE:
476 /* Set VMID to 2x50k */ 422 /* Set VMID to 2x50k */
477 reg = wm8960_read(codec, WM8960_POWER1); 423 reg = snd_soc_read(codec, WM8960_POWER1);
478 reg &= ~0x180; 424 reg &= ~0x180;
479 reg |= 0x80; 425 reg |= 0x80;
480 wm8960_write(codec, WM8960_POWER1, reg); 426 snd_soc_write(codec, WM8960_POWER1, reg);
481 break; 427 break;
482 428
483 case SND_SOC_BIAS_STANDBY: 429 case SND_SOC_BIAS_STANDBY:
484 if (codec->bias_level == SND_SOC_BIAS_OFF) { 430 if (codec->bias_level == SND_SOC_BIAS_OFF) {
485 /* Enable anti-pop features */ 431 /* Enable anti-pop features */
486 wm8960_write(codec, WM8960_APOP1, 432 snd_soc_write(codec, WM8960_APOP1,
487 WM8960_POBCTRL | WM8960_SOFT_ST | 433 WM8960_POBCTRL | WM8960_SOFT_ST |
488 WM8960_BUFDCOPEN | WM8960_BUFIOEN); 434 WM8960_BUFDCOPEN | WM8960_BUFIOEN);
489 435
@@ -491,43 +437,43 @@ static int wm8960_set_bias_level(struct snd_soc_codec *codec,
491 reg = WM8960_DISOP; 437 reg = WM8960_DISOP;
492 if (pdata) 438 if (pdata)
493 reg |= pdata->dres << 4; 439 reg |= pdata->dres << 4;
494 wm8960_write(codec, WM8960_APOP2, reg); 440 snd_soc_write(codec, WM8960_APOP2, reg);
495 441
496 msleep(400); 442 msleep(400);
497 443
498 wm8960_write(codec, WM8960_APOP2, 0); 444 snd_soc_write(codec, WM8960_APOP2, 0);
499 445
500 /* Enable & ramp VMID at 2x50k */ 446 /* Enable & ramp VMID at 2x50k */
501 reg = wm8960_read(codec, WM8960_POWER1); 447 reg = snd_soc_read(codec, WM8960_POWER1);
502 reg |= 0x80; 448 reg |= 0x80;
503 wm8960_write(codec, WM8960_POWER1, reg); 449 snd_soc_write(codec, WM8960_POWER1, reg);
504 msleep(100); 450 msleep(100);
505 451
506 /* Enable VREF */ 452 /* Enable VREF */
507 wm8960_write(codec, WM8960_POWER1, reg | WM8960_VREF); 453 snd_soc_write(codec, WM8960_POWER1, reg | WM8960_VREF);
508 454
509 /* Disable anti-pop features */ 455 /* Disable anti-pop features */
510 wm8960_write(codec, WM8960_APOP1, WM8960_BUFIOEN); 456 snd_soc_write(codec, WM8960_APOP1, WM8960_BUFIOEN);
511 } 457 }
512 458
513 /* Set VMID to 2x250k */ 459 /* Set VMID to 2x250k */
514 reg = wm8960_read(codec, WM8960_POWER1); 460 reg = snd_soc_read(codec, WM8960_POWER1);
515 reg &= ~0x180; 461 reg &= ~0x180;
516 reg |= 0x100; 462 reg |= 0x100;
517 wm8960_write(codec, WM8960_POWER1, reg); 463 snd_soc_write(codec, WM8960_POWER1, reg);
518 break; 464 break;
519 465
520 case SND_SOC_BIAS_OFF: 466 case SND_SOC_BIAS_OFF:
521 /* Enable anti-pop features */ 467 /* Enable anti-pop features */
522 wm8960_write(codec, WM8960_APOP1, 468 snd_soc_write(codec, WM8960_APOP1,
523 WM8960_POBCTRL | WM8960_SOFT_ST | 469 WM8960_POBCTRL | WM8960_SOFT_ST |
524 WM8960_BUFDCOPEN | WM8960_BUFIOEN); 470 WM8960_BUFDCOPEN | WM8960_BUFIOEN);
525 471
526 /* Disable VMID and VREF, let them discharge */ 472 /* Disable VMID and VREF, let them discharge */
527 wm8960_write(codec, WM8960_POWER1, 0); 473 snd_soc_write(codec, WM8960_POWER1, 0);
528 msleep(600); 474 msleep(600);
529 475
530 wm8960_write(codec, WM8960_APOP1, 0); 476 snd_soc_write(codec, WM8960_APOP1, 0);
531 break; 477 break;
532 } 478 }
533 479
@@ -610,33 +556,33 @@ static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai,
610 556
611 /* Disable the PLL: even if we are changing the frequency the 557 /* Disable the PLL: even if we are changing the frequency the
612 * PLL needs to be disabled while we do so. */ 558 * PLL needs to be disabled while we do so. */
613 wm8960_write(codec, WM8960_CLOCK1, 559 snd_soc_write(codec, WM8960_CLOCK1,
614 wm8960_read(codec, WM8960_CLOCK1) & ~1); 560 snd_soc_read(codec, WM8960_CLOCK1) & ~1);
615 wm8960_write(codec, WM8960_POWER2, 561 snd_soc_write(codec, WM8960_POWER2,
616 wm8960_read(codec, WM8960_POWER2) & ~1); 562 snd_soc_read(codec, WM8960_POWER2) & ~1);
617 563
618 if (!freq_in || !freq_out) 564 if (!freq_in || !freq_out)
619 return 0; 565 return 0;
620 566
621 reg = wm8960_read(codec, WM8960_PLL1) & ~0x3f; 567 reg = snd_soc_read(codec, WM8960_PLL1) & ~0x3f;
622 reg |= pll_div.pre_div << 4; 568 reg |= pll_div.pre_div << 4;
623 reg |= pll_div.n; 569 reg |= pll_div.n;
624 570
625 if (pll_div.k) { 571 if (pll_div.k) {
626 reg |= 0x20; 572 reg |= 0x20;
627 573
628 wm8960_write(codec, WM8960_PLL2, (pll_div.k >> 18) & 0x3f); 574 snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 18) & 0x3f);
629 wm8960_write(codec, WM8960_PLL3, (pll_div.k >> 9) & 0x1ff); 575 snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 9) & 0x1ff);
630 wm8960_write(codec, WM8960_PLL4, pll_div.k & 0x1ff); 576 snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0x1ff);
631 } 577 }
632 wm8960_write(codec, WM8960_PLL1, reg); 578 snd_soc_write(codec, WM8960_PLL1, reg);
633 579
634 /* Turn it on */ 580 /* Turn it on */
635 wm8960_write(codec, WM8960_POWER2, 581 snd_soc_write(codec, WM8960_POWER2,
636 wm8960_read(codec, WM8960_POWER2) | 1); 582 snd_soc_read(codec, WM8960_POWER2) | 1);
637 msleep(250); 583 msleep(250);
638 wm8960_write(codec, WM8960_CLOCK1, 584 snd_soc_write(codec, WM8960_CLOCK1,
639 wm8960_read(codec, WM8960_CLOCK1) | 1); 585 snd_soc_read(codec, WM8960_CLOCK1) | 1);
640 586
641 return 0; 587 return 0;
642} 588}
@@ -649,28 +595,28 @@ static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
649 595
650 switch (div_id) { 596 switch (div_id) {
651 case WM8960_SYSCLKSEL: 597 case WM8960_SYSCLKSEL:
652 reg = wm8960_read(codec, WM8960_CLOCK1) & 0x1fe; 598 reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1fe;
653 wm8960_write(codec, WM8960_CLOCK1, reg | div); 599 snd_soc_write(codec, WM8960_CLOCK1, reg | div);
654 break; 600 break;
655 case WM8960_SYSCLKDIV: 601 case WM8960_SYSCLKDIV:
656 reg = wm8960_read(codec, WM8960_CLOCK1) & 0x1f9; 602 reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1f9;
657 wm8960_write(codec, WM8960_CLOCK1, reg | div); 603 snd_soc_write(codec, WM8960_CLOCK1, reg | div);
658 break; 604 break;
659 case WM8960_DACDIV: 605 case WM8960_DACDIV:
660 reg = wm8960_read(codec, WM8960_CLOCK1) & 0x1c7; 606 reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1c7;
661 wm8960_write(codec, WM8960_CLOCK1, reg | div); 607 snd_soc_write(codec, WM8960_CLOCK1, reg | div);
662 break; 608 break;
663 case WM8960_OPCLKDIV: 609 case WM8960_OPCLKDIV:
664 reg = wm8960_read(codec, WM8960_PLL1) & 0x03f; 610 reg = snd_soc_read(codec, WM8960_PLL1) & 0x03f;
665 wm8960_write(codec, WM8960_PLL1, reg | div); 611 snd_soc_write(codec, WM8960_PLL1, reg | div);
666 break; 612 break;
667 case WM8960_DCLKDIV: 613 case WM8960_DCLKDIV:
668 reg = wm8960_read(codec, WM8960_CLOCK2) & 0x03f; 614 reg = snd_soc_read(codec, WM8960_CLOCK2) & 0x03f;
669 wm8960_write(codec, WM8960_CLOCK2, reg | div); 615 snd_soc_write(codec, WM8960_CLOCK2, reg | div);
670 break; 616 break;
671 case WM8960_TOCLKSEL: 617 case WM8960_TOCLKSEL:
672 reg = wm8960_read(codec, WM8960_ADDCTL1) & 0x1fd; 618 reg = snd_soc_read(codec, WM8960_ADDCTL1) & 0x1fd;
673 wm8960_write(codec, WM8960_ADDCTL1, reg | div); 619 snd_soc_write(codec, WM8960_ADDCTL1, reg | div);
674 break; 620 break;
675 default: 621 default:
676 return -EINVAL; 622 return -EINVAL;
@@ -801,7 +747,8 @@ struct snd_soc_codec_device soc_codec_dev_wm8960 = {
801}; 747};
802EXPORT_SYMBOL_GPL(soc_codec_dev_wm8960); 748EXPORT_SYMBOL_GPL(soc_codec_dev_wm8960);
803 749
804static int wm8960_register(struct wm8960_priv *wm8960) 750static int wm8960_register(struct wm8960_priv *wm8960,
751 enum snd_soc_control_type control)
805{ 752{
806 struct wm8960_data *pdata = wm8960->codec.dev->platform_data; 753 struct wm8960_data *pdata = wm8960->codec.dev->platform_data;
807 struct snd_soc_codec *codec = &wm8960->codec; 754 struct snd_soc_codec *codec = &wm8960->codec;
@@ -830,8 +777,6 @@ static int wm8960_register(struct wm8960_priv *wm8960)
830 codec->private_data = wm8960; 777 codec->private_data = wm8960;
831 codec->name = "WM8960"; 778 codec->name = "WM8960";
832 codec->owner = THIS_MODULE; 779 codec->owner = THIS_MODULE;
833 codec->read = wm8960_read_reg_cache;
834 codec->write = wm8960_write;
835 codec->bias_level = SND_SOC_BIAS_OFF; 780 codec->bias_level = SND_SOC_BIAS_OFF;
836 codec->set_bias_level = wm8960_set_bias_level; 781 codec->set_bias_level = wm8960_set_bias_level;
837 codec->dai = &wm8960_dai; 782 codec->dai = &wm8960_dai;
@@ -841,6 +786,12 @@ static int wm8960_register(struct wm8960_priv *wm8960)
841 786
842 memcpy(codec->reg_cache, wm8960_reg, sizeof(wm8960_reg)); 787 memcpy(codec->reg_cache, wm8960_reg, sizeof(wm8960_reg));
843 788
789 ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
790 if (ret < 0) {
791 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
792 goto err;
793 }
794
844 ret = wm8960_reset(codec); 795 ret = wm8960_reset(codec);
845 if (ret < 0) { 796 if (ret < 0) {
846 dev_err(codec->dev, "Failed to issue reset\n"); 797 dev_err(codec->dev, "Failed to issue reset\n");
@@ -852,26 +803,26 @@ static int wm8960_register(struct wm8960_priv *wm8960)
852 wm8960_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 803 wm8960_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
853 804
854 /* Latch the update bits */ 805 /* Latch the update bits */
855 reg = wm8960_read(codec, WM8960_LINVOL); 806 reg = snd_soc_read(codec, WM8960_LINVOL);
856 wm8960_write(codec, WM8960_LINVOL, reg | 0x100); 807 snd_soc_write(codec, WM8960_LINVOL, reg | 0x100);
857 reg = wm8960_read(codec, WM8960_RINVOL); 808 reg = snd_soc_read(codec, WM8960_RINVOL);
858 wm8960_write(codec, WM8960_RINVOL, reg | 0x100); 809 snd_soc_write(codec, WM8960_RINVOL, reg | 0x100);
859 reg = wm8960_read(codec, WM8960_LADC); 810 reg = snd_soc_read(codec, WM8960_LADC);
860 wm8960_write(codec, WM8960_LADC, reg | 0x100); 811 snd_soc_write(codec, WM8960_LADC, reg | 0x100);
861 reg = wm8960_read(codec, WM8960_RADC); 812 reg = snd_soc_read(codec, WM8960_RADC);
862 wm8960_write(codec, WM8960_RADC, reg | 0x100); 813 snd_soc_write(codec, WM8960_RADC, reg | 0x100);
863 reg = wm8960_read(codec, WM8960_LDAC); 814 reg = snd_soc_read(codec, WM8960_LDAC);
864 wm8960_write(codec, WM8960_LDAC, reg | 0x100); 815 snd_soc_write(codec, WM8960_LDAC, reg | 0x100);
865 reg = wm8960_read(codec, WM8960_RDAC); 816 reg = snd_soc_read(codec, WM8960_RDAC);
866 wm8960_write(codec, WM8960_RDAC, reg | 0x100); 817 snd_soc_write(codec, WM8960_RDAC, reg | 0x100);
867 reg = wm8960_read(codec, WM8960_LOUT1); 818 reg = snd_soc_read(codec, WM8960_LOUT1);
868 wm8960_write(codec, WM8960_LOUT1, reg | 0x100); 819 snd_soc_write(codec, WM8960_LOUT1, reg | 0x100);
869 reg = wm8960_read(codec, WM8960_ROUT1); 820 reg = snd_soc_read(codec, WM8960_ROUT1);
870 wm8960_write(codec, WM8960_ROUT1, reg | 0x100); 821 snd_soc_write(codec, WM8960_ROUT1, reg | 0x100);
871 reg = wm8960_read(codec, WM8960_LOUT2); 822 reg = snd_soc_read(codec, WM8960_LOUT2);
872 wm8960_write(codec, WM8960_LOUT2, reg | 0x100); 823 snd_soc_write(codec, WM8960_LOUT2, reg | 0x100);
873 reg = wm8960_read(codec, WM8960_ROUT2); 824 reg = snd_soc_read(codec, WM8960_ROUT2);
874 wm8960_write(codec, WM8960_ROUT2, reg | 0x100); 825 snd_soc_write(codec, WM8960_ROUT2, reg | 0x100);
875 826
876 wm8960_codec = codec; 827 wm8960_codec = codec;
877 828
@@ -916,14 +867,13 @@ static __devinit int wm8960_i2c_probe(struct i2c_client *i2c,
916 return -ENOMEM; 867 return -ENOMEM;
917 868
918 codec = &wm8960->codec; 869 codec = &wm8960->codec;
919 codec->hw_write = (hw_write_t)i2c_master_send;
920 870
921 i2c_set_clientdata(i2c, wm8960); 871 i2c_set_clientdata(i2c, wm8960);
922 codec->control_data = i2c; 872 codec->control_data = i2c;
923 873
924 codec->dev = &i2c->dev; 874 codec->dev = &i2c->dev;
925 875
926 return wm8960_register(wm8960); 876 return wm8960_register(wm8960, SND_SOC_I2C);
927} 877}
928 878
929static __devexit int wm8960_i2c_remove(struct i2c_client *client) 879static __devexit int wm8960_i2c_remove(struct i2c_client *client)
diff --git a/sound/soc/codecs/wm8961.c b/sound/soc/codecs/wm8961.c
index bd1af92a122f..503032085899 100644
--- a/sound/soc/codecs/wm8961.c
+++ b/sound/soc/codecs/wm8961.c
@@ -292,9 +292,10 @@ struct wm8961_priv {
292 u16 reg_cache[WM8961_MAX_REGISTER]; 292 u16 reg_cache[WM8961_MAX_REGISTER];
293}; 293};
294 294
295static int wm8961_reg_is_volatile(int reg) 295static int wm8961_volatile_register(unsigned int reg)
296{ 296{
297 switch (reg) { 297 switch (reg) {
298 case WM8961_SOFTWARE_RESET:
298 case WM8961_WRITE_SEQUENCER_7: 299 case WM8961_WRITE_SEQUENCER_7:
299 case WM8961_DC_SERVO_1: 300 case WM8961_DC_SERVO_1:
300 return 1; 301 return 1;
@@ -304,76 +305,9 @@ static int wm8961_reg_is_volatile(int reg)
304 } 305 }
305} 306}
306 307
307static unsigned int wm8961_read_reg_cache(struct snd_soc_codec *codec,
308 unsigned int reg)
309{
310 u16 *cache = codec->reg_cache;
311 BUG_ON(reg > WM8961_MAX_REGISTER);
312 return cache[reg];
313}
314
315static unsigned int wm8961_read_hw(struct snd_soc_codec *codec, u8 reg)
316{
317 struct i2c_msg xfer[2];
318 u16 data;
319 int ret;
320 struct i2c_client *client = codec->control_data;
321
322 BUG_ON(reg > WM8961_MAX_REGISTER);
323
324 /* Write register */
325 xfer[0].addr = client->addr;
326 xfer[0].flags = 0;
327 xfer[0].len = 1;
328 xfer[0].buf = &reg;
329
330 /* Read data */
331 xfer[1].addr = client->addr;
332 xfer[1].flags = I2C_M_RD;
333 xfer[1].len = 2;
334 xfer[1].buf = (u8 *)&data;
335
336 ret = i2c_transfer(client->adapter, xfer, 2);
337 if (ret != 2) {
338 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
339 return 0;
340 }
341
342 return (data >> 8) | ((data & 0xff) << 8);
343}
344
345static unsigned int wm8961_read(struct snd_soc_codec *codec, unsigned int reg)
346{
347 if (wm8961_reg_is_volatile(reg))
348 return wm8961_read_hw(codec, reg);
349 else
350 return wm8961_read_reg_cache(codec, reg);
351}
352
353static int wm8961_write(struct snd_soc_codec *codec, unsigned int reg,
354 unsigned int value)
355{
356 u16 *cache = codec->reg_cache;
357 u8 data[3];
358
359 BUG_ON(reg > WM8961_MAX_REGISTER);
360
361 if (!wm8961_reg_is_volatile(reg))
362 cache[reg] = value;
363
364 data[0] = reg;
365 data[1] = value >> 8;
366 data[2] = value & 0x00ff;
367
368 if (codec->hw_write(codec->control_data, data, 3) == 3)
369 return 0;
370 else
371 return -EIO;
372}
373
374static int wm8961_reset(struct snd_soc_codec *codec) 308static int wm8961_reset(struct snd_soc_codec *codec)
375{ 309{
376 return wm8961_write(codec, WM8961_SOFTWARE_RESET, 0); 310 return snd_soc_write(codec, WM8961_SOFTWARE_RESET, 0);
377} 311}
378 312
379/* 313/*
@@ -384,33 +318,33 @@ static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
384 struct snd_kcontrol *kcontrol, int event) 318 struct snd_kcontrol *kcontrol, int event)
385{ 319{
386 struct snd_soc_codec *codec = w->codec; 320 struct snd_soc_codec *codec = w->codec;
387 u16 hp_reg = wm8961_read(codec, WM8961_ANALOGUE_HP_0); 321 u16 hp_reg = snd_soc_read(codec, WM8961_ANALOGUE_HP_0);
388 u16 cp_reg = wm8961_read(codec, WM8961_CHARGE_PUMP_1); 322 u16 cp_reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_1);
389 u16 pwr_reg = wm8961_read(codec, WM8961_PWR_MGMT_2); 323 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
390 u16 dcs_reg = wm8961_read(codec, WM8961_DC_SERVO_1); 324 u16 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
391 int timeout = 500; 325 int timeout = 500;
392 326
393 if (event & SND_SOC_DAPM_POST_PMU) { 327 if (event & SND_SOC_DAPM_POST_PMU) {
394 /* Make sure the output is shorted */ 328 /* Make sure the output is shorted */
395 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT); 329 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
396 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 330 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
397 331
398 /* Enable the charge pump */ 332 /* Enable the charge pump */
399 cp_reg |= WM8961_CP_ENA; 333 cp_reg |= WM8961_CP_ENA;
400 wm8961_write(codec, WM8961_CHARGE_PUMP_1, cp_reg); 334 snd_soc_write(codec, WM8961_CHARGE_PUMP_1, cp_reg);
401 mdelay(5); 335 mdelay(5);
402 336
403 /* Enable the PGA */ 337 /* Enable the PGA */
404 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA; 338 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;
405 wm8961_write(codec, WM8961_PWR_MGMT_2, pwr_reg); 339 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
406 340
407 /* Enable the amplifier */ 341 /* Enable the amplifier */
408 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA; 342 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;
409 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 343 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
410 344
411 /* Second stage enable */ 345 /* Second stage enable */
412 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY; 346 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;
413 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 347 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
414 348
415 /* Enable the DC servo & trigger startup */ 349 /* Enable the DC servo & trigger startup */
416 dcs_reg |= 350 dcs_reg |=
@@ -418,10 +352,10 @@ static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
418 WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL; 352 WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;
419 dev_dbg(codec->dev, "Enabling DC servo\n"); 353 dev_dbg(codec->dev, "Enabling DC servo\n");
420 354
421 wm8961_write(codec, WM8961_DC_SERVO_1, dcs_reg); 355 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
422 do { 356 do {
423 msleep(1); 357 msleep(1);
424 dcs_reg = wm8961_read(codec, WM8961_DC_SERVO_1); 358 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
425 } while (--timeout && 359 } while (--timeout &&
426 dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR | 360 dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
427 WM8961_DCS_TRIG_STARTUP_HPL)); 361 WM8961_DCS_TRIG_STARTUP_HPL));
@@ -433,39 +367,39 @@ static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
433 367
434 /* Enable the output stage */ 368 /* Enable the output stage */
435 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP; 369 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;
436 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 370 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
437 371
438 /* Remove the short on the output stage */ 372 /* Remove the short on the output stage */
439 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT; 373 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;
440 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 374 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
441 } 375 }
442 376
443 if (event & SND_SOC_DAPM_PRE_PMD) { 377 if (event & SND_SOC_DAPM_PRE_PMD) {
444 /* Short the output */ 378 /* Short the output */
445 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT); 379 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
446 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 380 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
447 381
448 /* Disable the output stage */ 382 /* Disable the output stage */
449 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP); 383 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);
450 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 384 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
451 385
452 /* Disable DC offset cancellation */ 386 /* Disable DC offset cancellation */
453 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR | 387 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |
454 WM8961_DCS_ENA_CHAN_HPL); 388 WM8961_DCS_ENA_CHAN_HPL);
455 wm8961_write(codec, WM8961_DC_SERVO_1, dcs_reg); 389 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
456 390
457 /* Finish up */ 391 /* Finish up */
458 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA | 392 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |
459 WM8961_HPL_ENA_DLY | WM8961_HPL_ENA); 393 WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);
460 wm8961_write(codec, WM8961_ANALOGUE_HP_0, hp_reg); 394 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
461 395
462 /* Disable the PGA */ 396 /* Disable the PGA */
463 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA); 397 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);
464 wm8961_write(codec, WM8961_PWR_MGMT_2, pwr_reg); 398 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
465 399
466 /* Disable the charge pump */ 400 /* Disable the charge pump */
467 dev_dbg(codec->dev, "Disabling charge pump\n"); 401 dev_dbg(codec->dev, "Disabling charge pump\n");
468 wm8961_write(codec, WM8961_CHARGE_PUMP_1, 402 snd_soc_write(codec, WM8961_CHARGE_PUMP_1,
469 cp_reg & ~WM8961_CP_ENA); 403 cp_reg & ~WM8961_CP_ENA);
470 } 404 }
471 405
@@ -476,27 +410,27 @@ static int wm8961_spk_event(struct snd_soc_dapm_widget *w,
476 struct snd_kcontrol *kcontrol, int event) 410 struct snd_kcontrol *kcontrol, int event)
477{ 411{
478 struct snd_soc_codec *codec = w->codec; 412 struct snd_soc_codec *codec = w->codec;
479 u16 pwr_reg = wm8961_read(codec, WM8961_PWR_MGMT_2); 413 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
480 u16 spk_reg = wm8961_read(codec, WM8961_CLASS_D_CONTROL_1); 414 u16 spk_reg = snd_soc_read(codec, WM8961_CLASS_D_CONTROL_1);
481 415
482 if (event & SND_SOC_DAPM_POST_PMU) { 416 if (event & SND_SOC_DAPM_POST_PMU) {
483 /* Enable the PGA */ 417 /* Enable the PGA */
484 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA; 418 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;
485 wm8961_write(codec, WM8961_PWR_MGMT_2, pwr_reg); 419 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
486 420
487 /* Enable the amplifier */ 421 /* Enable the amplifier */
488 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA; 422 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;
489 wm8961_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg); 423 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
490 } 424 }
491 425
492 if (event & SND_SOC_DAPM_PRE_PMD) { 426 if (event & SND_SOC_DAPM_PRE_PMD) {
493 /* Enable the amplifier */ 427 /* Enable the amplifier */
494 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA); 428 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);
495 wm8961_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg); 429 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
496 430
497 /* Enable the PGA */ 431 /* Enable the PGA */
498 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA); 432 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);
499 wm8961_write(codec, WM8961_PWR_MGMT_2, pwr_reg); 433 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
500 } 434 }
501 435
502 return 0; 436 return 0;
@@ -714,10 +648,10 @@ static int wm8961_hw_params(struct snd_pcm_substream *substream,
714 abs(wm8961_srate[best].rate - fs)) 648 abs(wm8961_srate[best].rate - fs))
715 best = i; 649 best = i;
716 } 650 }
717 reg = wm8961_read(codec, WM8961_ADDITIONAL_CONTROL_3); 651 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_3);
718 reg &= ~WM8961_SAMPLE_RATE_MASK; 652 reg &= ~WM8961_SAMPLE_RATE_MASK;
719 reg |= wm8961_srate[best].val; 653 reg |= wm8961_srate[best].val;
720 wm8961_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg); 654 snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg);
721 dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n", 655 dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n",
722 wm8961_srate[best].rate, fs); 656 wm8961_srate[best].rate, fs);
723 657
@@ -747,12 +681,12 @@ static int wm8961_hw_params(struct snd_pcm_substream *substream,
747 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs, 681 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
748 wm8961->sysclk / fs); 682 wm8961->sysclk / fs);
749 683
750 reg = wm8961_read(codec, WM8961_CLOCKING_4); 684 reg = snd_soc_read(codec, WM8961_CLOCKING_4);
751 reg &= ~WM8961_CLK_SYS_RATE_MASK; 685 reg &= ~WM8961_CLK_SYS_RATE_MASK;
752 reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT; 686 reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
753 wm8961_write(codec, WM8961_CLOCKING_4, reg); 687 snd_soc_write(codec, WM8961_CLOCKING_4, reg);
754 688
755 reg = wm8961_read(codec, WM8961_AUDIO_INTERFACE_0); 689 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
756 reg &= ~WM8961_WL_MASK; 690 reg &= ~WM8961_WL_MASK;
757 switch (params_format(params)) { 691 switch (params_format(params)) {
758 case SNDRV_PCM_FORMAT_S16_LE: 692 case SNDRV_PCM_FORMAT_S16_LE:
@@ -769,15 +703,15 @@ static int wm8961_hw_params(struct snd_pcm_substream *substream,
769 default: 703 default:
770 return -EINVAL; 704 return -EINVAL;
771 } 705 }
772 wm8961_write(codec, WM8961_AUDIO_INTERFACE_0, reg); 706 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, reg);
773 707
774 /* Sloping stop-band filter is recommended for <= 24kHz */ 708 /* Sloping stop-band filter is recommended for <= 24kHz */
775 reg = wm8961_read(codec, WM8961_ADC_DAC_CONTROL_2); 709 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
776 if (fs <= 24000) 710 if (fs <= 24000)
777 reg |= WM8961_DACSLOPE; 711 reg |= WM8961_DACSLOPE;
778 else 712 else
779 reg &= WM8961_DACSLOPE; 713 reg &= WM8961_DACSLOPE;
780 wm8961_write(codec, WM8961_ADC_DAC_CONTROL_2, reg); 714 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
781 715
782 return 0; 716 return 0;
783} 717}
@@ -788,7 +722,7 @@ static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
788{ 722{
789 struct snd_soc_codec *codec = dai->codec; 723 struct snd_soc_codec *codec = dai->codec;
790 struct wm8961_priv *wm8961 = codec->private_data; 724 struct wm8961_priv *wm8961 = codec->private_data;
791 u16 reg = wm8961_read(codec, WM8961_CLOCKING1); 725 u16 reg = snd_soc_read(codec, WM8961_CLOCKING1);
792 726
793 if (freq > 33000000) { 727 if (freq > 33000000) {
794 dev_err(codec->dev, "MCLK must be <33MHz\n"); 728 dev_err(codec->dev, "MCLK must be <33MHz\n");
@@ -804,7 +738,7 @@ static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
804 reg &= WM8961_MCLKDIV; 738 reg &= WM8961_MCLKDIV;
805 } 739 }
806 740
807 wm8961_write(codec, WM8961_CLOCKING1, reg); 741 snd_soc_write(codec, WM8961_CLOCKING1, reg);
808 742
809 wm8961->sysclk = freq; 743 wm8961->sysclk = freq;
810 744
@@ -814,7 +748,7 @@ static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
814static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 748static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
815{ 749{
816 struct snd_soc_codec *codec = dai->codec; 750 struct snd_soc_codec *codec = dai->codec;
817 u16 aif = wm8961_read(codec, WM8961_AUDIO_INTERFACE_0); 751 u16 aif = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
818 752
819 aif &= ~(WM8961_BCLKINV | WM8961_LRP | 753 aif &= ~(WM8961_BCLKINV | WM8961_LRP |
820 WM8961_MS | WM8961_FORMAT_MASK); 754 WM8961_MS | WM8961_FORMAT_MASK);
@@ -874,26 +808,26 @@ static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
874 return -EINVAL; 808 return -EINVAL;
875 } 809 }
876 810
877 return wm8961_write(codec, WM8961_AUDIO_INTERFACE_0, aif); 811 return snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, aif);
878} 812}
879 813
880static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate) 814static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
881{ 815{
882 struct snd_soc_codec *codec = dai->codec; 816 struct snd_soc_codec *codec = dai->codec;
883 u16 reg = wm8961_read(codec, WM8961_ADDITIONAL_CONTROL_2); 817 u16 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_2);
884 818
885 if (tristate) 819 if (tristate)
886 reg |= WM8961_TRIS; 820 reg |= WM8961_TRIS;
887 else 821 else
888 reg &= ~WM8961_TRIS; 822 reg &= ~WM8961_TRIS;
889 823
890 return wm8961_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg); 824 return snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg);
891} 825}
892 826
893static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute) 827static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute)
894{ 828{
895 struct snd_soc_codec *codec = dai->codec; 829 struct snd_soc_codec *codec = dai->codec;
896 u16 reg = wm8961_read(codec, WM8961_ADC_DAC_CONTROL_1); 830 u16 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_1);
897 831
898 if (mute) 832 if (mute)
899 reg |= WM8961_DACMU; 833 reg |= WM8961_DACMU;
@@ -902,7 +836,7 @@ static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute)
902 836
903 msleep(17); 837 msleep(17);
904 838
905 return wm8961_write(codec, WM8961_ADC_DAC_CONTROL_1, reg); 839 return snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_1, reg);
906} 840}
907 841
908static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) 842static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
@@ -912,17 +846,17 @@ static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
912 846
913 switch (div_id) { 847 switch (div_id) {
914 case WM8961_BCLK: 848 case WM8961_BCLK:
915 reg = wm8961_read(codec, WM8961_CLOCKING2); 849 reg = snd_soc_read(codec, WM8961_CLOCKING2);
916 reg &= ~WM8961_BCLKDIV_MASK; 850 reg &= ~WM8961_BCLKDIV_MASK;
917 reg |= div; 851 reg |= div;
918 wm8961_write(codec, WM8961_CLOCKING2, reg); 852 snd_soc_write(codec, WM8961_CLOCKING2, reg);
919 break; 853 break;
920 854
921 case WM8961_LRCLK: 855 case WM8961_LRCLK:
922 reg = wm8961_read(codec, WM8961_AUDIO_INTERFACE_2); 856 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_2);
923 reg &= ~WM8961_LRCLK_RATE_MASK; 857 reg &= ~WM8961_LRCLK_RATE_MASK;
924 reg |= div; 858 reg |= div;
925 wm8961_write(codec, WM8961_AUDIO_INTERFACE_2, reg); 859 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_2, reg);
926 break; 860 break;
927 861
928 default: 862 default:
@@ -949,34 +883,34 @@ static int wm8961_set_bias_level(struct snd_soc_codec *codec,
949 case SND_SOC_BIAS_PREPARE: 883 case SND_SOC_BIAS_PREPARE:
950 if (codec->bias_level == SND_SOC_BIAS_STANDBY) { 884 if (codec->bias_level == SND_SOC_BIAS_STANDBY) {
951 /* Enable bias generation */ 885 /* Enable bias generation */
952 reg = wm8961_read(codec, WM8961_ANTI_POP); 886 reg = snd_soc_read(codec, WM8961_ANTI_POP);
953 reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN; 887 reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
954 wm8961_write(codec, WM8961_ANTI_POP, reg); 888 snd_soc_write(codec, WM8961_ANTI_POP, reg);
955 889
956 /* VMID=2*50k, VREF */ 890 /* VMID=2*50k, VREF */
957 reg = wm8961_read(codec, WM8961_PWR_MGMT_1); 891 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
958 reg &= ~WM8961_VMIDSEL_MASK; 892 reg &= ~WM8961_VMIDSEL_MASK;
959 reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF; 893 reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
960 wm8961_write(codec, WM8961_PWR_MGMT_1, reg); 894 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
961 } 895 }
962 break; 896 break;
963 897
964 case SND_SOC_BIAS_STANDBY: 898 case SND_SOC_BIAS_STANDBY:
965 if (codec->bias_level == SND_SOC_BIAS_PREPARE) { 899 if (codec->bias_level == SND_SOC_BIAS_PREPARE) {
966 /* VREF off */ 900 /* VREF off */
967 reg = wm8961_read(codec, WM8961_PWR_MGMT_1); 901 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
968 reg &= ~WM8961_VREF; 902 reg &= ~WM8961_VREF;
969 wm8961_write(codec, WM8961_PWR_MGMT_1, reg); 903 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
970 904
971 /* Bias generation off */ 905 /* Bias generation off */
972 reg = wm8961_read(codec, WM8961_ANTI_POP); 906 reg = snd_soc_read(codec, WM8961_ANTI_POP);
973 reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN); 907 reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
974 wm8961_write(codec, WM8961_ANTI_POP, reg); 908 snd_soc_write(codec, WM8961_ANTI_POP, reg);
975 909
976 /* VMID off */ 910 /* VMID off */
977 reg = wm8961_read(codec, WM8961_PWR_MGMT_1); 911 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
978 reg &= ~WM8961_VMIDSEL_MASK; 912 reg &= ~WM8961_VMIDSEL_MASK;
979 wm8961_write(codec, WM8961_PWR_MGMT_1, reg); 913 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
980 } 914 }
981 break; 915 break;
982 916
@@ -1101,7 +1035,7 @@ static int wm8961_resume(struct platform_device *pdev)
1101 if (i == WM8961_SOFTWARE_RESET) 1035 if (i == WM8961_SOFTWARE_RESET)
1102 continue; 1036 continue;
1103 1037
1104 wm8961_write(codec, i, reg_cache[i]); 1038 snd_soc_write(codec, i, reg_cache[i]);
1105 } 1039 }
1106 1040
1107 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1041 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
@@ -1140,26 +1074,32 @@ static int wm8961_register(struct wm8961_priv *wm8961)
1140 codec->private_data = wm8961; 1074 codec->private_data = wm8961;
1141 codec->name = "WM8961"; 1075 codec->name = "WM8961";
1142 codec->owner = THIS_MODULE; 1076 codec->owner = THIS_MODULE;
1143 codec->read = wm8961_read;
1144 codec->write = wm8961_write;
1145 codec->dai = &wm8961_dai; 1077 codec->dai = &wm8961_dai;
1146 codec->num_dai = 1; 1078 codec->num_dai = 1;
1147 codec->reg_cache_size = ARRAY_SIZE(wm8961->reg_cache); 1079 codec->reg_cache_size = ARRAY_SIZE(wm8961->reg_cache);
1148 codec->reg_cache = &wm8961->reg_cache; 1080 codec->reg_cache = &wm8961->reg_cache;
1149 codec->bias_level = SND_SOC_BIAS_OFF; 1081 codec->bias_level = SND_SOC_BIAS_OFF;
1150 codec->set_bias_level = wm8961_set_bias_level; 1082 codec->set_bias_level = wm8961_set_bias_level;
1083 codec->volatile_register = wm8961_volatile_register;
1151 1084
1152 memcpy(codec->reg_cache, wm8961_reg_defaults, 1085 memcpy(codec->reg_cache, wm8961_reg_defaults,
1153 sizeof(wm8961_reg_defaults)); 1086 sizeof(wm8961_reg_defaults));
1154 1087
1155 reg = wm8961_read_hw(codec, WM8961_SOFTWARE_RESET); 1088 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1089 if (ret != 0) {
1090 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1091 goto err;
1092 }
1093
1094 reg = snd_soc_read(codec, WM8961_SOFTWARE_RESET);
1156 if (reg != 0x1801) { 1095 if (reg != 0x1801) {
1157 dev_err(codec->dev, "Device is not a WM8961: ID=0x%x\n", reg); 1096 dev_err(codec->dev, "Device is not a WM8961: ID=0x%x\n", reg);
1158 ret = -EINVAL; 1097 ret = -EINVAL;
1159 goto err; 1098 goto err;
1160 } 1099 }
1161 1100
1162 reg = wm8961_read_hw(codec, WM8961_RIGHT_INPUT_VOLUME); 1101 /* This isn't volatile - readback doesn't correspond to write */
1102 reg = codec->hw_read(codec, WM8961_RIGHT_INPUT_VOLUME);
1163 dev_info(codec->dev, "WM8961 family %d revision %c\n", 1103 dev_info(codec->dev, "WM8961 family %d revision %c\n",
1164 (reg & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT, 1104 (reg & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
1165 ((reg & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT) 1105 ((reg & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
@@ -1172,37 +1112,37 @@ static int wm8961_register(struct wm8961_priv *wm8961)
1172 } 1112 }
1173 1113
1174 /* Enable class W */ 1114 /* Enable class W */
1175 reg = wm8961_read(codec, WM8961_CHARGE_PUMP_B); 1115 reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_B);
1176 reg |= WM8961_CP_DYN_PWR_MASK; 1116 reg |= WM8961_CP_DYN_PWR_MASK;
1177 wm8961_write(codec, WM8961_CHARGE_PUMP_B, reg); 1117 snd_soc_write(codec, WM8961_CHARGE_PUMP_B, reg);
1178 1118
1179 /* Latch volume update bits (right channel only, we always 1119 /* Latch volume update bits (right channel only, we always
1180 * write both out) and default ZC on. */ 1120 * write both out) and default ZC on. */
1181 reg = wm8961_read(codec, WM8961_ROUT1_VOLUME); 1121 reg = snd_soc_read(codec, WM8961_ROUT1_VOLUME);
1182 wm8961_write(codec, WM8961_ROUT1_VOLUME, 1122 snd_soc_write(codec, WM8961_ROUT1_VOLUME,
1183 reg | WM8961_LO1ZC | WM8961_OUT1VU); 1123 reg | WM8961_LO1ZC | WM8961_OUT1VU);
1184 wm8961_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC); 1124 snd_soc_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
1185 reg = wm8961_read(codec, WM8961_ROUT2_VOLUME); 1125 reg = snd_soc_read(codec, WM8961_ROUT2_VOLUME);
1186 wm8961_write(codec, WM8961_ROUT2_VOLUME, 1126 snd_soc_write(codec, WM8961_ROUT2_VOLUME,
1187 reg | WM8961_SPKRZC | WM8961_SPKVU); 1127 reg | WM8961_SPKRZC | WM8961_SPKVU);
1188 wm8961_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC); 1128 snd_soc_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
1189 1129
1190 reg = wm8961_read(codec, WM8961_RIGHT_ADC_VOLUME); 1130 reg = snd_soc_read(codec, WM8961_RIGHT_ADC_VOLUME);
1191 wm8961_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU); 1131 snd_soc_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
1192 reg = wm8961_read(codec, WM8961_RIGHT_INPUT_VOLUME); 1132 reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
1193 wm8961_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU); 1133 snd_soc_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
1194 1134
1195 /* Use soft mute by default */ 1135 /* Use soft mute by default */
1196 reg = wm8961_read(codec, WM8961_ADC_DAC_CONTROL_2); 1136 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
1197 reg |= WM8961_DACSMM; 1137 reg |= WM8961_DACSMM;
1198 wm8961_write(codec, WM8961_ADC_DAC_CONTROL_2, reg); 1138 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
1199 1139
1200 /* Use automatic clocking mode by default; for now this is all 1140 /* Use automatic clocking mode by default; for now this is all
1201 * we support. 1141 * we support.
1202 */ 1142 */
1203 reg = wm8961_read(codec, WM8961_CLOCKING_3); 1143 reg = snd_soc_read(codec, WM8961_CLOCKING_3);
1204 reg &= ~WM8961_MANUAL_MODE; 1144 reg &= ~WM8961_MANUAL_MODE;
1205 wm8961_write(codec, WM8961_CLOCKING_3, reg); 1145 snd_soc_write(codec, WM8961_CLOCKING_3, reg);
1206 1146
1207 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1147 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1208 1148
@@ -1250,7 +1190,6 @@ static __devinit int wm8961_i2c_probe(struct i2c_client *i2c,
1250 return -ENOMEM; 1190 return -ENOMEM;
1251 1191
1252 codec = &wm8961->codec; 1192 codec = &wm8961->codec;
1253 codec->hw_write = (hw_write_t)i2c_master_send;
1254 1193
1255 i2c_set_clientdata(i2c, wm8961); 1194 i2c_set_clientdata(i2c, wm8961);
1256 codec->control_data = i2c; 1195 codec->control_data = i2c;
diff --git a/sound/soc/codecs/wm8971.c b/sound/soc/codecs/wm8971.c
index 032dca22dbd3..d66efb0546ea 100644
--- a/sound/soc/codecs/wm8971.c
+++ b/sound/soc/codecs/wm8971.c
@@ -59,44 +59,7 @@ static const u16 wm8971_reg[] = {
59 0x0079, 0x0079, 0x0079, /* 40 */ 59 0x0079, 0x0079, 0x0079, /* 40 */
60}; 60};
61 61
62static inline unsigned int wm8971_read_reg_cache(struct snd_soc_codec *codec, 62#define wm8971_reset(c) snd_soc_write(c, WM8971_RESET, 0)
63 unsigned int reg)
64{
65 u16 *cache = codec->reg_cache;
66 if (reg < WM8971_REG_COUNT)
67 return cache[reg];
68
69 return -1;
70}
71
72static inline void wm8971_write_reg_cache(struct snd_soc_codec *codec,
73 unsigned int reg, unsigned int value)
74{
75 u16 *cache = codec->reg_cache;
76 if (reg < WM8971_REG_COUNT)
77 cache[reg] = value;
78}
79
80static int wm8971_write(struct snd_soc_codec *codec, unsigned int reg,
81 unsigned int value)
82{
83 u8 data[2];
84
85 /* data is
86 * D15..D9 WM8753 register offset
87 * D8...D0 register data
88 */
89 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
90 data[1] = value & 0x00ff;
91
92 wm8971_write_reg_cache (codec, reg, value);
93 if (codec->hw_write(codec->control_data, data, 2) == 2)
94 return 0;
95 else
96 return -EIO;
97}
98
99#define wm8971_reset(c) wm8971_write(c, WM8971_RESET, 0)
100 63
101/* WM8971 Controls */ 64/* WM8971 Controls */
102static const char *wm8971_bass[] = { "Linear Control", "Adaptive Boost" }; 65static const char *wm8971_bass[] = { "Linear Control", "Adaptive Boost" };
@@ -521,7 +484,7 @@ static int wm8971_set_dai_fmt(struct snd_soc_dai *codec_dai,
521 return -EINVAL; 484 return -EINVAL;
522 } 485 }
523 486
524 wm8971_write(codec, WM8971_IFACE, iface); 487 snd_soc_write(codec, WM8971_IFACE, iface);
525 return 0; 488 return 0;
526} 489}
527 490
@@ -533,8 +496,8 @@ static int wm8971_pcm_hw_params(struct snd_pcm_substream *substream,
533 struct snd_soc_device *socdev = rtd->socdev; 496 struct snd_soc_device *socdev = rtd->socdev;
534 struct snd_soc_codec *codec = socdev->card->codec; 497 struct snd_soc_codec *codec = socdev->card->codec;
535 struct wm8971_priv *wm8971 = codec->private_data; 498 struct wm8971_priv *wm8971 = codec->private_data;
536 u16 iface = wm8971_read_reg_cache(codec, WM8971_IFACE) & 0x1f3; 499 u16 iface = snd_soc_read(codec, WM8971_IFACE) & 0x1f3;
537 u16 srate = wm8971_read_reg_cache(codec, WM8971_SRATE) & 0x1c0; 500 u16 srate = snd_soc_read(codec, WM8971_SRATE) & 0x1c0;
538 int coeff = get_coeff(wm8971->sysclk, params_rate(params)); 501 int coeff = get_coeff(wm8971->sysclk, params_rate(params));
539 502
540 /* bit size */ 503 /* bit size */
@@ -553,9 +516,9 @@ static int wm8971_pcm_hw_params(struct snd_pcm_substream *substream,
553 } 516 }
554 517
555 /* set iface & srate */ 518 /* set iface & srate */
556 wm8971_write(codec, WM8971_IFACE, iface); 519 snd_soc_write(codec, WM8971_IFACE, iface);
557 if (coeff >= 0) 520 if (coeff >= 0)
558 wm8971_write(codec, WM8971_SRATE, srate | 521 snd_soc_write(codec, WM8971_SRATE, srate |
559 (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb); 522 (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
560 523
561 return 0; 524 return 0;
@@ -564,33 +527,33 @@ static int wm8971_pcm_hw_params(struct snd_pcm_substream *substream,
564static int wm8971_mute(struct snd_soc_dai *dai, int mute) 527static int wm8971_mute(struct snd_soc_dai *dai, int mute)
565{ 528{
566 struct snd_soc_codec *codec = dai->codec; 529 struct snd_soc_codec *codec = dai->codec;
567 u16 mute_reg = wm8971_read_reg_cache(codec, WM8971_ADCDAC) & 0xfff7; 530 u16 mute_reg = snd_soc_read(codec, WM8971_ADCDAC) & 0xfff7;
568 531
569 if (mute) 532 if (mute)
570 wm8971_write(codec, WM8971_ADCDAC, mute_reg | 0x8); 533 snd_soc_write(codec, WM8971_ADCDAC, mute_reg | 0x8);
571 else 534 else
572 wm8971_write(codec, WM8971_ADCDAC, mute_reg); 535 snd_soc_write(codec, WM8971_ADCDAC, mute_reg);
573 return 0; 536 return 0;
574} 537}
575 538
576static int wm8971_set_bias_level(struct snd_soc_codec *codec, 539static int wm8971_set_bias_level(struct snd_soc_codec *codec,
577 enum snd_soc_bias_level level) 540 enum snd_soc_bias_level level)
578{ 541{
579 u16 pwr_reg = wm8971_read_reg_cache(codec, WM8971_PWR1) & 0xfe3e; 542 u16 pwr_reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e;
580 543
581 switch (level) { 544 switch (level) {
582 case SND_SOC_BIAS_ON: 545 case SND_SOC_BIAS_ON:
583 /* set vmid to 50k and unmute dac */ 546 /* set vmid to 50k and unmute dac */
584 wm8971_write(codec, WM8971_PWR1, pwr_reg | 0x00c1); 547 snd_soc_write(codec, WM8971_PWR1, pwr_reg | 0x00c1);
585 break; 548 break;
586 case SND_SOC_BIAS_PREPARE: 549 case SND_SOC_BIAS_PREPARE:
587 break; 550 break;
588 case SND_SOC_BIAS_STANDBY: 551 case SND_SOC_BIAS_STANDBY:
589 /* mute dac and set vmid to 500k, enable VREF */ 552 /* mute dac and set vmid to 500k, enable VREF */
590 wm8971_write(codec, WM8971_PWR1, pwr_reg | 0x0140); 553 snd_soc_write(codec, WM8971_PWR1, pwr_reg | 0x0140);
591 break; 554 break;
592 case SND_SOC_BIAS_OFF: 555 case SND_SOC_BIAS_OFF:
593 wm8971_write(codec, WM8971_PWR1, 0x0001); 556 snd_soc_write(codec, WM8971_PWR1, 0x0001);
594 break; 557 break;
595 } 558 }
596 codec->bias_level = level; 559 codec->bias_level = level;
@@ -667,8 +630,8 @@ static int wm8971_resume(struct platform_device *pdev)
667 630
668 /* charge wm8971 caps */ 631 /* charge wm8971 caps */
669 if (codec->suspend_bias_level == SND_SOC_BIAS_ON) { 632 if (codec->suspend_bias_level == SND_SOC_BIAS_ON) {
670 reg = wm8971_read_reg_cache(codec, WM8971_PWR1) & 0xfe3e; 633 reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e;
671 wm8971_write(codec, WM8971_PWR1, reg | 0x01c0); 634 snd_soc_write(codec, WM8971_PWR1, reg | 0x01c0);
672 codec->bias_level = SND_SOC_BIAS_ON; 635 codec->bias_level = SND_SOC_BIAS_ON;
673 queue_delayed_work(wm8971_workq, &codec->delayed_work, 636 queue_delayed_work(wm8971_workq, &codec->delayed_work,
674 msecs_to_jiffies(1000)); 637 msecs_to_jiffies(1000));
@@ -677,15 +640,14 @@ static int wm8971_resume(struct platform_device *pdev)
677 return 0; 640 return 0;
678} 641}
679 642
680static int wm8971_init(struct snd_soc_device *socdev) 643static int wm8971_init(struct snd_soc_device *socdev,
644 enum snd_soc_control_type control)
681{ 645{
682 struct snd_soc_codec *codec = socdev->card->codec; 646 struct snd_soc_codec *codec = socdev->card->codec;
683 int reg, ret = 0; 647 int reg, ret = 0;
684 648
685 codec->name = "WM8971"; 649 codec->name = "WM8971";
686 codec->owner = THIS_MODULE; 650 codec->owner = THIS_MODULE;
687 codec->read = wm8971_read_reg_cache;
688 codec->write = wm8971_write;
689 codec->set_bias_level = wm8971_set_bias_level; 651 codec->set_bias_level = wm8971_set_bias_level;
690 codec->dai = &wm8971_dai; 652 codec->dai = &wm8971_dai;
691 codec->reg_cache_size = ARRAY_SIZE(wm8971_reg); 653 codec->reg_cache_size = ARRAY_SIZE(wm8971_reg);
@@ -695,42 +657,48 @@ static int wm8971_init(struct snd_soc_device *socdev)
695 if (codec->reg_cache == NULL) 657 if (codec->reg_cache == NULL)
696 return -ENOMEM; 658 return -ENOMEM;
697 659
660 ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
661 if (ret < 0) {
662 printk(KERN_ERR "wm8971: failed to set cache I/O: %d\n", ret);
663 goto err;
664 }
665
698 wm8971_reset(codec); 666 wm8971_reset(codec);
699 667
700 /* register pcms */ 668 /* register pcms */
701 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 669 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
702 if (ret < 0) { 670 if (ret < 0) {
703 printk(KERN_ERR "wm8971: failed to create pcms\n"); 671 printk(KERN_ERR "wm8971: failed to create pcms\n");
704 goto pcm_err; 672 goto err;
705 } 673 }
706 674
707 /* charge output caps - set vmid to 5k for quick power up */ 675 /* charge output caps - set vmid to 5k for quick power up */
708 reg = wm8971_read_reg_cache(codec, WM8971_PWR1) & 0xfe3e; 676 reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e;
709 wm8971_write(codec, WM8971_PWR1, reg | 0x01c0); 677 snd_soc_write(codec, WM8971_PWR1, reg | 0x01c0);
710 codec->bias_level = SND_SOC_BIAS_STANDBY; 678 codec->bias_level = SND_SOC_BIAS_STANDBY;
711 queue_delayed_work(wm8971_workq, &codec->delayed_work, 679 queue_delayed_work(wm8971_workq, &codec->delayed_work,
712 msecs_to_jiffies(1000)); 680 msecs_to_jiffies(1000));
713 681
714 /* set the update bits */ 682 /* set the update bits */
715 reg = wm8971_read_reg_cache(codec, WM8971_LDAC); 683 reg = snd_soc_read(codec, WM8971_LDAC);
716 wm8971_write(codec, WM8971_LDAC, reg | 0x0100); 684 snd_soc_write(codec, WM8971_LDAC, reg | 0x0100);
717 reg = wm8971_read_reg_cache(codec, WM8971_RDAC); 685 reg = snd_soc_read(codec, WM8971_RDAC);
718 wm8971_write(codec, WM8971_RDAC, reg | 0x0100); 686 snd_soc_write(codec, WM8971_RDAC, reg | 0x0100);
719 687
720 reg = wm8971_read_reg_cache(codec, WM8971_LOUT1V); 688 reg = snd_soc_read(codec, WM8971_LOUT1V);
721 wm8971_write(codec, WM8971_LOUT1V, reg | 0x0100); 689 snd_soc_write(codec, WM8971_LOUT1V, reg | 0x0100);
722 reg = wm8971_read_reg_cache(codec, WM8971_ROUT1V); 690 reg = snd_soc_read(codec, WM8971_ROUT1V);
723 wm8971_write(codec, WM8971_ROUT1V, reg | 0x0100); 691 snd_soc_write(codec, WM8971_ROUT1V, reg | 0x0100);
724 692
725 reg = wm8971_read_reg_cache(codec, WM8971_LOUT2V); 693 reg = snd_soc_read(codec, WM8971_LOUT2V);
726 wm8971_write(codec, WM8971_LOUT2V, reg | 0x0100); 694 snd_soc_write(codec, WM8971_LOUT2V, reg | 0x0100);
727 reg = wm8971_read_reg_cache(codec, WM8971_ROUT2V); 695 reg = snd_soc_read(codec, WM8971_ROUT2V);
728 wm8971_write(codec, WM8971_ROUT2V, reg | 0x0100); 696 snd_soc_write(codec, WM8971_ROUT2V, reg | 0x0100);
729 697
730 reg = wm8971_read_reg_cache(codec, WM8971_LINVOL); 698 reg = snd_soc_read(codec, WM8971_LINVOL);
731 wm8971_write(codec, WM8971_LINVOL, reg | 0x0100); 699 snd_soc_write(codec, WM8971_LINVOL, reg | 0x0100);
732 reg = wm8971_read_reg_cache(codec, WM8971_RINVOL); 700 reg = snd_soc_read(codec, WM8971_RINVOL);
733 wm8971_write(codec, WM8971_RINVOL, reg | 0x0100); 701 snd_soc_write(codec, WM8971_RINVOL, reg | 0x0100);
734 702
735 snd_soc_add_controls(codec, wm8971_snd_controls, 703 snd_soc_add_controls(codec, wm8971_snd_controls,
736 ARRAY_SIZE(wm8971_snd_controls)); 704 ARRAY_SIZE(wm8971_snd_controls));
@@ -745,7 +713,7 @@ static int wm8971_init(struct snd_soc_device *socdev)
745card_err: 713card_err:
746 snd_soc_free_pcms(socdev); 714 snd_soc_free_pcms(socdev);
747 snd_soc_dapm_free(socdev); 715 snd_soc_dapm_free(socdev);
748pcm_err: 716err:
749 kfree(codec->reg_cache); 717 kfree(codec->reg_cache);
750 return ret; 718 return ret;
751} 719}
@@ -767,7 +735,7 @@ static int wm8971_i2c_probe(struct i2c_client *i2c,
767 735
768 codec->control_data = i2c; 736 codec->control_data = i2c;
769 737
770 ret = wm8971_init(socdev); 738 ret = wm8971_init(socdev, SND_SOC_I2C);
771 if (ret < 0) 739 if (ret < 0)
772 pr_err("failed to initialise WM8971\n"); 740 pr_err("failed to initialise WM8971\n");
773 741
@@ -877,7 +845,6 @@ static int wm8971_probe(struct platform_device *pdev)
877 845
878#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE) 846#if defined (CONFIG_I2C) || defined (CONFIG_I2C_MODULE)
879 if (setup->i2c_address) { 847 if (setup->i2c_address) {
880 codec->hw_write = (hw_write_t)i2c_master_send;
881 ret = wm8971_add_i2c_device(pdev, setup); 848 ret = wm8971_add_i2c_device(pdev, setup);
882 } 849 }
883#endif 850#endif
diff --git a/sound/soc/codecs/wm8988.c b/sound/soc/codecs/wm8988.c
index 6f15acd10489..1c8653523c8c 100644
--- a/sound/soc/codecs/wm8988.c
+++ b/sound/soc/codecs/wm8988.c
@@ -57,50 +57,7 @@ struct wm8988_priv {
57}; 57};
58 58
59 59
60/* 60#define wm8988_reset(c) snd_soc_write(c, WM8988_RESET, 0)
61 * read wm8988 register cache
62 */
63static inline unsigned int wm8988_read_reg_cache(struct snd_soc_codec *codec,
64 unsigned int reg)
65{
66 u16 *cache = codec->reg_cache;
67 if (reg > WM8988_NUM_REG)
68 return -1;
69 return cache[reg];
70}
71
72/*
73 * write wm8988 register cache
74 */
75static inline void wm8988_write_reg_cache(struct snd_soc_codec *codec,
76 unsigned int reg, unsigned int value)
77{
78 u16 *cache = codec->reg_cache;
79 if (reg > WM8988_NUM_REG)
80 return;
81 cache[reg] = value;
82}
83
84static int wm8988_write(struct snd_soc_codec *codec, unsigned int reg,
85 unsigned int value)
86{
87 u8 data[2];
88
89 /* data is
90 * D15..D9 WM8753 register offset
91 * D8...D0 register data
92 */
93 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
94 data[1] = value & 0x00ff;
95
96 wm8988_write_reg_cache(codec, reg, value);
97 if (codec->hw_write(codec->control_data, data, 2) == 2)
98 return 0;
99 else
100 return -EIO;
101}
102
103#define wm8988_reset(c) wm8988_write(c, WM8988_RESET, 0)
104 61
105/* 62/*
106 * WM8988 Controls 63 * WM8988 Controls
@@ -226,15 +183,15 @@ static int wm8988_lrc_control(struct snd_soc_dapm_widget *w,
226 struct snd_kcontrol *kcontrol, int event) 183 struct snd_kcontrol *kcontrol, int event)
227{ 184{
228 struct snd_soc_codec *codec = w->codec; 185 struct snd_soc_codec *codec = w->codec;
229 u16 adctl2 = wm8988_read_reg_cache(codec, WM8988_ADCTL2); 186 u16 adctl2 = snd_soc_read(codec, WM8988_ADCTL2);
230 187
231 /* Use the DAC to gate LRC if active, otherwise use ADC */ 188 /* Use the DAC to gate LRC if active, otherwise use ADC */
232 if (wm8988_read_reg_cache(codec, WM8988_PWR2) & 0x180) 189 if (snd_soc_read(codec, WM8988_PWR2) & 0x180)
233 adctl2 &= ~0x4; 190 adctl2 &= ~0x4;
234 else 191 else
235 adctl2 |= 0x4; 192 adctl2 |= 0x4;
236 193
237 return wm8988_write(codec, WM8988_ADCTL2, adctl2); 194 return snd_soc_write(codec, WM8988_ADCTL2, adctl2);
238} 195}
239 196
240static const char *wm8988_line_texts[] = { 197static const char *wm8988_line_texts[] = {
@@ -619,7 +576,7 @@ static int wm8988_set_dai_fmt(struct snd_soc_dai *codec_dai,
619 return -EINVAL; 576 return -EINVAL;
620 } 577 }
621 578
622 wm8988_write(codec, WM8988_IFACE, iface); 579 snd_soc_write(codec, WM8988_IFACE, iface);
623 return 0; 580 return 0;
624} 581}
625 582
@@ -653,8 +610,8 @@ static int wm8988_pcm_hw_params(struct snd_pcm_substream *substream,
653 struct snd_soc_device *socdev = rtd->socdev; 610 struct snd_soc_device *socdev = rtd->socdev;
654 struct snd_soc_codec *codec = socdev->card->codec; 611 struct snd_soc_codec *codec = socdev->card->codec;
655 struct wm8988_priv *wm8988 = codec->private_data; 612 struct wm8988_priv *wm8988 = codec->private_data;
656 u16 iface = wm8988_read_reg_cache(codec, WM8988_IFACE) & 0x1f3; 613 u16 iface = snd_soc_read(codec, WM8988_IFACE) & 0x1f3;
657 u16 srate = wm8988_read_reg_cache(codec, WM8988_SRATE) & 0x180; 614 u16 srate = snd_soc_read(codec, WM8988_SRATE) & 0x180;
658 int coeff; 615 int coeff;
659 616
660 coeff = get_coeff(wm8988->sysclk, params_rate(params)); 617 coeff = get_coeff(wm8988->sysclk, params_rate(params));
@@ -685,9 +642,9 @@ static int wm8988_pcm_hw_params(struct snd_pcm_substream *substream,
685 } 642 }
686 643
687 /* set iface & srate */ 644 /* set iface & srate */
688 wm8988_write(codec, WM8988_IFACE, iface); 645 snd_soc_write(codec, WM8988_IFACE, iface);
689 if (coeff >= 0) 646 if (coeff >= 0)
690 wm8988_write(codec, WM8988_SRATE, srate | 647 snd_soc_write(codec, WM8988_SRATE, srate |
691 (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb); 648 (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
692 649
693 return 0; 650 return 0;
@@ -696,19 +653,19 @@ static int wm8988_pcm_hw_params(struct snd_pcm_substream *substream,
696static int wm8988_mute(struct snd_soc_dai *dai, int mute) 653static int wm8988_mute(struct snd_soc_dai *dai, int mute)
697{ 654{
698 struct snd_soc_codec *codec = dai->codec; 655 struct snd_soc_codec *codec = dai->codec;
699 u16 mute_reg = wm8988_read_reg_cache(codec, WM8988_ADCDAC) & 0xfff7; 656 u16 mute_reg = snd_soc_read(codec, WM8988_ADCDAC) & 0xfff7;
700 657
701 if (mute) 658 if (mute)
702 wm8988_write(codec, WM8988_ADCDAC, mute_reg | 0x8); 659 snd_soc_write(codec, WM8988_ADCDAC, mute_reg | 0x8);
703 else 660 else
704 wm8988_write(codec, WM8988_ADCDAC, mute_reg); 661 snd_soc_write(codec, WM8988_ADCDAC, mute_reg);
705 return 0; 662 return 0;
706} 663}
707 664
708static int wm8988_set_bias_level(struct snd_soc_codec *codec, 665static int wm8988_set_bias_level(struct snd_soc_codec *codec,
709 enum snd_soc_bias_level level) 666 enum snd_soc_bias_level level)
710{ 667{
711 u16 pwr_reg = wm8988_read_reg_cache(codec, WM8988_PWR1) & ~0x1c1; 668 u16 pwr_reg = snd_soc_read(codec, WM8988_PWR1) & ~0x1c1;
712 669
713 switch (level) { 670 switch (level) {
714 case SND_SOC_BIAS_ON: 671 case SND_SOC_BIAS_ON:
@@ -716,24 +673,24 @@ static int wm8988_set_bias_level(struct snd_soc_codec *codec,
716 673
717 case SND_SOC_BIAS_PREPARE: 674 case SND_SOC_BIAS_PREPARE:
718 /* VREF, VMID=2x50k, digital enabled */ 675 /* VREF, VMID=2x50k, digital enabled */
719 wm8988_write(codec, WM8988_PWR1, pwr_reg | 0x00c0); 676 snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x00c0);
720 break; 677 break;
721 678
722 case SND_SOC_BIAS_STANDBY: 679 case SND_SOC_BIAS_STANDBY:
723 if (codec->bias_level == SND_SOC_BIAS_OFF) { 680 if (codec->bias_level == SND_SOC_BIAS_OFF) {
724 /* VREF, VMID=2x5k */ 681 /* VREF, VMID=2x5k */
725 wm8988_write(codec, WM8988_PWR1, pwr_reg | 0x1c1); 682 snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x1c1);
726 683
727 /* Charge caps */ 684 /* Charge caps */
728 msleep(100); 685 msleep(100);
729 } 686 }
730 687
731 /* VREF, VMID=2*500k, digital stopped */ 688 /* VREF, VMID=2*500k, digital stopped */
732 wm8988_write(codec, WM8988_PWR1, pwr_reg | 0x0141); 689 snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x0141);
733 break; 690 break;
734 691
735 case SND_SOC_BIAS_OFF: 692 case SND_SOC_BIAS_OFF:
736 wm8988_write(codec, WM8988_PWR1, 0x0000); 693 snd_soc_write(codec, WM8988_PWR1, 0x0000);
737 break; 694 break;
738 } 695 }
739 codec->bias_level = level; 696 codec->bias_level = level;
@@ -868,7 +825,8 @@ struct snd_soc_codec_device soc_codec_dev_wm8988 = {
868}; 825};
869EXPORT_SYMBOL_GPL(soc_codec_dev_wm8988); 826EXPORT_SYMBOL_GPL(soc_codec_dev_wm8988);
870 827
871static int wm8988_register(struct wm8988_priv *wm8988) 828static int wm8988_register(struct wm8988_priv *wm8988,
829 enum snd_soc_control_type control)
872{ 830{
873 struct snd_soc_codec *codec = &wm8988->codec; 831 struct snd_soc_codec *codec = &wm8988->codec;
874 int ret; 832 int ret;
@@ -887,8 +845,6 @@ static int wm8988_register(struct wm8988_priv *wm8988)
887 codec->private_data = wm8988; 845 codec->private_data = wm8988;
888 codec->name = "WM8988"; 846 codec->name = "WM8988";
889 codec->owner = THIS_MODULE; 847 codec->owner = THIS_MODULE;
890 codec->read = wm8988_read_reg_cache;
891 codec->write = wm8988_write;
892 codec->dai = &wm8988_dai; 848 codec->dai = &wm8988_dai;
893 codec->num_dai = 1; 849 codec->num_dai = 1;
894 codec->reg_cache_size = ARRAY_SIZE(wm8988->reg_cache); 850 codec->reg_cache_size = ARRAY_SIZE(wm8988->reg_cache);
@@ -899,6 +855,12 @@ static int wm8988_register(struct wm8988_priv *wm8988)
899 memcpy(codec->reg_cache, wm8988_reg, 855 memcpy(codec->reg_cache, wm8988_reg,
900 sizeof(wm8988_reg)); 856 sizeof(wm8988_reg));
901 857
858 ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
859 if (ret < 0) {
860 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
861 goto err;
862 }
863
902 ret = wm8988_reset(codec); 864 ret = wm8988_reset(codec);
903 if (ret < 0) { 865 if (ret < 0) {
904 dev_err(codec->dev, "Failed to issue reset\n"); 866 dev_err(codec->dev, "Failed to issue reset\n");
@@ -906,16 +868,16 @@ static int wm8988_register(struct wm8988_priv *wm8988)
906 } 868 }
907 869
908 /* set the update bits (we always update left then right) */ 870 /* set the update bits (we always update left then right) */
909 reg = wm8988_read_reg_cache(codec, WM8988_RADC); 871 reg = snd_soc_read(codec, WM8988_RADC);
910 wm8988_write(codec, WM8988_RADC, reg | 0x100); 872 snd_soc_write(codec, WM8988_RADC, reg | 0x100);
911 reg = wm8988_read_reg_cache(codec, WM8988_RDAC); 873 reg = snd_soc_read(codec, WM8988_RDAC);
912 wm8988_write(codec, WM8988_RDAC, reg | 0x0100); 874 snd_soc_write(codec, WM8988_RDAC, reg | 0x0100);
913 reg = wm8988_read_reg_cache(codec, WM8988_ROUT1V); 875 reg = snd_soc_read(codec, WM8988_ROUT1V);
914 wm8988_write(codec, WM8988_ROUT1V, reg | 0x0100); 876 snd_soc_write(codec, WM8988_ROUT1V, reg | 0x0100);
915 reg = wm8988_read_reg_cache(codec, WM8988_ROUT2V); 877 reg = snd_soc_read(codec, WM8988_ROUT2V);
916 wm8988_write(codec, WM8988_ROUT2V, reg | 0x0100); 878 snd_soc_write(codec, WM8988_ROUT2V, reg | 0x0100);
917 reg = wm8988_read_reg_cache(codec, WM8988_RINVOL); 879 reg = snd_soc_read(codec, WM8988_RINVOL);
918 wm8988_write(codec, WM8988_RINVOL, reg | 0x0100); 880 snd_soc_write(codec, WM8988_RINVOL, reg | 0x0100);
919 881
920 wm8988_set_bias_level(&wm8988->codec, SND_SOC_BIAS_STANDBY); 882 wm8988_set_bias_level(&wm8988->codec, SND_SOC_BIAS_STANDBY);
921 883
@@ -966,14 +928,13 @@ static int wm8988_i2c_probe(struct i2c_client *i2c,
966 return -ENOMEM; 928 return -ENOMEM;
967 929
968 codec = &wm8988->codec; 930 codec = &wm8988->codec;
969 codec->hw_write = (hw_write_t)i2c_master_send;
970 931
971 i2c_set_clientdata(i2c, wm8988); 932 i2c_set_clientdata(i2c, wm8988);
972 codec->control_data = i2c; 933 codec->control_data = i2c;
973 934
974 codec->dev = &i2c->dev; 935 codec->dev = &i2c->dev;
975 936
976 return wm8988_register(wm8988); 937 return wm8988_register(wm8988, SND_SOC_I2C);
977} 938}
978 939
979static int wm8988_i2c_remove(struct i2c_client *client) 940static int wm8988_i2c_remove(struct i2c_client *client)
@@ -1018,30 +979,6 @@ static struct i2c_driver wm8988_i2c_driver = {
1018#endif 979#endif
1019 980
1020#if defined(CONFIG_SPI_MASTER) 981#if defined(CONFIG_SPI_MASTER)
1021static int wm8988_spi_write(struct spi_device *spi, const char *data, int len)
1022{
1023 struct spi_transfer t;
1024 struct spi_message m;
1025 u8 msg[2];
1026
1027 if (len <= 0)
1028 return 0;
1029
1030 msg[0] = data[0];
1031 msg[1] = data[1];
1032
1033 spi_message_init(&m);
1034 memset(&t, 0, (sizeof t));
1035
1036 t.tx_buf = &msg[0];
1037 t.len = len;
1038
1039 spi_message_add_tail(&t, &m);
1040 spi_sync(spi, &m);
1041
1042 return len;
1043}
1044
1045static int __devinit wm8988_spi_probe(struct spi_device *spi) 982static int __devinit wm8988_spi_probe(struct spi_device *spi)
1046{ 983{
1047 struct wm8988_priv *wm8988; 984 struct wm8988_priv *wm8988;
@@ -1052,13 +989,12 @@ static int __devinit wm8988_spi_probe(struct spi_device *spi)
1052 return -ENOMEM; 989 return -ENOMEM;
1053 990
1054 codec = &wm8988->codec; 991 codec = &wm8988->codec;
1055 codec->hw_write = (hw_write_t)wm8988_spi_write;
1056 codec->control_data = spi; 992 codec->control_data = spi;
1057 codec->dev = &spi->dev; 993 codec->dev = &spi->dev;
1058 994
1059 spi->dev.driver_data = wm8988; 995 spi->dev.driver_data = wm8988;
1060 996
1061 return wm8988_register(wm8988); 997 return wm8988_register(wm8988, SND_SOC_SPI);
1062} 998}
1063 999
1064static int __devexit wm8988_spi_remove(struct spi_device *spi) 1000static int __devexit wm8988_spi_remove(struct spi_device *spi)
diff --git a/sound/soc/codecs/wm8990.c b/sound/soc/codecs/wm8990.c
index d029818350e9..2d702db4131d 100644
--- a/sound/soc/codecs/wm8990.c
+++ b/sound/soc/codecs/wm8990.c
@@ -108,53 +108,7 @@ static const u16 wm8990_reg[] = {
108 0x0000, /* R63 - Driver internal */ 108 0x0000, /* R63 - Driver internal */
109}; 109};
110 110
111/* 111#define wm8990_reset(c) snd_soc_write(c, WM8990_RESET, 0)
112 * read wm8990 register cache
113 */
114static inline unsigned int wm8990_read_reg_cache(struct snd_soc_codec *codec,
115 unsigned int reg)
116{
117 u16 *cache = codec->reg_cache;
118 BUG_ON(reg >= ARRAY_SIZE(wm8990_reg));
119 return cache[reg];
120}
121
122/*
123 * write wm8990 register cache
124 */
125static inline void wm8990_write_reg_cache(struct snd_soc_codec *codec,
126 unsigned int reg, unsigned int value)
127{
128 u16 *cache = codec->reg_cache;
129
130 /* Reset register and reserved registers are uncached */
131 if (reg == 0 || reg >= ARRAY_SIZE(wm8990_reg))
132 return;
133
134 cache[reg] = value;
135}
136
137/*
138 * write to the wm8990 register space
139 */
140static int wm8990_write(struct snd_soc_codec *codec, unsigned int reg,
141 unsigned int value)
142{
143 u8 data[3];
144
145 data[0] = reg & 0xFF;
146 data[1] = (value >> 8) & 0xFF;
147 data[2] = value & 0xFF;
148
149 wm8990_write_reg_cache(codec, reg, value);
150
151 if (codec->hw_write(codec->control_data, data, 3) == 2)
152 return 0;
153 else
154 return -EIO;
155}
156
157#define wm8990_reset(c) wm8990_write(c, WM8990_RESET, 0)
158 112
159static const DECLARE_TLV_DB_LINEAR(rec_mix_tlv, -1500, 600); 113static const DECLARE_TLV_DB_LINEAR(rec_mix_tlv, -1500, 600);
160 114
@@ -187,8 +141,8 @@ static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
187 return ret; 141 return ret;
188 142
189 /* now hit the volume update bits (always bit 8) */ 143 /* now hit the volume update bits (always bit 8) */
190 val = wm8990_read_reg_cache(codec, reg); 144 val = snd_soc_read(codec, reg);
191 return wm8990_write(codec, reg, val | 0x0100); 145 return snd_soc_write(codec, reg, val | 0x0100);
192} 146}
193 147
194#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\ 148#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
@@ -427,8 +381,8 @@ static int inmixer_event(struct snd_soc_dapm_widget *w,
427{ 381{
428 u16 reg, fakepower; 382 u16 reg, fakepower;
429 383
430 reg = wm8990_read_reg_cache(w->codec, WM8990_POWER_MANAGEMENT_2); 384 reg = snd_soc_read(w->codec, WM8990_POWER_MANAGEMENT_2);
431 fakepower = wm8990_read_reg_cache(w->codec, WM8990_INTDRIVBITS); 385 fakepower = snd_soc_read(w->codec, WM8990_INTDRIVBITS);
432 386
433 if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) | 387 if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) |
434 (1 << WM8990_AINLMUX_PWR_BIT))) { 388 (1 << WM8990_AINLMUX_PWR_BIT))) {
@@ -443,7 +397,7 @@ static int inmixer_event(struct snd_soc_dapm_widget *w,
443 } else { 397 } else {
444 reg &= ~WM8990_AINL_ENA; 398 reg &= ~WM8990_AINL_ENA;
445 } 399 }
446 wm8990_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg); 400 snd_soc_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg);
447 401
448 return 0; 402 return 0;
449} 403}
@@ -457,7 +411,7 @@ static int outmixer_event(struct snd_soc_dapm_widget *w,
457 411
458 switch (reg_shift) { 412 switch (reg_shift) {
459 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) : 413 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
460 reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER1); 414 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER1);
461 if (reg & WM8990_LDLO) { 415 if (reg & WM8990_LDLO) {
462 printk(KERN_WARNING 416 printk(KERN_WARNING
463 "Cannot set as Output Mixer 1 LDLO Set\n"); 417 "Cannot set as Output Mixer 1 LDLO Set\n");
@@ -465,7 +419,7 @@ static int outmixer_event(struct snd_soc_dapm_widget *w,
465 } 419 }
466 break; 420 break;
467 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8): 421 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
468 reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER2); 422 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER2);
469 if (reg & WM8990_RDRO) { 423 if (reg & WM8990_RDRO) {
470 printk(KERN_WARNING 424 printk(KERN_WARNING
471 "Cannot set as Output Mixer 2 RDRO Set\n"); 425 "Cannot set as Output Mixer 2 RDRO Set\n");
@@ -473,7 +427,7 @@ static int outmixer_event(struct snd_soc_dapm_widget *w,
473 } 427 }
474 break; 428 break;
475 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8): 429 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
476 reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER); 430 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER);
477 if (reg & WM8990_LDSPK) { 431 if (reg & WM8990_LDSPK) {
478 printk(KERN_WARNING 432 printk(KERN_WARNING
479 "Cannot set as Speaker Mixer LDSPK Set\n"); 433 "Cannot set as Speaker Mixer LDSPK Set\n");
@@ -481,7 +435,7 @@ static int outmixer_event(struct snd_soc_dapm_widget *w,
481 } 435 }
482 break; 436 break;
483 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8): 437 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
484 reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER); 438 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER);
485 if (reg & WM8990_RDSPK) { 439 if (reg & WM8990_RDSPK) {
486 printk(KERN_WARNING 440 printk(KERN_WARNING
487 "Cannot set as Speaker Mixer RDSPK Set\n"); 441 "Cannot set as Speaker Mixer RDSPK Set\n");
@@ -1029,24 +983,24 @@ static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai,
1029 pll_factors(&pll_div, freq_out * 4, freq_in); 983 pll_factors(&pll_div, freq_out * 4, freq_in);
1030 984
1031 /* Turn on PLL */ 985 /* Turn on PLL */
1032 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); 986 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2);
1033 reg |= WM8990_PLL_ENA; 987 reg |= WM8990_PLL_ENA;
1034 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg); 988 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
1035 989
1036 /* sysclk comes from PLL */ 990 /* sysclk comes from PLL */
1037 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2); 991 reg = snd_soc_read(codec, WM8990_CLOCKING_2);
1038 wm8990_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC); 992 snd_soc_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC);
1039 993
1040 /* set up N , fractional mode and pre-divisor if neccessary */ 994 /* set up N , fractional mode and pre-divisor if neccessary */
1041 wm8990_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM | 995 snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM |
1042 (pll_div.div2?WM8990_PRESCALE:0)); 996 (pll_div.div2?WM8990_PRESCALE:0));
1043 wm8990_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8)); 997 snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8));
1044 wm8990_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF)); 998 snd_soc_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
1045 } else { 999 } else {
1046 /* Turn on PLL */ 1000 /* Turn on PLL */
1047 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); 1001 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2);
1048 reg &= ~WM8990_PLL_ENA; 1002 reg &= ~WM8990_PLL_ENA;
1049 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg); 1003 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
1050 } 1004 }
1051 return 0; 1005 return 0;
1052} 1006}
@@ -1073,8 +1027,8 @@ static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
1073 struct snd_soc_codec *codec = codec_dai->codec; 1027 struct snd_soc_codec *codec = codec_dai->codec;
1074 u16 audio1, audio3; 1028 u16 audio1, audio3;
1075 1029
1076 audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1); 1030 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
1077 audio3 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_3); 1031 audio3 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_3);
1078 1032
1079 /* set master/slave audio interface */ 1033 /* set master/slave audio interface */
1080 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1034 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -1115,8 +1069,8 @@ static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
1115 return -EINVAL; 1069 return -EINVAL;
1116 } 1070 }
1117 1071
1118 wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1072 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1119 wm8990_write(codec, WM8990_AUDIO_INTERFACE_3, audio3); 1073 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_3, audio3);
1120 return 0; 1074 return 0;
1121} 1075}
1122 1076
@@ -1128,24 +1082,24 @@ static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1128 1082
1129 switch (div_id) { 1083 switch (div_id) {
1130 case WM8990_MCLK_DIV: 1084 case WM8990_MCLK_DIV:
1131 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) & 1085 reg = snd_soc_read(codec, WM8990_CLOCKING_2) &
1132 ~WM8990_MCLK_DIV_MASK; 1086 ~WM8990_MCLK_DIV_MASK;
1133 wm8990_write(codec, WM8990_CLOCKING_2, reg | div); 1087 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div);
1134 break; 1088 break;
1135 case WM8990_DACCLK_DIV: 1089 case WM8990_DACCLK_DIV:
1136 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) & 1090 reg = snd_soc_read(codec, WM8990_CLOCKING_2) &
1137 ~WM8990_DAC_CLKDIV_MASK; 1091 ~WM8990_DAC_CLKDIV_MASK;
1138 wm8990_write(codec, WM8990_CLOCKING_2, reg | div); 1092 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div);
1139 break; 1093 break;
1140 case WM8990_ADCCLK_DIV: 1094 case WM8990_ADCCLK_DIV:
1141 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) & 1095 reg = snd_soc_read(codec, WM8990_CLOCKING_2) &
1142 ~WM8990_ADC_CLKDIV_MASK; 1096 ~WM8990_ADC_CLKDIV_MASK;
1143 wm8990_write(codec, WM8990_CLOCKING_2, reg | div); 1097 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div);
1144 break; 1098 break;
1145 case WM8990_BCLK_DIV: 1099 case WM8990_BCLK_DIV:
1146 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_1) & 1100 reg = snd_soc_read(codec, WM8990_CLOCKING_1) &
1147 ~WM8990_BCLK_DIV_MASK; 1101 ~WM8990_BCLK_DIV_MASK;
1148 wm8990_write(codec, WM8990_CLOCKING_1, reg | div); 1102 snd_soc_write(codec, WM8990_CLOCKING_1, reg | div);
1149 break; 1103 break;
1150 default: 1104 default:
1151 return -EINVAL; 1105 return -EINVAL;
@@ -1164,7 +1118,7 @@ static int wm8990_hw_params(struct snd_pcm_substream *substream,
1164 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1118 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1165 struct snd_soc_device *socdev = rtd->socdev; 1119 struct snd_soc_device *socdev = rtd->socdev;
1166 struct snd_soc_codec *codec = socdev->card->codec; 1120 struct snd_soc_codec *codec = socdev->card->codec;
1167 u16 audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1); 1121 u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
1168 1122
1169 audio1 &= ~WM8990_AIF_WL_MASK; 1123 audio1 &= ~WM8990_AIF_WL_MASK;
1170 /* bit size */ 1124 /* bit size */
@@ -1182,7 +1136,7 @@ static int wm8990_hw_params(struct snd_pcm_substream *substream,
1182 break; 1136 break;
1183 } 1137 }
1184 1138
1185 wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1); 1139 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1186 return 0; 1140 return 0;
1187} 1141}
1188 1142
@@ -1191,12 +1145,12 @@ static int wm8990_mute(struct snd_soc_dai *dai, int mute)
1191 struct snd_soc_codec *codec = dai->codec; 1145 struct snd_soc_codec *codec = dai->codec;
1192 u16 val; 1146 u16 val;
1193 1147
1194 val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE; 1148 val = snd_soc_read(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
1195 1149
1196 if (mute) 1150 if (mute)
1197 wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1151 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1198 else 1152 else
1199 wm8990_write(codec, WM8990_DAC_CTRL, val); 1153 snd_soc_write(codec, WM8990_DAC_CTRL, val);
1200 1154
1201 return 0; 1155 return 0;
1202} 1156}
@@ -1212,21 +1166,21 @@ static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1212 1166
1213 case SND_SOC_BIAS_PREPARE: 1167 case SND_SOC_BIAS_PREPARE:
1214 /* VMID=2*50k */ 1168 /* VMID=2*50k */
1215 val = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_1) & 1169 val = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_1) &
1216 ~WM8990_VMID_MODE_MASK; 1170 ~WM8990_VMID_MODE_MASK;
1217 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x2); 1171 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x2);
1218 break; 1172 break;
1219 1173
1220 case SND_SOC_BIAS_STANDBY: 1174 case SND_SOC_BIAS_STANDBY:
1221 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1175 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1222 /* Enable all output discharge bits */ 1176 /* Enable all output discharge bits */
1223 wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1177 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1224 WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1178 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1225 WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1179 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1226 WM8990_DIS_ROUT); 1180 WM8990_DIS_ROUT);
1227 1181
1228 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ 1182 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1229 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1183 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1230 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1184 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1231 WM8990_VMIDTOG); 1185 WM8990_VMIDTOG);
1232 1186
@@ -1234,83 +1188,83 @@ static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1234 msleep(msecs_to_jiffies(300)); 1188 msleep(msecs_to_jiffies(300));
1235 1189
1236 /* Disable VMIDTOG */ 1190 /* Disable VMIDTOG */
1237 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1191 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1238 WM8990_BUFDCOPEN | WM8990_POBCTRL); 1192 WM8990_BUFDCOPEN | WM8990_POBCTRL);
1239 1193
1240 /* disable all output discharge bits */ 1194 /* disable all output discharge bits */
1241 wm8990_write(codec, WM8990_ANTIPOP1, 0); 1195 snd_soc_write(codec, WM8990_ANTIPOP1, 0);
1242 1196
1243 /* Enable outputs */ 1197 /* Enable outputs */
1244 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00); 1198 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00);
1245 1199
1246 msleep(msecs_to_jiffies(50)); 1200 msleep(msecs_to_jiffies(50));
1247 1201
1248 /* Enable VMID at 2x50k */ 1202 /* Enable VMID at 2x50k */
1249 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02); 1203 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02);
1250 1204
1251 msleep(msecs_to_jiffies(100)); 1205 msleep(msecs_to_jiffies(100));
1252 1206
1253 /* Enable VREF */ 1207 /* Enable VREF */
1254 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1208 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1255 1209
1256 msleep(msecs_to_jiffies(600)); 1210 msleep(msecs_to_jiffies(600));
1257 1211
1258 /* Enable BUFIOEN */ 1212 /* Enable BUFIOEN */
1259 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1213 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1260 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1214 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1261 WM8990_BUFIOEN); 1215 WM8990_BUFIOEN);
1262 1216
1263 /* Disable outputs */ 1217 /* Disable outputs */
1264 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3); 1218 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3);
1265 1219
1266 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1220 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1267 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN); 1221 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN);
1268 1222
1269 /* Enable workaround for ADC clocking issue. */ 1223 /* Enable workaround for ADC clocking issue. */
1270 wm8990_write(codec, WM8990_EXT_ACCESS_ENA, 0x2); 1224 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0x2);
1271 wm8990_write(codec, WM8990_EXT_CTL1, 0xa003); 1225 snd_soc_write(codec, WM8990_EXT_CTL1, 0xa003);
1272 wm8990_write(codec, WM8990_EXT_ACCESS_ENA, 0); 1226 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0);
1273 } 1227 }
1274 1228
1275 /* VMID=2*250k */ 1229 /* VMID=2*250k */
1276 val = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_1) & 1230 val = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_1) &
1277 ~WM8990_VMID_MODE_MASK; 1231 ~WM8990_VMID_MODE_MASK;
1278 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x4); 1232 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x4);
1279 break; 1233 break;
1280 1234
1281 case SND_SOC_BIAS_OFF: 1235 case SND_SOC_BIAS_OFF:
1282 /* Enable POBCTRL and SOFT_ST */ 1236 /* Enable POBCTRL and SOFT_ST */
1283 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1237 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1284 WM8990_POBCTRL | WM8990_BUFIOEN); 1238 WM8990_POBCTRL | WM8990_BUFIOEN);
1285 1239
1286 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ 1240 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1287 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST | 1241 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1288 WM8990_BUFDCOPEN | WM8990_POBCTRL | 1242 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1289 WM8990_BUFIOEN); 1243 WM8990_BUFIOEN);
1290 1244
1291 /* mute DAC */ 1245 /* mute DAC */
1292 val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL); 1246 val = snd_soc_read(codec, WM8990_DAC_CTRL);
1293 wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE); 1247 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1294 1248
1295 /* Enable any disabled outputs */ 1249 /* Enable any disabled outputs */
1296 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03); 1250 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1297 1251
1298 /* Disable VMID */ 1252 /* Disable VMID */
1299 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01); 1253 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01);
1300 1254
1301 msleep(msecs_to_jiffies(300)); 1255 msleep(msecs_to_jiffies(300));
1302 1256
1303 /* Enable all output discharge bits */ 1257 /* Enable all output discharge bits */
1304 wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1258 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1305 WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1259 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1306 WM8990_DIS_OUT4 | WM8990_DIS_LOUT | 1260 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1307 WM8990_DIS_ROUT); 1261 WM8990_DIS_ROUT);
1308 1262
1309 /* Disable VREF */ 1263 /* Disable VREF */
1310 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0); 1264 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0);
1311 1265
1312 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1266 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1313 wm8990_write(codec, WM8990_ANTIPOP2, 0x0); 1267 snd_soc_write(codec, WM8990_ANTIPOP2, 0x0);
1314 break; 1268 break;
1315 } 1269 }
1316 1270
@@ -1411,8 +1365,6 @@ static int wm8990_init(struct snd_soc_device *socdev)
1411 1365
1412 codec->name = "WM8990"; 1366 codec->name = "WM8990";
1413 codec->owner = THIS_MODULE; 1367 codec->owner = THIS_MODULE;
1414 codec->read = wm8990_read_reg_cache;
1415 codec->write = wm8990_write;
1416 codec->set_bias_level = wm8990_set_bias_level; 1368 codec->set_bias_level = wm8990_set_bias_level;
1417 codec->dai = &wm8990_dai; 1369 codec->dai = &wm8990_dai;
1418 codec->num_dai = 2; 1370 codec->num_dai = 2;
@@ -1422,6 +1374,12 @@ static int wm8990_init(struct snd_soc_device *socdev)
1422 if (codec->reg_cache == NULL) 1374 if (codec->reg_cache == NULL)
1423 return -ENOMEM; 1375 return -ENOMEM;
1424 1376
1377 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1378 if (ret < 0) {
1379 printk(KERN_ERR "wm8990: failed to set cache I/O: %d\n", ret);
1380 goto pcm_err;
1381 }
1382
1425 wm8990_reset(codec); 1383 wm8990_reset(codec);
1426 1384
1427 /* register pcms */ 1385 /* register pcms */
@@ -1435,18 +1393,18 @@ static int wm8990_init(struct snd_soc_device *socdev)
1435 codec->bias_level = SND_SOC_BIAS_OFF; 1393 codec->bias_level = SND_SOC_BIAS_OFF;
1436 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1394 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1437 1395
1438 reg = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_4); 1396 reg = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_4);
1439 wm8990_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1); 1397 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1);
1440 1398
1441 reg = wm8990_read_reg_cache(codec, WM8990_GPIO1_GPIO2) & 1399 reg = snd_soc_read(codec, WM8990_GPIO1_GPIO2) &
1442 ~WM8990_GPIO1_SEL_MASK; 1400 ~WM8990_GPIO1_SEL_MASK;
1443 wm8990_write(codec, WM8990_GPIO1_GPIO2, reg | 1); 1401 snd_soc_write(codec, WM8990_GPIO1_GPIO2, reg | 1);
1444 1402
1445 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2); 1403 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2);
1446 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA); 1404 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA);
1447 1405
1448 wm8990_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1406 snd_soc_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1449 wm8990_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1407 snd_soc_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1450 1408
1451 snd_soc_add_controls(codec, wm8990_snd_controls, 1409 snd_soc_add_controls(codec, wm8990_snd_controls,
1452 ARRAY_SIZE(wm8990_snd_controls)); 1410 ARRAY_SIZE(wm8990_snd_controls));
diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c
index 156f2a4a5930..1f51dd542a46 100644
--- a/sound/soc/codecs/wm9081.c
+++ b/sound/soc/codecs/wm9081.c
@@ -168,84 +168,19 @@ struct wm9081_priv {
168 struct wm9081_retune_mobile_config *retune; 168 struct wm9081_retune_mobile_config *retune;
169}; 169};
170 170
171static int wm9081_reg_is_volatile(int reg) 171static int wm9081_volatile_register(unsigned int reg)
172{ 172{
173 switch (reg) { 173 switch (reg) {
174 case WM9081_SOFTWARE_RESET:
175 return 1;
174 default: 176 default:
175 return 0; 177 return 0;
176 } 178 }
177} 179}
178 180
179static unsigned int wm9081_read_reg_cache(struct snd_soc_codec *codec,
180 unsigned int reg)
181{
182 u16 *cache = codec->reg_cache;
183 BUG_ON(reg > WM9081_MAX_REGISTER);
184 return cache[reg];
185}
186
187static unsigned int wm9081_read_hw(struct snd_soc_codec *codec, u8 reg)
188{
189 struct i2c_msg xfer[2];
190 u16 data;
191 int ret;
192 struct i2c_client *client = codec->control_data;
193
194 BUG_ON(reg > WM9081_MAX_REGISTER);
195
196 /* Write register */
197 xfer[0].addr = client->addr;
198 xfer[0].flags = 0;
199 xfer[0].len = 1;
200 xfer[0].buf = &reg;
201
202 /* Read data */
203 xfer[1].addr = client->addr;
204 xfer[1].flags = I2C_M_RD;
205 xfer[1].len = 2;
206 xfer[1].buf = (u8 *)&data;
207
208 ret = i2c_transfer(client->adapter, xfer, 2);
209 if (ret != 2) {
210 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
211 return 0;
212 }
213
214 return (data >> 8) | ((data & 0xff) << 8);
215}
216
217static unsigned int wm9081_read(struct snd_soc_codec *codec, unsigned int reg)
218{
219 if (wm9081_reg_is_volatile(reg))
220 return wm9081_read_hw(codec, reg);
221 else
222 return wm9081_read_reg_cache(codec, reg);
223}
224
225static int wm9081_write(struct snd_soc_codec *codec, unsigned int reg,
226 unsigned int value)
227{
228 u16 *cache = codec->reg_cache;
229 u8 data[3];
230
231 BUG_ON(reg > WM9081_MAX_REGISTER);
232
233 if (!wm9081_reg_is_volatile(reg))
234 cache[reg] = value;
235
236 data[0] = reg;
237 data[1] = value >> 8;
238 data[2] = value & 0x00ff;
239
240 if (codec->hw_write(codec->control_data, data, 3) == 3)
241 return 0;
242 else
243 return -EIO;
244}
245
246static int wm9081_reset(struct snd_soc_codec *codec) 181static int wm9081_reset(struct snd_soc_codec *codec)
247{ 182{
248 return wm9081_write(codec, WM9081_SOFTWARE_RESET, 0); 183 return snd_soc_write(codec, WM9081_SOFTWARE_RESET, 0);
249} 184}
250 185
251static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0); 186static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
@@ -356,7 +291,7 @@ static int speaker_mode_get(struct snd_kcontrol *kcontrol,
356 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 291 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
357 unsigned int reg; 292 unsigned int reg;
358 293
359 reg = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_2); 294 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
360 if (reg & WM9081_SPK_MODE) 295 if (reg & WM9081_SPK_MODE)
361 ucontrol->value.integer.value[0] = 1; 296 ucontrol->value.integer.value[0] = 1;
362 else 297 else
@@ -375,8 +310,8 @@ static int speaker_mode_put(struct snd_kcontrol *kcontrol,
375 struct snd_ctl_elem_value *ucontrol) 310 struct snd_ctl_elem_value *ucontrol)
376{ 311{
377 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 312 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
378 unsigned int reg_pwr = wm9081_read(codec, WM9081_POWER_MANAGEMENT); 313 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
379 unsigned int reg2 = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_2); 314 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
380 315
381 /* Are we changing anything? */ 316 /* Are we changing anything? */
382 if (ucontrol->value.integer.value[0] == 317 if (ucontrol->value.integer.value[0] ==
@@ -397,7 +332,7 @@ static int speaker_mode_put(struct snd_kcontrol *kcontrol,
397 reg2 &= ~WM9081_SPK_MODE; 332 reg2 &= ~WM9081_SPK_MODE;
398 } 333 }
399 334
400 wm9081_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2); 335 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
401 336
402 return 0; 337 return 0;
403} 338}
@@ -456,7 +391,7 @@ static int speaker_event(struct snd_soc_dapm_widget *w,
456 struct snd_kcontrol *kcontrol, int event) 391 struct snd_kcontrol *kcontrol, int event)
457{ 392{
458 struct snd_soc_codec *codec = w->codec; 393 struct snd_soc_codec *codec = w->codec;
459 unsigned int reg = wm9081_read(codec, WM9081_POWER_MANAGEMENT); 394 unsigned int reg = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
460 395
461 switch (event) { 396 switch (event) {
462 case SND_SOC_DAPM_POST_PMU: 397 case SND_SOC_DAPM_POST_PMU:
@@ -468,7 +403,7 @@ static int speaker_event(struct snd_soc_dapm_widget *w,
468 break; 403 break;
469 } 404 }
470 405
471 wm9081_write(codec, WM9081_POWER_MANAGEMENT, reg); 406 snd_soc_write(codec, WM9081_POWER_MANAGEMENT, reg);
472 407
473 return 0; 408 return 0;
474} 409}
@@ -607,7 +542,7 @@ static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
607 if (ret != 0) 542 if (ret != 0)
608 return ret; 543 return ret;
609 544
610 reg5 = wm9081_read(codec, WM9081_FLL_CONTROL_5); 545 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
611 reg5 &= ~WM9081_FLL_CLK_SRC_MASK; 546 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
612 547
613 switch (fll_id) { 548 switch (fll_id) {
@@ -621,44 +556,44 @@ static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
621 } 556 }
622 557
623 /* Disable CLK_SYS while we reconfigure */ 558 /* Disable CLK_SYS while we reconfigure */
624 clk_sys_reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_3); 559 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
625 if (clk_sys_reg & WM9081_CLK_SYS_ENA) 560 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
626 wm9081_write(codec, WM9081_CLOCK_CONTROL_3, 561 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
627 clk_sys_reg & ~WM9081_CLK_SYS_ENA); 562 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
628 563
629 /* Any FLL configuration change requires that the FLL be 564 /* Any FLL configuration change requires that the FLL be
630 * disabled first. */ 565 * disabled first. */
631 reg1 = wm9081_read(codec, WM9081_FLL_CONTROL_1); 566 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
632 reg1 &= ~WM9081_FLL_ENA; 567 reg1 &= ~WM9081_FLL_ENA;
633 wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1); 568 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
634 569
635 /* Apply the configuration */ 570 /* Apply the configuration */
636 if (fll_div.k) 571 if (fll_div.k)
637 reg1 |= WM9081_FLL_FRAC_MASK; 572 reg1 |= WM9081_FLL_FRAC_MASK;
638 else 573 else
639 reg1 &= ~WM9081_FLL_FRAC_MASK; 574 reg1 &= ~WM9081_FLL_FRAC_MASK;
640 wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1); 575 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
641 576
642 wm9081_write(codec, WM9081_FLL_CONTROL_2, 577 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
643 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) | 578 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
644 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT)); 579 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
645 wm9081_write(codec, WM9081_FLL_CONTROL_3, fll_div.k); 580 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
646 581
647 reg4 = wm9081_read(codec, WM9081_FLL_CONTROL_4); 582 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
648 reg4 &= ~WM9081_FLL_N_MASK; 583 reg4 &= ~WM9081_FLL_N_MASK;
649 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT; 584 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
650 wm9081_write(codec, WM9081_FLL_CONTROL_4, reg4); 585 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
651 586
652 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK; 587 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
653 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT; 588 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
654 wm9081_write(codec, WM9081_FLL_CONTROL_5, reg5); 589 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
655 590
656 /* Enable the FLL */ 591 /* Enable the FLL */
657 wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA); 592 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
658 593
659 /* Then bring CLK_SYS up again if it was disabled */ 594 /* Then bring CLK_SYS up again if it was disabled */
660 if (clk_sys_reg & WM9081_CLK_SYS_ENA) 595 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
661 wm9081_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg); 596 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
662 597
663 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout); 598 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
664 599
@@ -742,19 +677,19 @@ static int configure_clock(struct snd_soc_codec *codec)
742 return -EINVAL; 677 return -EINVAL;
743 } 678 }
744 679
745 reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_1); 680 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
746 if (mclkdiv) 681 if (mclkdiv)
747 reg |= WM9081_MCLKDIV2; 682 reg |= WM9081_MCLKDIV2;
748 else 683 else
749 reg &= ~WM9081_MCLKDIV2; 684 reg &= ~WM9081_MCLKDIV2;
750 wm9081_write(codec, WM9081_CLOCK_CONTROL_1, reg); 685 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
751 686
752 reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_3); 687 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
753 if (fll) 688 if (fll)
754 reg |= WM9081_CLK_SRC_SEL; 689 reg |= WM9081_CLK_SRC_SEL;
755 else 690 else
756 reg &= ~WM9081_CLK_SRC_SEL; 691 reg &= ~WM9081_CLK_SRC_SEL;
757 wm9081_write(codec, WM9081_CLOCK_CONTROL_3, reg); 692 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
758 693
759 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate); 694 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
760 695
@@ -854,76 +789,76 @@ static int wm9081_set_bias_level(struct snd_soc_codec *codec,
854 789
855 case SND_SOC_BIAS_PREPARE: 790 case SND_SOC_BIAS_PREPARE:
856 /* VMID=2*40k */ 791 /* VMID=2*40k */
857 reg = wm9081_read(codec, WM9081_VMID_CONTROL); 792 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
858 reg &= ~WM9081_VMID_SEL_MASK; 793 reg &= ~WM9081_VMID_SEL_MASK;
859 reg |= 0x2; 794 reg |= 0x2;
860 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 795 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
861 796
862 /* Normal bias current */ 797 /* Normal bias current */
863 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 798 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
864 reg &= ~WM9081_STBY_BIAS_ENA; 799 reg &= ~WM9081_STBY_BIAS_ENA;
865 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 800 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
866 break; 801 break;
867 802
868 case SND_SOC_BIAS_STANDBY: 803 case SND_SOC_BIAS_STANDBY:
869 /* Initial cold start */ 804 /* Initial cold start */
870 if (codec->bias_level == SND_SOC_BIAS_OFF) { 805 if (codec->bias_level == SND_SOC_BIAS_OFF) {
871 /* Disable LINEOUT discharge */ 806 /* Disable LINEOUT discharge */
872 reg = wm9081_read(codec, WM9081_ANTI_POP_CONTROL); 807 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
873 reg &= ~WM9081_LINEOUT_DISCH; 808 reg &= ~WM9081_LINEOUT_DISCH;
874 wm9081_write(codec, WM9081_ANTI_POP_CONTROL, reg); 809 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
875 810
876 /* Select startup bias source */ 811 /* Select startup bias source */
877 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 812 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
878 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA; 813 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
879 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 814 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
880 815
881 /* VMID 2*4k; Soft VMID ramp enable */ 816 /* VMID 2*4k; Soft VMID ramp enable */
882 reg = wm9081_read(codec, WM9081_VMID_CONTROL); 817 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
883 reg |= WM9081_VMID_RAMP | 0x6; 818 reg |= WM9081_VMID_RAMP | 0x6;
884 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 819 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
885 820
886 mdelay(100); 821 mdelay(100);
887 822
888 /* Normal bias enable & soft start off */ 823 /* Normal bias enable & soft start off */
889 reg |= WM9081_BIAS_ENA; 824 reg |= WM9081_BIAS_ENA;
890 reg &= ~WM9081_VMID_RAMP; 825 reg &= ~WM9081_VMID_RAMP;
891 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 826 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
892 827
893 /* Standard bias source */ 828 /* Standard bias source */
894 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 829 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
895 reg &= ~WM9081_BIAS_SRC; 830 reg &= ~WM9081_BIAS_SRC;
896 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 831 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
897 } 832 }
898 833
899 /* VMID 2*240k */ 834 /* VMID 2*240k */
900 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 835 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
901 reg &= ~WM9081_VMID_SEL_MASK; 836 reg &= ~WM9081_VMID_SEL_MASK;
902 reg |= 0x40; 837 reg |= 0x40;
903 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 838 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
904 839
905 /* Standby bias current on */ 840 /* Standby bias current on */
906 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 841 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
907 reg |= WM9081_STBY_BIAS_ENA; 842 reg |= WM9081_STBY_BIAS_ENA;
908 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 843 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
909 break; 844 break;
910 845
911 case SND_SOC_BIAS_OFF: 846 case SND_SOC_BIAS_OFF:
912 /* Startup bias source */ 847 /* Startup bias source */
913 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1); 848 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
914 reg |= WM9081_BIAS_SRC; 849 reg |= WM9081_BIAS_SRC;
915 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg); 850 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
916 851
917 /* Disable VMID and biases with soft ramping */ 852 /* Disable VMID and biases with soft ramping */
918 reg = wm9081_read(codec, WM9081_VMID_CONTROL); 853 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
919 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA); 854 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA);
920 reg |= WM9081_VMID_RAMP; 855 reg |= WM9081_VMID_RAMP;
921 wm9081_write(codec, WM9081_VMID_CONTROL, reg); 856 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
922 857
923 /* Actively discharge LINEOUT */ 858 /* Actively discharge LINEOUT */
924 reg = wm9081_read(codec, WM9081_ANTI_POP_CONTROL); 859 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
925 reg |= WM9081_LINEOUT_DISCH; 860 reg |= WM9081_LINEOUT_DISCH;
926 wm9081_write(codec, WM9081_ANTI_POP_CONTROL, reg); 861 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
927 break; 862 break;
928 } 863 }
929 864
@@ -937,7 +872,7 @@ static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
937{ 872{
938 struct snd_soc_codec *codec = dai->codec; 873 struct snd_soc_codec *codec = dai->codec;
939 struct wm9081_priv *wm9081 = codec->private_data; 874 struct wm9081_priv *wm9081 = codec->private_data;
940 unsigned int aif2 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_2); 875 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
941 876
942 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV | 877 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
943 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK); 878 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
@@ -1018,7 +953,7 @@ static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
1018 return -EINVAL; 953 return -EINVAL;
1019 } 954 }
1020 955
1021 wm9081_write(codec, WM9081_AUDIO_INTERFACE_2, aif2); 956 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1022 957
1023 return 0; 958 return 0;
1024} 959}
@@ -1032,18 +967,18 @@ static int wm9081_hw_params(struct snd_pcm_substream *substream,
1032 int ret, i, best, best_val, cur_val; 967 int ret, i, best, best_val, cur_val;
1033 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4; 968 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
1034 969
1035 clk_ctrl2 = wm9081_read(codec, WM9081_CLOCK_CONTROL_2); 970 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
1036 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK); 971 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
1037 972
1038 aif1 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_1); 973 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1039 974
1040 aif2 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_2); 975 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
1041 aif2 &= ~WM9081_AIF_WL_MASK; 976 aif2 &= ~WM9081_AIF_WL_MASK;
1042 977
1043 aif3 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_3); 978 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
1044 aif3 &= ~WM9081_BCLK_DIV_MASK; 979 aif3 &= ~WM9081_BCLK_DIV_MASK;
1045 980
1046 aif4 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_4); 981 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
1047 aif4 &= ~WM9081_LRCLK_RATE_MASK; 982 aif4 &= ~WM9081_LRCLK_RATE_MASK;
1048 983
1049 /* What BCLK do we need? */ 984 /* What BCLK do we need? */
@@ -1157,22 +1092,22 @@ static int wm9081_hw_params(struct snd_pcm_substream *substream,
1157 s->name, s->rate); 1092 s->name, s->rate);
1158 1093
1159 /* If the EQ is enabled then disable it while we write out */ 1094 /* If the EQ is enabled then disable it while we write out */
1160 eq1 = wm9081_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA; 1095 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
1161 if (eq1 & WM9081_EQ_ENA) 1096 if (eq1 & WM9081_EQ_ENA)
1162 wm9081_write(codec, WM9081_EQ_1, 0); 1097 snd_soc_write(codec, WM9081_EQ_1, 0);
1163 1098
1164 /* Write out the other values */ 1099 /* Write out the other values */
1165 for (i = 1; i < ARRAY_SIZE(s->config); i++) 1100 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1166 wm9081_write(codec, WM9081_EQ_1 + i, s->config[i]); 1101 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
1167 1102
1168 eq1 |= (s->config[0] & ~WM9081_EQ_ENA); 1103 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
1169 wm9081_write(codec, WM9081_EQ_1, eq1); 1104 snd_soc_write(codec, WM9081_EQ_1, eq1);
1170 } 1105 }
1171 1106
1172 wm9081_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2); 1107 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1173 wm9081_write(codec, WM9081_AUDIO_INTERFACE_2, aif2); 1108 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1174 wm9081_write(codec, WM9081_AUDIO_INTERFACE_3, aif3); 1109 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1175 wm9081_write(codec, WM9081_AUDIO_INTERFACE_4, aif4); 1110 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
1176 1111
1177 return 0; 1112 return 0;
1178} 1113}
@@ -1182,14 +1117,14 @@ static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1182 struct snd_soc_codec *codec = codec_dai->codec; 1117 struct snd_soc_codec *codec = codec_dai->codec;
1183 unsigned int reg; 1118 unsigned int reg;
1184 1119
1185 reg = wm9081_read(codec, WM9081_DAC_DIGITAL_2); 1120 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
1186 1121
1187 if (mute) 1122 if (mute)
1188 reg |= WM9081_DAC_MUTE; 1123 reg |= WM9081_DAC_MUTE;
1189 else 1124 else
1190 reg &= ~WM9081_DAC_MUTE; 1125 reg &= ~WM9081_DAC_MUTE;
1191 1126
1192 wm9081_write(codec, WM9081_DAC_DIGITAL_2, reg); 1127 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
1193 1128
1194 return 0; 1129 return 0;
1195} 1130}
@@ -1218,7 +1153,7 @@ static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1218 unsigned int mask, int slots) 1153 unsigned int mask, int slots)
1219{ 1154{
1220 struct snd_soc_codec *codec = dai->codec; 1155 struct snd_soc_codec *codec = dai->codec;
1221 unsigned int aif1 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_1); 1156 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1222 1157
1223 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK); 1158 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1224 1159
@@ -1243,7 +1178,7 @@ static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1243 return -EINVAL; 1178 return -EINVAL;
1244 } 1179 }
1245 1180
1246 wm9081_write(codec, WM9081_AUDIO_INTERFACE_1, aif1); 1181 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
1247 1182
1248 return 0; 1183 return 0;
1249} 1184}
@@ -1365,7 +1300,7 @@ static int wm9081_resume(struct platform_device *pdev)
1365 if (i == WM9081_SOFTWARE_RESET) 1300 if (i == WM9081_SOFTWARE_RESET)
1366 continue; 1301 continue;
1367 1302
1368 wm9081_write(codec, i, reg_cache[i]); 1303 snd_soc_write(codec, i, reg_cache[i]);
1369 } 1304 }
1370 1305
1371 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1306 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
@@ -1385,7 +1320,8 @@ struct snd_soc_codec_device soc_codec_dev_wm9081 = {
1385}; 1320};
1386EXPORT_SYMBOL_GPL(soc_codec_dev_wm9081); 1321EXPORT_SYMBOL_GPL(soc_codec_dev_wm9081);
1387 1322
1388static int wm9081_register(struct wm9081_priv *wm9081) 1323static int wm9081_register(struct wm9081_priv *wm9081,
1324 enum snd_soc_control_type control)
1389{ 1325{
1390 struct snd_soc_codec *codec = &wm9081->codec; 1326 struct snd_soc_codec *codec = &wm9081->codec;
1391 int ret; 1327 int ret;
@@ -1404,19 +1340,24 @@ static int wm9081_register(struct wm9081_priv *wm9081)
1404 codec->private_data = wm9081; 1340 codec->private_data = wm9081;
1405 codec->name = "WM9081"; 1341 codec->name = "WM9081";
1406 codec->owner = THIS_MODULE; 1342 codec->owner = THIS_MODULE;
1407 codec->read = wm9081_read;
1408 codec->write = wm9081_write;
1409 codec->dai = &wm9081_dai; 1343 codec->dai = &wm9081_dai;
1410 codec->num_dai = 1; 1344 codec->num_dai = 1;
1411 codec->reg_cache_size = ARRAY_SIZE(wm9081->reg_cache); 1345 codec->reg_cache_size = ARRAY_SIZE(wm9081->reg_cache);
1412 codec->reg_cache = &wm9081->reg_cache; 1346 codec->reg_cache = &wm9081->reg_cache;
1413 codec->bias_level = SND_SOC_BIAS_OFF; 1347 codec->bias_level = SND_SOC_BIAS_OFF;
1414 codec->set_bias_level = wm9081_set_bias_level; 1348 codec->set_bias_level = wm9081_set_bias_level;
1349 codec->volatile_register = wm9081_volatile_register;
1415 1350
1416 memcpy(codec->reg_cache, wm9081_reg_defaults, 1351 memcpy(codec->reg_cache, wm9081_reg_defaults,
1417 sizeof(wm9081_reg_defaults)); 1352 sizeof(wm9081_reg_defaults));
1418 1353
1419 reg = wm9081_read_hw(codec, WM9081_SOFTWARE_RESET); 1354 ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
1355 if (ret != 0) {
1356 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1357 return ret;
1358 }
1359
1360 reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET);
1420 if (reg != 0x9081) { 1361 if (reg != 0x9081) {
1421 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg); 1362 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1422 ret = -EINVAL; 1363 ret = -EINVAL;
@@ -1432,10 +1373,10 @@ static int wm9081_register(struct wm9081_priv *wm9081)
1432 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1373 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1433 1374
1434 /* Enable zero cross by default */ 1375 /* Enable zero cross by default */
1435 reg = wm9081_read(codec, WM9081_ANALOGUE_LINEOUT); 1376 reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
1436 wm9081_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC); 1377 snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
1437 reg = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_PGA); 1378 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
1438 wm9081_write(codec, WM9081_ANALOGUE_SPEAKER_PGA, 1379 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1439 reg | WM9081_SPKPGAZC); 1380 reg | WM9081_SPKPGAZC);
1440 1381
1441 wm9081_dai.dev = codec->dev; 1382 wm9081_dai.dev = codec->dev;
@@ -1490,7 +1431,7 @@ static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1490 1431
1491 codec->dev = &i2c->dev; 1432 codec->dev = &i2c->dev;
1492 1433
1493 return wm9081_register(wm9081); 1434 return wm9081_register(wm9081, SND_SOC_I2C);
1494} 1435}
1495 1436
1496static __devexit int wm9081_i2c_remove(struct i2c_client *client) 1437static __devexit int wm9081_i2c_remove(struct i2c_client *client)
diff --git a/sound/soc/soc-cache.c b/sound/soc/soc-cache.c
new file mode 100644
index 000000000000..56ec3f22bf1c
--- /dev/null
+++ b/sound/soc/soc-cache.c
@@ -0,0 +1,218 @@
1/*
2 * soc-cache.c -- ASoC register cache helpers
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/i2c.h>
15#include <linux/spi/spi.h>
16#include <sound/soc.h>
17
18static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
19 unsigned int reg)
20{
21 u16 *cache = codec->reg_cache;
22 if (reg >= codec->reg_cache_size)
23 return -1;
24 return cache[reg];
25}
26
27static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
28 unsigned int value)
29{
30 u16 *cache = codec->reg_cache;
31 u8 data[2];
32 int ret;
33
34 BUG_ON(codec->volatile_register);
35
36 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
37 data[1] = value & 0x00ff;
38
39 if (reg < codec->reg_cache_size)
40 cache[reg] = value;
41 ret = codec->hw_write(codec->control_data, data, 2);
42 if (ret == 2)
43 return 0;
44 if (ret < 0)
45 return ret;
46 else
47 return -EIO;
48}
49
50#if defined(CONFIG_SPI_MASTER)
51static int snd_soc_7_9_spi_write(void *control_data, const char *data,
52 int len)
53{
54 struct spi_device *spi = control_data;
55 struct spi_transfer t;
56 struct spi_message m;
57 u8 msg[2];
58
59 if (len <= 0)
60 return 0;
61
62 msg[0] = data[0];
63 msg[1] = data[1];
64
65 spi_message_init(&m);
66 memset(&t, 0, (sizeof t));
67
68 t.tx_buf = &msg[0];
69 t.len = len;
70
71 spi_message_add_tail(&t, &m);
72 spi_sync(spi, &m);
73
74 return len;
75}
76#else
77#define snd_soc_7_9_spi_write NULL
78#endif
79
80static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
81 unsigned int value)
82{
83 u16 *reg_cache = codec->reg_cache;
84 u8 data[3];
85
86 data[0] = reg;
87 data[1] = (value >> 8) & 0xff;
88 data[2] = value & 0xff;
89
90 if (!snd_soc_codec_volatile_register(codec, reg))
91 reg_cache[reg] = value;
92
93 if (codec->hw_write(codec->control_data, data, 3) == 3)
94 return 0;
95 else
96 return -EIO;
97}
98
99static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
100 unsigned int reg)
101{
102 u16 *cache = codec->reg_cache;
103
104 if (reg >= codec->reg_cache_size ||
105 snd_soc_codec_volatile_register(codec, reg))
106 return codec->hw_read(codec, reg);
107 else
108 return cache[reg];
109}
110
111#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
112static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
113 unsigned int r)
114{
115 struct i2c_msg xfer[2];
116 u8 reg = r;
117 u16 data;
118 int ret;
119 struct i2c_client *client = codec->control_data;
120
121 /* Write register */
122 xfer[0].addr = client->addr;
123 xfer[0].flags = 0;
124 xfer[0].len = 1;
125 xfer[0].buf = &reg;
126
127 /* Read data */
128 xfer[1].addr = client->addr;
129 xfer[1].flags = I2C_M_RD;
130 xfer[1].len = 2;
131 xfer[1].buf = (u8 *)&data;
132
133 ret = i2c_transfer(client->adapter, xfer, 2);
134 if (ret != 2) {
135 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
136 return 0;
137 }
138
139 return (data >> 8) | ((data & 0xff) << 8);
140}
141#else
142#define snd_soc_8_16_read_i2c NULL
143#endif
144
145static struct {
146 int addr_bits;
147 int data_bits;
148 int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
149 int (*spi_write)(void *, const char *, int);
150 unsigned int (*read)(struct snd_soc_codec *, unsigned int);
151 unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
152} io_types[] = {
153 { 7, 9, snd_soc_7_9_write, snd_soc_7_9_spi_write, snd_soc_7_9_read },
154 { 8, 16, snd_soc_8_16_write, NULL, snd_soc_8_16_read,
155 snd_soc_8_16_read_i2c },
156};
157
158/**
159 * snd_soc_codec_set_cache_io: Set up standard I/O functions.
160 *
161 * @codec: CODEC to configure.
162 * @type: Type of cache.
163 * @addr_bits: Number of bits of register address data.
164 * @data_bits: Number of bits of data per register.
165 * @control: Control bus used.
166 *
167 * Register formats are frequently shared between many I2C and SPI
168 * devices. In order to promote code reuse the ASoC core provides
169 * some standard implementations of CODEC read and write operations
170 * which can be set up using this function.
171 *
172 * The caller is responsible for allocating and initialising the
173 * actual cache.
174 *
175 * Note that at present this code cannot be used by CODECs with
176 * volatile registers.
177 */
178int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
179 int addr_bits, int data_bits,
180 enum snd_soc_control_type control)
181{
182 int i;
183
184 for (i = 0; i < ARRAY_SIZE(io_types); i++)
185 if (io_types[i].addr_bits == addr_bits &&
186 io_types[i].data_bits == data_bits)
187 break;
188 if (i == ARRAY_SIZE(io_types)) {
189 printk(KERN_ERR
190 "No I/O functions for %d bit address %d bit data\n",
191 addr_bits, data_bits);
192 return -EINVAL;
193 }
194
195 codec->write = io_types[i].write;
196 codec->read = io_types[i].read;
197
198 switch (control) {
199 case SND_SOC_CUSTOM:
200 break;
201
202 case SND_SOC_I2C:
203#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
204 codec->hw_write = (hw_write_t)i2c_master_send;
205#endif
206 if (io_types[i].i2c_read)
207 codec->hw_read = io_types[i].i2c_read;
208 break;
209
210 case SND_SOC_SPI:
211 if (io_types[i].spi_write)
212 codec->hw_write = io_types[i].spi_write;
213 break;
214 }
215
216 return 0;
217}
218EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 14:01:45 -0500