diff options
Diffstat (limited to 'sound/soc')
-rw-r--r-- | sound/soc/codecs/wm8985.c | 43 |
1 files changed, 20 insertions, 23 deletions
diff --git a/sound/soc/codecs/wm8985.c b/sound/soc/codecs/wm8985.c index ab3782657ac8..dd6ce3bc01cf 100644 --- a/sound/soc/codecs/wm8985.c +++ b/sound/soc/codecs/wm8985.c | |||
@@ -830,33 +830,30 @@ static int wm8985_set_pll(struct snd_soc_dai *dai, int pll_id, | |||
830 | struct pll_div pll_div; | 830 | struct pll_div pll_div; |
831 | 831 | ||
832 | codec = dai->codec; | 832 | codec = dai->codec; |
833 | if (freq_in && freq_out) { | 833 | if (!freq_in || !freq_out) { |
834 | /* disable the PLL */ | ||
835 | snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1, | ||
836 | WM8985_PLLEN_MASK, 0); | ||
837 | } else { | ||
834 | ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in); | 838 | ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in); |
835 | if (ret) | 839 | if (ret) |
836 | return ret; | 840 | return ret; |
837 | } | ||
838 | 841 | ||
839 | /* disable the PLL before reprogramming it */ | 842 | /* set PLLN and PRESCALE */ |
840 | snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1, | 843 | snd_soc_write(codec, WM8985_PLL_N, |
841 | WM8985_PLLEN_MASK, 0); | 844 | (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT) |
842 | 845 | | pll_div.n); | |
843 | if (!freq_in || !freq_out) | 846 | /* set PLLK */ |
844 | return 0; | 847 | snd_soc_write(codec, WM8985_PLL_K_3, pll_div.k & 0x1ff); |
845 | 848 | snd_soc_write(codec, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff); | |
846 | /* set PLLN and PRESCALE */ | 849 | snd_soc_write(codec, WM8985_PLL_K_1, (pll_div.k >> 18)); |
847 | snd_soc_write(codec, WM8985_PLL_N, | 850 | /* set the source of the clock to be the PLL */ |
848 | (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT) | 851 | snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL, |
849 | | pll_div.n); | 852 | WM8985_CLKSEL_MASK, WM8985_CLKSEL); |
850 | /* set PLLK */ | 853 | /* enable the PLL */ |
851 | snd_soc_write(codec, WM8985_PLL_K_3, pll_div.k & 0x1ff); | 854 | snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1, |
852 | snd_soc_write(codec, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff); | 855 | WM8985_PLLEN_MASK, WM8985_PLLEN); |
853 | snd_soc_write(codec, WM8985_PLL_K_1, (pll_div.k >> 18)); | 856 | } |
854 | /* set the source of the clock to be the PLL */ | ||
855 | snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL, | ||
856 | WM8985_CLKSEL_MASK, WM8985_CLKSEL); | ||
857 | /* enable the PLL */ | ||
858 | snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1, | ||
859 | WM8985_PLLEN_MASK, WM8985_PLLEN); | ||
860 | return 0; | 857 | return 0; |
861 | } | 858 | } |
862 | 859 | ||