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Diffstat (limited to 'sound/soc/samsung/ac97.c')
-rw-r--r--sound/soc/samsung/ac97.c520
1 files changed, 520 insertions, 0 deletions
diff --git a/sound/soc/samsung/ac97.c b/sound/soc/samsung/ac97.c
new file mode 100644
index 000000000000..4770a9550341
--- /dev/null
+++ b/sound/soc/samsung/ac97.c
@@ -0,0 +1,520 @@
1/* sound/soc/samsung/ac97.c
2 *
3 * ALSA SoC Audio Layer - S3C AC97 Controller driver
4 * Evolved from s3c2443-ac97.c
5 *
6 * Copyright (c) 2010 Samsung Electronics Co. Ltd
7 * Author: Jaswinder Singh <jassi.brar@samsung.com>
8 * Credits: Graeme Gregory, Sean Choi
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/io.h>
18#include <linux/delay.h>
19#include <linux/clk.h>
20
21#include <sound/soc.h>
22
23#include <plat/regs-ac97.h>
24#include <mach/dma.h>
25#include <plat/audio.h>
26
27#include "dma.h"
28#include "ac97.h"
29
30#define AC_CMD_ADDR(x) (x << 16)
31#define AC_CMD_DATA(x) (x & 0xffff)
32
33struct s3c_ac97_info {
34 struct clk *ac97_clk;
35 void __iomem *regs;
36 struct mutex lock;
37 struct completion done;
38};
39static struct s3c_ac97_info s3c_ac97;
40
41static struct s3c2410_dma_client s3c_dma_client_out = {
42 .name = "AC97 PCMOut"
43};
44
45static struct s3c2410_dma_client s3c_dma_client_in = {
46 .name = "AC97 PCMIn"
47};
48
49static struct s3c2410_dma_client s3c_dma_client_micin = {
50 .name = "AC97 MicIn"
51};
52
53static struct s3c_dma_params s3c_ac97_pcm_out = {
54 .client = &s3c_dma_client_out,
55 .dma_size = 4,
56};
57
58static struct s3c_dma_params s3c_ac97_pcm_in = {
59 .client = &s3c_dma_client_in,
60 .dma_size = 4,
61};
62
63static struct s3c_dma_params s3c_ac97_mic_in = {
64 .client = &s3c_dma_client_micin,
65 .dma_size = 4,
66};
67
68static void s3c_ac97_activate(struct snd_ac97 *ac97)
69{
70 u32 ac_glbctrl, stat;
71
72 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
73 if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
74 return; /* Return if already active */
75
76 INIT_COMPLETION(s3c_ac97.done);
77
78 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
79 ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
80 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
81 msleep(1);
82
83 ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
84 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
85 msleep(1);
86
87 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
88 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
89 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
90
91 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
92 pr_err("AC97: Unable to activate!");
93}
94
95static unsigned short s3c_ac97_read(struct snd_ac97 *ac97,
96 unsigned short reg)
97{
98 u32 ac_glbctrl, ac_codec_cmd;
99 u32 stat, addr, data;
100
101 mutex_lock(&s3c_ac97.lock);
102
103 s3c_ac97_activate(ac97);
104
105 INIT_COMPLETION(s3c_ac97.done);
106
107 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
108 ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
109 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
110
111 udelay(50);
112
113 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
114 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
115 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
116
117 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
118 pr_err("AC97: Unable to read!");
119
120 stat = readl(s3c_ac97.regs + S3C_AC97_STAT);
121 addr = (stat >> 16) & 0x7f;
122 data = (stat & 0xffff);
123
124 if (addr != reg)
125 pr_err("ac97: req addr = %02x, rep addr = %02x\n",
126 reg, addr);
127
128 mutex_unlock(&s3c_ac97.lock);
129
130 return (unsigned short)data;
131}
132
133static void s3c_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
134 unsigned short val)
135{
136 u32 ac_glbctrl, ac_codec_cmd;
137
138 mutex_lock(&s3c_ac97.lock);
139
140 s3c_ac97_activate(ac97);
141
142 INIT_COMPLETION(s3c_ac97.done);
143
144 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
145 ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
146 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
147
148 udelay(50);
149
150 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
151 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
152 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
153
154 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
155 pr_err("AC97: Unable to write!");
156
157 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
158 ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
159 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
160
161 mutex_unlock(&s3c_ac97.lock);
162}
163
164static void s3c_ac97_cold_reset(struct snd_ac97 *ac97)
165{
166 pr_debug("AC97: Cold reset\n");
167 writel(S3C_AC97_GLBCTRL_COLDRESET,
168 s3c_ac97.regs + S3C_AC97_GLBCTRL);
169 msleep(1);
170
171 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
172 msleep(1);
173}
174
175static void s3c_ac97_warm_reset(struct snd_ac97 *ac97)
176{
177 u32 stat;
178
179 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
180 if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
181 return; /* Return if already active */
182
183 pr_debug("AC97: Warm reset\n");
184
185 writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL);
186 msleep(1);
187
188 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
189 msleep(1);
190
191 s3c_ac97_activate(ac97);
192}
193
194static irqreturn_t s3c_ac97_irq(int irq, void *dev_id)
195{
196 u32 ac_glbctrl, ac_glbstat;
197
198 ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT);
199
200 if (ac_glbstat & S3C_AC97_GLBSTAT_CODECREADY) {
201
202 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
203 ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
204 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
205
206 complete(&s3c_ac97.done);
207 }
208
209 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
210 ac_glbctrl |= (1<<30); /* Clear interrupt */
211 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
212
213 return IRQ_HANDLED;
214}
215
216struct snd_ac97_bus_ops soc_ac97_ops = {
217 .read = s3c_ac97_read,
218 .write = s3c_ac97_write,
219 .warm_reset = s3c_ac97_warm_reset,
220 .reset = s3c_ac97_cold_reset,
221};
222EXPORT_SYMBOL_GPL(soc_ac97_ops);
223
224static int s3c_ac97_hw_params(struct snd_pcm_substream *substream,
225 struct snd_pcm_hw_params *params,
226 struct snd_soc_dai *dai)
227{
228 struct snd_soc_pcm_runtime *rtd = substream->private_data;
229 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
230 struct s3c_dma_params *dma_data;
231
232 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
233 dma_data = &s3c_ac97_pcm_out;
234 else
235 dma_data = &s3c_ac97_pcm_in;
236
237 snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
238
239 return 0;
240}
241
242static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
243 struct snd_soc_dai *dai)
244{
245 u32 ac_glbctrl;
246 struct snd_soc_pcm_runtime *rtd = substream->private_data;
247 struct s3c_dma_params *dma_data =
248 snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
249
250 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
251 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
252 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
253 else
254 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
255
256 switch (cmd) {
257 case SNDRV_PCM_TRIGGER_START:
258 case SNDRV_PCM_TRIGGER_RESUME:
259 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
260 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
261 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
262 else
263 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
264 break;
265
266 case SNDRV_PCM_TRIGGER_STOP:
267 case SNDRV_PCM_TRIGGER_SUSPEND:
268 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
269 break;
270 }
271
272 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
273
274 s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
275
276 return 0;
277}
278
279static int s3c_ac97_hw_mic_params(struct snd_pcm_substream *substream,
280 struct snd_pcm_hw_params *params,
281 struct snd_soc_dai *dai)
282{
283 struct snd_soc_pcm_runtime *rtd = substream->private_data;
284 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
285
286 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
287 return -ENODEV;
288 else
289 snd_soc_dai_set_dma_data(cpu_dai, substream, &s3c_ac97_mic_in);
290
291 return 0;
292}
293
294static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream,
295 int cmd, struct snd_soc_dai *dai)
296{
297 u32 ac_glbctrl;
298 struct snd_soc_pcm_runtime *rtd = substream->private_data;
299 struct s3c_dma_params *dma_data =
300 snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
301
302 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
303 ac_glbctrl &= ~S3C_AC97_GLBCTRL_MICINTM_MASK;
304
305 switch (cmd) {
306 case SNDRV_PCM_TRIGGER_START:
307 case SNDRV_PCM_TRIGGER_RESUME:
308 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
309 ac_glbctrl |= S3C_AC97_GLBCTRL_MICINTM_DMA;
310 break;
311
312 case SNDRV_PCM_TRIGGER_STOP:
313 case SNDRV_PCM_TRIGGER_SUSPEND:
314 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
315 break;
316 }
317
318 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
319
320 s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
321
322 return 0;
323}
324
325static struct snd_soc_dai_ops s3c_ac97_dai_ops = {
326 .hw_params = s3c_ac97_hw_params,
327 .trigger = s3c_ac97_trigger,
328};
329
330static struct snd_soc_dai_ops s3c_ac97_mic_dai_ops = {
331 .hw_params = s3c_ac97_hw_mic_params,
332 .trigger = s3c_ac97_mic_trigger,
333};
334
335static struct snd_soc_dai_driver s3c_ac97_dai[] = {
336 [S3C_AC97_DAI_PCM] = {
337 .name = "samsung-ac97",
338 .ac97_control = 1,
339 .playback = {
340 .stream_name = "AC97 Playback",
341 .channels_min = 2,
342 .channels_max = 2,
343 .rates = SNDRV_PCM_RATE_8000_48000,
344 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
345 .capture = {
346 .stream_name = "AC97 Capture",
347 .channels_min = 2,
348 .channels_max = 2,
349 .rates = SNDRV_PCM_RATE_8000_48000,
350 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
351 .ops = &s3c_ac97_dai_ops,
352 },
353 [S3C_AC97_DAI_MIC] = {
354 .name = "samsung-ac97-mic",
355 .ac97_control = 1,
356 .capture = {
357 .stream_name = "AC97 Mic Capture",
358 .channels_min = 1,
359 .channels_max = 1,
360 .rates = SNDRV_PCM_RATE_8000_48000,
361 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
362 .ops = &s3c_ac97_mic_dai_ops,
363 },
364};
365
366static __devinit int s3c_ac97_probe(struct platform_device *pdev)
367{
368 struct resource *mem_res, *dmatx_res, *dmarx_res, *dmamic_res, *irq_res;
369 struct s3c_audio_pdata *ac97_pdata;
370 int ret;
371
372 ac97_pdata = pdev->dev.platform_data;
373 if (!ac97_pdata || !ac97_pdata->cfg_gpio) {
374 dev_err(&pdev->dev, "cfg_gpio callback not provided!\n");
375 return -EINVAL;
376 }
377
378 /* Check for availability of necessary resource */
379 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
380 if (!dmatx_res) {
381 dev_err(&pdev->dev, "Unable to get AC97-TX dma resource\n");
382 return -ENXIO;
383 }
384
385 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
386 if (!dmarx_res) {
387 dev_err(&pdev->dev, "Unable to get AC97-RX dma resource\n");
388 return -ENXIO;
389 }
390
391 dmamic_res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
392 if (!dmamic_res) {
393 dev_err(&pdev->dev, "Unable to get AC97-MIC dma resource\n");
394 return -ENXIO;
395 }
396
397 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
398 if (!mem_res) {
399 dev_err(&pdev->dev, "Unable to get register resource\n");
400 return -ENXIO;
401 }
402
403 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
404 if (!irq_res) {
405 dev_err(&pdev->dev, "AC97 IRQ not provided!\n");
406 return -ENXIO;
407 }
408
409 if (!request_mem_region(mem_res->start,
410 resource_size(mem_res), "ac97")) {
411 dev_err(&pdev->dev, "Unable to request register region\n");
412 return -EBUSY;
413 }
414
415 s3c_ac97_pcm_out.channel = dmatx_res->start;
416 s3c_ac97_pcm_out.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
417 s3c_ac97_pcm_in.channel = dmarx_res->start;
418 s3c_ac97_pcm_in.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
419 s3c_ac97_mic_in.channel = dmamic_res->start;
420 s3c_ac97_mic_in.dma_addr = mem_res->start + S3C_AC97_MIC_DATA;
421
422 init_completion(&s3c_ac97.done);
423 mutex_init(&s3c_ac97.lock);
424
425 s3c_ac97.regs = ioremap(mem_res->start, resource_size(mem_res));
426 if (s3c_ac97.regs == NULL) {
427 dev_err(&pdev->dev, "Unable to ioremap register region\n");
428 ret = -ENXIO;
429 goto err1;
430 }
431
432 s3c_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
433 if (IS_ERR(s3c_ac97.ac97_clk)) {
434 dev_err(&pdev->dev, "ac97 failed to get ac97_clock\n");
435 ret = -ENODEV;
436 goto err2;
437 }
438 clk_enable(s3c_ac97.ac97_clk);
439
440 if (ac97_pdata->cfg_gpio(pdev)) {
441 dev_err(&pdev->dev, "Unable to configure gpio\n");
442 ret = -EINVAL;
443 goto err3;
444 }
445
446 ret = request_irq(irq_res->start, s3c_ac97_irq,
447 IRQF_DISABLED, "AC97", NULL);
448 if (ret < 0) {
449 dev_err(&pdev->dev, "ac97: interrupt request failed.\n");
450 goto err4;
451 }
452
453 ret = snd_soc_register_dais(&pdev->dev, s3c_ac97_dai,
454 ARRAY_SIZE(s3c_ac97_dai));
455 if (ret)
456 goto err5;
457
458 return 0;
459
460err5:
461 free_irq(irq_res->start, NULL);
462err4:
463err3:
464 clk_disable(s3c_ac97.ac97_clk);
465 clk_put(s3c_ac97.ac97_clk);
466err2:
467 iounmap(s3c_ac97.regs);
468err1:
469 release_mem_region(mem_res->start, resource_size(mem_res));
470
471 return ret;
472}
473
474static __devexit int s3c_ac97_remove(struct platform_device *pdev)
475{
476 struct resource *mem_res, *irq_res;
477
478 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(s3c_ac97_dai));
479
480 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
481 if (irq_res)
482 free_irq(irq_res->start, NULL);
483
484 clk_disable(s3c_ac97.ac97_clk);
485 clk_put(s3c_ac97.ac97_clk);
486
487 iounmap(s3c_ac97.regs);
488
489 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
490 if (mem_res)
491 release_mem_region(mem_res->start, resource_size(mem_res));
492
493 return 0;
494}
495
496static struct platform_driver s3c_ac97_driver = {
497 .probe = s3c_ac97_probe,
498 .remove = s3c_ac97_remove,
499 .driver = {
500 .name = "samsung-ac97",
501 .owner = THIS_MODULE,
502 },
503};
504
505static int __init s3c_ac97_init(void)
506{
507 return platform_driver_register(&s3c_ac97_driver);
508}
509module_init(s3c_ac97_init);
510
511static void __exit s3c_ac97_exit(void)
512{
513 platform_driver_unregister(&s3c_ac97_driver);
514}
515module_exit(s3c_ac97_exit);
516
517MODULE_AUTHOR("Jaswinder Singh, <jassi.brar@samsung.com>");
518MODULE_DESCRIPTION("AC97 driver for the Samsung SoC");
519MODULE_LICENSE("GPL");
520MODULE_ALIAS("platform:samsung-ac97");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 06:36:47 -0500