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Diffstat (limited to 'sound/soc/s3c24xx/s3c2443-ac97.c')
-rw-r--r--sound/soc/s3c24xx/s3c2443-ac97.c432
1 files changed, 0 insertions, 432 deletions
diff --git a/sound/soc/s3c24xx/s3c2443-ac97.c b/sound/soc/s3c24xx/s3c2443-ac97.c
deleted file mode 100644
index 0191e3acb0b4..000000000000
--- a/sound/soc/s3c24xx/s3c2443-ac97.c
+++ /dev/null
@@ -1,432 +0,0 @@
1/*
2 * s3c2443-ac97.c -- ALSA Soc Audio Layer
3 *
4 * (c) 2007 Wolfson Microelectronics PLC.
5 * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
6 *
7 * Copyright (C) 2005, Sean Choi <sh428.choi@samsung.com>
8 * All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/wait.h>
21#include <linux/delay.h>
22#include <linux/gpio.h>
23#include <linux/clk.h>
24
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/ac97_codec.h>
28#include <sound/initval.h>
29#include <sound/soc.h>
30
31#include <mach/hardware.h>
32#include <plat/regs-ac97.h>
33#include <mach/regs-gpio.h>
34#include <mach/regs-clock.h>
35#include <asm/dma.h>
36#include <mach/dma.h>
37
38#include "s3c-dma.h"
39#include "s3c24xx-ac97.h"
40
41struct s3c24xx_ac97_info {
42 void __iomem *regs;
43 struct clk *ac97_clk;
44};
45static struct s3c24xx_ac97_info s3c24xx_ac97;
46
47static DECLARE_COMPLETION(ac97_completion);
48static u32 codec_ready;
49static DEFINE_MUTEX(ac97_mutex);
50
51static unsigned short s3c2443_ac97_read(struct snd_ac97 *ac97,
52 unsigned short reg)
53{
54 u32 ac_glbctrl;
55 u32 ac_codec_cmd;
56 u32 stat, addr, data;
57
58 mutex_lock(&ac97_mutex);
59
60 codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
61 ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
62 ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
63 writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
64
65 udelay(50);
66
67 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
68 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
69 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
70
71 wait_for_completion(&ac97_completion);
72
73 stat = readl(s3c24xx_ac97.regs + S3C_AC97_STAT);
74 addr = (stat >> 16) & 0x7f;
75 data = (stat & 0xffff);
76
77 if (addr != reg)
78 printk(KERN_ERR "s3c24xx-ac97: req addr = %02x,"
79 " rep addr = %02x\n", reg, addr);
80
81 mutex_unlock(&ac97_mutex);
82
83 return (unsigned short)data;
84}
85
86static void s3c2443_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
87 unsigned short val)
88{
89 u32 ac_glbctrl;
90 u32 ac_codec_cmd;
91
92 mutex_lock(&ac97_mutex);
93
94 codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
95 ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
96 ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
97 writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
98
99 udelay(50);
100
101 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
102 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
103 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
104
105 wait_for_completion(&ac97_completion);
106
107 ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
108 ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
109 writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
110
111 mutex_unlock(&ac97_mutex);
112
113}
114
115static void s3c2443_ac97_warm_reset(struct snd_ac97 *ac97)
116{
117 u32 ac_glbctrl;
118
119 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
120 ac_glbctrl = S3C_AC97_GLBCTRL_WARMRESET;
121 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
122 msleep(1);
123
124 ac_glbctrl = 0;
125 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
126 msleep(1);
127}
128
129static void s3c2443_ac97_cold_reset(struct snd_ac97 *ac97)
130{
131 u32 ac_glbctrl;
132
133 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
134 ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
135 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
136 msleep(1);
137
138 ac_glbctrl = 0;
139 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
140 msleep(1);
141
142 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
143 ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
144 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
145 msleep(1);
146
147 ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
148 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
149 msleep(1);
150
151 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA |
152 S3C_AC97_GLBCTRL_PCMINTM_DMA | S3C_AC97_GLBCTRL_MICINTM_DMA;
153 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
154}
155
156static irqreturn_t s3c2443_ac97_irq(int irq, void *dev_id)
157{
158 int status;
159 u32 ac_glbctrl;
160
161 status = readl(s3c24xx_ac97.regs + S3C_AC97_GLBSTAT) & codec_ready;
162
163 if (status) {
164 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
165 ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
166 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
167 complete(&ac97_completion);
168 }
169 return IRQ_HANDLED;
170}
171
172struct snd_ac97_bus_ops soc_ac97_ops = {
173 .read = s3c2443_ac97_read,
174 .write = s3c2443_ac97_write,
175 .warm_reset = s3c2443_ac97_warm_reset,
176 .reset = s3c2443_ac97_cold_reset,
177};
178
179static struct s3c2410_dma_client s3c2443_dma_client_out = {
180 .name = "AC97 PCM Stereo out"
181};
182
183static struct s3c2410_dma_client s3c2443_dma_client_in = {
184 .name = "AC97 PCM Stereo in"
185};
186
187static struct s3c2410_dma_client s3c2443_dma_client_micin = {
188 .name = "AC97 Mic Mono in"
189};
190
191static struct s3c_dma_params s3c2443_ac97_pcm_stereo_out = {
192 .client = &s3c2443_dma_client_out,
193 .channel = DMACH_PCM_OUT,
194 .dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
195 .dma_size = 4,
196};
197
198static struct s3c_dma_params s3c2443_ac97_pcm_stereo_in = {
199 .client = &s3c2443_dma_client_in,
200 .channel = DMACH_PCM_IN,
201 .dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
202 .dma_size = 4,
203};
204
205static struct s3c_dma_params s3c2443_ac97_mic_mono_in = {
206 .client = &s3c2443_dma_client_micin,
207 .channel = DMACH_MIC_IN,
208 .dma_addr = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
209 .dma_size = 4,
210};
211
212static int s3c2443_ac97_probe(struct platform_device *pdev,
213 struct snd_soc_dai *dai)
214{
215 int ret;
216 u32 ac_glbctrl;
217
218 s3c24xx_ac97.regs = ioremap(S3C2440_PA_AC97, 0x100);
219 if (s3c24xx_ac97.regs == NULL)
220 return -ENXIO;
221
222 s3c24xx_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
223 if (s3c24xx_ac97.ac97_clk == NULL) {
224 printk(KERN_ERR "s3c2443-ac97 failed to get ac97_clock\n");
225 iounmap(s3c24xx_ac97.regs);
226 return -ENODEV;
227 }
228 clk_enable(s3c24xx_ac97.ac97_clk);
229
230 s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2443_GPE0_AC_nRESET);
231 s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2443_GPE1_AC_SYNC);
232 s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2443_GPE2_AC_BITCLK);
233 s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2443_GPE3_AC_SDI);
234 s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2443_GPE4_AC_SDO);
235
236 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
237 ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
238 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
239 msleep(1);
240
241 ac_glbctrl = 0;
242 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
243 msleep(1);
244
245 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
246 ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
247 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
248 msleep(1);
249
250 ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
251 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
252
253 ret = request_irq(IRQ_S3C244x_AC97, s3c2443_ac97_irq,
254 IRQF_DISABLED, "AC97", NULL);
255 if (ret < 0) {
256 printk(KERN_ERR "s3c24xx-ac97: interrupt request failed.\n");
257 clk_disable(s3c24xx_ac97.ac97_clk);
258 clk_put(s3c24xx_ac97.ac97_clk);
259 iounmap(s3c24xx_ac97.regs);
260 }
261 return ret;
262}
263
264static void s3c2443_ac97_remove(struct platform_device *pdev,
265 struct snd_soc_dai *dai)
266{
267 free_irq(IRQ_S3C244x_AC97, NULL);
268 clk_disable(s3c24xx_ac97.ac97_clk);
269 clk_put(s3c24xx_ac97.ac97_clk);
270 iounmap(s3c24xx_ac97.regs);
271}
272
273static int s3c2443_ac97_hw_params(struct snd_pcm_substream *substream,
274 struct snd_pcm_hw_params *params,
275 struct snd_soc_dai *dai)
276{
277 struct snd_soc_pcm_runtime *rtd = substream->private_data;
278 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
279
280 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
281 cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_out;
282 else
283 cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_in;
284
285 return 0;
286}
287
288static int s3c2443_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
289 struct snd_soc_dai *dai)
290{
291 u32 ac_glbctrl;
292 struct snd_soc_pcm_runtime *rtd = substream->private_data;
293 int channel = ((struct s3c_dma_params *)
294 rtd->dai->cpu_dai->dma_data)->channel;
295
296 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
297 switch (cmd) {
298 case SNDRV_PCM_TRIGGER_START:
299 case SNDRV_PCM_TRIGGER_RESUME:
300 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
301 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
302 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
303 else
304 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
305 break;
306 case SNDRV_PCM_TRIGGER_STOP:
307 case SNDRV_PCM_TRIGGER_SUSPEND:
308 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
309 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
310 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
311 else
312 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
313 break;
314 }
315 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
316
317 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED);
318
319 return 0;
320}
321
322static int s3c2443_ac97_hw_mic_params(struct snd_pcm_substream *substream,
323 struct snd_pcm_hw_params *params,
324 struct snd_soc_dai *dai)
325{
326 struct snd_soc_pcm_runtime *rtd = substream->private_data;
327 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
328
329 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
330 return -ENODEV;
331 else
332 cpu_dai->dma_data = &s3c2443_ac97_mic_mono_in;
333
334 return 0;
335}
336
337static int s3c2443_ac97_mic_trigger(struct snd_pcm_substream *substream,
338 int cmd, struct snd_soc_dai *dai)
339{
340 u32 ac_glbctrl;
341 struct snd_soc_pcm_runtime *rtd = substream->private_data;
342 int channel = ((struct s3c_dma_params *)
343 rtd->dai->cpu_dai->dma_data)->channel;
344
345 ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
346 switch (cmd) {
347 case SNDRV_PCM_TRIGGER_START:
348 case SNDRV_PCM_TRIGGER_RESUME:
349 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
350 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
351 break;
352 case SNDRV_PCM_TRIGGER_STOP:
353 case SNDRV_PCM_TRIGGER_SUSPEND:
354 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
355 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
356 }
357 writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
358
359 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED);
360
361 return 0;
362}
363
364#define s3c2443_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
365 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
366 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
367
368static struct snd_soc_dai_ops s3c2443_ac97_dai_ops = {
369 .hw_params = s3c2443_ac97_hw_params,
370 .trigger = s3c2443_ac97_trigger,
371};
372
373static struct snd_soc_dai_ops s3c2443_ac97_mic_dai_ops = {
374 .hw_params = s3c2443_ac97_hw_mic_params,
375 .trigger = s3c2443_ac97_mic_trigger,
376};
377
378struct snd_soc_dai s3c2443_ac97_dai[] = {
379{
380 .name = "s3c2443-ac97",
381 .id = 0,
382 .ac97_control = 1,
383 .probe = s3c2443_ac97_probe,
384 .remove = s3c2443_ac97_remove,
385 .playback = {
386 .stream_name = "AC97 Playback",
387 .channels_min = 2,
388 .channels_max = 2,
389 .rates = s3c2443_AC97_RATES,
390 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
391 .capture = {
392 .stream_name = "AC97 Capture",
393 .channels_min = 2,
394 .channels_max = 2,
395 .rates = s3c2443_AC97_RATES,
396 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
397 .ops = &s3c2443_ac97_dai_ops,
398},
399{
400 .name = "pxa2xx-ac97-mic",
401 .id = 1,
402 .ac97_control = 1,
403 .capture = {
404 .stream_name = "AC97 Mic Capture",
405 .channels_min = 1,
406 .channels_max = 1,
407 .rates = s3c2443_AC97_RATES,
408 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
409 .ops = &s3c2443_ac97_mic_dai_ops,
410},
411};
412EXPORT_SYMBOL_GPL(s3c2443_ac97_dai);
413EXPORT_SYMBOL_GPL(soc_ac97_ops);
414
415static int __init s3c2443_ac97_init(void)
416{
417 return snd_soc_register_dais(s3c2443_ac97_dai,
418 ARRAY_SIZE(s3c2443_ac97_dai));
419}
420module_init(s3c2443_ac97_init);
421
422static void __exit s3c2443_ac97_exit(void)
423{
424 snd_soc_unregister_dais(s3c2443_ac97_dai,
425 ARRAY_SIZE(s3c2443_ac97_dai));
426}
427module_exit(s3c2443_ac97_exit);
428
429
430MODULE_AUTHOR("Graeme Gregory");
431MODULE_DESCRIPTION("AC97 driver for the Samsung s3c2443 chip");
432MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 14:25:41 -0500