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Diffstat (limited to 'sound/soc/s3c24xx/s3c-ac97.c')
-rw-r--r--sound/soc/s3c24xx/s3c-ac97.c518
1 files changed, 518 insertions, 0 deletions
diff --git a/sound/soc/s3c24xx/s3c-ac97.c b/sound/soc/s3c24xx/s3c-ac97.c
new file mode 100644
index 000000000000..ee8ed9d7e703
--- /dev/null
+++ b/sound/soc/s3c24xx/s3c-ac97.c
@@ -0,0 +1,518 @@
1/* sound/soc/s3c24xx/s3c-ac97.c
2 *
3 * ALSA SoC Audio Layer - S3C AC97 Controller driver
4 * Evolved from s3c2443-ac97.c
5 *
6 * Copyright (c) 2010 Samsung Electronics Co. Ltd
7 * Author: Jaswinder Singh <jassi.brar@samsung.com>
8 * Credits: Graeme Gregory, Sean Choi
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/io.h>
18#include <linux/delay.h>
19#include <linux/clk.h>
20
21#include <sound/soc.h>
22
23#include <plat/regs-ac97.h>
24#include <mach/dma.h>
25#include <plat/audio.h>
26
27#include "s3c-dma.h"
28#include "s3c-ac97.h"
29
30#define AC_CMD_ADDR(x) (x << 16)
31#define AC_CMD_DATA(x) (x & 0xffff)
32
33struct s3c_ac97_info {
34 unsigned state;
35 struct clk *ac97_clk;
36 void __iomem *regs;
37 struct mutex lock;
38 struct completion done;
39};
40static struct s3c_ac97_info s3c_ac97;
41
42static struct s3c2410_dma_client s3c_dma_client_out = {
43 .name = "AC97 PCMOut"
44};
45
46static struct s3c2410_dma_client s3c_dma_client_in = {
47 .name = "AC97 PCMIn"
48};
49
50static struct s3c2410_dma_client s3c_dma_client_micin = {
51 .name = "AC97 MicIn"
52};
53
54static struct s3c_dma_params s3c_ac97_pcm_out = {
55 .client = &s3c_dma_client_out,
56 .dma_size = 4,
57};
58
59static struct s3c_dma_params s3c_ac97_pcm_in = {
60 .client = &s3c_dma_client_in,
61 .dma_size = 4,
62};
63
64static struct s3c_dma_params s3c_ac97_mic_in = {
65 .client = &s3c_dma_client_micin,
66 .dma_size = 4,
67};
68
69static void s3c_ac97_activate(struct snd_ac97 *ac97)
70{
71 u32 ac_glbctrl, stat;
72
73 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
74 if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
75 return; /* Return if already active */
76
77 INIT_COMPLETION(s3c_ac97.done);
78
79 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
80 ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
81 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
82 msleep(1);
83
84 ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
85 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
86 msleep(1);
87
88 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
89 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
90 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
91
92 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
93 printk(KERN_ERR "AC97: Unable to activate!");
94}
95
96static unsigned short s3c_ac97_read(struct snd_ac97 *ac97,
97 unsigned short reg)
98{
99 u32 ac_glbctrl, ac_codec_cmd;
100 u32 stat, addr, data;
101
102 mutex_lock(&s3c_ac97.lock);
103
104 s3c_ac97_activate(ac97);
105
106 INIT_COMPLETION(s3c_ac97.done);
107
108 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
109 ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
110 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
111
112 udelay(50);
113
114 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
115 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
116 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
117
118 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
119 printk(KERN_ERR "AC97: Unable to read!");
120
121 stat = readl(s3c_ac97.regs + S3C_AC97_STAT);
122 addr = (stat >> 16) & 0x7f;
123 data = (stat & 0xffff);
124
125 if (addr != reg)
126 printk(KERN_ERR "s3c-ac97: req addr = %02x, rep addr = %02x\n", reg, addr);
127
128 mutex_unlock(&s3c_ac97.lock);
129
130 return (unsigned short)data;
131}
132
133static void s3c_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
134 unsigned short val)
135{
136 u32 ac_glbctrl, ac_codec_cmd;
137
138 mutex_lock(&s3c_ac97.lock);
139
140 s3c_ac97_activate(ac97);
141
142 INIT_COMPLETION(s3c_ac97.done);
143
144 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
145 ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
146 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
147
148 udelay(50);
149
150 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
151 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
152 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
153
154 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
155 printk(KERN_ERR "AC97: Unable to write!");
156
157 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
158 ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
159 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
160
161 mutex_unlock(&s3c_ac97.lock);
162}
163
164static void s3c_ac97_cold_reset(struct snd_ac97 *ac97)
165{
166 writel(S3C_AC97_GLBCTRL_COLDRESET,
167 s3c_ac97.regs + S3C_AC97_GLBCTRL);
168 msleep(1);
169
170 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
171 msleep(1);
172}
173
174static void s3c_ac97_warm_reset(struct snd_ac97 *ac97)
175{
176 u32 stat;
177
178 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
179 if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
180 return; /* Return if already active */
181
182 writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL);
183 msleep(1);
184
185 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
186 msleep(1);
187
188 s3c_ac97_activate(ac97);
189}
190
191static irqreturn_t s3c_ac97_irq(int irq, void *dev_id)
192{
193 u32 ac_glbctrl, ac_glbstat;
194
195 ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT);
196
197 if (ac_glbstat & S3C_AC97_GLBSTAT_CODECREADY) {
198
199 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
200 ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
201 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
202
203 complete(&s3c_ac97.done);
204 }
205
206 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
207 ac_glbctrl |= (1<<30); /* Clear interrupt */
208 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
209
210 return IRQ_HANDLED;
211}
212
213struct snd_ac97_bus_ops soc_ac97_ops = {
214 .read = s3c_ac97_read,
215 .write = s3c_ac97_write,
216 .warm_reset = s3c_ac97_warm_reset,
217 .reset = s3c_ac97_cold_reset,
218};
219EXPORT_SYMBOL_GPL(soc_ac97_ops);
220
221static int s3c_ac97_hw_params(struct snd_pcm_substream *substream,
222 struct snd_pcm_hw_params *params,
223 struct snd_soc_dai *dai)
224{
225 struct snd_soc_pcm_runtime *rtd = substream->private_data;
226 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
227
228 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
229 cpu_dai->dma_data = &s3c_ac97_pcm_out;
230 else
231 cpu_dai->dma_data = &s3c_ac97_pcm_in;
232
233 return 0;
234}
235
236static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
237 struct snd_soc_dai *dai)
238{
239 u32 ac_glbctrl;
240 struct snd_soc_pcm_runtime *rtd = substream->private_data;
241 int channel = ((struct s3c_dma_params *)
242 rtd->dai->cpu_dai->dma_data)->channel;
243
244 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
245 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
246 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
247 else
248 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
249
250 switch (cmd) {
251 case SNDRV_PCM_TRIGGER_START:
252 case SNDRV_PCM_TRIGGER_RESUME:
253 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
254 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
255 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
256 else
257 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
258 break;
259
260 case SNDRV_PCM_TRIGGER_STOP:
261 case SNDRV_PCM_TRIGGER_SUSPEND:
262 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
263 break;
264 }
265
266 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
267
268 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED);
269
270 return 0;
271}
272
273static int s3c_ac97_hw_mic_params(struct snd_pcm_substream *substream,
274 struct snd_pcm_hw_params *params,
275 struct snd_soc_dai *dai)
276{
277 struct snd_soc_pcm_runtime *rtd = substream->private_data;
278 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
279
280 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
281 return -ENODEV;
282 else
283 cpu_dai->dma_data = &s3c_ac97_mic_in;
284
285 return 0;
286}
287
288static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream,
289 int cmd, struct snd_soc_dai *dai)
290{
291 u32 ac_glbctrl;
292 struct snd_soc_pcm_runtime *rtd = substream->private_data;
293 int channel = ((struct s3c_dma_params *)
294 rtd->dai->cpu_dai->dma_data)->channel;
295
296 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
297 ac_glbctrl &= ~S3C_AC97_GLBCTRL_MICINTM_MASK;
298
299 switch (cmd) {
300 case SNDRV_PCM_TRIGGER_START:
301 case SNDRV_PCM_TRIGGER_RESUME:
302 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
303 ac_glbctrl |= S3C_AC97_GLBCTRL_MICINTM_DMA;
304 break;
305
306 case SNDRV_PCM_TRIGGER_STOP:
307 case SNDRV_PCM_TRIGGER_SUSPEND:
308 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
309 break;
310 }
311
312 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
313
314 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED);
315
316 return 0;
317}
318
319static struct snd_soc_dai_ops s3c_ac97_dai_ops = {
320 .hw_params = s3c_ac97_hw_params,
321 .trigger = s3c_ac97_trigger,
322};
323
324static struct snd_soc_dai_ops s3c_ac97_mic_dai_ops = {
325 .hw_params = s3c_ac97_hw_mic_params,
326 .trigger = s3c_ac97_mic_trigger,
327};
328
329struct snd_soc_dai s3c_ac97_dai[] = {
330 [S3C_AC97_DAI_PCM] = {
331 .name = "s3c-ac97",
332 .id = S3C_AC97_DAI_PCM,
333 .ac97_control = 1,
334 .playback = {
335 .stream_name = "AC97 Playback",
336 .channels_min = 2,
337 .channels_max = 2,
338 .rates = SNDRV_PCM_RATE_8000_48000,
339 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
340 .capture = {
341 .stream_name = "AC97 Capture",
342 .channels_min = 2,
343 .channels_max = 2,
344 .rates = SNDRV_PCM_RATE_8000_48000,
345 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
346 .ops = &s3c_ac97_dai_ops,
347 },
348 [S3C_AC97_DAI_MIC] = {
349 .name = "s3c-ac97-mic",
350 .id = S3C_AC97_DAI_MIC,
351 .ac97_control = 1,
352 .capture = {
353 .stream_name = "AC97 Mic Capture",
354 .channels_min = 1,
355 .channels_max = 1,
356 .rates = SNDRV_PCM_RATE_8000_48000,
357 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
358 .ops = &s3c_ac97_mic_dai_ops,
359 },
360};
361EXPORT_SYMBOL_GPL(s3c_ac97_dai);
362
363static __devinit int s3c_ac97_probe(struct platform_device *pdev)
364{
365 struct resource *mem_res, *dmatx_res, *dmarx_res, *dmamic_res, *irq_res;
366 struct s3c_audio_pdata *ac97_pdata;
367 int ret;
368
369 ac97_pdata = pdev->dev.platform_data;
370 if (!ac97_pdata || !ac97_pdata->cfg_gpio) {
371 dev_err(&pdev->dev, "cfg_gpio callback not provided!\n");
372 return -EINVAL;
373 }
374
375 /* Check for availability of necessary resource */
376 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
377 if (!dmatx_res) {
378 dev_err(&pdev->dev, "Unable to get AC97-TX dma resource\n");
379 return -ENXIO;
380 }
381
382 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
383 if (!dmarx_res) {
384 dev_err(&pdev->dev, "Unable to get AC97-RX dma resource\n");
385 return -ENXIO;
386 }
387
388 dmamic_res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
389 if (!dmamic_res) {
390 dev_err(&pdev->dev, "Unable to get AC97-MIC dma resource\n");
391 return -ENXIO;
392 }
393
394 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
395 if (!mem_res) {
396 dev_err(&pdev->dev, "Unable to get register resource\n");
397 return -ENXIO;
398 }
399
400 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
401 if (!irq_res) {
402 dev_err(&pdev->dev, "AC97 IRQ not provided!\n");
403 return -ENXIO;
404 }
405
406 if (!request_mem_region(mem_res->start,
407 resource_size(mem_res), "s3c-ac97")) {
408 dev_err(&pdev->dev, "Unable to request register region\n");
409 return -EBUSY;
410 }
411
412 s3c_ac97_pcm_out.channel = dmatx_res->start;
413 s3c_ac97_pcm_out.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
414 s3c_ac97_pcm_in.channel = dmarx_res->start;
415 s3c_ac97_pcm_in.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
416 s3c_ac97_mic_in.channel = dmamic_res->start;
417 s3c_ac97_mic_in.dma_addr = mem_res->start + S3C_AC97_MIC_DATA;
418
419 init_completion(&s3c_ac97.done);
420 mutex_init(&s3c_ac97.lock);
421
422 s3c_ac97.regs = ioremap(mem_res->start, resource_size(mem_res));
423 if (s3c_ac97.regs == NULL) {
424 dev_err(&pdev->dev, "Unable to ioremap register region\n");
425 ret = -ENXIO;
426 goto err1;
427 }
428
429 s3c_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
430 if (IS_ERR(s3c_ac97.ac97_clk)) {
431 dev_err(&pdev->dev, "s3c-ac97 failed to get ac97_clock\n");
432 ret = -ENODEV;
433 goto err2;
434 }
435 clk_enable(s3c_ac97.ac97_clk);
436
437 if (ac97_pdata->cfg_gpio(pdev)) {
438 dev_err(&pdev->dev, "Unable to configure gpio\n");
439 ret = -EINVAL;
440 goto err3;
441 }
442
443 ret = request_irq(irq_res->start, s3c_ac97_irq,
444 IRQF_DISABLED, "AC97", NULL);
445 if (ret < 0) {
446 printk(KERN_ERR "s3c-ac97: interrupt request failed.\n");
447 goto err4;
448 }
449
450 s3c_ac97_dai[S3C_AC97_DAI_PCM].dev = &pdev->dev;
451 s3c_ac97_dai[S3C_AC97_DAI_MIC].dev = &pdev->dev;
452
453 ret = snd_soc_register_dais(s3c_ac97_dai, ARRAY_SIZE(s3c_ac97_dai));
454 if (ret)
455 goto err5;
456
457 return 0;
458
459err5:
460 free_irq(irq_res->start, NULL);
461err4:
462err3:
463 clk_disable(s3c_ac97.ac97_clk);
464 clk_put(s3c_ac97.ac97_clk);
465err2:
466 iounmap(s3c_ac97.regs);
467err1:
468 release_mem_region(mem_res->start, resource_size(mem_res));
469
470 return ret;
471}
472
473static __devexit int s3c_ac97_remove(struct platform_device *pdev)
474{
475 struct resource *mem_res, *irq_res;
476
477 snd_soc_unregister_dais(s3c_ac97_dai, ARRAY_SIZE(s3c_ac97_dai));
478
479 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
480 if (irq_res)
481 free_irq(irq_res->start, NULL);
482
483 clk_disable(s3c_ac97.ac97_clk);
484 clk_put(s3c_ac97.ac97_clk);
485
486 iounmap(s3c_ac97.regs);
487
488 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
489 if (mem_res)
490 release_mem_region(mem_res->start, resource_size(mem_res));
491
492 return 0;
493}
494
495static struct platform_driver s3c_ac97_driver = {
496 .probe = s3c_ac97_probe,
497 .remove = s3c_ac97_remove,
498 .driver = {
499 .name = "s3c-ac97",
500 .owner = THIS_MODULE,
501 },
502};
503
504static int __init s3c_ac97_init(void)
505{
506 return platform_driver_register(&s3c_ac97_driver);
507}
508module_init(s3c_ac97_init);
509
510static void __exit s3c_ac97_exit(void)
511{
512 platform_driver_unregister(&s3c_ac97_driver);
513}
514module_exit(s3c_ac97_exit);
515
516MODULE_AUTHOR("Jaswinder Singh, <jassi.brar@samsung.com>");
517MODULE_DESCRIPTION("AC97 driver for the Samsung SoC");
518MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 13:16:47 -0500