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Diffstat (limited to 'sound/soc/mxs/mxs-saif.c')
-rw-r--r--sound/soc/mxs/mxs-saif.c22
1 files changed, 12 insertions, 10 deletions
diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c
index 0b3adaec9f4c..530017f7d14a 100644
--- a/sound/soc/mxs/mxs-saif.c
+++ b/sound/soc/mxs/mxs-saif.c
@@ -187,16 +187,20 @@ int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
187 if (!saif) 187 if (!saif)
188 return -EINVAL; 188 return -EINVAL;
189 189
190 /* Clear Reset */
191 __raw_writel(BM_SAIF_CTRL_SFTRST,
192 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
193
194 /* FIXME: need clear clk gate for register r/w */
195 __raw_writel(BM_SAIF_CTRL_CLKGATE,
196 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
197
190 stat = __raw_readl(saif->base + SAIF_STAT); 198 stat = __raw_readl(saif->base + SAIF_STAT);
191 if (stat & BM_SAIF_STAT_BUSY) { 199 if (stat & BM_SAIF_STAT_BUSY) {
192 dev_err(saif->dev, "error: busy\n"); 200 dev_err(saif->dev, "error: busy\n");
193 return -EBUSY; 201 return -EBUSY;
194 } 202 }
195 203
196 /* Clear Reset */
197 __raw_writel(BM_SAIF_CTRL_SFTRST,
198 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
199
200 saif->mclk_in_use = 1; 204 saif->mclk_in_use = 1;
201 ret = mxs_saif_set_clk(saif, mclk, rate); 205 ret = mxs_saif_set_clk(saif, mclk, rate);
202 if (ret) 206 if (ret)
@@ -207,8 +211,6 @@ int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
207 return ret; 211 return ret;
208 212
209 /* enable MCLK output */ 213 /* enable MCLK output */
210 __raw_writel(BM_SAIF_CTRL_CLKGATE,
211 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
212 __raw_writel(BM_SAIF_CTRL_RUN, 214 __raw_writel(BM_SAIF_CTRL_RUN,
213 saif->base + SAIF_CTRL + MXS_SET_ADDR); 215 saif->base + SAIF_CTRL + MXS_SET_ADDR);
214 216
@@ -303,6 +305,10 @@ static int mxs_saif_startup(struct snd_pcm_substream *substream,
303 __raw_writel(BM_SAIF_CTRL_SFTRST, 305 __raw_writel(BM_SAIF_CTRL_SFTRST,
304 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 306 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
305 307
308 /* clear clock gate */
309 __raw_writel(BM_SAIF_CTRL_CLKGATE,
310 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
311
306 return 0; 312 return 0;
307} 313}
308 314
@@ -379,10 +385,6 @@ static int mxs_saif_prepare(struct snd_pcm_substream *substream,
379{ 385{
380 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 386 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
381 387
382 /* clear clock gate */
383 __raw_writel(BM_SAIF_CTRL_CLKGATE,
384 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
385
386 /* enable FIFO error irqs */ 388 /* enable FIFO error irqs */
387 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, 389 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
388 saif->base + SAIF_CTRL + MXS_SET_ADDR); 390 saif->base + SAIF_CTRL + MXS_SET_ADDR);