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-rw-r--r--sound/soc/fsl/fsl_ssi.c583
1 files changed, 400 insertions, 183 deletions
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index 76e56b39db01..f9090b167ad7 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -35,6 +35,7 @@
35#include <linux/module.h> 35#include <linux/module.h>
36#include <linux/interrupt.h> 36#include <linux/interrupt.h>
37#include <linux/clk.h> 37#include <linux/clk.h>
38#include <linux/debugfs.h>
38#include <linux/device.h> 39#include <linux/device.h>
39#include <linux/delay.h> 40#include <linux/delay.h>
40#include <linux/slab.h> 41#include <linux/slab.h>
@@ -106,12 +107,33 @@ static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
106 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) 107 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
107#endif 108#endif
108 109
109/* SIER bitflag of interrupts to enable */ 110#define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
110#define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \ 111 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
111 CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \ 112 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
112 CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \ 113#define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
113 CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \ 114 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
114 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN) 115 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
116#define FSLSSI_SISR_MASK (FSLSSI_SIER_DBG_RX_FLAGS | FSLSSI_SIER_DBG_TX_FLAGS)
117
118
119enum fsl_ssi_type {
120 FSL_SSI_MCP8610,
121 FSL_SSI_MX21,
122 FSL_SSI_MX35,
123 FSL_SSI_MX51,
124};
125
126struct fsl_ssi_reg_val {
127 u32 sier;
128 u32 srcr;
129 u32 stcr;
130 u32 scr;
131};
132
133struct fsl_ssi_rxtx_reg_val {
134 struct fsl_ssi_reg_val rx;
135 struct fsl_ssi_reg_val tx;
136};
115 137
116/** 138/**
117 * fsl_ssi_private: per-SSI private data 139 * fsl_ssi_private: per-SSI private data
@@ -132,14 +154,16 @@ struct fsl_ssi_private {
132 unsigned int irq; 154 unsigned int irq;
133 unsigned int fifo_depth; 155 unsigned int fifo_depth;
134 struct snd_soc_dai_driver cpu_dai_drv; 156 struct snd_soc_dai_driver cpu_dai_drv;
135 struct device_attribute dev_attr;
136 struct platform_device *pdev; 157 struct platform_device *pdev;
137 158
159 enum fsl_ssi_type hw_type;
138 bool new_binding; 160 bool new_binding;
139 bool ssi_on_imx; 161 bool ssi_on_imx;
140 bool imx_ac97; 162 bool imx_ac97;
141 bool use_dma; 163 bool use_dma;
142 bool baudclk_locked; 164 bool baudclk_locked;
165 bool irq_stats;
166 bool offline_config;
143 u8 i2s_mode; 167 u8 i2s_mode;
144 spinlock_t baudclk_lock; 168 spinlock_t baudclk_lock;
145 struct clk *baudclk; 169 struct clk *baudclk;
@@ -149,6 +173,8 @@ struct fsl_ssi_private {
149 struct imx_dma_data filter_data_tx; 173 struct imx_dma_data filter_data_tx;
150 struct imx_dma_data filter_data_rx; 174 struct imx_dma_data filter_data_rx;
151 struct imx_pcm_fiq_params fiq_params; 175 struct imx_pcm_fiq_params fiq_params;
176 /* Register values for rx/tx configuration */
177 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
152 178
153 struct { 179 struct {
154 unsigned int rfrc; 180 unsigned int rfrc;
@@ -173,10 +199,21 @@ struct fsl_ssi_private {
173 unsigned int tfe1; 199 unsigned int tfe1;
174 unsigned int tfe0; 200 unsigned int tfe0;
175 } stats; 201 } stats;
202 struct dentry *dbg_dir;
203 struct dentry *dbg_stats;
176 204
177 char name[1]; 205 char name[1];
178}; 206};
179 207
208static const struct of_device_id fsl_ssi_ids[] = {
209 { .compatible = "fsl,mpc8610-ssi", .data = (void *) FSL_SSI_MCP8610},
210 { .compatible = "fsl,imx51-ssi", .data = (void *) FSL_SSI_MX51},
211 { .compatible = "fsl,imx35-ssi", .data = (void *) FSL_SSI_MX35},
212 { .compatible = "fsl,imx21-ssi", .data = (void *) FSL_SSI_MX21},
213 {}
214};
215MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
216
180/** 217/**
181 * fsl_ssi_isr: SSI interrupt handler 218 * fsl_ssi_isr: SSI interrupt handler
182 * 219 *
@@ -195,23 +232,40 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
195 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 232 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
196 irqreturn_t ret = IRQ_NONE; 233 irqreturn_t ret = IRQ_NONE;
197 __be32 sisr; 234 __be32 sisr;
198 __be32 sisr2 = 0; 235 __be32 sisr2;
236 __be32 sisr_write_mask = 0;
237
238 switch (ssi_private->hw_type) {
239 case FSL_SSI_MX21:
240 sisr_write_mask = 0;
241 break;
242
243 case FSL_SSI_MCP8610:
244 case FSL_SSI_MX35:
245 sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
246 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
247 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
248 break;
249
250 case FSL_SSI_MX51:
251 sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
252 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
253 break;
254 }
199 255
200 /* We got an interrupt, so read the status register to see what we 256 /* We got an interrupt, so read the status register to see what we
201 were interrupted for. We mask it with the Interrupt Enable register 257 were interrupted for. We mask it with the Interrupt Enable register
202 so that we only check for events that we're interested in. 258 so that we only check for events that we're interested in.
203 */ 259 */
204 sisr = read_ssi(&ssi->sisr) & SIER_FLAGS; 260 sisr = read_ssi(&ssi->sisr) & FSLSSI_SISR_MASK;
205 261
206 if (sisr & CCSR_SSI_SISR_RFRC) { 262 if (sisr & CCSR_SSI_SISR_RFRC) {
207 ssi_private->stats.rfrc++; 263 ssi_private->stats.rfrc++;
208 sisr2 |= CCSR_SSI_SISR_RFRC;
209 ret = IRQ_HANDLED; 264 ret = IRQ_HANDLED;
210 } 265 }
211 266
212 if (sisr & CCSR_SSI_SISR_TFRC) { 267 if (sisr & CCSR_SSI_SISR_TFRC) {
213 ssi_private->stats.tfrc++; 268 ssi_private->stats.tfrc++;
214 sisr2 |= CCSR_SSI_SISR_TFRC;
215 ret = IRQ_HANDLED; 269 ret = IRQ_HANDLED;
216 } 270 }
217 271
@@ -252,25 +306,21 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
252 306
253 if (sisr & CCSR_SSI_SISR_ROE1) { 307 if (sisr & CCSR_SSI_SISR_ROE1) {
254 ssi_private->stats.roe1++; 308 ssi_private->stats.roe1++;
255 sisr2 |= CCSR_SSI_SISR_ROE1;
256 ret = IRQ_HANDLED; 309 ret = IRQ_HANDLED;
257 } 310 }
258 311
259 if (sisr & CCSR_SSI_SISR_ROE0) { 312 if (sisr & CCSR_SSI_SISR_ROE0) {
260 ssi_private->stats.roe0++; 313 ssi_private->stats.roe0++;
261 sisr2 |= CCSR_SSI_SISR_ROE0;
262 ret = IRQ_HANDLED; 314 ret = IRQ_HANDLED;
263 } 315 }
264 316
265 if (sisr & CCSR_SSI_SISR_TUE1) { 317 if (sisr & CCSR_SSI_SISR_TUE1) {
266 ssi_private->stats.tue1++; 318 ssi_private->stats.tue1++;
267 sisr2 |= CCSR_SSI_SISR_TUE1;
268 ret = IRQ_HANDLED; 319 ret = IRQ_HANDLED;
269 } 320 }
270 321
271 if (sisr & CCSR_SSI_SISR_TUE0) { 322 if (sisr & CCSR_SSI_SISR_TUE0) {
272 ssi_private->stats.tue0++; 323 ssi_private->stats.tue0++;
273 sisr2 |= CCSR_SSI_SISR_TUE0;
274 ret = IRQ_HANDLED; 324 ret = IRQ_HANDLED;
275 } 325 }
276 326
@@ -314,6 +364,7 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
314 ret = IRQ_HANDLED; 364 ret = IRQ_HANDLED;
315 } 365 }
316 366
367 sisr2 = sisr & sisr_write_mask;
317 /* Clear the bits that we set */ 368 /* Clear the bits that we set */
318 if (sisr2) 369 if (sisr2)
319 write_ssi(sisr2, &ssi->sisr); 370 write_ssi(sisr2, &ssi->sisr);
@@ -321,6 +372,245 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
321 return ret; 372 return ret;
322} 373}
323 374
375#if IS_ENABLED(CONFIG_DEBUG_FS)
376/* Show the statistics of a flag only if its interrupt is enabled. The
377 * compiler will optimze this code to a no-op if the interrupt is not
378 * enabled.
379 */
380#define SIER_SHOW(flag, name) \
381 do { \
382 if (FSLSSI_SISR_MASK & CCSR_SSI_SIER_##flag) \
383 seq_printf(s, #name "=%u\n", ssi_private->stats.name); \
384 } while (0)
385
386
387/**
388 * fsl_sysfs_ssi_show: display SSI statistics
389 *
390 * Display the statistics for the current SSI device. To avoid confusion,
391 * we only show those counts that are enabled.
392 */
393static int fsl_ssi_stats_show(struct seq_file *s, void *unused)
394{
395 struct fsl_ssi_private *ssi_private = s->private;
396
397 SIER_SHOW(RFRC_EN, rfrc);
398 SIER_SHOW(TFRC_EN, tfrc);
399 SIER_SHOW(CMDAU_EN, cmdau);
400 SIER_SHOW(CMDDU_EN, cmddu);
401 SIER_SHOW(RXT_EN, rxt);
402 SIER_SHOW(RDR1_EN, rdr1);
403 SIER_SHOW(RDR0_EN, rdr0);
404 SIER_SHOW(TDE1_EN, tde1);
405 SIER_SHOW(TDE0_EN, tde0);
406 SIER_SHOW(ROE1_EN, roe1);
407 SIER_SHOW(ROE0_EN, roe0);
408 SIER_SHOW(TUE1_EN, tue1);
409 SIER_SHOW(TUE0_EN, tue0);
410 SIER_SHOW(TFS_EN, tfs);
411 SIER_SHOW(RFS_EN, rfs);
412 SIER_SHOW(TLS_EN, tls);
413 SIER_SHOW(RLS_EN, rls);
414 SIER_SHOW(RFF1_EN, rff1);
415 SIER_SHOW(RFF0_EN, rff0);
416 SIER_SHOW(TFE1_EN, tfe1);
417 SIER_SHOW(TFE0_EN, tfe0);
418
419 return 0;
420}
421
422static int fsl_ssi_stats_open(struct inode *inode, struct file *file)
423{
424 return single_open(file, fsl_ssi_stats_show, inode->i_private);
425}
426
427static const struct file_operations fsl_ssi_stats_ops = {
428 .open = fsl_ssi_stats_open,
429 .read = seq_read,
430 .llseek = seq_lseek,
431 .release = single_release,
432};
433
434static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
435 struct device *dev)
436{
437 ssi_private->dbg_dir = debugfs_create_dir(dev_name(dev), NULL);
438 if (!ssi_private->dbg_dir)
439 return -ENOMEM;
440
441 ssi_private->dbg_stats = debugfs_create_file("stats", S_IRUGO,
442 ssi_private->dbg_dir, ssi_private, &fsl_ssi_stats_ops);
443 if (!ssi_private->dbg_stats) {
444 debugfs_remove(ssi_private->dbg_dir);
445 return -ENOMEM;
446 }
447
448 return 0;
449}
450
451static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
452{
453 debugfs_remove(ssi_private->dbg_stats);
454 debugfs_remove(ssi_private->dbg_dir);
455}
456
457#else
458
459static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
460 struct device *dev)
461{
462 return 0;
463}
464
465static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
466{
467}
468
469#endif /* IS_ENABLED(CONFIG_DEBUG_FS) */
470
471/*
472 * Enable/Disable all rx/tx config flags at once.
473 */
474static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
475 bool enable)
476{
477 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
478 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
479
480 if (enable) {
481 write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier);
482 write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr);
483 write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr);
484 } else {
485 write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0);
486 write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0);
487 write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0);
488 }
489}
490
491/*
492 * Enable/Disable a ssi configuration. You have to pass either
493 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
494 */
495static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
496 struct fsl_ssi_reg_val *vals)
497{
498 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
499 struct fsl_ssi_reg_val *avals;
500 u32 scr_val = read_ssi(&ssi->scr);
501 int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
502 !!(scr_val & CCSR_SSI_SCR_RE);
503
504 /* Find the other direction values rx or tx which we do not want to
505 * modify */
506 if (&ssi_private->rxtx_reg_val.rx == vals)
507 avals = &ssi_private->rxtx_reg_val.tx;
508 else
509 avals = &ssi_private->rxtx_reg_val.rx;
510
511 /* If vals should be disabled, start with disabling the unit */
512 if (!enable) {
513 u32 scr = vals->scr & (vals->scr ^ avals->scr);
514 write_ssi_mask(&ssi->scr, scr, 0);
515 }
516
517 /*
518 * We are running on a SoC which does not support online SSI
519 * reconfiguration, so we have to enable all necessary flags at once
520 * even if we do not use them later (capture and playback configuration)
521 */
522 if (ssi_private->offline_config) {
523 if ((enable && !nr_active_streams) ||
524 (!enable && nr_active_streams == 1))
525 fsl_ssi_rxtx_config(ssi_private, enable);
526
527 goto config_done;
528 }
529
530 /*
531 * Configure single direction units while the SSI unit is running
532 * (online configuration)
533 */
534 if (enable) {
535 write_ssi_mask(&ssi->sier, 0, vals->sier);
536 write_ssi_mask(&ssi->srcr, 0, vals->srcr);
537 write_ssi_mask(&ssi->stcr, 0, vals->stcr);
538 } else {
539 u32 sier;
540 u32 srcr;
541 u32 stcr;
542
543 /*
544 * Disabling the necessary flags for one of rx/tx while the
545 * other stream is active is a little bit more difficult. We
546 * have to disable only those flags that differ between both
547 * streams (rx XOR tx) and that are set in the stream that is
548 * disabled now. Otherwise we could alter flags of the other
549 * stream
550 */
551
552 /* These assignments are simply vals without bits set in avals*/
553 sier = vals->sier & (vals->sier ^ avals->sier);
554 srcr = vals->srcr & (vals->srcr ^ avals->srcr);
555 stcr = vals->stcr & (vals->stcr ^ avals->stcr);
556
557 write_ssi_mask(&ssi->srcr, srcr, 0);
558 write_ssi_mask(&ssi->stcr, stcr, 0);
559 write_ssi_mask(&ssi->sier, sier, 0);
560 }
561
562config_done:
563 /* Enabling of subunits is done after configuration */
564 if (enable)
565 write_ssi_mask(&ssi->scr, 0, vals->scr);
566}
567
568
569static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
570{
571 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
572}
573
574static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
575{
576 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
577}
578
579/*
580 * Setup rx/tx register values used to enable/disable the streams. These will
581 * be used later in fsl_ssi_config to setup the streams without the need to
582 * check for all different SSI modes.
583 */
584static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
585{
586 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
587
588 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
589 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
590 reg->rx.scr = 0;
591 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
592 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
593 reg->tx.scr = 0;
594
595 if (!ssi_private->imx_ac97) {
596 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
597 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
598 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
599 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
600 }
601
602 if (ssi_private->use_dma) {
603 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
604 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
605 } else {
606 reg->rx.sier |= CCSR_SSI_SIER_RIE;
607 reg->tx.sier |= CCSR_SSI_SIER_TIE;
608 }
609
610 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
611 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
612}
613
324static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) 614static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
325{ 615{
326 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 616 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
@@ -357,6 +647,8 @@ static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
357 u8 wm; 647 u8 wm;
358 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates; 648 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
359 649
650 fsl_ssi_setup_reg_vals(ssi_private);
651
360 if (ssi_private->imx_ac97) 652 if (ssi_private->imx_ac97)
361 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET; 653 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
362 else 654 else
@@ -380,13 +672,12 @@ static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
380 ssi_private->i2s_mode | 672 ssi_private->i2s_mode |
381 (synchronous ? CCSR_SSI_SCR_SYN : 0)); 673 (synchronous ? CCSR_SSI_SCR_SYN : 0));
382 674
383 write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 | 675 write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFSI |
384 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS | 676 CCSR_SSI_STCR_TEFS | CCSR_SSI_STCR_TSCKP, &ssi->stcr);
385 CCSR_SSI_STCR_TSCKP, &ssi->stcr); 677
678 write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFSI |
679 CCSR_SSI_SRCR_REFS | CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
386 680
387 write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
388 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
389 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
390 /* 681 /*
391 * The DC and PM bits are only used if the SSI is the clock master. 682 * The DC and PM bits are only used if the SSI is the clock master.
392 */ 683 */
@@ -419,6 +710,17 @@ static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
419 if (ssi_private->imx_ac97) 710 if (ssi_private->imx_ac97)
420 fsl_ssi_setup_ac97(ssi_private); 711 fsl_ssi_setup_ac97(ssi_private);
421 712
713 /*
714 * Set a default slot number so that there is no need for those common
715 * cases like I2S mode to call the extra set_tdm_slot() any more.
716 */
717 if (!ssi_private->imx_ac97) {
718 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
719 CCSR_SSI_SxCCR_DC(2));
720 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
721 CCSR_SSI_SxCCR_DC(2));
722 }
723
422 return 0; 724 return 0;
423} 725}
424 726
@@ -761,50 +1063,26 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
761 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1063 struct snd_soc_pcm_runtime *rtd = substream->private_data;
762 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); 1064 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
763 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 1065 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
764 unsigned int sier_bits;
765 unsigned long flags; 1066 unsigned long flags;
766 1067
767 /*
768 * Enable only the interrupts and DMA requests
769 * that are needed for the channel. As the fiq
770 * is polling for this bits, we have to ensure
771 * that this are aligned with the preallocated
772 * buffers
773 */
774
775 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
776 if (ssi_private->use_dma)
777 sier_bits = SIER_FLAGS;
778 else
779 sier_bits = CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN;
780 } else {
781 if (ssi_private->use_dma)
782 sier_bits = SIER_FLAGS;
783 else
784 sier_bits = CCSR_SSI_SIER_RIE | CCSR_SSI_SIER_RFF0_EN;
785 }
786
787 switch (cmd) { 1068 switch (cmd) {
788 case SNDRV_PCM_TRIGGER_START: 1069 case SNDRV_PCM_TRIGGER_START:
789 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1070 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
790 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1071 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
791 write_ssi_mask(&ssi->scr, 0, 1072 fsl_ssi_tx_config(ssi_private, true);
792 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
793 else 1073 else
794 write_ssi_mask(&ssi->scr, 0, 1074 fsl_ssi_rx_config(ssi_private, true);
795 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
796 break; 1075 break;
797 1076
798 case SNDRV_PCM_TRIGGER_STOP: 1077 case SNDRV_PCM_TRIGGER_STOP:
799 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1078 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
800 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1079 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
801 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0); 1080 fsl_ssi_tx_config(ssi_private, false);
802 else 1081 else
803 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0); 1082 fsl_ssi_rx_config(ssi_private, false);
804 1083
805 if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) & 1084 if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
806 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) { 1085 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) {
807 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
808 spin_lock_irqsave(&ssi_private->baudclk_lock, flags); 1086 spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
809 ssi_private->baudclk_locked = false; 1087 ssi_private->baudclk_locked = false;
810 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags); 1088 spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
@@ -815,7 +1093,12 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
815 return -EINVAL; 1093 return -EINVAL;
816 } 1094 }
817 1095
818 write_ssi(sier_bits, &ssi->sier); 1096 if (ssi_private->imx_ac97) {
1097 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1098 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
1099 else
1100 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
1101 }
819 1102
820 return 0; 1103 return 0;
821} 1104}
@@ -863,58 +1146,6 @@ static const struct snd_soc_component_driver fsl_ssi_component = {
863 .name = "fsl-ssi", 1146 .name = "fsl-ssi",
864}; 1147};
865 1148
866/**
867 * fsl_ssi_ac97_trigger: start and stop the AC97 receive/transmit.
868 *
869 * This function is called by ALSA to start, stop, pause, and resume the
870 * transfer of data.
871 */
872static int fsl_ssi_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
873 struct snd_soc_dai *dai)
874{
875 struct snd_soc_pcm_runtime *rtd = substream->private_data;
876 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(
877 rtd->cpu_dai);
878 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
879
880 switch (cmd) {
881 case SNDRV_PCM_TRIGGER_START:
882 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
883 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
884 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TIE |
885 CCSR_SSI_SIER_TFE0_EN);
886 else
887 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RIE |
888 CCSR_SSI_SIER_RFF0_EN);
889 break;
890
891 case SNDRV_PCM_TRIGGER_STOP:
892 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
893 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
894 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TIE |
895 CCSR_SSI_SIER_TFE0_EN, 0);
896 else
897 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RIE |
898 CCSR_SSI_SIER_RFF0_EN, 0);
899 break;
900
901 default:
902 return -EINVAL;
903 }
904
905 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
906 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
907 else
908 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
909
910 return 0;
911}
912
913static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops = {
914 .startup = fsl_ssi_startup,
915 .trigger = fsl_ssi_ac97_trigger,
916};
917
918static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { 1149static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
919 .ac97_control = 1, 1150 .ac97_control = 1,
920 .playback = { 1151 .playback = {
@@ -931,7 +1162,7 @@ static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
931 .rates = SNDRV_PCM_RATE_48000, 1162 .rates = SNDRV_PCM_RATE_48000,
932 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1163 .formats = SNDRV_PCM_FMTBIT_S16_LE,
933 }, 1164 },
934 .ops = &fsl_ssi_ac97_dai_ops, 1165 .ops = &fsl_ssi_dai_ops,
935}; 1166};
936 1167
937 1168
@@ -989,56 +1220,6 @@ static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
989 .write = fsl_ssi_ac97_write, 1220 .write = fsl_ssi_ac97_write,
990}; 1221};
991 1222
992/* Show the statistics of a flag only if its interrupt is enabled. The
993 * compiler will optimze this code to a no-op if the interrupt is not
994 * enabled.
995 */
996#define SIER_SHOW(flag, name) \
997 do { \
998 if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \
999 length += sprintf(buf + length, #name "=%u\n", \
1000 ssi_private->stats.name); \
1001 } while (0)
1002
1003
1004/**
1005 * fsl_sysfs_ssi_show: display SSI statistics
1006 *
1007 * Display the statistics for the current SSI device. To avoid confusion,
1008 * we only show those counts that are enabled.
1009 */
1010static ssize_t fsl_sysfs_ssi_show(struct device *dev,
1011 struct device_attribute *attr, char *buf)
1012{
1013 struct fsl_ssi_private *ssi_private =
1014 container_of(attr, struct fsl_ssi_private, dev_attr);
1015 ssize_t length = 0;
1016
1017 SIER_SHOW(RFRC_EN, rfrc);
1018 SIER_SHOW(TFRC_EN, tfrc);
1019 SIER_SHOW(CMDAU_EN, cmdau);
1020 SIER_SHOW(CMDDU_EN, cmddu);
1021 SIER_SHOW(RXT_EN, rxt);
1022 SIER_SHOW(RDR1_EN, rdr1);
1023 SIER_SHOW(RDR0_EN, rdr0);
1024 SIER_SHOW(TDE1_EN, tde1);
1025 SIER_SHOW(TDE0_EN, tde0);
1026 SIER_SHOW(ROE1_EN, roe1);
1027 SIER_SHOW(ROE0_EN, roe0);
1028 SIER_SHOW(TUE1_EN, tue1);
1029 SIER_SHOW(TUE0_EN, tue0);
1030 SIER_SHOW(TFS_EN, tfs);
1031 SIER_SHOW(RFS_EN, rfs);
1032 SIER_SHOW(TLS_EN, tls);
1033 SIER_SHOW(RLS_EN, rls);
1034 SIER_SHOW(RFF1_EN, rff1);
1035 SIER_SHOW(RFF0_EN, rff0);
1036 SIER_SHOW(TFE1_EN, tfe1);
1037 SIER_SHOW(TFE0_EN, tfe0);
1038
1039 return length;
1040}
1041
1042/** 1223/**
1043 * Make every character in a string lower-case 1224 * Make every character in a string lower-case
1044 */ 1225 */
@@ -1060,6 +1241,8 @@ static int fsl_ssi_probe(struct platform_device *pdev)
1060 int ret = 0; 1241 int ret = 0;
1061 struct device_attribute *dev_attr = NULL; 1242 struct device_attribute *dev_attr = NULL;
1062 struct device_node *np = pdev->dev.of_node; 1243 struct device_node *np = pdev->dev.of_node;
1244 const struct of_device_id *of_id;
1245 enum fsl_ssi_type hw_type;
1063 const char *p, *sprop; 1246 const char *p, *sprop;
1064 const uint32_t *iprop; 1247 const uint32_t *iprop;
1065 struct resource res; 1248 struct resource res;
@@ -1074,6 +1257,11 @@ static int fsl_ssi_probe(struct platform_device *pdev)
1074 if (!of_device_is_available(np)) 1257 if (!of_device_is_available(np))
1075 return -ENODEV; 1258 return -ENODEV;
1076 1259
1260 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1261 if (!of_id)
1262 return -EINVAL;
1263 hw_type = (enum fsl_ssi_type) of_id->data;
1264
1077 /* We only support the SSI in "I2S Slave" mode */ 1265 /* We only support the SSI in "I2S Slave" mode */
1078 sprop = of_get_property(np, "fsl,mode", NULL); 1266 sprop = of_get_property(np, "fsl,mode", NULL);
1079 if (!sprop) { 1267 if (!sprop) {
@@ -1100,6 +1288,7 @@ static int fsl_ssi_probe(struct platform_device *pdev)
1100 1288
1101 ssi_private->use_dma = !of_property_read_bool(np, 1289 ssi_private->use_dma = !of_property_read_bool(np,
1102 "fsl,fiq-stream-filter"); 1290 "fsl,fiq-stream-filter");
1291 ssi_private->hw_type = hw_type;
1103 1292
1104 if (ac97) { 1293 if (ac97) {
1105 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai, 1294 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
@@ -1153,7 +1342,34 @@ static int fsl_ssi_probe(struct platform_device *pdev)
1153 ssi_private->baudclk_locked = false; 1342 ssi_private->baudclk_locked = false;
1154 spin_lock_init(&ssi_private->baudclk_lock); 1343 spin_lock_init(&ssi_private->baudclk_lock);
1155 1344
1156 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) { 1345 /*
1346 * imx51 and later SoCs have a slightly different IP that allows the
1347 * SSI configuration while the SSI unit is running.
1348 *
1349 * More important, it is necessary on those SoCs to configure the
1350 * sperate TX/RX DMA bits just before starting the stream
1351 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
1352 * sends any DMA requests to the SDMA unit, otherwise it is not defined
1353 * how the SDMA unit handles the DMA request.
1354 *
1355 * SDMA units are present on devices starting at imx35 but the imx35
1356 * reference manual states that the DMA bits should not be changed
1357 * while the SSI unit is running (SSIEN). So we support the necessary
1358 * online configuration of fsl-ssi starting at imx51.
1359 */
1360 switch (hw_type) {
1361 case FSL_SSI_MCP8610:
1362 case FSL_SSI_MX21:
1363 case FSL_SSI_MX35:
1364 ssi_private->offline_config = true;
1365 break;
1366 case FSL_SSI_MX51:
1367 ssi_private->offline_config = false;
1368 break;
1369 }
1370
1371 if (hw_type == FSL_SSI_MX21 || hw_type == FSL_SSI_MX51 ||
1372 hw_type == FSL_SSI_MX35) {
1157 u32 dma_events[2]; 1373 u32 dma_events[2];
1158 ssi_private->ssi_on_imx = true; 1374 ssi_private->ssi_on_imx = true;
1159 1375
@@ -1175,7 +1391,8 @@ static int fsl_ssi_probe(struct platform_device *pdev)
1175 */ 1391 */
1176 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); 1392 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1177 if (IS_ERR(ssi_private->baudclk)) 1393 if (IS_ERR(ssi_private->baudclk))
1178 dev_warn(&pdev->dev, "could not get baud clock: %d\n", ret); 1394 dev_warn(&pdev->dev, "could not get baud clock: %ld\n",
1395 PTR_ERR(ssi_private->baudclk));
1179 else 1396 else
1180 clk_prepare_enable(ssi_private->baudclk); 1397 clk_prepare_enable(ssi_private->baudclk);
1181 1398
@@ -1217,32 +1434,25 @@ static int fsl_ssi_probe(struct platform_device *pdev)
1217 dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI); 1434 dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1218 imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx, 1435 imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
1219 dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI); 1436 dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1220 } else if (ssi_private->use_dma) { 1437 }
1438
1439 /*
1440 * Enable interrupts only for MCP8610 and MX51. The other MXs have
1441 * different writeable interrupt status registers.
1442 */
1443 if (ssi_private->use_dma) {
1221 /* The 'name' should not have any slashes in it. */ 1444 /* The 'name' should not have any slashes in it. */
1222 ret = devm_request_irq(&pdev->dev, ssi_private->irq, 1445 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1223 fsl_ssi_isr, 0, ssi_private->name, 1446 fsl_ssi_isr, 0, ssi_private->name,
1224 ssi_private); 1447 ssi_private);
1448 ssi_private->irq_stats = true;
1225 if (ret < 0) { 1449 if (ret < 0) {
1226 dev_err(&pdev->dev, "could not claim irq %u\n", 1450 dev_err(&pdev->dev, "could not claim irq %u\n",
1227 ssi_private->irq); 1451 ssi_private->irq);
1228 goto error_irqmap; 1452 goto error_clk;
1229 } 1453 }
1230 } 1454 }
1231 1455
1232 /* Initialize the the device_attribute structure */
1233 dev_attr = &ssi_private->dev_attr;
1234 sysfs_attr_init(&dev_attr->attr);
1235 dev_attr->attr.name = "statistics";
1236 dev_attr->attr.mode = S_IRUGO;
1237 dev_attr->show = fsl_sysfs_ssi_show;
1238
1239 ret = device_create_file(&pdev->dev, dev_attr);
1240 if (ret) {
1241 dev_err(&pdev->dev, "could not create sysfs %s file\n",
1242 ssi_private->dev_attr.attr.name);
1243 goto error_clk;
1244 }
1245
1246 /* Register with ASoC */ 1456 /* Register with ASoC */
1247 dev_set_drvdata(&pdev->dev, ssi_private); 1457 dev_set_drvdata(&pdev->dev, ssi_private);
1248 1458
@@ -1253,6 +1463,10 @@ static int fsl_ssi_probe(struct platform_device *pdev)
1253 goto error_dev; 1463 goto error_dev;
1254 } 1464 }
1255 1465
1466 ret = fsl_ssi_debugfs_create(ssi_private, &pdev->dev);
1467 if (ret)
1468 goto error_dbgfs;
1469
1256 if (ssi_private->ssi_on_imx) { 1470 if (ssi_private->ssi_on_imx) {
1257 if (!ssi_private->use_dma) { 1471 if (!ssi_private->use_dma) {
1258 1472
@@ -1272,11 +1486,11 @@ static int fsl_ssi_probe(struct platform_device *pdev)
1272 1486
1273 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params); 1487 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1274 if (ret) 1488 if (ret)
1275 goto error_dev; 1489 goto error_pcm;
1276 } else { 1490 } else {
1277 ret = imx_pcm_dma_init(pdev); 1491 ret = imx_pcm_dma_init(pdev);
1278 if (ret) 1492 if (ret)
1279 goto error_dev; 1493 goto error_pcm;
1280 } 1494 }
1281 } 1495 }
1282 1496
@@ -1318,6 +1532,13 @@ done:
1318 return 0; 1532 return 0;
1319 1533
1320error_dai: 1534error_dai:
1535 if (ssi_private->ssi_on_imx && !ssi_private->use_dma)
1536 imx_pcm_fiq_exit(pdev);
1537
1538error_pcm:
1539 fsl_ssi_debugfs_remove(ssi_private);
1540
1541error_dbgfs:
1321 snd_soc_unregister_component(&pdev->dev); 1542 snd_soc_unregister_component(&pdev->dev);
1322 1543
1323error_dev: 1544error_dev:
@@ -1331,7 +1552,8 @@ error_clk:
1331 } 1552 }
1332 1553
1333error_irqmap: 1554error_irqmap:
1334 irq_dispose_mapping(ssi_private->irq); 1555 if (ssi_private->irq_stats)
1556 irq_dispose_mapping(ssi_private->irq);
1335 1557
1336 return ret; 1558 return ret;
1337} 1559}
@@ -1340,27 +1562,22 @@ static int fsl_ssi_remove(struct platform_device *pdev)
1340{ 1562{
1341 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); 1563 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1342 1564
1565 fsl_ssi_debugfs_remove(ssi_private);
1566
1343 if (!ssi_private->new_binding) 1567 if (!ssi_private->new_binding)
1344 platform_device_unregister(ssi_private->pdev); 1568 platform_device_unregister(ssi_private->pdev);
1345 snd_soc_unregister_component(&pdev->dev); 1569 snd_soc_unregister_component(&pdev->dev);
1346 device_remove_file(&pdev->dev, &ssi_private->dev_attr);
1347 if (ssi_private->ssi_on_imx) { 1570 if (ssi_private->ssi_on_imx) {
1348 if (!IS_ERR(ssi_private->baudclk)) 1571 if (!IS_ERR(ssi_private->baudclk))
1349 clk_disable_unprepare(ssi_private->baudclk); 1572 clk_disable_unprepare(ssi_private->baudclk);
1350 clk_disable_unprepare(ssi_private->clk); 1573 clk_disable_unprepare(ssi_private->clk);
1351 } 1574 }
1352 irq_dispose_mapping(ssi_private->irq); 1575 if (ssi_private->irq_stats)
1576 irq_dispose_mapping(ssi_private->irq);
1353 1577
1354 return 0; 1578 return 0;
1355} 1579}
1356 1580
1357static const struct of_device_id fsl_ssi_ids[] = {
1358 { .compatible = "fsl,mpc8610-ssi", },
1359 { .compatible = "fsl,imx21-ssi", },
1360 {}
1361};
1362MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
1363
1364static struct platform_driver fsl_ssi_driver = { 1581static struct platform_driver fsl_ssi_driver = {
1365 .driver = { 1582 .driver = {
1366 .name = "fsl-ssi-dai", 1583 .name = "fsl-ssi-dai",