1 files changed, 23 insertions, 25 deletions

diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 41bb62e69361..e432260be598 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -15,31 +15,36 @@
                          SNDRV_PCM_FMTBIT_S20_3LE |\
                          SNDRV_PCM_FMTBIT_S24_LE)
 
+/* SAI Register Map Register */
+#define FSL_SAI_TCSR    0x00 /* SAI Transmit Control */
+#define FSL_SAI_TCR1    0x04 /* SAI Transmit Configuration 1 */
+#define FSL_SAI_TCR2    0x08 /* SAI Transmit Configuration 2 */
+#define FSL_SAI_TCR3    0x0c /* SAI Transmit Configuration 3 */
+#define FSL_SAI_TCR4    0x10 /* SAI Transmit Configuration 4 */
+#define FSL_SAI_TCR5    0x14 /* SAI Transmit Configuration 5 */
+#define FSL_SAI_TDR     0x20 /* SAI Transmit Data */
+#define FSL_SAI_TFR     0x40 /* SAI Transmit FIFO */
+#define FSL_SAI_TMR     0x60 /* SAI Transmit Mask */
+#define FSL_SAI_RCSR    0x80 /* SAI Receive Control */
+#define FSL_SAI_RCR1    0x84 /* SAI Receive Configuration 1 */
+#define FSL_SAI_RCR2    0x88 /* SAI Receive Configuration 2 */
+#define FSL_SAI_RCR3    0x8c /* SAI Receive Configuration 3 */
+#define FSL_SAI_RCR4    0x90 /* SAI Receive Configuration 4 */
+#define FSL_SAI_RCR5    0x94 /* SAI Receive Configuration 5 */
+#define FSL_SAI_RDR     0xa0 /* SAI Receive Data */
+#define FSL_SAI_RFR     0xc0 /* SAI Receive FIFO */
+#define FSL_SAI_RMR     0xe0 /* SAI Receive Mask */
+
 /* SAI Transmit/Recieve Control Register */
-#define FSL_SAI_TCSR            0x00
-#define FSL_SAI_RCSR            0x80
 #define FSL_SAI_CSR_TERE        BIT(31)
 #define FSL_SAI_CSR_FWF         BIT(17)
 #define FSL_SAI_CSR_FRIE        BIT(8)
 #define FSL_SAI_CSR_FRDE        BIT(0)
 
-/* SAI Transmit Data/FIFO/MASK Register */
-#define FSL_SAI_TDR             0x20
-#define FSL_SAI_TFR             0x40
-#define FSL_SAI_TMR             0x60
-
-/* SAI Recieve Data/FIFO/MASK Register */
-#define FSL_SAI_RDR             0xa0
-#define FSL_SAI_RFR             0xc0
-#define FSL_SAI_RMR             0xe0
-
 /* SAI Transmit and Recieve Configuration 1 Register */
-#define FSL_SAI_TCR1            0x04
-#define FSL_SAI_RCR1            0x84
+#define FSL_SAI_CR1_RFW_MASK    0x1f
 
 /* SAI Transmit and Recieve Configuration 2 Register */
-#define FSL_SAI_TCR2            0x08
-#define FSL_SAI_RCR2            0x88
 #define FSL_SAI_CR2_SYNC        BIT(30)
 #define FSL_SAI_CR2_MSEL_MASK   (0xff << 26)
 #define FSL_SAI_CR2_MSEL_BUS    0
@@ -50,15 +55,11 @@
 #define FSL_SAI_CR2_BCD_MSTR    BIT(24)
 
 /* SAI Transmit and Recieve Configuration 3 Register */
-#define FSL_SAI_TCR3            0x0c
-#define FSL_SAI_RCR3            0x8c
 #define FSL_SAI_CR3_TRCE        BIT(16)
 #define FSL_SAI_CR3_WDFL(x)     (x)
 #define FSL_SAI_CR3_WDFL_MASK   0x1f
 
 /* SAI Transmit and Recieve Configuration 4 Register */
-#define FSL_SAI_TCR4            0x10
-#define FSL_SAI_RCR4            0x90
 #define FSL_SAI_CR4_FRSZ(x)     (((x) - 1) << 16)
 #define FSL_SAI_CR4_FRSZ_MASK   (0x1f << 16)
 #define FSL_SAI_CR4_SYWD(x)     (((x) - 1) << 8)
@@ -69,8 +70,6 @@
 #define FSL_SAI_CR4_FSD_MSTR    BIT(0)
 
 /* SAI Transmit and Recieve Configuration 5 Register */
-#define FSL_SAI_TCR5            0x14
-#define FSL_SAI_RCR5            0x94
 #define FSL_SAI_CR5_WNW(x)      (((x) - 1) << 24)
 #define FSL_SAI_CR5_WNW_MASK    (0x1f << 24)
 #define FSL_SAI_CR5_W0W(x)      (((x) - 1) << 16)
@@ -100,12 +99,11 @@
 #define FSL_SAI_MAXBURST_RX 6
 
 struct fsl_sai {
-        struct clk *clk;
-
-        void __iomem *base;
+        struct regmap *regmap;
 
         bool big_endian_regs;
         bool big_endian_data;
+        bool is_dsp_mode;
 
         struct snd_dmaengine_dai_dma_data dma_params_rx;
         struct snd_dmaengine_dai_dma_data dma_params_tx;