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-rw-r--r--sound/soc/davinci/davinci-mcasp.c277
1 files changed, 146 insertions, 131 deletions
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index b7858bfa0295..b0ae0677f023 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -37,6 +37,16 @@
37#include "davinci-pcm.h" 37#include "davinci-pcm.h"
38#include "davinci-mcasp.h" 38#include "davinci-mcasp.h"
39 39
40struct davinci_mcasp_context {
41 u32 txfmtctl;
42 u32 rxfmtctl;
43 u32 txfmt;
44 u32 rxfmt;
45 u32 aclkxctl;
46 u32 aclkrctl;
47 u32 pdir;
48};
49
40struct davinci_mcasp { 50struct davinci_mcasp {
41 struct davinci_pcm_dma_params dma_params[2]; 51 struct davinci_pcm_dma_params dma_params[2];
42 struct snd_dmaengine_dai_dma_data dma_data[2]; 52 struct snd_dmaengine_dai_dma_data dma_data[2];
@@ -53,6 +63,9 @@ struct davinci_mcasp {
53 u16 bclk_lrclk_ratio; 63 u16 bclk_lrclk_ratio;
54 int streams; 64 int streams;
55 65
66 int sysclk_freq;
67 bool bclk_master;
68
56 /* McASP FIFO related */ 69 /* McASP FIFO related */
57 u8 txnumevt; 70 u8 txnumevt;
58 u8 rxnumevt; 71 u8 rxnumevt;
@@ -60,15 +73,7 @@ struct davinci_mcasp {
60 bool dat_port; 73 bool dat_port;
61 74
62#ifdef CONFIG_PM_SLEEP 75#ifdef CONFIG_PM_SLEEP
63 struct { 76 struct davinci_mcasp_context context;
64 u32 txfmtctl;
65 u32 rxfmtctl;
66 u32 txfmt;
67 u32 rxfmt;
68 u32 aclkxctl;
69 u32 aclkrctl;
70 u32 pdir;
71 } context;
72#endif 77#endif
73}; 78};
74 79
@@ -263,7 +268,9 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
263 unsigned int fmt) 268 unsigned int fmt)
264{ 269{
265 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 270 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
271 int ret = 0;
266 272
273 pm_runtime_get_sync(mcasp->dev);
267 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 274 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
268 case SND_SOC_DAIFMT_DSP_B: 275 case SND_SOC_DAIFMT_DSP_B:
269 case SND_SOC_DAIFMT_AC97: 276 case SND_SOC_DAIFMT_AC97:
@@ -292,6 +299,7 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
292 299
293 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); 300 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
294 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); 301 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
302 mcasp->bclk_master = 1;
295 break; 303 break;
296 case SND_SOC_DAIFMT_CBM_CFS: 304 case SND_SOC_DAIFMT_CBM_CFS:
297 /* codec is clock master and frame slave */ 305 /* codec is clock master and frame slave */
@@ -303,6 +311,7 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
303 311
304 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); 312 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
305 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); 313 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
314 mcasp->bclk_master = 0;
306 break; 315 break;
307 case SND_SOC_DAIFMT_CBM_CFM: 316 case SND_SOC_DAIFMT_CBM_CFM:
308 /* codec is clock and frame master */ 317 /* codec is clock and frame master */
@@ -314,10 +323,12 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
314 323
315 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, 324 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
316 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); 325 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
326 mcasp->bclk_master = 0;
317 break; 327 break;
318 328
319 default: 329 default:
320 return -EINVAL; 330 ret = -EINVAL;
331 goto out;
321 } 332 }
322 333
323 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 334 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
@@ -354,10 +365,12 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
354 break; 365 break;
355 366
356 default: 367 default:
357 return -EINVAL; 368 ret = -EINVAL;
369 break;
358 } 370 }
359 371out:
360 return 0; 372 pm_runtime_put_sync(mcasp->dev);
373 return ret;
361} 374}
362 375
363static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) 376static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
@@ -405,6 +418,8 @@ static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
405 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); 418 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
406 } 419 }
407 420
421 mcasp->sysclk_freq = freq;
422
408 return 0; 423 return 0;
409} 424}
410 425
@@ -448,7 +463,7 @@ static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
448 return 0; 463 return 0;
449} 464}
450 465
451static int davinci_hw_common_param(struct davinci_mcasp *mcasp, int stream, 466static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
452 int channels) 467 int channels)
453{ 468{
454 int i; 469 int i;
@@ -524,12 +539,18 @@ static int davinci_hw_common_param(struct davinci_mcasp *mcasp, int stream,
524 return 0; 539 return 0;
525} 540}
526 541
527static void davinci_hw_param(struct davinci_mcasp *mcasp, int stream) 542static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
528{ 543{
529 int i, active_slots; 544 int i, active_slots;
530 u32 mask = 0; 545 u32 mask = 0;
531 u32 busel = 0; 546 u32 busel = 0;
532 547
548 if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) {
549 dev_err(mcasp->dev, "tdm slot %d not supported\n",
550 mcasp->tdm_slots);
551 return -EINVAL;
552 }
553
533 active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots; 554 active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
534 for (i = 0; i < active_slots; i++) 555 for (i = 0; i < active_slots; i++)
535 mask |= (1 << i); 556 mask |= (1 << i);
@@ -539,35 +560,21 @@ static void davinci_hw_param(struct davinci_mcasp *mcasp, int stream)
539 if (!mcasp->dat_port) 560 if (!mcasp->dat_port)
540 busel = TXSEL; 561 busel = TXSEL;
541 562
542 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 563 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
543 /* bit stream is MSB first with no delay */ 564 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
544 /* DSP_B mode */ 565 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
545 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); 566 FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
546 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); 567
547 568 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
548 if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32)) 569 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
549 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 570 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
550 FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF)); 571 FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
551 else 572
552 printk(KERN_ERR "playback tdm slot %d not supported\n", 573 return 0;
553 mcasp->tdm_slots);
554 } else {
555 /* bit stream is MSB first with no delay */
556 /* DSP_B mode */
557 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
558 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
559
560 if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32))
561 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
562 FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
563 else
564 printk(KERN_ERR "capture tdm slot %d not supported\n",
565 mcasp->tdm_slots);
566 }
567} 574}
568 575
569/* S/PDIF */ 576/* S/PDIF */
570static void davinci_hw_dit_param(struct davinci_mcasp *mcasp) 577static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp)
571{ 578{
572 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 579 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
573 and LSB first */ 580 and LSB first */
@@ -589,6 +596,8 @@ static void davinci_hw_dit_param(struct davinci_mcasp *mcasp)
589 596
590 /* Enable the DIT */ 597 /* Enable the DIT */
591 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); 598 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
599
600 return 0;
592} 601}
593 602
594static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, 603static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
@@ -604,24 +613,31 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
604 u8 fifo_level; 613 u8 fifo_level;
605 u8 slots = mcasp->tdm_slots; 614 u8 slots = mcasp->tdm_slots;
606 u8 active_serializers; 615 u8 active_serializers;
607 int channels; 616 int channels = params_channels(params);
608 struct snd_interval *pcm_channels = hw_param_interval(params, 617 int ret;
609 SNDRV_PCM_HW_PARAM_CHANNELS);
610 channels = pcm_channels->min;
611 618
612 active_serializers = (channels + slots - 1) / slots; 619 /* If mcasp is BCLK master we need to set BCLK divider */
620 if (mcasp->bclk_master) {
621 unsigned int bclk_freq = snd_soc_params_to_bclk(params);
622 if (mcasp->sysclk_freq % bclk_freq != 0) {
623 dev_err(mcasp->dev, "Can't produce requred BCLK\n");
624 return -EINVAL;
625 }
626 davinci_mcasp_set_clkdiv(
627 cpu_dai, 1, mcasp->sysclk_freq / bclk_freq);
628 }
613 629
614 if (davinci_hw_common_param(mcasp, substream->stream, channels) == -EINVAL) 630 ret = mcasp_common_hw_param(mcasp, substream->stream, channels);
615 return -EINVAL; 631 if (ret)
616 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 632 return ret;
617 fifo_level = mcasp->txnumevt * active_serializers;
618 else
619 fifo_level = mcasp->rxnumevt * active_serializers;
620 633
621 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 634 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
622 davinci_hw_dit_param(mcasp); 635 ret = mcasp_dit_hw_param(mcasp);
623 else 636 else
624 davinci_hw_param(mcasp, substream->stream); 637 ret = mcasp_i2s_hw_param(mcasp, substream->stream);
638
639 if (ret)
640 return ret;
625 641
626 switch (params_format(params)) { 642 switch (params_format(params)) {
627 case SNDRV_PCM_FORMAT_U8: 643 case SNDRV_PCM_FORMAT_U8:
@@ -655,6 +671,13 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
655 return -EINVAL; 671 return -EINVAL;
656 } 672 }
657 673
674 /* Calculate FIFO level */
675 active_serializers = (channels + slots - 1) / slots;
676 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
677 fifo_level = mcasp->txnumevt * active_serializers;
678 else
679 fifo_level = mcasp->rxnumevt * active_serializers;
680
658 if (mcasp->version == MCASP_VERSION_2 && !fifo_level) 681 if (mcasp->version == MCASP_VERSION_2 && !fifo_level)
659 dma_params->acnt = 4; 682 dma_params->acnt = 4;
660 else 683 else
@@ -678,19 +701,9 @@ static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
678 case SNDRV_PCM_TRIGGER_RESUME: 701 case SNDRV_PCM_TRIGGER_RESUME:
679 case SNDRV_PCM_TRIGGER_START: 702 case SNDRV_PCM_TRIGGER_START:
680 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 703 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
681 ret = pm_runtime_get_sync(mcasp->dev);
682 if (IS_ERR_VALUE(ret))
683 dev_err(mcasp->dev, "pm_runtime_get_sync() failed\n");
684 davinci_mcasp_start(mcasp, substream->stream); 704 davinci_mcasp_start(mcasp, substream->stream);
685 break; 705 break;
686
687 case SNDRV_PCM_TRIGGER_SUSPEND: 706 case SNDRV_PCM_TRIGGER_SUSPEND:
688 davinci_mcasp_stop(mcasp, substream->stream);
689 ret = pm_runtime_put_sync(mcasp->dev);
690 if (IS_ERR_VALUE(ret))
691 dev_err(mcasp->dev, "pm_runtime_put_sync() failed\n");
692 break;
693
694 case SNDRV_PCM_TRIGGER_STOP: 707 case SNDRV_PCM_TRIGGER_STOP:
695 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 708 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
696 davinci_mcasp_stop(mcasp, substream->stream); 709 davinci_mcasp_stop(mcasp, substream->stream);
@@ -726,6 +739,43 @@ static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
726 .set_sysclk = davinci_mcasp_set_sysclk, 739 .set_sysclk = davinci_mcasp_set_sysclk,
727}; 740};
728 741
742#ifdef CONFIG_PM_SLEEP
743static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
744{
745 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
746 struct davinci_mcasp_context *context = &mcasp->context;
747
748 context->txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
749 context->rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
750 context->txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
751 context->rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
752 context->aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
753 context->aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
754 context->pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
755
756 return 0;
757}
758
759static int davinci_mcasp_resume(struct snd_soc_dai *dai)
760{
761 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
762 struct davinci_mcasp_context *context = &mcasp->context;
763
764 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, context->txfmtctl);
765 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, context->rxfmtctl);
766 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, context->txfmt);
767 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, context->rxfmt);
768 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, context->aclkxctl);
769 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, context->aclkrctl);
770 mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, context->pdir);
771
772 return 0;
773}
774#else
775#define davinci_mcasp_suspend NULL
776#define davinci_mcasp_resume NULL
777#endif
778
729#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 779#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
730 780
731#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 781#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
@@ -742,6 +792,8 @@ static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
742static struct snd_soc_dai_driver davinci_mcasp_dai[] = { 792static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
743 { 793 {
744 .name = "davinci-mcasp.0", 794 .name = "davinci-mcasp.0",
795 .suspend = davinci_mcasp_suspend,
796 .resume = davinci_mcasp_resume,
745 .playback = { 797 .playback = {
746 .channels_min = 2, 798 .channels_min = 2,
747 .channels_max = 32 * 16, 799 .channels_max = 32 * 16,
@@ -775,28 +827,28 @@ static const struct snd_soc_component_driver davinci_mcasp_component = {
775}; 827};
776 828
777/* Some HW specific values and defaults. The rest is filled in from DT. */ 829/* Some HW specific values and defaults. The rest is filled in from DT. */
778static struct snd_platform_data dm646x_mcasp_pdata = { 830static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
779 .tx_dma_offset = 0x400, 831 .tx_dma_offset = 0x400,
780 .rx_dma_offset = 0x400, 832 .rx_dma_offset = 0x400,
781 .asp_chan_q = EVENTQ_0, 833 .asp_chan_q = EVENTQ_0,
782 .version = MCASP_VERSION_1, 834 .version = MCASP_VERSION_1,
783}; 835};
784 836
785static struct snd_platform_data da830_mcasp_pdata = { 837static struct davinci_mcasp_pdata da830_mcasp_pdata = {
786 .tx_dma_offset = 0x2000, 838 .tx_dma_offset = 0x2000,
787 .rx_dma_offset = 0x2000, 839 .rx_dma_offset = 0x2000,
788 .asp_chan_q = EVENTQ_0, 840 .asp_chan_q = EVENTQ_0,
789 .version = MCASP_VERSION_2, 841 .version = MCASP_VERSION_2,
790}; 842};
791 843
792static struct snd_platform_data am33xx_mcasp_pdata = { 844static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
793 .tx_dma_offset = 0, 845 .tx_dma_offset = 0,
794 .rx_dma_offset = 0, 846 .rx_dma_offset = 0,
795 .asp_chan_q = EVENTQ_0, 847 .asp_chan_q = EVENTQ_0,
796 .version = MCASP_VERSION_3, 848 .version = MCASP_VERSION_3,
797}; 849};
798 850
799static struct snd_platform_data dra7_mcasp_pdata = { 851static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
800 .tx_dma_offset = 0x200, 852 .tx_dma_offset = 0x200,
801 .rx_dma_offset = 0x284, 853 .rx_dma_offset = 0x284,
802 .asp_chan_q = EVENTQ_0, 854 .asp_chan_q = EVENTQ_0,
@@ -864,11 +916,11 @@ err1:
864 return ret; 916 return ret;
865} 917}
866 918
867static struct snd_platform_data *davinci_mcasp_set_pdata_from_of( 919static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
868 struct platform_device *pdev) 920 struct platform_device *pdev)
869{ 921{
870 struct device_node *np = pdev->dev.of_node; 922 struct device_node *np = pdev->dev.of_node;
871 struct snd_platform_data *pdata = NULL; 923 struct davinci_mcasp_pdata *pdata = NULL;
872 const struct of_device_id *match = 924 const struct of_device_id *match =
873 of_match_device(mcasp_dt_ids, &pdev->dev); 925 of_match_device(mcasp_dt_ids, &pdev->dev);
874 struct of_phandle_args dma_spec; 926 struct of_phandle_args dma_spec;
@@ -881,7 +933,7 @@ static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
881 pdata = pdev->dev.platform_data; 933 pdata = pdev->dev.platform_data;
882 return pdata; 934 return pdata;
883 } else if (match) { 935 } else if (match) {
884 pdata = (struct snd_platform_data *) match->data; 936 pdata = (struct davinci_mcasp_pdata*) match->data;
885 } else { 937 } else {
886 /* control shouldn't reach here. something is wrong */ 938 /* control shouldn't reach here. something is wrong */
887 ret = -EINVAL; 939 ret = -EINVAL;
@@ -973,9 +1025,9 @@ nodata:
973 1025
974static int davinci_mcasp_probe(struct platform_device *pdev) 1026static int davinci_mcasp_probe(struct platform_device *pdev)
975{ 1027{
976 struct davinci_pcm_dma_params *dma_data; 1028 struct davinci_pcm_dma_params *dma_params;
977 struct resource *mem, *ioarea, *res, *dat; 1029 struct resource *mem, *ioarea, *res, *dat;
978 struct snd_platform_data *pdata; 1030 struct davinci_mcasp_pdata *pdata;
979 struct davinci_mcasp *mcasp; 1031 struct davinci_mcasp *mcasp;
980 int ret; 1032 int ret;
981 1033
@@ -1042,41 +1094,41 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
1042 if (dat) 1094 if (dat)
1043 mcasp->dat_port = true; 1095 mcasp->dat_port = true;
1044 1096
1045 dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; 1097 dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1046 dma_data->asp_chan_q = pdata->asp_chan_q; 1098 dma_params->asp_chan_q = pdata->asp_chan_q;
1047 dma_data->ram_chan_q = pdata->ram_chan_q; 1099 dma_params->ram_chan_q = pdata->ram_chan_q;
1048 dma_data->sram_pool = pdata->sram_pool; 1100 dma_params->sram_pool = pdata->sram_pool;
1049 dma_data->sram_size = pdata->sram_size_playback; 1101 dma_params->sram_size = pdata->sram_size_playback;
1050 if (dat) 1102 if (dat)
1051 dma_data->dma_addr = dat->start; 1103 dma_params->dma_addr = dat->start;
1052 else 1104 else
1053 dma_data->dma_addr = mem->start + pdata->tx_dma_offset; 1105 dma_params->dma_addr = mem->start + pdata->tx_dma_offset;
1054 1106
1055 /* Unconditional dmaengine stuff */ 1107 /* Unconditional dmaengine stuff */
1056 mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = dma_data->dma_addr; 1108 mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = dma_params->dma_addr;
1057 1109
1058 res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1110 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1059 if (res) 1111 if (res)
1060 dma_data->channel = res->start; 1112 dma_params->channel = res->start;
1061 else 1113 else
1062 dma_data->channel = pdata->tx_dma_channel; 1114 dma_params->channel = pdata->tx_dma_channel;
1063 1115
1064 dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE]; 1116 dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1065 dma_data->asp_chan_q = pdata->asp_chan_q; 1117 dma_params->asp_chan_q = pdata->asp_chan_q;
1066 dma_data->ram_chan_q = pdata->ram_chan_q; 1118 dma_params->ram_chan_q = pdata->ram_chan_q;
1067 dma_data->sram_pool = pdata->sram_pool; 1119 dma_params->sram_pool = pdata->sram_pool;
1068 dma_data->sram_size = pdata->sram_size_capture; 1120 dma_params->sram_size = pdata->sram_size_capture;
1069 if (dat) 1121 if (dat)
1070 dma_data->dma_addr = dat->start; 1122 dma_params->dma_addr = dat->start;
1071 else 1123 else
1072 dma_data->dma_addr = mem->start + pdata->rx_dma_offset; 1124 dma_params->dma_addr = mem->start + pdata->rx_dma_offset;
1073 1125
1074 /* Unconditional dmaengine stuff */ 1126 /* Unconditional dmaengine stuff */
1075 mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = dma_data->dma_addr; 1127 mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = dma_params->dma_addr;
1076 1128
1077 if (mcasp->version < MCASP_VERSION_3) { 1129 if (mcasp->version < MCASP_VERSION_3) {
1078 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; 1130 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
1079 /* dma_data->dma_addr is pointing to the data port address */ 1131 /* dma_params->dma_addr is pointing to the data port address */
1080 mcasp->dat_port = true; 1132 mcasp->dat_port = true;
1081 } else { 1133 } else {
1082 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; 1134 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
@@ -1084,9 +1136,9 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
1084 1136
1085 res = platform_get_resource(pdev, IORESOURCE_DMA, 1); 1137 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1086 if (res) 1138 if (res)
1087 dma_data->channel = res->start; 1139 dma_params->channel = res->start;
1088 else 1140 else
1089 dma_data->channel = pdata->rx_dma_channel; 1141 dma_params->channel = pdata->rx_dma_channel;
1090 1142
1091 /* Unconditional dmaengine stuff */ 1143 /* Unconditional dmaengine stuff */
1092 mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data = "tx"; 1144 mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data = "tx";
@@ -1134,49 +1186,12 @@ static int davinci_mcasp_remove(struct platform_device *pdev)
1134 return 0; 1186 return 0;
1135} 1187}
1136 1188
1137#ifdef CONFIG_PM_SLEEP
1138static int davinci_mcasp_suspend(struct device *dev)
1139{
1140 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
1141
1142 mcasp->context.txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
1143 mcasp->context.rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
1144 mcasp->context.txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
1145 mcasp->context.rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
1146 mcasp->context.aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
1147 mcasp->context.aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
1148 mcasp->context.pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
1149
1150 return 0;
1151}
1152
1153static int davinci_mcasp_resume(struct device *dev)
1154{
1155 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
1156
1157 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, mcasp->context.txfmtctl);
1158 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, mcasp->context.rxfmtctl);
1159 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, mcasp->context.txfmt);
1160 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, mcasp->context.rxfmt);
1161 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, mcasp->context.aclkxctl);
1162 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, mcasp->context.aclkrctl);
1163 mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, mcasp->context.pdir);
1164
1165 return 0;
1166}
1167#endif
1168
1169SIMPLE_DEV_PM_OPS(davinci_mcasp_pm_ops,
1170 davinci_mcasp_suspend,
1171 davinci_mcasp_resume);
1172
1173static struct platform_driver davinci_mcasp_driver = { 1189static struct platform_driver davinci_mcasp_driver = {
1174 .probe = davinci_mcasp_probe, 1190 .probe = davinci_mcasp_probe,
1175 .remove = davinci_mcasp_remove, 1191 .remove = davinci_mcasp_remove,
1176 .driver = { 1192 .driver = {
1177 .name = "davinci-mcasp", 1193 .name = "davinci-mcasp",
1178 .owner = THIS_MODULE, 1194 .owner = THIS_MODULE,
1179 .pm = &davinci_mcasp_pm_ops,
1180 .of_match_table = mcasp_dt_ids, 1195 .of_match_table = mcasp_dt_ids,
1181 }, 1196 },
1182}; 1197};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 18:20:28 -0500