aboutsummaryrefslogtreecommitdiffstats
path: root/sound/soc/codecs
diff options
context:
space:
mode:
Diffstat (limited to 'sound/soc/codecs')
-rw-r--r--sound/soc/codecs/Kconfig24
-rw-r--r--sound/soc/codecs/Makefile12
-rw-r--r--sound/soc/codecs/ac97.c4
-rw-r--r--sound/soc/codecs/ad1980.c4
-rw-r--r--sound/soc/codecs/cs4270.c105
-rw-r--r--sound/soc/codecs/spdif_transciever.c71
-rw-r--r--sound/soc/codecs/spdif_transciever.h17
-rw-r--r--sound/soc/codecs/ssm2602.c33
-rw-r--r--sound/soc/codecs/stac9766.c463
-rw-r--r--sound/soc/codecs/stac9766.h21
-rw-r--r--sound/soc/codecs/tlv320aic23.c16
-rw-r--r--sound/soc/codecs/twl4030.c1116
-rw-r--r--sound/soc/codecs/twl4030.h43
-rw-r--r--sound/soc/codecs/uda134x.c4
-rw-r--r--sound/soc/codecs/wm8350.c2
-rw-r--r--sound/soc/codecs/wm8350.h1
-rw-r--r--sound/soc/codecs/wm8400.c8
-rw-r--r--sound/soc/codecs/wm8510.c2
-rw-r--r--sound/soc/codecs/wm8580.c4
-rw-r--r--sound/soc/codecs/wm8731.c4
-rw-r--r--sound/soc/codecs/wm8753.c6
-rw-r--r--sound/soc/codecs/wm8900.c6
-rw-r--r--sound/soc/codecs/wm8903.c119
-rw-r--r--sound/soc/codecs/wm8940.c955
-rw-r--r--sound/soc/codecs/wm8940.h104
-rw-r--r--sound/soc/codecs/wm8960.c969
-rw-r--r--sound/soc/codecs/wm8960.h127
-rw-r--r--sound/soc/codecs/wm8988.c1097
-rw-r--r--sound/soc/codecs/wm8988.h60
-rw-r--r--sound/soc/codecs/wm8990.c2
-rw-r--r--sound/soc/codecs/wm9081.c1534
-rw-r--r--sound/soc/codecs/wm9081.h787
-rw-r--r--sound/soc/codecs/wm9705.c4
-rw-r--r--sound/soc/codecs/wm9712.c8
-rw-r--r--sound/soc/codecs/wm9713.c48
35 files changed, 7392 insertions, 388 deletions
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index b6c7f7a01cb0..bbc97fd76648 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -18,7 +18,9 @@ config SND_SOC_ALL_CODECS
18 select SND_SOC_AK4535 if I2C 18 select SND_SOC_AK4535 if I2C
19 select SND_SOC_CS4270 if I2C 19 select SND_SOC_CS4270 if I2C
20 select SND_SOC_PCM3008 20 select SND_SOC_PCM3008
21 select SND_SOC_SPDIF
21 select SND_SOC_SSM2602 if I2C 22 select SND_SOC_SSM2602 if I2C
23 select SND_SOC_STAC9766 if SND_SOC_AC97_BUS
22 select SND_SOC_TLV320AIC23 if I2C 24 select SND_SOC_TLV320AIC23 if I2C
23 select SND_SOC_TLV320AIC26 if SPI_MASTER 25 select SND_SOC_TLV320AIC26 if SPI_MASTER
24 select SND_SOC_TLV320AIC3X if I2C 26 select SND_SOC_TLV320AIC3X if I2C
@@ -35,8 +37,12 @@ config SND_SOC_ALL_CODECS
35 select SND_SOC_WM8753 if SND_SOC_I2C_AND_SPI 37 select SND_SOC_WM8753 if SND_SOC_I2C_AND_SPI
36 select SND_SOC_WM8900 if I2C 38 select SND_SOC_WM8900 if I2C
37 select SND_SOC_WM8903 if I2C 39 select SND_SOC_WM8903 if I2C
40 select SND_SOC_WM8940 if I2C
41 select SND_SOC_WM8960 if I2C
38 select SND_SOC_WM8971 if I2C 42 select SND_SOC_WM8971 if I2C
43 select SND_SOC_WM8988 if SND_SOC_I2C_AND_SPI
39 select SND_SOC_WM8990 if I2C 44 select SND_SOC_WM8990 if I2C
45 select SND_SOC_WM9081 if I2C
40 select SND_SOC_WM9705 if SND_SOC_AC97_BUS 46 select SND_SOC_WM9705 if SND_SOC_AC97_BUS
41 select SND_SOC_WM9712 if SND_SOC_AC97_BUS 47 select SND_SOC_WM9712 if SND_SOC_AC97_BUS
42 select SND_SOC_WM9713 if SND_SOC_AC97_BUS 48 select SND_SOC_WM9713 if SND_SOC_AC97_BUS
@@ -86,9 +92,15 @@ config SND_SOC_L3
86config SND_SOC_PCM3008 92config SND_SOC_PCM3008
87 tristate 93 tristate
88 94
95config SND_SOC_SPDIF
96 tristate
97
89config SND_SOC_SSM2602 98config SND_SOC_SSM2602
90 tristate 99 tristate
91 100
101config SND_SOC_STAC9766
102 tristate
103
92config SND_SOC_TLV320AIC23 104config SND_SOC_TLV320AIC23
93 tristate 105 tristate
94 106
@@ -138,12 +150,24 @@ config SND_SOC_WM8900
138config SND_SOC_WM8903 150config SND_SOC_WM8903
139 tristate 151 tristate
140 152
153config SND_SOC_WM8940
154 tristate
155
156config SND_SOC_WM8960
157 tristate
158
141config SND_SOC_WM8971 159config SND_SOC_WM8971
142 tristate 160 tristate
143 161
162config SND_SOC_WM8988
163 tristate
164
144config SND_SOC_WM8990 165config SND_SOC_WM8990
145 tristate 166 tristate
146 167
168config SND_SOC_WM9081
169 tristate
170
147config SND_SOC_WM9705 171config SND_SOC_WM9705
148 tristate 172 tristate
149 173
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index f2653803ede8..8b7530546f4d 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -6,7 +6,9 @@ snd-soc-ak4535-objs := ak4535.o
6snd-soc-cs4270-objs := cs4270.o 6snd-soc-cs4270-objs := cs4270.o
7snd-soc-l3-objs := l3.o 7snd-soc-l3-objs := l3.o
8snd-soc-pcm3008-objs := pcm3008.o 8snd-soc-pcm3008-objs := pcm3008.o
9snd-soc-spdif-objs := spdif_transciever.o
9snd-soc-ssm2602-objs := ssm2602.o 10snd-soc-ssm2602-objs := ssm2602.o
11snd-soc-stac9766-objs := stac9766.o
10snd-soc-tlv320aic23-objs := tlv320aic23.o 12snd-soc-tlv320aic23-objs := tlv320aic23.o
11snd-soc-tlv320aic26-objs := tlv320aic26.o 13snd-soc-tlv320aic26-objs := tlv320aic26.o
12snd-soc-tlv320aic3x-objs := tlv320aic3x.o 14snd-soc-tlv320aic3x-objs := tlv320aic3x.o
@@ -23,8 +25,12 @@ snd-soc-wm8750-objs := wm8750.o
23snd-soc-wm8753-objs := wm8753.o 25snd-soc-wm8753-objs := wm8753.o
24snd-soc-wm8900-objs := wm8900.o 26snd-soc-wm8900-objs := wm8900.o
25snd-soc-wm8903-objs := wm8903.o 27snd-soc-wm8903-objs := wm8903.o
28snd-soc-wm8940-objs := wm8940.o
29snd-soc-wm8960-objs := wm8960.o
26snd-soc-wm8971-objs := wm8971.o 30snd-soc-wm8971-objs := wm8971.o
31snd-soc-wm8988-objs := wm8988.o
27snd-soc-wm8990-objs := wm8990.o 32snd-soc-wm8990-objs := wm8990.o
33snd-soc-wm9081-objs := wm9081.o
28snd-soc-wm9705-objs := wm9705.o 34snd-soc-wm9705-objs := wm9705.o
29snd-soc-wm9712-objs := wm9712.o 35snd-soc-wm9712-objs := wm9712.o
30snd-soc-wm9713-objs := wm9713.o 36snd-soc-wm9713-objs := wm9713.o
@@ -37,7 +43,9 @@ obj-$(CONFIG_SND_SOC_AK4535) += snd-soc-ak4535.o
37obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o 43obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o
38obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o 44obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o
39obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o 45obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o
46obj-$(CONFIG_SND_SOC_SPDIF) += snd-soc-spdif.o
40obj-$(CONFIG_SND_SOC_SSM2602) += snd-soc-ssm2602.o 47obj-$(CONFIG_SND_SOC_SSM2602) += snd-soc-ssm2602.o
48obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o
41obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o 49obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o
42obj-$(CONFIG_SND_SOC_TLV320AIC26) += snd-soc-tlv320aic26.o 50obj-$(CONFIG_SND_SOC_TLV320AIC26) += snd-soc-tlv320aic26.o
43obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o 51obj-$(CONFIG_SND_SOC_TLV320AIC3X) += snd-soc-tlv320aic3x.o
@@ -55,7 +63,11 @@ obj-$(CONFIG_SND_SOC_WM8753) += snd-soc-wm8753.o
55obj-$(CONFIG_SND_SOC_WM8900) += snd-soc-wm8900.o 63obj-$(CONFIG_SND_SOC_WM8900) += snd-soc-wm8900.o
56obj-$(CONFIG_SND_SOC_WM8903) += snd-soc-wm8903.o 64obj-$(CONFIG_SND_SOC_WM8903) += snd-soc-wm8903.o
57obj-$(CONFIG_SND_SOC_WM8971) += snd-soc-wm8971.o 65obj-$(CONFIG_SND_SOC_WM8971) += snd-soc-wm8971.o
66obj-$(CONFIG_SND_SOC_WM8940) += snd-soc-wm8940.o
67obj-$(CONFIG_SND_SOC_WM8960) += snd-soc-wm8960.o
68obj-$(CONFIG_SND_SOC_WM8988) += snd-soc-wm8988.o
58obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o 69obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o
70obj-$(CONFIG_SND_SOC_WM9081) += snd-soc-wm9081.o
59obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o 71obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o
60obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o 72obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o
61obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o 73obj-$(CONFIG_SND_SOC_WM9713) += snd-soc-wm9713.o
diff --git a/sound/soc/codecs/ac97.c b/sound/soc/codecs/ac97.c
index b0d4af145b87..932299bb5d1e 100644
--- a/sound/soc/codecs/ac97.c
+++ b/sound/soc/codecs/ac97.c
@@ -53,13 +53,13 @@ struct snd_soc_dai ac97_dai = {
53 .channels_min = 1, 53 .channels_min = 1,
54 .channels_max = 2, 54 .channels_max = 2,
55 .rates = STD_AC97_RATES, 55 .rates = STD_AC97_RATES,
56 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 56 .formats = SND_SOC_STD_AC97_FMTS,},
57 .capture = { 57 .capture = {
58 .stream_name = "AC97 Capture", 58 .stream_name = "AC97 Capture",
59 .channels_min = 1, 59 .channels_min = 1,
60 .channels_max = 2, 60 .channels_max = 2,
61 .rates = STD_AC97_RATES, 61 .rates = STD_AC97_RATES,
62 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 62 .formats = SND_SOC_STD_AC97_FMTS,},
63 .ops = &ac97_dai_ops, 63 .ops = &ac97_dai_ops,
64}; 64};
65EXPORT_SYMBOL_GPL(ac97_dai); 65EXPORT_SYMBOL_GPL(ac97_dai);
diff --git a/sound/soc/codecs/ad1980.c b/sound/soc/codecs/ad1980.c
index ddb3b08ac23c..d7440a982d22 100644
--- a/sound/soc/codecs/ad1980.c
+++ b/sound/soc/codecs/ad1980.c
@@ -137,13 +137,13 @@ struct snd_soc_dai ad1980_dai = {
137 .channels_min = 2, 137 .channels_min = 2,
138 .channels_max = 6, 138 .channels_max = 6,
139 .rates = SNDRV_PCM_RATE_48000, 139 .rates = SNDRV_PCM_RATE_48000,
140 .formats = SNDRV_PCM_FMTBIT_S16_LE, }, 140 .formats = SND_SOC_STD_AC97_FMTS, },
141 .capture = { 141 .capture = {
142 .stream_name = "Capture", 142 .stream_name = "Capture",
143 .channels_min = 2, 143 .channels_min = 2,
144 .channels_max = 2, 144 .channels_max = 2,
145 .rates = SNDRV_PCM_RATE_48000, 145 .rates = SNDRV_PCM_RATE_48000,
146 .formats = SNDRV_PCM_FMTBIT_S16_LE, }, 146 .formats = SND_SOC_STD_AC97_FMTS, },
147}; 147};
148EXPORT_SYMBOL_GPL(ad1980_dai); 148EXPORT_SYMBOL_GPL(ad1980_dai);
149 149
diff --git a/sound/soc/codecs/cs4270.c b/sound/soc/codecs/cs4270.c
index 7fa09a387622..a32b8226c8a4 100644
--- a/sound/soc/codecs/cs4270.c
+++ b/sound/soc/codecs/cs4270.c
@@ -18,7 +18,7 @@
18 * - The machine driver's 'startup' function must call 18 * - The machine driver's 'startup' function must call
19 * cs4270_set_dai_sysclk() with the value of MCLK. 19 * cs4270_set_dai_sysclk() with the value of MCLK.
20 * - Only I2S and left-justified modes are supported 20 * - Only I2S and left-justified modes are supported
21 * - Power management is not supported 21 * - Power management is supported
22 */ 22 */
23 23
24#include <linux/module.h> 24#include <linux/module.h>
@@ -27,6 +27,7 @@
27#include <sound/soc.h> 27#include <sound/soc.h>
28#include <sound/initval.h> 28#include <sound/initval.h>
29#include <linux/i2c.h> 29#include <linux/i2c.h>
30#include <linux/delay.h>
30 31
31#include "cs4270.h" 32#include "cs4270.h"
32 33
@@ -56,6 +57,7 @@
56#define CS4270_FIRSTREG 0x01 57#define CS4270_FIRSTREG 0x01
57#define CS4270_LASTREG 0x08 58#define CS4270_LASTREG 0x08
58#define CS4270_NUMREGS (CS4270_LASTREG - CS4270_FIRSTREG + 1) 59#define CS4270_NUMREGS (CS4270_LASTREG - CS4270_FIRSTREG + 1)
60#define CS4270_I2C_INCR 0x80
59 61
60/* Bit masks for the CS4270 registers */ 62/* Bit masks for the CS4270 registers */
61#define CS4270_CHIPID_ID 0xF0 63#define CS4270_CHIPID_ID 0xF0
@@ -64,6 +66,8 @@
64#define CS4270_PWRCTL_PDN_ADC 0x20 66#define CS4270_PWRCTL_PDN_ADC 0x20
65#define CS4270_PWRCTL_PDN_DAC 0x02 67#define CS4270_PWRCTL_PDN_DAC 0x02
66#define CS4270_PWRCTL_PDN 0x01 68#define CS4270_PWRCTL_PDN 0x01
69#define CS4270_PWRCTL_PDN_ALL \
70 (CS4270_PWRCTL_PDN_ADC | CS4270_PWRCTL_PDN_DAC | CS4270_PWRCTL_PDN)
67#define CS4270_MODE_SPEED_MASK 0x30 71#define CS4270_MODE_SPEED_MASK 0x30
68#define CS4270_MODE_1X 0x00 72#define CS4270_MODE_1X 0x00
69#define CS4270_MODE_2X 0x10 73#define CS4270_MODE_2X 0x10
@@ -109,6 +113,7 @@ struct cs4270_private {
109 unsigned int mclk; /* Input frequency of the MCLK pin */ 113 unsigned int mclk; /* Input frequency of the MCLK pin */
110 unsigned int mode; /* The mode (I2S or left-justified) */ 114 unsigned int mode; /* The mode (I2S or left-justified) */
111 unsigned int slave_mode; 115 unsigned int slave_mode;
116 unsigned int manual_mute;
112}; 117};
113 118
114/** 119/**
@@ -295,7 +300,7 @@ static int cs4270_fill_cache(struct snd_soc_codec *codec)
295 s32 length; 300 s32 length;
296 301
297 length = i2c_smbus_read_i2c_block_data(i2c_client, 302 length = i2c_smbus_read_i2c_block_data(i2c_client,
298 CS4270_FIRSTREG | 0x80, CS4270_NUMREGS, cache); 303 CS4270_FIRSTREG | CS4270_I2C_INCR, CS4270_NUMREGS, cache);
299 304
300 if (length != CS4270_NUMREGS) { 305 if (length != CS4270_NUMREGS) {
301 dev_err(codec->dev, "i2c read failure, addr=0x%x\n", 306 dev_err(codec->dev, "i2c read failure, addr=0x%x\n",
@@ -453,7 +458,7 @@ static int cs4270_hw_params(struct snd_pcm_substream *substream,
453} 458}
454 459
455/** 460/**
456 * cs4270_mute - enable/disable the CS4270 external mute 461 * cs4270_dai_mute - enable/disable the CS4270 external mute
457 * @dai: the SOC DAI 462 * @dai: the SOC DAI
458 * @mute: 0 = disable mute, 1 = enable mute 463 * @mute: 0 = disable mute, 1 = enable mute
459 * 464 *
@@ -462,21 +467,52 @@ static int cs4270_hw_params(struct snd_pcm_substream *substream,
462 * board does not have the MUTEA or MUTEB pins connected to such circuitry, 467 * board does not have the MUTEA or MUTEB pins connected to such circuitry,
463 * then this function will do nothing. 468 * then this function will do nothing.
464 */ 469 */
465static int cs4270_mute(struct snd_soc_dai *dai, int mute) 470static int cs4270_dai_mute(struct snd_soc_dai *dai, int mute)
466{ 471{
467 struct snd_soc_codec *codec = dai->codec; 472 struct snd_soc_codec *codec = dai->codec;
473 struct cs4270_private *cs4270 = codec->private_data;
468 int reg6; 474 int reg6;
469 475
470 reg6 = snd_soc_read(codec, CS4270_MUTE); 476 reg6 = snd_soc_read(codec, CS4270_MUTE);
471 477
472 if (mute) 478 if (mute)
473 reg6 |= CS4270_MUTE_DAC_A | CS4270_MUTE_DAC_B; 479 reg6 |= CS4270_MUTE_DAC_A | CS4270_MUTE_DAC_B;
474 else 480 else {
475 reg6 &= ~(CS4270_MUTE_DAC_A | CS4270_MUTE_DAC_B); 481 reg6 &= ~(CS4270_MUTE_DAC_A | CS4270_MUTE_DAC_B);
482 reg6 |= cs4270->manual_mute;
483 }
476 484
477 return snd_soc_write(codec, CS4270_MUTE, reg6); 485 return snd_soc_write(codec, CS4270_MUTE, reg6);
478} 486}
479 487
488/**
489 * cs4270_soc_put_mute - put callback for the 'Master Playback switch'
490 * alsa control.
491 * @kcontrol: mixer control
492 * @ucontrol: control element information
493 *
494 * This function basically passes the arguments on to the generic
495 * snd_soc_put_volsw() function and saves the mute information in
496 * our private data structure. This is because we want to prevent
497 * cs4270_dai_mute() neglecting the user's decision to manually
498 * mute the codec's output.
499 *
500 * Returns 0 for success.
501 */
502static int cs4270_soc_put_mute(struct snd_kcontrol *kcontrol,
503 struct snd_ctl_elem_value *ucontrol)
504{
505 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
506 struct cs4270_private *cs4270 = codec->private_data;
507 int left = !ucontrol->value.integer.value[0];
508 int right = !ucontrol->value.integer.value[1];
509
510 cs4270->manual_mute = (left ? CS4270_MUTE_DAC_A : 0) |
511 (right ? CS4270_MUTE_DAC_B : 0);
512
513 return snd_soc_put_volsw(kcontrol, ucontrol);
514}
515
480/* A list of non-DAPM controls that the CS4270 supports */ 516/* A list of non-DAPM controls that the CS4270 supports */
481static const struct snd_kcontrol_new cs4270_snd_controls[] = { 517static const struct snd_kcontrol_new cs4270_snd_controls[] = {
482 SOC_DOUBLE_R("Master Playback Volume", 518 SOC_DOUBLE_R("Master Playback Volume",
@@ -486,7 +522,9 @@ static const struct snd_kcontrol_new cs4270_snd_controls[] = {
486 SOC_SINGLE("Zero Cross Switch", CS4270_TRANS, 5, 1, 0), 522 SOC_SINGLE("Zero Cross Switch", CS4270_TRANS, 5, 1, 0),
487 SOC_SINGLE("Popguard Switch", CS4270_MODE, 0, 1, 1), 523 SOC_SINGLE("Popguard Switch", CS4270_MODE, 0, 1, 1),
488 SOC_SINGLE("Auto-Mute Switch", CS4270_MUTE, 5, 1, 0), 524 SOC_SINGLE("Auto-Mute Switch", CS4270_MUTE, 5, 1, 0),
489 SOC_DOUBLE("Master Capture Switch", CS4270_MUTE, 3, 4, 1, 0) 525 SOC_DOUBLE("Master Capture Switch", CS4270_MUTE, 3, 4, 1, 1),
526 SOC_DOUBLE_EXT("Master Playback Switch", CS4270_MUTE, 0, 1, 1, 1,
527 snd_soc_get_volsw, cs4270_soc_put_mute),
490}; 528};
491 529
492/* 530/*
@@ -506,7 +544,7 @@ static struct snd_soc_dai_ops cs4270_dai_ops = {
506 .hw_params = cs4270_hw_params, 544 .hw_params = cs4270_hw_params,
507 .set_sysclk = cs4270_set_dai_sysclk, 545 .set_sysclk = cs4270_set_dai_sysclk,
508 .set_fmt = cs4270_set_dai_fmt, 546 .set_fmt = cs4270_set_dai_fmt,
509 .digital_mute = cs4270_mute, 547 .digital_mute = cs4270_dai_mute,
510}; 548};
511 549
512struct snd_soc_dai cs4270_dai = { 550struct snd_soc_dai cs4270_dai = {
@@ -753,6 +791,57 @@ static struct i2c_device_id cs4270_id[] = {
753}; 791};
754MODULE_DEVICE_TABLE(i2c, cs4270_id); 792MODULE_DEVICE_TABLE(i2c, cs4270_id);
755 793
794#ifdef CONFIG_PM
795
796/* This suspend/resume implementation can handle both - a simple standby
797 * where the codec remains powered, and a full suspend, where the voltage
798 * domain the codec is connected to is teared down and/or any other hardware
799 * reset condition is asserted.
800 *
801 * The codec's own power saving features are enabled in the suspend callback,
802 * and all registers are written back to the hardware when resuming.
803 */
804
805static int cs4270_i2c_suspend(struct i2c_client *client, pm_message_t mesg)
806{
807 struct cs4270_private *cs4270 = i2c_get_clientdata(client);
808 struct snd_soc_codec *codec = &cs4270->codec;
809 int reg = snd_soc_read(codec, CS4270_PWRCTL) | CS4270_PWRCTL_PDN_ALL;
810
811 return snd_soc_write(codec, CS4270_PWRCTL, reg);
812}
813
814static int cs4270_i2c_resume(struct i2c_client *client)
815{
816 struct cs4270_private *cs4270 = i2c_get_clientdata(client);
817 struct snd_soc_codec *codec = &cs4270->codec;
818 int reg;
819
820 /* In case the device was put to hard reset during sleep, we need to
821 * wait 500ns here before any I2C communication. */
822 ndelay(500);
823
824 /* first restore the entire register cache ... */
825 for (reg = CS4270_FIRSTREG; reg <= CS4270_LASTREG; reg++) {
826 u8 val = snd_soc_read(codec, reg);
827
828 if (i2c_smbus_write_byte_data(client, reg, val)) {
829 dev_err(codec->dev, "i2c write failed\n");
830 return -EIO;
831 }
832 }
833
834 /* ... then disable the power-down bits */
835 reg = snd_soc_read(codec, CS4270_PWRCTL);
836 reg &= ~CS4270_PWRCTL_PDN_ALL;
837
838 return snd_soc_write(codec, CS4270_PWRCTL, reg);
839}
840#else
841#define cs4270_i2c_suspend NULL
842#define cs4270_i2c_resume NULL
843#endif /* CONFIG_PM */
844
756/* 845/*
757 * cs4270_i2c_driver - I2C device identification 846 * cs4270_i2c_driver - I2C device identification
758 * 847 *
@@ -767,6 +856,8 @@ static struct i2c_driver cs4270_i2c_driver = {
767 .id_table = cs4270_id, 856 .id_table = cs4270_id,
768 .probe = cs4270_i2c_probe, 857 .probe = cs4270_i2c_probe,
769 .remove = cs4270_i2c_remove, 858 .remove = cs4270_i2c_remove,
859 .suspend = cs4270_i2c_suspend,
860 .resume = cs4270_i2c_resume,
770}; 861};
771 862
772/* 863/*
diff --git a/sound/soc/codecs/spdif_transciever.c b/sound/soc/codecs/spdif_transciever.c
new file mode 100644
index 000000000000..218b33adad90
--- /dev/null
+++ b/sound/soc/codecs/spdif_transciever.c
@@ -0,0 +1,71 @@
1/*
2 * ALSA SoC SPDIF DIT driver
3 *
4 * This driver is used by controllers which can operate in DIT (SPDI/F) where
5 * no codec is needed. This file provides stub codec that can be used
6 * in these configurations. TI DaVinci Audio controller uses this driver.
7 *
8 * Author: Steve Chen, <schen@mvista.com>
9 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
10 * Copyright: (C) 2009 Texas Instruments, India
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <sound/soc.h>
20#include <sound/pcm.h>
21
22#include "spdif_transciever.h"
23
24#define STUB_RATES SNDRV_PCM_RATE_8000_96000
25#define STUB_FORMATS SNDRV_PCM_FMTBIT_S16_LE
26
27struct snd_soc_dai dit_stub_dai = {
28 .name = "DIT",
29 .playback = {
30 .stream_name = "Playback",
31 .channels_min = 1,
32 .channels_max = 384,
33 .rates = STUB_RATES,
34 .formats = STUB_FORMATS,
35 },
36};
37
38static int spdif_dit_probe(struct platform_device *pdev)
39{
40 dit_stub_dai.dev = &pdev->dev;
41 return snd_soc_register_dai(&dit_stub_dai);
42}
43
44static int spdif_dit_remove(struct platform_device *pdev)
45{
46 snd_soc_unregister_dai(&dit_stub_dai);
47 return 0;
48}
49
50static struct platform_driver spdif_dit_driver = {
51 .probe = spdif_dit_probe,
52 .remove = spdif_dit_remove,
53 .driver = {
54 .name = "spdif-dit",
55 .owner = THIS_MODULE,
56 },
57};
58
59static int __init dit_modinit(void)
60{
61 return platform_driver_register(&spdif_dit_driver);
62}
63
64static void __exit dit_exit(void)
65{
66 platform_driver_unregister(&spdif_dit_driver);
67}
68
69module_init(dit_modinit);
70module_exit(dit_exit);
71
diff --git a/sound/soc/codecs/spdif_transciever.h b/sound/soc/codecs/spdif_transciever.h
new file mode 100644
index 000000000000..296f2eb6c4ef
--- /dev/null
+++ b/sound/soc/codecs/spdif_transciever.h
@@ -0,0 +1,17 @@
1/*
2 * ALSA SoC DIT/DIR driver header
3 *
4 * Author: Steve Chen, <schen@mvista.com>
5 * Copyright: (C) 2008 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef CODEC_STUBS_H
13#define CODEC_STUBS_H
14
15extern struct snd_soc_dai dit_stub_dai;
16
17#endif /* CODEC_STUBS_H */
diff --git a/sound/soc/codecs/ssm2602.c b/sound/soc/codecs/ssm2602.c
index 87f606c76822..1fc4c8e0899c 100644
--- a/sound/soc/codecs/ssm2602.c
+++ b/sound/soc/codecs/ssm2602.c
@@ -336,15 +336,17 @@ static int ssm2602_startup(struct snd_pcm_substream *substream,
336 master_runtime->sample_bits, 336 master_runtime->sample_bits,
337 master_runtime->rate); 337 master_runtime->rate);
338 338
339 snd_pcm_hw_constraint_minmax(substream->runtime, 339 if (master_runtime->rate != 0)
340 SNDRV_PCM_HW_PARAM_RATE, 340 snd_pcm_hw_constraint_minmax(substream->runtime,
341 master_runtime->rate, 341 SNDRV_PCM_HW_PARAM_RATE,
342 master_runtime->rate); 342 master_runtime->rate,
343 343 master_runtime->rate);
344 snd_pcm_hw_constraint_minmax(substream->runtime, 344
345 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 345 if (master_runtime->sample_bits != 0)
346 master_runtime->sample_bits, 346 snd_pcm_hw_constraint_minmax(substream->runtime,
347 master_runtime->sample_bits); 347 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
348 master_runtime->sample_bits,
349 master_runtime->sample_bits);
348 350
349 ssm2602->slave_substream = substream; 351 ssm2602->slave_substream = substream;
350 } else 352 } else
@@ -372,6 +374,11 @@ static void ssm2602_shutdown(struct snd_pcm_substream *substream,
372 struct snd_soc_device *socdev = rtd->socdev; 374 struct snd_soc_device *socdev = rtd->socdev;
373 struct snd_soc_codec *codec = socdev->card->codec; 375 struct snd_soc_codec *codec = socdev->card->codec;
374 struct ssm2602_priv *ssm2602 = codec->private_data; 376 struct ssm2602_priv *ssm2602 = codec->private_data;
377
378 if (ssm2602->master_substream == substream)
379 ssm2602->master_substream = ssm2602->slave_substream;
380
381 ssm2602->slave_substream = NULL;
375 /* deactivate */ 382 /* deactivate */
376 if (!codec->active) 383 if (!codec->active)
377 ssm2602_write(codec, SSM2602_ACTIVE, 0); 384 ssm2602_write(codec, SSM2602_ACTIVE, 0);
@@ -497,11 +504,9 @@ static int ssm2602_set_bias_level(struct snd_soc_codec *codec,
497 return 0; 504 return 0;
498} 505}
499 506
500#define SSM2602_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 507#define SSM2602_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_32000 |\
501 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\ 508 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
502 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\ 509 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
503 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |\
504 SNDRV_PCM_RATE_96000)
505 510
506#define SSM2602_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 511#define SSM2602_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
507 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 512 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
diff --git a/sound/soc/codecs/stac9766.c b/sound/soc/codecs/stac9766.c
new file mode 100644
index 000000000000..8ad4b7b3e3ba
--- /dev/null
+++ b/sound/soc/codecs/stac9766.c
@@ -0,0 +1,463 @@
1/*
2 * stac9766.c -- ALSA SoC STAC9766 codec support
3 *
4 * Copyright 2009 Jon Smirl, Digispeaker
5 * Author: Jon Smirl <jonsmirl@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * Features:-
13 *
14 * o Support for AC97 Codec, S/PDIF
15 */
16
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/device.h>
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/ac97_codec.h>
23#include <sound/initval.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/tlv.h>
27#include <sound/soc-of-simple.h>
28
29#include "stac9766.h"
30
31#define STAC9766_VERSION "0.10"
32
33/*
34 * STAC9766 register cache
35 */
36static const u16 stac9766_reg[] = {
37 0x6A90, 0x8000, 0x8000, 0x8000, /* 6 */
38 0x0000, 0x0000, 0x8008, 0x8008, /* e */
39 0x8808, 0x8808, 0x8808, 0x8808, /* 16 */
40 0x8808, 0x0000, 0x8000, 0x0000, /* 1e */
41 0x0000, 0x0000, 0x0000, 0x000f, /* 26 */
42 0x0a05, 0x0400, 0xbb80, 0x0000, /* 2e */
43 0x0000, 0xbb80, 0x0000, 0x0000, /* 36 */
44 0x0000, 0x2000, 0x0000, 0x0100, /* 3e */
45 0x0000, 0x0000, 0x0080, 0x0000, /* 46 */
46 0x0000, 0x0000, 0x0003, 0xffff, /* 4e */
47 0x0000, 0x0000, 0x0000, 0x0000, /* 56 */
48 0x4000, 0x0000, 0x0000, 0x0000, /* 5e */
49 0x1201, 0xFFFF, 0xFFFF, 0x0000, /* 66 */
50 0x0000, 0x0000, 0x0000, 0x0000, /* 6e */
51 0x0000, 0x0000, 0x0000, 0x0006, /* 76 */
52 0x0000, 0x0000, 0x0000, 0x0000, /* 7e */
53};
54
55static const char *stac9766_record_mux[] = {"Mic", "CD", "Video", "AUX",
56 "Line", "Stereo Mix", "Mono Mix", "Phone"};
57static const char *stac9766_mono_mux[] = {"Mix", "Mic"};
58static const char *stac9766_mic_mux[] = {"Mic1", "Mic2"};
59static const char *stac9766_SPDIF_mux[] = {"PCM", "ADC Record"};
60static const char *stac9766_popbypass_mux[] = {"Normal", "Bypass Mixer"};
61static const char *stac9766_record_all_mux[] = {"All analog",
62 "Analog plus DAC"};
63static const char *stac9766_boost1[] = {"0dB", "10dB"};
64static const char *stac9766_boost2[] = {"0dB", "20dB"};
65static const char *stac9766_stereo_mic[] = {"Off", "On"};
66
67static const struct soc_enum stac9766_record_enum =
68 SOC_ENUM_DOUBLE(AC97_REC_SEL, 8, 0, 8, stac9766_record_mux);
69static const struct soc_enum stac9766_mono_enum =
70 SOC_ENUM_SINGLE(AC97_GENERAL_PURPOSE, 9, 2, stac9766_mono_mux);
71static const struct soc_enum stac9766_mic_enum =
72 SOC_ENUM_SINGLE(AC97_GENERAL_PURPOSE, 8, 2, stac9766_mic_mux);
73static const struct soc_enum stac9766_SPDIF_enum =
74 SOC_ENUM_SINGLE(AC97_STAC_DA_CONTROL, 1, 2, stac9766_SPDIF_mux);
75static const struct soc_enum stac9766_popbypass_enum =
76 SOC_ENUM_SINGLE(AC97_GENERAL_PURPOSE, 15, 2, stac9766_popbypass_mux);
77static const struct soc_enum stac9766_record_all_enum =
78 SOC_ENUM_SINGLE(AC97_STAC_ANALOG_SPECIAL, 12, 2,
79 stac9766_record_all_mux);
80static const struct soc_enum stac9766_boost1_enum =
81 SOC_ENUM_SINGLE(AC97_MIC, 6, 2, stac9766_boost1); /* 0/10dB */
82static const struct soc_enum stac9766_boost2_enum =
83 SOC_ENUM_SINGLE(AC97_STAC_ANALOG_SPECIAL, 2, 2, stac9766_boost2); /* 0/20dB */
84static const struct soc_enum stac9766_stereo_mic_enum =
85 SOC_ENUM_SINGLE(AC97_STAC_STEREO_MIC, 2, 1, stac9766_stereo_mic);
86
87static const DECLARE_TLV_DB_LINEAR(master_tlv, -4600, 0);
88static const DECLARE_TLV_DB_LINEAR(record_tlv, 0, 2250);
89static const DECLARE_TLV_DB_LINEAR(beep_tlv, -4500, 0);
90static const DECLARE_TLV_DB_LINEAR(mix_tlv, -3450, 1200);
91
92static const struct snd_kcontrol_new stac9766_snd_ac97_controls[] = {
93 SOC_DOUBLE_TLV("Speaker Volume", AC97_MASTER, 8, 0, 31, 1, master_tlv),
94 SOC_SINGLE("Speaker Switch", AC97_MASTER, 15, 1, 1),
95 SOC_DOUBLE_TLV("Headphone Volume", AC97_HEADPHONE, 8, 0, 31, 1,
96 master_tlv),
97 SOC_SINGLE("Headphone Switch", AC97_HEADPHONE, 15, 1, 1),
98 SOC_SINGLE_TLV("Mono Out Volume", AC97_MASTER_MONO, 0, 31, 1,
99 master_tlv),
100 SOC_SINGLE("Mono Out Switch", AC97_MASTER_MONO, 15, 1, 1),
101
102 SOC_DOUBLE_TLV("Record Volume", AC97_REC_GAIN, 8, 0, 15, 0, record_tlv),
103 SOC_SINGLE("Record Switch", AC97_REC_GAIN, 15, 1, 1),
104
105
106 SOC_SINGLE_TLV("Beep Volume", AC97_PC_BEEP, 1, 15, 1, beep_tlv),
107 SOC_SINGLE("Beep Switch", AC97_PC_BEEP, 15, 1, 1),
108 SOC_SINGLE("Beep Frequency", AC97_PC_BEEP, 5, 127, 1),
109 SOC_SINGLE_TLV("Phone Volume", AC97_PHONE, 0, 31, 1, mix_tlv),
110 SOC_SINGLE("Phone Switch", AC97_PHONE, 15, 1, 1),
111
112 SOC_ENUM("Mic Boost1", stac9766_boost1_enum),
113 SOC_ENUM("Mic Boost2", stac9766_boost2_enum),
114 SOC_SINGLE_TLV("Mic Volume", AC97_MIC, 0, 31, 1, mix_tlv),
115 SOC_SINGLE("Mic Switch", AC97_MIC, 15, 1, 1),
116 SOC_ENUM("Stereo Mic", stac9766_stereo_mic_enum),
117
118 SOC_DOUBLE_TLV("Line Volume", AC97_LINE, 8, 0, 31, 1, mix_tlv),
119 SOC_SINGLE("Line Switch", AC97_LINE, 15, 1, 1),
120 SOC_DOUBLE_TLV("CD Volume", AC97_CD, 8, 0, 31, 1, mix_tlv),
121 SOC_SINGLE("CD Switch", AC97_CD, 15, 1, 1),
122 SOC_DOUBLE_TLV("AUX Volume", AC97_AUX, 8, 0, 31, 1, mix_tlv),
123 SOC_SINGLE("AUX Switch", AC97_AUX, 15, 1, 1),
124 SOC_DOUBLE_TLV("Video Volume", AC97_VIDEO, 8, 0, 31, 1, mix_tlv),
125 SOC_SINGLE("Video Switch", AC97_VIDEO, 15, 1, 1),
126
127 SOC_DOUBLE_TLV("DAC Volume", AC97_PCM, 8, 0, 31, 1, mix_tlv),
128 SOC_SINGLE("DAC Switch", AC97_PCM, 15, 1, 1),
129 SOC_SINGLE("Loopback Test Switch", AC97_GENERAL_PURPOSE, 7, 1, 0),
130 SOC_SINGLE("3D Volume", AC97_3D_CONTROL, 3, 2, 1),
131 SOC_SINGLE("3D Switch", AC97_GENERAL_PURPOSE, 13, 1, 0),
132
133 SOC_ENUM("SPDIF Mux", stac9766_SPDIF_enum),
134 SOC_ENUM("Mic1/2 Mux", stac9766_mic_enum),
135 SOC_ENUM("Record All Mux", stac9766_record_all_enum),
136 SOC_ENUM("Record Mux", stac9766_record_enum),
137 SOC_ENUM("Mono Mux", stac9766_mono_enum),
138 SOC_ENUM("Pop Bypass Mux", stac9766_popbypass_enum),
139};
140
141static int stac9766_ac97_write(struct snd_soc_codec *codec, unsigned int reg,
142 unsigned int val)
143{
144 u16 *cache = codec->reg_cache;
145
146 if (reg > AC97_STAC_PAGE0) {
147 stac9766_ac97_write(codec, AC97_INT_PAGING, 0);
148 soc_ac97_ops.write(codec->ac97, reg, val);
149 stac9766_ac97_write(codec, AC97_INT_PAGING, 1);
150 return 0;
151 }
152 if (reg / 2 > ARRAY_SIZE(stac9766_reg))
153 return -EIO;
154
155 soc_ac97_ops.write(codec->ac97, reg, val);
156 cache[reg / 2] = val;
157 return 0;
158}
159
160static unsigned int stac9766_ac97_read(struct snd_soc_codec *codec,
161 unsigned int reg)
162{
163 u16 val = 0, *cache = codec->reg_cache;
164
165 if (reg > AC97_STAC_PAGE0) {
166 stac9766_ac97_write(codec, AC97_INT_PAGING, 0);
167 val = soc_ac97_ops.read(codec->ac97, reg - AC97_STAC_PAGE0);
168 stac9766_ac97_write(codec, AC97_INT_PAGING, 1);
169 return val;
170 }
171 if (reg / 2 > ARRAY_SIZE(stac9766_reg))
172 return -EIO;
173
174 if (reg == AC97_RESET || reg == AC97_GPIO_STATUS ||
175 reg == AC97_INT_PAGING || reg == AC97_VENDOR_ID1 ||
176 reg == AC97_VENDOR_ID2) {
177
178 val = soc_ac97_ops.read(codec->ac97, reg);
179 return val;
180 }
181 return cache[reg / 2];
182}
183
184static int ac97_analog_prepare(struct snd_pcm_substream *substream,
185 struct snd_soc_dai *dai)
186{
187 struct snd_soc_codec *codec = dai->codec;
188 struct snd_pcm_runtime *runtime = substream->runtime;
189 unsigned short reg, vra;
190
191 vra = stac9766_ac97_read(codec, AC97_EXTENDED_STATUS);
192
193 vra |= 0x1; /* enable variable rate audio */
194
195 stac9766_ac97_write(codec, AC97_EXTENDED_STATUS, vra);
196
197 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
198 reg = AC97_PCM_FRONT_DAC_RATE;
199 else
200 reg = AC97_PCM_LR_ADC_RATE;
201
202 return stac9766_ac97_write(codec, reg, runtime->rate);
203}
204
205static int ac97_digital_prepare(struct snd_pcm_substream *substream,
206 struct snd_soc_dai *dai)
207{
208 struct snd_soc_codec *codec = dai->codec;
209 struct snd_pcm_runtime *runtime = substream->runtime;
210 unsigned short reg, vra;
211
212 stac9766_ac97_write(codec, AC97_SPDIF, 0x2002);
213
214 vra = stac9766_ac97_read(codec, AC97_EXTENDED_STATUS);
215 vra |= 0x5; /* Enable VRA and SPDIF out */
216
217 stac9766_ac97_write(codec, AC97_EXTENDED_STATUS, vra);
218
219 reg = AC97_PCM_FRONT_DAC_RATE;
220
221 return stac9766_ac97_write(codec, reg, runtime->rate);
222}
223
224static int ac97_digital_trigger(struct snd_pcm_substream *substream,
225 int cmd, struct snd_soc_dai *dai)
226{
227 struct snd_soc_codec *codec = dai->codec;
228 unsigned short vra;
229
230 switch (cmd) {
231 case SNDRV_PCM_TRIGGER_STOP:
232 vra = stac9766_ac97_read(codec, AC97_EXTENDED_STATUS);
233 vra &= !0x04;
234 stac9766_ac97_write(codec, AC97_EXTENDED_STATUS, vra);
235 break;
236 }
237 return 0;
238}
239
240static int stac9766_set_bias_level(struct snd_soc_codec *codec,
241 enum snd_soc_bias_level level)
242{
243 switch (level) {
244 case SND_SOC_BIAS_ON: /* full On */
245 case SND_SOC_BIAS_PREPARE: /* partial On */
246 case SND_SOC_BIAS_STANDBY: /* Off, with power */
247 stac9766_ac97_write(codec, AC97_POWERDOWN, 0x0000);
248 break;
249 case SND_SOC_BIAS_OFF: /* Off, without power */
250 /* disable everything including AC link */
251 stac9766_ac97_write(codec, AC97_POWERDOWN, 0xffff);
252 break;
253 }
254 codec->bias_level = level;
255 return 0;
256}
257
258static int stac9766_reset(struct snd_soc_codec *codec, int try_warm)
259{
260 if (try_warm && soc_ac97_ops.warm_reset) {
261 soc_ac97_ops.warm_reset(codec->ac97);
262 if (stac9766_ac97_read(codec, 0) == stac9766_reg[0])
263 return 1;
264 }
265
266 soc_ac97_ops.reset(codec->ac97);
267 if (soc_ac97_ops.warm_reset)
268 soc_ac97_ops.warm_reset(codec->ac97);
269 if (stac9766_ac97_read(codec, 0) != stac9766_reg[0])
270 return -EIO;
271 return 0;
272}
273
274static int stac9766_codec_suspend(struct platform_device *pdev,
275 pm_message_t state)
276{
277 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
278 struct snd_soc_codec *codec = socdev->card->codec;
279
280 stac9766_set_bias_level(codec, SND_SOC_BIAS_OFF);
281 return 0;
282}
283
284static int stac9766_codec_resume(struct platform_device *pdev)
285{
286 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
287 struct snd_soc_codec *codec = socdev->card->codec;
288 u16 id, reset;
289
290 reset = 0;
291 /* give the codec an AC97 warm reset to start the link */
292reset:
293 if (reset > 5) {
294 printk(KERN_ERR "stac9766 failed to resume");
295 return -EIO;
296 }
297 codec->ac97->bus->ops->warm_reset(codec->ac97);
298 id = soc_ac97_ops.read(codec->ac97, AC97_VENDOR_ID2);
299 if (id != 0x4c13) {
300 stac9766_reset(codec, 0);
301 reset++;
302 goto reset;
303 }
304 stac9766_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
305
306 if (codec->suspend_bias_level == SND_SOC_BIAS_ON)
307 stac9766_set_bias_level(codec, SND_SOC_BIAS_ON);
308
309 return 0;
310}
311
312static struct snd_soc_dai_ops stac9766_dai_ops_analog = {
313 .prepare = ac97_analog_prepare,
314};
315
316static struct snd_soc_dai_ops stac9766_dai_ops_digital = {
317 .prepare = ac97_digital_prepare,
318 .trigger = ac97_digital_trigger,
319};
320
321struct snd_soc_dai stac9766_dai[] = {
322{
323 .name = "stac9766 analog",
324 .id = 0,
325 .ac97_control = 1,
326
327 /* stream cababilities */
328 .playback = {
329 .stream_name = "stac9766 analog",
330 .channels_min = 1,
331 .channels_max = 2,
332 .rates = SNDRV_PCM_RATE_8000_48000,
333 .formats = SND_SOC_STD_AC97_FMTS,
334 },
335 .capture = {
336 .stream_name = "stac9766 analog",
337 .channels_min = 1,
338 .channels_max = 2,
339 .rates = SNDRV_PCM_RATE_8000_48000,
340 .formats = SND_SOC_STD_AC97_FMTS,
341 },
342 /* alsa ops */
343 .ops = &stac9766_dai_ops_analog,
344},
345{
346 .name = "stac9766 IEC958",
347 .id = 1,
348 .ac97_control = 1,
349
350 /* stream cababilities */
351 .playback = {
352 .stream_name = "stac9766 IEC958",
353 .channels_min = 1,
354 .channels_max = 2,
355 .rates = SNDRV_PCM_RATE_32000 | \
356 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
357 .formats = SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE,
358 },
359 /* alsa ops */
360 .ops = &stac9766_dai_ops_digital,
361}
362};
363EXPORT_SYMBOL_GPL(stac9766_dai);
364
365static int stac9766_codec_probe(struct platform_device *pdev)
366{
367 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
368 struct snd_soc_codec *codec;
369 int ret = 0;
370
371 printk(KERN_INFO "STAC9766 SoC Audio Codec %s\n", STAC9766_VERSION);
372
373 socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
374 if (socdev->card->codec == NULL)
375 return -ENOMEM;
376 codec = socdev->card->codec;
377 mutex_init(&codec->mutex);
378
379 codec->reg_cache = kmemdup(stac9766_reg, sizeof(stac9766_reg),
380 GFP_KERNEL);
381 if (codec->reg_cache == NULL) {
382 ret = -ENOMEM;
383 goto cache_err;
384 }
385 codec->reg_cache_size = sizeof(stac9766_reg);
386 codec->reg_cache_step = 2;
387
388 codec->name = "STAC9766";
389 codec->owner = THIS_MODULE;
390 codec->dai = stac9766_dai;
391 codec->num_dai = ARRAY_SIZE(stac9766_dai);
392 codec->write = stac9766_ac97_write;
393 codec->read = stac9766_ac97_read;
394 codec->set_bias_level = stac9766_set_bias_level;
395 INIT_LIST_HEAD(&codec->dapm_widgets);
396 INIT_LIST_HEAD(&codec->dapm_paths);
397
398 ret = snd_soc_new_ac97_codec(codec, &soc_ac97_ops, 0);
399 if (ret < 0)
400 goto codec_err;
401
402 /* register pcms */
403 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
404 if (ret < 0)
405 goto pcm_err;
406
407 /* do a cold reset for the controller and then try
408 * a warm reset followed by an optional cold reset for codec */
409 stac9766_reset(codec, 0);
410 ret = stac9766_reset(codec, 1);
411 if (ret < 0) {
412 printk(KERN_ERR "Failed to reset STAC9766: AC97 link error\n");
413 goto reset_err;
414 }
415
416 stac9766_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
417
418 snd_soc_add_controls(codec, stac9766_snd_ac97_controls,
419 ARRAY_SIZE(stac9766_snd_ac97_controls));
420
421 ret = snd_soc_init_card(socdev);
422 if (ret < 0)
423 goto reset_err;
424 return 0;
425
426reset_err:
427 snd_soc_free_pcms(socdev);
428pcm_err:
429 snd_soc_free_ac97_codec(codec);
430codec_err:
431 kfree(codec->private_data);
432cache_err:
433 kfree(socdev->card->codec);
434 socdev->card->codec = NULL;
435 return ret;
436}
437
438static int stac9766_codec_remove(struct platform_device *pdev)
439{
440 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
441 struct snd_soc_codec *codec = socdev->card->codec;
442
443 if (codec == NULL)
444 return 0;
445
446 snd_soc_free_pcms(socdev);
447 snd_soc_free_ac97_codec(codec);
448 kfree(codec->reg_cache);
449 kfree(codec);
450 return 0;
451}
452
453struct snd_soc_codec_device soc_codec_dev_stac9766 = {
454 .probe = stac9766_codec_probe,
455 .remove = stac9766_codec_remove,
456 .suspend = stac9766_codec_suspend,
457 .resume = stac9766_codec_resume,
458};
459EXPORT_SYMBOL_GPL(soc_codec_dev_stac9766);
460
461MODULE_DESCRIPTION("ASoC stac9766 driver");
462MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
463MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/stac9766.h b/sound/soc/codecs/stac9766.h
new file mode 100644
index 000000000000..65642eb8393e
--- /dev/null
+++ b/sound/soc/codecs/stac9766.h
@@ -0,0 +1,21 @@
1/*
2 * stac9766.h -- STAC9766 Soc Audio driver
3 */
4
5#ifndef _STAC9766_H
6#define _STAC9766_H
7
8#define AC97_STAC_PAGE0 0x1000
9#define AC97_STAC_DA_CONTROL (AC97_STAC_PAGE0 | 0x6A)
10#define AC97_STAC_ANALOG_SPECIAL (AC97_STAC_PAGE0 | 0x6E)
11#define AC97_STAC_STEREO_MIC 0x78
12
13/* STAC9766 DAI ID's */
14#define STAC9766_DAI_AC97_ANALOG 0
15#define STAC9766_DAI_AC97_DIGITAL 1
16
17extern struct snd_soc_dai stac9766_dai[];
18extern struct snd_soc_codec_device soc_codec_dev_stac9766;
19
20
21#endif
diff --git a/sound/soc/codecs/tlv320aic23.c b/sound/soc/codecs/tlv320aic23.c
index c3f4afb5d017..0b8dcb5cd729 100644
--- a/sound/soc/codecs/tlv320aic23.c
+++ b/sound/soc/codecs/tlv320aic23.c
@@ -86,7 +86,7 @@ static int tlv320aic23_write(struct snd_soc_codec *codec, unsigned int reg,
86 */ 86 */
87 87
88 if ((reg < 0 || reg > 9) && (reg != 15)) { 88 if ((reg < 0 || reg > 9) && (reg != 15)) {
89 printk(KERN_WARNING "%s Invalid register R%d\n", __func__, reg); 89 printk(KERN_WARNING "%s Invalid register R%u\n", __func__, reg);
90 return -1; 90 return -1;
91 } 91 }
92 92
@@ -98,7 +98,7 @@ static int tlv320aic23_write(struct snd_soc_codec *codec, unsigned int reg,
98 if (codec->hw_write(codec->control_data, data, 2) == 2) 98 if (codec->hw_write(codec->control_data, data, 2) == 2)
99 return 0; 99 return 0;
100 100
101 printk(KERN_ERR "%s cannot write %03x to register R%d\n", __func__, 101 printk(KERN_ERR "%s cannot write %03x to register R%u\n", __func__,
102 value, reg); 102 value, reg);
103 103
104 return -EIO; 104 return -EIO;
@@ -273,14 +273,14 @@ static const unsigned short sr_valid_mask[] = {
273 * Every divisor is a factor of 11*12 273 * Every divisor is a factor of 11*12
274 */ 274 */
275#define SR_MULT (11*12) 275#define SR_MULT (11*12)
276#define A(x) (x) ? (SR_MULT/x) : 0 276#define A(x) (SR_MULT/x)
277static const unsigned char sr_adc_mult_table[] = { 277static const unsigned char sr_adc_mult_table[] = {
278 A(2), A(2), A(12), A(12), A(0), A(0), A(3), A(1), 278 A(2), A(2), A(12), A(12), 0, 0, A(3), A(1),
279 A(2), A(2), A(11), A(11), A(0), A(0), A(0), A(1) 279 A(2), A(2), A(11), A(11), 0, 0, 0, A(1)
280}; 280};
281static const unsigned char sr_dac_mult_table[] = { 281static const unsigned char sr_dac_mult_table[] = {
282 A(2), A(12), A(2), A(12), A(0), A(0), A(3), A(1), 282 A(2), A(12), A(2), A(12), 0, 0, A(3), A(1),
283 A(2), A(11), A(2), A(11), A(0), A(0), A(0), A(1) 283 A(2), A(11), A(2), A(11), 0, 0, 0, A(1)
284}; 284};
285 285
286static unsigned get_score(int adc, int adc_l, int adc_h, int need_adc, 286static unsigned get_score(int adc, int adc_l, int adc_h, int need_adc,
@@ -523,6 +523,8 @@ static int tlv320aic23_set_dai_fmt(struct snd_soc_dai *codec_dai,
523 case SND_SOC_DAIFMT_I2S: 523 case SND_SOC_DAIFMT_I2S:
524 iface_reg |= TLV320AIC23_FOR_I2S; 524 iface_reg |= TLV320AIC23_FOR_I2S;
525 break; 525 break;
526 case SND_SOC_DAIFMT_DSP_A:
527 iface_reg |= TLV320AIC23_LRP_ON;
526 case SND_SOC_DAIFMT_DSP_B: 528 case SND_SOC_DAIFMT_DSP_B:
527 iface_reg |= TLV320AIC23_FOR_DSP; 529 iface_reg |= TLV320AIC23_FOR_DSP;
528 break; 530 break;
diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index df7c8c281d2f..4dbb853eef5a 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -115,6 +115,7 @@ static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */ 115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */ 116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */ 117 0x00, /* REG_MISC_SET_2 (0x49) */
118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
118}; 119};
119 120
120/* codec private data */ 121/* codec private data */
@@ -125,6 +126,17 @@ struct twl4030_priv {
125 126
126 struct snd_pcm_substream *master_substream; 127 struct snd_pcm_substream *master_substream;
127 struct snd_pcm_substream *slave_substream; 128 struct snd_pcm_substream *slave_substream;
129
130 unsigned int configured;
131 unsigned int rate;
132 unsigned int sample_bits;
133 unsigned int channels;
134
135 unsigned int sysclk;
136
137 /* Headset output state handling */
138 unsigned int hsl_enabled;
139 unsigned int hsr_enabled;
128}; 140};
129 141
130/* 142/*
@@ -161,7 +173,11 @@ static int twl4030_write(struct snd_soc_codec *codec,
161 unsigned int reg, unsigned int value) 173 unsigned int reg, unsigned int value)
162{ 174{
163 twl4030_write_reg_cache(codec, reg, value); 175 twl4030_write_reg_cache(codec, reg, value);
164 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); 176 if (likely(reg < TWL4030_REG_SW_SHADOW))
177 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
178 reg);
179 else
180 return 0;
165} 181}
166 182
167static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable) 183static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
@@ -188,6 +204,7 @@ static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
188 204
189static void twl4030_init_chip(struct snd_soc_codec *codec) 205static void twl4030_init_chip(struct snd_soc_codec *codec)
190{ 206{
207 u8 *cache = codec->reg_cache;
191 int i; 208 int i;
192 209
193 /* clear CODECPDZ prior to setting register defaults */ 210 /* clear CODECPDZ prior to setting register defaults */
@@ -195,7 +212,7 @@ static void twl4030_init_chip(struct snd_soc_codec *codec)
195 212
196 /* set all audio section registers to reasonable defaults */ 213 /* set all audio section registers to reasonable defaults */
197 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++) 214 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
198 twl4030_write(codec, i, twl4030_reg[i]); 215 twl4030_write(codec, i, cache[i]);
199 216
200} 217}
201 218
@@ -232,7 +249,7 @@ static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
232 TWL4030_REG_PRECKL_CTL); 249 TWL4030_REG_PRECKL_CTL);
233 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL); 250 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
234 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 251 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
235 reg_val & (~TWL4030_PRECKL_GAIN), 252 reg_val & (~TWL4030_PRECKR_GAIN),
236 TWL4030_REG_PRECKR_CTL); 253 TWL4030_REG_PRECKR_CTL);
237 254
238 /* Disable PLL */ 255 /* Disable PLL */
@@ -316,104 +333,60 @@ static void twl4030_power_down(struct snd_soc_codec *codec)
316} 333}
317 334
318/* Earpiece */ 335/* Earpiece */
319static const char *twl4030_earpiece_texts[] = 336static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
320 {"Off", "DACL1", "DACL2", "DACR1"}; 337 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
321 338 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
322static const unsigned int twl4030_earpiece_values[] = 339 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
323 {0x0, 0x1, 0x2, 0x4}; 340 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
324 341};
325static const struct soc_enum twl4030_earpiece_enum =
326 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7,
327 ARRAY_SIZE(twl4030_earpiece_texts),
328 twl4030_earpiece_texts,
329 twl4030_earpiece_values);
330
331static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
332SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum);
333 342
334/* PreDrive Left */ 343/* PreDrive Left */
335static const char *twl4030_predrivel_texts[] = 344static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
336 {"Off", "DACL1", "DACL2", "DACR2"}; 345 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
337 346 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
338static const unsigned int twl4030_predrivel_values[] = 347 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
339 {0x0, 0x1, 0x2, 0x4}; 348 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
340 349};
341static const struct soc_enum twl4030_predrivel_enum =
342 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7,
343 ARRAY_SIZE(twl4030_predrivel_texts),
344 twl4030_predrivel_texts,
345 twl4030_predrivel_values);
346
347static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
348SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum);
349 350
350/* PreDrive Right */ 351/* PreDrive Right */
351static const char *twl4030_predriver_texts[] = 352static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
352 {"Off", "DACR1", "DACR2", "DACL2"}; 353 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
353 354 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
354static const unsigned int twl4030_predriver_values[] = 355 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
355 {0x0, 0x1, 0x2, 0x4}; 356 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
356 357};
357static const struct soc_enum twl4030_predriver_enum =
358 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7,
359 ARRAY_SIZE(twl4030_predriver_texts),
360 twl4030_predriver_texts,
361 twl4030_predriver_values);
362
363static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
364SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum);
365 358
366/* Headset Left */ 359/* Headset Left */
367static const char *twl4030_hsol_texts[] = 360static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
368 {"Off", "DACL1", "DACL2"}; 361 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
369 362 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
370static const struct soc_enum twl4030_hsol_enum = 363 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
371 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1, 364};
372 ARRAY_SIZE(twl4030_hsol_texts),
373 twl4030_hsol_texts);
374
375static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
376SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
377 365
378/* Headset Right */ 366/* Headset Right */
379static const char *twl4030_hsor_texts[] = 367static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
380 {"Off", "DACR1", "DACR2"}; 368 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
381 369 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
382static const struct soc_enum twl4030_hsor_enum = 370 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
383 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4, 371};
384 ARRAY_SIZE(twl4030_hsor_texts),
385 twl4030_hsor_texts);
386
387static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
388SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
389 372
390/* Carkit Left */ 373/* Carkit Left */
391static const char *twl4030_carkitl_texts[] = 374static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
392 {"Off", "DACL1", "DACL2"}; 375 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
393 376 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
394static const struct soc_enum twl4030_carkitl_enum = 377 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
395 SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1, 378};
396 ARRAY_SIZE(twl4030_carkitl_texts),
397 twl4030_carkitl_texts);
398
399static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
400SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
401 379
402/* Carkit Right */ 380/* Carkit Right */
403static const char *twl4030_carkitr_texts[] = 381static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
404 {"Off", "DACR1", "DACR2"}; 382 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
405 383 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
406static const struct soc_enum twl4030_carkitr_enum = 384 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
407 SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1, 385};
408 ARRAY_SIZE(twl4030_carkitr_texts),
409 twl4030_carkitr_texts);
410
411static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
412SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
413 386
414/* Handsfree Left */ 387/* Handsfree Left */
415static const char *twl4030_handsfreel_texts[] = 388static const char *twl4030_handsfreel_texts[] =
416 {"Voice", "DACL1", "DACL2", "DACR2"}; 389 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
417 390
418static const struct soc_enum twl4030_handsfreel_enum = 391static const struct soc_enum twl4030_handsfreel_enum =
419 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0, 392 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
@@ -423,9 +396,13 @@ static const struct soc_enum twl4030_handsfreel_enum =
423static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control = 396static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
424SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum); 397SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
425 398
399/* Handsfree Left virtual mute */
400static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
401 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
402
426/* Handsfree Right */ 403/* Handsfree Right */
427static const char *twl4030_handsfreer_texts[] = 404static const char *twl4030_handsfreer_texts[] =
428 {"Voice", "DACR1", "DACR2", "DACL2"}; 405 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
429 406
430static const struct soc_enum twl4030_handsfreer_enum = 407static const struct soc_enum twl4030_handsfreer_enum =
431 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0, 408 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
@@ -435,37 +412,48 @@ static const struct soc_enum twl4030_handsfreer_enum =
435static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control = 412static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
436SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum); 413SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
437 414
438/* Left analog microphone selection */ 415/* Handsfree Right virtual mute */
439static const char *twl4030_analoglmic_texts[] = 416static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
440 {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"}; 417 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
441 418
442static const unsigned int twl4030_analoglmic_values[] = 419/* Vibra */
443 {0x0, 0x1, 0x2, 0x4, 0x8}; 420/* Vibra audio path selection */
421static const char *twl4030_vibra_texts[] =
422 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
444 423
445static const struct soc_enum twl4030_analoglmic_enum = 424static const struct soc_enum twl4030_vibra_enum =
446 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf, 425 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
447 ARRAY_SIZE(twl4030_analoglmic_texts), 426 ARRAY_SIZE(twl4030_vibra_texts),
448 twl4030_analoglmic_texts, 427 twl4030_vibra_texts);
449 twl4030_analoglmic_values);
450 428
451static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control = 429static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
452SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum); 430SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
453 431
454/* Right analog microphone selection */ 432/* Vibra path selection: local vibrator (PWM) or audio driven */
455static const char *twl4030_analogrmic_texts[] = 433static const char *twl4030_vibrapath_texts[] =
456 {"Off", "Sub mic", "AUXR"}; 434 {"Local vibrator", "Audio"};
457 435
458static const unsigned int twl4030_analogrmic_values[] = 436static const struct soc_enum twl4030_vibrapath_enum =
459 {0x0, 0x1, 0x4}; 437 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
438 ARRAY_SIZE(twl4030_vibrapath_texts),
439 twl4030_vibrapath_texts);
460 440
461static const struct soc_enum twl4030_analogrmic_enum = 441static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
462 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5, 442SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
463 ARRAY_SIZE(twl4030_analogrmic_texts),
464 twl4030_analogrmic_texts,
465 twl4030_analogrmic_values);
466 443
467static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control = 444/* Left analog microphone selection */
468SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum); 445static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
446 SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
447 SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
448 SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
449 SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
450};
451
452/* Right analog microphone selection */
453static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
454 SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
455 SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
456};
469 457
470/* TX1 L/R Analog/Digital microphone selection */ 458/* TX1 L/R Analog/Digital microphone selection */
471static const char *twl4030_micpathtx1_texts[] = 459static const char *twl4030_micpathtx1_texts[] =
@@ -507,6 +495,10 @@ static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
507static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control = 495static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
508 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0); 496 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
509 497
498/* Analog bypass for Voice */
499static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
500 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
501
510/* Digital bypass gain, 0 mutes the bypass */ 502/* Digital bypass gain, 0 mutes the bypass */
511static const unsigned int twl4030_dapm_dbypass_tlv[] = { 503static const unsigned int twl4030_dapm_dbypass_tlv[] = {
512 TLV_DB_RANGE_HEAD(2), 504 TLV_DB_RANGE_HEAD(2),
@@ -526,6 +518,18 @@ static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
526 TWL4030_REG_ATX2ARXPGA, 0, 7, 0, 518 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
527 twl4030_dapm_dbypass_tlv); 519 twl4030_dapm_dbypass_tlv);
528 520
521/*
522 * Voice Sidetone GAIN volume control:
523 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
524 */
525static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
526
527/* Digital bypass voice: sidetone (VUL -> VDL)*/
528static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
529 SOC_DAPM_SINGLE_TLV("Volume",
530 TWL4030_REG_VSTPGA, 0, 0x29, 0,
531 twl4030_dapm_dbypassv_tlv);
532
529static int micpath_event(struct snd_soc_dapm_widget *w, 533static int micpath_event(struct snd_soc_dapm_widget *w,
530 struct snd_kcontrol *kcontrol, int event) 534 struct snd_kcontrol *kcontrol, int event)
531{ 535{
@@ -556,63 +560,143 @@ static int micpath_event(struct snd_soc_dapm_widget *w,
556 return 0; 560 return 0;
557} 561}
558 562
559static int handsfree_event(struct snd_soc_dapm_widget *w, 563static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
560 struct snd_kcontrol *kcontrol, int event)
561{ 564{
562 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
563 unsigned char hs_ctl; 565 unsigned char hs_ctl;
564 566
565 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg); 567 hs_ctl = twl4030_read_reg_cache(codec, reg);
566 568
567 if (hs_ctl & TWL4030_HF_CTL_REF_EN) { 569 if (ramp) {
570 /* HF ramp-up */
571 hs_ctl |= TWL4030_HF_CTL_REF_EN;
572 twl4030_write(codec, reg, hs_ctl);
573 udelay(10);
568 hs_ctl |= TWL4030_HF_CTL_RAMP_EN; 574 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
569 twl4030_write(w->codec, e->reg, hs_ctl); 575 twl4030_write(codec, reg, hs_ctl);
576 udelay(40);
570 hs_ctl |= TWL4030_HF_CTL_LOOP_EN; 577 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
571 twl4030_write(w->codec, e->reg, hs_ctl);
572 hs_ctl |= TWL4030_HF_CTL_HB_EN; 578 hs_ctl |= TWL4030_HF_CTL_HB_EN;
573 twl4030_write(w->codec, e->reg, hs_ctl); 579 twl4030_write(codec, reg, hs_ctl);
574 } else { 580 } else {
575 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN 581 /* HF ramp-down */
576 | TWL4030_HF_CTL_HB_EN); 582 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
577 twl4030_write(w->codec, e->reg, hs_ctl); 583 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
584 twl4030_write(codec, reg, hs_ctl);
585 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
586 twl4030_write(codec, reg, hs_ctl);
587 udelay(40);
588 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
589 twl4030_write(codec, reg, hs_ctl);
578 } 590 }
591}
579 592
593static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
594 struct snd_kcontrol *kcontrol, int event)
595{
596 switch (event) {
597 case SND_SOC_DAPM_POST_PMU:
598 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
599 break;
600 case SND_SOC_DAPM_POST_PMD:
601 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
602 break;
603 }
580 return 0; 604 return 0;
581} 605}
582 606
583static int headsetl_event(struct snd_soc_dapm_widget *w, 607static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
584 struct snd_kcontrol *kcontrol, int event) 608 struct snd_kcontrol *kcontrol, int event)
585{ 609{
610 switch (event) {
611 case SND_SOC_DAPM_POST_PMU:
612 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
613 break;
614 case SND_SOC_DAPM_POST_PMD:
615 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
616 break;
617 }
618 return 0;
619}
620
621static void headset_ramp(struct snd_soc_codec *codec, int ramp)
622{
586 unsigned char hs_gain, hs_pop; 623 unsigned char hs_gain, hs_pop;
624 struct twl4030_priv *twl4030 = codec->private_data;
625 /* Base values for ramp delay calculation: 2^19 - 2^26 */
626 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
627 8388608, 16777216, 33554432, 67108864};
587 628
588 /* Save the current volume */ 629 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
589 hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET); 630 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
590 hs_pop = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_POPN_SET);
591 631
592 switch (event) { 632 if (ramp) {
593 case SND_SOC_DAPM_POST_PMU: 633 /* Headset ramp-up according to the TRM */
594 /* Do the anti-pop/bias ramp enable according to the TRM */
595 hs_pop |= TWL4030_VMID_EN; 634 hs_pop |= TWL4030_VMID_EN;
596 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop); 635 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
597 /* Is this needed? Can we just use whatever gain here? */ 636 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
598 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
599 (hs_gain & (~0x0f)) | 0x0a);
600 hs_pop |= TWL4030_RAMP_EN; 637 hs_pop |= TWL4030_RAMP_EN;
601 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop); 638 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
602 639 } else {
603 /* Restore the original volume */ 640 /* Headset ramp-down _not_ according to
604 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain); 641 * the TRM, but in a way that it is working */
605 break;
606 case SND_SOC_DAPM_POST_PMD:
607 /* Do the anti-pop/bias ramp disable according to the TRM */
608 hs_pop &= ~TWL4030_RAMP_EN; 642 hs_pop &= ~TWL4030_RAMP_EN;
609 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop); 643 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
644 /* Wait ramp delay time + 1, so the VMID can settle */
645 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
646 twl4030->sysclk) + 1);
610 /* Bypass the reg_cache to mute the headset */ 647 /* Bypass the reg_cache to mute the headset */
611 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 648 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
612 hs_gain & (~0x0f), 649 hs_gain & (~0x0f),
613 TWL4030_REG_HS_GAIN_SET); 650 TWL4030_REG_HS_GAIN_SET);
651
614 hs_pop &= ~TWL4030_VMID_EN; 652 hs_pop &= ~TWL4030_VMID_EN;
615 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop); 653 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
654 }
655}
656
657static int headsetlpga_event(struct snd_soc_dapm_widget *w,
658 struct snd_kcontrol *kcontrol, int event)
659{
660 struct twl4030_priv *twl4030 = w->codec->private_data;
661
662 switch (event) {
663 case SND_SOC_DAPM_POST_PMU:
664 /* Do the ramp-up only once */
665 if (!twl4030->hsr_enabled)
666 headset_ramp(w->codec, 1);
667
668 twl4030->hsl_enabled = 1;
669 break;
670 case SND_SOC_DAPM_POST_PMD:
671 /* Do the ramp-down only if both headsetL/R is disabled */
672 if (!twl4030->hsr_enabled)
673 headset_ramp(w->codec, 0);
674
675 twl4030->hsl_enabled = 0;
676 break;
677 }
678 return 0;
679}
680
681static int headsetrpga_event(struct snd_soc_dapm_widget *w,
682 struct snd_kcontrol *kcontrol, int event)
683{
684 struct twl4030_priv *twl4030 = w->codec->private_data;
685
686 switch (event) {
687 case SND_SOC_DAPM_POST_PMU:
688 /* Do the ramp-up only once */
689 if (!twl4030->hsl_enabled)
690 headset_ramp(w->codec, 1);
691
692 twl4030->hsr_enabled = 1;
693 break;
694 case SND_SOC_DAPM_POST_PMD:
695 /* Do the ramp-down only if both headsetL/R is disabled */
696 if (!twl4030->hsl_enabled)
697 headset_ramp(w->codec, 0);
698
699 twl4030->hsr_enabled = 0;
616 break; 700 break;
617 } 701 }
618 return 0; 702 return 0;
@@ -624,7 +708,7 @@ static int bypass_event(struct snd_soc_dapm_widget *w,
624 struct soc_mixer_control *m = 708 struct soc_mixer_control *m =
625 (struct soc_mixer_control *)w->kcontrols->private_value; 709 (struct soc_mixer_control *)w->kcontrols->private_value;
626 struct twl4030_priv *twl4030 = w->codec->private_data; 710 struct twl4030_priv *twl4030 = w->codec->private_data;
627 unsigned char reg; 711 unsigned char reg, misc;
628 712
629 reg = twl4030_read_reg_cache(w->codec, m->reg); 713 reg = twl4030_read_reg_cache(w->codec, m->reg);
630 714
@@ -636,14 +720,34 @@ static int bypass_event(struct snd_soc_dapm_widget *w,
636 else 720 else
637 twl4030->bypass_state &= 721 twl4030->bypass_state &=
638 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL)); 722 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
723 } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
724 /* Analog voice bypass */
725 if (reg & (1 << m->shift))
726 twl4030->bypass_state |= (1 << 4);
727 else
728 twl4030->bypass_state &= ~(1 << 4);
729 } else if (m->reg == TWL4030_REG_VSTPGA) {
730 /* Voice digital bypass */
731 if (reg)
732 twl4030->bypass_state |= (1 << 5);
733 else
734 twl4030->bypass_state &= ~(1 << 5);
639 } else { 735 } else {
640 /* Digital bypass */ 736 /* Digital bypass */
641 if (reg & (0x7 << m->shift)) 737 if (reg & (0x7 << m->shift))
642 twl4030->bypass_state |= (1 << (m->shift ? 5 : 4)); 738 twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
643 else 739 else
644 twl4030->bypass_state &= ~(1 << (m->shift ? 5 : 4)); 740 twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
645 } 741 }
646 742
743 /* Enable master analog loopback mode if any analog switch is enabled*/
744 misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
745 if (twl4030->bypass_state & 0x1F)
746 misc |= TWL4030_FMLOOP_EN;
747 else
748 misc &= ~TWL4030_FMLOOP_EN;
749 twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
750
647 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) { 751 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
648 if (twl4030->bypass_state) 752 if (twl4030->bypass_state)
649 twl4030_codec_mute(w->codec, 0); 753 twl4030_codec_mute(w->codec, 0);
@@ -810,6 +914,48 @@ static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
810 return err; 914 return err;
811} 915}
812 916
917/* Codec operation modes */
918static const char *twl4030_op_modes_texts[] = {
919 "Option 2 (voice/audio)", "Option 1 (audio)"
920};
921
922static const struct soc_enum twl4030_op_modes_enum =
923 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
924 ARRAY_SIZE(twl4030_op_modes_texts),
925 twl4030_op_modes_texts);
926
927int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
928 struct snd_ctl_elem_value *ucontrol)
929{
930 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
931 struct twl4030_priv *twl4030 = codec->private_data;
932 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
933 unsigned short val;
934 unsigned short mask, bitmask;
935
936 if (twl4030->configured) {
937 printk(KERN_ERR "twl4030 operation mode cannot be "
938 "changed on-the-fly\n");
939 return -EBUSY;
940 }
941
942 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
943 ;
944 if (ucontrol->value.enumerated.item[0] > e->max - 1)
945 return -EINVAL;
946
947 val = ucontrol->value.enumerated.item[0] << e->shift_l;
948 mask = (bitmask - 1) << e->shift_l;
949 if (e->shift_l != e->shift_r) {
950 if (ucontrol->value.enumerated.item[1] > e->max - 1)
951 return -EINVAL;
952 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
953 mask |= (bitmask - 1) << e->shift_r;
954 }
955
956 return snd_soc_update_bits(codec, e->reg, mask, val);
957}
958
813/* 959/*
814 * FGAIN volume control: 960 * FGAIN volume control:
815 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB) 961 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
@@ -824,6 +970,12 @@ static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
824static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0); 970static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
825 971
826/* 972/*
973 * Voice Downlink GAIN volume control:
974 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
975 */
976static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
977
978/*
827 * Analog playback gain 979 * Analog playback gain
828 * -24 dB to 12 dB in 2 dB steps 980 * -24 dB to 12 dB in 2 dB steps
829 */ 981 */
@@ -864,7 +1016,32 @@ static const struct soc_enum twl4030_rampdelay_enum =
864 ARRAY_SIZE(twl4030_rampdelay_texts), 1016 ARRAY_SIZE(twl4030_rampdelay_texts),
865 twl4030_rampdelay_texts); 1017 twl4030_rampdelay_texts);
866 1018
1019/* Vibra H-bridge direction mode */
1020static const char *twl4030_vibradirmode_texts[] = {
1021 "Vibra H-bridge direction", "Audio data MSB",
1022};
1023
1024static const struct soc_enum twl4030_vibradirmode_enum =
1025 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1026 ARRAY_SIZE(twl4030_vibradirmode_texts),
1027 twl4030_vibradirmode_texts);
1028
1029/* Vibra H-bridge direction */
1030static const char *twl4030_vibradir_texts[] = {
1031 "Positive polarity", "Negative polarity",
1032};
1033
1034static const struct soc_enum twl4030_vibradir_enum =
1035 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1036 ARRAY_SIZE(twl4030_vibradir_texts),
1037 twl4030_vibradir_texts);
1038
867static const struct snd_kcontrol_new twl4030_snd_controls[] = { 1039static const struct snd_kcontrol_new twl4030_snd_controls[] = {
1040 /* Codec operation mode control */
1041 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1042 snd_soc_get_enum_double,
1043 snd_soc_put_twl4030_opmode_enum_double),
1044
868 /* Common playback gain controls */ 1045 /* Common playback gain controls */
869 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume", 1046 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
870 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, 1047 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
@@ -893,6 +1070,16 @@ static const struct snd_kcontrol_new twl4030_snd_controls[] = {
893 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, 1070 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
894 1, 1, 0), 1071 1, 1, 0),
895 1072
1073 /* Common voice downlink gain controls */
1074 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1075 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1076
1077 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1078 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1079
1080 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1081 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1082
896 /* Separate output gain controls */ 1083 /* Separate output gain controls */
897 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume", 1084 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
898 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL, 1085 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
@@ -920,6 +1107,9 @@ static const struct snd_kcontrol_new twl4030_snd_controls[] = {
920 0, 3, 5, 0, input_gain_tlv), 1107 0, 3, 5, 0, input_gain_tlv),
921 1108
922 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum), 1109 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
1110
1111 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1112 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
923}; 1113};
924 1114
925static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { 1115static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
@@ -947,26 +1137,19 @@ static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
947 SND_SOC_DAPM_OUTPUT("CARKITR"), 1137 SND_SOC_DAPM_OUTPUT("CARKITR"),
948 SND_SOC_DAPM_OUTPUT("HFL"), 1138 SND_SOC_DAPM_OUTPUT("HFL"),
949 SND_SOC_DAPM_OUTPUT("HFR"), 1139 SND_SOC_DAPM_OUTPUT("HFR"),
1140 SND_SOC_DAPM_OUTPUT("VIBRA"),
950 1141
951 /* DACs */ 1142 /* DACs */
952 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback", 1143 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
953 SND_SOC_NOPM, 0, 0), 1144 SND_SOC_NOPM, 0, 0),
954 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback", 1145 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
955 SND_SOC_NOPM, 0, 0), 1146 SND_SOC_NOPM, 0, 0),
956 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback", 1147 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
957 SND_SOC_NOPM, 0, 0), 1148 SND_SOC_NOPM, 0, 0),
958 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback", 1149 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
1150 SND_SOC_NOPM, 0, 0),
1151 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
959 SND_SOC_NOPM, 0, 0), 1152 SND_SOC_NOPM, 0, 0),
960
961 /* Analog PGAs */
962 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
963 0, 0, NULL, 0),
964 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
965 0, 0, NULL, 0),
966 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
967 0, 0, NULL, 0),
968 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
969 0, 0, NULL, 0),
970 1153
971 /* Analog bypasses */ 1154 /* Analog bypasses */
972 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0, 1155 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
@@ -981,6 +1164,9 @@ static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
981 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0, 1164 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
982 &twl4030_dapm_abypassl2_control, 1165 &twl4030_dapm_abypassl2_control,
983 bypass_event, SND_SOC_DAPM_POST_REG), 1166 bypass_event, SND_SOC_DAPM_POST_REG),
1167 SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1168 &twl4030_dapm_abypassv_control,
1169 bypass_event, SND_SOC_DAPM_POST_REG),
984 1170
985 /* Digital bypasses */ 1171 /* Digital bypasses */
986 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0, 1172 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
@@ -989,43 +1175,88 @@ static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
989 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0, 1175 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
990 &twl4030_dapm_dbypassr_control, bypass_event, 1176 &twl4030_dapm_dbypassr_control, bypass_event,
991 SND_SOC_DAPM_POST_REG), 1177 SND_SOC_DAPM_POST_REG),
1178 SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1179 &twl4030_dapm_dbypassv_control, bypass_event,
1180 SND_SOC_DAPM_POST_REG),
992 1181
993 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL, 1182 /* Digital mixers, power control for the physical DACs */
994 0, 0, NULL, 0), 1183 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
995 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL, 1184 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
996 1, 0, NULL, 0), 1185 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
997 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL, 1186 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
998 2, 0, NULL, 0), 1187 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
999 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL, 1188 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1000 3, 0, NULL, 0), 1189 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1001 1190 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1002 /* Output MUX controls */ 1191 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1192 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1193
1194 /* Analog mixers, power control for the physical PGAs */
1195 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1196 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1197 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1198 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1199 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1200 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1201 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1202 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1203 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1204 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
1205
1206 /* Output MIXER controls */
1003 /* Earpiece */ 1207 /* Earpiece */
1004 SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0, 1208 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1005 &twl4030_dapm_earpiece_control), 1209 &twl4030_dapm_earpiece_controls[0],
1210 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
1006 /* PreDrivL/R */ 1211 /* PreDrivL/R */
1007 SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0, 1212 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1008 &twl4030_dapm_predrivel_control), 1213 &twl4030_dapm_predrivel_controls[0],
1009 SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0, 1214 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1010 &twl4030_dapm_predriver_control), 1215 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1216 &twl4030_dapm_predriver_controls[0],
1217 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
1011 /* HeadsetL/R */ 1218 /* HeadsetL/R */
1012 SND_SOC_DAPM_MUX_E("HeadsetL Mux", SND_SOC_NOPM, 0, 0, 1219 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1013 &twl4030_dapm_hsol_control, headsetl_event, 1220 &twl4030_dapm_hsol_controls[0],
1014 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 1221 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1015 SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0, 1222 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1016 &twl4030_dapm_hsor_control), 1223 0, 0, NULL, 0, headsetlpga_event,
1224 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1225 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1226 &twl4030_dapm_hsor_controls[0],
1227 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
1228 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1229 0, 0, NULL, 0, headsetrpga_event,
1230 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1017 /* CarkitL/R */ 1231 /* CarkitL/R */
1018 SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0, 1232 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1019 &twl4030_dapm_carkitl_control), 1233 &twl4030_dapm_carkitl_controls[0],
1020 SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0, 1234 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1021 &twl4030_dapm_carkitr_control), 1235 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1236 &twl4030_dapm_carkitr_controls[0],
1237 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1238
1239 /* Output MUX controls */
1022 /* HandsfreeL/R */ 1240 /* HandsfreeL/R */
1023 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0, 1241 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1024 &twl4030_dapm_handsfreel_control, handsfree_event, 1242 &twl4030_dapm_handsfreel_control),
1025 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 1243 SND_SOC_DAPM_SWITCH("HandsfreeL Switch", SND_SOC_NOPM, 0, 0,
1026 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0, 1244 &twl4030_dapm_handsfreelmute_control),
1027 &twl4030_dapm_handsfreer_control, handsfree_event, 1245 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1028 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 1246 0, 0, NULL, 0, handsfreelpga_event,
1247 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1248 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1249 &twl4030_dapm_handsfreer_control),
1250 SND_SOC_DAPM_SWITCH("HandsfreeR Switch", SND_SOC_NOPM, 0, 0,
1251 &twl4030_dapm_handsfreermute_control),
1252 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1253 0, 0, NULL, 0, handsfreerpga_event,
1254 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1255 /* Vibra */
1256 SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1257 &twl4030_dapm_vibra_control),
1258 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1259 &twl4030_dapm_vibrapath_control),
1029 1260
1030 /* Introducing four virtual ADC, since TWL4030 have four channel for 1261 /* Introducing four virtual ADC, since TWL4030 have four channel for
1031 capture */ 1262 capture */
@@ -1050,11 +1281,15 @@ static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
1050 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD| 1281 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1051 SND_SOC_DAPM_POST_REG), 1282 SND_SOC_DAPM_POST_REG),
1052 1283
1053 /* Analog input muxes with switch for the capture amplifiers */ 1284 /* Analog input mixers for the capture amplifiers */
1054 SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route", 1285 SND_SOC_DAPM_MIXER("Analog Left Capture Route",
1055 TWL4030_REG_ANAMICL, 4, 0, &twl4030_dapm_analoglmic_control), 1286 TWL4030_REG_ANAMICL, 4, 0,
1056 SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route", 1287 &twl4030_dapm_analoglmic_controls[0],
1057 TWL4030_REG_ANAMICR, 4, 0, &twl4030_dapm_analogrmic_control), 1288 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1289 SND_SOC_DAPM_MIXER("Analog Right Capture Route",
1290 TWL4030_REG_ANAMICR, 4, 0,
1291 &twl4030_dapm_analogrmic_controls[0],
1292 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
1058 1293
1059 SND_SOC_DAPM_PGA("ADC Physical Left", 1294 SND_SOC_DAPM_PGA("ADC Physical Left",
1060 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0), 1295 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
@@ -1073,62 +1308,86 @@ static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
1073}; 1308};
1074 1309
1075static const struct snd_soc_dapm_route intercon[] = { 1310static const struct snd_soc_dapm_route intercon[] = {
1076 {"Analog L1 Playback Mixer", NULL, "DAC Left1"}, 1311 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1077 {"Analog R1 Playback Mixer", NULL, "DAC Right1"}, 1312 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1078 {"Analog L2 Playback Mixer", NULL, "DAC Left2"}, 1313 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1079 {"Analog R2 Playback Mixer", NULL, "DAC Right2"}, 1314 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1080 1315 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1081 {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"}, 1316
1082 {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"}, 1317 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1083 {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"}, 1318 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1084 {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"}, 1319 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1320 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1321 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1085 1322
1086 /* Internal playback routings */ 1323 /* Internal playback routings */
1087 /* Earpiece */ 1324 /* Earpiece */
1088 {"Earpiece Mux", "DACL1", "ARXL1_APGA"}, 1325 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1089 {"Earpiece Mux", "DACL2", "ARXL2_APGA"}, 1326 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1090 {"Earpiece Mux", "DACR1", "ARXR1_APGA"}, 1327 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1328 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1091 /* PreDrivL */ 1329 /* PreDrivL */
1092 {"PredriveL Mux", "DACL1", "ARXL1_APGA"}, 1330 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1093 {"PredriveL Mux", "DACL2", "ARXL2_APGA"}, 1331 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1094 {"PredriveL Mux", "DACR2", "ARXR2_APGA"}, 1332 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1333 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1095 /* PreDrivR */ 1334 /* PreDrivR */
1096 {"PredriveR Mux", "DACR1", "ARXR1_APGA"}, 1335 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1097 {"PredriveR Mux", "DACR2", "ARXR2_APGA"}, 1336 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1098 {"PredriveR Mux", "DACL2", "ARXL2_APGA"}, 1337 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1338 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1099 /* HeadsetL */ 1339 /* HeadsetL */
1100 {"HeadsetL Mux", "DACL1", "ARXL1_APGA"}, 1340 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1101 {"HeadsetL Mux", "DACL2", "ARXL2_APGA"}, 1341 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1342 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1343 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
1102 /* HeadsetR */ 1344 /* HeadsetR */
1103 {"HeadsetR Mux", "DACR1", "ARXR1_APGA"}, 1345 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1104 {"HeadsetR Mux", "DACR2", "ARXR2_APGA"}, 1346 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1347 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1348 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
1105 /* CarkitL */ 1349 /* CarkitL */
1106 {"CarkitL Mux", "DACL1", "ARXL1_APGA"}, 1350 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1107 {"CarkitL Mux", "DACL2", "ARXL2_APGA"}, 1351 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1352 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1108 /* CarkitR */ 1353 /* CarkitR */
1109 {"CarkitR Mux", "DACR1", "ARXR1_APGA"}, 1354 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1110 {"CarkitR Mux", "DACR2", "ARXR2_APGA"}, 1355 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1356 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1111 /* HandsfreeL */ 1357 /* HandsfreeL */
1112 {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"}, 1358 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1113 {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"}, 1359 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1114 {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"}, 1360 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1361 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
1362 {"HandsfreeL Switch", "Switch", "HandsfreeL Mux"},
1363 {"HandsfreeL PGA", NULL, "HandsfreeL Switch"},
1115 /* HandsfreeR */ 1364 /* HandsfreeR */
1116 {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"}, 1365 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1117 {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"}, 1366 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1118 {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"}, 1367 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1368 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
1369 {"HandsfreeR Switch", "Switch", "HandsfreeR Mux"},
1370 {"HandsfreeR PGA", NULL, "HandsfreeR Switch"},
1371 /* Vibra */
1372 {"Vibra Mux", "AudioL1", "DAC Left1"},
1373 {"Vibra Mux", "AudioR1", "DAC Right1"},
1374 {"Vibra Mux", "AudioL2", "DAC Left2"},
1375 {"Vibra Mux", "AudioR2", "DAC Right2"},
1119 1376
1120 /* outputs */ 1377 /* outputs */
1121 {"OUTL", NULL, "ARXL2_APGA"}, 1378 {"OUTL", NULL, "Analog L2 Playback Mixer"},
1122 {"OUTR", NULL, "ARXR2_APGA"}, 1379 {"OUTR", NULL, "Analog R2 Playback Mixer"},
1123 {"EARPIECE", NULL, "Earpiece Mux"}, 1380 {"EARPIECE", NULL, "Earpiece Mixer"},
1124 {"PREDRIVEL", NULL, "PredriveL Mux"}, 1381 {"PREDRIVEL", NULL, "PredriveL Mixer"},
1125 {"PREDRIVER", NULL, "PredriveR Mux"}, 1382 {"PREDRIVER", NULL, "PredriveR Mixer"},
1126 {"HSOL", NULL, "HeadsetL Mux"}, 1383 {"HSOL", NULL, "HeadsetL PGA"},
1127 {"HSOR", NULL, "HeadsetR Mux"}, 1384 {"HSOR", NULL, "HeadsetR PGA"},
1128 {"CARKITL", NULL, "CarkitL Mux"}, 1385 {"CARKITL", NULL, "CarkitL Mixer"},
1129 {"CARKITR", NULL, "CarkitR Mux"}, 1386 {"CARKITR", NULL, "CarkitR Mixer"},
1130 {"HFL", NULL, "HandsfreeL Mux"}, 1387 {"HFL", NULL, "HandsfreeL PGA"},
1131 {"HFR", NULL, "HandsfreeR Mux"}, 1388 {"HFR", NULL, "HandsfreeR PGA"},
1389 {"Vibra Route", "Audio", "Vibra Mux"},
1390 {"VIBRA", NULL, "Vibra Route"},
1132 1391
1133 /* Capture path */ 1392 /* Capture path */
1134 {"Analog Left Capture Route", "Main mic", "MAINMIC"}, 1393 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
@@ -1168,18 +1427,22 @@ static const struct snd_soc_dapm_route intercon[] = {
1168 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"}, 1427 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1169 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"}, 1428 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1170 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"}, 1429 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
1430 {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
1171 1431
1172 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"}, 1432 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1173 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"}, 1433 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1174 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"}, 1434 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1175 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"}, 1435 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1436 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
1176 1437
1177 /* Digital bypass routes */ 1438 /* Digital bypass routes */
1178 {"Right Digital Loopback", "Volume", "TX1 Capture Route"}, 1439 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1179 {"Left Digital Loopback", "Volume", "TX1 Capture Route"}, 1440 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
1441 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
1180 1442
1181 {"Analog R2 Playback Mixer", NULL, "Right Digital Loopback"}, 1443 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1182 {"Analog L2 Playback Mixer", NULL, "Left Digital Loopback"}, 1444 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1445 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
1183 1446
1184}; 1447};
1185 1448
@@ -1226,6 +1489,58 @@ static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1226 return 0; 1489 return 0;
1227} 1490}
1228 1491
1492static void twl4030_constraints(struct twl4030_priv *twl4030,
1493 struct snd_pcm_substream *mst_substream)
1494{
1495 struct snd_pcm_substream *slv_substream;
1496
1497 /* Pick the stream, which need to be constrained */
1498 if (mst_substream == twl4030->master_substream)
1499 slv_substream = twl4030->slave_substream;
1500 else if (mst_substream == twl4030->slave_substream)
1501 slv_substream = twl4030->master_substream;
1502 else /* This should not happen.. */
1503 return;
1504
1505 /* Set the constraints according to the already configured stream */
1506 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1507 SNDRV_PCM_HW_PARAM_RATE,
1508 twl4030->rate,
1509 twl4030->rate);
1510
1511 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1512 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1513 twl4030->sample_bits,
1514 twl4030->sample_bits);
1515
1516 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1517 SNDRV_PCM_HW_PARAM_CHANNELS,
1518 twl4030->channels,
1519 twl4030->channels);
1520}
1521
1522/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1523 * capture has to be enabled/disabled. */
1524static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1525 int enable)
1526{
1527 u8 reg, mask;
1528
1529 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1530
1531 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1532 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1533 else
1534 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1535
1536 if (enable)
1537 reg |= mask;
1538 else
1539 reg &= ~mask;
1540
1541 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1542}
1543
1229static int twl4030_startup(struct snd_pcm_substream *substream, 1544static int twl4030_startup(struct snd_pcm_substream *substream,
1230 struct snd_soc_dai *dai) 1545 struct snd_soc_dai *dai)
1231{ 1546{
@@ -1234,26 +1549,25 @@ static int twl4030_startup(struct snd_pcm_substream *substream,
1234 struct snd_soc_codec *codec = socdev->card->codec; 1549 struct snd_soc_codec *codec = socdev->card->codec;
1235 struct twl4030_priv *twl4030 = codec->private_data; 1550 struct twl4030_priv *twl4030 = codec->private_data;
1236 1551
1237 /* If we already have a playback or capture going then constrain
1238 * this substream to match it.
1239 */
1240 if (twl4030->master_substream) { 1552 if (twl4030->master_substream) {
1241 struct snd_pcm_runtime *master_runtime;
1242 master_runtime = twl4030->master_substream->runtime;
1243
1244 snd_pcm_hw_constraint_minmax(substream->runtime,
1245 SNDRV_PCM_HW_PARAM_RATE,
1246 master_runtime->rate,
1247 master_runtime->rate);
1248
1249 snd_pcm_hw_constraint_minmax(substream->runtime,
1250 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1251 master_runtime->sample_bits,
1252 master_runtime->sample_bits);
1253
1254 twl4030->slave_substream = substream; 1553 twl4030->slave_substream = substream;
1255 } else 1554 /* The DAI has one configuration for playback and capture, so
1555 * if the DAI has been already configured then constrain this
1556 * substream to match it. */
1557 if (twl4030->configured)
1558 twl4030_constraints(twl4030, twl4030->master_substream);
1559 } else {
1560 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1561 TWL4030_OPTION_1)) {
1562 /* In option2 4 channel is not supported, set the
1563 * constraint for the first stream for channels, the
1564 * second stream will 'inherit' this cosntraint */
1565 snd_pcm_hw_constraint_minmax(substream->runtime,
1566 SNDRV_PCM_HW_PARAM_CHANNELS,
1567 2, 2);
1568 }
1256 twl4030->master_substream = substream; 1569 twl4030->master_substream = substream;
1570 }
1257 1571
1258 return 0; 1572 return 0;
1259} 1573}
@@ -1270,6 +1584,17 @@ static void twl4030_shutdown(struct snd_pcm_substream *substream,
1270 twl4030->master_substream = twl4030->slave_substream; 1584 twl4030->master_substream = twl4030->slave_substream;
1271 1585
1272 twl4030->slave_substream = NULL; 1586 twl4030->slave_substream = NULL;
1587
1588 /* If all streams are closed, or the remaining stream has not yet
1589 * been configured than set the DAI as not configured. */
1590 if (!twl4030->master_substream)
1591 twl4030->configured = 0;
1592 else if (!twl4030->master_substream->runtime->channels)
1593 twl4030->configured = 0;
1594
1595 /* If the closing substream had 4 channel, do the necessary cleanup */
1596 if (substream->runtime->channels == 4)
1597 twl4030_tdm_enable(codec, substream->stream, 0);
1273} 1598}
1274 1599
1275static int twl4030_hw_params(struct snd_pcm_substream *substream, 1600static int twl4030_hw_params(struct snd_pcm_substream *substream,
@@ -1282,8 +1607,24 @@ static int twl4030_hw_params(struct snd_pcm_substream *substream,
1282 struct twl4030_priv *twl4030 = codec->private_data; 1607 struct twl4030_priv *twl4030 = codec->private_data;
1283 u8 mode, old_mode, format, old_format; 1608 u8 mode, old_mode, format, old_format;
1284 1609
1285 if (substream == twl4030->slave_substream) 1610 /* If the substream has 4 channel, do the necessary setup */
1286 /* Ignoring hw_params for slave substream */ 1611 if (params_channels(params) == 4) {
1612 u8 format, mode;
1613
1614 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1615 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1616
1617 /* Safety check: are we in the correct operating mode and
1618 * the interface is in TDM mode? */
1619 if ((mode & TWL4030_OPTION_1) &&
1620 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
1621 twl4030_tdm_enable(codec, substream->stream, 1);
1622 else
1623 return -EINVAL;
1624 }
1625
1626 if (twl4030->configured)
1627 /* Ignoring hw_params for already configured DAI */
1287 return 0; 1628 return 0;
1288 1629
1289 /* bit rate */ 1630 /* bit rate */
@@ -1363,6 +1704,21 @@ static int twl4030_hw_params(struct snd_pcm_substream *substream,
1363 /* set CODECPDZ afterwards */ 1704 /* set CODECPDZ afterwards */
1364 twl4030_codec_enable(codec, 1); 1705 twl4030_codec_enable(codec, 1);
1365 } 1706 }
1707
1708 /* Store the important parameters for the DAI configuration and set
1709 * the DAI as configured */
1710 twl4030->configured = 1;
1711 twl4030->rate = params_rate(params);
1712 twl4030->sample_bits = hw_param_interval(params,
1713 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1714 twl4030->channels = params_channels(params);
1715
1716 /* If both playback and capture streams are open, and one of them
1717 * is setting the hw parameters right now (since we are here), set
1718 * constraints to the other stream to match the current one. */
1719 if (twl4030->slave_substream)
1720 twl4030_constraints(twl4030, substream);
1721
1366 return 0; 1722 return 0;
1367} 1723}
1368 1724
@@ -1370,17 +1726,21 @@ static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1370 int clk_id, unsigned int freq, int dir) 1726 int clk_id, unsigned int freq, int dir)
1371{ 1727{
1372 struct snd_soc_codec *codec = codec_dai->codec; 1728 struct snd_soc_codec *codec = codec_dai->codec;
1729 struct twl4030_priv *twl4030 = codec->private_data;
1373 u8 infreq; 1730 u8 infreq;
1374 1731
1375 switch (freq) { 1732 switch (freq) {
1376 case 19200000: 1733 case 19200000:
1377 infreq = TWL4030_APLL_INFREQ_19200KHZ; 1734 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1735 twl4030->sysclk = 19200;
1378 break; 1736 break;
1379 case 26000000: 1737 case 26000000:
1380 infreq = TWL4030_APLL_INFREQ_26000KHZ; 1738 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1739 twl4030->sysclk = 26000;
1381 break; 1740 break;
1382 case 38400000: 1741 case 38400000:
1383 infreq = TWL4030_APLL_INFREQ_38400KHZ; 1742 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1743 twl4030->sysclk = 38400;
1384 break; 1744 break;
1385 default: 1745 default:
1386 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n", 1746 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
@@ -1424,6 +1784,9 @@ static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1424 case SND_SOC_DAIFMT_I2S: 1784 case SND_SOC_DAIFMT_I2S:
1425 format |= TWL4030_AIF_FORMAT_CODEC; 1785 format |= TWL4030_AIF_FORMAT_CODEC;
1426 break; 1786 break;
1787 case SND_SOC_DAIFMT_DSP_A:
1788 format |= TWL4030_AIF_FORMAT_TDM;
1789 break;
1427 default: 1790 default:
1428 return -EINVAL; 1791 return -EINVAL;
1429 } 1792 }
@@ -1443,6 +1806,180 @@ static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1443 return 0; 1806 return 0;
1444} 1807}
1445 1808
1809/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1810 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1811static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1812 int enable)
1813{
1814 u8 reg, mask;
1815
1816 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1817
1818 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1819 mask = TWL4030_ARXL1_VRX_EN;
1820 else
1821 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1822
1823 if (enable)
1824 reg |= mask;
1825 else
1826 reg &= ~mask;
1827
1828 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1829}
1830
1831static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1832 struct snd_soc_dai *dai)
1833{
1834 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1835 struct snd_soc_device *socdev = rtd->socdev;
1836 struct snd_soc_codec *codec = socdev->card->codec;
1837 u8 infreq;
1838 u8 mode;
1839
1840 /* If the system master clock is not 26MHz, the voice PCM interface is
1841 * not avilable.
1842 */
1843 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1844 & TWL4030_APLL_INFREQ;
1845
1846 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1847 printk(KERN_ERR "TWL4030 voice startup: "
1848 "MCLK is not 26MHz, call set_sysclk() on init\n");
1849 return -EINVAL;
1850 }
1851
1852 /* If the codec mode is not option2, the voice PCM interface is not
1853 * avilable.
1854 */
1855 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1856 & TWL4030_OPT_MODE;
1857
1858 if (mode != TWL4030_OPTION_2) {
1859 printk(KERN_ERR "TWL4030 voice startup: "
1860 "the codec mode is not option2\n");
1861 return -EINVAL;
1862 }
1863
1864 return 0;
1865}
1866
1867static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1868 struct snd_soc_dai *dai)
1869{
1870 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1871 struct snd_soc_device *socdev = rtd->socdev;
1872 struct snd_soc_codec *codec = socdev->card->codec;
1873
1874 /* Enable voice digital filters */
1875 twl4030_voice_enable(codec, substream->stream, 0);
1876}
1877
1878static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1879 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1880{
1881 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1882 struct snd_soc_device *socdev = rtd->socdev;
1883 struct snd_soc_codec *codec = socdev->card->codec;
1884 u8 old_mode, mode;
1885
1886 /* Enable voice digital filters */
1887 twl4030_voice_enable(codec, substream->stream, 1);
1888
1889 /* bit rate */
1890 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1891 & ~(TWL4030_CODECPDZ);
1892 mode = old_mode;
1893
1894 switch (params_rate(params)) {
1895 case 8000:
1896 mode &= ~(TWL4030_SEL_16K);
1897 break;
1898 case 16000:
1899 mode |= TWL4030_SEL_16K;
1900 break;
1901 default:
1902 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1903 params_rate(params));
1904 return -EINVAL;
1905 }
1906
1907 if (mode != old_mode) {
1908 /* change rate and set CODECPDZ */
1909 twl4030_codec_enable(codec, 0);
1910 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1911 twl4030_codec_enable(codec, 1);
1912 }
1913
1914 return 0;
1915}
1916
1917static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1918 int clk_id, unsigned int freq, int dir)
1919{
1920 struct snd_soc_codec *codec = codec_dai->codec;
1921 u8 infreq;
1922
1923 switch (freq) {
1924 case 26000000:
1925 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1926 break;
1927 default:
1928 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1929 freq);
1930 return -EINVAL;
1931 }
1932
1933 infreq |= TWL4030_APLL_EN;
1934 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1935
1936 return 0;
1937}
1938
1939static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1940 unsigned int fmt)
1941{
1942 struct snd_soc_codec *codec = codec_dai->codec;
1943 u8 old_format, format;
1944
1945 /* get format */
1946 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1947 format = old_format;
1948
1949 /* set master/slave audio interface */
1950 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1951 case SND_SOC_DAIFMT_CBS_CFM:
1952 format &= ~(TWL4030_VIF_SLAVE_EN);
1953 break;
1954 case SND_SOC_DAIFMT_CBS_CFS:
1955 format |= TWL4030_VIF_SLAVE_EN;
1956 break;
1957 default:
1958 return -EINVAL;
1959 }
1960
1961 /* clock inversion */
1962 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1963 case SND_SOC_DAIFMT_IB_NF:
1964 format &= ~(TWL4030_VIF_FORMAT);
1965 break;
1966 case SND_SOC_DAIFMT_NB_IF:
1967 format |= TWL4030_VIF_FORMAT;
1968 break;
1969 default:
1970 return -EINVAL;
1971 }
1972
1973 if (format != old_format) {
1974 /* change format and set CODECPDZ */
1975 twl4030_codec_enable(codec, 0);
1976 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
1977 twl4030_codec_enable(codec, 1);
1978 }
1979
1980 return 0;
1981}
1982
1446#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000) 1983#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
1447#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE) 1984#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1448 1985
@@ -1454,21 +1991,47 @@ static struct snd_soc_dai_ops twl4030_dai_ops = {
1454 .set_fmt = twl4030_set_dai_fmt, 1991 .set_fmt = twl4030_set_dai_fmt,
1455}; 1992};
1456 1993
1457struct snd_soc_dai twl4030_dai = { 1994static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
1995 .startup = twl4030_voice_startup,
1996 .shutdown = twl4030_voice_shutdown,
1997 .hw_params = twl4030_voice_hw_params,
1998 .set_sysclk = twl4030_voice_set_dai_sysclk,
1999 .set_fmt = twl4030_voice_set_dai_fmt,
2000};
2001
2002struct snd_soc_dai twl4030_dai[] = {
2003{
1458 .name = "twl4030", 2004 .name = "twl4030",
1459 .playback = { 2005 .playback = {
1460 .stream_name = "Playback", 2006 .stream_name = "HiFi Playback",
1461 .channels_min = 2, 2007 .channels_min = 2,
1462 .channels_max = 2, 2008 .channels_max = 4,
1463 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000, 2009 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
1464 .formats = TWL4030_FORMATS,}, 2010 .formats = TWL4030_FORMATS,},
1465 .capture = { 2011 .capture = {
1466 .stream_name = "Capture", 2012 .stream_name = "Capture",
1467 .channels_min = 2, 2013 .channels_min = 2,
1468 .channels_max = 2, 2014 .channels_max = 4,
1469 .rates = TWL4030_RATES, 2015 .rates = TWL4030_RATES,
1470 .formats = TWL4030_FORMATS,}, 2016 .formats = TWL4030_FORMATS,},
1471 .ops = &twl4030_dai_ops, 2017 .ops = &twl4030_dai_ops,
2018},
2019{
2020 .name = "twl4030 Voice",
2021 .playback = {
2022 .stream_name = "Voice Playback",
2023 .channels_min = 1,
2024 .channels_max = 1,
2025 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2026 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2027 .capture = {
2028 .stream_name = "Capture",
2029 .channels_min = 1,
2030 .channels_max = 2,
2031 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2032 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2033 .ops = &twl4030_dai_voice_ops,
2034},
1472}; 2035};
1473EXPORT_SYMBOL_GPL(twl4030_dai); 2036EXPORT_SYMBOL_GPL(twl4030_dai);
1474 2037
@@ -1500,6 +2063,8 @@ static int twl4030_resume(struct platform_device *pdev)
1500static int twl4030_init(struct snd_soc_device *socdev) 2063static int twl4030_init(struct snd_soc_device *socdev)
1501{ 2064{
1502 struct snd_soc_codec *codec = socdev->card->codec; 2065 struct snd_soc_codec *codec = socdev->card->codec;
2066 struct twl4030_setup_data *setup = socdev->codec_data;
2067 struct twl4030_priv *twl4030 = codec->private_data;
1503 int ret = 0; 2068 int ret = 0;
1504 2069
1505 printk(KERN_INFO "TWL4030 Audio Codec init \n"); 2070 printk(KERN_INFO "TWL4030 Audio Codec init \n");
@@ -1509,14 +2074,31 @@ static int twl4030_init(struct snd_soc_device *socdev)
1509 codec->read = twl4030_read_reg_cache; 2074 codec->read = twl4030_read_reg_cache;
1510 codec->write = twl4030_write; 2075 codec->write = twl4030_write;
1511 codec->set_bias_level = twl4030_set_bias_level; 2076 codec->set_bias_level = twl4030_set_bias_level;
1512 codec->dai = &twl4030_dai; 2077 codec->dai = twl4030_dai;
1513 codec->num_dai = 1; 2078 codec->num_dai = ARRAY_SIZE(twl4030_dai),
1514 codec->reg_cache_size = sizeof(twl4030_reg); 2079 codec->reg_cache_size = sizeof(twl4030_reg);
1515 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), 2080 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1516 GFP_KERNEL); 2081 GFP_KERNEL);
1517 if (codec->reg_cache == NULL) 2082 if (codec->reg_cache == NULL)
1518 return -ENOMEM; 2083 return -ENOMEM;
1519 2084
2085 /* Configuration for headset ramp delay from setup data */
2086 if (setup) {
2087 unsigned char hs_pop;
2088
2089 if (setup->sysclk)
2090 twl4030->sysclk = setup->sysclk;
2091 else
2092 twl4030->sysclk = 26000;
2093
2094 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
2095 hs_pop &= ~TWL4030_RAMP_DELAY;
2096 hs_pop |= (setup->ramp_delay_value << 2);
2097 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
2098 } else {
2099 twl4030->sysclk = 26000;
2100 }
2101
1520 /* register pcms */ 2102 /* register pcms */
1521 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 2103 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1522 if (ret < 0) { 2104 if (ret < 0) {
@@ -1604,13 +2186,13 @@ EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1604 2186
1605static int __init twl4030_modinit(void) 2187static int __init twl4030_modinit(void)
1606{ 2188{
1607 return snd_soc_register_dai(&twl4030_dai); 2189 return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
1608} 2190}
1609module_init(twl4030_modinit); 2191module_init(twl4030_modinit);
1610 2192
1611static void __exit twl4030_exit(void) 2193static void __exit twl4030_exit(void)
1612{ 2194{
1613 snd_soc_unregister_dai(&twl4030_dai); 2195 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
1614} 2196}
1615module_exit(twl4030_exit); 2197module_exit(twl4030_exit);
1616 2198
diff --git a/sound/soc/codecs/twl4030.h b/sound/soc/codecs/twl4030.h
index cb63765db1df..fe5f395d9e4f 100644
--- a/sound/soc/codecs/twl4030.h
+++ b/sound/soc/codecs/twl4030.h
@@ -92,8 +92,9 @@
92#define TWL4030_REG_VIBRA_PWM_SET 0x47 92#define TWL4030_REG_VIBRA_PWM_SET 0x47
93#define TWL4030_REG_ANAMIC_GAIN 0x48 93#define TWL4030_REG_ANAMIC_GAIN 0x48
94#define TWL4030_REG_MISC_SET_2 0x49 94#define TWL4030_REG_MISC_SET_2 0x49
95#define TWL4030_REG_SW_SHADOW 0x4A
95 96
96#define TWL4030_CACHEREGNUM (TWL4030_REG_MISC_SET_2 + 1) 97#define TWL4030_CACHEREGNUM (TWL4030_REG_SW_SHADOW + 1)
97 98
98/* Bitfield Definitions */ 99/* Bitfield Definitions */
99 100
@@ -110,9 +111,22 @@
110#define TWL4030_APLL_RATE_44100 0x90 111#define TWL4030_APLL_RATE_44100 0x90
111#define TWL4030_APLL_RATE_48000 0xA0 112#define TWL4030_APLL_RATE_48000 0xA0
112#define TWL4030_APLL_RATE_96000 0xE0 113#define TWL4030_APLL_RATE_96000 0xE0
113#define TWL4030_SEL_16K 0x04 114#define TWL4030_SEL_16K 0x08
114#define TWL4030_CODECPDZ 0x02 115#define TWL4030_CODECPDZ 0x02
115#define TWL4030_OPT_MODE 0x01 116#define TWL4030_OPT_MODE 0x01
117#define TWL4030_OPTION_1 (1 << 0)
118#define TWL4030_OPTION_2 (0 << 0)
119
120/* TWL4030_OPTION (0x02) Fields */
121
122#define TWL4030_ATXL1_EN (1 << 0)
123#define TWL4030_ATXR1_EN (1 << 1)
124#define TWL4030_ATXL2_VTXL_EN (1 << 2)
125#define TWL4030_ATXR2_VTXR_EN (1 << 3)
126#define TWL4030_ARXL1_VRX_EN (1 << 4)
127#define TWL4030_ARXR1_EN (1 << 5)
128#define TWL4030_ARXL2_EN (1 << 6)
129#define TWL4030_ARXR2_EN (1 << 7)
116 130
117/* TWL4030_REG_MICBIAS_CTL (0x04) Fields */ 131/* TWL4030_REG_MICBIAS_CTL (0x04) Fields */
118 132
@@ -171,6 +185,17 @@
171#define TWL4030_CLK256FS_EN 0x02 185#define TWL4030_CLK256FS_EN 0x02
172#define TWL4030_AIF_EN 0x01 186#define TWL4030_AIF_EN 0x01
173 187
188/* VOICE_IF (0x0F) Fields */
189
190#define TWL4030_VIF_SLAVE_EN 0x80
191#define TWL4030_VIF_DIN_EN 0x40
192#define TWL4030_VIF_DOUT_EN 0x20
193#define TWL4030_VIF_SWAP 0x10
194#define TWL4030_VIF_FORMAT 0x08
195#define TWL4030_VIF_TRI_EN 0x04
196#define TWL4030_VIF_SUB_EN 0x02
197#define TWL4030_VIF_EN 0x01
198
174/* EAR_CTL (0x21) */ 199/* EAR_CTL (0x21) */
175#define TWL4030_EAR_GAIN 0x30 200#define TWL4030_EAR_GAIN 0x30
176 201
@@ -236,7 +261,19 @@
236#define TWL4030_SMOOTH_ANAVOL_EN 0x02 261#define TWL4030_SMOOTH_ANAVOL_EN 0x02
237#define TWL4030_DIGMIC_LR_SWAP_EN 0x01 262#define TWL4030_DIGMIC_LR_SWAP_EN 0x01
238 263
239extern struct snd_soc_dai twl4030_dai; 264/* TWL4030_REG_SW_SHADOW (0x4A) Fields */
265#define TWL4030_HFL_EN 0x01
266#define TWL4030_HFR_EN 0x02
267
268#define TWL4030_DAI_HIFI 0
269#define TWL4030_DAI_VOICE 1
270
271extern struct snd_soc_dai twl4030_dai[2];
240extern struct snd_soc_codec_device soc_codec_dev_twl4030; 272extern struct snd_soc_codec_device soc_codec_dev_twl4030;
241 273
274struct twl4030_setup_data {
275 unsigned int ramp_delay_value;
276 unsigned int sysclk;
277};
278
242#endif /* End of __TWL4030_AUDIO_H__ */ 279#endif /* End of __TWL4030_AUDIO_H__ */
diff --git a/sound/soc/codecs/uda134x.c b/sound/soc/codecs/uda134x.c
index ddefb8f80145..269b108e1de6 100644
--- a/sound/soc/codecs/uda134x.c
+++ b/sound/soc/codecs/uda134x.c
@@ -101,7 +101,7 @@ static int uda134x_write(struct snd_soc_codec *codec, unsigned int reg,
101 pr_debug("%s reg: %02X, value:%02X\n", __func__, reg, value); 101 pr_debug("%s reg: %02X, value:%02X\n", __func__, reg, value);
102 102
103 if (reg >= UDA134X_REGS_NUM) { 103 if (reg >= UDA134X_REGS_NUM) {
104 printk(KERN_ERR "%s unkown register: reg: %d", 104 printk(KERN_ERR "%s unkown register: reg: %u",
105 __func__, reg); 105 __func__, reg);
106 return -EINVAL; 106 return -EINVAL;
107 } 107 }
@@ -296,7 +296,7 @@ static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
296 struct snd_soc_codec *codec = codec_dai->codec; 296 struct snd_soc_codec *codec = codec_dai->codec;
297 struct uda134x_priv *uda134x = codec->private_data; 297 struct uda134x_priv *uda134x = codec->private_data;
298 298
299 pr_debug("%s clk_id: %d, freq: %d, dir: %d\n", __func__, 299 pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
300 clk_id, freq, dir); 300 clk_id, freq, dir);
301 301
302 /* Anything between 256fs*8Khz and 512fs*48Khz should be acceptable 302 /* Anything between 256fs*8Khz and 512fs*48Khz should be acceptable
diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c
index 0275321ff8ab..e7348d341b76 100644
--- a/sound/soc/codecs/wm8350.c
+++ b/sound/soc/codecs/wm8350.c
@@ -1108,7 +1108,7 @@ static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
1108 if (ret < 0) 1108 if (ret < 0)
1109 return ret; 1109 return ret;
1110 dev_dbg(wm8350->dev, 1110 dev_dbg(wm8350->dev,
1111 "FLL in %d FLL out %d N 0x%x K 0x%x div %d ratio %d", 1111 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",
1112 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div, 1112 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
1113 fll_div.ratio); 1113 fll_div.ratio);
1114 1114
diff --git a/sound/soc/codecs/wm8350.h b/sound/soc/codecs/wm8350.h
index d11bd9288cf9..d088eb4b88bb 100644
--- a/sound/soc/codecs/wm8350.h
+++ b/sound/soc/codecs/wm8350.h
@@ -13,6 +13,7 @@
13#define _WM8350_H 13#define _WM8350_H
14 14
15#include <sound/soc.h> 15#include <sound/soc.h>
16#include <linux/mfd/wm8350/audio.h>
16 17
17extern struct snd_soc_dai wm8350_dai; 18extern struct snd_soc_dai wm8350_dai;
18extern struct snd_soc_codec_device soc_codec_dev_wm8350; 19extern struct snd_soc_codec_device soc_codec_dev_wm8350;
diff --git a/sound/soc/codecs/wm8400.c b/sound/soc/codecs/wm8400.c
index 510efa604008..502eefac1ecd 100644
--- a/sound/soc/codecs/wm8400.c
+++ b/sound/soc/codecs/wm8400.c
@@ -954,7 +954,7 @@ static int fll_factors(struct wm8400_priv *wm8400, struct fll_factors *factors,
954 factors->outdiv *= 2; 954 factors->outdiv *= 2;
955 if (factors->outdiv > 32) { 955 if (factors->outdiv > 32) {
956 dev_err(wm8400->wm8400->dev, 956 dev_err(wm8400->wm8400->dev,
957 "Unsupported FLL output frequency %dHz\n", 957 "Unsupported FLL output frequency %uHz\n",
958 Fout); 958 Fout);
959 return -EINVAL; 959 return -EINVAL;
960 } 960 }
@@ -1003,7 +1003,7 @@ static int fll_factors(struct wm8400_priv *wm8400, struct fll_factors *factors,
1003 factors->k = K / 10; 1003 factors->k = K / 10;
1004 1004
1005 dev_dbg(wm8400->wm8400->dev, 1005 dev_dbg(wm8400->wm8400->dev,
1006 "FLL: Fref=%d Fout=%d N=%x K=%x, FRATIO=%x OUTDIV=%x\n", 1006 "FLL: Fref=%u Fout=%u N=%x K=%x, FRATIO=%x OUTDIV=%x\n",
1007 Fref, Fout, 1007 Fref, Fout,
1008 factors->n, factors->k, factors->fratio, factors->outdiv); 1008 factors->n, factors->k, factors->fratio, factors->outdiv);
1009 1009
@@ -1473,8 +1473,8 @@ static int wm8400_codec_probe(struct platform_device *dev)
1473 1473
1474 codec = &priv->codec; 1474 codec = &priv->codec;
1475 codec->private_data = priv; 1475 codec->private_data = priv;
1476 codec->control_data = dev->dev.driver_data; 1476 codec->control_data = dev_get_drvdata(&dev->dev);
1477 priv->wm8400 = dev->dev.driver_data; 1477 priv->wm8400 = dev_get_drvdata(&dev->dev);
1478 1478
1479 ret = regulator_bulk_get(priv->wm8400->dev, 1479 ret = regulator_bulk_get(priv->wm8400->dev,
1480 ARRAY_SIZE(power), &power[0]); 1480 ARRAY_SIZE(power), &power[0]);
diff --git a/sound/soc/codecs/wm8510.c b/sound/soc/codecs/wm8510.c
index 6a4cea09c45d..c8b8dba85890 100644
--- a/sound/soc/codecs/wm8510.c
+++ b/sound/soc/codecs/wm8510.c
@@ -298,7 +298,7 @@ static void pll_factors(unsigned int target, unsigned int source)
298 298
299 if ((Ndiv < 6) || (Ndiv > 12)) 299 if ((Ndiv < 6) || (Ndiv > 12))
300 printk(KERN_WARNING 300 printk(KERN_WARNING
301 "WM8510 N value %d outwith recommended range!d\n", 301 "WM8510 N value %u outwith recommended range!d\n",
302 Ndiv); 302 Ndiv);
303 303
304 pll_div.n = Ndiv; 304 pll_div.n = Ndiv;
diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c
index 9f6be3d31ac0..86c4b24db817 100644
--- a/sound/soc/codecs/wm8580.c
+++ b/sound/soc/codecs/wm8580.c
@@ -415,7 +415,7 @@ static int pll_factors(struct _pll_div *pll_div, unsigned int target,
415 unsigned int K, Ndiv, Nmod; 415 unsigned int K, Ndiv, Nmod;
416 int i; 416 int i;
417 417
418 pr_debug("wm8580: PLL %dHz->%dHz\n", source, target); 418 pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
419 419
420 /* Scale the output frequency up; the PLL should run in the 420 /* Scale the output frequency up; the PLL should run in the
421 * region of 90-100MHz. 421 * region of 90-100MHz.
@@ -447,7 +447,7 @@ static int pll_factors(struct _pll_div *pll_div, unsigned int target,
447 447
448 if ((Ndiv < 5) || (Ndiv > 13)) { 448 if ((Ndiv < 5) || (Ndiv > 13)) {
449 printk(KERN_ERR 449 printk(KERN_ERR
450 "WM8580 N=%d outside supported range\n", Ndiv); 450 "WM8580 N=%u outside supported range\n", Ndiv);
451 return -EINVAL; 451 return -EINVAL;
452 } 452 }
453 453
diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c
index e043e3f60008..7a205876ef4f 100644
--- a/sound/soc/codecs/wm8731.c
+++ b/sound/soc/codecs/wm8731.c
@@ -666,14 +666,14 @@ static int __devinit wm8731_spi_probe(struct spi_device *spi)
666 codec->hw_write = (hw_write_t)wm8731_spi_write; 666 codec->hw_write = (hw_write_t)wm8731_spi_write;
667 codec->dev = &spi->dev; 667 codec->dev = &spi->dev;
668 668
669 spi->dev.driver_data = wm8731; 669 dev_set_drvdata(&spi->dev, wm8731);
670 670
671 return wm8731_register(wm8731); 671 return wm8731_register(wm8731);
672} 672}
673 673
674static int __devexit wm8731_spi_remove(struct spi_device *spi) 674static int __devexit wm8731_spi_remove(struct spi_device *spi)
675{ 675{
676 struct wm8731_priv *wm8731 = spi->dev.driver_data; 676 struct wm8731_priv *wm8731 = dev_get_drvdata(&spi->dev);
677 677
678 wm8731_unregister(wm8731); 678 wm8731_unregister(wm8731);
679 679
diff --git a/sound/soc/codecs/wm8753.c b/sound/soc/codecs/wm8753.c
index a6e8f3f7f052..d28eeaceb857 100644
--- a/sound/soc/codecs/wm8753.c
+++ b/sound/soc/codecs/wm8753.c
@@ -703,7 +703,7 @@ static void pll_factors(struct _pll_div *pll_div, unsigned int target,
703 703
704 if ((Ndiv < 6) || (Ndiv > 12)) 704 if ((Ndiv < 6) || (Ndiv > 12))
705 printk(KERN_WARNING 705 printk(KERN_WARNING
706 "wm8753: unsupported N = %d\n", Ndiv); 706 "wm8753: unsupported N = %u\n", Ndiv);
707 707
708 pll_div->n = Ndiv; 708 pll_div->n = Ndiv;
709 Nmod = target % source; 709 Nmod = target % source;
@@ -1822,14 +1822,14 @@ static int __devinit wm8753_spi_probe(struct spi_device *spi)
1822 codec->hw_write = (hw_write_t)wm8753_spi_write; 1822 codec->hw_write = (hw_write_t)wm8753_spi_write;
1823 codec->dev = &spi->dev; 1823 codec->dev = &spi->dev;
1824 1824
1825 spi->dev.driver_data = wm8753; 1825 dev_set_drvdata(&spi->dev, wm8753);
1826 1826
1827 return wm8753_register(wm8753); 1827 return wm8753_register(wm8753);
1828} 1828}
1829 1829
1830static int __devexit wm8753_spi_remove(struct spi_device *spi) 1830static int __devexit wm8753_spi_remove(struct spi_device *spi)
1831{ 1831{
1832 struct wm8753_priv *wm8753 = spi->dev.driver_data; 1832 struct wm8753_priv *wm8753 = dev_get_drvdata(&spi->dev);
1833 wm8753_unregister(wm8753); 1833 wm8753_unregister(wm8753);
1834 return 0; 1834 return 0;
1835} 1835}
diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c
index 46c5ea1ff921..3c78945244b8 100644
--- a/sound/soc/codecs/wm8900.c
+++ b/sound/soc/codecs/wm8900.c
@@ -778,11 +778,11 @@ static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
778 } 778 }
779 779
780 if (target > 100000000) 780 if (target > 100000000)
781 printk(KERN_WARNING "wm8900: FLL rate %d out of range, Fref=%d" 781 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
782 " Fout=%d\n", target, Fref, Fout); 782 " Fout=%u\n", target, Fref, Fout);
783 if (div > 32) { 783 if (div > 32) {
784 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, " 784 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
785 "Fref=%d, Fout=%d, target=%d\n", 785 "Fref=%u, Fout=%u, target=%u\n",
786 div, Fref, Fout, target); 786 div, Fref, Fout, target);
787 return -EINVAL; 787 return -EINVAL;
788 } 788 }
diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c
index 8cf571f1a803..d8a9222fbf74 100644
--- a/sound/soc/codecs/wm8903.c
+++ b/sound/soc/codecs/wm8903.c
@@ -217,7 +217,6 @@ struct wm8903_priv {
217 int sysclk; 217 int sysclk;
218 218
219 /* Reference counts */ 219 /* Reference counts */
220 int charge_pump_users;
221 int class_w_users; 220 int class_w_users;
222 int playback_active; 221 int playback_active;
223 int capture_active; 222 int capture_active;
@@ -373,6 +372,15 @@ static void wm8903_reset(struct snd_soc_codec *codec)
373#define WM8903_OUTPUT_INT 0x2 372#define WM8903_OUTPUT_INT 0x2
374#define WM8903_OUTPUT_IN 0x1 373#define WM8903_OUTPUT_IN 0x1
375 374
375static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
376 struct snd_kcontrol *kcontrol, int event)
377{
378 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
379 mdelay(4);
380
381 return 0;
382}
383
376/* 384/*
377 * Event for headphone and line out amplifier power changes. Special 385 * Event for headphone and line out amplifier power changes. Special
378 * power up/down sequences are required in order to maximise pop/click 386 * power up/down sequences are required in order to maximise pop/click
@@ -382,19 +390,20 @@ static int wm8903_output_event(struct snd_soc_dapm_widget *w,
382 struct snd_kcontrol *kcontrol, int event) 390 struct snd_kcontrol *kcontrol, int event)
383{ 391{
384 struct snd_soc_codec *codec = w->codec; 392 struct snd_soc_codec *codec = w->codec;
385 struct wm8903_priv *wm8903 = codec->private_data;
386 struct i2c_client *i2c = codec->control_data;
387 u16 val; 393 u16 val;
388 u16 reg; 394 u16 reg;
395 u16 dcs_reg;
396 u16 dcs_bit;
389 int shift; 397 int shift;
390 u16 cp_reg = wm8903_read(codec, WM8903_CHARGE_PUMP_0);
391 398
392 switch (w->reg) { 399 switch (w->reg) {
393 case WM8903_POWER_MANAGEMENT_2: 400 case WM8903_POWER_MANAGEMENT_2:
394 reg = WM8903_ANALOGUE_HP_0; 401 reg = WM8903_ANALOGUE_HP_0;
402 dcs_bit = 0 + w->shift;
395 break; 403 break;
396 case WM8903_POWER_MANAGEMENT_3: 404 case WM8903_POWER_MANAGEMENT_3:
397 reg = WM8903_ANALOGUE_LINEOUT_0; 405 reg = WM8903_ANALOGUE_LINEOUT_0;
406 dcs_bit = 2 + w->shift;
398 break; 407 break;
399 default: 408 default:
400 BUG(); 409 BUG();
@@ -419,18 +428,6 @@ static int wm8903_output_event(struct snd_soc_dapm_widget *w,
419 /* Short the output */ 428 /* Short the output */
420 val &= ~(WM8903_OUTPUT_SHORT << shift); 429 val &= ~(WM8903_OUTPUT_SHORT << shift);
421 wm8903_write(codec, reg, val); 430 wm8903_write(codec, reg, val);
422
423 wm8903->charge_pump_users++;
424
425 dev_dbg(&i2c->dev, "Charge pump use count now %d\n",
426 wm8903->charge_pump_users);
427
428 if (wm8903->charge_pump_users == 1) {
429 dev_dbg(&i2c->dev, "Enabling charge pump\n");
430 wm8903_write(codec, WM8903_CHARGE_PUMP_0,
431 cp_reg | WM8903_CP_ENA);
432 mdelay(4);
433 }
434 } 431 }
435 432
436 if (event & SND_SOC_DAPM_POST_PMU) { 433 if (event & SND_SOC_DAPM_POST_PMU) {
@@ -446,6 +443,11 @@ static int wm8903_output_event(struct snd_soc_dapm_widget *w,
446 val |= (WM8903_OUTPUT_OUT << shift); 443 val |= (WM8903_OUTPUT_OUT << shift);
447 wm8903_write(codec, reg, val); 444 wm8903_write(codec, reg, val);
448 445
446 /* Enable the DC servo */
447 dcs_reg = wm8903_read(codec, WM8903_DC_SERVO_0);
448 dcs_reg |= dcs_bit;
449 wm8903_write(codec, WM8903_DC_SERVO_0, dcs_reg);
450
449 /* Remove the short */ 451 /* Remove the short */
450 val |= (WM8903_OUTPUT_SHORT << shift); 452 val |= (WM8903_OUTPUT_SHORT << shift);
451 wm8903_write(codec, reg, val); 453 wm8903_write(codec, reg, val);
@@ -458,25 +460,17 @@ static int wm8903_output_event(struct snd_soc_dapm_widget *w,
458 val &= ~(WM8903_OUTPUT_SHORT << shift); 460 val &= ~(WM8903_OUTPUT_SHORT << shift);
459 wm8903_write(codec, reg, val); 461 wm8903_write(codec, reg, val);
460 462
463 /* Disable the DC servo */
464 dcs_reg = wm8903_read(codec, WM8903_DC_SERVO_0);
465 dcs_reg &= ~dcs_bit;
466 wm8903_write(codec, WM8903_DC_SERVO_0, dcs_reg);
467
461 /* Then disable the intermediate and output stages */ 468 /* Then disable the intermediate and output stages */
462 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT | 469 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
463 WM8903_OUTPUT_IN) << shift); 470 WM8903_OUTPUT_IN) << shift);
464 wm8903_write(codec, reg, val); 471 wm8903_write(codec, reg, val);
465 } 472 }
466 473
467 if (event & SND_SOC_DAPM_POST_PMD) {
468 wm8903->charge_pump_users--;
469
470 dev_dbg(&i2c->dev, "Charge pump use count now %d\n",
471 wm8903->charge_pump_users);
472
473 if (wm8903->charge_pump_users == 0) {
474 dev_dbg(&i2c->dev, "Disabling charge pump\n");
475 wm8903_write(codec, WM8903_CHARGE_PUMP_0,
476 cp_reg & ~WM8903_CP_ENA);
477 }
478 }
479
480 return 0; 474 return 0;
481} 475}
482 476
@@ -539,6 +533,7 @@ static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
539/* ALSA can only do steps of .01dB */ 533/* ALSA can only do steps of .01dB */
540static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 534static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
541 535
536static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
542static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); 537static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
543 538
544static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0); 539static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
@@ -657,6 +652,16 @@ static const struct soc_enum rinput_inv_enum =
657 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text); 652 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
658 653
659 654
655static const char *sidetone_text[] = {
656 "None", "Left", "Right"
657};
658
659static const struct soc_enum lsidetone_enum =
660 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
661
662static const struct soc_enum rsidetone_enum =
663 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
664
660static const struct snd_kcontrol_new wm8903_snd_controls[] = { 665static const struct snd_kcontrol_new wm8903_snd_controls[] = {
661 666
662/* Input PGAs - No TLV since the scale depends on PGA mode */ 667/* Input PGAs - No TLV since the scale depends on PGA mode */
@@ -700,6 +705,9 @@ SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
700SOC_ENUM("ADC Companding Mode", adc_companding), 705SOC_ENUM("ADC Companding Mode", adc_companding),
701SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0), 706SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
702 707
708SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
709 12, 0, digital_sidetone_tlv),
710
703/* DAC */ 711/* DAC */
704SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT, 712SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
705 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), 713 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
@@ -762,6 +770,12 @@ static const struct snd_kcontrol_new rinput_mux =
762static const struct snd_kcontrol_new rinput_inv_mux = 770static const struct snd_kcontrol_new rinput_inv_mux =
763 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum); 771 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
764 772
773static const struct snd_kcontrol_new lsidetone_mux =
774 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
775
776static const struct snd_kcontrol_new rsidetone_mux =
777 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
778
765static const struct snd_kcontrol_new left_output_mixer[] = { 779static const struct snd_kcontrol_new left_output_mixer[] = {
766SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0), 780SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
767SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0), 781SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
@@ -828,6 +842,9 @@ SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
828SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0), 842SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
829SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0), 843SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
830 844
845SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
846SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
847
831SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0), 848SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
832SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0), 849SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
833 850
@@ -844,26 +861,29 @@ SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
844SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2, 861SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
845 1, 0, NULL, 0, wm8903_output_event, 862 1, 0, NULL, 0, wm8903_output_event,
846 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 863 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
847 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 864 SND_SOC_DAPM_PRE_PMD),
848SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2, 865SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
849 0, 0, NULL, 0, wm8903_output_event, 866 0, 0, NULL, 0, wm8903_output_event,
850 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 867 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
851 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 868 SND_SOC_DAPM_PRE_PMD),
852 869
853SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0, 870SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
854 NULL, 0, wm8903_output_event, 871 NULL, 0, wm8903_output_event,
855 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 872 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
856 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 873 SND_SOC_DAPM_PRE_PMD),
857SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0, 874SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
858 NULL, 0, wm8903_output_event, 875 NULL, 0, wm8903_output_event,
859 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 876 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
860 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 877 SND_SOC_DAPM_PRE_PMD),
861 878
862SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0, 879SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
863 NULL, 0), 880 NULL, 0),
864SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0, 881SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
865 NULL, 0), 882 NULL, 0),
866 883
884SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
885 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
886SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
867}; 887};
868 888
869static const struct snd_soc_dapm_route intercon[] = { 889static const struct snd_soc_dapm_route intercon[] = {
@@ -909,7 +929,19 @@ static const struct snd_soc_dapm_route intercon[] = {
909 { "Right Input PGA", NULL, "Right Input Mode Mux" }, 929 { "Right Input PGA", NULL, "Right Input Mode Mux" },
910 930
911 { "ADCL", NULL, "Left Input PGA" }, 931 { "ADCL", NULL, "Left Input PGA" },
932 { "ADCL", NULL, "CLK_DSP" },
912 { "ADCR", NULL, "Right Input PGA" }, 933 { "ADCR", NULL, "Right Input PGA" },
934 { "ADCR", NULL, "CLK_DSP" },
935
936 { "DACL Sidetone", "Left", "ADCL" },
937 { "DACL Sidetone", "Right", "ADCR" },
938 { "DACR Sidetone", "Left", "ADCL" },
939 { "DACR Sidetone", "Right", "ADCR" },
940
941 { "DACL", NULL, "DACL Sidetone" },
942 { "DACL", NULL, "CLK_DSP" },
943 { "DACR", NULL, "DACR Sidetone" },
944 { "DACR", NULL, "CLK_DSP" },
913 945
914 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" }, 946 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
915 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" }, 947 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
@@ -951,6 +983,11 @@ static const struct snd_soc_dapm_route intercon[] = {
951 983
952 { "ROP", NULL, "Right Speaker PGA" }, 984 { "ROP", NULL, "Right Speaker PGA" },
953 { "RON", NULL, "Right Speaker PGA" }, 985 { "RON", NULL, "Right Speaker PGA" },
986
987 { "Left Headphone Output PGA", NULL, "Charge Pump" },
988 { "Right Headphone Output PGA", NULL, "Charge Pump" },
989 { "Left Line Output PGA", NULL, "Charge Pump" },
990 { "Right Line Output PGA", NULL, "Charge Pump" },
954}; 991};
955 992
956static int wm8903_add_widgets(struct snd_soc_codec *codec) 993static int wm8903_add_widgets(struct snd_soc_codec *codec)
@@ -985,6 +1022,11 @@ static int wm8903_set_bias_level(struct snd_soc_codec *codec,
985 wm8903_write(codec, WM8903_CLOCK_RATES_2, 1022 wm8903_write(codec, WM8903_CLOCK_RATES_2,
986 WM8903_CLK_SYS_ENA); 1023 WM8903_CLK_SYS_ENA);
987 1024
1025 /* Change DC servo dither level in startup sequence */
1026 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
1027 wm8903_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
1028 wm8903_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
1029
988 wm8903_run_sequence(codec, 0); 1030 wm8903_run_sequence(codec, 0);
989 wm8903_sync_reg_cache(codec, codec->reg_cache); 1031 wm8903_sync_reg_cache(codec, codec->reg_cache);
990 1032
@@ -1277,14 +1319,8 @@ static int wm8903_startup(struct snd_pcm_substream *substream,
1277 if (wm8903->master_substream) { 1319 if (wm8903->master_substream) {
1278 master_runtime = wm8903->master_substream->runtime; 1320 master_runtime = wm8903->master_substream->runtime;
1279 1321
1280 dev_dbg(&i2c->dev, "Constraining to %d bits at %dHz\n", 1322 dev_dbg(&i2c->dev, "Constraining to %d bits\n",
1281 master_runtime->sample_bits, 1323 master_runtime->sample_bits);
1282 master_runtime->rate);
1283
1284 snd_pcm_hw_constraint_minmax(substream->runtime,
1285 SNDRV_PCM_HW_PARAM_RATE,
1286 master_runtime->rate,
1287 master_runtime->rate);
1288 1324
1289 snd_pcm_hw_constraint_minmax(substream->runtime, 1325 snd_pcm_hw_constraint_minmax(substream->runtime,
1290 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 1326 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
@@ -1523,6 +1559,7 @@ struct snd_soc_dai wm8903_dai = {
1523 .formats = WM8903_FORMATS, 1559 .formats = WM8903_FORMATS,
1524 }, 1560 },
1525 .ops = &wm8903_dai_ops, 1561 .ops = &wm8903_dai_ops,
1562 .symmetric_rates = 1,
1526}; 1563};
1527EXPORT_SYMBOL_GPL(wm8903_dai); 1564EXPORT_SYMBOL_GPL(wm8903_dai);
1528 1565
diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c
new file mode 100644
index 000000000000..b8e17d6bc1f7
--- /dev/null
+++ b/sound/soc/codecs/wm8940.c
@@ -0,0 +1,955 @@
1/*
2 * wm8940.c -- WM8940 ALSA Soc Audio driver
3 *
4 * Author: Jonathan Cameron <jic23@cam.ac.uk>
5 *
6 * Based on wm8510.c
7 * Copyright 2006 Wolfson Microelectronics PLC.
8 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * Not currently handled:
15 * Notch filter control
16 * AUXMode (inverting vs mixer)
17 * No means to obtain current gain if alc enabled.
18 * No use made of gpio
19 * Fast VMID discharge for power down
20 * Soft Start
21 * DLR and ALR Swaps not enabled
22 * Digital Sidetone not supported
23 */
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/kernel.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/pm.h>
30#include <linux/i2c.h>
31#include <linux/platform_device.h>
32#include <linux/spi/spi.h>
33#include <sound/core.h>
34#include <sound/pcm.h>
35#include <sound/pcm_params.h>
36#include <sound/soc.h>
37#include <sound/soc-dapm.h>
38#include <sound/initval.h>
39#include <sound/tlv.h>
40
41#include "wm8940.h"
42
43struct wm8940_priv {
44 unsigned int sysclk;
45 u16 reg_cache[WM8940_CACHEREGNUM];
46 struct snd_soc_codec codec;
47};
48
49static u16 wm8940_reg_defaults[] = {
50 0x8940, /* Soft Reset */
51 0x0000, /* Power 1 */
52 0x0000, /* Power 2 */
53 0x0000, /* Power 3 */
54 0x0010, /* Interface Control */
55 0x0000, /* Companding Control */
56 0x0140, /* Clock Control */
57 0x0000, /* Additional Controls */
58 0x0000, /* GPIO Control */
59 0x0002, /* Auto Increment Control */
60 0x0000, /* DAC Control */
61 0x00FF, /* DAC Volume */
62 0,
63 0,
64 0x0100, /* ADC Control */
65 0x00FF, /* ADC Volume */
66 0x0000, /* Notch Filter 1 Control 1 */
67 0x0000, /* Notch Filter 1 Control 2 */
68 0x0000, /* Notch Filter 2 Control 1 */
69 0x0000, /* Notch Filter 2 Control 2 */
70 0x0000, /* Notch Filter 3 Control 1 */
71 0x0000, /* Notch Filter 3 Control 2 */
72 0x0000, /* Notch Filter 4 Control 1 */
73 0x0000, /* Notch Filter 4 Control 2 */
74 0x0032, /* DAC Limit Control 1 */
75 0x0000, /* DAC Limit Control 2 */
76 0,
77 0,
78 0,
79 0,
80 0,
81 0,
82 0x0038, /* ALC Control 1 */
83 0x000B, /* ALC Control 2 */
84 0x0032, /* ALC Control 3 */
85 0x0000, /* Noise Gate */
86 0x0041, /* PLLN */
87 0x000C, /* PLLK1 */
88 0x0093, /* PLLK2 */
89 0x00E9, /* PLLK3 */
90 0,
91 0,
92 0x0030, /* ALC Control 4 */
93 0,
94 0x0002, /* Input Control */
95 0x0050, /* PGA Gain */
96 0,
97 0x0002, /* ADC Boost Control */
98 0,
99 0x0002, /* Output Control */
100 0x0000, /* Speaker Mixer Control */
101 0,
102 0,
103 0,
104 0x0079, /* Speaker Volume */
105 0,
106 0x0000, /* Mono Mixer Control */
107};
108
109static inline unsigned int wm8940_read_reg_cache(struct snd_soc_codec *codec,
110 unsigned int reg)
111{
112 u16 *cache = codec->reg_cache;
113
114 if (reg >= ARRAY_SIZE(wm8940_reg_defaults))
115 return -1;
116
117 return cache[reg];
118}
119
120static inline int wm8940_write_reg_cache(struct snd_soc_codec *codec,
121 u16 reg, unsigned int value)
122{
123 u16 *cache = codec->reg_cache;
124
125 if (reg >= ARRAY_SIZE(wm8940_reg_defaults))
126 return -1;
127
128 cache[reg] = value;
129
130 return 0;
131}
132
133static int wm8940_write(struct snd_soc_codec *codec, unsigned int reg,
134 unsigned int value)
135{
136 int ret;
137 u8 data[3] = { reg,
138 (value & 0xff00) >> 8,
139 (value & 0x00ff)
140 };
141
142 wm8940_write_reg_cache(codec, reg, value);
143
144 ret = codec->hw_write(codec->control_data, data, 3);
145
146 if (ret < 0)
147 return ret;
148 else if (ret != 3)
149 return -EIO;
150 return 0;
151}
152
153static const char *wm8940_companding[] = { "Off", "NC", "u-law", "A-law" };
154static const struct soc_enum wm8940_adc_companding_enum
155= SOC_ENUM_SINGLE(WM8940_COMPANDINGCTL, 1, 4, wm8940_companding);
156static const struct soc_enum wm8940_dac_companding_enum
157= SOC_ENUM_SINGLE(WM8940_COMPANDINGCTL, 3, 4, wm8940_companding);
158
159static const char *wm8940_alc_mode_text[] = {"ALC", "Limiter"};
160static const struct soc_enum wm8940_alc_mode_enum
161= SOC_ENUM_SINGLE(WM8940_ALC3, 8, 2, wm8940_alc_mode_text);
162
163static const char *wm8940_mic_bias_level_text[] = {"0.9", "0.65"};
164static const struct soc_enum wm8940_mic_bias_level_enum
165= SOC_ENUM_SINGLE(WM8940_INPUTCTL, 8, 2, wm8940_mic_bias_level_text);
166
167static const char *wm8940_filter_mode_text[] = {"Audio", "Application"};
168static const struct soc_enum wm8940_filter_mode_enum
169= SOC_ENUM_SINGLE(WM8940_ADC, 7, 2, wm8940_filter_mode_text);
170
171static DECLARE_TLV_DB_SCALE(wm8940_spk_vol_tlv, -5700, 100, 1);
172static DECLARE_TLV_DB_SCALE(wm8940_att_tlv, -1000, 1000, 0);
173static DECLARE_TLV_DB_SCALE(wm8940_pga_vol_tlv, -1200, 75, 0);
174static DECLARE_TLV_DB_SCALE(wm8940_alc_min_tlv, -1200, 600, 0);
175static DECLARE_TLV_DB_SCALE(wm8940_alc_max_tlv, 675, 600, 0);
176static DECLARE_TLV_DB_SCALE(wm8940_alc_tar_tlv, -2250, 50, 0);
177static DECLARE_TLV_DB_SCALE(wm8940_lim_boost_tlv, 0, 100, 0);
178static DECLARE_TLV_DB_SCALE(wm8940_lim_thresh_tlv, -600, 100, 0);
179static DECLARE_TLV_DB_SCALE(wm8940_adc_tlv, -12750, 50, 1);
180static DECLARE_TLV_DB_SCALE(wm8940_capture_boost_vol_tlv, 0, 2000, 0);
181
182static const struct snd_kcontrol_new wm8940_snd_controls[] = {
183 SOC_SINGLE("Digital Loopback Switch", WM8940_COMPANDINGCTL,
184 6, 1, 0),
185 SOC_ENUM("DAC Companding", wm8940_dac_companding_enum),
186 SOC_ENUM("ADC Companding", wm8940_adc_companding_enum),
187
188 SOC_ENUM("ALC Mode", wm8940_alc_mode_enum),
189 SOC_SINGLE("ALC Switch", WM8940_ALC1, 8, 1, 0),
190 SOC_SINGLE_TLV("ALC Capture Max Gain", WM8940_ALC1,
191 3, 7, 1, wm8940_alc_max_tlv),
192 SOC_SINGLE_TLV("ALC Capture Min Gain", WM8940_ALC1,
193 0, 7, 0, wm8940_alc_min_tlv),
194 SOC_SINGLE_TLV("ALC Capture Target", WM8940_ALC2,
195 0, 14, 0, wm8940_alc_tar_tlv),
196 SOC_SINGLE("ALC Capture Hold", WM8940_ALC2, 4, 10, 0),
197 SOC_SINGLE("ALC Capture Decay", WM8940_ALC3, 4, 10, 0),
198 SOC_SINGLE("ALC Capture Attach", WM8940_ALC3, 0, 10, 0),
199 SOC_SINGLE("ALC ZC Switch", WM8940_ALC4, 1, 1, 0),
200 SOC_SINGLE("ALC Capture Noise Gate Switch", WM8940_NOISEGATE,
201 3, 1, 0),
202 SOC_SINGLE("ALC Capture Noise Gate Threshold", WM8940_NOISEGATE,
203 0, 7, 0),
204
205 SOC_SINGLE("DAC Playback Limiter Switch", WM8940_DACLIM1, 8, 1, 0),
206 SOC_SINGLE("DAC Playback Limiter Attack", WM8940_DACLIM1, 0, 9, 0),
207 SOC_SINGLE("DAC Playback Limiter Decay", WM8940_DACLIM1, 4, 11, 0),
208 SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8940_DACLIM2,
209 4, 9, 1, wm8940_lim_thresh_tlv),
210 SOC_SINGLE_TLV("DAC Playback Limiter Boost", WM8940_DACLIM2,
211 0, 12, 0, wm8940_lim_boost_tlv),
212
213 SOC_SINGLE("Capture PGA ZC Switch", WM8940_PGAGAIN, 7, 1, 0),
214 SOC_SINGLE_TLV("Capture PGA Volume", WM8940_PGAGAIN,
215 0, 63, 0, wm8940_pga_vol_tlv),
216 SOC_SINGLE_TLV("Digital Playback Volume", WM8940_DACVOL,
217 0, 255, 0, wm8940_adc_tlv),
218 SOC_SINGLE_TLV("Digital Capture Volume", WM8940_ADCVOL,
219 0, 255, 0, wm8940_adc_tlv),
220 SOC_ENUM("Mic Bias Level", wm8940_mic_bias_level_enum),
221 SOC_SINGLE_TLV("Capture Boost Volue", WM8940_ADCBOOST,
222 8, 1, 0, wm8940_capture_boost_vol_tlv),
223 SOC_SINGLE_TLV("Speaker Playback Volume", WM8940_SPKVOL,
224 0, 63, 0, wm8940_spk_vol_tlv),
225 SOC_SINGLE("Speaker Playback Switch", WM8940_SPKVOL, 6, 1, 1),
226
227 SOC_SINGLE_TLV("Speaker Mixer Line Bypass Volume", WM8940_SPKVOL,
228 8, 1, 1, wm8940_att_tlv),
229 SOC_SINGLE("Speaker Playback ZC Switch", WM8940_SPKVOL, 7, 1, 0),
230
231 SOC_SINGLE("Mono Out Switch", WM8940_MONOMIX, 6, 1, 1),
232 SOC_SINGLE_TLV("Mono Mixer Line Bypass Volume", WM8940_MONOMIX,
233 7, 1, 1, wm8940_att_tlv),
234
235 SOC_SINGLE("High Pass Filter Switch", WM8940_ADC, 8, 1, 0),
236 SOC_ENUM("High Pass Filter Mode", wm8940_filter_mode_enum),
237 SOC_SINGLE("High Pass Filter Cut Off", WM8940_ADC, 4, 7, 0),
238 SOC_SINGLE("ADC Inversion Switch", WM8940_ADC, 0, 1, 0),
239 SOC_SINGLE("DAC Inversion Switch", WM8940_DAC, 0, 1, 0),
240 SOC_SINGLE("DAC Auto Mute Switch", WM8940_DAC, 2, 1, 0),
241 SOC_SINGLE("ZC Timeout Clock Switch", WM8940_ADDCNTRL, 0, 1, 0),
242};
243
244static const struct snd_kcontrol_new wm8940_speaker_mixer_controls[] = {
245 SOC_DAPM_SINGLE("Line Bypass Switch", WM8940_SPKMIX, 1, 1, 0),
246 SOC_DAPM_SINGLE("Aux Playback Switch", WM8940_SPKMIX, 5, 1, 0),
247 SOC_DAPM_SINGLE("PCM Playback Switch", WM8940_SPKMIX, 0, 1, 0),
248};
249
250static const struct snd_kcontrol_new wm8940_mono_mixer_controls[] = {
251 SOC_DAPM_SINGLE("Line Bypass Switch", WM8940_MONOMIX, 1, 1, 0),
252 SOC_DAPM_SINGLE("Aux Playback Switch", WM8940_MONOMIX, 2, 1, 0),
253 SOC_DAPM_SINGLE("PCM Playback Switch", WM8940_MONOMIX, 0, 1, 0),
254};
255
256static DECLARE_TLV_DB_SCALE(wm8940_boost_vol_tlv, -1500, 300, 1);
257static const struct snd_kcontrol_new wm8940_input_boost_controls[] = {
258 SOC_DAPM_SINGLE("Mic PGA Switch", WM8940_PGAGAIN, 6, 1, 1),
259 SOC_DAPM_SINGLE_TLV("Aux Volume", WM8940_ADCBOOST,
260 0, 7, 0, wm8940_boost_vol_tlv),
261 SOC_DAPM_SINGLE_TLV("Mic Volume", WM8940_ADCBOOST,
262 4, 7, 0, wm8940_boost_vol_tlv),
263};
264
265static const struct snd_kcontrol_new wm8940_micpga_controls[] = {
266 SOC_DAPM_SINGLE("AUX Switch", WM8940_INPUTCTL, 2, 1, 0),
267 SOC_DAPM_SINGLE("MICP Switch", WM8940_INPUTCTL, 0, 1, 0),
268 SOC_DAPM_SINGLE("MICN Switch", WM8940_INPUTCTL, 1, 1, 0),
269};
270
271static const struct snd_soc_dapm_widget wm8940_dapm_widgets[] = {
272 SND_SOC_DAPM_MIXER("Speaker Mixer", WM8940_POWER3, 2, 0,
273 &wm8940_speaker_mixer_controls[0],
274 ARRAY_SIZE(wm8940_speaker_mixer_controls)),
275 SND_SOC_DAPM_MIXER("Mono Mixer", WM8940_POWER3, 3, 0,
276 &wm8940_mono_mixer_controls[0],
277 ARRAY_SIZE(wm8940_mono_mixer_controls)),
278 SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8940_POWER3, 0, 0),
279
280 SND_SOC_DAPM_PGA("SpkN Out", WM8940_POWER3, 5, 0, NULL, 0),
281 SND_SOC_DAPM_PGA("SpkP Out", WM8940_POWER3, 6, 0, NULL, 0),
282 SND_SOC_DAPM_PGA("Mono Out", WM8940_POWER3, 7, 0, NULL, 0),
283 SND_SOC_DAPM_OUTPUT("MONOOUT"),
284 SND_SOC_DAPM_OUTPUT("SPKOUTP"),
285 SND_SOC_DAPM_OUTPUT("SPKOUTN"),
286
287 SND_SOC_DAPM_PGA("Aux Input", WM8940_POWER1, 6, 0, NULL, 0),
288 SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8940_POWER2, 0, 0),
289 SND_SOC_DAPM_MIXER("Mic PGA", WM8940_POWER2, 2, 0,
290 &wm8940_micpga_controls[0],
291 ARRAY_SIZE(wm8940_micpga_controls)),
292 SND_SOC_DAPM_MIXER("Boost Mixer", WM8940_POWER2, 4, 0,
293 &wm8940_input_boost_controls[0],
294 ARRAY_SIZE(wm8940_input_boost_controls)),
295 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8940_POWER1, 4, 0),
296
297 SND_SOC_DAPM_INPUT("MICN"),
298 SND_SOC_DAPM_INPUT("MICP"),
299 SND_SOC_DAPM_INPUT("AUX"),
300};
301
302static const struct snd_soc_dapm_route audio_map[] = {
303 /* Mono output mixer */
304 {"Mono Mixer", "PCM Playback Switch", "DAC"},
305 {"Mono Mixer", "Aux Playback Switch", "Aux Input"},
306 {"Mono Mixer", "Line Bypass Switch", "Boost Mixer"},
307
308 /* Speaker output mixer */
309 {"Speaker Mixer", "PCM Playback Switch", "DAC"},
310 {"Speaker Mixer", "Aux Playback Switch", "Aux Input"},
311 {"Speaker Mixer", "Line Bypass Switch", "Boost Mixer"},
312
313 /* Outputs */
314 {"Mono Out", NULL, "Mono Mixer"},
315 {"MONOOUT", NULL, "Mono Out"},
316 {"SpkN Out", NULL, "Speaker Mixer"},
317 {"SpkP Out", NULL, "Speaker Mixer"},
318 {"SPKOUTN", NULL, "SpkN Out"},
319 {"SPKOUTP", NULL, "SpkP Out"},
320
321 /* Microphone PGA */
322 {"Mic PGA", "MICN Switch", "MICN"},
323 {"Mic PGA", "MICP Switch", "MICP"},
324 {"Mic PGA", "AUX Switch", "AUX"},
325
326 /* Boost Mixer */
327 {"Boost Mixer", "Mic PGA Switch", "Mic PGA"},
328 {"Boost Mixer", "Mic Volume", "MICP"},
329 {"Boost Mixer", "Aux Volume", "Aux Input"},
330
331 {"ADC", NULL, "Boost Mixer"},
332};
333
334static int wm8940_add_widgets(struct snd_soc_codec *codec)
335{
336 int ret;
337
338 ret = snd_soc_dapm_new_controls(codec, wm8940_dapm_widgets,
339 ARRAY_SIZE(wm8940_dapm_widgets));
340 if (ret)
341 goto error_ret;
342 ret = snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
343 if (ret)
344 goto error_ret;
345 ret = snd_soc_dapm_new_widgets(codec);
346
347error_ret:
348 return ret;
349}
350
351#define wm8940_reset(c) wm8940_write(c, WM8940_SOFTRESET, 0);
352
353static int wm8940_set_dai_fmt(struct snd_soc_dai *codec_dai,
354 unsigned int fmt)
355{
356 struct snd_soc_codec *codec = codec_dai->codec;
357 u16 iface = wm8940_read_reg_cache(codec, WM8940_IFACE) & 0xFE67;
358 u16 clk = wm8940_read_reg_cache(codec, WM8940_CLOCK) & 0x1fe;
359
360 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
361 case SND_SOC_DAIFMT_CBM_CFM:
362 clk |= 1;
363 break;
364 case SND_SOC_DAIFMT_CBS_CFS:
365 break;
366 default:
367 return -EINVAL;
368 }
369 wm8940_write(codec, WM8940_CLOCK, clk);
370
371 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
372 case SND_SOC_DAIFMT_I2S:
373 iface |= (2 << 3);
374 break;
375 case SND_SOC_DAIFMT_LEFT_J:
376 iface |= (1 << 3);
377 break;
378 case SND_SOC_DAIFMT_RIGHT_J:
379 break;
380 case SND_SOC_DAIFMT_DSP_A:
381 iface |= (3 << 3);
382 break;
383 case SND_SOC_DAIFMT_DSP_B:
384 iface |= (3 << 3) | (1 << 7);
385 break;
386 }
387
388 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
389 case SND_SOC_DAIFMT_NB_NF:
390 break;
391 case SND_SOC_DAIFMT_NB_IF:
392 iface |= (1 << 7);
393 break;
394 case SND_SOC_DAIFMT_IB_NF:
395 iface |= (1 << 8);
396 break;
397 case SND_SOC_DAIFMT_IB_IF:
398 iface |= (1 << 8) | (1 << 7);
399 break;
400 }
401
402 wm8940_write(codec, WM8940_IFACE, iface);
403
404 return 0;
405}
406
407static int wm8940_i2s_hw_params(struct snd_pcm_substream *substream,
408 struct snd_pcm_hw_params *params,
409 struct snd_soc_dai *dai)
410{
411 struct snd_soc_pcm_runtime *rtd = substream->private_data;
412 struct snd_soc_device *socdev = rtd->socdev;
413 struct snd_soc_codec *codec = socdev->card->codec;
414 u16 iface = wm8940_read_reg_cache(codec, WM8940_IFACE) & 0xFD9F;
415 u16 addcntrl = wm8940_read_reg_cache(codec, WM8940_ADDCNTRL) & 0xFFF1;
416 u16 companding = wm8940_read_reg_cache(codec,
417 WM8940_COMPANDINGCTL) & 0xFFDF;
418 int ret;
419
420 /* LoutR control */
421 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
422 && params_channels(params) == 2)
423 iface |= (1 << 9);
424
425 switch (params_rate(params)) {
426 case SNDRV_PCM_RATE_8000:
427 addcntrl |= (0x5 << 1);
428 break;
429 case SNDRV_PCM_RATE_11025:
430 addcntrl |= (0x4 << 1);
431 break;
432 case SNDRV_PCM_RATE_16000:
433 addcntrl |= (0x3 << 1);
434 break;
435 case SNDRV_PCM_RATE_22050:
436 addcntrl |= (0x2 << 1);
437 break;
438 case SNDRV_PCM_RATE_32000:
439 addcntrl |= (0x1 << 1);
440 break;
441 case SNDRV_PCM_RATE_44100:
442 case SNDRV_PCM_RATE_48000:
443 break;
444 }
445 ret = wm8940_write(codec, WM8940_ADDCNTRL, addcntrl);
446 if (ret)
447 goto error_ret;
448
449 switch (params_format(params)) {
450 case SNDRV_PCM_FORMAT_S8:
451 companding = companding | (1 << 5);
452 break;
453 case SNDRV_PCM_FORMAT_S16_LE:
454 break;
455 case SNDRV_PCM_FORMAT_S20_3LE:
456 iface |= (1 << 5);
457 break;
458 case SNDRV_PCM_FORMAT_S24_LE:
459 iface |= (2 << 5);
460 break;
461 case SNDRV_PCM_FORMAT_S32_LE:
462 iface |= (3 << 5);
463 break;
464 }
465 ret = wm8940_write(codec, WM8940_COMPANDINGCTL, companding);
466 if (ret)
467 goto error_ret;
468 ret = wm8940_write(codec, WM8940_IFACE, iface);
469
470error_ret:
471 return ret;
472}
473
474static int wm8940_mute(struct snd_soc_dai *dai, int mute)
475{
476 struct snd_soc_codec *codec = dai->codec;
477 u16 mute_reg = wm8940_read_reg_cache(codec, WM8940_DAC) & 0xffbf;
478
479 if (mute)
480 mute_reg |= 0x40;
481
482 return wm8940_write(codec, WM8940_DAC, mute_reg);
483}
484
485static int wm8940_set_bias_level(struct snd_soc_codec *codec,
486 enum snd_soc_bias_level level)
487{
488 u16 val;
489 u16 pwr_reg = wm8940_read_reg_cache(codec, WM8940_POWER1) & 0x1F0;
490 int ret = 0;
491
492 switch (level) {
493 case SND_SOC_BIAS_ON:
494 /* ensure bufioen and biasen */
495 pwr_reg |= (1 << 2) | (1 << 3);
496 /* Enable thermal shutdown */
497 val = wm8940_read_reg_cache(codec, WM8940_OUTPUTCTL);
498 ret = wm8940_write(codec, WM8940_OUTPUTCTL, val | 0x2);
499 if (ret)
500 break;
501 /* set vmid to 75k */
502 ret = wm8940_write(codec, WM8940_POWER1, pwr_reg | 0x1);
503 break;
504 case SND_SOC_BIAS_PREPARE:
505 /* ensure bufioen and biasen */
506 pwr_reg |= (1 << 2) | (1 << 3);
507 ret = wm8940_write(codec, WM8940_POWER1, pwr_reg | 0x1);
508 break;
509 case SND_SOC_BIAS_STANDBY:
510 /* ensure bufioen and biasen */
511 pwr_reg |= (1 << 2) | (1 << 3);
512 /* set vmid to 300k for standby */
513 ret = wm8940_write(codec, WM8940_POWER1, pwr_reg | 0x2);
514 break;
515 case SND_SOC_BIAS_OFF:
516 ret = wm8940_write(codec, WM8940_POWER1, pwr_reg);
517 break;
518 }
519
520 return ret;
521}
522
523struct pll_ {
524 unsigned int pre_scale:2;
525 unsigned int n:4;
526 unsigned int k;
527};
528
529static struct pll_ pll_div;
530
531/* The size in bits of the pll divide multiplied by 10
532 * to allow rounding later */
533#define FIXED_PLL_SIZE ((1 << 24) * 10)
534static void pll_factors(unsigned int target, unsigned int source)
535{
536 unsigned long long Kpart;
537 unsigned int K, Ndiv, Nmod;
538 /* The left shift ist to avoid accuracy loss when right shifting */
539 Ndiv = target / source;
540
541 if (Ndiv > 12) {
542 source <<= 1;
543 /* Multiply by 2 */
544 pll_div.pre_scale = 0;
545 Ndiv = target / source;
546 } else if (Ndiv < 3) {
547 source >>= 2;
548 /* Divide by 4 */
549 pll_div.pre_scale = 3;
550 Ndiv = target / source;
551 } else if (Ndiv < 6) {
552 source >>= 1;
553 /* divide by 2 */
554 pll_div.pre_scale = 2;
555 Ndiv = target / source;
556 } else
557 pll_div.pre_scale = 1;
558
559 if ((Ndiv < 6) || (Ndiv > 12))
560 printk(KERN_WARNING
561 "WM8940 N value %d outwith recommended range!d\n",
562 Ndiv);
563
564 pll_div.n = Ndiv;
565 Nmod = target % source;
566 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
567
568 do_div(Kpart, source);
569
570 K = Kpart & 0xFFFFFFFF;
571
572 /* Check if we need to round */
573 if ((K % 10) >= 5)
574 K += 5;
575
576 /* Move down to proper range now rounding is done */
577 K /= 10;
578
579 pll_div.k = K;
580}
581
582/* Untested at the moment */
583static int wm8940_set_dai_pll(struct snd_soc_dai *codec_dai,
584 int pll_id, unsigned int freq_in, unsigned int freq_out)
585{
586 struct snd_soc_codec *codec = codec_dai->codec;
587 u16 reg;
588
589 /* Turn off PLL */
590 reg = wm8940_read_reg_cache(codec, WM8940_POWER1);
591 wm8940_write(codec, WM8940_POWER1, reg & 0x1df);
592
593 if (freq_in == 0 || freq_out == 0) {
594 /* Clock CODEC directly from MCLK */
595 reg = wm8940_read_reg_cache(codec, WM8940_CLOCK);
596 wm8940_write(codec, WM8940_CLOCK, reg & 0x0ff);
597 /* Pll power down */
598 wm8940_write(codec, WM8940_PLLN, (1 << 7));
599 return 0;
600 }
601
602 /* Pll is followed by a frequency divide by 4 */
603 pll_factors(freq_out*4, freq_in);
604 if (pll_div.k)
605 wm8940_write(codec, WM8940_PLLN,
606 (pll_div.pre_scale << 4) | pll_div.n | (1 << 6));
607 else /* No factional component */
608 wm8940_write(codec, WM8940_PLLN,
609 (pll_div.pre_scale << 4) | pll_div.n);
610 wm8940_write(codec, WM8940_PLLK1, pll_div.k >> 18);
611 wm8940_write(codec, WM8940_PLLK2, (pll_div.k >> 9) & 0x1ff);
612 wm8940_write(codec, WM8940_PLLK3, pll_div.k & 0x1ff);
613 /* Enable the PLL */
614 reg = wm8940_read_reg_cache(codec, WM8940_POWER1);
615 wm8940_write(codec, WM8940_POWER1, reg | 0x020);
616
617 /* Run CODEC from PLL instead of MCLK */
618 reg = wm8940_read_reg_cache(codec, WM8940_CLOCK);
619 wm8940_write(codec, WM8940_CLOCK, reg | 0x100);
620
621 return 0;
622}
623
624static int wm8940_set_dai_sysclk(struct snd_soc_dai *codec_dai,
625 int clk_id, unsigned int freq, int dir)
626{
627 struct snd_soc_codec *codec = codec_dai->codec;
628 struct wm8940_priv *wm8940 = codec->private_data;
629
630 switch (freq) {
631 case 11289600:
632 case 12000000:
633 case 12288000:
634 case 16934400:
635 case 18432000:
636 wm8940->sysclk = freq;
637 return 0;
638 }
639 return -EINVAL;
640}
641
642static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
643 int div_id, int div)
644{
645 struct snd_soc_codec *codec = codec_dai->codec;
646 u16 reg;
647 int ret = 0;
648
649 switch (div_id) {
650 case WM8940_BCLKDIV:
651 reg = wm8940_read_reg_cache(codec, WM8940_CLOCK) & 0xFFEF3;
652 ret = wm8940_write(codec, WM8940_CLOCK, reg | (div << 2));
653 break;
654 case WM8940_MCLKDIV:
655 reg = wm8940_read_reg_cache(codec, WM8940_CLOCK) & 0xFF1F;
656 ret = wm8940_write(codec, WM8940_CLOCK, reg | (div << 5));
657 break;
658 case WM8940_OPCLKDIV:
659 reg = wm8940_read_reg_cache(codec, WM8940_ADDCNTRL) & 0xFFCF;
660 ret = wm8940_write(codec, WM8940_ADDCNTRL, reg | (div << 4));
661 break;
662 }
663 return ret;
664}
665
666#define WM8940_RATES SNDRV_PCM_RATE_8000_48000
667
668#define WM8940_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
669 SNDRV_PCM_FMTBIT_S16_LE | \
670 SNDRV_PCM_FMTBIT_S20_3LE | \
671 SNDRV_PCM_FMTBIT_S24_LE | \
672 SNDRV_PCM_FMTBIT_S32_LE)
673
674static struct snd_soc_dai_ops wm8940_dai_ops = {
675 .hw_params = wm8940_i2s_hw_params,
676 .set_sysclk = wm8940_set_dai_sysclk,
677 .digital_mute = wm8940_mute,
678 .set_fmt = wm8940_set_dai_fmt,
679 .set_clkdiv = wm8940_set_dai_clkdiv,
680 .set_pll = wm8940_set_dai_pll,
681};
682
683struct snd_soc_dai wm8940_dai = {
684 .name = "WM8940",
685 .playback = {
686 .stream_name = "Playback",
687 .channels_min = 1,
688 .channels_max = 2,
689 .rates = WM8940_RATES,
690 .formats = WM8940_FORMATS,
691 },
692 .capture = {
693 .stream_name = "Capture",
694 .channels_min = 1,
695 .channels_max = 2,
696 .rates = WM8940_RATES,
697 .formats = WM8940_FORMATS,
698 },
699 .ops = &wm8940_dai_ops,
700 .symmetric_rates = 1,
701};
702EXPORT_SYMBOL_GPL(wm8940_dai);
703
704static int wm8940_suspend(struct platform_device *pdev, pm_message_t state)
705{
706 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
707 struct snd_soc_codec *codec = socdev->card->codec;
708
709 return wm8940_set_bias_level(codec, SND_SOC_BIAS_OFF);
710}
711
712static int wm8940_resume(struct platform_device *pdev)
713{
714 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
715 struct snd_soc_codec *codec = socdev->card->codec;
716 int i;
717 int ret;
718 u8 data[3];
719 u16 *cache = codec->reg_cache;
720
721 /* Sync reg_cache with the hardware
722 * Could use auto incremented writes to speed this up
723 */
724 for (i = 0; i < ARRAY_SIZE(wm8940_reg_defaults); i++) {
725 data[0] = i;
726 data[1] = (cache[i] & 0xFF00) >> 8;
727 data[2] = cache[i] & 0x00FF;
728 ret = codec->hw_write(codec->control_data, data, 3);
729 if (ret < 0)
730 goto error_ret;
731 else if (ret != 3) {
732 ret = -EIO;
733 goto error_ret;
734 }
735 }
736 ret = wm8940_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
737 if (ret)
738 goto error_ret;
739 ret = wm8940_set_bias_level(codec, codec->suspend_bias_level);
740
741error_ret:
742 return ret;
743}
744
745static struct snd_soc_codec *wm8940_codec;
746
747static int wm8940_probe(struct platform_device *pdev)
748{
749 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
750 struct snd_soc_codec *codec;
751
752 int ret = 0;
753
754 if (wm8940_codec == NULL) {
755 dev_err(&pdev->dev, "Codec device not registered\n");
756 return -ENODEV;
757 }
758
759 socdev->card->codec = wm8940_codec;
760 codec = wm8940_codec;
761
762 mutex_init(&codec->mutex);
763 /* register pcms */
764 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
765 if (ret < 0) {
766 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
767 goto pcm_err;
768 }
769
770 ret = snd_soc_add_controls(codec, wm8940_snd_controls,
771 ARRAY_SIZE(wm8940_snd_controls));
772 if (ret)
773 goto error_free_pcms;
774 ret = wm8940_add_widgets(codec);
775 if (ret)
776 goto error_free_pcms;
777
778 ret = snd_soc_init_card(socdev);
779 if (ret < 0) {
780 dev_err(codec->dev, "failed to register card: %d\n", ret);
781 goto error_free_pcms;
782 }
783
784 return ret;
785
786error_free_pcms:
787 snd_soc_free_pcms(socdev);
788 snd_soc_dapm_free(socdev);
789pcm_err:
790 return ret;
791}
792
793static int wm8940_remove(struct platform_device *pdev)
794{
795 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
796
797 snd_soc_free_pcms(socdev);
798 snd_soc_dapm_free(socdev);
799
800 return 0;
801}
802
803struct snd_soc_codec_device soc_codec_dev_wm8940 = {
804 .probe = wm8940_probe,
805 .remove = wm8940_remove,
806 .suspend = wm8940_suspend,
807 .resume = wm8940_resume,
808};
809EXPORT_SYMBOL_GPL(soc_codec_dev_wm8940);
810
811static int wm8940_register(struct wm8940_priv *wm8940)
812{
813 struct wm8940_setup_data *pdata = wm8940->codec.dev->platform_data;
814 struct snd_soc_codec *codec = &wm8940->codec;
815 int ret;
816 u16 reg;
817 if (wm8940_codec) {
818 dev_err(codec->dev, "Another WM8940 is registered\n");
819 return -EINVAL;
820 }
821
822 INIT_LIST_HEAD(&codec->dapm_widgets);
823 INIT_LIST_HEAD(&codec->dapm_paths);
824
825 codec->private_data = wm8940;
826 codec->name = "WM8940";
827 codec->owner = THIS_MODULE;
828 codec->read = wm8940_read_reg_cache;
829 codec->write = wm8940_write;
830 codec->bias_level = SND_SOC_BIAS_OFF;
831 codec->set_bias_level = wm8940_set_bias_level;
832 codec->dai = &wm8940_dai;
833 codec->num_dai = 1;
834 codec->reg_cache_size = ARRAY_SIZE(wm8940_reg_defaults);
835 codec->reg_cache = &wm8940->reg_cache;
836
837 memcpy(codec->reg_cache, wm8940_reg_defaults,
838 sizeof(wm8940_reg_defaults));
839
840 ret = wm8940_reset(codec);
841 if (ret < 0) {
842 dev_err(codec->dev, "Failed to issue reset\n");
843 return ret;
844 }
845
846 wm8940_dai.dev = codec->dev;
847
848 wm8940_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
849
850 ret = wm8940_write(codec, WM8940_POWER1, 0x180);
851 if (ret < 0)
852 return ret;
853
854 if (!pdata)
855 dev_warn(codec->dev, "No platform data supplied\n");
856 else {
857 reg = wm8940_read_reg_cache(codec, WM8940_OUTPUTCTL);
858 ret = wm8940_write(codec, WM8940_OUTPUTCTL, reg | pdata->vroi);
859 if (ret < 0)
860 return ret;
861 }
862
863
864 wm8940_codec = codec;
865
866 ret = snd_soc_register_codec(codec);
867 if (ret) {
868 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
869 return ret;
870 }
871
872 ret = snd_soc_register_dai(&wm8940_dai);
873 if (ret) {
874 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
875 snd_soc_unregister_codec(codec);
876 return ret;
877 }
878
879 return 0;
880}
881
882static void wm8940_unregister(struct wm8940_priv *wm8940)
883{
884 wm8940_set_bias_level(&wm8940->codec, SND_SOC_BIAS_OFF);
885 snd_soc_unregister_dai(&wm8940_dai);
886 snd_soc_unregister_codec(&wm8940->codec);
887 kfree(wm8940);
888 wm8940_codec = NULL;
889}
890
891static int wm8940_i2c_probe(struct i2c_client *i2c,
892 const struct i2c_device_id *id)
893{
894 struct wm8940_priv *wm8940;
895 struct snd_soc_codec *codec;
896
897 wm8940 = kzalloc(sizeof *wm8940, GFP_KERNEL);
898 if (wm8940 == NULL)
899 return -ENOMEM;
900
901 codec = &wm8940->codec;
902 codec->hw_write = (hw_write_t)i2c_master_send;
903 i2c_set_clientdata(i2c, wm8940);
904 codec->control_data = i2c;
905 codec->dev = &i2c->dev;
906
907 return wm8940_register(wm8940);
908}
909
910static int __devexit wm8940_i2c_remove(struct i2c_client *client)
911{
912 struct wm8940_priv *wm8940 = i2c_get_clientdata(client);
913
914 wm8940_unregister(wm8940);
915
916 return 0;
917}
918
919static const struct i2c_device_id wm8940_i2c_id[] = {
920 { "wm8940", 0 },
921 { }
922};
923MODULE_DEVICE_TABLE(i2c, wm8940_i2c_id);
924
925static struct i2c_driver wm8940_i2c_driver = {
926 .driver = {
927 .name = "WM8940 I2C Codec",
928 .owner = THIS_MODULE,
929 },
930 .probe = wm8940_i2c_probe,
931 .remove = __devexit_p(wm8940_i2c_remove),
932 .id_table = wm8940_i2c_id,
933};
934
935static int __init wm8940_modinit(void)
936{
937 int ret;
938
939 ret = i2c_add_driver(&wm8940_i2c_driver);
940 if (ret)
941 printk(KERN_ERR "Failed to register WM8940 I2C driver: %d\n",
942 ret);
943 return ret;
944}
945module_init(wm8940_modinit);
946
947static void __exit wm8940_exit(void)
948{
949 i2c_del_driver(&wm8940_i2c_driver);
950}
951module_exit(wm8940_exit);
952
953MODULE_DESCRIPTION("ASoC WM8940 driver");
954MODULE_AUTHOR("Jonathan Cameron");
955MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8940.h b/sound/soc/codecs/wm8940.h
new file mode 100644
index 000000000000..8410eed3ef84
--- /dev/null
+++ b/sound/soc/codecs/wm8940.h
@@ -0,0 +1,104 @@
1/*
2 * wm8940.h -- WM8940 Soc Audio driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef _WM8940_H
10#define _WM8940_H
11
12struct wm8940_setup_data {
13 /* Vref to analogue output resistance */
14#define WM8940_VROI_1K 0
15#define WM8940_VROI_30K 1
16 unsigned int vroi:1;
17};
18extern struct snd_soc_dai wm8940_dai;
19extern struct snd_soc_codec_device soc_codec_dev_wm8940;
20
21/* WM8940 register space */
22#define WM8940_SOFTRESET 0x00
23#define WM8940_POWER1 0x01
24#define WM8940_POWER2 0x02
25#define WM8940_POWER3 0x03
26#define WM8940_IFACE 0x04
27#define WM8940_COMPANDINGCTL 0x05
28#define WM8940_CLOCK 0x06
29#define WM8940_ADDCNTRL 0x07
30#define WM8940_GPIO 0x08
31#define WM8940_CTLINT 0x09
32#define WM8940_DAC 0x0A
33#define WM8940_DACVOL 0x0B
34
35#define WM8940_ADC 0x0E
36#define WM8940_ADCVOL 0x0F
37#define WM8940_NOTCH1 0x10
38#define WM8940_NOTCH2 0x11
39#define WM8940_NOTCH3 0x12
40#define WM8940_NOTCH4 0x13
41#define WM8940_NOTCH5 0x14
42#define WM8940_NOTCH6 0x15
43#define WM8940_NOTCH7 0x16
44#define WM8940_NOTCH8 0x17
45#define WM8940_DACLIM1 0x18
46#define WM8940_DACLIM2 0x19
47
48#define WM8940_ALC1 0x20
49#define WM8940_ALC2 0x21
50#define WM8940_ALC3 0x22
51#define WM8940_NOISEGATE 0x23
52#define WM8940_PLLN 0x24
53#define WM8940_PLLK1 0x25
54#define WM8940_PLLK2 0x26
55#define WM8940_PLLK3 0x27
56
57#define WM8940_ALC4 0x2A
58
59#define WM8940_INPUTCTL 0x2C
60#define WM8940_PGAGAIN 0x2D
61
62#define WM8940_ADCBOOST 0x2F
63
64#define WM8940_OUTPUTCTL 0x31
65#define WM8940_SPKMIX 0x32
66
67#define WM8940_SPKVOL 0x36
68
69#define WM8940_MONOMIX 0x38
70
71#define WM8940_CACHEREGNUM 0x57
72
73
74/* Clock divider Id's */
75#define WM8940_BCLKDIV 0
76#define WM8940_MCLKDIV 1
77#define WM8940_OPCLKDIV 2
78
79/* MCLK clock dividers */
80#define WM8940_MCLKDIV_1 0
81#define WM8940_MCLKDIV_1_5 1
82#define WM8940_MCLKDIV_2 2
83#define WM8940_MCLKDIV_3 3
84#define WM8940_MCLKDIV_4 4
85#define WM8940_MCLKDIV_6 5
86#define WM8940_MCLKDIV_8 6
87#define WM8940_MCLKDIV_12 7
88
89/* BCLK clock dividers */
90#define WM8940_BCLKDIV_1 0
91#define WM8940_BCLKDIV_2 1
92#define WM8940_BCLKDIV_4 2
93#define WM8940_BCLKDIV_8 3
94#define WM8940_BCLKDIV_16 4
95#define WM8940_BCLKDIV_32 5
96
97/* PLL Out Dividers */
98#define WM8940_OPCLKDIV_1 0
99#define WM8940_OPCLKDIV_2 1
100#define WM8940_OPCLKDIV_3 2
101#define WM8940_OPCLKDIV_4 3
102
103#endif /* _WM8940_H */
104
diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c
new file mode 100644
index 000000000000..e224d8add170
--- /dev/null
+++ b/sound/soc/codecs/wm8960.c
@@ -0,0 +1,969 @@
1/*
2 * wm8960.c -- WM8960 ALSA SoC Audio driver
3 *
4 * Author: Liam Girdwood
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pm.h>
16#include <linux/i2c.h>
17#include <linux/platform_device.h>
18#include <sound/core.h>
19#include <sound/pcm.h>
20#include <sound/pcm_params.h>
21#include <sound/soc.h>
22#include <sound/soc-dapm.h>
23#include <sound/initval.h>
24#include <sound/tlv.h>
25
26#include "wm8960.h"
27
28#define AUDIO_NAME "wm8960"
29
30struct snd_soc_codec_device soc_codec_dev_wm8960;
31
32/* R25 - Power 1 */
33#define WM8960_VREF 0x40
34
35/* R28 - Anti-pop 1 */
36#define WM8960_POBCTRL 0x80
37#define WM8960_BUFDCOPEN 0x10
38#define WM8960_BUFIOEN 0x08
39#define WM8960_SOFT_ST 0x04
40#define WM8960_HPSTBY 0x01
41
42/* R29 - Anti-pop 2 */
43#define WM8960_DISOP 0x40
44
45/*
46 * wm8960 register cache
47 * We can't read the WM8960 register space when we are
48 * using 2 wire for device control, so we cache them instead.
49 */
50static const u16 wm8960_reg[WM8960_CACHEREGNUM] = {
51 0x0097, 0x0097, 0x0000, 0x0000,
52 0x0000, 0x0008, 0x0000, 0x000a,
53 0x01c0, 0x0000, 0x00ff, 0x00ff,
54 0x0000, 0x0000, 0x0000, 0x0000,
55 0x0000, 0x007b, 0x0100, 0x0032,
56 0x0000, 0x00c3, 0x00c3, 0x01c0,
57 0x0000, 0x0000, 0x0000, 0x0000,
58 0x0000, 0x0000, 0x0000, 0x0000,
59 0x0100, 0x0100, 0x0050, 0x0050,
60 0x0050, 0x0050, 0x0000, 0x0000,
61 0x0000, 0x0000, 0x0040, 0x0000,
62 0x0000, 0x0050, 0x0050, 0x0000,
63 0x0002, 0x0037, 0x004d, 0x0080,
64 0x0008, 0x0031, 0x0026, 0x00e9,
65};
66
67struct wm8960_priv {
68 u16 reg_cache[WM8960_CACHEREGNUM];
69 struct snd_soc_codec codec;
70};
71
72/*
73 * read wm8960 register cache
74 */
75static inline unsigned int wm8960_read_reg_cache(struct snd_soc_codec *codec,
76 unsigned int reg)
77{
78 u16 *cache = codec->reg_cache;
79 if (reg == WM8960_RESET)
80 return 0;
81 if (reg >= WM8960_CACHEREGNUM)
82 return -1;
83 return cache[reg];
84}
85
86/*
87 * write wm8960 register cache
88 */
89static inline void wm8960_write_reg_cache(struct snd_soc_codec *codec,
90 u16 reg, unsigned int value)
91{
92 u16 *cache = codec->reg_cache;
93 if (reg >= WM8960_CACHEREGNUM)
94 return;
95 cache[reg] = value;
96}
97
98static inline unsigned int wm8960_read(struct snd_soc_codec *codec,
99 unsigned int reg)
100{
101 return wm8960_read_reg_cache(codec, reg);
102}
103
104/*
105 * write to the WM8960 register space
106 */
107static int wm8960_write(struct snd_soc_codec *codec, unsigned int reg,
108 unsigned int value)
109{
110 u8 data[2];
111
112 /* data is
113 * D15..D9 WM8960 register offset
114 * D8...D0 register data
115 */
116 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
117 data[1] = value & 0x00ff;
118
119 wm8960_write_reg_cache(codec, reg, value);
120 if (codec->hw_write(codec->control_data, data, 2) == 2)
121 return 0;
122 else
123 return -EIO;
124}
125
126#define wm8960_reset(c) wm8960_write(c, WM8960_RESET, 0)
127
128/* enumerated controls */
129static const char *wm8960_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
130static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted",
131 "Right Inverted", "Stereo Inversion"};
132static const char *wm8960_3d_upper_cutoff[] = {"High", "Low"};
133static const char *wm8960_3d_lower_cutoff[] = {"Low", "High"};
134static const char *wm8960_alcfunc[] = {"Off", "Right", "Left", "Stereo"};
135static const char *wm8960_alcmode[] = {"ALC", "Limiter"};
136
137static const struct soc_enum wm8960_enum[] = {
138 SOC_ENUM_SINGLE(WM8960_DACCTL1, 1, 4, wm8960_deemph),
139 SOC_ENUM_SINGLE(WM8960_DACCTL1, 5, 4, wm8960_polarity),
140 SOC_ENUM_SINGLE(WM8960_DACCTL2, 5, 4, wm8960_polarity),
141 SOC_ENUM_SINGLE(WM8960_3D, 6, 2, wm8960_3d_upper_cutoff),
142 SOC_ENUM_SINGLE(WM8960_3D, 5, 2, wm8960_3d_lower_cutoff),
143 SOC_ENUM_SINGLE(WM8960_ALC1, 7, 4, wm8960_alcfunc),
144 SOC_ENUM_SINGLE(WM8960_ALC3, 8, 2, wm8960_alcmode),
145};
146
147static const DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 50, 0);
148static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
149static const DECLARE_TLV_DB_SCALE(bypass_tlv, -2100, 300, 0);
150static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
151
152static const struct snd_kcontrol_new wm8960_snd_controls[] = {
153SOC_DOUBLE_R_TLV("Capture Volume", WM8960_LINVOL, WM8960_RINVOL,
154 0, 63, 0, adc_tlv),
155SOC_DOUBLE_R("Capture Volume ZC Switch", WM8960_LINVOL, WM8960_RINVOL,
156 6, 1, 0),
157SOC_DOUBLE_R("Capture Switch", WM8960_LINVOL, WM8960_RINVOL,
158 7, 1, 0),
159
160SOC_DOUBLE_R_TLV("Playback Volume", WM8960_LDAC, WM8960_RDAC,
161 0, 255, 0, dac_tlv),
162
163SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8960_LOUT1, WM8960_ROUT1,
164 0, 127, 0, out_tlv),
165SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8960_LOUT1, WM8960_ROUT1,
166 7, 1, 0),
167
168SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8960_LOUT2, WM8960_ROUT2,
169 0, 127, 0, out_tlv),
170SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8960_LOUT2, WM8960_ROUT2,
171 7, 1, 0),
172SOC_SINGLE("Speaker DC Volume", WM8960_CLASSD3, 3, 5, 0),
173SOC_SINGLE("Speaker AC Volume", WM8960_CLASSD3, 0, 5, 0),
174
175SOC_SINGLE("PCM Playback -6dB Switch", WM8960_DACCTL1, 7, 1, 0),
176SOC_ENUM("ADC Polarity", wm8960_enum[1]),
177SOC_ENUM("Playback De-emphasis", wm8960_enum[0]),
178SOC_SINGLE("ADC High Pass Filter Switch", WM8960_DACCTL1, 0, 1, 0),
179
180SOC_ENUM("DAC Polarity", wm8960_enum[2]),
181
182SOC_ENUM("3D Filter Upper Cut-Off", wm8960_enum[3]),
183SOC_ENUM("3D Filter Lower Cut-Off", wm8960_enum[4]),
184SOC_SINGLE("3D Volume", WM8960_3D, 1, 15, 0),
185SOC_SINGLE("3D Switch", WM8960_3D, 0, 1, 0),
186
187SOC_ENUM("ALC Function", wm8960_enum[5]),
188SOC_SINGLE("ALC Max Gain", WM8960_ALC1, 4, 7, 0),
189SOC_SINGLE("ALC Target", WM8960_ALC1, 0, 15, 1),
190SOC_SINGLE("ALC Min Gain", WM8960_ALC2, 4, 7, 0),
191SOC_SINGLE("ALC Hold Time", WM8960_ALC2, 0, 15, 0),
192SOC_ENUM("ALC Mode", wm8960_enum[6]),
193SOC_SINGLE("ALC Decay", WM8960_ALC3, 4, 15, 0),
194SOC_SINGLE("ALC Attack", WM8960_ALC3, 0, 15, 0),
195
196SOC_SINGLE("Noise Gate Threshold", WM8960_NOISEG, 3, 31, 0),
197SOC_SINGLE("Noise Gate Switch", WM8960_NOISEG, 0, 1, 0),
198
199SOC_DOUBLE_R("ADC PCM Capture Volume", WM8960_LINPATH, WM8960_RINPATH,
200 0, 127, 0),
201
202SOC_SINGLE_TLV("Left Output Mixer Boost Bypass Volume",
203 WM8960_BYPASS1, 4, 7, 1, bypass_tlv),
204SOC_SINGLE_TLV("Left Output Mixer LINPUT3 Volume",
205 WM8960_LOUTMIX, 4, 7, 1, bypass_tlv),
206SOC_SINGLE_TLV("Right Output Mixer Boost Bypass Volume",
207 WM8960_BYPASS2, 4, 7, 1, bypass_tlv),
208SOC_SINGLE_TLV("Right Output Mixer RINPUT3 Volume",
209 WM8960_ROUTMIX, 4, 7, 1, bypass_tlv),
210};
211
212static const struct snd_kcontrol_new wm8960_lin_boost[] = {
213SOC_DAPM_SINGLE("LINPUT2 Switch", WM8960_LINPATH, 6, 1, 0),
214SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LINPATH, 7, 1, 0),
215SOC_DAPM_SINGLE("LINPUT1 Switch", WM8960_LINPATH, 8, 1, 0),
216};
217
218static const struct snd_kcontrol_new wm8960_lin[] = {
219SOC_DAPM_SINGLE("Boost Switch", WM8960_LINPATH, 3, 1, 0),
220};
221
222static const struct snd_kcontrol_new wm8960_rin_boost[] = {
223SOC_DAPM_SINGLE("RINPUT2 Switch", WM8960_RINPATH, 6, 1, 0),
224SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_RINPATH, 7, 1, 0),
225SOC_DAPM_SINGLE("RINPUT1 Switch", WM8960_RINPATH, 8, 1, 0),
226};
227
228static const struct snd_kcontrol_new wm8960_rin[] = {
229SOC_DAPM_SINGLE("Boost Switch", WM8960_RINPATH, 3, 1, 0),
230};
231
232static const struct snd_kcontrol_new wm8960_loutput_mixer[] = {
233SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_LOUTMIX, 8, 1, 0),
234SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LOUTMIX, 7, 1, 0),
235SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS1, 7, 1, 0),
236};
237
238static const struct snd_kcontrol_new wm8960_routput_mixer[] = {
239SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_ROUTMIX, 8, 1, 0),
240SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_ROUTMIX, 7, 1, 0),
241SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS2, 7, 1, 0),
242};
243
244static const struct snd_kcontrol_new wm8960_mono_out[] = {
245SOC_DAPM_SINGLE("Left Switch", WM8960_MONOMIX1, 7, 1, 0),
246SOC_DAPM_SINGLE("Right Switch", WM8960_MONOMIX2, 7, 1, 0),
247};
248
249static const struct snd_soc_dapm_widget wm8960_dapm_widgets[] = {
250SND_SOC_DAPM_INPUT("LINPUT1"),
251SND_SOC_DAPM_INPUT("RINPUT1"),
252SND_SOC_DAPM_INPUT("LINPUT2"),
253SND_SOC_DAPM_INPUT("RINPUT2"),
254SND_SOC_DAPM_INPUT("LINPUT3"),
255SND_SOC_DAPM_INPUT("RINPUT3"),
256
257SND_SOC_DAPM_MICBIAS("MICB", WM8960_POWER1, 1, 0),
258
259SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8960_POWER1, 5, 0,
260 wm8960_lin_boost, ARRAY_SIZE(wm8960_lin_boost)),
261SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8960_POWER1, 4, 0,
262 wm8960_rin_boost, ARRAY_SIZE(wm8960_rin_boost)),
263
264SND_SOC_DAPM_MIXER("Left Input Mixer", WM8960_POWER3, 5, 0,
265 wm8960_lin, ARRAY_SIZE(wm8960_lin)),
266SND_SOC_DAPM_MIXER("Right Input Mixer", WM8960_POWER3, 4, 0,
267 wm8960_rin, ARRAY_SIZE(wm8960_rin)),
268
269SND_SOC_DAPM_ADC("Left ADC", "Capture", WM8960_POWER2, 3, 0),
270SND_SOC_DAPM_ADC("Right ADC", "Capture", WM8960_POWER2, 2, 0),
271
272SND_SOC_DAPM_DAC("Left DAC", "Playback", WM8960_POWER2, 8, 0),
273SND_SOC_DAPM_DAC("Right DAC", "Playback", WM8960_POWER2, 7, 0),
274
275SND_SOC_DAPM_MIXER("Left Output Mixer", WM8960_POWER3, 3, 0,
276 &wm8960_loutput_mixer[0],
277 ARRAY_SIZE(wm8960_loutput_mixer)),
278SND_SOC_DAPM_MIXER("Right Output Mixer", WM8960_POWER3, 2, 0,
279 &wm8960_routput_mixer[0],
280 ARRAY_SIZE(wm8960_routput_mixer)),
281
282SND_SOC_DAPM_MIXER("Mono Output Mixer", WM8960_POWER2, 1, 0,
283 &wm8960_mono_out[0],
284 ARRAY_SIZE(wm8960_mono_out)),
285
286SND_SOC_DAPM_PGA("LOUT1 PGA", WM8960_POWER2, 6, 0, NULL, 0),
287SND_SOC_DAPM_PGA("ROUT1 PGA", WM8960_POWER2, 5, 0, NULL, 0),
288
289SND_SOC_DAPM_PGA("Left Speaker PGA", WM8960_POWER2, 4, 0, NULL, 0),
290SND_SOC_DAPM_PGA("Right Speaker PGA", WM8960_POWER2, 3, 0, NULL, 0),
291
292SND_SOC_DAPM_PGA("Right Speaker Output", WM8960_CLASSD1, 7, 0, NULL, 0),
293SND_SOC_DAPM_PGA("Left Speaker Output", WM8960_CLASSD1, 6, 0, NULL, 0),
294
295SND_SOC_DAPM_OUTPUT("SPK_LP"),
296SND_SOC_DAPM_OUTPUT("SPK_LN"),
297SND_SOC_DAPM_OUTPUT("HP_L"),
298SND_SOC_DAPM_OUTPUT("HP_R"),
299SND_SOC_DAPM_OUTPUT("SPK_RP"),
300SND_SOC_DAPM_OUTPUT("SPK_RN"),
301SND_SOC_DAPM_OUTPUT("OUT3"),
302};
303
304static const struct snd_soc_dapm_route audio_paths[] = {
305 { "Left Boost Mixer", "LINPUT1 Switch", "LINPUT1" },
306 { "Left Boost Mixer", "LINPUT2 Switch", "LINPUT2" },
307 { "Left Boost Mixer", "LINPUT3 Switch", "LINPUT3" },
308
309 { "Left Input Mixer", "Boost Switch", "Left Boost Mixer", },
310 { "Left Input Mixer", NULL, "LINPUT1", }, /* Really Boost Switch */
311 { "Left Input Mixer", NULL, "LINPUT2" },
312 { "Left Input Mixer", NULL, "LINPUT3" },
313
314 { "Right Boost Mixer", "RINPUT1 Switch", "RINPUT1" },
315 { "Right Boost Mixer", "RINPUT2 Switch", "RINPUT2" },
316 { "Right Boost Mixer", "RINPUT3 Switch", "RINPUT3" },
317
318 { "Right Input Mixer", "Boost Switch", "Right Boost Mixer", },
319 { "Right Input Mixer", NULL, "RINPUT1", }, /* Really Boost Switch */
320 { "Right Input Mixer", NULL, "RINPUT2" },
321 { "Right Input Mixer", NULL, "LINPUT3" },
322
323 { "Left ADC", NULL, "Left Input Mixer" },
324 { "Right ADC", NULL, "Right Input Mixer" },
325
326 { "Left Output Mixer", "LINPUT3 Switch", "LINPUT3" },
327 { "Left Output Mixer", "Boost Bypass Switch", "Left Boost Mixer"} ,
328 { "Left Output Mixer", "PCM Playback Switch", "Left DAC" },
329
330 { "Right Output Mixer", "RINPUT3 Switch", "RINPUT3" },
331 { "Right Output Mixer", "Boost Bypass Switch", "Right Boost Mixer" } ,
332 { "Right Output Mixer", "PCM Playback Switch", "Right DAC" },
333
334 { "Mono Output Mixer", "Left Switch", "Left Output Mixer" },
335 { "Mono Output Mixer", "Right Switch", "Right Output Mixer" },
336
337 { "LOUT1 PGA", NULL, "Left Output Mixer" },
338 { "ROUT1 PGA", NULL, "Right Output Mixer" },
339
340 { "HP_L", NULL, "LOUT1 PGA" },
341 { "HP_R", NULL, "ROUT1 PGA" },
342
343 { "Left Speaker PGA", NULL, "Left Output Mixer" },
344 { "Right Speaker PGA", NULL, "Right Output Mixer" },
345
346 { "Left Speaker Output", NULL, "Left Speaker PGA" },
347 { "Right Speaker Output", NULL, "Right Speaker PGA" },
348
349 { "SPK_LN", NULL, "Left Speaker Output" },
350 { "SPK_LP", NULL, "Left Speaker Output" },
351 { "SPK_RN", NULL, "Right Speaker Output" },
352 { "SPK_RP", NULL, "Right Speaker Output" },
353
354 { "OUT3", NULL, "Mono Output Mixer", }
355};
356
357static int wm8960_add_widgets(struct snd_soc_codec *codec)
358{
359 snd_soc_dapm_new_controls(codec, wm8960_dapm_widgets,
360 ARRAY_SIZE(wm8960_dapm_widgets));
361
362 snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
363
364 snd_soc_dapm_new_widgets(codec);
365 return 0;
366}
367
368static int wm8960_set_dai_fmt(struct snd_soc_dai *codec_dai,
369 unsigned int fmt)
370{
371 struct snd_soc_codec *codec = codec_dai->codec;
372 u16 iface = 0;
373
374 /* set master/slave audio interface */
375 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
376 case SND_SOC_DAIFMT_CBM_CFM:
377 iface |= 0x0040;
378 break;
379 case SND_SOC_DAIFMT_CBS_CFS:
380 break;
381 default:
382 return -EINVAL;
383 }
384
385 /* interface format */
386 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
387 case SND_SOC_DAIFMT_I2S:
388 iface |= 0x0002;
389 break;
390 case SND_SOC_DAIFMT_RIGHT_J:
391 break;
392 case SND_SOC_DAIFMT_LEFT_J:
393 iface |= 0x0001;
394 break;
395 case SND_SOC_DAIFMT_DSP_A:
396 iface |= 0x0003;
397 break;
398 case SND_SOC_DAIFMT_DSP_B:
399 iface |= 0x0013;
400 break;
401 default:
402 return -EINVAL;
403 }
404
405 /* clock inversion */
406 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
407 case SND_SOC_DAIFMT_NB_NF:
408 break;
409 case SND_SOC_DAIFMT_IB_IF:
410 iface |= 0x0090;
411 break;
412 case SND_SOC_DAIFMT_IB_NF:
413 iface |= 0x0080;
414 break;
415 case SND_SOC_DAIFMT_NB_IF:
416 iface |= 0x0010;
417 break;
418 default:
419 return -EINVAL;
420 }
421
422 /* set iface */
423 wm8960_write(codec, WM8960_IFACE1, iface);
424 return 0;
425}
426
427static int wm8960_hw_params(struct snd_pcm_substream *substream,
428 struct snd_pcm_hw_params *params,
429 struct snd_soc_dai *dai)
430{
431 struct snd_soc_pcm_runtime *rtd = substream->private_data;
432 struct snd_soc_device *socdev = rtd->socdev;
433 struct snd_soc_codec *codec = socdev->card->codec;
434 u16 iface = wm8960_read(codec, WM8960_IFACE1) & 0xfff3;
435
436 /* bit size */
437 switch (params_format(params)) {
438 case SNDRV_PCM_FORMAT_S16_LE:
439 break;
440 case SNDRV_PCM_FORMAT_S20_3LE:
441 iface |= 0x0004;
442 break;
443 case SNDRV_PCM_FORMAT_S24_LE:
444 iface |= 0x0008;
445 break;
446 }
447
448 /* set iface */
449 wm8960_write(codec, WM8960_IFACE1, iface);
450 return 0;
451}
452
453static int wm8960_mute(struct snd_soc_dai *dai, int mute)
454{
455 struct snd_soc_codec *codec = dai->codec;
456 u16 mute_reg = wm8960_read(codec, WM8960_DACCTL1) & 0xfff7;
457
458 if (mute)
459 wm8960_write(codec, WM8960_DACCTL1, mute_reg | 0x8);
460 else
461 wm8960_write(codec, WM8960_DACCTL1, mute_reg);
462 return 0;
463}
464
465static int wm8960_set_bias_level(struct snd_soc_codec *codec,
466 enum snd_soc_bias_level level)
467{
468 struct wm8960_data *pdata = codec->dev->platform_data;
469 u16 reg;
470
471 switch (level) {
472 case SND_SOC_BIAS_ON:
473 break;
474
475 case SND_SOC_BIAS_PREPARE:
476 /* Set VMID to 2x50k */
477 reg = wm8960_read(codec, WM8960_POWER1);
478 reg &= ~0x180;
479 reg |= 0x80;
480 wm8960_write(codec, WM8960_POWER1, reg);
481 break;
482
483 case SND_SOC_BIAS_STANDBY:
484 if (codec->bias_level == SND_SOC_BIAS_OFF) {
485 /* Enable anti-pop features */
486 wm8960_write(codec, WM8960_APOP1,
487 WM8960_POBCTRL | WM8960_SOFT_ST |
488 WM8960_BUFDCOPEN | WM8960_BUFIOEN);
489
490 /* Discharge HP output */
491 reg = WM8960_DISOP;
492 if (pdata)
493 reg |= pdata->dres << 4;
494 wm8960_write(codec, WM8960_APOP2, reg);
495
496 msleep(400);
497
498 wm8960_write(codec, WM8960_APOP2, 0);
499
500 /* Enable & ramp VMID at 2x50k */
501 reg = wm8960_read(codec, WM8960_POWER1);
502 reg |= 0x80;
503 wm8960_write(codec, WM8960_POWER1, reg);
504 msleep(100);
505
506 /* Enable VREF */
507 wm8960_write(codec, WM8960_POWER1, reg | WM8960_VREF);
508
509 /* Disable anti-pop features */
510 wm8960_write(codec, WM8960_APOP1, WM8960_BUFIOEN);
511 }
512
513 /* Set VMID to 2x250k */
514 reg = wm8960_read(codec, WM8960_POWER1);
515 reg &= ~0x180;
516 reg |= 0x100;
517 wm8960_write(codec, WM8960_POWER1, reg);
518 break;
519
520 case SND_SOC_BIAS_OFF:
521 /* Enable anti-pop features */
522 wm8960_write(codec, WM8960_APOP1,
523 WM8960_POBCTRL | WM8960_SOFT_ST |
524 WM8960_BUFDCOPEN | WM8960_BUFIOEN);
525
526 /* Disable VMID and VREF, let them discharge */
527 wm8960_write(codec, WM8960_POWER1, 0);
528 msleep(600);
529
530 wm8960_write(codec, WM8960_APOP1, 0);
531 break;
532 }
533
534 codec->bias_level = level;
535
536 return 0;
537}
538
539/* PLL divisors */
540struct _pll_div {
541 u32 pre_div:1;
542 u32 n:4;
543 u32 k:24;
544};
545
546/* The size in bits of the pll divide multiplied by 10
547 * to allow rounding later */
548#define FIXED_PLL_SIZE ((1 << 24) * 10)
549
550static int pll_factors(unsigned int source, unsigned int target,
551 struct _pll_div *pll_div)
552{
553 unsigned long long Kpart;
554 unsigned int K, Ndiv, Nmod;
555
556 pr_debug("WM8960 PLL: setting %dHz->%dHz\n", source, target);
557
558 /* Scale up target to PLL operating frequency */
559 target *= 4;
560
561 Ndiv = target / source;
562 if (Ndiv < 6) {
563 source >>= 1;
564 pll_div->pre_div = 1;
565 Ndiv = target / source;
566 } else
567 pll_div->pre_div = 0;
568
569 if ((Ndiv < 6) || (Ndiv > 12)) {
570 pr_err("WM8960 PLL: Unsupported N=%d\n", Ndiv);
571 return -EINVAL;
572 }
573
574 pll_div->n = Ndiv;
575 Nmod = target % source;
576 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
577
578 do_div(Kpart, source);
579
580 K = Kpart & 0xFFFFFFFF;
581
582 /* Check if we need to round */
583 if ((K % 10) >= 5)
584 K += 5;
585
586 /* Move down to proper range now rounding is done */
587 K /= 10;
588
589 pll_div->k = K;
590
591 pr_debug("WM8960 PLL: N=%x K=%x pre_div=%d\n",
592 pll_div->n, pll_div->k, pll_div->pre_div);
593
594 return 0;
595}
596
597static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai,
598 int pll_id, unsigned int freq_in, unsigned int freq_out)
599{
600 struct snd_soc_codec *codec = codec_dai->codec;
601 u16 reg;
602 static struct _pll_div pll_div;
603 int ret;
604
605 if (freq_in && freq_out) {
606 ret = pll_factors(freq_in, freq_out, &pll_div);
607 if (ret != 0)
608 return ret;
609 }
610
611 /* Disable the PLL: even if we are changing the frequency the
612 * PLL needs to be disabled while we do so. */
613 wm8960_write(codec, WM8960_CLOCK1,
614 wm8960_read(codec, WM8960_CLOCK1) & ~1);
615 wm8960_write(codec, WM8960_POWER2,
616 wm8960_read(codec, WM8960_POWER2) & ~1);
617
618 if (!freq_in || !freq_out)
619 return 0;
620
621 reg = wm8960_read(codec, WM8960_PLL1) & ~0x3f;
622 reg |= pll_div.pre_div << 4;
623 reg |= pll_div.n;
624
625 if (pll_div.k) {
626 reg |= 0x20;
627
628 wm8960_write(codec, WM8960_PLL2, (pll_div.k >> 18) & 0x3f);
629 wm8960_write(codec, WM8960_PLL3, (pll_div.k >> 9) & 0x1ff);
630 wm8960_write(codec, WM8960_PLL4, pll_div.k & 0x1ff);
631 }
632 wm8960_write(codec, WM8960_PLL1, reg);
633
634 /* Turn it on */
635 wm8960_write(codec, WM8960_POWER2,
636 wm8960_read(codec, WM8960_POWER2) | 1);
637 msleep(250);
638 wm8960_write(codec, WM8960_CLOCK1,
639 wm8960_read(codec, WM8960_CLOCK1) | 1);
640
641 return 0;
642}
643
644static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
645 int div_id, int div)
646{
647 struct snd_soc_codec *codec = codec_dai->codec;
648 u16 reg;
649
650 switch (div_id) {
651 case WM8960_SYSCLKSEL:
652 reg = wm8960_read(codec, WM8960_CLOCK1) & 0x1fe;
653 wm8960_write(codec, WM8960_CLOCK1, reg | div);
654 break;
655 case WM8960_SYSCLKDIV:
656 reg = wm8960_read(codec, WM8960_CLOCK1) & 0x1f9;
657 wm8960_write(codec, WM8960_CLOCK1, reg | div);
658 break;
659 case WM8960_DACDIV:
660 reg = wm8960_read(codec, WM8960_CLOCK1) & 0x1c7;
661 wm8960_write(codec, WM8960_CLOCK1, reg | div);
662 break;
663 case WM8960_OPCLKDIV:
664 reg = wm8960_read(codec, WM8960_PLL1) & 0x03f;
665 wm8960_write(codec, WM8960_PLL1, reg | div);
666 break;
667 case WM8960_DCLKDIV:
668 reg = wm8960_read(codec, WM8960_CLOCK2) & 0x03f;
669 wm8960_write(codec, WM8960_CLOCK2, reg | div);
670 break;
671 case WM8960_TOCLKSEL:
672 reg = wm8960_read(codec, WM8960_ADDCTL1) & 0x1fd;
673 wm8960_write(codec, WM8960_ADDCTL1, reg | div);
674 break;
675 default:
676 return -EINVAL;
677 }
678
679 return 0;
680}
681
682#define WM8960_RATES SNDRV_PCM_RATE_8000_48000
683
684#define WM8960_FORMATS \
685 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
686 SNDRV_PCM_FMTBIT_S24_LE)
687
688static struct snd_soc_dai_ops wm8960_dai_ops = {
689 .hw_params = wm8960_hw_params,
690 .digital_mute = wm8960_mute,
691 .set_fmt = wm8960_set_dai_fmt,
692 .set_clkdiv = wm8960_set_dai_clkdiv,
693 .set_pll = wm8960_set_dai_pll,
694};
695
696struct snd_soc_dai wm8960_dai = {
697 .name = "WM8960",
698 .playback = {
699 .stream_name = "Playback",
700 .channels_min = 1,
701 .channels_max = 2,
702 .rates = WM8960_RATES,
703 .formats = WM8960_FORMATS,},
704 .capture = {
705 .stream_name = "Capture",
706 .channels_min = 1,
707 .channels_max = 2,
708 .rates = WM8960_RATES,
709 .formats = WM8960_FORMATS,},
710 .ops = &wm8960_dai_ops,
711 .symmetric_rates = 1,
712};
713EXPORT_SYMBOL_GPL(wm8960_dai);
714
715static int wm8960_suspend(struct platform_device *pdev, pm_message_t state)
716{
717 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
718 struct snd_soc_codec *codec = socdev->card->codec;
719
720 wm8960_set_bias_level(codec, SND_SOC_BIAS_OFF);
721 return 0;
722}
723
724static int wm8960_resume(struct platform_device *pdev)
725{
726 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
727 struct snd_soc_codec *codec = socdev->card->codec;
728 int i;
729 u8 data[2];
730 u16 *cache = codec->reg_cache;
731
732 /* Sync reg_cache with the hardware */
733 for (i = 0; i < ARRAY_SIZE(wm8960_reg); i++) {
734 data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
735 data[1] = cache[i] & 0x00ff;
736 codec->hw_write(codec->control_data, data, 2);
737 }
738
739 wm8960_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
740 wm8960_set_bias_level(codec, codec->suspend_bias_level);
741 return 0;
742}
743
744static struct snd_soc_codec *wm8960_codec;
745
746static int wm8960_probe(struct platform_device *pdev)
747{
748 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
749 struct snd_soc_codec *codec;
750 int ret = 0;
751
752 if (wm8960_codec == NULL) {
753 dev_err(&pdev->dev, "Codec device not registered\n");
754 return -ENODEV;
755 }
756
757 socdev->card->codec = wm8960_codec;
758 codec = wm8960_codec;
759
760 /* register pcms */
761 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
762 if (ret < 0) {
763 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
764 goto pcm_err;
765 }
766
767 snd_soc_add_controls(codec, wm8960_snd_controls,
768 ARRAY_SIZE(wm8960_snd_controls));
769 wm8960_add_widgets(codec);
770 ret = snd_soc_init_card(socdev);
771 if (ret < 0) {
772 dev_err(codec->dev, "failed to register card: %d\n", ret);
773 goto card_err;
774 }
775
776 return ret;
777
778card_err:
779 snd_soc_free_pcms(socdev);
780 snd_soc_dapm_free(socdev);
781pcm_err:
782 return ret;
783}
784
785/* power down chip */
786static int wm8960_remove(struct platform_device *pdev)
787{
788 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
789
790 snd_soc_free_pcms(socdev);
791 snd_soc_dapm_free(socdev);
792
793 return 0;
794}
795
796struct snd_soc_codec_device soc_codec_dev_wm8960 = {
797 .probe = wm8960_probe,
798 .remove = wm8960_remove,
799 .suspend = wm8960_suspend,
800 .resume = wm8960_resume,
801};
802EXPORT_SYMBOL_GPL(soc_codec_dev_wm8960);
803
804static int wm8960_register(struct wm8960_priv *wm8960)
805{
806 struct wm8960_data *pdata = wm8960->codec.dev->platform_data;
807 struct snd_soc_codec *codec = &wm8960->codec;
808 int ret;
809 u16 reg;
810
811 if (wm8960_codec) {
812 dev_err(codec->dev, "Another WM8960 is registered\n");
813 return -EINVAL;
814 }
815
816 if (!pdata) {
817 dev_warn(codec->dev, "No platform data supplied\n");
818 } else {
819 if (pdata->dres > WM8960_DRES_MAX) {
820 dev_err(codec->dev, "Invalid DRES: %d\n", pdata->dres);
821 pdata->dres = 0;
822 }
823 }
824
825 mutex_init(&codec->mutex);
826 INIT_LIST_HEAD(&codec->dapm_widgets);
827 INIT_LIST_HEAD(&codec->dapm_paths);
828
829 codec->private_data = wm8960;
830 codec->name = "WM8960";
831 codec->owner = THIS_MODULE;
832 codec->read = wm8960_read_reg_cache;
833 codec->write = wm8960_write;
834 codec->bias_level = SND_SOC_BIAS_OFF;
835 codec->set_bias_level = wm8960_set_bias_level;
836 codec->dai = &wm8960_dai;
837 codec->num_dai = 1;
838 codec->reg_cache_size = WM8960_CACHEREGNUM;
839 codec->reg_cache = &wm8960->reg_cache;
840
841 memcpy(codec->reg_cache, wm8960_reg, sizeof(wm8960_reg));
842
843 ret = wm8960_reset(codec);
844 if (ret < 0) {
845 dev_err(codec->dev, "Failed to issue reset\n");
846 return ret;
847 }
848
849 wm8960_dai.dev = codec->dev;
850
851 wm8960_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
852
853 /* Latch the update bits */
854 reg = wm8960_read(codec, WM8960_LINVOL);
855 wm8960_write(codec, WM8960_LINVOL, reg | 0x100);
856 reg = wm8960_read(codec, WM8960_RINVOL);
857 wm8960_write(codec, WM8960_RINVOL, reg | 0x100);
858 reg = wm8960_read(codec, WM8960_LADC);
859 wm8960_write(codec, WM8960_LADC, reg | 0x100);
860 reg = wm8960_read(codec, WM8960_RADC);
861 wm8960_write(codec, WM8960_RADC, reg | 0x100);
862 reg = wm8960_read(codec, WM8960_LDAC);
863 wm8960_write(codec, WM8960_LDAC, reg | 0x100);
864 reg = wm8960_read(codec, WM8960_RDAC);
865 wm8960_write(codec, WM8960_RDAC, reg | 0x100);
866 reg = wm8960_read(codec, WM8960_LOUT1);
867 wm8960_write(codec, WM8960_LOUT1, reg | 0x100);
868 reg = wm8960_read(codec, WM8960_ROUT1);
869 wm8960_write(codec, WM8960_ROUT1, reg | 0x100);
870 reg = wm8960_read(codec, WM8960_LOUT2);
871 wm8960_write(codec, WM8960_LOUT2, reg | 0x100);
872 reg = wm8960_read(codec, WM8960_ROUT2);
873 wm8960_write(codec, WM8960_ROUT2, reg | 0x100);
874
875 wm8960_codec = codec;
876
877 ret = snd_soc_register_codec(codec);
878 if (ret != 0) {
879 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
880 return ret;
881 }
882
883 ret = snd_soc_register_dai(&wm8960_dai);
884 if (ret != 0) {
885 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
886 snd_soc_unregister_codec(codec);
887 return ret;
888 }
889
890 return 0;
891}
892
893static void wm8960_unregister(struct wm8960_priv *wm8960)
894{
895 wm8960_set_bias_level(&wm8960->codec, SND_SOC_BIAS_OFF);
896 snd_soc_unregister_dai(&wm8960_dai);
897 snd_soc_unregister_codec(&wm8960->codec);
898 kfree(wm8960);
899 wm8960_codec = NULL;
900}
901
902static __devinit int wm8960_i2c_probe(struct i2c_client *i2c,
903 const struct i2c_device_id *id)
904{
905 struct wm8960_priv *wm8960;
906 struct snd_soc_codec *codec;
907
908 wm8960 = kzalloc(sizeof(struct wm8960_priv), GFP_KERNEL);
909 if (wm8960 == NULL)
910 return -ENOMEM;
911
912 codec = &wm8960->codec;
913 codec->hw_write = (hw_write_t)i2c_master_send;
914
915 i2c_set_clientdata(i2c, wm8960);
916 codec->control_data = i2c;
917
918 codec->dev = &i2c->dev;
919
920 return wm8960_register(wm8960);
921}
922
923static __devexit int wm8960_i2c_remove(struct i2c_client *client)
924{
925 struct wm8960_priv *wm8960 = i2c_get_clientdata(client);
926 wm8960_unregister(wm8960);
927 return 0;
928}
929
930static const struct i2c_device_id wm8960_i2c_id[] = {
931 { "wm8960", 0 },
932 { }
933};
934MODULE_DEVICE_TABLE(i2c, wm8960_i2c_id);
935
936static struct i2c_driver wm8960_i2c_driver = {
937 .driver = {
938 .name = "WM8960 I2C Codec",
939 .owner = THIS_MODULE,
940 },
941 .probe = wm8960_i2c_probe,
942 .remove = __devexit_p(wm8960_i2c_remove),
943 .id_table = wm8960_i2c_id,
944};
945
946static int __init wm8960_modinit(void)
947{
948 int ret;
949
950 ret = i2c_add_driver(&wm8960_i2c_driver);
951 if (ret != 0) {
952 printk(KERN_ERR "Failed to register WM8960 I2C driver: %d\n",
953 ret);
954 }
955
956 return ret;
957}
958module_init(wm8960_modinit);
959
960static void __exit wm8960_exit(void)
961{
962 i2c_del_driver(&wm8960_i2c_driver);
963}
964module_exit(wm8960_exit);
965
966
967MODULE_DESCRIPTION("ASoC WM8960 driver");
968MODULE_AUTHOR("Liam Girdwood");
969MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8960.h b/sound/soc/codecs/wm8960.h
new file mode 100644
index 000000000000..c9af56c9d9d4
--- /dev/null
+++ b/sound/soc/codecs/wm8960.h
@@ -0,0 +1,127 @@
1/*
2 * wm8960.h -- WM8960 Soc Audio driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef _WM8960_H
10#define _WM8960_H
11
12/* WM8960 register space */
13
14
15#define WM8960_CACHEREGNUM 56
16
17#define WM8960_LINVOL 0x0
18#define WM8960_RINVOL 0x1
19#define WM8960_LOUT1 0x2
20#define WM8960_ROUT1 0x3
21#define WM8960_CLOCK1 0x4
22#define WM8960_DACCTL1 0x5
23#define WM8960_DACCTL2 0x6
24#define WM8960_IFACE1 0x7
25#define WM8960_CLOCK2 0x8
26#define WM8960_IFACE2 0x9
27#define WM8960_LDAC 0xa
28#define WM8960_RDAC 0xb
29
30#define WM8960_RESET 0xf
31#define WM8960_3D 0x10
32#define WM8960_ALC1 0x11
33#define WM8960_ALC2 0x12
34#define WM8960_ALC3 0x13
35#define WM8960_NOISEG 0x14
36#define WM8960_LADC 0x15
37#define WM8960_RADC 0x16
38#define WM8960_ADDCTL1 0x17
39#define WM8960_ADDCTL2 0x18
40#define WM8960_POWER1 0x19
41#define WM8960_POWER2 0x1a
42#define WM8960_ADDCTL3 0x1b
43#define WM8960_APOP1 0x1c
44#define WM8960_APOP2 0x1d
45
46#define WM8960_LINPATH 0x20
47#define WM8960_RINPATH 0x21
48#define WM8960_LOUTMIX 0x22
49
50#define WM8960_ROUTMIX 0x25
51#define WM8960_MONOMIX1 0x26
52#define WM8960_MONOMIX2 0x27
53#define WM8960_LOUT2 0x28
54#define WM8960_ROUT2 0x29
55#define WM8960_MONO 0x2a
56#define WM8960_INBMIX1 0x2b
57#define WM8960_INBMIX2 0x2c
58#define WM8960_BYPASS1 0x2d
59#define WM8960_BYPASS2 0x2e
60#define WM8960_POWER3 0x2f
61#define WM8960_ADDCTL4 0x30
62#define WM8960_CLASSD1 0x31
63
64#define WM8960_CLASSD3 0x33
65#define WM8960_PLL1 0x34
66#define WM8960_PLL2 0x35
67#define WM8960_PLL3 0x36
68#define WM8960_PLL4 0x37
69
70
71/*
72 * WM8960 Clock dividers
73 */
74#define WM8960_SYSCLKDIV 0
75#define WM8960_DACDIV 1
76#define WM8960_OPCLKDIV 2
77#define WM8960_DCLKDIV 3
78#define WM8960_TOCLKSEL 4
79#define WM8960_SYSCLKSEL 5
80
81#define WM8960_SYSCLK_DIV_1 (0 << 1)
82#define WM8960_SYSCLK_DIV_2 (2 << 1)
83
84#define WM8960_SYSCLK_MCLK (0 << 0)
85#define WM8960_SYSCLK_PLL (1 << 0)
86
87#define WM8960_DAC_DIV_1 (0 << 3)
88#define WM8960_DAC_DIV_1_5 (1 << 3)
89#define WM8960_DAC_DIV_2 (2 << 3)
90#define WM8960_DAC_DIV_3 (3 << 3)
91#define WM8960_DAC_DIV_4 (4 << 3)
92#define WM8960_DAC_DIV_5_5 (5 << 3)
93#define WM8960_DAC_DIV_6 (6 << 3)
94
95#define WM8960_DCLK_DIV_1_5 (0 << 6)
96#define WM8960_DCLK_DIV_2 (1 << 6)
97#define WM8960_DCLK_DIV_3 (2 << 6)
98#define WM8960_DCLK_DIV_4 (3 << 6)
99#define WM8960_DCLK_DIV_6 (4 << 6)
100#define WM8960_DCLK_DIV_8 (5 << 6)
101#define WM8960_DCLK_DIV_12 (6 << 6)
102#define WM8960_DCLK_DIV_16 (7 << 6)
103
104#define WM8960_TOCLK_F19 (0 << 1)
105#define WM8960_TOCLK_F21 (1 << 1)
106
107#define WM8960_OPCLK_DIV_1 (0 << 0)
108#define WM8960_OPCLK_DIV_2 (1 << 0)
109#define WM8960_OPCLK_DIV_3 (2 << 0)
110#define WM8960_OPCLK_DIV_4 (3 << 0)
111#define WM8960_OPCLK_DIV_5_5 (4 << 0)
112#define WM8960_OPCLK_DIV_6 (5 << 0)
113
114extern struct snd_soc_dai wm8960_dai;
115extern struct snd_soc_codec_device soc_codec_dev_wm8960;
116
117#define WM8960_DRES_400R 0
118#define WM8960_DRES_200R 1
119#define WM8960_DRES_600R 2
120#define WM8960_DRES_150R 3
121#define WM8960_DRES_MAX 3
122
123struct wm8960_data {
124 int dres;
125};
126
127#endif
diff --git a/sound/soc/codecs/wm8988.c b/sound/soc/codecs/wm8988.c
new file mode 100644
index 000000000000..c05f71803aa8
--- /dev/null
+++ b/sound/soc/codecs/wm8988.c
@@ -0,0 +1,1097 @@
1/*
2 * wm8988.c -- WM8988 ALSA SoC audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 * Copyright 2005 Openedhand Ltd.
6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/spi/spi.h>
21#include <linux/platform_device.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/tlv.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29
30#include "wm8988.h"
31
32/*
33 * wm8988 register cache
34 * We can't read the WM8988 register space when we
35 * are using 2 wire for device control, so we cache them instead.
36 */
37static const u16 wm8988_reg[] = {
38 0x0097, 0x0097, 0x0079, 0x0079, /* 0 */
39 0x0000, 0x0008, 0x0000, 0x000a, /* 4 */
40 0x0000, 0x0000, 0x00ff, 0x00ff, /* 8 */
41 0x000f, 0x000f, 0x0000, 0x0000, /* 12 */
42 0x0000, 0x007b, 0x0000, 0x0032, /* 16 */
43 0x0000, 0x00c3, 0x00c3, 0x00c0, /* 20 */
44 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
45 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
46 0x0000, 0x0000, 0x0050, 0x0050, /* 32 */
47 0x0050, 0x0050, 0x0050, 0x0050, /* 36 */
48 0x0079, 0x0079, 0x0079, /* 40 */
49};
50
51/* codec private data */
52struct wm8988_priv {
53 unsigned int sysclk;
54 struct snd_soc_codec codec;
55 struct snd_pcm_hw_constraint_list *sysclk_constraints;
56 u16 reg_cache[WM8988_NUM_REG];
57};
58
59
60/*
61 * read wm8988 register cache
62 */
63static inline unsigned int wm8988_read_reg_cache(struct snd_soc_codec *codec,
64 unsigned int reg)
65{
66 u16 *cache = codec->reg_cache;
67 if (reg > WM8988_NUM_REG)
68 return -1;
69 return cache[reg];
70}
71
72/*
73 * write wm8988 register cache
74 */
75static inline void wm8988_write_reg_cache(struct snd_soc_codec *codec,
76 unsigned int reg, unsigned int value)
77{
78 u16 *cache = codec->reg_cache;
79 if (reg > WM8988_NUM_REG)
80 return;
81 cache[reg] = value;
82}
83
84static int wm8988_write(struct snd_soc_codec *codec, unsigned int reg,
85 unsigned int value)
86{
87 u8 data[2];
88
89 /* data is
90 * D15..D9 WM8753 register offset
91 * D8...D0 register data
92 */
93 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
94 data[1] = value & 0x00ff;
95
96 wm8988_write_reg_cache(codec, reg, value);
97 if (codec->hw_write(codec->control_data, data, 2) == 2)
98 return 0;
99 else
100 return -EIO;
101}
102
103#define wm8988_reset(c) wm8988_write(c, WM8988_RESET, 0)
104
105/*
106 * WM8988 Controls
107 */
108
109static const char *bass_boost_txt[] = {"Linear Control", "Adaptive Boost"};
110static const struct soc_enum bass_boost =
111 SOC_ENUM_SINGLE(WM8988_BASS, 7, 2, bass_boost_txt);
112
113static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
114static const struct soc_enum bass_filter =
115 SOC_ENUM_SINGLE(WM8988_BASS, 6, 2, bass_filter_txt);
116
117static const char *treble_txt[] = {"8kHz", "4kHz"};
118static const struct soc_enum treble =
119 SOC_ENUM_SINGLE(WM8988_TREBLE, 6, 2, treble_txt);
120
121static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
122static const struct soc_enum stereo_3d_lc =
123 SOC_ENUM_SINGLE(WM8988_3D, 5, 2, stereo_3d_lc_txt);
124
125static const char *stereo_3d_uc_txt[] = {"2.2kHz", "1.5kHz"};
126static const struct soc_enum stereo_3d_uc =
127 SOC_ENUM_SINGLE(WM8988_3D, 6, 2, stereo_3d_uc_txt);
128
129static const char *stereo_3d_func_txt[] = {"Capture", "Playback"};
130static const struct soc_enum stereo_3d_func =
131 SOC_ENUM_SINGLE(WM8988_3D, 7, 2, stereo_3d_func_txt);
132
133static const char *alc_func_txt[] = {"Off", "Right", "Left", "Stereo"};
134static const struct soc_enum alc_func =
135 SOC_ENUM_SINGLE(WM8988_ALC1, 7, 4, alc_func_txt);
136
137static const char *ng_type_txt[] = {"Constant PGA Gain",
138 "Mute ADC Output"};
139static const struct soc_enum ng_type =
140 SOC_ENUM_SINGLE(WM8988_NGATE, 1, 2, ng_type_txt);
141
142static const char *deemph_txt[] = {"None", "32Khz", "44.1Khz", "48Khz"};
143static const struct soc_enum deemph =
144 SOC_ENUM_SINGLE(WM8988_ADCDAC, 1, 4, deemph_txt);
145
146static const char *adcpol_txt[] = {"Normal", "L Invert", "R Invert",
147 "L + R Invert"};
148static const struct soc_enum adcpol =
149 SOC_ENUM_SINGLE(WM8988_ADCDAC, 5, 4, adcpol_txt);
150
151static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
152static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
153static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
154static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
155static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
156
157static const struct snd_kcontrol_new wm8988_snd_controls[] = {
158
159SOC_ENUM("Bass Boost", bass_boost),
160SOC_ENUM("Bass Filter", bass_filter),
161SOC_SINGLE("Bass Volume", WM8988_BASS, 0, 15, 1),
162
163SOC_SINGLE("Treble Volume", WM8988_TREBLE, 0, 15, 0),
164SOC_ENUM("Treble Cut-off", treble),
165
166SOC_SINGLE("3D Switch", WM8988_3D, 0, 1, 0),
167SOC_SINGLE("3D Volume", WM8988_3D, 1, 15, 0),
168SOC_ENUM("3D Lower Cut-off", stereo_3d_lc),
169SOC_ENUM("3D Upper Cut-off", stereo_3d_uc),
170SOC_ENUM("3D Mode", stereo_3d_func),
171
172SOC_SINGLE("ALC Capture Target Volume", WM8988_ALC1, 0, 7, 0),
173SOC_SINGLE("ALC Capture Max Volume", WM8988_ALC1, 4, 7, 0),
174SOC_ENUM("ALC Capture Function", alc_func),
175SOC_SINGLE("ALC Capture ZC Switch", WM8988_ALC2, 7, 1, 0),
176SOC_SINGLE("ALC Capture Hold Time", WM8988_ALC2, 0, 15, 0),
177SOC_SINGLE("ALC Capture Decay Time", WM8988_ALC3, 4, 15, 0),
178SOC_SINGLE("ALC Capture Attack Time", WM8988_ALC3, 0, 15, 0),
179SOC_SINGLE("ALC Capture NG Threshold", WM8988_NGATE, 3, 31, 0),
180SOC_ENUM("ALC Capture NG Type", ng_type),
181SOC_SINGLE("ALC Capture NG Switch", WM8988_NGATE, 0, 1, 0),
182
183SOC_SINGLE("ZC Timeout Switch", WM8988_ADCTL1, 0, 1, 0),
184
185SOC_DOUBLE_R_TLV("Capture Digital Volume", WM8988_LADC, WM8988_RADC,
186 0, 255, 0, adc_tlv),
187SOC_DOUBLE_R_TLV("Capture Volume", WM8988_LINVOL, WM8988_RINVOL,
188 0, 63, 0, pga_tlv),
189SOC_DOUBLE_R("Capture ZC Switch", WM8988_LINVOL, WM8988_RINVOL, 6, 1, 0),
190SOC_DOUBLE_R("Capture Switch", WM8988_LINVOL, WM8988_RINVOL, 7, 1, 1),
191
192SOC_ENUM("Playback De-emphasis", deemph),
193
194SOC_ENUM("Capture Polarity", adcpol),
195SOC_SINGLE("Playback 6dB Attenuate", WM8988_ADCDAC, 7, 1, 0),
196SOC_SINGLE("Capture 6dB Attenuate", WM8988_ADCDAC, 8, 1, 0),
197
198SOC_DOUBLE_R_TLV("PCM Volume", WM8988_LDAC, WM8988_RDAC, 0, 255, 0, dac_tlv),
199
200SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", WM8988_LOUTM1, 4, 7, 1,
201 bypass_tlv),
202SOC_SINGLE_TLV("Left Mixer Right Bypass Volume", WM8988_LOUTM2, 4, 7, 1,
203 bypass_tlv),
204SOC_SINGLE_TLV("Right Mixer Left Bypass Volume", WM8988_ROUTM1, 4, 7, 1,
205 bypass_tlv),
206SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", WM8988_ROUTM2, 4, 7, 1,
207 bypass_tlv),
208
209SOC_DOUBLE_R("Output 1 Playback ZC Switch", WM8988_LOUT1V,
210 WM8988_ROUT1V, 7, 1, 0),
211SOC_DOUBLE_R_TLV("Output 1 Playback Volume", WM8988_LOUT1V, WM8988_ROUT1V,
212 0, 127, 0, out_tlv),
213
214SOC_DOUBLE_R("Output 2 Playback ZC Switch", WM8988_LOUT2V,
215 WM8988_ROUT2V, 7, 1, 0),
216SOC_DOUBLE_R_TLV("Output 2 Playback Volume", WM8988_LOUT2V, WM8988_ROUT2V,
217 0, 127, 0, out_tlv),
218
219};
220
221/*
222 * DAPM Controls
223 */
224
225static int wm8988_lrc_control(struct snd_soc_dapm_widget *w,
226 struct snd_kcontrol *kcontrol, int event)
227{
228 struct snd_soc_codec *codec = w->codec;
229 u16 adctl2 = wm8988_read_reg_cache(codec, WM8988_ADCTL2);
230
231 /* Use the DAC to gate LRC if active, otherwise use ADC */
232 if (wm8988_read_reg_cache(codec, WM8988_PWR2) & 0x180)
233 adctl2 &= ~0x4;
234 else
235 adctl2 |= 0x4;
236
237 return wm8988_write(codec, WM8988_ADCTL2, adctl2);
238}
239
240static const char *wm8988_line_texts[] = {
241 "Line 1", "Line 2", "PGA", "Differential"};
242
243static const unsigned int wm8988_line_values[] = {
244 0, 1, 3, 4};
245
246static const struct soc_enum wm8988_lline_enum =
247 SOC_VALUE_ENUM_SINGLE(WM8988_LOUTM1, 0, 7,
248 ARRAY_SIZE(wm8988_line_texts),
249 wm8988_line_texts,
250 wm8988_line_values);
251static const struct snd_kcontrol_new wm8988_left_line_controls =
252 SOC_DAPM_VALUE_ENUM("Route", wm8988_lline_enum);
253
254static const struct soc_enum wm8988_rline_enum =
255 SOC_VALUE_ENUM_SINGLE(WM8988_ROUTM1, 0, 7,
256 ARRAY_SIZE(wm8988_line_texts),
257 wm8988_line_texts,
258 wm8988_line_values);
259static const struct snd_kcontrol_new wm8988_right_line_controls =
260 SOC_DAPM_VALUE_ENUM("Route", wm8988_lline_enum);
261
262/* Left Mixer */
263static const struct snd_kcontrol_new wm8988_left_mixer_controls[] = {
264 SOC_DAPM_SINGLE("Playback Switch", WM8988_LOUTM1, 8, 1, 0),
265 SOC_DAPM_SINGLE("Left Bypass Switch", WM8988_LOUTM1, 7, 1, 0),
266 SOC_DAPM_SINGLE("Right Playback Switch", WM8988_LOUTM2, 8, 1, 0),
267 SOC_DAPM_SINGLE("Right Bypass Switch", WM8988_LOUTM2, 7, 1, 0),
268};
269
270/* Right Mixer */
271static const struct snd_kcontrol_new wm8988_right_mixer_controls[] = {
272 SOC_DAPM_SINGLE("Left Playback Switch", WM8988_ROUTM1, 8, 1, 0),
273 SOC_DAPM_SINGLE("Left Bypass Switch", WM8988_ROUTM1, 7, 1, 0),
274 SOC_DAPM_SINGLE("Playback Switch", WM8988_ROUTM2, 8, 1, 0),
275 SOC_DAPM_SINGLE("Right Bypass Switch", WM8988_ROUTM2, 7, 1, 0),
276};
277
278static const char *wm8988_pga_sel[] = {"Line 1", "Line 2", "Differential"};
279static const unsigned int wm8988_pga_val[] = { 0, 1, 3 };
280
281/* Left PGA Mux */
282static const struct soc_enum wm8988_lpga_enum =
283 SOC_VALUE_ENUM_SINGLE(WM8988_LADCIN, 6, 3,
284 ARRAY_SIZE(wm8988_pga_sel),
285 wm8988_pga_sel,
286 wm8988_pga_val);
287static const struct snd_kcontrol_new wm8988_left_pga_controls =
288 SOC_DAPM_VALUE_ENUM("Route", wm8988_lpga_enum);
289
290/* Right PGA Mux */
291static const struct soc_enum wm8988_rpga_enum =
292 SOC_VALUE_ENUM_SINGLE(WM8988_RADCIN, 6, 3,
293 ARRAY_SIZE(wm8988_pga_sel),
294 wm8988_pga_sel,
295 wm8988_pga_val);
296static const struct snd_kcontrol_new wm8988_right_pga_controls =
297 SOC_DAPM_VALUE_ENUM("Route", wm8988_rpga_enum);
298
299/* Differential Mux */
300static const char *wm8988_diff_sel[] = {"Line 1", "Line 2"};
301static const struct soc_enum diffmux =
302 SOC_ENUM_SINGLE(WM8988_ADCIN, 8, 2, wm8988_diff_sel);
303static const struct snd_kcontrol_new wm8988_diffmux_controls =
304 SOC_DAPM_ENUM("Route", diffmux);
305
306/* Mono ADC Mux */
307static const char *wm8988_mono_mux[] = {"Stereo", "Mono (Left)",
308 "Mono (Right)", "Digital Mono"};
309static const struct soc_enum monomux =
310 SOC_ENUM_SINGLE(WM8988_ADCIN, 6, 4, wm8988_mono_mux);
311static const struct snd_kcontrol_new wm8988_monomux_controls =
312 SOC_DAPM_ENUM("Route", monomux);
313
314static const struct snd_soc_dapm_widget wm8988_dapm_widgets[] = {
315 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8988_PWR1, 1, 0),
316
317 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
318 &wm8988_diffmux_controls),
319 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
320 &wm8988_monomux_controls),
321 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
322 &wm8988_monomux_controls),
323
324 SND_SOC_DAPM_MUX("Left PGA Mux", WM8988_PWR1, 5, 0,
325 &wm8988_left_pga_controls),
326 SND_SOC_DAPM_MUX("Right PGA Mux", WM8988_PWR1, 4, 0,
327 &wm8988_right_pga_controls),
328
329 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
330 &wm8988_left_line_controls),
331 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
332 &wm8988_right_line_controls),
333
334 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8988_PWR1, 2, 0),
335 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8988_PWR1, 3, 0),
336
337 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8988_PWR2, 7, 0),
338 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8988_PWR2, 8, 0),
339
340 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
341 &wm8988_left_mixer_controls[0],
342 ARRAY_SIZE(wm8988_left_mixer_controls)),
343 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
344 &wm8988_right_mixer_controls[0],
345 ARRAY_SIZE(wm8988_right_mixer_controls)),
346
347 SND_SOC_DAPM_PGA("Right Out 2", WM8988_PWR2, 3, 0, NULL, 0),
348 SND_SOC_DAPM_PGA("Left Out 2", WM8988_PWR2, 4, 0, NULL, 0),
349 SND_SOC_DAPM_PGA("Right Out 1", WM8988_PWR2, 5, 0, NULL, 0),
350 SND_SOC_DAPM_PGA("Left Out 1", WM8988_PWR2, 6, 0, NULL, 0),
351
352 SND_SOC_DAPM_POST("LRC control", wm8988_lrc_control),
353
354 SND_SOC_DAPM_OUTPUT("LOUT1"),
355 SND_SOC_DAPM_OUTPUT("ROUT1"),
356 SND_SOC_DAPM_OUTPUT("LOUT2"),
357 SND_SOC_DAPM_OUTPUT("ROUT2"),
358 SND_SOC_DAPM_OUTPUT("VREF"),
359
360 SND_SOC_DAPM_INPUT("LINPUT1"),
361 SND_SOC_DAPM_INPUT("LINPUT2"),
362 SND_SOC_DAPM_INPUT("RINPUT1"),
363 SND_SOC_DAPM_INPUT("RINPUT2"),
364};
365
366static const struct snd_soc_dapm_route audio_map[] = {
367
368 { "Left Line Mux", "Line 1", "LINPUT1" },
369 { "Left Line Mux", "Line 2", "LINPUT2" },
370 { "Left Line Mux", "PGA", "Left PGA Mux" },
371 { "Left Line Mux", "Differential", "Differential Mux" },
372
373 { "Right Line Mux", "Line 1", "RINPUT1" },
374 { "Right Line Mux", "Line 2", "RINPUT2" },
375 { "Right Line Mux", "PGA", "Right PGA Mux" },
376 { "Right Line Mux", "Differential", "Differential Mux" },
377
378 { "Left PGA Mux", "Line 1", "LINPUT1" },
379 { "Left PGA Mux", "Line 2", "LINPUT2" },
380 { "Left PGA Mux", "Differential", "Differential Mux" },
381
382 { "Right PGA Mux", "Line 1", "RINPUT1" },
383 { "Right PGA Mux", "Line 2", "RINPUT2" },
384 { "Right PGA Mux", "Differential", "Differential Mux" },
385
386 { "Differential Mux", "Line 1", "LINPUT1" },
387 { "Differential Mux", "Line 1", "RINPUT1" },
388 { "Differential Mux", "Line 2", "LINPUT2" },
389 { "Differential Mux", "Line 2", "RINPUT2" },
390
391 { "Left ADC Mux", "Stereo", "Left PGA Mux" },
392 { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
393 { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
394
395 { "Right ADC Mux", "Stereo", "Right PGA Mux" },
396 { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
397 { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
398
399 { "Left ADC", NULL, "Left ADC Mux" },
400 { "Right ADC", NULL, "Right ADC Mux" },
401
402 { "Left Line Mux", "Line 1", "LINPUT1" },
403 { "Left Line Mux", "Line 2", "LINPUT2" },
404 { "Left Line Mux", "PGA", "Left PGA Mux" },
405 { "Left Line Mux", "Differential", "Differential Mux" },
406
407 { "Right Line Mux", "Line 1", "RINPUT1" },
408 { "Right Line Mux", "Line 2", "RINPUT2" },
409 { "Right Line Mux", "PGA", "Right PGA Mux" },
410 { "Right Line Mux", "Differential", "Differential Mux" },
411
412 { "Left Mixer", "Playback Switch", "Left DAC" },
413 { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
414 { "Left Mixer", "Right Playback Switch", "Right DAC" },
415 { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
416
417 { "Right Mixer", "Left Playback Switch", "Left DAC" },
418 { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
419 { "Right Mixer", "Playback Switch", "Right DAC" },
420 { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
421
422 { "Left Out 1", NULL, "Left Mixer" },
423 { "LOUT1", NULL, "Left Out 1" },
424 { "Right Out 1", NULL, "Right Mixer" },
425 { "ROUT1", NULL, "Right Out 1" },
426
427 { "Left Out 2", NULL, "Left Mixer" },
428 { "LOUT2", NULL, "Left Out 2" },
429 { "Right Out 2", NULL, "Right Mixer" },
430 { "ROUT2", NULL, "Right Out 2" },
431};
432
433struct _coeff_div {
434 u32 mclk;
435 u32 rate;
436 u16 fs;
437 u8 sr:5;
438 u8 usb:1;
439};
440
441/* codec hifi mclk clock divider coefficients */
442static const struct _coeff_div coeff_div[] = {
443 /* 8k */
444 {12288000, 8000, 1536, 0x6, 0x0},
445 {11289600, 8000, 1408, 0x16, 0x0},
446 {18432000, 8000, 2304, 0x7, 0x0},
447 {16934400, 8000, 2112, 0x17, 0x0},
448 {12000000, 8000, 1500, 0x6, 0x1},
449
450 /* 11.025k */
451 {11289600, 11025, 1024, 0x18, 0x0},
452 {16934400, 11025, 1536, 0x19, 0x0},
453 {12000000, 11025, 1088, 0x19, 0x1},
454
455 /* 16k */
456 {12288000, 16000, 768, 0xa, 0x0},
457 {18432000, 16000, 1152, 0xb, 0x0},
458 {12000000, 16000, 750, 0xa, 0x1},
459
460 /* 22.05k */
461 {11289600, 22050, 512, 0x1a, 0x0},
462 {16934400, 22050, 768, 0x1b, 0x0},
463 {12000000, 22050, 544, 0x1b, 0x1},
464
465 /* 32k */
466 {12288000, 32000, 384, 0xc, 0x0},
467 {18432000, 32000, 576, 0xd, 0x0},
468 {12000000, 32000, 375, 0xa, 0x1},
469
470 /* 44.1k */
471 {11289600, 44100, 256, 0x10, 0x0},
472 {16934400, 44100, 384, 0x11, 0x0},
473 {12000000, 44100, 272, 0x11, 0x1},
474
475 /* 48k */
476 {12288000, 48000, 256, 0x0, 0x0},
477 {18432000, 48000, 384, 0x1, 0x0},
478 {12000000, 48000, 250, 0x0, 0x1},
479
480 /* 88.2k */
481 {11289600, 88200, 128, 0x1e, 0x0},
482 {16934400, 88200, 192, 0x1f, 0x0},
483 {12000000, 88200, 136, 0x1f, 0x1},
484
485 /* 96k */
486 {12288000, 96000, 128, 0xe, 0x0},
487 {18432000, 96000, 192, 0xf, 0x0},
488 {12000000, 96000, 125, 0xe, 0x1},
489};
490
491static inline int get_coeff(int mclk, int rate)
492{
493 int i;
494
495 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
496 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
497 return i;
498 }
499
500 return -EINVAL;
501}
502
503/* The set of rates we can generate from the above for each SYSCLK */
504
505static unsigned int rates_12288[] = {
506 8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
507};
508
509static struct snd_pcm_hw_constraint_list constraints_12288 = {
510 .count = ARRAY_SIZE(rates_12288),
511 .list = rates_12288,
512};
513
514static unsigned int rates_112896[] = {
515 8000, 11025, 22050, 44100,
516};
517
518static struct snd_pcm_hw_constraint_list constraints_112896 = {
519 .count = ARRAY_SIZE(rates_112896),
520 .list = rates_112896,
521};
522
523static unsigned int rates_12[] = {
524 8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000,
525 48000, 88235, 96000,
526};
527
528static struct snd_pcm_hw_constraint_list constraints_12 = {
529 .count = ARRAY_SIZE(rates_12),
530 .list = rates_12,
531};
532
533/*
534 * Note that this should be called from init rather than from hw_params.
535 */
536static int wm8988_set_dai_sysclk(struct snd_soc_dai *codec_dai,
537 int clk_id, unsigned int freq, int dir)
538{
539 struct snd_soc_codec *codec = codec_dai->codec;
540 struct wm8988_priv *wm8988 = codec->private_data;
541
542 switch (freq) {
543 case 11289600:
544 case 18432000:
545 case 22579200:
546 case 36864000:
547 wm8988->sysclk_constraints = &constraints_112896;
548 wm8988->sysclk = freq;
549 return 0;
550
551 case 12288000:
552 case 16934400:
553 case 24576000:
554 case 33868800:
555 wm8988->sysclk_constraints = &constraints_12288;
556 wm8988->sysclk = freq;
557 return 0;
558
559 case 12000000:
560 case 24000000:
561 wm8988->sysclk_constraints = &constraints_12;
562 wm8988->sysclk = freq;
563 return 0;
564 }
565 return -EINVAL;
566}
567
568static int wm8988_set_dai_fmt(struct snd_soc_dai *codec_dai,
569 unsigned int fmt)
570{
571 struct snd_soc_codec *codec = codec_dai->codec;
572 u16 iface = 0;
573
574 /* set master/slave audio interface */
575 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
576 case SND_SOC_DAIFMT_CBM_CFM:
577 iface = 0x0040;
578 break;
579 case SND_SOC_DAIFMT_CBS_CFS:
580 break;
581 default:
582 return -EINVAL;
583 }
584
585 /* interface format */
586 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
587 case SND_SOC_DAIFMT_I2S:
588 iface |= 0x0002;
589 break;
590 case SND_SOC_DAIFMT_RIGHT_J:
591 break;
592 case SND_SOC_DAIFMT_LEFT_J:
593 iface |= 0x0001;
594 break;
595 case SND_SOC_DAIFMT_DSP_A:
596 iface |= 0x0003;
597 break;
598 case SND_SOC_DAIFMT_DSP_B:
599 iface |= 0x0013;
600 break;
601 default:
602 return -EINVAL;
603 }
604
605 /* clock inversion */
606 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
607 case SND_SOC_DAIFMT_NB_NF:
608 break;
609 case SND_SOC_DAIFMT_IB_IF:
610 iface |= 0x0090;
611 break;
612 case SND_SOC_DAIFMT_IB_NF:
613 iface |= 0x0080;
614 break;
615 case SND_SOC_DAIFMT_NB_IF:
616 iface |= 0x0010;
617 break;
618 default:
619 return -EINVAL;
620 }
621
622 wm8988_write(codec, WM8988_IFACE, iface);
623 return 0;
624}
625
626static int wm8988_pcm_startup(struct snd_pcm_substream *substream,
627 struct snd_soc_dai *dai)
628{
629 struct snd_soc_codec *codec = dai->codec;
630 struct wm8988_priv *wm8988 = codec->private_data;
631
632 /* The set of sample rates that can be supported depends on the
633 * MCLK supplied to the CODEC - enforce this.
634 */
635 if (!wm8988->sysclk) {
636 dev_err(codec->dev,
637 "No MCLK configured, call set_sysclk() on init\n");
638 return -EINVAL;
639 }
640
641 snd_pcm_hw_constraint_list(substream->runtime, 0,
642 SNDRV_PCM_HW_PARAM_RATE,
643 wm8988->sysclk_constraints);
644
645 return 0;
646}
647
648static int wm8988_pcm_hw_params(struct snd_pcm_substream *substream,
649 struct snd_pcm_hw_params *params,
650 struct snd_soc_dai *dai)
651{
652 struct snd_soc_pcm_runtime *rtd = substream->private_data;
653 struct snd_soc_device *socdev = rtd->socdev;
654 struct snd_soc_codec *codec = socdev->card->codec;
655 struct wm8988_priv *wm8988 = codec->private_data;
656 u16 iface = wm8988_read_reg_cache(codec, WM8988_IFACE) & 0x1f3;
657 u16 srate = wm8988_read_reg_cache(codec, WM8988_SRATE) & 0x180;
658 int coeff;
659
660 coeff = get_coeff(wm8988->sysclk, params_rate(params));
661 if (coeff < 0) {
662 coeff = get_coeff(wm8988->sysclk / 2, params_rate(params));
663 srate |= 0x40;
664 }
665 if (coeff < 0) {
666 dev_err(codec->dev,
667 "Unable to configure sample rate %dHz with %dHz MCLK\n",
668 params_rate(params), wm8988->sysclk);
669 return coeff;
670 }
671
672 /* bit size */
673 switch (params_format(params)) {
674 case SNDRV_PCM_FORMAT_S16_LE:
675 break;
676 case SNDRV_PCM_FORMAT_S20_3LE:
677 iface |= 0x0004;
678 break;
679 case SNDRV_PCM_FORMAT_S24_LE:
680 iface |= 0x0008;
681 break;
682 case SNDRV_PCM_FORMAT_S32_LE:
683 iface |= 0x000c;
684 break;
685 }
686
687 /* set iface & srate */
688 wm8988_write(codec, WM8988_IFACE, iface);
689 if (coeff >= 0)
690 wm8988_write(codec, WM8988_SRATE, srate |
691 (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
692
693 return 0;
694}
695
696static int wm8988_mute(struct snd_soc_dai *dai, int mute)
697{
698 struct snd_soc_codec *codec = dai->codec;
699 u16 mute_reg = wm8988_read_reg_cache(codec, WM8988_ADCDAC) & 0xfff7;
700
701 if (mute)
702 wm8988_write(codec, WM8988_ADCDAC, mute_reg | 0x8);
703 else
704 wm8988_write(codec, WM8988_ADCDAC, mute_reg);
705 return 0;
706}
707
708static int wm8988_set_bias_level(struct snd_soc_codec *codec,
709 enum snd_soc_bias_level level)
710{
711 u16 pwr_reg = wm8988_read_reg_cache(codec, WM8988_PWR1) & ~0x1c1;
712
713 switch (level) {
714 case SND_SOC_BIAS_ON:
715 break;
716
717 case SND_SOC_BIAS_PREPARE:
718 /* VREF, VMID=2x50k, digital enabled */
719 wm8988_write(codec, WM8988_PWR1, pwr_reg | 0x00c0);
720 break;
721
722 case SND_SOC_BIAS_STANDBY:
723 if (codec->bias_level == SND_SOC_BIAS_OFF) {
724 /* VREF, VMID=2x5k */
725 wm8988_write(codec, WM8988_PWR1, pwr_reg | 0x1c1);
726
727 /* Charge caps */
728 msleep(100);
729 }
730
731 /* VREF, VMID=2*500k, digital stopped */
732 wm8988_write(codec, WM8988_PWR1, pwr_reg | 0x0141);
733 break;
734
735 case SND_SOC_BIAS_OFF:
736 wm8988_write(codec, WM8988_PWR1, 0x0000);
737 break;
738 }
739 codec->bias_level = level;
740 return 0;
741}
742
743#define WM8988_RATES SNDRV_PCM_RATE_8000_96000
744
745#define WM8988_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
746 SNDRV_PCM_FMTBIT_S24_LE)
747
748static struct snd_soc_dai_ops wm8988_ops = {
749 .startup = wm8988_pcm_startup,
750 .hw_params = wm8988_pcm_hw_params,
751 .set_fmt = wm8988_set_dai_fmt,
752 .set_sysclk = wm8988_set_dai_sysclk,
753 .digital_mute = wm8988_mute,
754};
755
756struct snd_soc_dai wm8988_dai = {
757 .name = "WM8988",
758 .playback = {
759 .stream_name = "Playback",
760 .channels_min = 1,
761 .channels_max = 2,
762 .rates = WM8988_RATES,
763 .formats = WM8988_FORMATS,
764 },
765 .capture = {
766 .stream_name = "Capture",
767 .channels_min = 1,
768 .channels_max = 2,
769 .rates = WM8988_RATES,
770 .formats = WM8988_FORMATS,
771 },
772 .ops = &wm8988_ops,
773 .symmetric_rates = 1,
774};
775EXPORT_SYMBOL_GPL(wm8988_dai);
776
777static int wm8988_suspend(struct platform_device *pdev, pm_message_t state)
778{
779 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
780 struct snd_soc_codec *codec = socdev->card->codec;
781
782 wm8988_set_bias_level(codec, SND_SOC_BIAS_OFF);
783 return 0;
784}
785
786static int wm8988_resume(struct platform_device *pdev)
787{
788 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
789 struct snd_soc_codec *codec = socdev->card->codec;
790 int i;
791 u8 data[2];
792 u16 *cache = codec->reg_cache;
793
794 /* Sync reg_cache with the hardware */
795 for (i = 0; i < WM8988_NUM_REG; i++) {
796 if (i == WM8988_RESET)
797 continue;
798 data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
799 data[1] = cache[i] & 0x00ff;
800 codec->hw_write(codec->control_data, data, 2);
801 }
802
803 wm8988_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
804
805 return 0;
806}
807
808static struct snd_soc_codec *wm8988_codec;
809
810static int wm8988_probe(struct platform_device *pdev)
811{
812 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
813 struct snd_soc_codec *codec;
814 int ret = 0;
815
816 if (wm8988_codec == NULL) {
817 dev_err(&pdev->dev, "Codec device not registered\n");
818 return -ENODEV;
819 }
820
821 socdev->card->codec = wm8988_codec;
822 codec = wm8988_codec;
823
824 /* register pcms */
825 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
826 if (ret < 0) {
827 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
828 goto pcm_err;
829 }
830
831 snd_soc_add_controls(codec, wm8988_snd_controls,
832 ARRAY_SIZE(wm8988_snd_controls));
833 snd_soc_dapm_new_controls(codec, wm8988_dapm_widgets,
834 ARRAY_SIZE(wm8988_dapm_widgets));
835 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
836 snd_soc_dapm_new_widgets(codec);
837
838 ret = snd_soc_init_card(socdev);
839 if (ret < 0) {
840 dev_err(codec->dev, "failed to register card: %d\n", ret);
841 goto card_err;
842 }
843
844 return ret;
845
846card_err:
847 snd_soc_free_pcms(socdev);
848 snd_soc_dapm_free(socdev);
849pcm_err:
850 return ret;
851}
852
853static int wm8988_remove(struct platform_device *pdev)
854{
855 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
856
857 snd_soc_free_pcms(socdev);
858 snd_soc_dapm_free(socdev);
859
860 return 0;
861}
862
863struct snd_soc_codec_device soc_codec_dev_wm8988 = {
864 .probe = wm8988_probe,
865 .remove = wm8988_remove,
866 .suspend = wm8988_suspend,
867 .resume = wm8988_resume,
868};
869EXPORT_SYMBOL_GPL(soc_codec_dev_wm8988);
870
871static int wm8988_register(struct wm8988_priv *wm8988)
872{
873 struct snd_soc_codec *codec = &wm8988->codec;
874 int ret;
875 u16 reg;
876
877 if (wm8988_codec) {
878 dev_err(codec->dev, "Another WM8988 is registered\n");
879 ret = -EINVAL;
880 goto err;
881 }
882
883 mutex_init(&codec->mutex);
884 INIT_LIST_HEAD(&codec->dapm_widgets);
885 INIT_LIST_HEAD(&codec->dapm_paths);
886
887 codec->private_data = wm8988;
888 codec->name = "WM8988";
889 codec->owner = THIS_MODULE;
890 codec->read = wm8988_read_reg_cache;
891 codec->write = wm8988_write;
892 codec->dai = &wm8988_dai;
893 codec->num_dai = 1;
894 codec->reg_cache_size = ARRAY_SIZE(wm8988->reg_cache);
895 codec->reg_cache = &wm8988->reg_cache;
896 codec->bias_level = SND_SOC_BIAS_OFF;
897 codec->set_bias_level = wm8988_set_bias_level;
898
899 memcpy(codec->reg_cache, wm8988_reg,
900 sizeof(wm8988_reg));
901
902 ret = wm8988_reset(codec);
903 if (ret < 0) {
904 dev_err(codec->dev, "Failed to issue reset\n");
905 return ret;
906 }
907
908 /* set the update bits (we always update left then right) */
909 reg = wm8988_read_reg_cache(codec, WM8988_RADC);
910 wm8988_write(codec, WM8988_RADC, reg | 0x100);
911 reg = wm8988_read_reg_cache(codec, WM8988_RDAC);
912 wm8988_write(codec, WM8988_RDAC, reg | 0x0100);
913 reg = wm8988_read_reg_cache(codec, WM8988_ROUT1V);
914 wm8988_write(codec, WM8988_ROUT1V, reg | 0x0100);
915 reg = wm8988_read_reg_cache(codec, WM8988_ROUT2V);
916 wm8988_write(codec, WM8988_ROUT2V, reg | 0x0100);
917 reg = wm8988_read_reg_cache(codec, WM8988_RINVOL);
918 wm8988_write(codec, WM8988_RINVOL, reg | 0x0100);
919
920 wm8988_set_bias_level(&wm8988->codec, SND_SOC_BIAS_STANDBY);
921
922 wm8988_dai.dev = codec->dev;
923
924 wm8988_codec = codec;
925
926 ret = snd_soc_register_codec(codec);
927 if (ret != 0) {
928 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
929 return ret;
930 }
931
932 ret = snd_soc_register_dai(&wm8988_dai);
933 if (ret != 0) {
934 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
935 snd_soc_unregister_codec(codec);
936 return ret;
937 }
938
939 return 0;
940
941err:
942 kfree(wm8988);
943 return ret;
944}
945
946static void wm8988_unregister(struct wm8988_priv *wm8988)
947{
948 wm8988_set_bias_level(&wm8988->codec, SND_SOC_BIAS_OFF);
949 snd_soc_unregister_dai(&wm8988_dai);
950 snd_soc_unregister_codec(&wm8988->codec);
951 kfree(wm8988);
952 wm8988_codec = NULL;
953}
954
955#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
956static int wm8988_i2c_probe(struct i2c_client *i2c,
957 const struct i2c_device_id *id)
958{
959 struct wm8988_priv *wm8988;
960 struct snd_soc_codec *codec;
961
962 wm8988 = kzalloc(sizeof(struct wm8988_priv), GFP_KERNEL);
963 if (wm8988 == NULL)
964 return -ENOMEM;
965
966 codec = &wm8988->codec;
967 codec->hw_write = (hw_write_t)i2c_master_send;
968
969 i2c_set_clientdata(i2c, wm8988);
970 codec->control_data = i2c;
971
972 codec->dev = &i2c->dev;
973
974 return wm8988_register(wm8988);
975}
976
977static int wm8988_i2c_remove(struct i2c_client *client)
978{
979 struct wm8988_priv *wm8988 = i2c_get_clientdata(client);
980 wm8988_unregister(wm8988);
981 return 0;
982}
983
984static const struct i2c_device_id wm8988_i2c_id[] = {
985 { "wm8988", 0 },
986 { }
987};
988MODULE_DEVICE_TABLE(i2c, wm8988_i2c_id);
989
990static struct i2c_driver wm8988_i2c_driver = {
991 .driver = {
992 .name = "WM8988",
993 .owner = THIS_MODULE,
994 },
995 .probe = wm8988_i2c_probe,
996 .remove = wm8988_i2c_remove,
997 .id_table = wm8988_i2c_id,
998};
999#endif
1000
1001#if defined(CONFIG_SPI_MASTER)
1002static int wm8988_spi_write(struct spi_device *spi, const char *data, int len)
1003{
1004 struct spi_transfer t;
1005 struct spi_message m;
1006 u8 msg[2];
1007
1008 if (len <= 0)
1009 return 0;
1010
1011 msg[0] = data[0];
1012 msg[1] = data[1];
1013
1014 spi_message_init(&m);
1015 memset(&t, 0, (sizeof t));
1016
1017 t.tx_buf = &msg[0];
1018 t.len = len;
1019
1020 spi_message_add_tail(&t, &m);
1021 spi_sync(spi, &m);
1022
1023 return len;
1024}
1025
1026static int __devinit wm8988_spi_probe(struct spi_device *spi)
1027{
1028 struct wm8988_priv *wm8988;
1029 struct snd_soc_codec *codec;
1030
1031 wm8988 = kzalloc(sizeof(struct wm8988_priv), GFP_KERNEL);
1032 if (wm8988 == NULL)
1033 return -ENOMEM;
1034
1035 codec = &wm8988->codec;
1036 codec->hw_write = (hw_write_t)wm8988_spi_write;
1037 codec->control_data = spi;
1038 codec->dev = &spi->dev;
1039
1040 spi->dev.driver_data = wm8988;
1041
1042 return wm8988_register(wm8988);
1043}
1044
1045static int __devexit wm8988_spi_remove(struct spi_device *spi)
1046{
1047 struct wm8988_priv *wm8988 = spi->dev.driver_data;
1048
1049 wm8988_unregister(wm8988);
1050
1051 return 0;
1052}
1053
1054static struct spi_driver wm8988_spi_driver = {
1055 .driver = {
1056 .name = "wm8988",
1057 .bus = &spi_bus_type,
1058 .owner = THIS_MODULE,
1059 },
1060 .probe = wm8988_spi_probe,
1061 .remove = __devexit_p(wm8988_spi_remove),
1062};
1063#endif
1064
1065static int __init wm8988_modinit(void)
1066{
1067 int ret;
1068
1069#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1070 ret = i2c_add_driver(&wm8988_i2c_driver);
1071 if (ret != 0)
1072 pr_err("WM8988: Unable to register I2C driver: %d\n", ret);
1073#endif
1074#if defined(CONFIG_SPI_MASTER)
1075 ret = spi_register_driver(&wm8988_spi_driver);
1076 if (ret != 0)
1077 pr_err("WM8988: Unable to register SPI driver: %d\n", ret);
1078#endif
1079 return ret;
1080}
1081module_init(wm8988_modinit);
1082
1083static void __exit wm8988_exit(void)
1084{
1085#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1086 i2c_del_driver(&wm8988_i2c_driver);
1087#endif
1088#if defined(CONFIG_SPI_MASTER)
1089 spi_unregister_driver(&wm8988_spi_driver);
1090#endif
1091}
1092module_exit(wm8988_exit);
1093
1094
1095MODULE_DESCRIPTION("ASoC WM8988 driver");
1096MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1097MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8988.h b/sound/soc/codecs/wm8988.h
new file mode 100644
index 000000000000..4552d37fdd41
--- /dev/null
+++ b/sound/soc/codecs/wm8988.h
@@ -0,0 +1,60 @@
1/*
2 * Copyright 2005 Openedhand Ltd.
3 *
4 * Author: Richard Purdie <richard@openedhand.com>
5 *
6 * Based on WM8753.h
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#ifndef _WM8988_H
15#define _WM8988_H
16
17/* WM8988 register space */
18
19#define WM8988_LINVOL 0x00
20#define WM8988_RINVOL 0x01
21#define WM8988_LOUT1V 0x02
22#define WM8988_ROUT1V 0x03
23#define WM8988_ADCDAC 0x05
24#define WM8988_IFACE 0x07
25#define WM8988_SRATE 0x08
26#define WM8988_LDAC 0x0a
27#define WM8988_RDAC 0x0b
28#define WM8988_BASS 0x0c
29#define WM8988_TREBLE 0x0d
30#define WM8988_RESET 0x0f
31#define WM8988_3D 0x10
32#define WM8988_ALC1 0x11
33#define WM8988_ALC2 0x12
34#define WM8988_ALC3 0x13
35#define WM8988_NGATE 0x14
36#define WM8988_LADC 0x15
37#define WM8988_RADC 0x16
38#define WM8988_ADCTL1 0x17
39#define WM8988_ADCTL2 0x18
40#define WM8988_PWR1 0x19
41#define WM8988_PWR2 0x1a
42#define WM8988_ADCTL3 0x1b
43#define WM8988_ADCIN 0x1f
44#define WM8988_LADCIN 0x20
45#define WM8988_RADCIN 0x21
46#define WM8988_LOUTM1 0x22
47#define WM8988_LOUTM2 0x23
48#define WM8988_ROUTM1 0x24
49#define WM8988_ROUTM2 0x25
50#define WM8988_LOUT2V 0x28
51#define WM8988_ROUT2V 0x29
52#define WM8988_LPPB 0x43
53#define WM8988_NUM_REG 0x44
54
55#define WM8988_SYSCLK 0
56
57extern struct snd_soc_dai wm8988_dai;
58extern struct snd_soc_codec_device soc_codec_dev_wm8988;
59
60#endif
diff --git a/sound/soc/codecs/wm8990.c b/sound/soc/codecs/wm8990.c
index 40cd274eb1ef..d029818350e9 100644
--- a/sound/soc/codecs/wm8990.c
+++ b/sound/soc/codecs/wm8990.c
@@ -998,7 +998,7 @@ static void pll_factors(struct _pll_div *pll_div, unsigned int target,
998 998
999 if ((Ndiv < 6) || (Ndiv > 12)) 999 if ((Ndiv < 6) || (Ndiv > 12))
1000 printk(KERN_WARNING 1000 printk(KERN_WARNING
1001 "WM8990 N value outwith recommended range! N = %d\n", Ndiv); 1001 "WM8990 N value outwith recommended range! N = %u\n", Ndiv);
1002 1002
1003 pll_div->n = Ndiv; 1003 pll_div->n = Ndiv;
1004 Nmod = target % source; 1004 Nmod = target % source;
diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c
new file mode 100644
index 000000000000..86fc57e25f97
--- /dev/null
+++ b/sound/soc/codecs/wm9081.c
@@ -0,0 +1,1534 @@
1/*
2 * wm9081.c -- WM9081 ALSA SoC Audio driver
3 *
4 * Author: Mark Brown
5 *
6 * Copyright 2009 Wolfson Microelectronics plc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
27#include <sound/tlv.h>
28
29#include <sound/wm9081.h>
30#include "wm9081.h"
31
32static u16 wm9081_reg_defaults[] = {
33 0x0000, /* R0 - Software Reset */
34 0x0000, /* R1 */
35 0x00B9, /* R2 - Analogue Lineout */
36 0x00B9, /* R3 - Analogue Speaker PGA */
37 0x0001, /* R4 - VMID Control */
38 0x0068, /* R5 - Bias Control 1 */
39 0x0000, /* R6 */
40 0x0000, /* R7 - Analogue Mixer */
41 0x0000, /* R8 - Anti Pop Control */
42 0x01DB, /* R9 - Analogue Speaker 1 */
43 0x0018, /* R10 - Analogue Speaker 2 */
44 0x0180, /* R11 - Power Management */
45 0x0000, /* R12 - Clock Control 1 */
46 0x0038, /* R13 - Clock Control 2 */
47 0x4000, /* R14 - Clock Control 3 */
48 0x0000, /* R15 */
49 0x0000, /* R16 - FLL Control 1 */
50 0x0200, /* R17 - FLL Control 2 */
51 0x0000, /* R18 - FLL Control 3 */
52 0x0204, /* R19 - FLL Control 4 */
53 0x0000, /* R20 - FLL Control 5 */
54 0x0000, /* R21 */
55 0x0000, /* R22 - Audio Interface 1 */
56 0x0002, /* R23 - Audio Interface 2 */
57 0x0008, /* R24 - Audio Interface 3 */
58 0x0022, /* R25 - Audio Interface 4 */
59 0x0000, /* R26 - Interrupt Status */
60 0x0006, /* R27 - Interrupt Status Mask */
61 0x0000, /* R28 - Interrupt Polarity */
62 0x0000, /* R29 - Interrupt Control */
63 0x00C0, /* R30 - DAC Digital 1 */
64 0x0008, /* R31 - DAC Digital 2 */
65 0x09AF, /* R32 - DRC 1 */
66 0x4201, /* R33 - DRC 2 */
67 0x0000, /* R34 - DRC 3 */
68 0x0000, /* R35 - DRC 4 */
69 0x0000, /* R36 */
70 0x0000, /* R37 */
71 0x0000, /* R38 - Write Sequencer 1 */
72 0x0000, /* R39 - Write Sequencer 2 */
73 0x0002, /* R40 - MW Slave 1 */
74 0x0000, /* R41 */
75 0x0000, /* R42 - EQ 1 */
76 0x0000, /* R43 - EQ 2 */
77 0x0FCA, /* R44 - EQ 3 */
78 0x0400, /* R45 - EQ 4 */
79 0x00B8, /* R46 - EQ 5 */
80 0x1EB5, /* R47 - EQ 6 */
81 0xF145, /* R48 - EQ 7 */
82 0x0B75, /* R49 - EQ 8 */
83 0x01C5, /* R50 - EQ 9 */
84 0x169E, /* R51 - EQ 10 */
85 0xF829, /* R52 - EQ 11 */
86 0x07AD, /* R53 - EQ 12 */
87 0x1103, /* R54 - EQ 13 */
88 0x1C58, /* R55 - EQ 14 */
89 0xF373, /* R56 - EQ 15 */
90 0x0A54, /* R57 - EQ 16 */
91 0x0558, /* R58 - EQ 17 */
92 0x0564, /* R59 - EQ 18 */
93 0x0559, /* R60 - EQ 19 */
94 0x4000, /* R61 - EQ 20 */
95};
96
97static struct {
98 int ratio;
99 int clk_sys_rate;
100} clk_sys_rates[] = {
101 { 64, 0 },
102 { 128, 1 },
103 { 192, 2 },
104 { 256, 3 },
105 { 384, 4 },
106 { 512, 5 },
107 { 768, 6 },
108 { 1024, 7 },
109 { 1408, 8 },
110 { 1536, 9 },
111};
112
113static struct {
114 int rate;
115 int sample_rate;
116} sample_rates[] = {
117 { 8000, 0 },
118 { 11025, 1 },
119 { 12000, 2 },
120 { 16000, 3 },
121 { 22050, 4 },
122 { 24000, 5 },
123 { 32000, 6 },
124 { 44100, 7 },
125 { 48000, 8 },
126 { 88200, 9 },
127 { 96000, 10 },
128};
129
130static struct {
131 int div; /* *10 due to .5s */
132 int bclk_div;
133} bclk_divs[] = {
134 { 10, 0 },
135 { 15, 1 },
136 { 20, 2 },
137 { 30, 3 },
138 { 40, 4 },
139 { 50, 5 },
140 { 55, 6 },
141 { 60, 7 },
142 { 80, 8 },
143 { 100, 9 },
144 { 110, 10 },
145 { 120, 11 },
146 { 160, 12 },
147 { 200, 13 },
148 { 220, 14 },
149 { 240, 15 },
150 { 250, 16 },
151 { 300, 17 },
152 { 320, 18 },
153 { 440, 19 },
154 { 480, 20 },
155};
156
157struct wm9081_priv {
158 struct snd_soc_codec codec;
159 u16 reg_cache[WM9081_MAX_REGISTER + 1];
160 int sysclk_source;
161 int mclk_rate;
162 int sysclk_rate;
163 int fs;
164 int bclk;
165 int master;
166 int fll_fref;
167 int fll_fout;
168 struct wm9081_retune_mobile_config *retune;
169};
170
171static int wm9081_reg_is_volatile(int reg)
172{
173 switch (reg) {
174 default:
175 return 0;
176 }
177}
178
179static unsigned int wm9081_read_reg_cache(struct snd_soc_codec *codec,
180 unsigned int reg)
181{
182 u16 *cache = codec->reg_cache;
183 BUG_ON(reg > WM9081_MAX_REGISTER);
184 return cache[reg];
185}
186
187static unsigned int wm9081_read_hw(struct snd_soc_codec *codec, u8 reg)
188{
189 struct i2c_msg xfer[2];
190 u16 data;
191 int ret;
192 struct i2c_client *client = codec->control_data;
193
194 BUG_ON(reg > WM9081_MAX_REGISTER);
195
196 /* Write register */
197 xfer[0].addr = client->addr;
198 xfer[0].flags = 0;
199 xfer[0].len = 1;
200 xfer[0].buf = &reg;
201
202 /* Read data */
203 xfer[1].addr = client->addr;
204 xfer[1].flags = I2C_M_RD;
205 xfer[1].len = 2;
206 xfer[1].buf = (u8 *)&data;
207
208 ret = i2c_transfer(client->adapter, xfer, 2);
209 if (ret != 2) {
210 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
211 return 0;
212 }
213
214 return (data >> 8) | ((data & 0xff) << 8);
215}
216
217static unsigned int wm9081_read(struct snd_soc_codec *codec, unsigned int reg)
218{
219 if (wm9081_reg_is_volatile(reg))
220 return wm9081_read_hw(codec, reg);
221 else
222 return wm9081_read_reg_cache(codec, reg);
223}
224
225static int wm9081_write(struct snd_soc_codec *codec, unsigned int reg,
226 unsigned int value)
227{
228 u16 *cache = codec->reg_cache;
229 u8 data[3];
230
231 BUG_ON(reg > WM9081_MAX_REGISTER);
232
233 if (!wm9081_reg_is_volatile(reg))
234 cache[reg] = value;
235
236 data[0] = reg;
237 data[1] = value >> 8;
238 data[2] = value & 0x00ff;
239
240 if (codec->hw_write(codec->control_data, data, 3) == 3)
241 return 0;
242 else
243 return -EIO;
244}
245
246static int wm9081_reset(struct snd_soc_codec *codec)
247{
248 return wm9081_write(codec, WM9081_SOFTWARE_RESET, 0);
249}
250
251static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
252static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
253static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
254static unsigned int drc_max_tlv[] = {
255 TLV_DB_RANGE_HEAD(4),
256 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
257 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
258 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
259 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
260};
261static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
262static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
263
264static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
265
266static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
267static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
268static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
269
270static const char *drc_high_text[] = {
271 "1",
272 "1/2",
273 "1/4",
274 "1/8",
275 "1/16",
276 "0",
277};
278
279static const struct soc_enum drc_high =
280 SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text);
281
282static const char *drc_low_text[] = {
283 "1",
284 "1/2",
285 "1/4",
286 "1/8",
287 "0",
288};
289
290static const struct soc_enum drc_low =
291 SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text);
292
293static const char *drc_atk_text[] = {
294 "181us",
295 "181us",
296 "363us",
297 "726us",
298 "1.45ms",
299 "2.9ms",
300 "5.8ms",
301 "11.6ms",
302 "23.2ms",
303 "46.4ms",
304 "92.8ms",
305 "185.6ms",
306};
307
308static const struct soc_enum drc_atk =
309 SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text);
310
311static const char *drc_dcy_text[] = {
312 "186ms",
313 "372ms",
314 "743ms",
315 "1.49s",
316 "2.97s",
317 "5.94s",
318 "11.89s",
319 "23.78s",
320 "47.56s",
321};
322
323static const struct soc_enum drc_dcy =
324 SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text);
325
326static const char *drc_qr_dcy_text[] = {
327 "0.725ms",
328 "1.45ms",
329 "5.8ms",
330};
331
332static const struct soc_enum drc_qr_dcy =
333 SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text);
334
335static const char *dac_deemph_text[] = {
336 "None",
337 "32kHz",
338 "44.1kHz",
339 "48kHz",
340};
341
342static const struct soc_enum dac_deemph =
343 SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text);
344
345static const char *speaker_mode_text[] = {
346 "Class D",
347 "Class AB",
348};
349
350static const struct soc_enum speaker_mode =
351 SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text);
352
353static int speaker_mode_get(struct snd_kcontrol *kcontrol,
354 struct snd_ctl_elem_value *ucontrol)
355{
356 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
357 unsigned int reg;
358
359 reg = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_2);
360 if (reg & WM9081_SPK_MODE)
361 ucontrol->value.integer.value[0] = 1;
362 else
363 ucontrol->value.integer.value[0] = 0;
364
365 return 0;
366}
367
368/*
369 * Stop any attempts to change speaker mode while the speaker is enabled.
370 *
371 * We also have some special anti-pop controls dependant on speaker
372 * mode which must be changed along with the mode.
373 */
374static int speaker_mode_put(struct snd_kcontrol *kcontrol,
375 struct snd_ctl_elem_value *ucontrol)
376{
377 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
378 unsigned int reg_pwr = wm9081_read(codec, WM9081_POWER_MANAGEMENT);
379 unsigned int reg2 = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_2);
380
381 /* Are we changing anything? */
382 if (ucontrol->value.integer.value[0] ==
383 ((reg2 & WM9081_SPK_MODE) != 0))
384 return 0;
385
386 /* Don't try to change modes while enabled */
387 if (reg_pwr & WM9081_SPK_ENA)
388 return -EINVAL;
389
390 if (ucontrol->value.integer.value[0]) {
391 /* Class AB */
392 reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
393 reg2 |= WM9081_SPK_MODE;
394 } else {
395 /* Class D */
396 reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
397 reg2 &= ~WM9081_SPK_MODE;
398 }
399
400 wm9081_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
401
402 return 0;
403}
404
405static const struct snd_kcontrol_new wm9081_snd_controls[] = {
406SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
407SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
408
409SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
410
411SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
412SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
413SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
414
415SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
416SOC_ENUM("DRC High Slope", drc_high),
417SOC_ENUM("DRC Low Slope", drc_low),
418SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
419SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
420SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
421SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
422SOC_ENUM("DRC Attack", drc_atk),
423SOC_ENUM("DRC Decay", drc_dcy),
424SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
425SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
426SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
427SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
428
429SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
430
431SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
432SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
433SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
434SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
435SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
436 out_tlv),
437SOC_ENUM("DAC Deemphasis", dac_deemph),
438SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
439};
440
441static const struct snd_kcontrol_new wm9081_eq_controls[] = {
442SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
443SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
444SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
445SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
446SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
447};
448
449static const struct snd_kcontrol_new mixer[] = {
450SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
451SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
452SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
453};
454
455static int speaker_event(struct snd_soc_dapm_widget *w,
456 struct snd_kcontrol *kcontrol, int event)
457{
458 struct snd_soc_codec *codec = w->codec;
459 unsigned int reg = wm9081_read(codec, WM9081_POWER_MANAGEMENT);
460
461 switch (event) {
462 case SND_SOC_DAPM_POST_PMU:
463 reg |= WM9081_SPK_ENA;
464 break;
465
466 case SND_SOC_DAPM_PRE_PMD:
467 reg &= ~WM9081_SPK_ENA;
468 break;
469 }
470
471 wm9081_write(codec, WM9081_POWER_MANAGEMENT, reg);
472
473 return 0;
474}
475
476struct _fll_div {
477 u16 fll_fratio;
478 u16 fll_outdiv;
479 u16 fll_clk_ref_div;
480 u16 n;
481 u16 k;
482};
483
484/* The size in bits of the FLL divide multiplied by 10
485 * to allow rounding later */
486#define FIXED_FLL_SIZE ((1 << 16) * 10)
487
488static struct {
489 unsigned int min;
490 unsigned int max;
491 u16 fll_fratio;
492 int ratio;
493} fll_fratios[] = {
494 { 0, 64000, 4, 16 },
495 { 64000, 128000, 3, 8 },
496 { 128000, 256000, 2, 4 },
497 { 256000, 1000000, 1, 2 },
498 { 1000000, 13500000, 0, 1 },
499};
500
501static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
502 unsigned int Fout)
503{
504 u64 Kpart;
505 unsigned int K, Ndiv, Nmod, target;
506 unsigned int div;
507 int i;
508
509 /* Fref must be <=13.5MHz */
510 div = 1;
511 while ((Fref / div) > 13500000) {
512 div *= 2;
513
514 if (div > 8) {
515 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
516 Fref);
517 return -EINVAL;
518 }
519 }
520 fll_div->fll_clk_ref_div = div / 2;
521
522 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
523
524 /* Apply the division for our remaining calculations */
525 Fref /= div;
526
527 /* Fvco should be 90-100MHz; don't check the upper bound */
528 div = 0;
529 target = Fout * 2;
530 while (target < 90000000) {
531 div++;
532 target *= 2;
533 if (div > 7) {
534 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
535 Fout);
536 return -EINVAL;
537 }
538 }
539 fll_div->fll_outdiv = div;
540
541 pr_debug("Fvco=%dHz\n", target);
542
543 /* Find an appropraite FLL_FRATIO and factor it out of the target */
544 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
545 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
546 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
547 target /= fll_fratios[i].ratio;
548 break;
549 }
550 }
551 if (i == ARRAY_SIZE(fll_fratios)) {
552 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
553 return -EINVAL;
554 }
555
556 /* Now, calculate N.K */
557 Ndiv = target / Fref;
558
559 fll_div->n = Ndiv;
560 Nmod = target % Fref;
561 pr_debug("Nmod=%d\n", Nmod);
562
563 /* Calculate fractional part - scale up so we can round. */
564 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
565
566 do_div(Kpart, Fref);
567
568 K = Kpart & 0xFFFFFFFF;
569
570 if ((K % 10) >= 5)
571 K += 5;
572
573 /* Move down to proper range now rounding is done */
574 fll_div->k = K / 10;
575
576 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
577 fll_div->n, fll_div->k,
578 fll_div->fll_fratio, fll_div->fll_outdiv,
579 fll_div->fll_clk_ref_div);
580
581 return 0;
582}
583
584static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
585 unsigned int Fref, unsigned int Fout)
586{
587 struct wm9081_priv *wm9081 = codec->private_data;
588 u16 reg1, reg4, reg5;
589 struct _fll_div fll_div;
590 int ret;
591 int clk_sys_reg;
592
593 /* Any change? */
594 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
595 return 0;
596
597 /* Disable the FLL */
598 if (Fout == 0) {
599 dev_dbg(codec->dev, "FLL disabled\n");
600 wm9081->fll_fref = 0;
601 wm9081->fll_fout = 0;
602
603 return 0;
604 }
605
606 ret = fll_factors(&fll_div, Fref, Fout);
607 if (ret != 0)
608 return ret;
609
610 reg5 = wm9081_read(codec, WM9081_FLL_CONTROL_5);
611 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
612
613 switch (fll_id) {
614 case WM9081_SYSCLK_FLL_MCLK:
615 reg5 |= 0x1;
616 break;
617
618 default:
619 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
620 return -EINVAL;
621 }
622
623 /* Disable CLK_SYS while we reconfigure */
624 clk_sys_reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_3);
625 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
626 wm9081_write(codec, WM9081_CLOCK_CONTROL_3,
627 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
628
629 /* Any FLL configuration change requires that the FLL be
630 * disabled first. */
631 reg1 = wm9081_read(codec, WM9081_FLL_CONTROL_1);
632 reg1 &= ~WM9081_FLL_ENA;
633 wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1);
634
635 /* Apply the configuration */
636 if (fll_div.k)
637 reg1 |= WM9081_FLL_FRAC_MASK;
638 else
639 reg1 &= ~WM9081_FLL_FRAC_MASK;
640 wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1);
641
642 wm9081_write(codec, WM9081_FLL_CONTROL_2,
643 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
644 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
645 wm9081_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
646
647 reg4 = wm9081_read(codec, WM9081_FLL_CONTROL_4);
648 reg4 &= ~WM9081_FLL_N_MASK;
649 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
650 wm9081_write(codec, WM9081_FLL_CONTROL_4, reg4);
651
652 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
653 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
654 wm9081_write(codec, WM9081_FLL_CONTROL_5, reg5);
655
656 /* Enable the FLL */
657 wm9081_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
658
659 /* Then bring CLK_SYS up again if it was disabled */
660 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
661 wm9081_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
662
663 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
664
665 wm9081->fll_fref = Fref;
666 wm9081->fll_fout = Fout;
667
668 return 0;
669}
670
671static int configure_clock(struct snd_soc_codec *codec)
672{
673 struct wm9081_priv *wm9081 = codec->private_data;
674 int new_sysclk, i, target;
675 unsigned int reg;
676 int ret = 0;
677 int mclkdiv = 0;
678 int fll = 0;
679
680 switch (wm9081->sysclk_source) {
681 case WM9081_SYSCLK_MCLK:
682 if (wm9081->mclk_rate > 12225000) {
683 mclkdiv = 1;
684 wm9081->sysclk_rate = wm9081->mclk_rate / 2;
685 } else {
686 wm9081->sysclk_rate = wm9081->mclk_rate;
687 }
688 wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
689 break;
690
691 case WM9081_SYSCLK_FLL_MCLK:
692 /* If we have a sample rate calculate a CLK_SYS that
693 * gives us a suitable DAC configuration, plus BCLK.
694 * Ideally we would check to see if we can clock
695 * directly from MCLK and only use the FLL if this is
696 * not the case, though care must be taken with free
697 * running mode.
698 */
699 if (wm9081->master && wm9081->bclk) {
700 /* Make sure we can generate CLK_SYS and BCLK
701 * and that we've got 3MHz for optimal
702 * performance. */
703 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
704 target = wm9081->fs * clk_sys_rates[i].ratio;
705 new_sysclk = target;
706 if (target >= wm9081->bclk &&
707 target > 3000000)
708 break;
709 }
710 } else if (wm9081->fs) {
711 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
712 new_sysclk = clk_sys_rates[i].ratio
713 * wm9081->fs;
714 if (new_sysclk > 3000000)
715 break;
716 }
717 } else {
718 new_sysclk = 12288000;
719 }
720
721 ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
722 wm9081->mclk_rate, new_sysclk);
723 if (ret == 0) {
724 wm9081->sysclk_rate = new_sysclk;
725
726 /* Switch SYSCLK over to FLL */
727 fll = 1;
728 } else {
729 wm9081->sysclk_rate = wm9081->mclk_rate;
730 }
731 break;
732
733 default:
734 return -EINVAL;
735 }
736
737 reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_1);
738 if (mclkdiv)
739 reg |= WM9081_MCLKDIV2;
740 else
741 reg &= ~WM9081_MCLKDIV2;
742 wm9081_write(codec, WM9081_CLOCK_CONTROL_1, reg);
743
744 reg = wm9081_read(codec, WM9081_CLOCK_CONTROL_3);
745 if (fll)
746 reg |= WM9081_CLK_SRC_SEL;
747 else
748 reg &= ~WM9081_CLK_SRC_SEL;
749 wm9081_write(codec, WM9081_CLOCK_CONTROL_3, reg);
750
751 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
752
753 return ret;
754}
755
756static int clk_sys_event(struct snd_soc_dapm_widget *w,
757 struct snd_kcontrol *kcontrol, int event)
758{
759 struct snd_soc_codec *codec = w->codec;
760 struct wm9081_priv *wm9081 = codec->private_data;
761
762 /* This should be done on init() for bypass paths */
763 switch (wm9081->sysclk_source) {
764 case WM9081_SYSCLK_MCLK:
765 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
766 break;
767 case WM9081_SYSCLK_FLL_MCLK:
768 dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
769 wm9081->mclk_rate);
770 break;
771 default:
772 dev_err(codec->dev, "System clock not configured\n");
773 return -EINVAL;
774 }
775
776 switch (event) {
777 case SND_SOC_DAPM_PRE_PMU:
778 configure_clock(codec);
779 break;
780
781 case SND_SOC_DAPM_POST_PMD:
782 /* Disable the FLL if it's running */
783 wm9081_set_fll(codec, 0, 0, 0);
784 break;
785 }
786
787 return 0;
788}
789
790static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
791SND_SOC_DAPM_INPUT("IN1"),
792SND_SOC_DAPM_INPUT("IN2"),
793
794SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0),
795
796SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
797 mixer, ARRAY_SIZE(mixer)),
798
799SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
800
801SND_SOC_DAPM_PGA_E("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0,
802 speaker_event,
803 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
804
805SND_SOC_DAPM_OUTPUT("LINEOUT"),
806SND_SOC_DAPM_OUTPUT("SPKN"),
807SND_SOC_DAPM_OUTPUT("SPKP"),
808
809SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
810 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
811SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
812SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
813};
814
815
816static const struct snd_soc_dapm_route audio_paths[] = {
817 { "DAC", NULL, "CLK_SYS" },
818 { "DAC", NULL, "CLK_DSP" },
819
820 { "Mixer", "IN1 Switch", "IN1" },
821 { "Mixer", "IN2 Switch", "IN2" },
822 { "Mixer", "Playback Switch", "DAC" },
823
824 { "LINEOUT PGA", NULL, "Mixer" },
825 { "LINEOUT PGA", NULL, "TOCLK" },
826 { "LINEOUT PGA", NULL, "CLK_SYS" },
827
828 { "LINEOUT", NULL, "LINEOUT PGA" },
829
830 { "Speaker PGA", NULL, "Mixer" },
831 { "Speaker PGA", NULL, "TOCLK" },
832 { "Speaker PGA", NULL, "CLK_SYS" },
833
834 { "SPKN", NULL, "Speaker PGA" },
835 { "SPKP", NULL, "Speaker PGA" },
836};
837
838static int wm9081_set_bias_level(struct snd_soc_codec *codec,
839 enum snd_soc_bias_level level)
840{
841 u16 reg;
842
843 switch (level) {
844 case SND_SOC_BIAS_ON:
845 break;
846
847 case SND_SOC_BIAS_PREPARE:
848 /* VMID=2*40k */
849 reg = wm9081_read(codec, WM9081_VMID_CONTROL);
850 reg &= ~WM9081_VMID_SEL_MASK;
851 reg |= 0x2;
852 wm9081_write(codec, WM9081_VMID_CONTROL, reg);
853
854 /* Normal bias current */
855 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1);
856 reg &= ~WM9081_STBY_BIAS_ENA;
857 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg);
858 break;
859
860 case SND_SOC_BIAS_STANDBY:
861 /* Initial cold start */
862 if (codec->bias_level == SND_SOC_BIAS_OFF) {
863 /* Disable LINEOUT discharge */
864 reg = wm9081_read(codec, WM9081_ANTI_POP_CONTROL);
865 reg &= ~WM9081_LINEOUT_DISCH;
866 wm9081_write(codec, WM9081_ANTI_POP_CONTROL, reg);
867
868 /* Select startup bias source */
869 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1);
870 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
871 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg);
872
873 /* VMID 2*4k; Soft VMID ramp enable */
874 reg = wm9081_read(codec, WM9081_VMID_CONTROL);
875 reg |= WM9081_VMID_RAMP | 0x6;
876 wm9081_write(codec, WM9081_VMID_CONTROL, reg);
877
878 mdelay(100);
879
880 /* Normal bias enable & soft start off */
881 reg |= WM9081_BIAS_ENA;
882 reg &= ~WM9081_VMID_RAMP;
883 wm9081_write(codec, WM9081_VMID_CONTROL, reg);
884
885 /* Standard bias source */
886 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1);
887 reg &= ~WM9081_BIAS_SRC;
888 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg);
889 }
890
891 /* VMID 2*240k */
892 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1);
893 reg &= ~WM9081_VMID_SEL_MASK;
894 reg |= 0x40;
895 wm9081_write(codec, WM9081_VMID_CONTROL, reg);
896
897 /* Standby bias current on */
898 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1);
899 reg |= WM9081_STBY_BIAS_ENA;
900 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg);
901 break;
902
903 case SND_SOC_BIAS_OFF:
904 /* Startup bias source */
905 reg = wm9081_read(codec, WM9081_BIAS_CONTROL_1);
906 reg |= WM9081_BIAS_SRC;
907 wm9081_write(codec, WM9081_BIAS_CONTROL_1, reg);
908
909 /* Disable VMID and biases with soft ramping */
910 reg = wm9081_read(codec, WM9081_VMID_CONTROL);
911 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA);
912 reg |= WM9081_VMID_RAMP;
913 wm9081_write(codec, WM9081_VMID_CONTROL, reg);
914
915 /* Actively discharge LINEOUT */
916 reg = wm9081_read(codec, WM9081_ANTI_POP_CONTROL);
917 reg |= WM9081_LINEOUT_DISCH;
918 wm9081_write(codec, WM9081_ANTI_POP_CONTROL, reg);
919 break;
920 }
921
922 codec->bias_level = level;
923
924 return 0;
925}
926
927static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
928 unsigned int fmt)
929{
930 struct snd_soc_codec *codec = dai->codec;
931 struct wm9081_priv *wm9081 = codec->private_data;
932 unsigned int aif2 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_2);
933
934 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
935 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
936
937 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
938 case SND_SOC_DAIFMT_CBS_CFS:
939 wm9081->master = 0;
940 break;
941 case SND_SOC_DAIFMT_CBS_CFM:
942 aif2 |= WM9081_LRCLK_DIR;
943 wm9081->master = 1;
944 break;
945 case SND_SOC_DAIFMT_CBM_CFS:
946 aif2 |= WM9081_BCLK_DIR;
947 wm9081->master = 1;
948 break;
949 case SND_SOC_DAIFMT_CBM_CFM:
950 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
951 wm9081->master = 1;
952 break;
953 default:
954 return -EINVAL;
955 }
956
957 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
958 case SND_SOC_DAIFMT_DSP_B:
959 aif2 |= WM9081_AIF_LRCLK_INV;
960 case SND_SOC_DAIFMT_DSP_A:
961 aif2 |= 0x3;
962 break;
963 case SND_SOC_DAIFMT_I2S:
964 aif2 |= 0x2;
965 break;
966 case SND_SOC_DAIFMT_RIGHT_J:
967 break;
968 case SND_SOC_DAIFMT_LEFT_J:
969 aif2 |= 0x1;
970 break;
971 default:
972 return -EINVAL;
973 }
974
975 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
976 case SND_SOC_DAIFMT_DSP_A:
977 case SND_SOC_DAIFMT_DSP_B:
978 /* frame inversion not valid for DSP modes */
979 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
980 case SND_SOC_DAIFMT_NB_NF:
981 break;
982 case SND_SOC_DAIFMT_IB_NF:
983 aif2 |= WM9081_AIF_BCLK_INV;
984 break;
985 default:
986 return -EINVAL;
987 }
988 break;
989
990 case SND_SOC_DAIFMT_I2S:
991 case SND_SOC_DAIFMT_RIGHT_J:
992 case SND_SOC_DAIFMT_LEFT_J:
993 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
994 case SND_SOC_DAIFMT_NB_NF:
995 break;
996 case SND_SOC_DAIFMT_IB_IF:
997 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
998 break;
999 case SND_SOC_DAIFMT_IB_NF:
1000 aif2 |= WM9081_AIF_BCLK_INV;
1001 break;
1002 case SND_SOC_DAIFMT_NB_IF:
1003 aif2 |= WM9081_AIF_LRCLK_INV;
1004 break;
1005 default:
1006 return -EINVAL;
1007 }
1008 break;
1009 default:
1010 return -EINVAL;
1011 }
1012
1013 wm9081_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1014
1015 return 0;
1016}
1017
1018static int wm9081_hw_params(struct snd_pcm_substream *substream,
1019 struct snd_pcm_hw_params *params,
1020 struct snd_soc_dai *dai)
1021{
1022 struct snd_soc_codec *codec = dai->codec;
1023 struct wm9081_priv *wm9081 = codec->private_data;
1024 int ret, i, best, best_val, cur_val;
1025 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
1026
1027 clk_ctrl2 = wm9081_read(codec, WM9081_CLOCK_CONTROL_2);
1028 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
1029
1030 aif1 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_1);
1031
1032 aif2 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_2);
1033 aif2 &= ~WM9081_AIF_WL_MASK;
1034
1035 aif3 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_3);
1036 aif3 &= ~WM9081_BCLK_DIV_MASK;
1037
1038 aif4 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_4);
1039 aif4 &= ~WM9081_LRCLK_RATE_MASK;
1040
1041 /* What BCLK do we need? */
1042 wm9081->fs = params_rate(params);
1043 wm9081->bclk = 2 * wm9081->fs;
1044 switch (params_format(params)) {
1045 case SNDRV_PCM_FORMAT_S16_LE:
1046 wm9081->bclk *= 16;
1047 break;
1048 case SNDRV_PCM_FORMAT_S20_3LE:
1049 wm9081->bclk *= 20;
1050 aif2 |= 0x4;
1051 break;
1052 case SNDRV_PCM_FORMAT_S24_LE:
1053 wm9081->bclk *= 24;
1054 aif2 |= 0x8;
1055 break;
1056 case SNDRV_PCM_FORMAT_S32_LE:
1057 wm9081->bclk *= 32;
1058 aif2 |= 0xc;
1059 break;
1060 default:
1061 return -EINVAL;
1062 }
1063
1064 if (aif1 & WM9081_AIFDAC_TDM_MODE_MASK) {
1065 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
1066 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
1067 wm9081->bclk *= slots;
1068 }
1069
1070 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1071
1072 ret = configure_clock(codec);
1073 if (ret != 0)
1074 return ret;
1075
1076 /* Select nearest CLK_SYS_RATE */
1077 best = 0;
1078 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1079 - wm9081->fs);
1080 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1081 cur_val = abs((wm9081->sysclk_rate /
1082 clk_sys_rates[i].ratio) - wm9081->fs);;
1083 if (cur_val < best_val) {
1084 best = i;
1085 best_val = cur_val;
1086 }
1087 }
1088 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1089 clk_sys_rates[best].ratio);
1090 clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1091 << WM9081_CLK_SYS_RATE_SHIFT);
1092
1093 /* SAMPLE_RATE */
1094 best = 0;
1095 best_val = abs(wm9081->fs - sample_rates[0].rate);
1096 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1097 /* Closest match */
1098 cur_val = abs(wm9081->fs - sample_rates[i].rate);
1099 if (cur_val < best_val) {
1100 best = i;
1101 best_val = cur_val;
1102 }
1103 }
1104 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1105 sample_rates[best].rate);
1106 clk_ctrl2 |= (sample_rates[best].sample_rate
1107 << WM9081_SAMPLE_RATE_SHIFT);
1108
1109 /* BCLK_DIV */
1110 best = 0;
1111 best_val = INT_MAX;
1112 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1113 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1114 - wm9081->bclk;
1115 if (cur_val < 0) /* Table is sorted */
1116 break;
1117 if (cur_val < best_val) {
1118 best = i;
1119 best_val = cur_val;
1120 }
1121 }
1122 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1123 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1124 bclk_divs[best].div, wm9081->bclk);
1125 aif3 |= bclk_divs[best].bclk_div;
1126
1127 /* LRCLK is a simple fraction of BCLK */
1128 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1129 aif4 |= wm9081->bclk / wm9081->fs;
1130
1131 /* Apply a ReTune Mobile configuration if it's in use */
1132 if (wm9081->retune) {
1133 struct wm9081_retune_mobile_config *retune = wm9081->retune;
1134 struct wm9081_retune_mobile_setting *s;
1135 int eq1;
1136
1137 best = 0;
1138 best_val = abs(retune->configs[0].rate - wm9081->fs);
1139 for (i = 0; i < retune->num_configs; i++) {
1140 cur_val = abs(retune->configs[i].rate - wm9081->fs);
1141 if (cur_val < best_val) {
1142 best_val = cur_val;
1143 best = i;
1144 }
1145 }
1146 s = &retune->configs[best];
1147
1148 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1149 s->name, s->rate);
1150
1151 /* If the EQ is enabled then disable it while we write out */
1152 eq1 = wm9081_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
1153 if (eq1 & WM9081_EQ_ENA)
1154 wm9081_write(codec, WM9081_EQ_1, 0);
1155
1156 /* Write out the other values */
1157 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1158 wm9081_write(codec, WM9081_EQ_1 + i, s->config[i]);
1159
1160 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
1161 wm9081_write(codec, WM9081_EQ_1, eq1);
1162 }
1163
1164 wm9081_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1165 wm9081_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1166 wm9081_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1167 wm9081_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
1168
1169 return 0;
1170}
1171
1172static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1173{
1174 struct snd_soc_codec *codec = codec_dai->codec;
1175 unsigned int reg;
1176
1177 reg = wm9081_read(codec, WM9081_DAC_DIGITAL_2);
1178
1179 if (mute)
1180 reg |= WM9081_DAC_MUTE;
1181 else
1182 reg &= ~WM9081_DAC_MUTE;
1183
1184 wm9081_write(codec, WM9081_DAC_DIGITAL_2, reg);
1185
1186 return 0;
1187}
1188
1189static int wm9081_set_sysclk(struct snd_soc_dai *codec_dai,
1190 int clk_id, unsigned int freq, int dir)
1191{
1192 struct snd_soc_codec *codec = codec_dai->codec;
1193 struct wm9081_priv *wm9081 = codec->private_data;
1194
1195 switch (clk_id) {
1196 case WM9081_SYSCLK_MCLK:
1197 case WM9081_SYSCLK_FLL_MCLK:
1198 wm9081->sysclk_source = clk_id;
1199 wm9081->mclk_rate = freq;
1200 break;
1201
1202 default:
1203 return -EINVAL;
1204 }
1205
1206 return 0;
1207}
1208
1209static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1210 unsigned int mask, int slots)
1211{
1212 struct snd_soc_codec *codec = dai->codec;
1213 unsigned int aif1 = wm9081_read(codec, WM9081_AUDIO_INTERFACE_1);
1214
1215 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1216
1217 if (slots < 1 || slots > 4)
1218 return -EINVAL;
1219
1220 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1221
1222 switch (mask) {
1223 case 1:
1224 break;
1225 case 2:
1226 aif1 |= 0x10;
1227 break;
1228 case 4:
1229 aif1 |= 0x20;
1230 break;
1231 case 8:
1232 aif1 |= 0x30;
1233 break;
1234 default:
1235 return -EINVAL;
1236 }
1237
1238 wm9081_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
1239
1240 return 0;
1241}
1242
1243#define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1244
1245#define WM9081_FORMATS \
1246 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1247 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1248
1249static struct snd_soc_dai_ops wm9081_dai_ops = {
1250 .hw_params = wm9081_hw_params,
1251 .set_sysclk = wm9081_set_sysclk,
1252 .set_fmt = wm9081_set_dai_fmt,
1253 .digital_mute = wm9081_digital_mute,
1254 .set_tdm_slot = wm9081_set_tdm_slot,
1255};
1256
1257/* We report two channels because the CODEC processes a stereo signal, even
1258 * though it is only capable of handling a mono output.
1259 */
1260struct snd_soc_dai wm9081_dai = {
1261 .name = "WM9081",
1262 .playback = {
1263 .stream_name = "HiFi Playback",
1264 .channels_min = 1,
1265 .channels_max = 2,
1266 .rates = WM9081_RATES,
1267 .formats = WM9081_FORMATS,
1268 },
1269 .ops = &wm9081_dai_ops,
1270};
1271EXPORT_SYMBOL_GPL(wm9081_dai);
1272
1273
1274static struct snd_soc_codec *wm9081_codec;
1275
1276static int wm9081_probe(struct platform_device *pdev)
1277{
1278 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1279 struct snd_soc_codec *codec;
1280 struct wm9081_priv *wm9081;
1281 int ret = 0;
1282
1283 if (wm9081_codec == NULL) {
1284 dev_err(&pdev->dev, "Codec device not registered\n");
1285 return -ENODEV;
1286 }
1287
1288 socdev->card->codec = wm9081_codec;
1289 codec = wm9081_codec;
1290 wm9081 = codec->private_data;
1291
1292 /* register pcms */
1293 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1294 if (ret < 0) {
1295 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
1296 goto pcm_err;
1297 }
1298
1299 snd_soc_add_controls(codec, wm9081_snd_controls,
1300 ARRAY_SIZE(wm9081_snd_controls));
1301 if (!wm9081->retune) {
1302 dev_dbg(codec->dev,
1303 "No ReTune Mobile data, using normal EQ\n");
1304 snd_soc_add_controls(codec, wm9081_eq_controls,
1305 ARRAY_SIZE(wm9081_eq_controls));
1306 }
1307
1308 snd_soc_dapm_new_controls(codec, wm9081_dapm_widgets,
1309 ARRAY_SIZE(wm9081_dapm_widgets));
1310 snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
1311 snd_soc_dapm_new_widgets(codec);
1312
1313 ret = snd_soc_init_card(socdev);
1314 if (ret < 0) {
1315 dev_err(codec->dev, "failed to register card: %d\n", ret);
1316 goto card_err;
1317 }
1318
1319 return ret;
1320
1321card_err:
1322 snd_soc_free_pcms(socdev);
1323 snd_soc_dapm_free(socdev);
1324pcm_err:
1325 return ret;
1326}
1327
1328static int wm9081_remove(struct platform_device *pdev)
1329{
1330 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1331
1332 snd_soc_free_pcms(socdev);
1333 snd_soc_dapm_free(socdev);
1334
1335 return 0;
1336}
1337
1338#ifdef CONFIG_PM
1339static int wm9081_suspend(struct platform_device *pdev, pm_message_t state)
1340{
1341 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1342 struct snd_soc_codec *codec = socdev->card->codec;
1343
1344 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1345
1346 return 0;
1347}
1348
1349static int wm9081_resume(struct platform_device *pdev)
1350{
1351 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1352 struct snd_soc_codec *codec = socdev->card->codec;
1353 u16 *reg_cache = codec->reg_cache;
1354 int i;
1355
1356 for (i = 0; i < codec->reg_cache_size; i++) {
1357 if (i == WM9081_SOFTWARE_RESET)
1358 continue;
1359
1360 wm9081_write(codec, i, reg_cache[i]);
1361 }
1362
1363 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1364
1365 return 0;
1366}
1367#else
1368#define wm9081_suspend NULL
1369#define wm9081_resume NULL
1370#endif
1371
1372struct snd_soc_codec_device soc_codec_dev_wm9081 = {
1373 .probe = wm9081_probe,
1374 .remove = wm9081_remove,
1375 .suspend = wm9081_suspend,
1376 .resume = wm9081_resume,
1377};
1378EXPORT_SYMBOL_GPL(soc_codec_dev_wm9081);
1379
1380static int wm9081_register(struct wm9081_priv *wm9081)
1381{
1382 struct snd_soc_codec *codec = &wm9081->codec;
1383 int ret;
1384 u16 reg;
1385
1386 if (wm9081_codec) {
1387 dev_err(codec->dev, "Another WM9081 is registered\n");
1388 ret = -EINVAL;
1389 goto err;
1390 }
1391
1392 mutex_init(&codec->mutex);
1393 INIT_LIST_HEAD(&codec->dapm_widgets);
1394 INIT_LIST_HEAD(&codec->dapm_paths);
1395
1396 codec->private_data = wm9081;
1397 codec->name = "WM9081";
1398 codec->owner = THIS_MODULE;
1399 codec->read = wm9081_read;
1400 codec->write = wm9081_write;
1401 codec->dai = &wm9081_dai;
1402 codec->num_dai = 1;
1403 codec->reg_cache_size = ARRAY_SIZE(wm9081->reg_cache);
1404 codec->reg_cache = &wm9081->reg_cache;
1405 codec->bias_level = SND_SOC_BIAS_OFF;
1406 codec->set_bias_level = wm9081_set_bias_level;
1407
1408 memcpy(codec->reg_cache, wm9081_reg_defaults,
1409 sizeof(wm9081_reg_defaults));
1410
1411 reg = wm9081_read_hw(codec, WM9081_SOFTWARE_RESET);
1412 if (reg != 0x9081) {
1413 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1414 ret = -EINVAL;
1415 goto err;
1416 }
1417
1418 ret = wm9081_reset(codec);
1419 if (ret < 0) {
1420 dev_err(codec->dev, "Failed to issue reset\n");
1421 return ret;
1422 }
1423
1424 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1425
1426 /* Enable zero cross by default */
1427 reg = wm9081_read(codec, WM9081_ANALOGUE_LINEOUT);
1428 wm9081_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
1429 reg = wm9081_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
1430 wm9081_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1431 reg | WM9081_SPKPGAZC);
1432
1433 wm9081_dai.dev = codec->dev;
1434
1435 wm9081_codec = codec;
1436
1437 ret = snd_soc_register_codec(codec);
1438 if (ret != 0) {
1439 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1440 return ret;
1441 }
1442
1443 ret = snd_soc_register_dai(&wm9081_dai);
1444 if (ret != 0) {
1445 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1446 snd_soc_unregister_codec(codec);
1447 return ret;
1448 }
1449
1450 return 0;
1451
1452err:
1453 kfree(wm9081);
1454 return ret;
1455}
1456
1457static void wm9081_unregister(struct wm9081_priv *wm9081)
1458{
1459 wm9081_set_bias_level(&wm9081->codec, SND_SOC_BIAS_OFF);
1460 snd_soc_unregister_dai(&wm9081_dai);
1461 snd_soc_unregister_codec(&wm9081->codec);
1462 kfree(wm9081);
1463 wm9081_codec = NULL;
1464}
1465
1466static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1467 const struct i2c_device_id *id)
1468{
1469 struct wm9081_priv *wm9081;
1470 struct snd_soc_codec *codec;
1471
1472 wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL);
1473 if (wm9081 == NULL)
1474 return -ENOMEM;
1475
1476 codec = &wm9081->codec;
1477 codec->hw_write = (hw_write_t)i2c_master_send;
1478 wm9081->retune = i2c->dev.platform_data;
1479
1480 i2c_set_clientdata(i2c, wm9081);
1481 codec->control_data = i2c;
1482
1483 codec->dev = &i2c->dev;
1484
1485 return wm9081_register(wm9081);
1486}
1487
1488static __devexit int wm9081_i2c_remove(struct i2c_client *client)
1489{
1490 struct wm9081_priv *wm9081 = i2c_get_clientdata(client);
1491 wm9081_unregister(wm9081);
1492 return 0;
1493}
1494
1495static const struct i2c_device_id wm9081_i2c_id[] = {
1496 { "wm9081", 0 },
1497 { }
1498};
1499MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1500
1501static struct i2c_driver wm9081_i2c_driver = {
1502 .driver = {
1503 .name = "wm9081",
1504 .owner = THIS_MODULE,
1505 },
1506 .probe = wm9081_i2c_probe,
1507 .remove = __devexit_p(wm9081_i2c_remove),
1508 .id_table = wm9081_i2c_id,
1509};
1510
1511static int __init wm9081_modinit(void)
1512{
1513 int ret;
1514
1515 ret = i2c_add_driver(&wm9081_i2c_driver);
1516 if (ret != 0) {
1517 printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n",
1518 ret);
1519 }
1520
1521 return ret;
1522}
1523module_init(wm9081_modinit);
1524
1525static void __exit wm9081_exit(void)
1526{
1527 i2c_del_driver(&wm9081_i2c_driver);
1528}
1529module_exit(wm9081_exit);
1530
1531
1532MODULE_DESCRIPTION("ASoC WM9081 driver");
1533MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1534MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm9081.h b/sound/soc/codecs/wm9081.h
new file mode 100644
index 000000000000..42d3bc757021
--- /dev/null
+++ b/sound/soc/codecs/wm9081.h
@@ -0,0 +1,787 @@
1#ifndef WM9081_H
2#define WM9081_H
3
4/*
5 * wm9081.c -- WM9081 ALSA SoC Audio driver
6 *
7 * Author: Mark Brown
8 *
9 * Copyright 2009 Wolfson Microelectronics plc
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <sound/soc.h>
17
18extern struct snd_soc_dai wm9081_dai;
19extern struct snd_soc_codec_device soc_codec_dev_wm9081;
20
21/*
22 * SYSCLK sources
23 */
24#define WM9081_SYSCLK_MCLK 1 /* Use MCLK without FLL */
25#define WM9081_SYSCLK_FLL_MCLK 2 /* Use MCLK, enabling FLL if required */
26
27/*
28 * Register values.
29 */
30#define WM9081_SOFTWARE_RESET 0x00
31#define WM9081_ANALOGUE_LINEOUT 0x02
32#define WM9081_ANALOGUE_SPEAKER_PGA 0x03
33#define WM9081_VMID_CONTROL 0x04
34#define WM9081_BIAS_CONTROL_1 0x05
35#define WM9081_ANALOGUE_MIXER 0x07
36#define WM9081_ANTI_POP_CONTROL 0x08
37#define WM9081_ANALOGUE_SPEAKER_1 0x09
38#define WM9081_ANALOGUE_SPEAKER_2 0x0A
39#define WM9081_POWER_MANAGEMENT 0x0B
40#define WM9081_CLOCK_CONTROL_1 0x0C
41#define WM9081_CLOCK_CONTROL_2 0x0D
42#define WM9081_CLOCK_CONTROL_3 0x0E
43#define WM9081_FLL_CONTROL_1 0x10
44#define WM9081_FLL_CONTROL_2 0x11
45#define WM9081_FLL_CONTROL_3 0x12
46#define WM9081_FLL_CONTROL_4 0x13
47#define WM9081_FLL_CONTROL_5 0x14
48#define WM9081_AUDIO_INTERFACE_1 0x16
49#define WM9081_AUDIO_INTERFACE_2 0x17
50#define WM9081_AUDIO_INTERFACE_3 0x18
51#define WM9081_AUDIO_INTERFACE_4 0x19
52#define WM9081_INTERRUPT_STATUS 0x1A
53#define WM9081_INTERRUPT_STATUS_MASK 0x1B
54#define WM9081_INTERRUPT_POLARITY 0x1C
55#define WM9081_INTERRUPT_CONTROL 0x1D
56#define WM9081_DAC_DIGITAL_1 0x1E
57#define WM9081_DAC_DIGITAL_2 0x1F
58#define WM9081_DRC_1 0x20
59#define WM9081_DRC_2 0x21
60#define WM9081_DRC_3 0x22
61#define WM9081_DRC_4 0x23
62#define WM9081_WRITE_SEQUENCER_1 0x26
63#define WM9081_WRITE_SEQUENCER_2 0x27
64#define WM9081_MW_SLAVE_1 0x28
65#define WM9081_EQ_1 0x2A
66#define WM9081_EQ_2 0x2B
67#define WM9081_EQ_3 0x2C
68#define WM9081_EQ_4 0x2D
69#define WM9081_EQ_5 0x2E
70#define WM9081_EQ_6 0x2F
71#define WM9081_EQ_7 0x30
72#define WM9081_EQ_8 0x31
73#define WM9081_EQ_9 0x32
74#define WM9081_EQ_10 0x33
75#define WM9081_EQ_11 0x34
76#define WM9081_EQ_12 0x35
77#define WM9081_EQ_13 0x36
78#define WM9081_EQ_14 0x37
79#define WM9081_EQ_15 0x38
80#define WM9081_EQ_16 0x39
81#define WM9081_EQ_17 0x3A
82#define WM9081_EQ_18 0x3B
83#define WM9081_EQ_19 0x3C
84#define WM9081_EQ_20 0x3D
85
86#define WM9081_REGISTER_COUNT 55
87#define WM9081_MAX_REGISTER 0x3D
88
89/*
90 * Field Definitions.
91 */
92
93/*
94 * R0 (0x00) - Software Reset
95 */
96#define WM9081_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
97#define WM9081_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
98#define WM9081_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
99
100/*
101 * R2 (0x02) - Analogue Lineout
102 */
103#define WM9081_LINEOUT_MUTE 0x0080 /* LINEOUT_MUTE */
104#define WM9081_LINEOUT_MUTE_MASK 0x0080 /* LINEOUT_MUTE */
105#define WM9081_LINEOUT_MUTE_SHIFT 7 /* LINEOUT_MUTE */
106#define WM9081_LINEOUT_MUTE_WIDTH 1 /* LINEOUT_MUTE */
107#define WM9081_LINEOUTZC 0x0040 /* LINEOUTZC */
108#define WM9081_LINEOUTZC_MASK 0x0040 /* LINEOUTZC */
109#define WM9081_LINEOUTZC_SHIFT 6 /* LINEOUTZC */
110#define WM9081_LINEOUTZC_WIDTH 1 /* LINEOUTZC */
111#define WM9081_LINEOUT_VOL_MASK 0x003F /* LINEOUT_VOL - [5:0] */
112#define WM9081_LINEOUT_VOL_SHIFT 0 /* LINEOUT_VOL - [5:0] */
113#define WM9081_LINEOUT_VOL_WIDTH 6 /* LINEOUT_VOL - [5:0] */
114
115/*
116 * R3 (0x03) - Analogue Speaker PGA
117 */
118#define WM9081_SPKPGA_MUTE 0x0080 /* SPKPGA_MUTE */
119#define WM9081_SPKPGA_MUTE_MASK 0x0080 /* SPKPGA_MUTE */
120#define WM9081_SPKPGA_MUTE_SHIFT 7 /* SPKPGA_MUTE */
121#define WM9081_SPKPGA_MUTE_WIDTH 1 /* SPKPGA_MUTE */
122#define WM9081_SPKPGAZC 0x0040 /* SPKPGAZC */
123#define WM9081_SPKPGAZC_MASK 0x0040 /* SPKPGAZC */
124#define WM9081_SPKPGAZC_SHIFT 6 /* SPKPGAZC */
125#define WM9081_SPKPGAZC_WIDTH 1 /* SPKPGAZC */
126#define WM9081_SPKPGA_VOL_MASK 0x003F /* SPKPGA_VOL - [5:0] */
127#define WM9081_SPKPGA_VOL_SHIFT 0 /* SPKPGA_VOL - [5:0] */
128#define WM9081_SPKPGA_VOL_WIDTH 6 /* SPKPGA_VOL - [5:0] */
129
130/*
131 * R4 (0x04) - VMID Control
132 */
133#define WM9081_VMID_BUF_ENA 0x0020 /* VMID_BUF_ENA */
134#define WM9081_VMID_BUF_ENA_MASK 0x0020 /* VMID_BUF_ENA */
135#define WM9081_VMID_BUF_ENA_SHIFT 5 /* VMID_BUF_ENA */
136#define WM9081_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */
137#define WM9081_VMID_RAMP 0x0008 /* VMID_RAMP */
138#define WM9081_VMID_RAMP_MASK 0x0008 /* VMID_RAMP */
139#define WM9081_VMID_RAMP_SHIFT 3 /* VMID_RAMP */
140#define WM9081_VMID_RAMP_WIDTH 1 /* VMID_RAMP */
141#define WM9081_VMID_SEL_MASK 0x0006 /* VMID_SEL - [2:1] */
142#define WM9081_VMID_SEL_SHIFT 1 /* VMID_SEL - [2:1] */
143#define WM9081_VMID_SEL_WIDTH 2 /* VMID_SEL - [2:1] */
144#define WM9081_VMID_FAST_ST 0x0001 /* VMID_FAST_ST */
145#define WM9081_VMID_FAST_ST_MASK 0x0001 /* VMID_FAST_ST */
146#define WM9081_VMID_FAST_ST_SHIFT 0 /* VMID_FAST_ST */
147#define WM9081_VMID_FAST_ST_WIDTH 1 /* VMID_FAST_ST */
148
149/*
150 * R5 (0x05) - Bias Control 1
151 */
152#define WM9081_BIAS_SRC 0x0040 /* BIAS_SRC */
153#define WM9081_BIAS_SRC_MASK 0x0040 /* BIAS_SRC */
154#define WM9081_BIAS_SRC_SHIFT 6 /* BIAS_SRC */
155#define WM9081_BIAS_SRC_WIDTH 1 /* BIAS_SRC */
156#define WM9081_STBY_BIAS_LVL 0x0020 /* STBY_BIAS_LVL */
157#define WM9081_STBY_BIAS_LVL_MASK 0x0020 /* STBY_BIAS_LVL */
158#define WM9081_STBY_BIAS_LVL_SHIFT 5 /* STBY_BIAS_LVL */
159#define WM9081_STBY_BIAS_LVL_WIDTH 1 /* STBY_BIAS_LVL */
160#define WM9081_STBY_BIAS_ENA 0x0010 /* STBY_BIAS_ENA */
161#define WM9081_STBY_BIAS_ENA_MASK 0x0010 /* STBY_BIAS_ENA */
162#define WM9081_STBY_BIAS_ENA_SHIFT 4 /* STBY_BIAS_ENA */
163#define WM9081_STBY_BIAS_ENA_WIDTH 1 /* STBY_BIAS_ENA */
164#define WM9081_BIAS_LVL_MASK 0x000C /* BIAS_LVL - [3:2] */
165#define WM9081_BIAS_LVL_SHIFT 2 /* BIAS_LVL - [3:2] */
166#define WM9081_BIAS_LVL_WIDTH 2 /* BIAS_LVL - [3:2] */
167#define WM9081_BIAS_ENA 0x0002 /* BIAS_ENA */
168#define WM9081_BIAS_ENA_MASK 0x0002 /* BIAS_ENA */
169#define WM9081_BIAS_ENA_SHIFT 1 /* BIAS_ENA */
170#define WM9081_BIAS_ENA_WIDTH 1 /* BIAS_ENA */
171#define WM9081_STARTUP_BIAS_ENA 0x0001 /* STARTUP_BIAS_ENA */
172#define WM9081_STARTUP_BIAS_ENA_MASK 0x0001 /* STARTUP_BIAS_ENA */
173#define WM9081_STARTUP_BIAS_ENA_SHIFT 0 /* STARTUP_BIAS_ENA */
174#define WM9081_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */
175
176/*
177 * R7 (0x07) - Analogue Mixer
178 */
179#define WM9081_DAC_SEL 0x0010 /* DAC_SEL */
180#define WM9081_DAC_SEL_MASK 0x0010 /* DAC_SEL */
181#define WM9081_DAC_SEL_SHIFT 4 /* DAC_SEL */
182#define WM9081_DAC_SEL_WIDTH 1 /* DAC_SEL */
183#define WM9081_IN2_VOL 0x0008 /* IN2_VOL */
184#define WM9081_IN2_VOL_MASK 0x0008 /* IN2_VOL */
185#define WM9081_IN2_VOL_SHIFT 3 /* IN2_VOL */
186#define WM9081_IN2_VOL_WIDTH 1 /* IN2_VOL */
187#define WM9081_IN2_ENA 0x0004 /* IN2_ENA */
188#define WM9081_IN2_ENA_MASK 0x0004 /* IN2_ENA */
189#define WM9081_IN2_ENA_SHIFT 2 /* IN2_ENA */
190#define WM9081_IN2_ENA_WIDTH 1 /* IN2_ENA */
191#define WM9081_IN1_VOL 0x0002 /* IN1_VOL */
192#define WM9081_IN1_VOL_MASK 0x0002 /* IN1_VOL */
193#define WM9081_IN1_VOL_SHIFT 1 /* IN1_VOL */
194#define WM9081_IN1_VOL_WIDTH 1 /* IN1_VOL */
195#define WM9081_IN1_ENA 0x0001 /* IN1_ENA */
196#define WM9081_IN1_ENA_MASK 0x0001 /* IN1_ENA */
197#define WM9081_IN1_ENA_SHIFT 0 /* IN1_ENA */
198#define WM9081_IN1_ENA_WIDTH 1 /* IN1_ENA */
199
200/*
201 * R8 (0x08) - Anti Pop Control
202 */
203#define WM9081_LINEOUT_DISCH 0x0004 /* LINEOUT_DISCH */
204#define WM9081_LINEOUT_DISCH_MASK 0x0004 /* LINEOUT_DISCH */
205#define WM9081_LINEOUT_DISCH_SHIFT 2 /* LINEOUT_DISCH */
206#define WM9081_LINEOUT_DISCH_WIDTH 1 /* LINEOUT_DISCH */
207#define WM9081_LINEOUT_VROI 0x0002 /* LINEOUT_VROI */
208#define WM9081_LINEOUT_VROI_MASK 0x0002 /* LINEOUT_VROI */
209#define WM9081_LINEOUT_VROI_SHIFT 1 /* LINEOUT_VROI */
210#define WM9081_LINEOUT_VROI_WIDTH 1 /* LINEOUT_VROI */
211#define WM9081_LINEOUT_CLAMP 0x0001 /* LINEOUT_CLAMP */
212#define WM9081_LINEOUT_CLAMP_MASK 0x0001 /* LINEOUT_CLAMP */
213#define WM9081_LINEOUT_CLAMP_SHIFT 0 /* LINEOUT_CLAMP */
214#define WM9081_LINEOUT_CLAMP_WIDTH 1 /* LINEOUT_CLAMP */
215
216/*
217 * R9 (0x09) - Analogue Speaker 1
218 */
219#define WM9081_SPK_DCGAIN_MASK 0x0038 /* SPK_DCGAIN - [5:3] */
220#define WM9081_SPK_DCGAIN_SHIFT 3 /* SPK_DCGAIN - [5:3] */
221#define WM9081_SPK_DCGAIN_WIDTH 3 /* SPK_DCGAIN - [5:3] */
222#define WM9081_SPK_ACGAIN_MASK 0x0007 /* SPK_ACGAIN - [2:0] */
223#define WM9081_SPK_ACGAIN_SHIFT 0 /* SPK_ACGAIN - [2:0] */
224#define WM9081_SPK_ACGAIN_WIDTH 3 /* SPK_ACGAIN - [2:0] */
225
226/*
227 * R10 (0x0A) - Analogue Speaker 2
228 */
229#define WM9081_SPK_MODE 0x0040 /* SPK_MODE */
230#define WM9081_SPK_MODE_MASK 0x0040 /* SPK_MODE */
231#define WM9081_SPK_MODE_SHIFT 6 /* SPK_MODE */
232#define WM9081_SPK_MODE_WIDTH 1 /* SPK_MODE */
233#define WM9081_SPK_INV_MUTE 0x0010 /* SPK_INV_MUTE */
234#define WM9081_SPK_INV_MUTE_MASK 0x0010 /* SPK_INV_MUTE */
235#define WM9081_SPK_INV_MUTE_SHIFT 4 /* SPK_INV_MUTE */
236#define WM9081_SPK_INV_MUTE_WIDTH 1 /* SPK_INV_MUTE */
237#define WM9081_OUT_SPK_CTRL 0x0008 /* OUT_SPK_CTRL */
238#define WM9081_OUT_SPK_CTRL_MASK 0x0008 /* OUT_SPK_CTRL */
239#define WM9081_OUT_SPK_CTRL_SHIFT 3 /* OUT_SPK_CTRL */
240#define WM9081_OUT_SPK_CTRL_WIDTH 1 /* OUT_SPK_CTRL */
241
242/*
243 * R11 (0x0B) - Power Management
244 */
245#define WM9081_TSHUT_ENA 0x0100 /* TSHUT_ENA */
246#define WM9081_TSHUT_ENA_MASK 0x0100 /* TSHUT_ENA */
247#define WM9081_TSHUT_ENA_SHIFT 8 /* TSHUT_ENA */
248#define WM9081_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */
249#define WM9081_TSENSE_ENA 0x0080 /* TSENSE_ENA */
250#define WM9081_TSENSE_ENA_MASK 0x0080 /* TSENSE_ENA */
251#define WM9081_TSENSE_ENA_SHIFT 7 /* TSENSE_ENA */
252#define WM9081_TSENSE_ENA_WIDTH 1 /* TSENSE_ENA */
253#define WM9081_TEMP_SHUT 0x0040 /* TEMP_SHUT */
254#define WM9081_TEMP_SHUT_MASK 0x0040 /* TEMP_SHUT */
255#define WM9081_TEMP_SHUT_SHIFT 6 /* TEMP_SHUT */
256#define WM9081_TEMP_SHUT_WIDTH 1 /* TEMP_SHUT */
257#define WM9081_LINEOUT_ENA 0x0010 /* LINEOUT_ENA */
258#define WM9081_LINEOUT_ENA_MASK 0x0010 /* LINEOUT_ENA */
259#define WM9081_LINEOUT_ENA_SHIFT 4 /* LINEOUT_ENA */
260#define WM9081_LINEOUT_ENA_WIDTH 1 /* LINEOUT_ENA */
261#define WM9081_SPKPGA_ENA 0x0004 /* SPKPGA_ENA */
262#define WM9081_SPKPGA_ENA_MASK 0x0004 /* SPKPGA_ENA */
263#define WM9081_SPKPGA_ENA_SHIFT 2 /* SPKPGA_ENA */
264#define WM9081_SPKPGA_ENA_WIDTH 1 /* SPKPGA_ENA */
265#define WM9081_SPK_ENA 0x0002 /* SPK_ENA */
266#define WM9081_SPK_ENA_MASK 0x0002 /* SPK_ENA */
267#define WM9081_SPK_ENA_SHIFT 1 /* SPK_ENA */
268#define WM9081_SPK_ENA_WIDTH 1 /* SPK_ENA */
269#define WM9081_DAC_ENA 0x0001 /* DAC_ENA */
270#define WM9081_DAC_ENA_MASK 0x0001 /* DAC_ENA */
271#define WM9081_DAC_ENA_SHIFT 0 /* DAC_ENA */
272#define WM9081_DAC_ENA_WIDTH 1 /* DAC_ENA */
273
274/*
275 * R12 (0x0C) - Clock Control 1
276 */
277#define WM9081_CLK_OP_DIV_MASK 0x1C00 /* CLK_OP_DIV - [12:10] */
278#define WM9081_CLK_OP_DIV_SHIFT 10 /* CLK_OP_DIV - [12:10] */
279#define WM9081_CLK_OP_DIV_WIDTH 3 /* CLK_OP_DIV - [12:10] */
280#define WM9081_CLK_TO_DIV_MASK 0x0300 /* CLK_TO_DIV - [9:8] */
281#define WM9081_CLK_TO_DIV_SHIFT 8 /* CLK_TO_DIV - [9:8] */
282#define WM9081_CLK_TO_DIV_WIDTH 2 /* CLK_TO_DIV - [9:8] */
283#define WM9081_MCLKDIV2 0x0080 /* MCLKDIV2 */
284#define WM9081_MCLKDIV2_MASK 0x0080 /* MCLKDIV2 */
285#define WM9081_MCLKDIV2_SHIFT 7 /* MCLKDIV2 */
286#define WM9081_MCLKDIV2_WIDTH 1 /* MCLKDIV2 */
287
288/*
289 * R13 (0x0D) - Clock Control 2
290 */
291#define WM9081_CLK_SYS_RATE_MASK 0x00F0 /* CLK_SYS_RATE - [7:4] */
292#define WM9081_CLK_SYS_RATE_SHIFT 4 /* CLK_SYS_RATE - [7:4] */
293#define WM9081_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [7:4] */
294#define WM9081_SAMPLE_RATE_MASK 0x000F /* SAMPLE_RATE - [3:0] */
295#define WM9081_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [3:0] */
296#define WM9081_SAMPLE_RATE_WIDTH 4 /* SAMPLE_RATE - [3:0] */
297
298/*
299 * R14 (0x0E) - Clock Control 3
300 */
301#define WM9081_CLK_SRC_SEL 0x2000 /* CLK_SRC_SEL */
302#define WM9081_CLK_SRC_SEL_MASK 0x2000 /* CLK_SRC_SEL */
303#define WM9081_CLK_SRC_SEL_SHIFT 13 /* CLK_SRC_SEL */
304#define WM9081_CLK_SRC_SEL_WIDTH 1 /* CLK_SRC_SEL */
305#define WM9081_CLK_OP_ENA 0x0020 /* CLK_OP_ENA */
306#define WM9081_CLK_OP_ENA_MASK 0x0020 /* CLK_OP_ENA */
307#define WM9081_CLK_OP_ENA_SHIFT 5 /* CLK_OP_ENA */
308#define WM9081_CLK_OP_ENA_WIDTH 1 /* CLK_OP_ENA */
309#define WM9081_CLK_TO_ENA 0x0004 /* CLK_TO_ENA */
310#define WM9081_CLK_TO_ENA_MASK 0x0004 /* CLK_TO_ENA */
311#define WM9081_CLK_TO_ENA_SHIFT 2 /* CLK_TO_ENA */
312#define WM9081_CLK_TO_ENA_WIDTH 1 /* CLK_TO_ENA */
313#define WM9081_CLK_DSP_ENA 0x0002 /* CLK_DSP_ENA */
314#define WM9081_CLK_DSP_ENA_MASK 0x0002 /* CLK_DSP_ENA */
315#define WM9081_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */
316#define WM9081_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */
317#define WM9081_CLK_SYS_ENA 0x0001 /* CLK_SYS_ENA */
318#define WM9081_CLK_SYS_ENA_MASK 0x0001 /* CLK_SYS_ENA */
319#define WM9081_CLK_SYS_ENA_SHIFT 0 /* CLK_SYS_ENA */
320#define WM9081_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */
321
322/*
323 * R16 (0x10) - FLL Control 1
324 */
325#define WM9081_FLL_HOLD 0x0008 /* FLL_HOLD */
326#define WM9081_FLL_HOLD_MASK 0x0008 /* FLL_HOLD */
327#define WM9081_FLL_HOLD_SHIFT 3 /* FLL_HOLD */
328#define WM9081_FLL_HOLD_WIDTH 1 /* FLL_HOLD */
329#define WM9081_FLL_FRAC 0x0004 /* FLL_FRAC */
330#define WM9081_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */
331#define WM9081_FLL_FRAC_SHIFT 2 /* FLL_FRAC */
332#define WM9081_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
333#define WM9081_FLL_ENA 0x0001 /* FLL_ENA */
334#define WM9081_FLL_ENA_MASK 0x0001 /* FLL_ENA */
335#define WM9081_FLL_ENA_SHIFT 0 /* FLL_ENA */
336#define WM9081_FLL_ENA_WIDTH 1 /* FLL_ENA */
337
338/*
339 * R17 (0x11) - FLL Control 2
340 */
341#define WM9081_FLL_OUTDIV_MASK 0x0700 /* FLL_OUTDIV - [10:8] */
342#define WM9081_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [10:8] */
343#define WM9081_FLL_OUTDIV_WIDTH 3 /* FLL_OUTDIV - [10:8] */
344#define WM9081_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */
345#define WM9081_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */
346#define WM9081_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */
347#define WM9081_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
348#define WM9081_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
349#define WM9081_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
350
351/*
352 * R18 (0x12) - FLL Control 3
353 */
354#define WM9081_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
355#define WM9081_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
356#define WM9081_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
357
358/*
359 * R19 (0x13) - FLL Control 4
360 */
361#define WM9081_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
362#define WM9081_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
363#define WM9081_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
364#define WM9081_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */
365#define WM9081_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */
366#define WM9081_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */
367
368/*
369 * R20 (0x14) - FLL Control 5
370 */
371#define WM9081_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */
372#define WM9081_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */
373#define WM9081_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */
374#define WM9081_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */
375#define WM9081_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */
376#define WM9081_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */
377
378/*
379 * R22 (0x16) - Audio Interface 1
380 */
381#define WM9081_AIFDAC_CHAN 0x0040 /* AIFDAC_CHAN */
382#define WM9081_AIFDAC_CHAN_MASK 0x0040 /* AIFDAC_CHAN */
383#define WM9081_AIFDAC_CHAN_SHIFT 6 /* AIFDAC_CHAN */
384#define WM9081_AIFDAC_CHAN_WIDTH 1 /* AIFDAC_CHAN */
385#define WM9081_AIFDAC_TDM_SLOT_MASK 0x0030 /* AIFDAC_TDM_SLOT - [5:4] */
386#define WM9081_AIFDAC_TDM_SLOT_SHIFT 4 /* AIFDAC_TDM_SLOT - [5:4] */
387#define WM9081_AIFDAC_TDM_SLOT_WIDTH 2 /* AIFDAC_TDM_SLOT - [5:4] */
388#define WM9081_AIFDAC_TDM_MODE_MASK 0x000C /* AIFDAC_TDM_MODE - [3:2] */
389#define WM9081_AIFDAC_TDM_MODE_SHIFT 2 /* AIFDAC_TDM_MODE - [3:2] */
390#define WM9081_AIFDAC_TDM_MODE_WIDTH 2 /* AIFDAC_TDM_MODE - [3:2] */
391#define WM9081_DAC_COMP 0x0002 /* DAC_COMP */
392#define WM9081_DAC_COMP_MASK 0x0002 /* DAC_COMP */
393#define WM9081_DAC_COMP_SHIFT 1 /* DAC_COMP */
394#define WM9081_DAC_COMP_WIDTH 1 /* DAC_COMP */
395#define WM9081_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */
396#define WM9081_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */
397#define WM9081_DAC_COMPMODE_SHIFT 0 /* DAC_COMPMODE */
398#define WM9081_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */
399
400/*
401 * R23 (0x17) - Audio Interface 2
402 */
403#define WM9081_AIF_TRIS 0x0200 /* AIF_TRIS */
404#define WM9081_AIF_TRIS_MASK 0x0200 /* AIF_TRIS */
405#define WM9081_AIF_TRIS_SHIFT 9 /* AIF_TRIS */
406#define WM9081_AIF_TRIS_WIDTH 1 /* AIF_TRIS */
407#define WM9081_DAC_DAT_INV 0x0100 /* DAC_DAT_INV */
408#define WM9081_DAC_DAT_INV_MASK 0x0100 /* DAC_DAT_INV */
409#define WM9081_DAC_DAT_INV_SHIFT 8 /* DAC_DAT_INV */
410#define WM9081_DAC_DAT_INV_WIDTH 1 /* DAC_DAT_INV */
411#define WM9081_AIF_BCLK_INV 0x0080 /* AIF_BCLK_INV */
412#define WM9081_AIF_BCLK_INV_MASK 0x0080 /* AIF_BCLK_INV */
413#define WM9081_AIF_BCLK_INV_SHIFT 7 /* AIF_BCLK_INV */
414#define WM9081_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */
415#define WM9081_BCLK_DIR 0x0040 /* BCLK_DIR */
416#define WM9081_BCLK_DIR_MASK 0x0040 /* BCLK_DIR */
417#define WM9081_BCLK_DIR_SHIFT 6 /* BCLK_DIR */
418#define WM9081_BCLK_DIR_WIDTH 1 /* BCLK_DIR */
419#define WM9081_LRCLK_DIR 0x0020 /* LRCLK_DIR */
420#define WM9081_LRCLK_DIR_MASK 0x0020 /* LRCLK_DIR */
421#define WM9081_LRCLK_DIR_SHIFT 5 /* LRCLK_DIR */
422#define WM9081_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */
423#define WM9081_AIF_LRCLK_INV 0x0010 /* AIF_LRCLK_INV */
424#define WM9081_AIF_LRCLK_INV_MASK 0x0010 /* AIF_LRCLK_INV */
425#define WM9081_AIF_LRCLK_INV_SHIFT 4 /* AIF_LRCLK_INV */
426#define WM9081_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */
427#define WM9081_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */
428#define WM9081_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */
429#define WM9081_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */
430#define WM9081_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */
431#define WM9081_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */
432#define WM9081_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */
433
434/*
435 * R24 (0x18) - Audio Interface 3
436 */
437#define WM9081_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */
438#define WM9081_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */
439#define WM9081_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */
440
441/*
442 * R25 (0x19) - Audio Interface 4
443 */
444#define WM9081_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */
445#define WM9081_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */
446#define WM9081_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */
447
448/*
449 * R26 (0x1A) - Interrupt Status
450 */
451#define WM9081_WSEQ_BUSY_EINT 0x0004 /* WSEQ_BUSY_EINT */
452#define WM9081_WSEQ_BUSY_EINT_MASK 0x0004 /* WSEQ_BUSY_EINT */
453#define WM9081_WSEQ_BUSY_EINT_SHIFT 2 /* WSEQ_BUSY_EINT */
454#define WM9081_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */
455#define WM9081_TSHUT_EINT 0x0001 /* TSHUT_EINT */
456#define WM9081_TSHUT_EINT_MASK 0x0001 /* TSHUT_EINT */
457#define WM9081_TSHUT_EINT_SHIFT 0 /* TSHUT_EINT */
458#define WM9081_TSHUT_EINT_WIDTH 1 /* TSHUT_EINT */
459
460/*
461 * R27 (0x1B) - Interrupt Status Mask
462 */
463#define WM9081_IM_WSEQ_BUSY_EINT 0x0004 /* IM_WSEQ_BUSY_EINT */
464#define WM9081_IM_WSEQ_BUSY_EINT_MASK 0x0004 /* IM_WSEQ_BUSY_EINT */
465#define WM9081_IM_WSEQ_BUSY_EINT_SHIFT 2 /* IM_WSEQ_BUSY_EINT */
466#define WM9081_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */
467#define WM9081_IM_TSHUT_EINT 0x0001 /* IM_TSHUT_EINT */
468#define WM9081_IM_TSHUT_EINT_MASK 0x0001 /* IM_TSHUT_EINT */
469#define WM9081_IM_TSHUT_EINT_SHIFT 0 /* IM_TSHUT_EINT */
470#define WM9081_IM_TSHUT_EINT_WIDTH 1 /* IM_TSHUT_EINT */
471
472/*
473 * R28 (0x1C) - Interrupt Polarity
474 */
475#define WM9081_TSHUT_INV 0x0001 /* TSHUT_INV */
476#define WM9081_TSHUT_INV_MASK 0x0001 /* TSHUT_INV */
477#define WM9081_TSHUT_INV_SHIFT 0 /* TSHUT_INV */
478#define WM9081_TSHUT_INV_WIDTH 1 /* TSHUT_INV */
479
480/*
481 * R29 (0x1D) - Interrupt Control
482 */
483#define WM9081_IRQ_POL 0x8000 /* IRQ_POL */
484#define WM9081_IRQ_POL_MASK 0x8000 /* IRQ_POL */
485#define WM9081_IRQ_POL_SHIFT 15 /* IRQ_POL */
486#define WM9081_IRQ_POL_WIDTH 1 /* IRQ_POL */
487#define WM9081_IRQ_OP_CTRL 0x0001 /* IRQ_OP_CTRL */
488#define WM9081_IRQ_OP_CTRL_MASK 0x0001 /* IRQ_OP_CTRL */
489#define WM9081_IRQ_OP_CTRL_SHIFT 0 /* IRQ_OP_CTRL */
490#define WM9081_IRQ_OP_CTRL_WIDTH 1 /* IRQ_OP_CTRL */
491
492/*
493 * R30 (0x1E) - DAC Digital 1
494 */
495#define WM9081_DAC_VOL_MASK 0x00FF /* DAC_VOL - [7:0] */
496#define WM9081_DAC_VOL_SHIFT 0 /* DAC_VOL - [7:0] */
497#define WM9081_DAC_VOL_WIDTH 8 /* DAC_VOL - [7:0] */
498
499/*
500 * R31 (0x1F) - DAC Digital 2
501 */
502#define WM9081_DAC_MUTERATE 0x0400 /* DAC_MUTERATE */
503#define WM9081_DAC_MUTERATE_MASK 0x0400 /* DAC_MUTERATE */
504#define WM9081_DAC_MUTERATE_SHIFT 10 /* DAC_MUTERATE */
505#define WM9081_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
506#define WM9081_DAC_MUTEMODE 0x0200 /* DAC_MUTEMODE */
507#define WM9081_DAC_MUTEMODE_MASK 0x0200 /* DAC_MUTEMODE */
508#define WM9081_DAC_MUTEMODE_SHIFT 9 /* DAC_MUTEMODE */
509#define WM9081_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */
510#define WM9081_DAC_MUTE 0x0008 /* DAC_MUTE */
511#define WM9081_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */
512#define WM9081_DAC_MUTE_SHIFT 3 /* DAC_MUTE */
513#define WM9081_DAC_MUTE_WIDTH 1 /* DAC_MUTE */
514#define WM9081_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */
515#define WM9081_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */
516#define WM9081_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */
517
518/*
519 * R32 (0x20) - DRC 1
520 */
521#define WM9081_DRC_ENA 0x8000 /* DRC_ENA */
522#define WM9081_DRC_ENA_MASK 0x8000 /* DRC_ENA */
523#define WM9081_DRC_ENA_SHIFT 15 /* DRC_ENA */
524#define WM9081_DRC_ENA_WIDTH 1 /* DRC_ENA */
525#define WM9081_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */
526#define WM9081_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */
527#define WM9081_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */
528#define WM9081_DRC_FF_DLY 0x0020 /* DRC_FF_DLY */
529#define WM9081_DRC_FF_DLY_MASK 0x0020 /* DRC_FF_DLY */
530#define WM9081_DRC_FF_DLY_SHIFT 5 /* DRC_FF_DLY */
531#define WM9081_DRC_FF_DLY_WIDTH 1 /* DRC_FF_DLY */
532#define WM9081_DRC_QR 0x0004 /* DRC_QR */
533#define WM9081_DRC_QR_MASK 0x0004 /* DRC_QR */
534#define WM9081_DRC_QR_SHIFT 2 /* DRC_QR */
535#define WM9081_DRC_QR_WIDTH 1 /* DRC_QR */
536#define WM9081_DRC_ANTICLIP 0x0002 /* DRC_ANTICLIP */
537#define WM9081_DRC_ANTICLIP_MASK 0x0002 /* DRC_ANTICLIP */
538#define WM9081_DRC_ANTICLIP_SHIFT 1 /* DRC_ANTICLIP */
539#define WM9081_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */
540
541/*
542 * R33 (0x21) - DRC 2
543 */
544#define WM9081_DRC_ATK_MASK 0xF000 /* DRC_ATK - [15:12] */
545#define WM9081_DRC_ATK_SHIFT 12 /* DRC_ATK - [15:12] */
546#define WM9081_DRC_ATK_WIDTH 4 /* DRC_ATK - [15:12] */
547#define WM9081_DRC_DCY_MASK 0x0F00 /* DRC_DCY - [11:8] */
548#define WM9081_DRC_DCY_SHIFT 8 /* DRC_DCY - [11:8] */
549#define WM9081_DRC_DCY_WIDTH 4 /* DRC_DCY - [11:8] */
550#define WM9081_DRC_QR_THR_MASK 0x00C0 /* DRC_QR_THR - [7:6] */
551#define WM9081_DRC_QR_THR_SHIFT 6 /* DRC_QR_THR - [7:6] */
552#define WM9081_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [7:6] */
553#define WM9081_DRC_QR_DCY_MASK 0x0030 /* DRC_QR_DCY - [5:4] */
554#define WM9081_DRC_QR_DCY_SHIFT 4 /* DRC_QR_DCY - [5:4] */
555#define WM9081_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [5:4] */
556#define WM9081_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */
557#define WM9081_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */
558#define WM9081_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */
559#define WM9081_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */
560#define WM9081_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */
561#define WM9081_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */
562
563/*
564 * R34 (0x22) - DRC 3
565 */
566#define WM9081_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */
567#define WM9081_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */
568#define WM9081_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */
569#define WM9081_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */
570#define WM9081_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */
571#define WM9081_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */
572
573/*
574 * R35 (0x23) - DRC 4
575 */
576#define WM9081_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */
577#define WM9081_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */
578#define WM9081_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */
579#define WM9081_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */
580#define WM9081_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */
581#define WM9081_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */
582
583/*
584 * R38 (0x26) - Write Sequencer 1
585 */
586#define WM9081_WSEQ_ENA 0x8000 /* WSEQ_ENA */
587#define WM9081_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */
588#define WM9081_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */
589#define WM9081_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
590#define WM9081_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
591#define WM9081_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
592#define WM9081_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
593#define WM9081_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
594#define WM9081_WSEQ_START 0x0100 /* WSEQ_START */
595#define WM9081_WSEQ_START_MASK 0x0100 /* WSEQ_START */
596#define WM9081_WSEQ_START_SHIFT 8 /* WSEQ_START */
597#define WM9081_WSEQ_START_WIDTH 1 /* WSEQ_START */
598#define WM9081_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
599#define WM9081_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
600#define WM9081_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
601
602/*
603 * R39 (0x27) - Write Sequencer 2
604 */
605#define WM9081_WSEQ_CURRENT_INDEX_MASK 0x07F0 /* WSEQ_CURRENT_INDEX - [10:4] */
606#define WM9081_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [10:4] */
607#define WM9081_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [10:4] */
608#define WM9081_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */
609#define WM9081_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */
610#define WM9081_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */
611#define WM9081_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
612
613/*
614 * R40 (0x28) - MW Slave 1
615 */
616#define WM9081_SPI_CFG 0x0020 /* SPI_CFG */
617#define WM9081_SPI_CFG_MASK 0x0020 /* SPI_CFG */
618#define WM9081_SPI_CFG_SHIFT 5 /* SPI_CFG */
619#define WM9081_SPI_CFG_WIDTH 1 /* SPI_CFG */
620#define WM9081_SPI_4WIRE 0x0010 /* SPI_4WIRE */
621#define WM9081_SPI_4WIRE_MASK 0x0010 /* SPI_4WIRE */
622#define WM9081_SPI_4WIRE_SHIFT 4 /* SPI_4WIRE */
623#define WM9081_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
624#define WM9081_ARA_ENA 0x0008 /* ARA_ENA */
625#define WM9081_ARA_ENA_MASK 0x0008 /* ARA_ENA */
626#define WM9081_ARA_ENA_SHIFT 3 /* ARA_ENA */
627#define WM9081_ARA_ENA_WIDTH 1 /* ARA_ENA */
628#define WM9081_AUTO_INC 0x0002 /* AUTO_INC */
629#define WM9081_AUTO_INC_MASK 0x0002 /* AUTO_INC */
630#define WM9081_AUTO_INC_SHIFT 1 /* AUTO_INC */
631#define WM9081_AUTO_INC_WIDTH 1 /* AUTO_INC */
632
633/*
634 * R42 (0x2A) - EQ 1
635 */
636#define WM9081_EQ_B1_GAIN_MASK 0xF800 /* EQ_B1_GAIN - [15:11] */
637#define WM9081_EQ_B1_GAIN_SHIFT 11 /* EQ_B1_GAIN - [15:11] */
638#define WM9081_EQ_B1_GAIN_WIDTH 5 /* EQ_B1_GAIN - [15:11] */
639#define WM9081_EQ_B2_GAIN_MASK 0x07C0 /* EQ_B2_GAIN - [10:6] */
640#define WM9081_EQ_B2_GAIN_SHIFT 6 /* EQ_B2_GAIN - [10:6] */
641#define WM9081_EQ_B2_GAIN_WIDTH 5 /* EQ_B2_GAIN - [10:6] */
642#define WM9081_EQ_B4_GAIN_MASK 0x003E /* EQ_B4_GAIN - [5:1] */
643#define WM9081_EQ_B4_GAIN_SHIFT 1 /* EQ_B4_GAIN - [5:1] */
644#define WM9081_EQ_B4_GAIN_WIDTH 5 /* EQ_B4_GAIN - [5:1] */
645#define WM9081_EQ_ENA 0x0001 /* EQ_ENA */
646#define WM9081_EQ_ENA_MASK 0x0001 /* EQ_ENA */
647#define WM9081_EQ_ENA_SHIFT 0 /* EQ_ENA */
648#define WM9081_EQ_ENA_WIDTH 1 /* EQ_ENA */
649
650/*
651 * R43 (0x2B) - EQ 2
652 */
653#define WM9081_EQ_B3_GAIN_MASK 0xF800 /* EQ_B3_GAIN - [15:11] */
654#define WM9081_EQ_B3_GAIN_SHIFT 11 /* EQ_B3_GAIN - [15:11] */
655#define WM9081_EQ_B3_GAIN_WIDTH 5 /* EQ_B3_GAIN - [15:11] */
656#define WM9081_EQ_B5_GAIN_MASK 0x07C0 /* EQ_B5_GAIN - [10:6] */
657#define WM9081_EQ_B5_GAIN_SHIFT 6 /* EQ_B5_GAIN - [10:6] */
658#define WM9081_EQ_B5_GAIN_WIDTH 5 /* EQ_B5_GAIN - [10:6] */
659
660/*
661 * R44 (0x2C) - EQ 3
662 */
663#define WM9081_EQ_B1_A_MASK 0xFFFF /* EQ_B1_A - [15:0] */
664#define WM9081_EQ_B1_A_SHIFT 0 /* EQ_B1_A - [15:0] */
665#define WM9081_EQ_B1_A_WIDTH 16 /* EQ_B1_A - [15:0] */
666
667/*
668 * R45 (0x2D) - EQ 4
669 */
670#define WM9081_EQ_B1_B_MASK 0xFFFF /* EQ_B1_B - [15:0] */
671#define WM9081_EQ_B1_B_SHIFT 0 /* EQ_B1_B - [15:0] */
672#define WM9081_EQ_B1_B_WIDTH 16 /* EQ_B1_B - [15:0] */
673
674/*
675 * R46 (0x2E) - EQ 5
676 */
677#define WM9081_EQ_B1_PG_MASK 0xFFFF /* EQ_B1_PG - [15:0] */
678#define WM9081_EQ_B1_PG_SHIFT 0 /* EQ_B1_PG - [15:0] */
679#define WM9081_EQ_B1_PG_WIDTH 16 /* EQ_B1_PG - [15:0] */
680
681/*
682 * R47 (0x2F) - EQ 6
683 */
684#define WM9081_EQ_B2_A_MASK 0xFFFF /* EQ_B2_A - [15:0] */
685#define WM9081_EQ_B2_A_SHIFT 0 /* EQ_B2_A - [15:0] */
686#define WM9081_EQ_B2_A_WIDTH 16 /* EQ_B2_A - [15:0] */
687
688/*
689 * R48 (0x30) - EQ 7
690 */
691#define WM9081_EQ_B2_B_MASK 0xFFFF /* EQ_B2_B - [15:0] */
692#define WM9081_EQ_B2_B_SHIFT 0 /* EQ_B2_B - [15:0] */
693#define WM9081_EQ_B2_B_WIDTH 16 /* EQ_B2_B - [15:0] */
694
695/*
696 * R49 (0x31) - EQ 8
697 */
698#define WM9081_EQ_B2_C_MASK 0xFFFF /* EQ_B2_C - [15:0] */
699#define WM9081_EQ_B2_C_SHIFT 0 /* EQ_B2_C - [15:0] */
700#define WM9081_EQ_B2_C_WIDTH 16 /* EQ_B2_C - [15:0] */
701
702/*
703 * R50 (0x32) - EQ 9
704 */
705#define WM9081_EQ_B2_PG_MASK 0xFFFF /* EQ_B2_PG - [15:0] */
706#define WM9081_EQ_B2_PG_SHIFT 0 /* EQ_B2_PG - [15:0] */
707#define WM9081_EQ_B2_PG_WIDTH 16 /* EQ_B2_PG - [15:0] */
708
709/*
710 * R51 (0x33) - EQ 10
711 */
712#define WM9081_EQ_B4_A_MASK 0xFFFF /* EQ_B4_A - [15:0] */
713#define WM9081_EQ_B4_A_SHIFT 0 /* EQ_B4_A - [15:0] */
714#define WM9081_EQ_B4_A_WIDTH 16 /* EQ_B4_A - [15:0] */
715
716/*
717 * R52 (0x34) - EQ 11
718 */
719#define WM9081_EQ_B4_B_MASK 0xFFFF /* EQ_B4_B - [15:0] */
720#define WM9081_EQ_B4_B_SHIFT 0 /* EQ_B4_B - [15:0] */
721#define WM9081_EQ_B4_B_WIDTH 16 /* EQ_B4_B - [15:0] */
722
723/*
724 * R53 (0x35) - EQ 12
725 */
726#define WM9081_EQ_B4_C_MASK 0xFFFF /* EQ_B4_C - [15:0] */
727#define WM9081_EQ_B4_C_SHIFT 0 /* EQ_B4_C - [15:0] */
728#define WM9081_EQ_B4_C_WIDTH 16 /* EQ_B4_C - [15:0] */
729
730/*
731 * R54 (0x36) - EQ 13
732 */
733#define WM9081_EQ_B4_PG_MASK 0xFFFF /* EQ_B4_PG - [15:0] */
734#define WM9081_EQ_B4_PG_SHIFT 0 /* EQ_B4_PG - [15:0] */
735#define WM9081_EQ_B4_PG_WIDTH 16 /* EQ_B4_PG - [15:0] */
736
737/*
738 * R55 (0x37) - EQ 14
739 */
740#define WM9081_EQ_B3_A_MASK 0xFFFF /* EQ_B3_A - [15:0] */
741#define WM9081_EQ_B3_A_SHIFT 0 /* EQ_B3_A - [15:0] */
742#define WM9081_EQ_B3_A_WIDTH 16 /* EQ_B3_A - [15:0] */
743
744/*
745 * R56 (0x38) - EQ 15
746 */
747#define WM9081_EQ_B3_B_MASK 0xFFFF /* EQ_B3_B - [15:0] */
748#define WM9081_EQ_B3_B_SHIFT 0 /* EQ_B3_B - [15:0] */
749#define WM9081_EQ_B3_B_WIDTH 16 /* EQ_B3_B - [15:0] */
750
751/*
752 * R57 (0x39) - EQ 16
753 */
754#define WM9081_EQ_B3_C_MASK 0xFFFF /* EQ_B3_C - [15:0] */
755#define WM9081_EQ_B3_C_SHIFT 0 /* EQ_B3_C - [15:0] */
756#define WM9081_EQ_B3_C_WIDTH 16 /* EQ_B3_C - [15:0] */
757
758/*
759 * R58 (0x3A) - EQ 17
760 */
761#define WM9081_EQ_B3_PG_MASK 0xFFFF /* EQ_B3_PG - [15:0] */
762#define WM9081_EQ_B3_PG_SHIFT 0 /* EQ_B3_PG - [15:0] */
763#define WM9081_EQ_B3_PG_WIDTH 16 /* EQ_B3_PG - [15:0] */
764
765/*
766 * R59 (0x3B) - EQ 18
767 */
768#define WM9081_EQ_B5_A_MASK 0xFFFF /* EQ_B5_A - [15:0] */
769#define WM9081_EQ_B5_A_SHIFT 0 /* EQ_B5_A - [15:0] */
770#define WM9081_EQ_B5_A_WIDTH 16 /* EQ_B5_A - [15:0] */
771
772/*
773 * R60 (0x3C) - EQ 19
774 */
775#define WM9081_EQ_B5_B_MASK 0xFFFF /* EQ_B5_B - [15:0] */
776#define WM9081_EQ_B5_B_SHIFT 0 /* EQ_B5_B - [15:0] */
777#define WM9081_EQ_B5_B_WIDTH 16 /* EQ_B5_B - [15:0] */
778
779/*
780 * R61 (0x3D) - EQ 20
781 */
782#define WM9081_EQ_B5_PG_MASK 0xFFFF /* EQ_B5_PG - [15:0] */
783#define WM9081_EQ_B5_PG_SHIFT 0 /* EQ_B5_PG - [15:0] */
784#define WM9081_EQ_B5_PG_WIDTH 16 /* EQ_B5_PG - [15:0] */
785
786
787#endif
diff --git a/sound/soc/codecs/wm9705.c b/sound/soc/codecs/wm9705.c
index c2d1a7a18fa3..fa88b463e71f 100644
--- a/sound/soc/codecs/wm9705.c
+++ b/sound/soc/codecs/wm9705.c
@@ -282,14 +282,14 @@ struct snd_soc_dai wm9705_dai[] = {
282 .channels_min = 1, 282 .channels_min = 1,
283 .channels_max = 2, 283 .channels_max = 2,
284 .rates = WM9705_AC97_RATES, 284 .rates = WM9705_AC97_RATES,
285 .formats = SNDRV_PCM_FMTBIT_S16_LE, 285 .formats = SND_SOC_STD_AC97_FMTS,
286 }, 286 },
287 .capture = { 287 .capture = {
288 .stream_name = "HiFi Capture", 288 .stream_name = "HiFi Capture",
289 .channels_min = 1, 289 .channels_min = 1,
290 .channels_max = 2, 290 .channels_max = 2,
291 .rates = WM9705_AC97_RATES, 291 .rates = WM9705_AC97_RATES,
292 .formats = SNDRV_PCM_FMTBIT_S16_LE, 292 .formats = SND_SOC_STD_AC97_FMTS,
293 }, 293 },
294 .ops = &wm9705_dai_ops, 294 .ops = &wm9705_dai_ops,
295 }, 295 },
diff --git a/sound/soc/codecs/wm9712.c b/sound/soc/codecs/wm9712.c
index 765cf1e7369e..1fd4e88f50cf 100644
--- a/sound/soc/codecs/wm9712.c
+++ b/sound/soc/codecs/wm9712.c
@@ -534,13 +534,13 @@ struct snd_soc_dai wm9712_dai[] = {
534 .channels_min = 1, 534 .channels_min = 1,
535 .channels_max = 2, 535 .channels_max = 2,
536 .rates = WM9712_AC97_RATES, 536 .rates = WM9712_AC97_RATES,
537 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 537 .formats = SND_SOC_STD_AC97_FMTS,},
538 .capture = { 538 .capture = {
539 .stream_name = "HiFi Capture", 539 .stream_name = "HiFi Capture",
540 .channels_min = 1, 540 .channels_min = 1,
541 .channels_max = 2, 541 .channels_max = 2,
542 .rates = WM9712_AC97_RATES, 542 .rates = WM9712_AC97_RATES,
543 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 543 .formats = SND_SOC_STD_AC97_FMTS,},
544 .ops = &wm9712_dai_ops_hifi, 544 .ops = &wm9712_dai_ops_hifi,
545}, 545},
546{ 546{
@@ -550,7 +550,7 @@ struct snd_soc_dai wm9712_dai[] = {
550 .channels_min = 1, 550 .channels_min = 1,
551 .channels_max = 1, 551 .channels_max = 1,
552 .rates = WM9712_AC97_RATES, 552 .rates = WM9712_AC97_RATES,
553 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 553 .formats = SND_SOC_STD_AC97_FMTS,},
554 .ops = &wm9712_dai_ops_aux, 554 .ops = &wm9712_dai_ops_aux,
555} 555}
556}; 556};
@@ -585,6 +585,8 @@ static int wm9712_reset(struct snd_soc_codec *codec, int try_warm)
585 } 585 }
586 586
587 soc_ac97_ops.reset(codec->ac97); 587 soc_ac97_ops.reset(codec->ac97);
588 if (soc_ac97_ops.warm_reset)
589 soc_ac97_ops.warm_reset(codec->ac97);
588 if (ac97_read(codec, 0) != wm9712_reg[0]) 590 if (ac97_read(codec, 0) != wm9712_reg[0])
589 goto err; 591 goto err;
590 return 0; 592 return 0;
diff --git a/sound/soc/codecs/wm9713.c b/sound/soc/codecs/wm9713.c
index 523bad077fa0..abed37acf787 100644
--- a/sound/soc/codecs/wm9713.c
+++ b/sound/soc/codecs/wm9713.c
@@ -189,6 +189,26 @@ SOC_SINGLE("3D Lower Cut-off Switch", AC97_REC_GAIN_MIC, 4, 1, 0),
189SOC_SINGLE("3D Depth", AC97_REC_GAIN_MIC, 0, 15, 1), 189SOC_SINGLE("3D Depth", AC97_REC_GAIN_MIC, 0, 15, 1),
190}; 190};
191 191
192static int wm9713_voice_shutdown(struct snd_soc_dapm_widget *w,
193 struct snd_kcontrol *kcontrol, int event)
194{
195 struct snd_soc_codec *codec = w->codec;
196 u16 status, rate;
197
198 BUG_ON(event != SND_SOC_DAPM_PRE_PMD);
199
200 /* Gracefully shut down the voice interface. */
201 status = ac97_read(codec, AC97_EXTENDED_MID) | 0x1000;
202 rate = ac97_read(codec, AC97_HANDSET_RATE) & 0xF0FF;
203 ac97_write(codec, AC97_HANDSET_RATE, rate | 0x0200);
204 schedule_timeout_interruptible(msecs_to_jiffies(1));
205 ac97_write(codec, AC97_HANDSET_RATE, rate | 0x0F00);
206 ac97_write(codec, AC97_EXTENDED_MID, status);
207
208 return 0;
209}
210
211
192/* We have to create a fake left and right HP mixers because 212/* We have to create a fake left and right HP mixers because
193 * the codec only has a single control that is shared by both channels. 213 * the codec only has a single control that is shared by both channels.
194 * This makes it impossible to determine the audio path using the current 214 * This makes it impossible to determine the audio path using the current
@@ -400,7 +420,8 @@ SND_SOC_DAPM_MIXER("AC97 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
400SND_SOC_DAPM_MIXER("HP Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 420SND_SOC_DAPM_MIXER("HP Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
401SND_SOC_DAPM_MIXER("Line Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 421SND_SOC_DAPM_MIXER("Line Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
402SND_SOC_DAPM_MIXER("Capture Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 422SND_SOC_DAPM_MIXER("Capture Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
403SND_SOC_DAPM_DAC("Voice DAC", "Voice Playback", AC97_EXTENDED_MID, 12, 1), 423SND_SOC_DAPM_DAC_E("Voice DAC", "Voice Playback", AC97_EXTENDED_MID, 12, 1,
424 wm9713_voice_shutdown, SND_SOC_DAPM_PRE_PMD),
404SND_SOC_DAPM_DAC("Aux DAC", "Aux Playback", AC97_EXTENDED_MID, 11, 1), 425SND_SOC_DAPM_DAC("Aux DAC", "Aux Playback", AC97_EXTENDED_MID, 11, 1),
405SND_SOC_DAPM_PGA("Left ADC", AC97_EXTENDED_MID, 5, 1, NULL, 0), 426SND_SOC_DAPM_PGA("Left ADC", AC97_EXTENDED_MID, 5, 1, NULL, 0),
406SND_SOC_DAPM_PGA("Right ADC", AC97_EXTENDED_MID, 4, 1, NULL, 0), 427SND_SOC_DAPM_PGA("Right ADC", AC97_EXTENDED_MID, 4, 1, NULL, 0),
@@ -689,7 +710,7 @@ static void pll_factors(struct _pll_div *pll_div, unsigned int source)
689 Ndiv = target / source; 710 Ndiv = target / source;
690 if ((Ndiv < 5) || (Ndiv > 12)) 711 if ((Ndiv < 5) || (Ndiv > 12))
691 printk(KERN_WARNING 712 printk(KERN_WARNING
692 "WM9713 PLL N value %d out of recommended range!\n", 713 "WM9713 PLL N value %u out of recommended range!\n",
693 Ndiv); 714 Ndiv);
694 715
695 pll_div->n = Ndiv; 716 pll_div->n = Ndiv;
@@ -936,21 +957,6 @@ static int wm9713_pcm_hw_params(struct snd_pcm_substream *substream,
936 return 0; 957 return 0;
937} 958}
938 959
939static void wm9713_voiceshutdown(struct snd_pcm_substream *substream,
940 struct snd_soc_dai *dai)
941{
942 struct snd_soc_codec *codec = dai->codec;
943 u16 status, rate;
944
945 /* Gracefully shut down the voice interface. */
946 status = ac97_read(codec, AC97_EXTENDED_STATUS) | 0x1000;
947 rate = ac97_read(codec, AC97_HANDSET_RATE) & 0xF0FF;
948 ac97_write(codec, AC97_HANDSET_RATE, rate | 0x0200);
949 schedule_timeout_interruptible(msecs_to_jiffies(1));
950 ac97_write(codec, AC97_HANDSET_RATE, rate | 0x0F00);
951 ac97_write(codec, AC97_EXTENDED_MID, status);
952}
953
954static int ac97_hifi_prepare(struct snd_pcm_substream *substream, 960static int ac97_hifi_prepare(struct snd_pcm_substream *substream,
955 struct snd_soc_dai *dai) 961 struct snd_soc_dai *dai)
956{ 962{
@@ -1019,7 +1025,6 @@ static struct snd_soc_dai_ops wm9713_dai_ops_aux = {
1019 1025
1020static struct snd_soc_dai_ops wm9713_dai_ops_voice = { 1026static struct snd_soc_dai_ops wm9713_dai_ops_voice = {
1021 .hw_params = wm9713_pcm_hw_params, 1027 .hw_params = wm9713_pcm_hw_params,
1022 .shutdown = wm9713_voiceshutdown,
1023 .set_clkdiv = wm9713_set_dai_clkdiv, 1028 .set_clkdiv = wm9713_set_dai_clkdiv,
1024 .set_pll = wm9713_set_dai_pll, 1029 .set_pll = wm9713_set_dai_pll,
1025 .set_fmt = wm9713_set_dai_fmt, 1030 .set_fmt = wm9713_set_dai_fmt,
@@ -1035,13 +1040,13 @@ struct snd_soc_dai wm9713_dai[] = {
1035 .channels_min = 1, 1040 .channels_min = 1,
1036 .channels_max = 2, 1041 .channels_max = 2,
1037 .rates = WM9713_RATES, 1042 .rates = WM9713_RATES,
1038 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 1043 .formats = SND_SOC_STD_AC97_FMTS,},
1039 .capture = { 1044 .capture = {
1040 .stream_name = "HiFi Capture", 1045 .stream_name = "HiFi Capture",
1041 .channels_min = 1, 1046 .channels_min = 1,
1042 .channels_max = 2, 1047 .channels_max = 2,
1043 .rates = WM9713_RATES, 1048 .rates = WM9713_RATES,
1044 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 1049 .formats = SND_SOC_STD_AC97_FMTS,},
1045 .ops = &wm9713_dai_ops_hifi, 1050 .ops = &wm9713_dai_ops_hifi,
1046 }, 1051 },
1047 { 1052 {
@@ -1051,7 +1056,7 @@ struct snd_soc_dai wm9713_dai[] = {
1051 .channels_min = 1, 1056 .channels_min = 1,
1052 .channels_max = 1, 1057 .channels_max = 1,
1053 .rates = WM9713_RATES, 1058 .rates = WM9713_RATES,
1054 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 1059 .formats = SND_SOC_STD_AC97_FMTS,},
1055 .ops = &wm9713_dai_ops_aux, 1060 .ops = &wm9713_dai_ops_aux,
1056 }, 1061 },
1057 { 1062 {
@@ -1069,6 +1074,7 @@ struct snd_soc_dai wm9713_dai[] = {
1069 .rates = WM9713_PCM_RATES, 1074 .rates = WM9713_PCM_RATES,
1070 .formats = WM9713_PCM_FORMATS,}, 1075 .formats = WM9713_PCM_FORMATS,},
1071 .ops = &wm9713_dai_ops_voice, 1076 .ops = &wm9713_dai_ops_voice,
1077 .symmetric_rates = 1,
1072 }, 1078 },
1073}; 1079};
1074EXPORT_SYMBOL_GPL(wm9713_dai); 1080EXPORT_SYMBOL_GPL(wm9713_dai);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 18:07:08 -0500