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-rw-r--r--sound/soc/codecs/Kconfig20
-rw-r--r--sound/soc/codecs/Makefile12
-rw-r--r--sound/soc/codecs/ac97.c6
-rw-r--r--sound/soc/codecs/ad1836.c4
-rw-r--r--sound/soc/codecs/ad193x.c4
-rw-r--r--sound/soc/codecs/adau1701.c3
-rw-r--r--sound/soc/codecs/ak4104.c3
-rw-r--r--sound/soc/codecs/ak4535.c3
-rw-r--r--sound/soc/codecs/ak4641.c113
-rw-r--r--sound/soc/codecs/alc5623.c23
-rw-r--r--sound/soc/codecs/alc5632.c31
-rw-r--r--sound/soc/codecs/cs4270.c11
-rw-r--r--sound/soc/codecs/cs4271.c3
-rw-r--r--sound/soc/codecs/cs42l51.c9
-rw-r--r--sound/soc/codecs/cs42l52.c1295
-rw-r--r--sound/soc/codecs/cs42l52.h274
-rw-r--r--sound/soc/codecs/cs42l73.c93
-rw-r--r--sound/soc/codecs/da7210.c379
-rw-r--r--sound/soc/codecs/jz4740.c3
-rw-r--r--sound/soc/codecs/lm49453.c1550
-rw-r--r--sound/soc/codecs/lm49453.h380
-rw-r--r--sound/soc/codecs/max98095.c158
-rw-r--r--sound/soc/codecs/max98095.h22
-rw-r--r--sound/soc/codecs/mc13783.c786
-rw-r--r--sound/soc/codecs/mc13783.h28
-rw-r--r--sound/soc/codecs/ml26124.c681
-rw-r--r--sound/soc/codecs/ml26124.h184
-rw-r--r--sound/soc/codecs/omap-hdmi.c69
-rw-r--r--sound/soc/codecs/rt5631.c110
-rw-r--r--sound/soc/codecs/sgtl5000.c25
-rw-r--r--sound/soc/codecs/ssm2602.c138
-rw-r--r--sound/soc/codecs/sta32x.c3
-rw-r--r--sound/soc/codecs/tlv320aic23.c13
-rw-r--r--sound/soc/codecs/tlv320aic26.c3
-rw-r--r--sound/soc/codecs/tlv320aic3x.c21
-rw-r--r--sound/soc/codecs/tlv320dac33.c35
-rw-r--r--sound/soc/codecs/twl4030.c18
-rw-r--r--sound/soc/codecs/twl6040.c450
-rw-r--r--sound/soc/codecs/uda134x.c6
-rw-r--r--sound/soc/codecs/uda1380.c6
-rw-r--r--sound/soc/codecs/wl1273.c6
-rw-r--r--sound/soc/codecs/wm1250-ev1.c65
-rw-r--r--sound/soc/codecs/wm5100-tables.c125
-rw-r--r--sound/soc/codecs/wm5100.c47
-rw-r--r--sound/soc/codecs/wm5100.h159
-rw-r--r--sound/soc/codecs/wm8350.c187
-rw-r--r--sound/soc/codecs/wm8400.c135
-rw-r--r--sound/soc/codecs/wm8510.c3
-rw-r--r--sound/soc/codecs/wm8523.c3
-rw-r--r--sound/soc/codecs/wm8728.c3
-rw-r--r--sound/soc/codecs/wm8731.c37
-rw-r--r--sound/soc/codecs/wm8737.c3
-rw-r--r--sound/soc/codecs/wm8741.c3
-rw-r--r--sound/soc/codecs/wm8750.c3
-rw-r--r--sound/soc/codecs/wm8753.c6
-rw-r--r--sound/soc/codecs/wm8900.c3
-rw-r--r--sound/soc/codecs/wm8903.c3
-rw-r--r--sound/soc/codecs/wm8940.c3
-rw-r--r--sound/soc/codecs/wm8960.c3
-rw-r--r--sound/soc/codecs/wm8962.c18
-rw-r--r--sound/soc/codecs/wm8971.c3
-rw-r--r--sound/soc/codecs/wm8978.c3
-rw-r--r--sound/soc/codecs/wm8988.c3
-rw-r--r--sound/soc/codecs/wm8990.c3
-rw-r--r--sound/soc/codecs/wm8993.c86
-rw-r--r--sound/soc/codecs/wm8994.c290
-rw-r--r--sound/soc/codecs/wm8994.h3
-rw-r--r--sound/soc/codecs/wm8996.c12
-rw-r--r--sound/soc/codecs/wm9081.c5
-rw-r--r--sound/soc/codecs/wm9705.c6
-rw-r--r--sound/soc/codecs/wm9712.c10
-rw-r--r--sound/soc/codecs/wm_hubs.c220
-rw-r--r--sound/soc/codecs/wm_hubs.h12
73 files changed, 6966 insertions, 1480 deletions
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 59d8efaa17e9..1e1613a438dd 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -29,6 +29,7 @@ config SND_SOC_ALL_CODECS
29 select SND_SOC_ALC5632 if I2C 29 select SND_SOC_ALC5632 if I2C
30 select SND_SOC_CQ0093VC if MFD_DAVINCI_VOICECODEC 30 select SND_SOC_CQ0093VC if MFD_DAVINCI_VOICECODEC
31 select SND_SOC_CS42L51 if I2C 31 select SND_SOC_CS42L51 if I2C
32 select SND_SOC_CS42L52 if I2C
32 select SND_SOC_CS42L73 if I2C 33 select SND_SOC_CS42L73 if I2C
33 select SND_SOC_CS4270 if I2C 34 select SND_SOC_CS4270 if I2C
34 select SND_SOC_CS4271 if SND_SOC_I2C_AND_SPI 35 select SND_SOC_CS4271 if SND_SOC_I2C_AND_SPI
@@ -37,11 +38,15 @@ config SND_SOC_ALL_CODECS
37 select SND_SOC_DFBMCS320 38 select SND_SOC_DFBMCS320
38 select SND_SOC_JZ4740_CODEC 39 select SND_SOC_JZ4740_CODEC
39 select SND_SOC_LM4857 if I2C 40 select SND_SOC_LM4857 if I2C
41 select SND_SOC_LM49453 if I2C
40 select SND_SOC_MAX98088 if I2C 42 select SND_SOC_MAX98088 if I2C
41 select SND_SOC_MAX98095 if I2C 43 select SND_SOC_MAX98095 if I2C
42 select SND_SOC_MAX9850 if I2C 44 select SND_SOC_MAX9850 if I2C
43 select SND_SOC_MAX9768 if I2C 45 select SND_SOC_MAX9768 if I2C
44 select SND_SOC_MAX9877 if I2C 46 select SND_SOC_MAX9877 if I2C
47 select SND_SOC_MC13783 if MFD_MC13XXX
48 select SND_SOC_ML26124 if I2C
49 select SND_SOC_OMAP_HDMI_CODEC if OMAP4_DSS_HDMI
45 select SND_SOC_PCM3008 50 select SND_SOC_PCM3008
46 select SND_SOC_RT5631 if I2C 51 select SND_SOC_RT5631 if I2C
47 select SND_SOC_SGTL5000 if I2C 52 select SND_SOC_SGTL5000 if I2C
@@ -181,6 +186,9 @@ config SND_SOC_CQ0093VC
181config SND_SOC_CS42L51 186config SND_SOC_CS42L51
182 tristate 187 tristate
183 188
189config SND_SOC_CS42L52
190 tristate
191
184config SND_SOC_CS42L73 192config SND_SOC_CS42L73
185 tristate 193 tristate
186 194
@@ -217,6 +225,9 @@ config SND_SOC_DFBMCS320
217config SND_SOC_DMIC 225config SND_SOC_DMIC
218 tristate 226 tristate
219 227
228config SND_SOC_LM49453
229 tristate
230
220config SND_SOC_MAX98088 231config SND_SOC_MAX98088
221 tristate 232 tristate
222 233
@@ -226,6 +237,9 @@ config SND_SOC_MAX98095
226config SND_SOC_MAX9850 237config SND_SOC_MAX9850
227 tristate 238 tristate
228 239
240config SND_SOC_OMAP_HDMI_CODEC
241 tristate
242
229config SND_SOC_PCM3008 243config SND_SOC_PCM3008
230 tristate 244 tristate
231 245
@@ -435,5 +449,11 @@ config SND_SOC_MAX9768
435config SND_SOC_MAX9877 449config SND_SOC_MAX9877
436 tristate 450 tristate
437 451
452config SND_SOC_MC13783
453 tristate
454
455config SND_SOC_ML26124
456 tristate
457
438config SND_SOC_TPA6130A2 458config SND_SOC_TPA6130A2
439 tristate 459 tristate
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 6662eb0cdcc0..fc27fec39487 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -15,6 +15,7 @@ snd-soc-ak4642-objs := ak4642.o
15snd-soc-ak4671-objs := ak4671.o 15snd-soc-ak4671-objs := ak4671.o
16snd-soc-cq93vc-objs := cq93vc.o 16snd-soc-cq93vc-objs := cq93vc.o
17snd-soc-cs42l51-objs := cs42l51.o 17snd-soc-cs42l51-objs := cs42l51.o
18snd-soc-cs42l52-objs := cs42l52.o
18snd-soc-cs42l73-objs := cs42l73.o 19snd-soc-cs42l73-objs := cs42l73.o
19snd-soc-cs4270-objs := cs4270.o 20snd-soc-cs4270-objs := cs4270.o
20snd-soc-cs4271-objs := cs4271.o 21snd-soc-cs4271-objs := cs4271.o
@@ -25,10 +26,14 @@ snd-soc-dmic-objs := dmic.o
25snd-soc-jz4740-codec-objs := jz4740.o 26snd-soc-jz4740-codec-objs := jz4740.o
26snd-soc-l3-objs := l3.o 27snd-soc-l3-objs := l3.o
27snd-soc-lm4857-objs := lm4857.o 28snd-soc-lm4857-objs := lm4857.o
29snd-soc-lm49453-objs := lm49453.o
28snd-soc-max9768-objs := max9768.o 30snd-soc-max9768-objs := max9768.o
29snd-soc-max98088-objs := max98088.o 31snd-soc-max98088-objs := max98088.o
30snd-soc-max98095-objs := max98095.o 32snd-soc-max98095-objs := max98095.o
31snd-soc-max9850-objs := max9850.o 33snd-soc-max9850-objs := max9850.o
34snd-soc-mc13783-objs := mc13783.o
35snd-soc-ml26124-objs := ml26124.o
36snd-soc-omap-hdmi-codec-objs := omap-hdmi.o
32snd-soc-pcm3008-objs := pcm3008.o 37snd-soc-pcm3008-objs := pcm3008.o
33snd-soc-rt5631-objs := rt5631.o 38snd-soc-rt5631-objs := rt5631.o
34snd-soc-sgtl5000-objs := sgtl5000.o 39snd-soc-sgtl5000-objs := sgtl5000.o
@@ -121,6 +126,7 @@ obj-$(CONFIG_SND_SOC_ALC5623) += snd-soc-alc5623.o
121obj-$(CONFIG_SND_SOC_ALC5632) += snd-soc-alc5632.o 126obj-$(CONFIG_SND_SOC_ALC5632) += snd-soc-alc5632.o
122obj-$(CONFIG_SND_SOC_CQ0093VC) += snd-soc-cq93vc.o 127obj-$(CONFIG_SND_SOC_CQ0093VC) += snd-soc-cq93vc.o
123obj-$(CONFIG_SND_SOC_CS42L51) += snd-soc-cs42l51.o 128obj-$(CONFIG_SND_SOC_CS42L51) += snd-soc-cs42l51.o
129obj-$(CONFIG_SND_SOC_CS42L52) += snd-soc-cs42l52.o
124obj-$(CONFIG_SND_SOC_CS42L73) += snd-soc-cs42l73.o 130obj-$(CONFIG_SND_SOC_CS42L73) += snd-soc-cs42l73.o
125obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o 131obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o
126obj-$(CONFIG_SND_SOC_CS4271) += snd-soc-cs4271.o 132obj-$(CONFIG_SND_SOC_CS4271) += snd-soc-cs4271.o
@@ -128,13 +134,17 @@ obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o
128obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o 134obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o
129obj-$(CONFIG_SND_SOC_DFBMCS320) += snd-soc-dfbmcs320.o 135obj-$(CONFIG_SND_SOC_DFBMCS320) += snd-soc-dfbmcs320.o
130obj-$(CONFIG_SND_SOC_DMIC) += snd-soc-dmic.o 136obj-$(CONFIG_SND_SOC_DMIC) += snd-soc-dmic.o
137obj-$(CONFIG_SND_SOC_JZ4740_CODEC) += snd-soc-jz4740-codec.o
131obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o 138obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o
132obj-$(CONFIG_SND_SOC_LM4857) += snd-soc-lm4857.o 139obj-$(CONFIG_SND_SOC_LM4857) += snd-soc-lm4857.o
133obj-$(CONFIG_SND_SOC_JZ4740_CODEC) += snd-soc-jz4740-codec.o 140obj-$(CONFIG_SND_SOC_LM49453) += snd-soc-lm49453.o
134obj-$(CONFIG_SND_SOC_MAX9768) += snd-soc-max9768.o 141obj-$(CONFIG_SND_SOC_MAX9768) += snd-soc-max9768.o
135obj-$(CONFIG_SND_SOC_MAX98088) += snd-soc-max98088.o 142obj-$(CONFIG_SND_SOC_MAX98088) += snd-soc-max98088.o
136obj-$(CONFIG_SND_SOC_MAX98095) += snd-soc-max98095.o 143obj-$(CONFIG_SND_SOC_MAX98095) += snd-soc-max98095.o
137obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o 144obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o
145obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o
146obj-$(CONFIG_SND_SOC_ML26124) += snd-soc-ml26124.o
147obj-$(CONFIG_SND_SOC_OMAP_HDMI_CODEC) += snd-soc-omap-hdmi-codec.o
138obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o 148obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o
139obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o 149obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o
140obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o 150obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o
diff --git a/sound/soc/codecs/ac97.c b/sound/soc/codecs/ac97.c
index 1bbad4c16d28..2023c749f232 100644
--- a/sound/soc/codecs/ac97.c
+++ b/sound/soc/codecs/ac97.c
@@ -26,13 +26,11 @@
26static int ac97_prepare(struct snd_pcm_substream *substream, 26static int ac97_prepare(struct snd_pcm_substream *substream,
27 struct snd_soc_dai *dai) 27 struct snd_soc_dai *dai)
28{ 28{
29 struct snd_pcm_runtime *runtime = substream->runtime; 29 struct snd_soc_codec *codec = dai->codec;
30 struct snd_soc_pcm_runtime *rtd = substream->private_data;
31 struct snd_soc_codec *codec = rtd->codec;
32 30
33 int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 31 int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
34 AC97_PCM_FRONT_DAC_RATE : AC97_PCM_LR_ADC_RATE; 32 AC97_PCM_FRONT_DAC_RATE : AC97_PCM_LR_ADC_RATE;
35 return snd_ac97_set_rate(codec->ac97, reg, runtime->rate); 33 return snd_ac97_set_rate(codec->ac97, reg, substream->runtime->rate);
36} 34}
37 35
38#define STD_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 36#define STD_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
diff --git a/sound/soc/codecs/ad1836.c b/sound/soc/codecs/ad1836.c
index 12e3b4118557..c67b50d8b317 100644
--- a/sound/soc/codecs/ad1836.c
+++ b/sound/soc/codecs/ad1836.c
@@ -162,9 +162,7 @@ static int ad1836_hw_params(struct snd_pcm_substream *substream,
162 struct snd_soc_dai *dai) 162 struct snd_soc_dai *dai)
163{ 163{
164 int word_len = 0; 164 int word_len = 0;
165 165 struct snd_soc_codec *codec = dai->codec;
166 struct snd_soc_pcm_runtime *rtd = substream->private_data;
167 struct snd_soc_codec *codec = rtd->codec;
168 166
169 /* bit size */ 167 /* bit size */
170 switch (params_format(params)) { 168 switch (params_format(params)) {
diff --git a/sound/soc/codecs/ad193x.c b/sound/soc/codecs/ad193x.c
index a4a6bef2c0bb..13e62be4f990 100644
--- a/sound/soc/codecs/ad193x.c
+++ b/sound/soc/codecs/ad193x.c
@@ -245,9 +245,7 @@ static int ad193x_hw_params(struct snd_pcm_substream *substream,
245 struct snd_soc_dai *dai) 245 struct snd_soc_dai *dai)
246{ 246{
247 int word_len = 0, master_rate = 0; 247 int word_len = 0, master_rate = 0;
248 248 struct snd_soc_codec *codec = dai->codec;
249 struct snd_soc_pcm_runtime *rtd = substream->private_data;
250 struct snd_soc_codec *codec = rtd->codec;
251 struct ad193x_priv *ad193x = snd_soc_codec_get_drvdata(codec); 249 struct ad193x_priv *ad193x = snd_soc_codec_get_drvdata(codec);
252 250
253 /* bit size */ 251 /* bit size */
diff --git a/sound/soc/codecs/adau1701.c b/sound/soc/codecs/adau1701.c
index 78e9ce48bb99..3d50fc8646b6 100644
--- a/sound/soc/codecs/adau1701.c
+++ b/sound/soc/codecs/adau1701.c
@@ -258,8 +258,7 @@ static int adau1701_set_playback_pcm_format(struct snd_soc_codec *codec,
258static int adau1701_hw_params(struct snd_pcm_substream *substream, 258static int adau1701_hw_params(struct snd_pcm_substream *substream,
259 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 259 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
260{ 260{
261 struct snd_soc_pcm_runtime *rtd = substream->private_data; 261 struct snd_soc_codec *codec = dai->codec;
262 struct snd_soc_codec *codec = rtd->codec;
263 snd_pcm_format_t format; 262 snd_pcm_format_t format;
264 unsigned int val; 263 unsigned int val;
265 264
diff --git a/sound/soc/codecs/ak4104.c b/sound/soc/codecs/ak4104.c
index ceb96ecf5588..31d4483245d0 100644
--- a/sound/soc/codecs/ak4104.c
+++ b/sound/soc/codecs/ak4104.c
@@ -88,8 +88,7 @@ static int ak4104_hw_params(struct snd_pcm_substream *substream,
88 struct snd_pcm_hw_params *params, 88 struct snd_pcm_hw_params *params,
89 struct snd_soc_dai *dai) 89 struct snd_soc_dai *dai)
90{ 90{
91 struct snd_soc_pcm_runtime *rtd = substream->private_data; 91 struct snd_soc_codec *codec = dai->codec;
92 struct snd_soc_codec *codec = rtd->codec;
93 int val = 0; 92 int val = 0;
94 93
95 /* set the IEC958 bits: consumer mode, no copyright bit */ 94 /* set the IEC958 bits: consumer mode, no copyright bit */
diff --git a/sound/soc/codecs/ak4535.c b/sound/soc/codecs/ak4535.c
index 838ae8b22b50..618fdc30f73e 100644
--- a/sound/soc/codecs/ak4535.c
+++ b/sound/soc/codecs/ak4535.c
@@ -262,8 +262,7 @@ static int ak4535_hw_params(struct snd_pcm_substream *substream,
262 struct snd_pcm_hw_params *params, 262 struct snd_pcm_hw_params *params,
263 struct snd_soc_dai *dai) 263 struct snd_soc_dai *dai)
264{ 264{
265 struct snd_soc_pcm_runtime *rtd = substream->private_data; 265 struct snd_soc_codec *codec = dai->codec;
266 struct snd_soc_codec *codec = rtd->codec;
267 struct ak4535_priv *ak4535 = snd_soc_codec_get_drvdata(codec); 266 struct ak4535_priv *ak4535 = snd_soc_codec_get_drvdata(codec);
268 u8 mode2 = snd_soc_read(codec, AK4535_MODE2) & ~(0x3 << 5); 267 u8 mode2 = snd_soc_read(codec, AK4535_MODE2) & ~(0x3 << 5);
269 int rate = params_rate(params), fs = 256; 268 int rate = params_rate(params), fs = 256;
diff --git a/sound/soc/codecs/ak4641.c b/sound/soc/codecs/ak4641.c
index c4d165a4bddf..543a12f471be 100644
--- a/sound/soc/codecs/ak4641.c
+++ b/sound/soc/codecs/ak4641.c
@@ -296,8 +296,7 @@ static int ak4641_i2s_hw_params(struct snd_pcm_substream *substream,
296 struct snd_pcm_hw_params *params, 296 struct snd_pcm_hw_params *params,
297 struct snd_soc_dai *dai) 297 struct snd_soc_dai *dai)
298{ 298{
299 struct snd_soc_pcm_runtime *rtd = substream->private_data; 299 struct snd_soc_codec *codec = dai->codec;
300 struct snd_soc_codec *codec = rtd->codec;
301 struct ak4641_priv *ak4641 = snd_soc_codec_get_drvdata(codec); 300 struct ak4641_priv *ak4641 = snd_soc_codec_get_drvdata(codec);
302 int rate = params_rate(params), fs = 256; 301 int rate = params_rate(params), fs = 256;
303 u8 mode2; 302 u8 mode2;
@@ -517,67 +516,24 @@ static int ak4641_resume(struct snd_soc_codec *codec)
517 516
518static int ak4641_probe(struct snd_soc_codec *codec) 517static int ak4641_probe(struct snd_soc_codec *codec)
519{ 518{
520 struct ak4641_platform_data *pdata = codec->dev->platform_data;
521 int ret; 519 int ret;
522 520
523
524 if (pdata) {
525 if (gpio_is_valid(pdata->gpio_power)) {
526 ret = gpio_request_one(pdata->gpio_power,
527 GPIOF_OUT_INIT_LOW, "ak4641 power");
528 if (ret)
529 goto err_out;
530 }
531 if (gpio_is_valid(pdata->gpio_npdn)) {
532 ret = gpio_request_one(pdata->gpio_npdn,
533 GPIOF_OUT_INIT_LOW, "ak4641 npdn");
534 if (ret)
535 goto err_gpio;
536
537 udelay(1); /* > 150 ns */
538 gpio_set_value(pdata->gpio_npdn, 1);
539 }
540 }
541
542 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); 521 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
543 if (ret != 0) { 522 if (ret != 0) {
544 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 523 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
545 goto err_register; 524 return ret;
546 } 525 }
547 526
548 /* power on device */ 527 /* power on device */
549 ak4641_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 528 ak4641_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
550 529
551 return 0; 530 return 0;
552
553err_register:
554 if (pdata) {
555 if (gpio_is_valid(pdata->gpio_power))
556 gpio_set_value(pdata->gpio_power, 0);
557 if (gpio_is_valid(pdata->gpio_npdn))
558 gpio_free(pdata->gpio_npdn);
559 }
560err_gpio:
561 if (pdata && gpio_is_valid(pdata->gpio_power))
562 gpio_free(pdata->gpio_power);
563err_out:
564 return ret;
565} 531}
566 532
567static int ak4641_remove(struct snd_soc_codec *codec) 533static int ak4641_remove(struct snd_soc_codec *codec)
568{ 534{
569 struct ak4641_platform_data *pdata = codec->dev->platform_data;
570
571 ak4641_set_bias_level(codec, SND_SOC_BIAS_OFF); 535 ak4641_set_bias_level(codec, SND_SOC_BIAS_OFF);
572 536
573 if (pdata) {
574 if (gpio_is_valid(pdata->gpio_power)) {
575 gpio_set_value(pdata->gpio_power, 0);
576 gpio_free(pdata->gpio_power);
577 }
578 if (gpio_is_valid(pdata->gpio_npdn))
579 gpio_free(pdata->gpio_npdn);
580 }
581 return 0; 537 return 0;
582} 538}
583 539
@@ -604,6 +560,7 @@ static struct snd_soc_codec_driver soc_codec_dev_ak4641 = {
604static int __devinit ak4641_i2c_probe(struct i2c_client *i2c, 560static int __devinit ak4641_i2c_probe(struct i2c_client *i2c,
605 const struct i2c_device_id *id) 561 const struct i2c_device_id *id)
606{ 562{
563 struct ak4641_platform_data *pdata = i2c->dev.platform_data;
607 struct ak4641_priv *ak4641; 564 struct ak4641_priv *ak4641;
608 int ret; 565 int ret;
609 566
@@ -612,16 +569,62 @@ static int __devinit ak4641_i2c_probe(struct i2c_client *i2c,
612 if (!ak4641) 569 if (!ak4641)
613 return -ENOMEM; 570 return -ENOMEM;
614 571
572 if (pdata) {
573 if (gpio_is_valid(pdata->gpio_power)) {
574 ret = gpio_request_one(pdata->gpio_power,
575 GPIOF_OUT_INIT_LOW, "ak4641 power");
576 if (ret)
577 goto err_out;
578 }
579 if (gpio_is_valid(pdata->gpio_npdn)) {
580 ret = gpio_request_one(pdata->gpio_npdn,
581 GPIOF_OUT_INIT_LOW, "ak4641 npdn");
582 if (ret)
583 goto err_gpio;
584
585 udelay(1); /* > 150 ns */
586 gpio_set_value(pdata->gpio_npdn, 1);
587 }
588 }
589
615 i2c_set_clientdata(i2c, ak4641); 590 i2c_set_clientdata(i2c, ak4641);
616 591
617 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_ak4641, 592 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_ak4641,
618 ak4641_dai, ARRAY_SIZE(ak4641_dai)); 593 ak4641_dai, ARRAY_SIZE(ak4641_dai));
594 if (ret != 0)
595 goto err_gpio2;
596
597 return 0;
598
599err_gpio2:
600 if (pdata) {
601 if (gpio_is_valid(pdata->gpio_power))
602 gpio_set_value(pdata->gpio_power, 0);
603 if (gpio_is_valid(pdata->gpio_npdn))
604 gpio_free(pdata->gpio_npdn);
605 }
606err_gpio:
607 if (pdata && gpio_is_valid(pdata->gpio_power))
608 gpio_free(pdata->gpio_power);
609err_out:
619 return ret; 610 return ret;
620} 611}
621 612
622static int __devexit ak4641_i2c_remove(struct i2c_client *i2c) 613static int __devexit ak4641_i2c_remove(struct i2c_client *i2c)
623{ 614{
615 struct ak4641_platform_data *pdata = i2c->dev.platform_data;
616
624 snd_soc_unregister_codec(&i2c->dev); 617 snd_soc_unregister_codec(&i2c->dev);
618
619 if (pdata) {
620 if (gpio_is_valid(pdata->gpio_power)) {
621 gpio_set_value(pdata->gpio_power, 0);
622 gpio_free(pdata->gpio_power);
623 }
624 if (gpio_is_valid(pdata->gpio_npdn))
625 gpio_free(pdata->gpio_npdn);
626 }
627
625 return 0; 628 return 0;
626} 629}
627 630
@@ -641,23 +644,7 @@ static struct i2c_driver ak4641_i2c_driver = {
641 .id_table = ak4641_i2c_id, 644 .id_table = ak4641_i2c_id,
642}; 645};
643 646
644static int __init ak4641_modinit(void) 647module_i2c_driver(ak4641_i2c_driver);
645{
646 int ret;
647
648 ret = i2c_add_driver(&ak4641_i2c_driver);
649 if (ret != 0)
650 pr_err("Failed to register AK4641 I2C driver: %d\n", ret);
651
652 return ret;
653}
654module_init(ak4641_modinit);
655
656static void __exit ak4641_exit(void)
657{
658 i2c_del_driver(&ak4641_i2c_driver);
659}
660module_exit(ak4641_exit);
661 648
662MODULE_DESCRIPTION("SoC AK4641 driver"); 649MODULE_DESCRIPTION("SoC AK4641 driver");
663MODULE_AUTHOR("Harald Welte <laforge@gnufiish.org>"); 650MODULE_AUTHOR("Harald Welte <laforge@gnufiish.org>");
diff --git a/sound/soc/codecs/alc5623.c b/sound/soc/codecs/alc5623.c
index d47b62ddb210..1960478ce6bb 100644
--- a/sound/soc/codecs/alc5623.c
+++ b/sound/soc/codecs/alc5623.c
@@ -705,8 +705,7 @@ static int alc5623_set_dai_fmt(struct snd_soc_dai *codec_dai,
705static int alc5623_pcm_hw_params(struct snd_pcm_substream *substream, 705static int alc5623_pcm_hw_params(struct snd_pcm_substream *substream,
706 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 706 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
707{ 707{
708 struct snd_soc_pcm_runtime *rtd = substream->private_data; 708 struct snd_soc_codec *codec = dai->codec;
709 struct snd_soc_codec *codec = rtd->codec;
710 struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec); 709 struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec);
711 int coeff, rate; 710 int coeff, rate;
712 u16 iface; 711 u16 iface;
@@ -1084,25 +1083,7 @@ static struct i2c_driver alc5623_i2c_driver = {
1084 .id_table = alc5623_i2c_table, 1083 .id_table = alc5623_i2c_table,
1085}; 1084};
1086 1085
1087static int __init alc5623_modinit(void) 1086module_i2c_driver(alc5623_i2c_driver);
1088{
1089 int ret;
1090
1091 ret = i2c_add_driver(&alc5623_i2c_driver);
1092 if (ret != 0) {
1093 printk(KERN_ERR "%s: can't add i2c driver", __func__);
1094 return ret;
1095 }
1096
1097 return ret;
1098}
1099module_init(alc5623_modinit);
1100
1101static void __exit alc5623_modexit(void)
1102{
1103 i2c_del_driver(&alc5623_i2c_driver);
1104}
1105module_exit(alc5623_modexit);
1106 1087
1107MODULE_DESCRIPTION("ASoC alc5621/2/3 driver"); 1088MODULE_DESCRIPTION("ASoC alc5621/2/3 driver");
1108MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>"); 1089MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
diff --git a/sound/soc/codecs/alc5632.c b/sound/soc/codecs/alc5632.c
index e2111e0ccad7..7dd02420b36d 100644
--- a/sound/soc/codecs/alc5632.c
+++ b/sound/soc/codecs/alc5632.c
@@ -861,8 +861,7 @@ static int alc5632_set_dai_fmt(struct snd_soc_dai *codec_dai,
861static int alc5632_pcm_hw_params(struct snd_pcm_substream *substream, 861static int alc5632_pcm_hw_params(struct snd_pcm_substream *substream,
862 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 862 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
863{ 863{
864 struct snd_soc_pcm_runtime *rtd = substream->private_data; 864 struct snd_soc_codec *codec = dai->codec;
865 struct snd_soc_codec *codec = rtd->codec;
866 int coeff, rate; 865 int coeff, rate;
867 u16 iface; 866 u16 iface;
868 867
@@ -1131,7 +1130,7 @@ static __devinit int alc5632_i2c_probe(struct i2c_client *client,
1131 1130
1132 i2c_set_clientdata(client, alc5632); 1131 i2c_set_clientdata(client, alc5632);
1133 1132
1134 alc5632->regmap = regmap_init_i2c(client, &alc5632_regmap); 1133 alc5632->regmap = devm_regmap_init_i2c(client, &alc5632_regmap);
1135 if (IS_ERR(alc5632->regmap)) { 1134 if (IS_ERR(alc5632->regmap)) {
1136 ret = PTR_ERR(alc5632->regmap); 1135 ret = PTR_ERR(alc5632->regmap);
1137 dev_err(&client->dev, "regmap_init() failed: %d\n", ret); 1136 dev_err(&client->dev, "regmap_init() failed: %d\n", ret);
@@ -1143,7 +1142,6 @@ static __devinit int alc5632_i2c_probe(struct i2c_client *client,
1143 if (ret1 != 0 || ret2 != 0) { 1142 if (ret1 != 0 || ret2 != 0) {
1144 dev_err(&client->dev, 1143 dev_err(&client->dev,
1145 "Failed to read chip ID: ret1=%d, ret2=%d\n", ret1, ret2); 1144 "Failed to read chip ID: ret1=%d, ret2=%d\n", ret1, ret2);
1146 regmap_exit(alc5632->regmap);
1147 return -EIO; 1145 return -EIO;
1148 } 1146 }
1149 1147
@@ -1152,14 +1150,12 @@ static __devinit int alc5632_i2c_probe(struct i2c_client *client,
1152 if ((vid1 != 0x10EC) || (vid2 != id->driver_data)) { 1150 if ((vid1 != 0x10EC) || (vid2 != id->driver_data)) {
1153 dev_err(&client->dev, 1151 dev_err(&client->dev,
1154 "Device is not a ALC5632: VID1=0x%x, VID2=0x%x\n", vid1, vid2); 1152 "Device is not a ALC5632: VID1=0x%x, VID2=0x%x\n", vid1, vid2);
1155 regmap_exit(alc5632->regmap);
1156 return -EINVAL; 1153 return -EINVAL;
1157 } 1154 }
1158 1155
1159 ret = alc5632_reset(alc5632->regmap); 1156 ret = alc5632_reset(alc5632->regmap);
1160 if (ret < 0) { 1157 if (ret < 0) {
1161 dev_err(&client->dev, "Failed to issue reset\n"); 1158 dev_err(&client->dev, "Failed to issue reset\n");
1162 regmap_exit(alc5632->regmap);
1163 return ret; 1159 return ret;
1164 } 1160 }
1165 1161
@@ -1177,7 +1173,6 @@ static __devinit int alc5632_i2c_probe(struct i2c_client *client,
1177 1173
1178 if (ret < 0) { 1174 if (ret < 0) {
1179 dev_err(&client->dev, "Failed to register codec: %d\n", ret); 1175 dev_err(&client->dev, "Failed to register codec: %d\n", ret);
1180 regmap_exit(alc5632->regmap);
1181 return ret; 1176 return ret;
1182 } 1177 }
1183 1178
@@ -1186,9 +1181,7 @@ static __devinit int alc5632_i2c_probe(struct i2c_client *client,
1186 1181
1187static __devexit int alc5632_i2c_remove(struct i2c_client *client) 1182static __devexit int alc5632_i2c_remove(struct i2c_client *client)
1188{ 1183{
1189 struct alc5632_priv *alc5632 = i2c_get_clientdata(client);
1190 snd_soc_unregister_codec(&client->dev); 1184 snd_soc_unregister_codec(&client->dev);
1191 regmap_exit(alc5632->regmap);
1192 return 0; 1185 return 0;
1193} 1186}
1194 1187
@@ -1209,25 +1202,7 @@ static struct i2c_driver alc5632_i2c_driver = {
1209 .id_table = alc5632_i2c_table, 1202 .id_table = alc5632_i2c_table,
1210}; 1203};
1211 1204
1212static int __init alc5632_modinit(void) 1205module_i2c_driver(alc5632_i2c_driver);
1213{
1214 int ret;
1215
1216 ret = i2c_add_driver(&alc5632_i2c_driver);
1217 if (ret != 0) {
1218 printk(KERN_ERR "%s: can't add i2c driver", __func__);
1219 return ret;
1220 }
1221
1222 return ret;
1223}
1224module_init(alc5632_modinit);
1225
1226static void __exit alc5632_modexit(void)
1227{
1228 i2c_del_driver(&alc5632_i2c_driver);
1229}
1230module_exit(alc5632_modexit);
1231 1206
1232MODULE_DESCRIPTION("ASoC ALC5632 driver"); 1207MODULE_DESCRIPTION("ASoC ALC5632 driver");
1233MODULE_AUTHOR("Leon Romanovsky <leon@leon.nu>"); 1208MODULE_AUTHOR("Leon Romanovsky <leon@leon.nu>");
diff --git a/sound/soc/codecs/cs4270.c b/sound/soc/codecs/cs4270.c
index 1d672f528662..047917f0b8ae 100644
--- a/sound/soc/codecs/cs4270.c
+++ b/sound/soc/codecs/cs4270.c
@@ -307,8 +307,7 @@ static int cs4270_hw_params(struct snd_pcm_substream *substream,
307 struct snd_pcm_hw_params *params, 307 struct snd_pcm_hw_params *params,
308 struct snd_soc_dai *dai) 308 struct snd_soc_dai *dai)
309{ 309{
310 struct snd_soc_pcm_runtime *rtd = substream->private_data; 310 struct snd_soc_codec *codec = dai->codec;
311 struct snd_soc_codec *codec = rtd->codec;
312 struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec); 311 struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec);
313 int ret; 312 int ret;
314 unsigned int i; 313 unsigned int i;
@@ -600,10 +599,12 @@ static int cs4270_soc_suspend(struct snd_soc_codec *codec)
600static int cs4270_soc_resume(struct snd_soc_codec *codec) 599static int cs4270_soc_resume(struct snd_soc_codec *codec)
601{ 600{
602 struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec); 601 struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec);
603 int reg; 602 int reg, ret;
604 603
605 regulator_bulk_enable(ARRAY_SIZE(cs4270->supplies), 604 ret = regulator_bulk_enable(ARRAY_SIZE(cs4270->supplies),
606 cs4270->supplies); 605 cs4270->supplies);
606 if (ret != 0)
607 return ret;
607 608
608 /* In case the device was put to hard reset during sleep, we need to 609 /* In case the device was put to hard reset during sleep, we need to
609 * wait 500ns here before any I2C communication. */ 610 * wait 500ns here before any I2C communication. */
diff --git a/sound/soc/codecs/cs4271.c b/sound/soc/codecs/cs4271.c
index bf7141280a74..9eb01d7d58a3 100644
--- a/sound/soc/codecs/cs4271.c
+++ b/sound/soc/codecs/cs4271.c
@@ -318,8 +318,7 @@ static int cs4271_hw_params(struct snd_pcm_substream *substream,
318 struct snd_pcm_hw_params *params, 318 struct snd_pcm_hw_params *params,
319 struct snd_soc_dai *dai) 319 struct snd_soc_dai *dai)
320{ 320{
321 struct snd_soc_pcm_runtime *rtd = substream->private_data; 321 struct snd_soc_codec *codec = dai->codec;
322 struct snd_soc_codec *codec = rtd->codec;
323 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); 322 struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec);
324 int i, ret; 323 int i, ret;
325 unsigned int ratio, val; 324 unsigned int ratio, val;
diff --git a/sound/soc/codecs/cs42l51.c b/sound/soc/codecs/cs42l51.c
index a8bf588e8740..091d0193f507 100644
--- a/sound/soc/codecs/cs42l51.c
+++ b/sound/soc/codecs/cs42l51.c
@@ -141,15 +141,15 @@ static const struct soc_enum cs42l51_chan_mix =
141static const struct snd_kcontrol_new cs42l51_snd_controls[] = { 141static const struct snd_kcontrol_new cs42l51_snd_controls[] = {
142 SOC_DOUBLE_R_SX_TLV("PCM Playback Volume", 142 SOC_DOUBLE_R_SX_TLV("PCM Playback Volume",
143 CS42L51_PCMA_VOL, CS42L51_PCMB_VOL, 143 CS42L51_PCMA_VOL, CS42L51_PCMB_VOL,
144 7, 0xffffff99, 0x18, adc_pcm_tlv), 144 6, 0x19, 0x7F, adc_pcm_tlv),
145 SOC_DOUBLE_R("PCM Playback Switch", 145 SOC_DOUBLE_R("PCM Playback Switch",
146 CS42L51_PCMA_VOL, CS42L51_PCMB_VOL, 7, 1, 1), 146 CS42L51_PCMA_VOL, CS42L51_PCMB_VOL, 7, 1, 1),
147 SOC_DOUBLE_R_SX_TLV("Analog Playback Volume", 147 SOC_DOUBLE_R_SX_TLV("Analog Playback Volume",
148 CS42L51_AOUTA_VOL, CS42L51_AOUTB_VOL, 148 CS42L51_AOUTA_VOL, CS42L51_AOUTB_VOL,
149 8, 0xffffff19, 0x18, aout_tlv), 149 0, 0x34, 0xE4, aout_tlv),
150 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume", 150 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
151 CS42L51_ADCA_VOL, CS42L51_ADCB_VOL, 151 CS42L51_ADCA_VOL, CS42L51_ADCB_VOL,
152 7, 0xffffff99, 0x18, adc_pcm_tlv), 152 6, 0x19, 0x7F, adc_pcm_tlv),
153 SOC_DOUBLE_R("ADC Mixer Switch", 153 SOC_DOUBLE_R("ADC Mixer Switch",
154 CS42L51_ADCA_VOL, CS42L51_ADCB_VOL, 7, 1, 1), 154 CS42L51_ADCA_VOL, CS42L51_ADCB_VOL, 7, 1, 1),
155 SOC_SINGLE("Playback Deemphasis Switch", CS42L51_DAC_CTL, 3, 1, 0), 155 SOC_SINGLE("Playback Deemphasis Switch", CS42L51_DAC_CTL, 3, 1, 0),
@@ -356,8 +356,7 @@ static int cs42l51_hw_params(struct snd_pcm_substream *substream,
356 struct snd_pcm_hw_params *params, 356 struct snd_pcm_hw_params *params,
357 struct snd_soc_dai *dai) 357 struct snd_soc_dai *dai)
358{ 358{
359 struct snd_soc_pcm_runtime *rtd = substream->private_data; 359 struct snd_soc_codec *codec = dai->codec;
360 struct snd_soc_codec *codec = rtd->codec;
361 struct cs42l51_private *cs42l51 = snd_soc_codec_get_drvdata(codec); 360 struct cs42l51_private *cs42l51 = snd_soc_codec_get_drvdata(codec);
362 int ret; 361 int ret;
363 unsigned int i; 362 unsigned int i;
diff --git a/sound/soc/codecs/cs42l52.c b/sound/soc/codecs/cs42l52.c
new file mode 100644
index 000000000000..a7109413aef1
--- /dev/null
+++ b/sound/soc/codecs/cs42l52.c
@@ -0,0 +1,1295 @@
1/*
2 * cs42l52.c -- CS42L52 ALSA SoC audio driver
3 *
4 * Copyright 2012 CirrusLogic, Inc.
5 *
6 * Author: Georgi Vlaev <joe@nucleusys.com>
7 * Author: Brian Austin <brian.austin@cirrus.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/version.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/pm.h>
22#include <linux/i2c.h>
23#include <linux/input.h>
24#include <linux/regmap.h>
25#include <linux/slab.h>
26#include <linux/workqueue.h>
27#include <linux/platform_device.h>
28#include <linux/slab.h>
29#include <sound/core.h>
30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/soc.h>
33#include <sound/soc-dapm.h>
34#include <sound/initval.h>
35#include <sound/tlv.h>
36#include <sound/cs42l52.h>
37#include "cs42l52.h"
38
39struct sp_config {
40 u8 spc, format, spfs;
41 u32 srate;
42};
43
44struct cs42l52_private {
45 struct regmap *regmap;
46 struct snd_soc_codec *codec;
47 struct device *dev;
48 struct sp_config config;
49 struct cs42l52_platform_data pdata;
50 u32 sysclk;
51 u8 mclksel;
52 u32 mclk;
53 u8 flags;
54#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
55 struct input_dev *beep;
56 struct work_struct beep_work;
57 int beep_rate;
58#endif
59};
60
61static const struct reg_default cs42l52_reg_defaults[] = {
62 { CS42L52_PWRCTL1, 0x9F }, /* r02 PWRCTL 1 */
63 { CS42L52_PWRCTL2, 0x07 }, /* r03 PWRCTL 2 */
64 { CS42L52_PWRCTL3, 0xFF }, /* r04 PWRCTL 3 */
65 { CS42L52_CLK_CTL, 0xA0 }, /* r05 Clocking Ctl */
66 { CS42L52_IFACE_CTL1, 0x00 }, /* r06 Interface Ctl 1 */
67 { CS42L52_ADC_PGA_A, 0x80 }, /* r08 Input A Select */
68 { CS42L52_ADC_PGA_B, 0x80 }, /* r09 Input B Select */
69 { CS42L52_ANALOG_HPF_CTL, 0xA5 }, /* r0A Analog HPF Ctl */
70 { CS42L52_ADC_HPF_FREQ, 0x00 }, /* r0B ADC HPF Corner Freq */
71 { CS42L52_ADC_MISC_CTL, 0x00 }, /* r0C Misc. ADC Ctl */
72 { CS42L52_PB_CTL1, 0x60 }, /* r0D Playback Ctl 1 */
73 { CS42L52_MISC_CTL, 0x02 }, /* r0E Misc. Ctl */
74 { CS42L52_PB_CTL2, 0x00 }, /* r0F Playback Ctl 2 */
75 { CS42L52_MICA_CTL, 0x00 }, /* r10 MICA Amp Ctl */
76 { CS42L52_MICB_CTL, 0x00 }, /* r11 MICB Amp Ctl */
77 { CS42L52_PGAA_CTL, 0x00 }, /* r12 PGAA Vol, Misc. */
78 { CS42L52_PGAB_CTL, 0x00 }, /* r13 PGAB Vol, Misc. */
79 { CS42L52_PASSTHRUA_VOL, 0x00 }, /* r14 Bypass A Vol */
80 { CS42L52_PASSTHRUB_VOL, 0x00 }, /* r15 Bypass B Vol */
81 { CS42L52_ADCA_VOL, 0x00 }, /* r16 ADCA Volume */
82 { CS42L52_ADCB_VOL, 0x00 }, /* r17 ADCB Volume */
83 { CS42L52_ADCA_MIXER_VOL, 0x80 }, /* r18 ADCA Mixer Volume */
84 { CS42L52_ADCB_MIXER_VOL, 0x80 }, /* r19 ADCB Mixer Volume */
85 { CS42L52_PCMA_MIXER_VOL, 0x00 }, /* r1A PCMA Mixer Volume */
86 { CS42L52_PCMB_MIXER_VOL, 0x00 }, /* r1B PCMB Mixer Volume */
87 { CS42L52_BEEP_FREQ, 0x00 }, /* r1C Beep Freq on Time */
88 { CS42L52_BEEP_VOL, 0x00 }, /* r1D Beep Volume off Time */
89 { CS42L52_BEEP_TONE_CTL, 0x00 }, /* r1E Beep Tone Cfg. */
90 { CS42L52_TONE_CTL, 0x00 }, /* r1F Tone Ctl */
91 { CS42L52_MASTERA_VOL, 0x88 }, /* r20 Master A Volume */
92 { CS42L52_MASTERB_VOL, 0x00 }, /* r21 Master B Volume */
93 { CS42L52_HPA_VOL, 0x00 }, /* r22 Headphone A Volume */
94 { CS42L52_HPB_VOL, 0x00 }, /* r23 Headphone B Volume */
95 { CS42L52_SPKA_VOL, 0x00 }, /* r24 Speaker A Volume */
96 { CS42L52_SPKB_VOL, 0x00 }, /* r25 Speaker B Volume */
97 { CS42L52_ADC_PCM_MIXER, 0x00 }, /* r26 Channel Mixer and Swap */
98 { CS42L52_LIMITER_CTL1, 0x00 }, /* r27 Limit Ctl 1 Thresholds */
99 { CS42L52_LIMITER_CTL2, 0x7F }, /* r28 Limit Ctl 2 Release Rate */
100 { CS42L52_LIMITER_AT_RATE, 0xC0 }, /* r29 Limiter Attack Rate */
101 { CS42L52_ALC_CTL, 0x00 }, /* r2A ALC Ctl 1 Attack Rate */
102 { CS42L52_ALC_RATE, 0x3F }, /* r2B ALC Release Rate */
103 { CS42L52_ALC_THRESHOLD, 0x3f }, /* r2C ALC Thresholds */
104 { CS42L52_NOISE_GATE_CTL, 0x00 }, /* r2D Noise Gate Ctl */
105 { CS42L52_CLK_STATUS, 0x00 }, /* r2E Overflow and Clock Status */
106 { CS42L52_BATT_COMPEN, 0x00 }, /* r2F battery Compensation */
107 { CS42L52_BATT_LEVEL, 0x00 }, /* r30 VP Battery Level */
108 { CS42L52_SPK_STATUS, 0x00 }, /* r31 Speaker Status */
109 { CS42L52_TEM_CTL, 0x3B }, /* r32 Temp Ctl */
110 { CS42L52_THE_FOLDBACK, 0x00 }, /* r33 Foldback */
111};
112
113static bool cs42l52_readable_register(struct device *dev, unsigned int reg)
114{
115 switch (reg) {
116 case CS42L52_CHIP:
117 case CS42L52_PWRCTL1:
118 case CS42L52_PWRCTL2:
119 case CS42L52_PWRCTL3:
120 case CS42L52_CLK_CTL:
121 case CS42L52_IFACE_CTL1:
122 case CS42L52_IFACE_CTL2:
123 case CS42L52_ADC_PGA_A:
124 case CS42L52_ADC_PGA_B:
125 case CS42L52_ANALOG_HPF_CTL:
126 case CS42L52_ADC_HPF_FREQ:
127 case CS42L52_ADC_MISC_CTL:
128 case CS42L52_PB_CTL1:
129 case CS42L52_MISC_CTL:
130 case CS42L52_PB_CTL2:
131 case CS42L52_MICA_CTL:
132 case CS42L52_MICB_CTL:
133 case CS42L52_PGAA_CTL:
134 case CS42L52_PGAB_CTL:
135 case CS42L52_PASSTHRUA_VOL:
136 case CS42L52_PASSTHRUB_VOL:
137 case CS42L52_ADCA_VOL:
138 case CS42L52_ADCB_VOL:
139 case CS42L52_ADCA_MIXER_VOL:
140 case CS42L52_ADCB_MIXER_VOL:
141 case CS42L52_PCMA_MIXER_VOL:
142 case CS42L52_PCMB_MIXER_VOL:
143 case CS42L52_BEEP_FREQ:
144 case CS42L52_BEEP_VOL:
145 case CS42L52_BEEP_TONE_CTL:
146 case CS42L52_TONE_CTL:
147 case CS42L52_MASTERA_VOL:
148 case CS42L52_MASTERB_VOL:
149 case CS42L52_HPA_VOL:
150 case CS42L52_HPB_VOL:
151 case CS42L52_SPKA_VOL:
152 case CS42L52_SPKB_VOL:
153 case CS42L52_ADC_PCM_MIXER:
154 case CS42L52_LIMITER_CTL1:
155 case CS42L52_LIMITER_CTL2:
156 case CS42L52_LIMITER_AT_RATE:
157 case CS42L52_ALC_CTL:
158 case CS42L52_ALC_RATE:
159 case CS42L52_ALC_THRESHOLD:
160 case CS42L52_NOISE_GATE_CTL:
161 case CS42L52_CLK_STATUS:
162 case CS42L52_BATT_COMPEN:
163 case CS42L52_BATT_LEVEL:
164 case CS42L52_SPK_STATUS:
165 case CS42L52_TEM_CTL:
166 case CS42L52_THE_FOLDBACK:
167 case CS42L52_CHARGE_PUMP:
168 return true;
169 default:
170 return false;
171 }
172}
173
174static bool cs42l52_volatile_register(struct device *dev, unsigned int reg)
175{
176 switch (reg) {
177 case CS42L52_IFACE_CTL2:
178 case CS42L52_CLK_STATUS:
179 case CS42L52_BATT_LEVEL:
180 case CS42L52_SPK_STATUS:
181 case CS42L52_CHARGE_PUMP:
182 return 1;
183 default:
184 return 0;
185 }
186}
187
188static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
189
190static DECLARE_TLV_DB_SCALE(hpd_tlv, -9600, 50, 1);
191
192static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
193
194static DECLARE_TLV_DB_SCALE(mic_tlv, 1600, 100, 0);
195
196static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
197
198static const unsigned int limiter_tlv[] = {
199 TLV_DB_RANGE_HEAD(2),
200 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
201 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0),
202};
203
204static const char * const cs42l52_adca_text[] = {
205 "Input1A", "Input2A", "Input3A", "Input4A", "PGA Input Left"};
206
207static const char * const cs42l52_adcb_text[] = {
208 "Input1B", "Input2B", "Input3B", "Input4B", "PGA Input Right"};
209
210static const struct soc_enum adca_enum =
211 SOC_ENUM_SINGLE(CS42L52_ADC_PGA_A, 5,
212 ARRAY_SIZE(cs42l52_adca_text), cs42l52_adca_text);
213
214static const struct soc_enum adcb_enum =
215 SOC_ENUM_SINGLE(CS42L52_ADC_PGA_B, 5,
216 ARRAY_SIZE(cs42l52_adcb_text), cs42l52_adcb_text);
217
218static const struct snd_kcontrol_new adca_mux =
219 SOC_DAPM_ENUM("Left ADC Input Capture Mux", adca_enum);
220
221static const struct snd_kcontrol_new adcb_mux =
222 SOC_DAPM_ENUM("Right ADC Input Capture Mux", adcb_enum);
223
224static const char * const mic_bias_level_text[] = {
225 "0.5 +VA", "0.6 +VA", "0.7 +VA",
226 "0.8 +VA", "0.83 +VA", "0.91 +VA"
227};
228
229static const struct soc_enum mic_bias_level_enum =
230 SOC_ENUM_SINGLE(CS42L52_IFACE_CTL1, 0,
231 ARRAY_SIZE(mic_bias_level_text), mic_bias_level_text);
232
233static const char * const cs42l52_mic_text[] = { "Single", "Differential" };
234
235static const struct soc_enum mica_enum =
236 SOC_ENUM_SINGLE(CS42L52_MICA_CTL, 5,
237 ARRAY_SIZE(cs42l52_mic_text), cs42l52_mic_text);
238
239static const struct soc_enum micb_enum =
240 SOC_ENUM_SINGLE(CS42L52_MICB_CTL, 5,
241 ARRAY_SIZE(cs42l52_mic_text), cs42l52_mic_text);
242
243static const struct snd_kcontrol_new mica_mux =
244 SOC_DAPM_ENUM("Left Mic Input Capture Mux", mica_enum);
245
246static const struct snd_kcontrol_new micb_mux =
247 SOC_DAPM_ENUM("Right Mic Input Capture Mux", micb_enum);
248
249static const char * const digital_output_mux_text[] = {"ADC", "DSP"};
250
251static const struct soc_enum digital_output_mux_enum =
252 SOC_ENUM_SINGLE(CS42L52_ADC_MISC_CTL, 6,
253 ARRAY_SIZE(digital_output_mux_text),
254 digital_output_mux_text);
255
256static const struct snd_kcontrol_new digital_output_mux =
257 SOC_DAPM_ENUM("Digital Output Mux", digital_output_mux_enum);
258
259static const char * const hp_gain_num_text[] = {
260 "0.3959", "0.4571", "0.5111", "0.6047",
261 "0.7099", "0.8399", "1.000", "1.1430"
262};
263
264static const struct soc_enum hp_gain_enum =
265 SOC_ENUM_SINGLE(CS42L52_PB_CTL1, 4,
266 ARRAY_SIZE(hp_gain_num_text), hp_gain_num_text);
267
268static const char * const beep_pitch_text[] = {
269 "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
270 "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
271};
272
273static const struct soc_enum beep_pitch_enum =
274 SOC_ENUM_SINGLE(CS42L52_BEEP_FREQ, 4,
275 ARRAY_SIZE(beep_pitch_text), beep_pitch_text);
276
277static const char * const beep_ontime_text[] = {
278 "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
279 "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
280 "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
281};
282
283static const struct soc_enum beep_ontime_enum =
284 SOC_ENUM_SINGLE(CS42L52_BEEP_FREQ, 0,
285 ARRAY_SIZE(beep_ontime_text), beep_ontime_text);
286
287static const char * const beep_offtime_text[] = {
288 "1.23 s", "2.58 s", "3.90 s", "5.20 s",
289 "6.60 s", "8.05 s", "9.35 s", "10.80 s"
290};
291
292static const struct soc_enum beep_offtime_enum =
293 SOC_ENUM_SINGLE(CS42L52_BEEP_VOL, 5,
294 ARRAY_SIZE(beep_offtime_text), beep_offtime_text);
295
296static const char * const beep_config_text[] = {
297 "Off", "Single", "Multiple", "Continuous"
298};
299
300static const struct soc_enum beep_config_enum =
301 SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 6,
302 ARRAY_SIZE(beep_config_text), beep_config_text);
303
304static const char * const beep_bass_text[] = {
305 "50 Hz", "100 Hz", "200 Hz", "250 Hz"
306};
307
308static const struct soc_enum beep_bass_enum =
309 SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 1,
310 ARRAY_SIZE(beep_bass_text), beep_bass_text);
311
312static const char * const beep_treble_text[] = {
313 "5 kHz", "7 kHz", "10 kHz", " 15 kHz"
314};
315
316static const struct soc_enum beep_treble_enum =
317 SOC_ENUM_SINGLE(CS42L52_BEEP_TONE_CTL, 3,
318 ARRAY_SIZE(beep_treble_text), beep_treble_text);
319
320static const char * const ng_threshold_text[] = {
321 "-34dB", "-37dB", "-40dB", "-43dB",
322 "-46dB", "-52dB", "-58dB", "-64dB"
323};
324
325static const struct soc_enum ng_threshold_enum =
326 SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 2,
327 ARRAY_SIZE(ng_threshold_text), ng_threshold_text);
328
329static const char * const cs42l52_ng_delay_text[] = {
330 "50ms", "100ms", "150ms", "200ms"};
331
332static const struct soc_enum ng_delay_enum =
333 SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 0,
334 ARRAY_SIZE(cs42l52_ng_delay_text), cs42l52_ng_delay_text);
335
336static const char * const cs42l52_ng_type_text[] = {
337 "Apply Specific", "Apply All"
338};
339
340static const struct soc_enum ng_type_enum =
341 SOC_ENUM_SINGLE(CS42L52_NOISE_GATE_CTL, 6,
342 ARRAY_SIZE(cs42l52_ng_type_text), cs42l52_ng_type_text);
343
344static const char * const left_swap_text[] = {
345 "Left", "LR 2", "Right"};
346
347static const char * const right_swap_text[] = {
348 "Right", "LR 2", "Left"};
349
350static const unsigned int swap_values[] = { 0, 1, 3 };
351
352static const struct soc_enum adca_swap_enum =
353 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 2, 1,
354 ARRAY_SIZE(left_swap_text),
355 left_swap_text,
356 swap_values);
357
358static const struct snd_kcontrol_new adca_mixer =
359 SOC_DAPM_ENUM("Route", adca_swap_enum);
360
361static const struct soc_enum pcma_swap_enum =
362 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 6, 1,
363 ARRAY_SIZE(left_swap_text),
364 left_swap_text,
365 swap_values);
366
367static const struct snd_kcontrol_new pcma_mixer =
368 SOC_DAPM_ENUM("Route", pcma_swap_enum);
369
370static const struct soc_enum adcb_swap_enum =
371 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 0, 1,
372 ARRAY_SIZE(right_swap_text),
373 right_swap_text,
374 swap_values);
375
376static const struct snd_kcontrol_new adcb_mixer =
377 SOC_DAPM_ENUM("Route", adcb_swap_enum);
378
379static const struct soc_enum pcmb_swap_enum =
380 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 4, 1,
381 ARRAY_SIZE(right_swap_text),
382 right_swap_text,
383 swap_values);
384
385static const struct snd_kcontrol_new pcmb_mixer =
386 SOC_DAPM_ENUM("Route", pcmb_swap_enum);
387
388
389static const struct snd_kcontrol_new passthrul_ctl =
390 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 6, 1, 0);
391
392static const struct snd_kcontrol_new passthrur_ctl =
393 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 7, 1, 0);
394
395static const struct snd_kcontrol_new spkl_ctl =
396 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 0, 1, 1);
397
398static const struct snd_kcontrol_new spkr_ctl =
399 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 2, 1, 1);
400
401static const struct snd_kcontrol_new hpl_ctl =
402 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 4, 1, 1);
403
404static const struct snd_kcontrol_new hpr_ctl =
405 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 6, 1, 1);
406
407static const struct snd_kcontrol_new cs42l52_snd_controls[] = {
408
409 SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L52_MASTERA_VOL,
410 CS42L52_MASTERB_VOL, 0, 0x34, 0xE4, hl_tlv),
411
412 SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L52_HPA_VOL,
413 CS42L52_HPB_VOL, 0, 0x34, 0xCC, hpd_tlv),
414
415 SOC_ENUM("Headphone Analog Gain", hp_gain_enum),
416
417 SOC_DOUBLE_R_SX_TLV("Speaker Volume", CS42L52_SPKA_VOL,
418 CS42L52_SPKB_VOL, 7, 0x1, 0xff, hl_tlv),
419
420 SOC_DOUBLE_R_SX_TLV("Bypass Volume", CS42L52_PASSTHRUA_VOL,
421 CS42L52_PASSTHRUB_VOL, 6, 0x18, 0x90, pga_tlv),
422
423 SOC_DOUBLE("Bypass Mute", CS42L52_MISC_CTL, 4, 5, 1, 0),
424
425 SOC_DOUBLE_R_TLV("MIC Gain Volume", CS42L52_MICA_CTL,
426 CS42L52_MICB_CTL, 0, 0x10, 0, mic_tlv),
427
428 SOC_ENUM("MIC Bias Level", mic_bias_level_enum),
429
430 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L52_ADCA_VOL,
431 CS42L52_ADCB_VOL, 7, 0x80, 0xA0, ipd_tlv),
432 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
433 CS42L52_ADCA_MIXER_VOL, CS42L52_ADCB_MIXER_VOL,
434 6, 0x7f, 0x19, ipd_tlv),
435
436 SOC_DOUBLE("ADC Switch", CS42L52_ADC_MISC_CTL, 0, 1, 1, 0),
437
438 SOC_DOUBLE_R("ADC Mixer Switch", CS42L52_ADCA_MIXER_VOL,
439 CS42L52_ADCB_MIXER_VOL, 7, 1, 1),
440
441 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L52_PGAA_CTL,
442 CS42L52_PGAB_CTL, 0, 0x28, 0x30, pga_tlv),
443
444 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume",
445 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL,
446 6, 0x7f, 0x19, hl_tlv),
447 SOC_DOUBLE_R("PCM Mixer Switch",
448 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 7, 1, 1),
449
450 SOC_ENUM("Beep Config", beep_config_enum),
451 SOC_ENUM("Beep Pitch", beep_pitch_enum),
452 SOC_ENUM("Beep on Time", beep_ontime_enum),
453 SOC_ENUM("Beep off Time", beep_offtime_enum),
454 SOC_SINGLE_TLV("Beep Volume", CS42L52_BEEP_VOL, 0, 0x1f, 0x07, hl_tlv),
455 SOC_SINGLE("Beep Mixer Switch", CS42L52_BEEP_TONE_CTL, 5, 1, 1),
456 SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
457 SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
458
459 SOC_SINGLE("Tone Control Switch", CS42L52_BEEP_TONE_CTL, 0, 1, 1),
460 SOC_SINGLE_TLV("Treble Gain Volume",
461 CS42L52_TONE_CTL, 4, 15, 1, hl_tlv),
462 SOC_SINGLE_TLV("Bass Gain Volume",
463 CS42L52_TONE_CTL, 0, 15, 1, hl_tlv),
464
465 /* Limiter */
466 SOC_SINGLE_TLV("Limiter Max Threshold Volume",
467 CS42L52_LIMITER_CTL1, 5, 7, 0, limiter_tlv),
468 SOC_SINGLE_TLV("Limiter Cushion Threshold Volume",
469 CS42L52_LIMITER_CTL1, 2, 7, 0, limiter_tlv),
470 SOC_SINGLE_TLV("Limiter Release Rate Volume",
471 CS42L52_LIMITER_CTL2, 0, 63, 0, limiter_tlv),
472 SOC_SINGLE_TLV("Limiter Attack Rate Volume",
473 CS42L52_LIMITER_AT_RATE, 0, 63, 0, limiter_tlv),
474
475 SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1, 1, 1, 0),
476 SOC_SINGLE("Limiter ZC Switch", CS42L52_LIMITER_CTL1, 0, 1, 0),
477 SOC_SINGLE("Limiter Switch", CS42L52_LIMITER_CTL2, 7, 1, 0),
478
479 /* ALC */
480 SOC_SINGLE_TLV("ALC Attack Rate Volume", CS42L52_ALC_CTL,
481 0, 63, 0, limiter_tlv),
482 SOC_SINGLE_TLV("ALC Release Rate Volume", CS42L52_ALC_RATE,
483 0, 63, 0, limiter_tlv),
484 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L52_ALC_THRESHOLD,
485 5, 7, 0, limiter_tlv),
486 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L52_ALC_THRESHOLD,
487 2, 7, 0, limiter_tlv),
488
489 SOC_DOUBLE_R("ALC SR Capture Switch", CS42L52_PGAA_CTL,
490 CS42L52_PGAB_CTL, 7, 1, 1),
491 SOC_DOUBLE_R("ALC ZC Capture Switch", CS42L52_PGAA_CTL,
492 CS42L52_PGAB_CTL, 6, 1, 1),
493 SOC_DOUBLE("ALC Capture Switch", CS42L52_ALC_CTL, 6, 7, 1, 0),
494
495 /* Noise gate */
496 SOC_ENUM("NG Type Switch", ng_type_enum),
497 SOC_SINGLE("NG Enable Switch", CS42L52_NOISE_GATE_CTL, 6, 1, 0),
498 SOC_SINGLE("NG Boost Switch", CS42L52_NOISE_GATE_CTL, 5, 1, 1),
499 SOC_ENUM("NG Threshold", ng_threshold_enum),
500 SOC_ENUM("NG Delay", ng_delay_enum),
501
502 SOC_DOUBLE("HPF Switch", CS42L52_ANALOG_HPF_CTL, 5, 7, 1, 0),
503
504 SOC_DOUBLE("Analog SR Switch", CS42L52_ANALOG_HPF_CTL, 1, 3, 1, 1),
505 SOC_DOUBLE("Analog ZC Switch", CS42L52_ANALOG_HPF_CTL, 0, 2, 1, 1),
506 SOC_SINGLE("Digital SR Switch", CS42L52_MISC_CTL, 1, 1, 0),
507 SOC_SINGLE("Digital ZC Switch", CS42L52_MISC_CTL, 0, 1, 0),
508 SOC_SINGLE("Deemphasis Switch", CS42L52_MISC_CTL, 2, 1, 0),
509
510 SOC_SINGLE("Batt Compensation Switch", CS42L52_BATT_COMPEN, 7, 1, 0),
511 SOC_SINGLE("Batt VP Monitor Switch", CS42L52_BATT_COMPEN, 6, 1, 0),
512 SOC_SINGLE("Batt VP ref", CS42L52_BATT_COMPEN, 0, 0x0f, 0),
513
514 SOC_SINGLE("PGA AIN1L Switch", CS42L52_ADC_PGA_A, 0, 1, 0),
515 SOC_SINGLE("PGA AIN1R Switch", CS42L52_ADC_PGA_B, 0, 1, 0),
516 SOC_SINGLE("PGA AIN2L Switch", CS42L52_ADC_PGA_A, 1, 1, 0),
517 SOC_SINGLE("PGA AIN2R Switch", CS42L52_ADC_PGA_B, 1, 1, 0),
518
519 SOC_SINGLE("PGA AIN3L Switch", CS42L52_ADC_PGA_A, 2, 1, 0),
520 SOC_SINGLE("PGA AIN3R Switch", CS42L52_ADC_PGA_B, 2, 1, 0),
521
522 SOC_SINGLE("PGA AIN4L Switch", CS42L52_ADC_PGA_A, 3, 1, 0),
523 SOC_SINGLE("PGA AIN4R Switch", CS42L52_ADC_PGA_B, 3, 1, 0),
524
525 SOC_SINGLE("PGA MICA Switch", CS42L52_ADC_PGA_A, 4, 1, 0),
526 SOC_SINGLE("PGA MICB Switch", CS42L52_ADC_PGA_B, 4, 1, 0),
527
528};
529
530static const struct snd_soc_dapm_widget cs42l52_dapm_widgets[] = {
531
532 SND_SOC_DAPM_INPUT("AIN1L"),
533 SND_SOC_DAPM_INPUT("AIN1R"),
534 SND_SOC_DAPM_INPUT("AIN2L"),
535 SND_SOC_DAPM_INPUT("AIN2R"),
536 SND_SOC_DAPM_INPUT("AIN3L"),
537 SND_SOC_DAPM_INPUT("AIN3R"),
538 SND_SOC_DAPM_INPUT("AIN4L"),
539 SND_SOC_DAPM_INPUT("AIN4R"),
540 SND_SOC_DAPM_INPUT("MICA"),
541 SND_SOC_DAPM_INPUT("MICB"),
542 SND_SOC_DAPM_SIGGEN("Beep"),
543
544 SND_SOC_DAPM_AIF_OUT("AIFOUTL", NULL, 0,
545 SND_SOC_NOPM, 0, 0),
546 SND_SOC_DAPM_AIF_OUT("AIFOUTR", NULL, 0,
547 SND_SOC_NOPM, 0, 0),
548
549 SND_SOC_DAPM_MUX("MICA Mux", SND_SOC_NOPM, 0, 0, &mica_mux),
550 SND_SOC_DAPM_MUX("MICB Mux", SND_SOC_NOPM, 0, 0, &micb_mux),
551
552 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L52_PWRCTL1, 1, 1),
553 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L52_PWRCTL1, 2, 1),
554 SND_SOC_DAPM_PGA("PGA Left", CS42L52_PWRCTL1, 3, 1, NULL, 0),
555 SND_SOC_DAPM_PGA("PGA Right", CS42L52_PWRCTL1, 4, 1, NULL, 0),
556
557 SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM, 0, 0, &adca_mux),
558 SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM, 0, 0, &adcb_mux),
559
560 SND_SOC_DAPM_MUX("ADC Left Swap", SND_SOC_NOPM,
561 0, 0, &adca_mixer),
562 SND_SOC_DAPM_MUX("ADC Right Swap", SND_SOC_NOPM,
563 0, 0, &adcb_mixer),
564
565 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM,
566 0, 0, &digital_output_mux),
567
568 SND_SOC_DAPM_PGA("PGA MICA", CS42L52_PWRCTL2, 1, 1, NULL, 0),
569 SND_SOC_DAPM_PGA("PGA MICB", CS42L52_PWRCTL2, 2, 1, NULL, 0),
570
571 SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L52_PWRCTL2, 0, 1, NULL, 0),
572 SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L52_PWRCTL1, 7, 1, NULL, 0),
573
574 SND_SOC_DAPM_AIF_IN("AIFINL", NULL, 0,
575 SND_SOC_NOPM, 0, 0),
576 SND_SOC_DAPM_AIF_IN("AIFINR", NULL, 0,
577 SND_SOC_NOPM, 0, 0),
578
579 SND_SOC_DAPM_DAC("DAC Left", NULL, SND_SOC_NOPM, 0, 0),
580 SND_SOC_DAPM_DAC("DAC Right", NULL, SND_SOC_NOPM, 0, 0),
581
582 SND_SOC_DAPM_SWITCH("Bypass Left", CS42L52_MISC_CTL,
583 6, 0, &passthrul_ctl),
584 SND_SOC_DAPM_SWITCH("Bypass Right", CS42L52_MISC_CTL,
585 7, 0, &passthrur_ctl),
586
587 SND_SOC_DAPM_MUX("PCM Left Swap", SND_SOC_NOPM,
588 0, 0, &pcma_mixer),
589 SND_SOC_DAPM_MUX("PCM Right Swap", SND_SOC_NOPM,
590 0, 0, &pcmb_mixer),
591
592 SND_SOC_DAPM_SWITCH("HP Left Amp", SND_SOC_NOPM, 0, 0, &hpl_ctl),
593 SND_SOC_DAPM_SWITCH("HP Right Amp", SND_SOC_NOPM, 0, 0, &hpr_ctl),
594
595 SND_SOC_DAPM_SWITCH("SPK Left Amp", SND_SOC_NOPM, 0, 0, &spkl_ctl),
596 SND_SOC_DAPM_SWITCH("SPK Right Amp", SND_SOC_NOPM, 0, 0, &spkr_ctl),
597
598 SND_SOC_DAPM_OUTPUT("HPOUTA"),
599 SND_SOC_DAPM_OUTPUT("HPOUTB"),
600 SND_SOC_DAPM_OUTPUT("SPKOUTA"),
601 SND_SOC_DAPM_OUTPUT("SPKOUTB"),
602
603};
604
605static const struct snd_soc_dapm_route cs42l52_audio_map[] = {
606
607 {"Capture", NULL, "AIFOUTL"},
608 {"Capture", NULL, "AIFOUTL"},
609
610 {"AIFOUTL", NULL, "Output Mux"},
611 {"AIFOUTR", NULL, "Output Mux"},
612
613 {"Output Mux", "ADC", "ADC Left"},
614 {"Output Mux", "ADC", "ADC Right"},
615
616 {"ADC Left", NULL, "Charge Pump"},
617 {"ADC Right", NULL, "Charge Pump"},
618
619 {"Charge Pump", NULL, "ADC Left Mux"},
620 {"Charge Pump", NULL, "ADC Right Mux"},
621
622 {"ADC Left Mux", "Input1A", "AIN1L"},
623 {"ADC Right Mux", "Input1B", "AIN1R"},
624 {"ADC Left Mux", "Input2A", "AIN2L"},
625 {"ADC Right Mux", "Input2B", "AIN2R"},
626 {"ADC Left Mux", "Input3A", "AIN3L"},
627 {"ADC Right Mux", "Input3B", "AIN3R"},
628 {"ADC Left Mux", "Input4A", "AIN4L"},
629 {"ADC Right Mux", "Input4B", "AIN4R"},
630 {"ADC Left Mux", "PGA Input Left", "PGA Left"},
631 {"ADC Right Mux", "PGA Input Right" , "PGA Right"},
632
633 {"PGA Left", "Switch", "AIN1L"},
634 {"PGA Right", "Switch", "AIN1R"},
635 {"PGA Left", "Switch", "AIN2L"},
636 {"PGA Right", "Switch", "AIN2R"},
637 {"PGA Left", "Switch", "AIN3L"},
638 {"PGA Right", "Switch", "AIN3R"},
639 {"PGA Left", "Switch", "AIN4L"},
640 {"PGA Right", "Switch", "AIN4R"},
641
642 {"PGA Left", "Switch", "PGA MICA"},
643 {"PGA MICA", NULL, "MICA"},
644
645 {"PGA Right", "Switch", "PGA MICB"},
646 {"PGA MICB", NULL, "MICB"},
647
648 {"HPOUTA", NULL, "HP Left Amp"},
649 {"HPOUTB", NULL, "HP Right Amp"},
650 {"HP Left Amp", NULL, "Bypass Left"},
651 {"HP Right Amp", NULL, "Bypass Right"},
652 {"Bypass Left", "Switch", "PGA Left"},
653 {"Bypass Right", "Switch", "PGA Right"},
654 {"HP Left Amp", "Switch", "DAC Left"},
655 {"HP Right Amp", "Switch", "DAC Right"},
656
657 {"SPKOUTA", NULL, "SPK Left Amp"},
658 {"SPKOUTB", NULL, "SPK Right Amp"},
659
660 {"SPK Left Amp", NULL, "Beep"},
661 {"SPK Right Amp", NULL, "Beep"},
662 {"SPK Left Amp", "Switch", "Playback"},
663 {"SPK Right Amp", "Switch", "Playback"},
664
665 {"DAC Left", NULL, "Beep"},
666 {"DAC Right", NULL, "Beep"},
667 {"DAC Left", NULL, "Playback"},
668 {"DAC Right", NULL, "Playback"},
669
670 {"Output Mux", "DSP", "Playback"},
671 {"Output Mux", "DSP", "Playback"},
672
673 {"AIFINL", NULL, "Playback"},
674 {"AIFINR", NULL, "Playback"},
675
676};
677
678struct cs42l52_clk_para {
679 u32 mclk;
680 u32 rate;
681 u8 speed;
682 u8 group;
683 u8 videoclk;
684 u8 ratio;
685 u8 mclkdiv2;
686};
687
688static const struct cs42l52_clk_para clk_map_table[] = {
689 /*8k*/
690 {12288000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
691 {18432000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
692 {12000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
693 {24000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
694 {27000000, 8000, CLK_QS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
695
696 /*11.025k*/
697 {11289600, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
698 {16934400, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
699
700 /*16k*/
701 {12288000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
702 {18432000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
703 {12000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
704 {24000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
705 {27000000, 16000, CLK_HS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 1},
706
707 /*22.05k*/
708 {11289600, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
709 {16934400, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
710
711 /* 32k */
712 {12288000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
713 {18432000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
714 {12000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
715 {24000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
716 {27000000, 32000, CLK_SS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
717
718 /* 44.1k */
719 {11289600, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
720 {16934400, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
721
722 /* 48k */
723 {12288000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
724 {18432000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
725 {12000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
726 {24000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
727 {27000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_27M_MCLK, CLK_R_125, 1},
728
729 /* 88.2k */
730 {11289600, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
731 {16934400, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
732
733 /* 96k */
734 {12288000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
735 {18432000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
736 {12000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
737 {24000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
738};
739
740static int cs42l52_get_clk(int mclk, int rate)
741{
742 int i, ret = 0;
743 u_int mclk1, mclk2 = 0;
744
745 for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
746 if (clk_map_table[i].rate == rate) {
747 mclk1 = clk_map_table[i].mclk;
748 if (abs(mclk - mclk1) < abs(mclk - mclk2)) {
749 mclk2 = mclk1;
750 ret = i;
751 }
752 }
753 }
754 if (ret > ARRAY_SIZE(clk_map_table))
755 return -EINVAL;
756 return ret;
757}
758
759static int cs42l52_set_sysclk(struct snd_soc_dai *codec_dai,
760 int clk_id, unsigned int freq, int dir)
761{
762 struct snd_soc_codec *codec = codec_dai->codec;
763 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
764
765 if ((freq >= CS42L52_MIN_CLK) && (freq <= CS42L52_MAX_CLK)) {
766 cs42l52->sysclk = freq;
767 } else {
768 dev_err(codec->dev, "Invalid freq paramter\n");
769 return -EINVAL;
770 }
771 return 0;
772}
773
774static int cs42l52_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
775{
776 struct snd_soc_codec *codec = codec_dai->codec;
777 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
778 int ret = 0;
779 u8 iface = 0;
780
781 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
782 case SND_SOC_DAIFMT_CBM_CFM:
783 iface = CS42L52_IFACE_CTL1_MASTER;
784 break;
785 case SND_SOC_DAIFMT_CBS_CFS:
786 iface = CS42L52_IFACE_CTL1_SLAVE;
787 break;
788 default:
789 return -EINVAL;
790 }
791
792 /* interface format */
793 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
794 case SND_SOC_DAIFMT_I2S:
795 iface |= CS42L52_IFACE_CTL1_ADC_FMT_I2S |
796 CS42L52_IFACE_CTL1_DAC_FMT_I2S;
797 break;
798 case SND_SOC_DAIFMT_RIGHT_J:
799 iface |= CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J;
800 break;
801 case SND_SOC_DAIFMT_LEFT_J:
802 iface |= CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J |
803 CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J;
804 break;
805 case SND_SOC_DAIFMT_DSP_A:
806 iface |= CS42L52_IFACE_CTL1_DSP_MODE_EN;
807 break;
808 case SND_SOC_DAIFMT_DSP_B:
809 break;
810 default:
811 return -EINVAL;
812 }
813
814 /* clock inversion */
815 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
816 case SND_SOC_DAIFMT_NB_NF:
817 break;
818 case SND_SOC_DAIFMT_IB_IF:
819 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
820 break;
821 case SND_SOC_DAIFMT_IB_NF:
822 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
823 break;
824 case SND_SOC_DAIFMT_NB_IF:
825 break;
826 default:
827 ret = -EINVAL;
828 }
829 cs42l52->config.format = iface;
830 snd_soc_write(codec, CS42L52_IFACE_CTL1, cs42l52->config.format);
831
832 return 0;
833}
834
835static int cs42l52_digital_mute(struct snd_soc_dai *dai, int mute)
836{
837 struct snd_soc_codec *codec = dai->codec;
838
839 if (mute)
840 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
841 CS42L52_PB_CTL1_MUTE_MASK,
842 CS42L52_PB_CTL1_MUTE);
843 else
844 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
845 CS42L52_PB_CTL1_MUTE_MASK,
846 CS42L52_PB_CTL1_UNMUTE);
847
848 return 0;
849}
850
851static int cs42l52_pcm_hw_params(struct snd_pcm_substream *substream,
852 struct snd_pcm_hw_params *params,
853 struct snd_soc_dai *dai)
854{
855 struct snd_soc_codec *codec = dai->codec;
856 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
857 u32 clk = 0;
858 int index;
859
860 index = cs42l52_get_clk(cs42l52->sysclk, params_rate(params));
861 if (index >= 0) {
862 cs42l52->sysclk = clk_map_table[index].mclk;
863
864 clk |= (clk_map_table[index].speed << CLK_SPEED_SHIFT) |
865 (clk_map_table[index].group << CLK_32K_SR_SHIFT) |
866 (clk_map_table[index].videoclk << CLK_27M_MCLK_SHIFT) |
867 (clk_map_table[index].ratio << CLK_RATIO_SHIFT) |
868 clk_map_table[index].mclkdiv2;
869
870 snd_soc_write(codec, CS42L52_CLK_CTL, clk);
871 } else {
872 dev_err(codec->dev, "can't get correct mclk\n");
873 return -EINVAL;
874 }
875
876 return 0;
877}
878
879static int cs42l52_set_bias_level(struct snd_soc_codec *codec,
880 enum snd_soc_bias_level level)
881{
882 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
883
884 switch (level) {
885 case SND_SOC_BIAS_ON:
886 break;
887 case SND_SOC_BIAS_PREPARE:
888 snd_soc_update_bits(codec, CS42L52_PWRCTL1,
889 CS42L52_PWRCTL1_PDN_CODEC, 0);
890 break;
891 case SND_SOC_BIAS_STANDBY:
892 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
893 regcache_cache_only(cs42l52->regmap, false);
894 regcache_sync(cs42l52->regmap);
895 }
896 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
897 break;
898 case SND_SOC_BIAS_OFF:
899 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
900 regcache_cache_only(cs42l52->regmap, true);
901 break;
902 }
903 codec->dapm.bias_level = level;
904
905 return 0;
906}
907
908#define CS42L52_RATES (SNDRV_PCM_RATE_8000_96000)
909
910#define CS42L52_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
911 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
912 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
913 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE)
914
915static struct snd_soc_dai_ops cs42l52_ops = {
916 .hw_params = cs42l52_pcm_hw_params,
917 .digital_mute = cs42l52_digital_mute,
918 .set_fmt = cs42l52_set_fmt,
919 .set_sysclk = cs42l52_set_sysclk,
920};
921
922static struct snd_soc_dai_driver cs42l52_dai = {
923 .name = "cs42l52",
924 .playback = {
925 .stream_name = "Playback",
926 .channels_min = 1,
927 .channels_max = 2,
928 .rates = CS42L52_RATES,
929 .formats = CS42L52_FORMATS,
930 },
931 .capture = {
932 .stream_name = "Capture",
933 .channels_min = 1,
934 .channels_max = 2,
935 .rates = CS42L52_RATES,
936 .formats = CS42L52_FORMATS,
937 },
938 .ops = &cs42l52_ops,
939};
940
941static int cs42l52_suspend(struct snd_soc_codec *codec)
942{
943 cs42l52_set_bias_level(codec, SND_SOC_BIAS_OFF);
944
945 return 0;
946}
947
948static int cs42l52_resume(struct snd_soc_codec *codec)
949{
950 cs42l52_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
951
952 return 0;
953}
954
955#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
956static int beep_rates[] = {
957 261, 522, 585, 667, 706, 774, 889, 1000,
958 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
959};
960
961static void cs42l52_beep_work(struct work_struct *work)
962{
963 struct cs42l52_private *cs42l52 =
964 container_of(work, struct cs42l52_private, beep_work);
965 struct snd_soc_codec *codec = cs42l52->codec;
966 struct snd_soc_dapm_context *dapm = &codec->dapm;
967 int i;
968 int val = 0;
969 int best = 0;
970
971 if (cs42l52->beep_rate) {
972 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
973 if (abs(cs42l52->beep_rate - beep_rates[i]) <
974 abs(cs42l52->beep_rate - beep_rates[best]))
975 best = i;
976 }
977
978 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
979 beep_rates[best], cs42l52->beep_rate);
980
981 val = (best << CS42L52_BEEP_RATE_SHIFT);
982
983 snd_soc_dapm_enable_pin(dapm, "Beep");
984 } else {
985 dev_dbg(codec->dev, "Disabling beep\n");
986 snd_soc_dapm_disable_pin(dapm, "Beep");
987 }
988
989 snd_soc_update_bits(codec, CS42L52_BEEP_FREQ,
990 CS42L52_BEEP_RATE_MASK, val);
991
992 snd_soc_dapm_sync(dapm);
993}
994
995/* For usability define a way of injecting beep events for the device -
996 * many systems will not have a keyboard.
997 */
998static int cs42l52_beep_event(struct input_dev *dev, unsigned int type,
999 unsigned int code, int hz)
1000{
1001 struct snd_soc_codec *codec = input_get_drvdata(dev);
1002 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1003
1004 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
1005
1006 switch (code) {
1007 case SND_BELL:
1008 if (hz)
1009 hz = 261;
1010 case SND_TONE:
1011 break;
1012 default:
1013 return -1;
1014 }
1015
1016 /* Kick the beep from a workqueue */
1017 cs42l52->beep_rate = hz;
1018 schedule_work(&cs42l52->beep_work);
1019 return 0;
1020}
1021
1022static ssize_t cs42l52_beep_set(struct device *dev,
1023 struct device_attribute *attr,
1024 const char *buf, size_t count)
1025{
1026 struct cs42l52_private *cs42l52 = dev_get_drvdata(dev);
1027 long int time;
1028 int ret;
1029
1030 ret = kstrtol(buf, 10, &time);
1031 if (ret != 0)
1032 return ret;
1033
1034 input_event(cs42l52->beep, EV_SND, SND_TONE, time);
1035
1036 return count;
1037}
1038
1039static DEVICE_ATTR(beep, 0200, NULL, cs42l52_beep_set);
1040
1041static void cs42l52_init_beep(struct snd_soc_codec *codec)
1042{
1043 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1044 int ret;
1045
1046 cs42l52->beep = input_allocate_device();
1047 if (!cs42l52->beep) {
1048 dev_err(codec->dev, "Failed to allocate beep device\n");
1049 return;
1050 }
1051
1052 INIT_WORK(&cs42l52->beep_work, cs42l52_beep_work);
1053 cs42l52->beep_rate = 0;
1054
1055 cs42l52->beep->name = "CS42L52 Beep Generator";
1056 cs42l52->beep->phys = dev_name(codec->dev);
1057 cs42l52->beep->id.bustype = BUS_I2C;
1058
1059 cs42l52->beep->evbit[0] = BIT_MASK(EV_SND);
1060 cs42l52->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1061 cs42l52->beep->event = cs42l52_beep_event;
1062 cs42l52->beep->dev.parent = codec->dev;
1063 input_set_drvdata(cs42l52->beep, codec);
1064
1065 ret = input_register_device(cs42l52->beep);
1066 if (ret != 0) {
1067 input_free_device(cs42l52->beep);
1068 cs42l52->beep = NULL;
1069 dev_err(codec->dev, "Failed to register beep device\n");
1070 }
1071
1072 ret = device_create_file(codec->dev, &dev_attr_beep);
1073 if (ret != 0) {
1074 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1075 ret);
1076 }
1077}
1078
1079static void cs42l52_free_beep(struct snd_soc_codec *codec)
1080{
1081 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1082
1083 device_remove_file(codec->dev, &dev_attr_beep);
1084 input_unregister_device(cs42l52->beep);
1085 cancel_work_sync(&cs42l52->beep_work);
1086 cs42l52->beep = NULL;
1087
1088 snd_soc_update_bits(codec, CS42L52_BEEP_TONE_CTL,
1089 CS42L52_BEEP_EN_MASK, 0);
1090}
1091#else
1092static void cs42l52_init_beep(struct snd_soc_codec *codec)
1093{
1094}
1095
1096static void cs42l52_free_beep(struct snd_soc_codec *codec)
1097{
1098}
1099#endif
1100
1101static int cs42l52_probe(struct snd_soc_codec *codec)
1102{
1103 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1104 int ret;
1105
1106 codec->control_data = cs42l52->regmap;
1107 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
1108 if (ret < 0) {
1109 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1110 return ret;
1111 }
1112 regcache_cache_only(cs42l52->regmap, true);
1113
1114 cs42l52_init_beep(codec);
1115
1116 cs42l52_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1117
1118 cs42l52->sysclk = CS42L52_DEFAULT_CLK;
1119 cs42l52->config.format = CS42L52_DEFAULT_FORMAT;
1120
1121 /* Set Platform MICx CFG */
1122 snd_soc_update_bits(codec, CS42L52_MICA_CTL,
1123 CS42L52_MIC_CTL_TYPE_MASK,
1124 cs42l52->pdata.mica_cfg <<
1125 CS42L52_MIC_CTL_TYPE_SHIFT);
1126
1127 snd_soc_update_bits(codec, CS42L52_MICB_CTL,
1128 CS42L52_MIC_CTL_TYPE_MASK,
1129 cs42l52->pdata.micb_cfg <<
1130 CS42L52_MIC_CTL_TYPE_SHIFT);
1131
1132 /* if Single Ended, Get Mic_Select */
1133 if (cs42l52->pdata.mica_cfg)
1134 snd_soc_update_bits(codec, CS42L52_MICA_CTL,
1135 CS42L52_MIC_CTL_MIC_SEL_MASK,
1136 cs42l52->pdata.mica_sel <<
1137 CS42L52_MIC_CTL_MIC_SEL_SHIFT);
1138 if (cs42l52->pdata.micb_cfg)
1139 snd_soc_update_bits(codec, CS42L52_MICB_CTL,
1140 CS42L52_MIC_CTL_MIC_SEL_MASK,
1141 cs42l52->pdata.micb_sel <<
1142 CS42L52_MIC_CTL_MIC_SEL_SHIFT);
1143
1144 /* Set Platform Charge Pump Freq */
1145 snd_soc_update_bits(codec, CS42L52_CHARGE_PUMP,
1146 CS42L52_CHARGE_PUMP_MASK,
1147 cs42l52->pdata.chgfreq <<
1148 CS42L52_CHARGE_PUMP_SHIFT);
1149
1150 /* Set Platform Bias Level */
1151 snd_soc_update_bits(codec, CS42L52_IFACE_CTL2,
1152 CS42L52_IFACE_CTL2_BIAS_LVL,
1153 cs42l52->pdata.micbias_lvl);
1154
1155 return ret;
1156}
1157
1158static int cs42l52_remove(struct snd_soc_codec *codec)
1159{
1160 cs42l52_free_beep(codec);
1161 cs42l52_set_bias_level(codec, SND_SOC_BIAS_OFF);
1162
1163 return 0;
1164}
1165
1166static struct snd_soc_codec_driver soc_codec_dev_cs42l52 = {
1167 .probe = cs42l52_probe,
1168 .remove = cs42l52_remove,
1169 .suspend = cs42l52_suspend,
1170 .resume = cs42l52_resume,
1171 .set_bias_level = cs42l52_set_bias_level,
1172
1173 .dapm_widgets = cs42l52_dapm_widgets,
1174 .num_dapm_widgets = ARRAY_SIZE(cs42l52_dapm_widgets),
1175 .dapm_routes = cs42l52_audio_map,
1176 .num_dapm_routes = ARRAY_SIZE(cs42l52_audio_map),
1177
1178 .controls = cs42l52_snd_controls,
1179 .num_controls = ARRAY_SIZE(cs42l52_snd_controls),
1180};
1181
1182/* Current and threshold powerup sequence Pg37 */
1183static const struct reg_default cs42l52_threshold_patch[] = {
1184
1185 { 0x00, 0x99 },
1186 { 0x3E, 0xBA },
1187 { 0x47, 0x80 },
1188 { 0x32, 0xBB },
1189 { 0x32, 0x3B },
1190 { 0x00, 0x00 },
1191
1192};
1193
1194static struct regmap_config cs42l52_regmap = {
1195 .reg_bits = 8,
1196 .val_bits = 8,
1197
1198 .max_register = CS42L52_MAX_REGISTER,
1199 .reg_defaults = cs42l52_reg_defaults,
1200 .num_reg_defaults = ARRAY_SIZE(cs42l52_reg_defaults),
1201 .readable_reg = cs42l52_readable_register,
1202 .volatile_reg = cs42l52_volatile_register,
1203 .cache_type = REGCACHE_RBTREE,
1204};
1205
1206static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1207 const struct i2c_device_id *id)
1208{
1209 struct cs42l52_private *cs42l52;
1210 int ret;
1211 unsigned int devid = 0;
1212 unsigned int reg;
1213
1214 cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l52_private),
1215 GFP_KERNEL);
1216 if (cs42l52 == NULL)
1217 return -ENOMEM;
1218 cs42l52->dev = &i2c_client->dev;
1219
1220 cs42l52->regmap = regmap_init_i2c(i2c_client, &cs42l52_regmap);
1221 if (IS_ERR(cs42l52->regmap)) {
1222 ret = PTR_ERR(cs42l52->regmap);
1223 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1224 goto err;
1225 }
1226
1227 i2c_set_clientdata(i2c_client, cs42l52);
1228
1229 if (dev_get_platdata(&i2c_client->dev))
1230 memcpy(&cs42l52->pdata, dev_get_platdata(&i2c_client->dev),
1231 sizeof(cs42l52->pdata));
1232
1233 ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch,
1234 ARRAY_SIZE(cs42l52_threshold_patch));
1235 if (ret != 0)
1236 dev_warn(cs42l52->dev, "Failed to apply regmap patch: %d\n",
1237 ret);
1238
1239 ret = regmap_read(cs42l52->regmap, CS42L52_CHIP, &reg);
1240 devid = reg & CS42L52_CHIP_ID_MASK;
1241 if (devid != CS42L52_CHIP_ID) {
1242 ret = -ENODEV;
1243 dev_err(&i2c_client->dev,
1244 "CS42L52 Device ID (%X). Expected %X\n",
1245 devid, CS42L52_CHIP_ID);
1246 goto err_regmap;
1247 }
1248
1249 regcache_cache_only(cs42l52->regmap, true);
1250
1251 ret = snd_soc_register_codec(&i2c_client->dev,
1252 &soc_codec_dev_cs42l52, &cs42l52_dai, 1);
1253 if (ret < 0)
1254 goto err_regmap;
1255 return 0;
1256
1257err_regmap:
1258 regmap_exit(cs42l52->regmap);
1259
1260err:
1261 return ret;
1262}
1263
1264static int cs42l52_i2c_remove(struct i2c_client *client)
1265{
1266 struct cs42l52_private *cs42l52 = i2c_get_clientdata(client);
1267
1268 snd_soc_unregister_codec(&client->dev);
1269 regmap_exit(cs42l52->regmap);
1270
1271 return 0;
1272}
1273
1274static const struct i2c_device_id cs42l52_id[] = {
1275 { "cs42l52", 0 },
1276 { }
1277};
1278MODULE_DEVICE_TABLE(i2c, cs42l52_id);
1279
1280static struct i2c_driver cs42l52_i2c_driver = {
1281 .driver = {
1282 .name = "cs42l52",
1283 .owner = THIS_MODULE,
1284 },
1285 .id_table = cs42l52_id,
1286 .probe = cs42l52_i2c_probe,
1287 .remove = __devexit_p(cs42l52_i2c_remove),
1288};
1289
1290module_i2c_driver(cs42l52_i2c_driver);
1291
1292MODULE_DESCRIPTION("ASoC CS42L52 driver");
1293MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1294MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1295MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/cs42l52.h b/sound/soc/codecs/cs42l52.h
new file mode 100644
index 000000000000..60985c059071
--- /dev/null
+++ b/sound/soc/codecs/cs42l52.h
@@ -0,0 +1,274 @@
1/*
2 * cs42l52.h -- CS42L52 ALSA SoC audio driver
3 *
4 * Copyright 2012 CirrusLogic, Inc.
5 *
6 * Author: Georgi Vlaev <joe@nucleusys.com>
7 * Author: Brian Austin <brian.austin@cirrus.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#ifndef __CS42L52_H__
16#define __CS42L52_H__
17
18#define CS42L52_NAME "CS42L52"
19#define CS42L52_DEFAULT_CLK 12000000
20#define CS42L52_MIN_CLK 11000000
21#define CS42L52_MAX_CLK 27000000
22#define CS42L52_DEFAULT_FORMAT SNDRV_PCM_FMTBIT_S16_LE
23#define CS42L52_DEFAULT_MAX_CHANS 2
24#define CS42L52_SYSCLK 1
25
26#define CS42L52_CHIP_SWICTH (1 << 17)
27#define CS42L52_ALL_IN_ONE (1 << 16)
28#define CS42L52_CHIP_ONE 0x00
29#define CS42L52_CHIP_TWO 0x01
30#define CS42L52_CHIP_THR 0x02
31#define CS42L52_CHIP_MASK 0x0f
32
33#define CS42L52_FIX_BITS_CTL 0x00
34#define CS42L52_CHIP 0x01
35#define CS42L52_CHIP_ID 0xE0
36#define CS42L52_CHIP_ID_MASK 0xF8
37#define CS42L52_CHIP_REV_A0 0x00
38#define CS42L52_CHIP_REV_A1 0x01
39#define CS42L52_CHIP_REV_B0 0x02
40#define CS42L52_CHIP_REV_MASK 0x03
41
42#define CS42L52_PWRCTL1 0x02
43#define CS42L52_PWRCTL1_PDN_ALL 0x9F
44#define CS42L52_PWRCTL1_PDN_CHRG 0x80
45#define CS42L52_PWRCTL1_PDN_PGAB 0x10
46#define CS42L52_PWRCTL1_PDN_PGAA 0x08
47#define CS42L52_PWRCTL1_PDN_ADCB 0x04
48#define CS42L52_PWRCTL1_PDN_ADCA 0x02
49#define CS42L52_PWRCTL1_PDN_CODEC 0x01
50
51#define CS42L52_PWRCTL2 0x03
52#define CS42L52_PWRCTL2_OVRDB (1 << 4)
53#define CS42L52_PWRCTL2_OVRDA (1 << 3)
54#define CS42L52_PWRCTL2_PDN_MICB (1 << 2)
55#define CS42L52_PWRCTL2_PDN_MICB_SHIFT 2
56#define CS42L52_PWRCTL2_PDN_MICA (1 << 1)
57#define CS42L52_PWRCTL2_PDN_MICA_SHIFT 1
58#define CS42L52_PWRCTL2_PDN_MICBIAS (1 << 0)
59#define CS42L52_PWRCTL2_PDN_MICBIAS_SHIFT 0
60
61#define CS42L52_PWRCTL3 0x04
62#define CS42L52_PWRCTL3_HPB_PDN_SHIFT 6
63#define CS42L52_PWRCTL3_HPB_ON_LOW 0x00
64#define CS42L52_PWRCTL3_HPB_ON_HIGH 0x01
65#define CS42L52_PWRCTL3_HPB_ALWAYS_ON 0x02
66#define CS42L52_PWRCTL3_HPB_ALWAYS_OFF 0x03
67#define CS42L52_PWRCTL3_HPA_PDN_SHIFT 4
68#define CS42L52_PWRCTL3_HPA_ON_LOW 0x00
69#define CS42L52_PWRCTL3_HPA_ON_HIGH 0x01
70#define CS42L52_PWRCTL3_HPA_ALWAYS_ON 0x02
71#define CS42L52_PWRCTL3_HPA_ALWAYS_OFF 0x03
72#define CS42L52_PWRCTL3_SPKB_PDN_SHIFT 2
73#define CS42L52_PWRCTL3_SPKB_ON_LOW 0x00
74#define CS42L52_PWRCTL3_SPKB_ON_HIGH 0x01
75#define CS42L52_PWRCTL3_SPKB_ALWAYS_ON 0x02
76#define CS42L52_PWRCTL3_PDN_SPKB (1 << 2)
77#define CS42L52_PWRCTL3_PDN_SPKA (1 << 0)
78#define CS42L52_PWRCTL3_SPKA_PDN_SHIFT 0
79#define CS42L52_PWRCTL3_SPKA_ON_LOW 0x00
80#define CS42L52_PWRCTL3_SPKA_ON_HIGH 0x01
81#define CS42L52_PWRCTL3_SPKA_ALWAYS_ON 0x02
82
83#define CS42L52_DEFAULT_OUTPUT_STATE 0x05
84#define CS42L52_PWRCTL3_CONF_MASK 0x03
85
86#define CS42L52_CLK_CTL 0x05
87#define CLK_AUTODECT_ENABLE (1 << 7)
88#define CLK_SPEED_SHIFT 5
89#define CLK_DS_MODE 0x00
90#define CLK_SS_MODE 0x01
91#define CLK_HS_MODE 0x02
92#define CLK_QS_MODE 0x03
93#define CLK_32K_SR_SHIFT 4
94#define CLK_32K 0x01
95#define CLK_NO_32K 0x00
96#define CLK_27M_MCLK_SHIFT 3
97#define CLK_27M_MCLK 0x01
98#define CLK_NO_27M 0x00
99#define CLK_RATIO_SHIFT 1
100#define CLK_R_128 0x00
101#define CLK_R_125 0x01
102#define CLK_R_132 0x02
103#define CLK_R_136 0x03
104
105#define CS42L52_IFACE_CTL1 0x06
106#define CS42L52_IFACE_CTL1_MASTER (1 << 7)
107#define CS42L52_IFACE_CTL1_SLAVE (0 << 7)
108#define CS42L52_IFACE_CTL1_INV_SCLK (1 << 6)
109#define CS42L52_IFACE_CTL1_ADC_FMT_I2S (1 << 5)
110#define CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J (0 << 5)
111#define CS42L52_IFACE_CTL1_DSP_MODE_EN (1 << 4)
112#define CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J (0 << 2)
113#define CS42L52_IFACE_CTL1_DAC_FMT_I2S (1 << 2)
114#define CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J (2 << 2)
115#define CS42L52_IFACE_CTL1_WL_32BIT (0x00)
116#define CS42L52_IFACE_CTL1_WL_24BIT (0x01)
117#define CS42L52_IFACE_CTL1_WL_20BIT (0x02)
118#define CS42L52_IFACE_CTL1_WL_16BIT (0x03)
119#define CS42L52_IFACE_CTL1_WL_MASK 0xFFFF
120
121#define CS42L52_IFACE_CTL2 0x07
122#define CS42L52_IFACE_CTL2_SC_MC_EQ (1 << 6)
123#define CS42L52_IFACE_CTL2_LOOPBACK (1 << 5)
124#define CS42L52_IFACE_CTL2_S_MODE_OUTPUT_EN (0 << 4)
125#define CS42L52_IFACE_CTL2_S_MODE_OUTPUT_HIZ (1 << 4)
126#define CS42L52_IFACE_CTL2_HP_SW_INV (1 << 3)
127#define CS42L52_IFACE_CTL2_BIAS_LVL 0x07
128
129#define CS42L52_ADC_PGA_A 0x08
130#define CS42L52_ADC_PGA_B 0x09
131#define CS42L52_ADC_SEL_SHIFT 5
132#define CS42L52_ADC_SEL_AIN1 0x00
133#define CS42L52_ADC_SEL_AIN2 0x01
134#define CS42L52_ADC_SEL_AIN3 0x02
135#define CS42L52_ADC_SEL_AIN4 0x03
136#define CS42L52_ADC_SEL_PGA 0x04
137
138#define CS42L52_ANALOG_HPF_CTL 0x0A
139#define CS42L52_HPF_CTL_ANLGSFTB (1 << 3)
140#define CS42L52_HPF_CTL_ANLGSFTA (1 << 0)
141
142#define CS42L52_ADC_HPF_FREQ 0x0B
143#define CS42L52_ADC_MISC_CTL 0x0C
144#define CS42L52_ADC_MISC_CTL_SOURCE_DSP (1 << 6)
145
146#define CS42L52_PB_CTL1 0x0D
147#define CS42L52_PB_CTL1_HP_GAIN_SHIFT 5
148#define CS42L52_PB_CTL1_HP_GAIN_03959 0x00
149#define CS42L52_PB_CTL1_HP_GAIN_04571 0x01
150#define CS42L52_PB_CTL1_HP_GAIN_05111 0x02
151#define CS42L52_PB_CTL1_HP_GAIN_06047 0x03
152#define CS42L52_PB_CTL1_HP_GAIN_07099 0x04
153#define CS42L52_PB_CTL1_HP_GAIN_08399 0x05
154#define CS42L52_PB_CTL1_HP_GAIN_10000 0x06
155#define CS42L52_PB_CTL1_HP_GAIN_11430 0x07
156#define CS42L52_PB_CTL1_INV_PCMB (1 << 3)
157#define CS42L52_PB_CTL1_INV_PCMA (1 << 2)
158#define CS42L52_PB_CTL1_MSTB_MUTE (1 << 1)
159#define CS42L52_PB_CTL1_MSTA_MUTE (1 << 0)
160#define CS42L52_PB_CTL1_MUTE_MASK 0xFFFD
161#define CS42L52_PB_CTL1_MUTE 3
162#define CS42L52_PB_CTL1_UNMUTE 0
163
164#define CS42L52_MISC_CTL 0x0E
165#define CS42L52_MISC_CTL_DEEMPH (1 << 2)
166#define CS42L52_MISC_CTL_DIGSFT (1 << 1)
167#define CS42L52_MISC_CTL_DIGZC (1 << 0)
168
169#define CS42L52_PB_CTL2 0x0F
170#define CS42L52_PB_CTL2_HPB_MUTE (1 << 7)
171#define CS42L52_PB_CTL2_HPA_MUTE (1 << 6)
172#define CS42L52_PB_CTL2_SPKB_MUTE (1 << 5)
173#define CS42L52_PB_CTL2_SPKA_MUTE (1 << 4)
174#define CS42L52_PB_CTL2_SPK_SWAP (1 << 2)
175#define CS42L52_PB_CTL2_SPK_MONO (1 << 1)
176#define CS42L52_PB_CTL2_SPK_MUTE50 (1 << 0)
177
178#define CS42L52_MICA_CTL 0x10
179#define CS42L52_MICB_CTL 0x11
180#define CS42L52_MIC_CTL_MIC_SEL_MASK 0xBF
181#define CS42L52_MIC_CTL_MIC_SEL_SHIFT 6
182#define CS42L52_MIC_CTL_TYPE_MASK 0xDF
183#define CS42L52_MIC_CTL_TYPE_SHIFT 5
184
185
186#define CS42L52_PGAA_CTL 0x12
187#define CS42L52_PGAB_CTL 0x13
188#define CS42L52_PGAX_CTL_VOL_12DB 24
189#define CS42L52_PGAX_CTL_VOL_6DB 12 /*step size 0.5db*/
190
191#define CS42L52_PASSTHRUA_VOL 0x14
192#define CS42L52_PASSTHRUB_VOL 0x15
193
194#define CS42L52_ADCA_VOL 0x16
195#define CS42L52_ADCB_VOL 0x17
196#define CS42L52_ADCX_VOL_24DB 24 /*step size 1db*/
197#define CS42L52_ADCX_VOL_12DB 12
198#define CS42L52_ADCX_VOL_6DB 6
199
200#define CS42L52_ADCA_MIXER_VOL 0x18
201#define CS42L52_ADCB_MIXER_VOL 0x19
202#define CS42L52_ADC_MIXER_VOL_12DB 0x18
203
204#define CS42L52_PCMA_MIXER_VOL 0x1A
205#define CS42L52_PCMB_MIXER_VOL 0x1B
206
207#define CS42L52_BEEP_FREQ 0x1C
208#define CS42L52_BEEP_VOL 0x1D
209#define CS42L52_BEEP_TONE_CTL 0x1E
210#define CS42L52_BEEP_RATE_SHIFT 4
211#define CS42L52_BEEP_RATE_MASK 0x0F
212
213#define CS42L52_TONE_CTL 0x1F
214#define CS42L52_BEEP_EN_MASK 0x3F
215
216#define CS42L52_MASTERA_VOL 0x20
217#define CS42L52_MASTERB_VOL 0x21
218
219#define CS42L52_HPA_VOL 0x22
220#define CS42L52_HPB_VOL 0x23
221#define CS42L52_DEFAULT_HP_VOL 0xF0
222
223#define CS42L52_SPKA_VOL 0x24
224#define CS42L52_SPKB_VOL 0x25
225#define CS42L52_DEFAULT_SPK_VOL 0xF0
226
227#define CS42L52_ADC_PCM_MIXER 0x26
228
229#define CS42L52_LIMITER_CTL1 0x27
230#define CS42L52_LIMITER_CTL2 0x28
231#define CS42L52_LIMITER_AT_RATE 0x29
232
233#define CS42L52_ALC_CTL 0x2A
234#define CS42L52_ALC_CTL_ALCB_ENABLE_SHIFT 7
235#define CS42L52_ALC_CTL_ALCA_ENABLE_SHIFT 6
236#define CS42L52_ALC_CTL_FASTEST_ATTACK 0
237
238#define CS42L52_ALC_RATE 0x2B
239#define CS42L52_ALC_SLOWEST_RELEASE 0x3F
240
241#define CS42L52_ALC_THRESHOLD 0x2C
242#define CS42L52_ALC_MAX_RATE_SHIFT 5
243#define CS42L52_ALC_MIN_RATE_SHIFT 2
244#define CS42L52_ALC_RATE_0DB 0
245#define CS42L52_ALC_RATE_3DB 1
246#define CS42L52_ALC_RATE_6DB 2
247
248#define CS42L52_NOISE_GATE_CTL 0x2D
249#define CS42L52_NG_ENABLE_SHIFT 6
250#define CS42L52_NG_THRESHOLD_SHIFT 2
251#define CS42L52_NG_MIN_70DB 2
252#define CS42L52_NG_DELAY_SHIFT 0
253#define CS42L52_NG_DELAY_100MS 1
254
255#define CS42L52_CLK_STATUS 0x2E
256#define CS42L52_BATT_COMPEN 0x2F
257
258#define CS42L52_BATT_LEVEL 0x30
259#define CS42L52_SPK_STATUS 0x31
260#define CS42L52_SPK_STATUS_PIN_SHIFT 3
261#define CS42L52_SPK_STATUS_PIN_HIGH 1
262
263#define CS42L52_TEM_CTL 0x32
264#define CS42L52_TEM_CTL_SET 0x80
265#define CS42L52_THE_FOLDBACK 0x33
266#define CS42L52_CHARGE_PUMP 0x34
267#define CS42L52_CHARGE_PUMP_MASK 0xF0
268#define CS42L52_CHARGE_PUMP_SHIFT 4
269#define CS42L52_FIX_BITS1 0x3E
270#define CS42L52_FIX_BITS2 0x47
271
272#define CS42L52_MAX_REGISTER 0x34
273
274#endif
diff --git a/sound/soc/codecs/cs42l73.c b/sound/soc/codecs/cs42l73.c
index 3686417f5ea5..e0d45fdaa750 100644
--- a/sound/soc/codecs/cs42l73.c
+++ b/sound/soc/codecs/cs42l73.c
@@ -43,9 +43,6 @@ struct cs42l73_private {
43}; 43};
44 44
45static const struct reg_default cs42l73_reg_defaults[] = { 45static const struct reg_default cs42l73_reg_defaults[] = {
46 { 1, 0x42 }, /* r01 - Device ID A&B */
47 { 2, 0xA7 }, /* r02 - Device ID C&D */
48 { 3, 0x30 }, /* r03 - Device ID E */
49 { 6, 0xF1 }, /* r06 - Power Ctl 1 */ 46 { 6, 0xF1 }, /* r06 - Power Ctl 1 */
50 { 7, 0xDF }, /* r07 - Power Ctl 2 */ 47 { 7, 0xDF }, /* r07 - Power Ctl 2 */
51 { 8, 0x3F }, /* r08 - Power Ctl 3 */ 48 { 8, 0x3F }, /* r08 - Power Ctl 3 */
@@ -402,37 +399,37 @@ static const struct snd_kcontrol_new ear_amp_ctl =
402 399
403static const struct snd_kcontrol_new cs42l73_snd_controls[] = { 400static const struct snd_kcontrol_new cs42l73_snd_controls[] = {
404 SOC_DOUBLE_R_SX_TLV("Headphone Analog Playback Volume", 401 SOC_DOUBLE_R_SX_TLV("Headphone Analog Playback Volume",
405 CS42L73_HPAAVOL, CS42L73_HPBAVOL, 7, 402 CS42L73_HPAAVOL, CS42L73_HPBAVOL, 0,
406 0xffffffC1, 0x0C, hpaloa_tlv), 403 0x41, 0x4B, hpaloa_tlv),
407 404
408 SOC_DOUBLE_R_SX_TLV("LineOut Analog Playback Volume", CS42L73_LOAAVOL, 405 SOC_DOUBLE_R_SX_TLV("LineOut Analog Playback Volume", CS42L73_LOAAVOL,
409 CS42L73_LOBAVOL, 7, 0xffffffC1, 0x0C, hpaloa_tlv), 406 CS42L73_LOBAVOL, 0, 0x41, 0x4B, hpaloa_tlv),
410 407
411 SOC_DOUBLE_R_SX_TLV("Input PGA Analog Volume", CS42L73_MICAPREPGAAVOL, 408 SOC_DOUBLE_R_SX_TLV("Input PGA Analog Volume", CS42L73_MICAPREPGAAVOL,
412 CS42L73_MICBPREPGABVOL, 5, 0xffffff35, 409 CS42L73_MICBPREPGABVOL, 5, 0x34,
413 0x34, micpga_tlv), 410 0x24, micpga_tlv),
414 411
415 SOC_DOUBLE_R("MIC Preamp Switch", CS42L73_MICAPREPGAAVOL, 412 SOC_DOUBLE_R("MIC Preamp Switch", CS42L73_MICAPREPGAAVOL,
416 CS42L73_MICBPREPGABVOL, 6, 1, 1), 413 CS42L73_MICBPREPGABVOL, 6, 1, 1),
417 414
418 SOC_DOUBLE_R_SX_TLV("Input Path Digital Volume", CS42L73_IPADVOL, 415 SOC_DOUBLE_R_SX_TLV("Input Path Digital Volume", CS42L73_IPADVOL,
419 CS42L73_IPBDVOL, 7, 0xffffffA0, 0xA0, ipd_tlv), 416 CS42L73_IPBDVOL, 0, 0xA0, 0x6C, ipd_tlv),
420 417
421 SOC_DOUBLE_R_SX_TLV("HL Digital Playback Volume", 418 SOC_DOUBLE_R_SX_TLV("HL Digital Playback Volume",
422 CS42L73_HLADVOL, CS42L73_HLBDVOL, 7, 0xffffffE5, 419 CS42L73_HLADVOL, CS42L73_HLBDVOL,
423 0xE4, hl_tlv), 420 0, 0x34, 0xE4, hl_tlv),
424 421
425 SOC_SINGLE_TLV("ADC A Boost Volume", 422 SOC_SINGLE_TLV("ADC A Boost Volume",
426 CS42L73_ADCIPC, 2, 0x01, 1, adc_boost_tlv), 423 CS42L73_ADCIPC, 2, 0x01, 1, adc_boost_tlv),
427 424
428 SOC_SINGLE_TLV("ADC B Boost Volume", 425 SOC_SINGLE_TLV("ADC B Boost Volume",
429 CS42L73_ADCIPC, 6, 0x01, 1, adc_boost_tlv), 426 CS42L73_ADCIPC, 6, 0x01, 1, adc_boost_tlv),
430 427
431 SOC_SINGLE_TLV("Speakerphone Digital Playback Volume", 428 SOC_SINGLE_SX_TLV("Speakerphone Digital Volume",
432 CS42L73_SPKDVOL, 0, 0xE4, 1, hl_tlv), 429 CS42L73_SPKDVOL, 0, 0x34, 0xE4, hl_tlv),
433 430
434 SOC_SINGLE_TLV("Ear Speaker Digital Playback Volume", 431 SOC_SINGLE_SX_TLV("Ear Speaker Digital Volume",
435 CS42L73_ESLDVOL, 0, 0xE4, 1, hl_tlv), 432 CS42L73_ESLDVOL, 0, 0x34, 0xE4, hl_tlv),
436 433
437 SOC_DOUBLE_R("Headphone Analog Playback Switch", CS42L73_HPAAVOL, 434 SOC_DOUBLE_R("Headphone Analog Playback Switch", CS42L73_HPAAVOL,
438 CS42L73_HPBAVOL, 7, 1, 1), 435 CS42L73_HPBAVOL, 7, 1, 1),
@@ -599,17 +596,17 @@ static const struct snd_soc_dapm_widget cs42l73_dapm_widgets[] = {
599 SND_SOC_DAPM_INPUT("MIC2"), 596 SND_SOC_DAPM_INPUT("MIC2"),
600 SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS42L73_PWRCTL2, 7, 1, NULL, 0), 597 SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS42L73_PWRCTL2, 7, 1, NULL, 0),
601 598
602 SND_SOC_DAPM_AIF_OUT("XSPOUTL", "XSP Capture", 0, 599 SND_SOC_DAPM_AIF_OUT("XSPOUTL", NULL, 0,
603 CS42L73_PWRCTL2, 1, 1), 600 CS42L73_PWRCTL2, 1, 1),
604 SND_SOC_DAPM_AIF_OUT("XSPOUTR", "XSP Capture", 0, 601 SND_SOC_DAPM_AIF_OUT("XSPOUTR", NULL, 0,
605 CS42L73_PWRCTL2, 1, 1), 602 CS42L73_PWRCTL2, 1, 1),
606 SND_SOC_DAPM_AIF_OUT("ASPOUTL", "ASP Capture", 0, 603 SND_SOC_DAPM_AIF_OUT("ASPOUTL", NULL, 0,
607 CS42L73_PWRCTL2, 3, 1), 604 CS42L73_PWRCTL2, 3, 1),
608 SND_SOC_DAPM_AIF_OUT("ASPOUTR", "ASP Capture", 0, 605 SND_SOC_DAPM_AIF_OUT("ASPOUTR", NULL, 0,
609 CS42L73_PWRCTL2, 3, 1), 606 CS42L73_PWRCTL2, 3, 1),
610 SND_SOC_DAPM_AIF_OUT("VSPOUTL", "VSP Capture", 0, 607 SND_SOC_DAPM_AIF_OUT("VSPOUTL", NULL, 0,
611 CS42L73_PWRCTL2, 4, 1), 608 CS42L73_PWRCTL2, 4, 1),
612 SND_SOC_DAPM_AIF_OUT("VSPOUTR", "VSP Capture", 0, 609 SND_SOC_DAPM_AIF_OUT("VSPOUTR", NULL, 0,
613 CS42L73_PWRCTL2, 4, 1), 610 CS42L73_PWRCTL2, 4, 1),
614 611
615 SND_SOC_DAPM_PGA("PGA Left", SND_SOC_NOPM, 0, 0, NULL, 0), 612 SND_SOC_DAPM_PGA("PGA Left", SND_SOC_NOPM, 0, 0, NULL, 0),
@@ -638,21 +635,21 @@ static const struct snd_soc_dapm_widget cs42l73_dapm_widgets[] = {
638 SND_SOC_DAPM_MIXER("VSPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 635 SND_SOC_DAPM_MIXER("VSPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
639 SND_SOC_DAPM_MIXER("VSPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 636 SND_SOC_DAPM_MIXER("VSPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
640 637
641 SND_SOC_DAPM_AIF_IN("XSPINL", "XSP Playback", 0, 638 SND_SOC_DAPM_AIF_IN("XSPINL", NULL, 0,
642 CS42L73_PWRCTL2, 0, 1), 639 CS42L73_PWRCTL2, 0, 1),
643 SND_SOC_DAPM_AIF_IN("XSPINR", "XSP Playback", 0, 640 SND_SOC_DAPM_AIF_IN("XSPINR", NULL, 0,
644 CS42L73_PWRCTL2, 0, 1), 641 CS42L73_PWRCTL2, 0, 1),
645 SND_SOC_DAPM_AIF_IN("XSPINM", "XSP Playback", 0, 642 SND_SOC_DAPM_AIF_IN("XSPINM", NULL, 0,
646 CS42L73_PWRCTL2, 0, 1), 643 CS42L73_PWRCTL2, 0, 1),
647 644
648 SND_SOC_DAPM_AIF_IN("ASPINL", "ASP Playback", 0, 645 SND_SOC_DAPM_AIF_IN("ASPINL", NULL, 0,
649 CS42L73_PWRCTL2, 2, 1), 646 CS42L73_PWRCTL2, 2, 1),
650 SND_SOC_DAPM_AIF_IN("ASPINR", "ASP Playback", 0, 647 SND_SOC_DAPM_AIF_IN("ASPINR", NULL, 0,
651 CS42L73_PWRCTL2, 2, 1), 648 CS42L73_PWRCTL2, 2, 1),
652 SND_SOC_DAPM_AIF_IN("ASPINM", "ASP Playback", 0, 649 SND_SOC_DAPM_AIF_IN("ASPINM", NULL, 0,
653 CS42L73_PWRCTL2, 2, 1), 650 CS42L73_PWRCTL2, 2, 1),
654 651
655 SND_SOC_DAPM_AIF_IN("VSPIN", "VSP Playback", 0, 652 SND_SOC_DAPM_AIF_IN("VSPIN", NULL, 0,
656 CS42L73_PWRCTL2, 4, 1), 653 CS42L73_PWRCTL2, 4, 1),
657 654
658 SND_SOC_DAPM_MIXER("HL Left Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), 655 SND_SOC_DAPM_MIXER("HL Left Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
@@ -776,6 +773,14 @@ static const struct snd_soc_dapm_route cs42l73_audio_map[] = {
776 {"HL Left Mixer", NULL, "VSPIN"}, 773 {"HL Left Mixer", NULL, "VSPIN"},
777 {"HL Right Mixer", NULL, "VSPIN"}, 774 {"HL Right Mixer", NULL, "VSPIN"},
778 775
776 {"ASPINL", NULL, "ASP Playback"},
777 {"ASPINM", NULL, "ASP Playback"},
778 {"ASPINR", NULL, "ASP Playback"},
779 {"XSPINL", NULL, "XSP Playback"},
780 {"XSPINM", NULL, "XSP Playback"},
781 {"XSPINR", NULL, "XSP Playback"},
782 {"VSPIN", NULL, "VSP Playback"},
783
779 /* Capture Paths */ 784 /* Capture Paths */
780 {"MIC1", NULL, "MIC1 Bias"}, 785 {"MIC1", NULL, "MIC1 Bias"},
781 {"PGA Left Mux", "Mic 1", "MIC1"}, 786 {"PGA Left Mux", "Mic 1", "MIC1"},
@@ -822,6 +827,13 @@ static const struct snd_soc_dapm_route cs42l73_audio_map[] = {
822 827
823 {"VSPOUTL", NULL, "VSPL Output Mixer"}, 828 {"VSPOUTL", NULL, "VSPL Output Mixer"},
824 {"VSPOUTR", NULL, "VSPR Output Mixer"}, 829 {"VSPOUTR", NULL, "VSPR Output Mixer"},
830
831 {"ASP Capture", NULL, "ASPOUTL"},
832 {"ASP Capture", NULL, "ASPOUTR"},
833 {"XSP Capture", NULL, "XSPOUTL"},
834 {"XSP Capture", NULL, "XSPOUTR"},
835 {"VSP Capture", NULL, "VSPOUTL"},
836 {"VSP Capture", NULL, "VSPOUTR"},
825}; 837};
826 838
827struct cs42l73_mclk_div { 839struct cs42l73_mclk_div {
@@ -1091,8 +1103,7 @@ static int cs42l73_pcm_hw_params(struct snd_pcm_substream *substream,
1091 struct snd_pcm_hw_params *params, 1103 struct snd_pcm_hw_params *params,
1092 struct snd_soc_dai *dai) 1104 struct snd_soc_dai *dai)
1093{ 1105{
1094 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1106 struct snd_soc_codec *codec = dai->codec;
1095 struct snd_soc_codec *codec = rtd->codec;
1096 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec); 1107 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
1097 int id = dai->id; 1108 int id = dai->id;
1098 int mclk_coeff; 1109 int mclk_coeff;
@@ -1429,25 +1440,7 @@ static struct i2c_driver cs42l73_i2c_driver = {
1429 1440
1430}; 1441};
1431 1442
1432static int __init cs42l73_modinit(void) 1443module_i2c_driver(cs42l73_i2c_driver);
1433{
1434 int ret;
1435 ret = i2c_add_driver(&cs42l73_i2c_driver);
1436 if (ret != 0) {
1437 pr_err("Failed to register CS42L73 I2C driver: %d\n", ret);
1438 return ret;
1439 }
1440 return 0;
1441}
1442
1443module_init(cs42l73_modinit);
1444
1445static void __exit cs42l73_exit(void)
1446{
1447 i2c_del_driver(&cs42l73_i2c_driver);
1448}
1449
1450module_exit(cs42l73_exit);
1451 1444
1452MODULE_DESCRIPTION("ASoC CS42L73 driver"); 1445MODULE_DESCRIPTION("ASoC CS42L73 driver");
1453MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>"); 1446MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
diff --git a/sound/soc/codecs/da7210.c b/sound/soc/codecs/da7210.c
index 7843711729bc..af5db7080519 100644
--- a/sound/soc/codecs/da7210.c
+++ b/sound/soc/codecs/da7210.c
@@ -17,6 +17,7 @@
17 17
18#include <linux/delay.h> 18#include <linux/delay.h>
19#include <linux/i2c.h> 19#include <linux/i2c.h>
20#include <linux/spi/spi.h>
20#include <linux/regmap.h> 21#include <linux/regmap.h>
21#include <linux/slab.h> 22#include <linux/slab.h>
22#include <linux/module.h> 23#include <linux/module.h>
@@ -27,6 +28,7 @@
27#include <sound/tlv.h> 28#include <sound/tlv.h>
28 29
29/* DA7210 register space */ 30/* DA7210 register space */
31#define DA7210_PAGE_CONTROL 0x00
30#define DA7210_CONTROL 0x01 32#define DA7210_CONTROL 0x01
31#define DA7210_STATUS 0x02 33#define DA7210_STATUS 0x02
32#define DA7210_STARTUP1 0x03 34#define DA7210_STARTUP1 0x03
@@ -146,6 +148,7 @@
146#define DA7210_DAI_EN (1 << 7) 148#define DA7210_DAI_EN (1 << 7)
147 149
148/*PLL_DIV3 bit fields */ 150/*PLL_DIV3 bit fields */
151#define DA7210_PLL_DIV_L_MASK (0xF << 0)
149#define DA7210_MCLK_RANGE_10_20_MHZ (1 << 4) 152#define DA7210_MCLK_RANGE_10_20_MHZ (1 << 4)
150#define DA7210_PLL_BYP (1 << 6) 153#define DA7210_PLL_BYP (1 << 6)
151 154
@@ -162,12 +165,16 @@
162#define DA7210_PLL_FS_48000 (0xB << 0) 165#define DA7210_PLL_FS_48000 (0xB << 0)
163#define DA7210_PLL_FS_88200 (0xE << 0) 166#define DA7210_PLL_FS_88200 (0xE << 0)
164#define DA7210_PLL_FS_96000 (0xF << 0) 167#define DA7210_PLL_FS_96000 (0xF << 0)
168#define DA7210_MCLK_DET_EN (0x1 << 5)
169#define DA7210_MCLK_SRM_EN (0x1 << 6)
165#define DA7210_PLL_EN (0x1 << 7) 170#define DA7210_PLL_EN (0x1 << 7)
166 171
167/* SOFTMUTE bit fields */ 172/* SOFTMUTE bit fields */
168#define DA7210_RAMP_EN (1 << 6) 173#define DA7210_RAMP_EN (1 << 6)
169 174
170/* CONTROL bit fields */ 175/* CONTROL bit fields */
176#define DA7210_REG_EN (1 << 0)
177#define DA7210_BIAS_EN (1 << 2)
171#define DA7210_NOISE_SUP_EN (1 << 3) 178#define DA7210_NOISE_SUP_EN (1 << 3)
172 179
173/* IN_GAIN bit fields */ 180/* IN_GAIN bit fields */
@@ -206,6 +213,47 @@
206#define DA7210_OUT2_OUTMIX_L (1 << 6) 213#define DA7210_OUT2_OUTMIX_L (1 << 6)
207#define DA7210_OUT2_EN (1 << 7) 214#define DA7210_OUT2_EN (1 << 7)
208 215
216struct pll_div {
217 int fref;
218 int fout;
219 u8 div1;
220 u8 div2;
221 u8 div3;
222 u8 mode; /* 0 = slave, 1 = master */
223};
224
225/* PLL dividers table */
226static const struct pll_div da7210_pll_div[] = {
227 /* for MASTER mode, fs = 44.1Khz */
228 { 12000000, 2822400, 0xE8, 0x6C, 0x2, 1}, /* MCLK=12Mhz */
229 { 13000000, 2822400, 0xDF, 0x28, 0xC, 1}, /* MCLK=13Mhz */
230 { 13500000, 2822400, 0xDB, 0x0A, 0xD, 1}, /* MCLK=13.5Mhz */
231 { 14400000, 2822400, 0xD4, 0x5A, 0x2, 1}, /* MCLK=14.4Mhz */
232 { 19200000, 2822400, 0xBB, 0x43, 0x9, 1}, /* MCLK=19.2Mhz */
233 { 19680000, 2822400, 0xB9, 0x6D, 0xA, 1}, /* MCLK=19.68Mhz */
234 { 19800000, 2822400, 0xB8, 0xFB, 0xB, 1}, /* MCLK=19.8Mhz */
235 /* for MASTER mode, fs = 48Khz */
236 { 12000000, 3072000, 0xF3, 0x12, 0x7, 1}, /* MCLK=12Mhz */
237 { 13000000, 3072000, 0xE8, 0xFD, 0x5, 1}, /* MCLK=13Mhz */
238 { 13500000, 3072000, 0xE4, 0x82, 0x3, 1}, /* MCLK=13.5Mhz */
239 { 14400000, 3072000, 0xDD, 0x3A, 0x0, 1}, /* MCLK=14.4Mhz */
240 { 19200000, 3072000, 0xC1, 0xEB, 0x8, 1}, /* MCLK=19.2Mhz */
241 { 19680000, 3072000, 0xBF, 0xEC, 0x0, 1}, /* MCLK=19.68Mhz */
242 { 19800000, 3072000, 0xBF, 0x70, 0x0, 1}, /* MCLK=19.8Mhz */
243 /* for SLAVE mode with SRM */
244 { 12000000, 2822400, 0xED, 0xBF, 0x5, 0}, /* MCLK=12Mhz */
245 { 13000000, 2822400, 0xE4, 0x13, 0x0, 0}, /* MCLK=13Mhz */
246 { 13500000, 2822400, 0xDF, 0xC6, 0x8, 0}, /* MCLK=13.5Mhz */
247 { 14400000, 2822400, 0xD8, 0xCA, 0x1, 0}, /* MCLK=14.4Mhz */
248 { 19200000, 2822400, 0xBE, 0x97, 0x9, 0}, /* MCLK=19.2Mhz */
249 { 19680000, 2822400, 0xBC, 0xAC, 0xD, 0}, /* MCLK=19.68Mhz */
250 { 19800000, 2822400, 0xBC, 0x35, 0xE, 0}, /* MCLK=19.8Mhz */
251};
252
253enum clk_src {
254 DA7210_CLKSRC_MCLK
255};
256
209#define DA7210_VERSION "0.0.1" 257#define DA7210_VERSION "0.0.1"
210 258
211/* 259/*
@@ -628,9 +676,12 @@ static const struct snd_soc_dapm_route da7210_audio_map[] = {
628/* Codec private data */ 676/* Codec private data */
629struct da7210_priv { 677struct da7210_priv {
630 struct regmap *regmap; 678 struct regmap *regmap;
679 unsigned int mclk_rate;
680 int master;
631}; 681};
632 682
633static struct reg_default da7210_reg_defaults[] = { 683static struct reg_default da7210_reg_defaults[] = {
684 { 0x00, 0x00 },
634 { 0x01, 0x11 }, 685 { 0x01, 0x11 },
635 { 0x03, 0x00 }, 686 { 0x03, 0x00 },
636 { 0x04, 0x00 }, 687 { 0x04, 0x00 },
@@ -713,10 +764,10 @@ static int da7210_hw_params(struct snd_pcm_substream *substream,
713 struct snd_pcm_hw_params *params, 764 struct snd_pcm_hw_params *params,
714 struct snd_soc_dai *dai) 765 struct snd_soc_dai *dai)
715{ 766{
716 struct snd_soc_pcm_runtime *rtd = substream->private_data; 767 struct snd_soc_codec *codec = dai->codec;
717 struct snd_soc_codec *codec = rtd->codec; 768 struct da7210_priv *da7210 = snd_soc_codec_get_drvdata(codec);
718 u32 dai_cfg1; 769 u32 dai_cfg1;
719 u32 fs, bypass; 770 u32 fs, sysclk;
720 771
721 /* set DAI source to Left and Right ADC */ 772 /* set DAI source to Left and Right ADC */
722 snd_soc_write(codec, DA7210_DAI_SRC_SEL, 773 snd_soc_write(codec, DA7210_DAI_SRC_SEL,
@@ -749,43 +800,43 @@ static int da7210_hw_params(struct snd_pcm_substream *substream,
749 switch (params_rate(params)) { 800 switch (params_rate(params)) {
750 case 8000: 801 case 8000:
751 fs = DA7210_PLL_FS_8000; 802 fs = DA7210_PLL_FS_8000;
752 bypass = DA7210_PLL_BYP; 803 sysclk = 3072000;
753 break; 804 break;
754 case 11025: 805 case 11025:
755 fs = DA7210_PLL_FS_11025; 806 fs = DA7210_PLL_FS_11025;
756 bypass = 0; 807 sysclk = 2822400;
757 break; 808 break;
758 case 12000: 809 case 12000:
759 fs = DA7210_PLL_FS_12000; 810 fs = DA7210_PLL_FS_12000;
760 bypass = DA7210_PLL_BYP; 811 sysclk = 3072000;
761 break; 812 break;
762 case 16000: 813 case 16000:
763 fs = DA7210_PLL_FS_16000; 814 fs = DA7210_PLL_FS_16000;
764 bypass = DA7210_PLL_BYP; 815 sysclk = 3072000;
765 break; 816 break;
766 case 22050: 817 case 22050:
767 fs = DA7210_PLL_FS_22050; 818 fs = DA7210_PLL_FS_22050;
768 bypass = 0; 819 sysclk = 2822400;
769 break; 820 break;
770 case 32000: 821 case 32000:
771 fs = DA7210_PLL_FS_32000; 822 fs = DA7210_PLL_FS_32000;
772 bypass = DA7210_PLL_BYP; 823 sysclk = 3072000;
773 break; 824 break;
774 case 44100: 825 case 44100:
775 fs = DA7210_PLL_FS_44100; 826 fs = DA7210_PLL_FS_44100;
776 bypass = 0; 827 sysclk = 2822400;
777 break; 828 break;
778 case 48000: 829 case 48000:
779 fs = DA7210_PLL_FS_48000; 830 fs = DA7210_PLL_FS_48000;
780 bypass = DA7210_PLL_BYP; 831 sysclk = 3072000;
781 break; 832 break;
782 case 88200: 833 case 88200:
783 fs = DA7210_PLL_FS_88200; 834 fs = DA7210_PLL_FS_88200;
784 bypass = 0; 835 sysclk = 2822400;
785 break; 836 break;
786 case 96000: 837 case 96000:
787 fs = DA7210_PLL_FS_96000; 838 fs = DA7210_PLL_FS_96000;
788 bypass = DA7210_PLL_BYP; 839 sysclk = 3072000;
789 break; 840 break;
790 default: 841 default:
791 return -EINVAL; 842 return -EINVAL;
@@ -795,8 +846,26 @@ static int da7210_hw_params(struct snd_pcm_substream *substream,
795 snd_soc_update_bits(codec, DA7210_STARTUP1, DA7210_SC_MST_EN, 0); 846 snd_soc_update_bits(codec, DA7210_STARTUP1, DA7210_SC_MST_EN, 0);
796 847
797 snd_soc_update_bits(codec, DA7210_PLL, DA7210_PLL_FS_MASK, fs); 848 snd_soc_update_bits(codec, DA7210_PLL, DA7210_PLL_FS_MASK, fs);
798 snd_soc_update_bits(codec, DA7210_PLL_DIV3, DA7210_PLL_BYP, bypass);
799 849
850 if (da7210->mclk_rate && (da7210->mclk_rate != sysclk)) {
851 /* PLL mode, disable PLL bypass */
852 snd_soc_update_bits(codec, DA7210_PLL_DIV3, DA7210_PLL_BYP, 0);
853
854 if (!da7210->master) {
855 /* PLL slave mode, also enable SRM */
856 snd_soc_update_bits(codec, DA7210_PLL,
857 (DA7210_MCLK_SRM_EN |
858 DA7210_MCLK_DET_EN),
859 (DA7210_MCLK_SRM_EN |
860 DA7210_MCLK_DET_EN));
861 }
862 } else {
863 /* PLL bypass mode, enable PLL bypass and Auto Detection */
864 snd_soc_update_bits(codec, DA7210_PLL, DA7210_MCLK_DET_EN,
865 DA7210_MCLK_DET_EN);
866 snd_soc_update_bits(codec, DA7210_PLL_DIV3, DA7210_PLL_BYP,
867 DA7210_PLL_BYP);
868 }
800 /* Enable active mode */ 869 /* Enable active mode */
801 snd_soc_update_bits(codec, DA7210_STARTUP1, 870 snd_soc_update_bits(codec, DA7210_STARTUP1,
802 DA7210_SC_MST_EN, DA7210_SC_MST_EN); 871 DA7210_SC_MST_EN, DA7210_SC_MST_EN);
@@ -810,17 +879,24 @@ static int da7210_hw_params(struct snd_pcm_substream *substream,
810static int da7210_set_dai_fmt(struct snd_soc_dai *codec_dai, u32 fmt) 879static int da7210_set_dai_fmt(struct snd_soc_dai *codec_dai, u32 fmt)
811{ 880{
812 struct snd_soc_codec *codec = codec_dai->codec; 881 struct snd_soc_codec *codec = codec_dai->codec;
882 struct da7210_priv *da7210 = snd_soc_codec_get_drvdata(codec);
813 u32 dai_cfg1; 883 u32 dai_cfg1;
814 u32 dai_cfg3; 884 u32 dai_cfg3;
815 885
816 dai_cfg1 = 0x7f & snd_soc_read(codec, DA7210_DAI_CFG1); 886 dai_cfg1 = 0x7f & snd_soc_read(codec, DA7210_DAI_CFG1);
817 dai_cfg3 = 0xfc & snd_soc_read(codec, DA7210_DAI_CFG3); 887 dai_cfg3 = 0xfc & snd_soc_read(codec, DA7210_DAI_CFG3);
818 888
889 if ((snd_soc_read(codec, DA7210_PLL) & DA7210_PLL_EN) &&
890 (!(snd_soc_read(codec, DA7210_PLL_DIV3) & DA7210_PLL_BYP)))
891 return -EINVAL;
892
819 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 893 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
820 case SND_SOC_DAIFMT_CBM_CFM: 894 case SND_SOC_DAIFMT_CBM_CFM:
895 da7210->master = 1;
821 dai_cfg1 |= DA7210_DAI_MODE_MASTER; 896 dai_cfg1 |= DA7210_DAI_MODE_MASTER;
822 break; 897 break;
823 case SND_SOC_DAIFMT_CBS_CFS: 898 case SND_SOC_DAIFMT_CBS_CFS:
899 da7210->master = 0;
824 dai_cfg1 |= DA7210_DAI_MODE_SLAVE; 900 dai_cfg1 |= DA7210_DAI_MODE_SLAVE;
825 break; 901 break;
826 default: 902 default:
@@ -872,10 +948,101 @@ static int da7210_mute(struct snd_soc_dai *dai, int mute)
872#define DA7210_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 948#define DA7210_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
873 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 949 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
874 950
951static int da7210_set_dai_sysclk(struct snd_soc_dai *codec_dai,
952 int clk_id, unsigned int freq, int dir)
953{
954 struct snd_soc_codec *codec = codec_dai->codec;
955 struct da7210_priv *da7210 = snd_soc_codec_get_drvdata(codec);
956
957 switch (clk_id) {
958 case DA7210_CLKSRC_MCLK:
959 switch (freq) {
960 case 12000000:
961 case 13000000:
962 case 13500000:
963 case 14400000:
964 case 19200000:
965 case 19680000:
966 case 19800000:
967 da7210->mclk_rate = freq;
968 return 0;
969 default:
970 dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",
971 freq);
972 return -EINVAL;
973 }
974 break;
975 default:
976 dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);
977 return -EINVAL;
978 }
979}
980
981/**
982 * da7210_set_dai_pll :Configure the codec PLL
983 * @param codec_dai : pointer to codec DAI
984 * @param pll_id : da7210 has only one pll, so pll_id is always zero
985 * @param fref : MCLK frequency, should be < 20MHz
986 * @param fout : FsDM value, Refer page 44 & 45 of datasheet
987 * @return int : Zero for success, negative error code for error
988 *
989 * Note: Supported PLL input frequencies are 12MHz, 13MHz, 13.5MHz, 14.4MHz,
990 * 19.2MHz, 19.6MHz and 19.8MHz
991 */
992static int da7210_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
993 int source, unsigned int fref, unsigned int fout)
994{
995 struct snd_soc_codec *codec = codec_dai->codec;
996 struct da7210_priv *da7210 = snd_soc_codec_get_drvdata(codec);
997
998 u8 pll_div1, pll_div2, pll_div3, cnt;
999
1000 /* In slave mode, there is only one set of divisors */
1001 if (!da7210->master)
1002 fout = 2822400;
1003
1004 /* Search pll div array for correct divisors */
1005 for (cnt = 0; cnt < ARRAY_SIZE(da7210_pll_div); cnt++) {
1006 /* check fref, mode and fout */
1007 if ((fref == da7210_pll_div[cnt].fref) &&
1008 (da7210->master == da7210_pll_div[cnt].mode) &&
1009 (fout == da7210_pll_div[cnt].fout)) {
1010 /* all match, pick up divisors */
1011 pll_div1 = da7210_pll_div[cnt].div1;
1012 pll_div2 = da7210_pll_div[cnt].div2;
1013 pll_div3 = da7210_pll_div[cnt].div3;
1014 break;
1015 }
1016 }
1017 if (cnt >= ARRAY_SIZE(da7210_pll_div))
1018 goto err;
1019
1020 /* Disable active mode */
1021 snd_soc_update_bits(codec, DA7210_STARTUP1, DA7210_SC_MST_EN, 0);
1022 /* Write PLL dividers */
1023 snd_soc_write(codec, DA7210_PLL_DIV1, pll_div1);
1024 snd_soc_write(codec, DA7210_PLL_DIV2, pll_div2);
1025 snd_soc_update_bits(codec, DA7210_PLL_DIV3,
1026 DA7210_PLL_DIV_L_MASK, pll_div3);
1027
1028 /* Enable PLL */
1029 snd_soc_update_bits(codec, DA7210_PLL, DA7210_PLL_EN, DA7210_PLL_EN);
1030
1031 /* Enable active mode */
1032 snd_soc_update_bits(codec, DA7210_STARTUP1, DA7210_SC_MST_EN,
1033 DA7210_SC_MST_EN);
1034 return 0;
1035err:
1036 dev_err(codec_dai->dev, "Unsupported PLL input frequency %d\n", fref);
1037 return -EINVAL;
1038}
1039
875/* DAI operations */ 1040/* DAI operations */
876static const struct snd_soc_dai_ops da7210_dai_ops = { 1041static const struct snd_soc_dai_ops da7210_dai_ops = {
877 .hw_params = da7210_hw_params, 1042 .hw_params = da7210_hw_params,
878 .set_fmt = da7210_set_dai_fmt, 1043 .set_fmt = da7210_set_dai_fmt,
1044 .set_sysclk = da7210_set_dai_sysclk,
1045 .set_pll = da7210_set_dai_pll,
879 .digital_mute = da7210_mute, 1046 .digital_mute = da7210_mute,
880}; 1047};
881 1048
@@ -915,24 +1082,11 @@ static int da7210_probe(struct snd_soc_codec *codec)
915 return ret; 1082 return ret;
916 } 1083 }
917 1084
918 /* FIXME 1085 da7210->mclk_rate = 0; /* This will be set from set_sysclk() */
919 * 1086 da7210->master = 0; /* This will be set from set_fmt() */
920 * This driver use fixed value here
921 * And below settings expects MCLK = 12.288MHz
922 *
923 * When you select different MCLK, please check...
924 * DA7210_PLL_DIV1 val
925 * DA7210_PLL_DIV2 val
926 * DA7210_PLL_DIV3 val
927 * DA7210_PLL_DIV3 :: DA7210_MCLK_RANGExxx
928 */
929 1087
930 /* 1088 /* Enable internal regulator & bias current */
931 * make sure that DA7210 use bypass mode before start up 1089 snd_soc_write(codec, DA7210_CONTROL, DA7210_REG_EN | DA7210_BIAS_EN);
932 */
933 snd_soc_write(codec, DA7210_STARTUP1, 0);
934 snd_soc_write(codec, DA7210_PLL_DIV3,
935 DA7210_MCLK_RANGE_10_20_MHZ | DA7210_PLL_BYP);
936 1090
937 /* 1091 /*
938 * ADC settings 1092 * ADC settings
@@ -1007,34 +1161,13 @@ static int da7210_probe(struct snd_soc_codec *codec)
1007 /* Enable Aux2 */ 1161 /* Enable Aux2 */
1008 snd_soc_write(codec, DA7210_AUX2, DA7210_AUX2_EN); 1162 snd_soc_write(codec, DA7210_AUX2, DA7210_AUX2_EN);
1009 1163
1164 /* Set PLL Master clock range 10-20 MHz, enable PLL bypass */
1165 snd_soc_write(codec, DA7210_PLL_DIV3, DA7210_MCLK_RANGE_10_20_MHZ |
1166 DA7210_PLL_BYP);
1167
1010 /* Diable PLL and bypass it */ 1168 /* Diable PLL and bypass it */
1011 snd_soc_write(codec, DA7210_PLL, DA7210_PLL_FS_48000); 1169 snd_soc_write(codec, DA7210_PLL, DA7210_PLL_FS_48000);
1012 1170
1013 /*
1014 * If 48kHz sound came, it use bypass mode,
1015 * and when it is 44.1kHz, it use PLL.
1016 *
1017 * This time, this driver sets PLL always ON
1018 * and controls bypass/PLL mode by switching
1019 * DA7210_PLL_DIV3 :: DA7210_PLL_BYP bit.
1020 * see da7210_hw_params
1021 */
1022 snd_soc_write(codec, DA7210_PLL_DIV1, 0xE5); /* MCLK = 12.288MHz */
1023 snd_soc_write(codec, DA7210_PLL_DIV2, 0x99);
1024 snd_soc_write(codec, DA7210_PLL_DIV3, 0x0A |
1025 DA7210_MCLK_RANGE_10_20_MHZ | DA7210_PLL_BYP);
1026 snd_soc_update_bits(codec, DA7210_PLL, DA7210_PLL_EN, DA7210_PLL_EN);
1027
1028 /* As suggested by Dialog */
1029 /* unlock */
1030 regmap_write(da7210->regmap, DA7210_A_HID_UNLOCK, 0x8B);
1031 regmap_write(da7210->regmap, DA7210_A_TEST_UNLOCK, 0xB4);
1032 regmap_write(da7210->regmap, DA7210_A_PLL1, 0x01);
1033 regmap_write(da7210->regmap, DA7210_A_CP_MODE, 0x7C);
1034 /* re-lock */
1035 regmap_write(da7210->regmap, DA7210_A_HID_UNLOCK, 0x00);
1036 regmap_write(da7210->regmap, DA7210_A_TEST_UNLOCK, 0x00);
1037
1038 /* Activate all enabled subsystem */ 1171 /* Activate all enabled subsystem */
1039 snd_soc_write(codec, DA7210_STARTUP1, DA7210_SC_MST_EN); 1172 snd_soc_write(codec, DA7210_STARTUP1, DA7210_SC_MST_EN);
1040 1173
@@ -1055,7 +1188,26 @@ static struct snd_soc_codec_driver soc_codec_dev_da7210 = {
1055 .num_dapm_routes = ARRAY_SIZE(da7210_audio_map), 1188 .num_dapm_routes = ARRAY_SIZE(da7210_audio_map),
1056}; 1189};
1057 1190
1058static struct regmap_config da7210_regmap = { 1191#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1192
1193static struct reg_default da7210_regmap_i2c_patch[] = {
1194
1195 /* System controller master disable */
1196 { DA7210_STARTUP1, 0x00 },
1197 /* Set PLL Master clock range 10-20 MHz */
1198 { DA7210_PLL_DIV3, DA7210_MCLK_RANGE_10_20_MHZ },
1199
1200 /* to unlock */
1201 { DA7210_A_HID_UNLOCK, 0x8B},
1202 { DA7210_A_TEST_UNLOCK, 0xB4},
1203 { DA7210_A_PLL1, 0x01},
1204 { DA7210_A_CP_MODE, 0x7C},
1205 /* to re-lock */
1206 { DA7210_A_HID_UNLOCK, 0x00},
1207 { DA7210_A_TEST_UNLOCK, 0x00},
1208};
1209
1210static const struct regmap_config da7210_regmap_config_i2c = {
1059 .reg_bits = 8, 1211 .reg_bits = 8,
1060 .val_bits = 8, 1212 .val_bits = 8,
1061 1213
@@ -1066,7 +1218,6 @@ static struct regmap_config da7210_regmap = {
1066 .cache_type = REGCACHE_RBTREE, 1218 .cache_type = REGCACHE_RBTREE,
1067}; 1219};
1068 1220
1069#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1070static int __devinit da7210_i2c_probe(struct i2c_client *i2c, 1221static int __devinit da7210_i2c_probe(struct i2c_client *i2c,
1071 const struct i2c_device_id *id) 1222 const struct i2c_device_id *id)
1072{ 1223{
@@ -1080,13 +1231,18 @@ static int __devinit da7210_i2c_probe(struct i2c_client *i2c,
1080 1231
1081 i2c_set_clientdata(i2c, da7210); 1232 i2c_set_clientdata(i2c, da7210);
1082 1233
1083 da7210->regmap = regmap_init_i2c(i2c, &da7210_regmap); 1234 da7210->regmap = regmap_init_i2c(i2c, &da7210_regmap_config_i2c);
1084 if (IS_ERR(da7210->regmap)) { 1235 if (IS_ERR(da7210->regmap)) {
1085 ret = PTR_ERR(da7210->regmap); 1236 ret = PTR_ERR(da7210->regmap);
1086 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret); 1237 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
1087 return ret; 1238 return ret;
1088 } 1239 }
1089 1240
1241 ret = regmap_register_patch(da7210->regmap, da7210_regmap_i2c_patch,
1242 ARRAY_SIZE(da7210_regmap_i2c_patch));
1243 if (ret != 0)
1244 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1245
1090 ret = snd_soc_register_codec(&i2c->dev, 1246 ret = snd_soc_register_codec(&i2c->dev,
1091 &soc_codec_dev_da7210, &da7210_dai, 1); 1247 &soc_codec_dev_da7210, &da7210_dai, 1);
1092 if (ret < 0) { 1248 if (ret < 0) {
@@ -1119,7 +1275,7 @@ MODULE_DEVICE_TABLE(i2c, da7210_i2c_id);
1119/* I2C codec control layer */ 1275/* I2C codec control layer */
1120static struct i2c_driver da7210_i2c_driver = { 1276static struct i2c_driver da7210_i2c_driver = {
1121 .driver = { 1277 .driver = {
1122 .name = "da7210-codec", 1278 .name = "da7210",
1123 .owner = THIS_MODULE, 1279 .owner = THIS_MODULE,
1124 }, 1280 },
1125 .probe = da7210_i2c_probe, 1281 .probe = da7210_i2c_probe,
@@ -1128,12 +1284,112 @@ static struct i2c_driver da7210_i2c_driver = {
1128}; 1284};
1129#endif 1285#endif
1130 1286
1287#if defined(CONFIG_SPI_MASTER)
1288
1289static struct reg_default da7210_regmap_spi_patch[] = {
1290 /* Dummy read to give two pulses over nCS for SPI */
1291 { DA7210_AUX2, 0x00 },
1292 { DA7210_AUX2, 0x00 },
1293
1294 /* System controller master disable */
1295 { DA7210_STARTUP1, 0x00 },
1296 /* Set PLL Master clock range 10-20 MHz */
1297 { DA7210_PLL_DIV3, DA7210_MCLK_RANGE_10_20_MHZ },
1298
1299 /* to set PAGE1 of SPI register space */
1300 { DA7210_PAGE_CONTROL, 0x80 },
1301 /* to unlock */
1302 { DA7210_A_HID_UNLOCK, 0x8B},
1303 { DA7210_A_TEST_UNLOCK, 0xB4},
1304 { DA7210_A_PLL1, 0x01},
1305 { DA7210_A_CP_MODE, 0x7C},
1306 /* to re-lock */
1307 { DA7210_A_HID_UNLOCK, 0x00},
1308 { DA7210_A_TEST_UNLOCK, 0x00},
1309 /* to set back PAGE0 of SPI register space */
1310 { DA7210_PAGE_CONTROL, 0x00 },
1311};
1312
1313static const struct regmap_config da7210_regmap_config_spi = {
1314 .reg_bits = 8,
1315 .val_bits = 8,
1316 .read_flag_mask = 0x01,
1317 .write_flag_mask = 0x00,
1318
1319 .reg_defaults = da7210_reg_defaults,
1320 .num_reg_defaults = ARRAY_SIZE(da7210_reg_defaults),
1321 .volatile_reg = da7210_volatile_register,
1322 .readable_reg = da7210_readable_register,
1323 .cache_type = REGCACHE_RBTREE,
1324};
1325
1326static int __devinit da7210_spi_probe(struct spi_device *spi)
1327{
1328 struct da7210_priv *da7210;
1329 int ret;
1330
1331 da7210 = devm_kzalloc(&spi->dev, sizeof(struct da7210_priv),
1332 GFP_KERNEL);
1333 if (!da7210)
1334 return -ENOMEM;
1335
1336 spi_set_drvdata(spi, da7210);
1337 da7210->regmap = devm_regmap_init_spi(spi, &da7210_regmap_config_spi);
1338 if (IS_ERR(da7210->regmap)) {
1339 ret = PTR_ERR(da7210->regmap);
1340 dev_err(&spi->dev, "Failed to register regmap: %d\n", ret);
1341 return ret;
1342 }
1343
1344 ret = regmap_register_patch(da7210->regmap, da7210_regmap_spi_patch,
1345 ARRAY_SIZE(da7210_regmap_spi_patch));
1346 if (ret != 0)
1347 dev_warn(&spi->dev, "Failed to apply regmap patch: %d\n", ret);
1348
1349 ret = snd_soc_register_codec(&spi->dev,
1350 &soc_codec_dev_da7210, &da7210_dai, 1);
1351 if (ret < 0)
1352 goto err_regmap;
1353
1354 return ret;
1355
1356err_regmap:
1357 regmap_exit(da7210->regmap);
1358
1359 return ret;
1360}
1361
1362static int __devexit da7210_spi_remove(struct spi_device *spi)
1363{
1364 struct da7210_priv *da7210 = spi_get_drvdata(spi);
1365 snd_soc_unregister_codec(&spi->dev);
1366 regmap_exit(da7210->regmap);
1367 return 0;
1368}
1369
1370static struct spi_driver da7210_spi_driver = {
1371 .driver = {
1372 .name = "da7210",
1373 .owner = THIS_MODULE,
1374 },
1375 .probe = da7210_spi_probe,
1376 .remove = __devexit_p(da7210_spi_remove)
1377};
1378#endif
1379
1131static int __init da7210_modinit(void) 1380static int __init da7210_modinit(void)
1132{ 1381{
1133 int ret = 0; 1382 int ret = 0;
1134#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1383#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1135 ret = i2c_add_driver(&da7210_i2c_driver); 1384 ret = i2c_add_driver(&da7210_i2c_driver);
1136#endif 1385#endif
1386#if defined(CONFIG_SPI_MASTER)
1387 ret = spi_register_driver(&da7210_spi_driver);
1388 if (ret) {
1389 printk(KERN_ERR "Failed to register da7210 SPI driver: %d\n",
1390 ret);
1391 }
1392#endif
1137 return ret; 1393 return ret;
1138} 1394}
1139module_init(da7210_modinit); 1395module_init(da7210_modinit);
@@ -1143,6 +1399,9 @@ static void __exit da7210_exit(void)
1143#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1399#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1144 i2c_del_driver(&da7210_i2c_driver); 1400 i2c_del_driver(&da7210_i2c_driver);
1145#endif 1401#endif
1402#if defined(CONFIG_SPI_MASTER)
1403 spi_unregister_driver(&da7210_spi_driver);
1404#endif
1146} 1405}
1147module_exit(da7210_exit); 1406module_exit(da7210_exit);
1148 1407
diff --git a/sound/soc/codecs/jz4740.c b/sound/soc/codecs/jz4740.c
index 4624e752a188..85d9cabe6d55 100644
--- a/sound/soc/codecs/jz4740.c
+++ b/sound/soc/codecs/jz4740.c
@@ -164,8 +164,7 @@ static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
164 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 164 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
165{ 165{
166 uint32_t val; 166 uint32_t val;
167 struct snd_soc_pcm_runtime *rtd = substream->private_data; 167 struct snd_soc_codec *codec = dai->codec;
168 struct snd_soc_codec *codec =rtd->codec;
169 168
170 switch (params_rate(params)) { 169 switch (params_rate(params)) {
171 case 8000: 170 case 8000:
diff --git a/sound/soc/codecs/lm49453.c b/sound/soc/codecs/lm49453.c
new file mode 100644
index 000000000000..802b9f176b16
--- /dev/null
+++ b/sound/soc/codecs/lm49453.c
@@ -0,0 +1,1550 @@
1/*
2 * lm49453.c - LM49453 ALSA Soc Audio driver
3 *
4 * Copyright (c) 2012 Texas Instruments, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * Initially based on sound/soc/codecs/wm8350.c
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/version.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/regmap.h>
22#include <linux/slab.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/tlv.h>
29#include <sound/jack.h>
30#include <sound/initval.h>
31#include <asm/div64.h>
32#include "lm49453.h"
33
34static struct reg_default lm49453_reg_defs[] = {
35 { 0, 0x00 },
36 { 1, 0x00 },
37 { 2, 0x00 },
38 { 3, 0x00 },
39 { 4, 0x00 },
40 { 5, 0x00 },
41 { 6, 0x00 },
42 { 7, 0x00 },
43 { 8, 0x00 },
44 { 9, 0x00 },
45 { 10, 0x00 },
46 { 11, 0x00 },
47 { 12, 0x00 },
48 { 13, 0x00 },
49 { 14, 0x00 },
50 { 15, 0x00 },
51 { 16, 0x00 },
52 { 17, 0x00 },
53 { 18, 0x00 },
54 { 19, 0x00 },
55 { 20, 0x00 },
56 { 21, 0x00 },
57 { 22, 0x00 },
58 { 23, 0x00 },
59 { 32, 0x00 },
60 { 33, 0x00 },
61 { 35, 0x00 },
62 { 36, 0x00 },
63 { 37, 0x00 },
64 { 46, 0x00 },
65 { 48, 0x00 },
66 { 49, 0x00 },
67 { 51, 0x00 },
68 { 56, 0x00 },
69 { 58, 0x00 },
70 { 59, 0x00 },
71 { 60, 0x00 },
72 { 61, 0x00 },
73 { 62, 0x00 },
74 { 63, 0x00 },
75 { 64, 0x00 },
76 { 65, 0x00 },
77 { 66, 0x00 },
78 { 67, 0x00 },
79 { 68, 0x00 },
80 { 69, 0x00 },
81 { 70, 0x00 },
82 { 71, 0x00 },
83 { 72, 0x00 },
84 { 73, 0x00 },
85 { 74, 0x00 },
86 { 75, 0x00 },
87 { 76, 0x00 },
88 { 77, 0x00 },
89 { 78, 0x00 },
90 { 79, 0x00 },
91 { 80, 0x00 },
92 { 81, 0x00 },
93 { 82, 0x00 },
94 { 83, 0x00 },
95 { 85, 0x00 },
96 { 85, 0x00 },
97 { 86, 0x00 },
98 { 87, 0x00 },
99 { 88, 0x00 },
100 { 89, 0x00 },
101 { 90, 0x00 },
102 { 91, 0x00 },
103 { 92, 0x00 },
104 { 93, 0x00 },
105 { 94, 0x00 },
106 { 95, 0x00 },
107 { 96, 0x01 },
108 { 97, 0x00 },
109 { 98, 0x00 },
110 { 99, 0x00 },
111 { 100, 0x00 },
112 { 101, 0x00 },
113 { 102, 0x00 },
114 { 103, 0x01 },
115 { 105, 0x01 },
116 { 106, 0x00 },
117 { 107, 0x01 },
118 { 107, 0x00 },
119 { 108, 0x00 },
120 { 109, 0x00 },
121 { 110, 0x00 },
122 { 111, 0x02 },
123 { 112, 0x02 },
124 { 113, 0x00 },
125 { 121, 0x80 },
126 { 122, 0xBB },
127 { 123, 0x80 },
128 { 124, 0xBB },
129 { 128, 0x00 },
130 { 130, 0x00 },
131 { 131, 0x00 },
132 { 132, 0x00 },
133 { 133, 0x0A },
134 { 134, 0x0A },
135 { 135, 0x0A },
136 { 136, 0x0F },
137 { 137, 0x00 },
138 { 138, 0x73 },
139 { 139, 0x33 },
140 { 140, 0x73 },
141 { 141, 0x33 },
142 { 142, 0x73 },
143 { 143, 0x33 },
144 { 144, 0x73 },
145 { 145, 0x33 },
146 { 146, 0x73 },
147 { 147, 0x33 },
148 { 148, 0x73 },
149 { 149, 0x33 },
150 { 150, 0x73 },
151 { 151, 0x33 },
152 { 152, 0x00 },
153 { 153, 0x00 },
154 { 154, 0x00 },
155 { 155, 0x00 },
156 { 176, 0x00 },
157 { 177, 0x00 },
158 { 178, 0x00 },
159 { 179, 0x00 },
160 { 180, 0x00 },
161 { 181, 0x00 },
162 { 182, 0x00 },
163 { 183, 0x00 },
164 { 184, 0x00 },
165 { 185, 0x00 },
166 { 186, 0x00 },
167 { 189, 0x00 },
168 { 188, 0x00 },
169 { 194, 0x00 },
170 { 195, 0x00 },
171 { 196, 0x00 },
172 { 197, 0x00 },
173 { 200, 0x00 },
174 { 201, 0x00 },
175 { 202, 0x00 },
176 { 203, 0x00 },
177 { 204, 0x00 },
178 { 205, 0x00 },
179 { 208, 0x00 },
180 { 209, 0x00 },
181 { 210, 0x00 },
182 { 211, 0x00 },
183 { 213, 0x00 },
184 { 214, 0x00 },
185 { 215, 0x00 },
186 { 216, 0x00 },
187 { 217, 0x00 },
188 { 218, 0x00 },
189 { 219, 0x00 },
190 { 221, 0x00 },
191 { 222, 0x00 },
192 { 224, 0x00 },
193 { 225, 0x00 },
194 { 226, 0x00 },
195 { 227, 0x00 },
196 { 228, 0x00 },
197 { 229, 0x00 },
198 { 230, 0x13 },
199 { 231, 0x00 },
200 { 232, 0x80 },
201 { 233, 0x0C },
202 { 234, 0xDD },
203 { 235, 0x00 },
204 { 236, 0x04 },
205 { 237, 0x00 },
206 { 238, 0x00 },
207 { 239, 0x00 },
208 { 240, 0x00 },
209 { 241, 0x00 },
210 { 242, 0x00 },
211 { 243, 0x00 },
212 { 244, 0x00 },
213 { 245, 0x00 },
214 { 248, 0x00 },
215 { 249, 0x00 },
216 { 254, 0x00 },
217 { 255, 0x00 },
218};
219
220/* codec private data */
221struct lm49453_priv {
222 struct regmap *regmap;
223 int fs_rate;
224};
225
226/* capture path controls */
227
228static const char *lm49453_mic2mode_text[] = {"Single Ended", "Differential"};
229
230static const SOC_ENUM_SINGLE_DECL(lm49453_mic2mode_enum, LM49453_P0_MICR_REG, 5,
231 lm49453_mic2mode_text);
232
233static const char *lm49453_dmic_cfg_text[] = {"DMICDAT1", "DMICDAT2"};
234
235static const SOC_ENUM_SINGLE_DECL(lm49453_dmic12_cfg_enum,
236 LM49453_P0_DIGITAL_MIC1_CONFIG_REG,
237 7, lm49453_dmic_cfg_text);
238
239static const SOC_ENUM_SINGLE_DECL(lm49453_dmic34_cfg_enum,
240 LM49453_P0_DIGITAL_MIC2_CONFIG_REG,
241 7, lm49453_dmic_cfg_text);
242
243/* MUX Controls */
244static const char *lm49453_adcl_mux_text[] = { "MIC1", "Aux_L" };
245
246static const char *lm49453_adcr_mux_text[] = { "MIC2", "Aux_R" };
247
248static const struct soc_enum lm49453_adcl_enum =
249 SOC_ENUM_SINGLE(LM49453_P0_ANALOG_MIXER_ADC_REG, 0,
250 ARRAY_SIZE(lm49453_adcl_mux_text),
251 lm49453_adcl_mux_text);
252
253static const struct soc_enum lm49453_adcr_enum =
254 SOC_ENUM_SINGLE(LM49453_P0_ANALOG_MIXER_ADC_REG, 1,
255 ARRAY_SIZE(lm49453_adcr_mux_text),
256 lm49453_adcr_mux_text);
257
258static const struct snd_kcontrol_new lm49453_adcl_mux_control =
259 SOC_DAPM_ENUM("ADC Left Mux", lm49453_adcl_enum);
260
261static const struct snd_kcontrol_new lm49453_adcr_mux_control =
262 SOC_DAPM_ENUM("ADC Right Mux", lm49453_adcr_enum);
263
264static const struct snd_kcontrol_new lm49453_headset_left_mixer[] = {
265SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPL1_REG, 0, 1, 0),
266SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPL1_REG, 1, 1, 0),
267SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPL1_REG, 2, 1, 0),
268SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPL1_REG, 3, 1, 0),
269SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPL1_REG, 4, 1, 0),
270SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPL1_REG, 5, 1, 0),
271SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPL1_REG, 6, 1, 0),
272SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPL1_REG, 7, 1, 0),
273SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPL2_REG, 0, 1, 0),
274SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPL2_REG, 1, 1, 0),
275SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPL2_REG, 2, 1, 0),
276SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPL2_REG, 3, 1, 0),
277SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPL2_REG, 4, 1, 0),
278SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPL2_REG, 5, 1, 0),
279SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPL2_REG, 6, 1, 0),
280SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPL2_REG, 7, 1, 0),
281SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 0, 0, 0),
282};
283
284static const struct snd_kcontrol_new lm49453_headset_right_mixer[] = {
285SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPR1_REG, 0, 1, 0),
286SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPR1_REG, 1, 1, 0),
287SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPR1_REG, 2, 1, 0),
288SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPR1_REG, 3, 1, 0),
289SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPR1_REG, 4, 1, 0),
290SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPR1_REG, 5, 1, 0),
291SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPR1_REG, 6, 1, 0),
292SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPR1_REG, 7, 1, 0),
293SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPR2_REG, 0, 1, 0),
294SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPR2_REG, 1, 1, 0),
295SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPR2_REG, 2, 1, 0),
296SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPR2_REG, 3, 1, 0),
297SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPR2_REG, 4, 1, 0),
298SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPR2_REG, 5, 1, 0),
299SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPR2_REG, 6, 1, 0),
300SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPR2_REG, 7, 1, 0),
301SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 1, 0, 0),
302};
303
304static const struct snd_kcontrol_new lm49453_speaker_left_mixer[] = {
305SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSL1_REG, 0, 1, 0),
306SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSL1_REG, 1, 1, 0),
307SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSL1_REG, 2, 1, 0),
308SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSL1_REG, 3, 1, 0),
309SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSL1_REG, 4, 1, 0),
310SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSL1_REG, 5, 1, 0),
311SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSL1_REG, 6, 1, 0),
312SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSL1_REG, 7, 1, 0),
313SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSL2_REG, 0, 1, 0),
314SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSL2_REG, 1, 1, 0),
315SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSL2_REG, 2, 1, 0),
316SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSL2_REG, 3, 1, 0),
317SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSL2_REG, 4, 1, 0),
318SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSL2_REG, 5, 1, 0),
319SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSL2_REG, 6, 1, 0),
320SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSL2_REG, 7, 1, 0),
321SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 2, 0, 0),
322};
323
324static const struct snd_kcontrol_new lm49453_speaker_right_mixer[] = {
325SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSR1_REG, 0, 1, 0),
326SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSR1_REG, 1, 1, 0),
327SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSR1_REG, 2, 1, 0),
328SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSR1_REG, 3, 1, 0),
329SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSR1_REG, 4, 1, 0),
330SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSR1_REG, 5, 1, 0),
331SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSR1_REG, 6, 1, 0),
332SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSR1_REG, 7, 1, 0),
333SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSR2_REG, 0, 1, 0),
334SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSR2_REG, 1, 1, 0),
335SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSR2_REG, 2, 1, 0),
336SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSR2_REG, 3, 1, 0),
337SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSR2_REG, 4, 1, 0),
338SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSR2_REG, 5, 1, 0),
339SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSR2_REG, 6, 1, 0),
340SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSR2_REG, 7, 1, 0),
341SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 3, 0, 0),
342};
343
344static const struct snd_kcontrol_new lm49453_haptic_left_mixer[] = {
345SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAL1_REG, 0, 1, 0),
346SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAL1_REG, 1, 1, 0),
347SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAL1_REG, 2, 1, 0),
348SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAL1_REG, 3, 1, 0),
349SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAL1_REG, 4, 1, 0),
350SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAL1_REG, 5, 1, 0),
351SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAL1_REG, 6, 1, 0),
352SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAL1_REG, 7, 1, 0),
353SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAL2_REG, 0, 1, 0),
354SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAL2_REG, 1, 1, 0),
355SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAL2_REG, 2, 1, 0),
356SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAL2_REG, 3, 1, 0),
357SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAL2_REG, 4, 1, 0),
358SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAL2_REG, 5, 1, 0),
359SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAL2_REG, 6, 1, 0),
360SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAL2_REG, 7, 1, 0),
361SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 4, 0, 0),
362};
363
364static const struct snd_kcontrol_new lm49453_haptic_right_mixer[] = {
365SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAR1_REG, 0, 1, 0),
366SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAR1_REG, 1, 1, 0),
367SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAR1_REG, 2, 1, 0),
368SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAR1_REG, 3, 1, 0),
369SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAR1_REG, 4, 1, 0),
370SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAR1_REG, 5, 1, 0),
371SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAR1_REG, 6, 1, 0),
372SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAR1_REG, 7, 1, 0),
373SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAR2_REG, 0, 1, 0),
374SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAR2_REG, 1, 1, 0),
375SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAR2_REG, 2, 1, 0),
376SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAR2_REG, 3, 1, 0),
377SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAR2_REG, 4, 1, 0),
378SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAR2_REG, 5, 1, 0),
379SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAR2_REG, 6, 1, 0),
380SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAR2_REG, 7, 1, 0),
381SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 5, 0, 0),
382};
383
384static const struct snd_kcontrol_new lm49453_lineout_left_mixer[] = {
385SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOL1_REG, 0, 1, 0),
386SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOL1_REG, 1, 1, 0),
387SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOL1_REG, 2, 1, 0),
388SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOL1_REG, 3, 1, 0),
389SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOL1_REG, 4, 1, 0),
390SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOL1_REG, 5, 1, 0),
391SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOL1_REG, 6, 1, 0),
392SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOL1_REG, 7, 1, 0),
393SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOL2_REG, 0, 1, 0),
394SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOL2_REG, 1, 1, 0),
395SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOL2_REG, 2, 1, 0),
396SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOL2_REG, 3, 1, 0),
397SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOL2_REG, 4, 1, 0),
398SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOL2_REG, 5, 1, 0),
399SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOL2_REG, 6, 1, 0),
400SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOL2_REG, 7, 1, 0),
401SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 6, 0, 0),
402};
403
404static const struct snd_kcontrol_new lm49453_lineout_right_mixer[] = {
405SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOR1_REG, 0, 1, 0),
406SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOR1_REG, 1, 1, 0),
407SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOR1_REG, 2, 1, 0),
408SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOR1_REG, 3, 1, 0),
409SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOR1_REG, 4, 1, 0),
410SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOR1_REG, 5, 1, 0),
411SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOR1_REG, 6, 1, 0),
412SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOR1_REG, 7, 1, 0),
413SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOR2_REG, 0, 1, 0),
414SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOR2_REG, 1, 1, 0),
415SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOR2_REG, 2, 1, 0),
416SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOR2_REG, 3, 1, 0),
417SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOR2_REG, 4, 1, 0),
418SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOR2_REG, 5, 1, 0),
419SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOR2_REG, 6, 1, 0),
420SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOR2_REG, 7, 1, 0),
421SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 7, 0, 0),
422};
423
424static const struct snd_kcontrol_new lm49453_port1_tx1_mixer[] = {
425SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX1_REG, 0, 1, 0),
426SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX1_REG, 1, 1, 0),
427SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX1_REG, 2, 1, 0),
428SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX1_REG, 3, 1, 0),
429SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX1_REG, 4, 1, 0),
430SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX1_REG, 5, 1, 0),
431SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT1_TX1_REG, 6, 1, 0),
432SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT1_TX1_REG, 7, 1, 0),
433};
434
435static const struct snd_kcontrol_new lm49453_port1_tx2_mixer[] = {
436SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX2_REG, 0, 1, 0),
437SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX2_REG, 1, 1, 0),
438SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX2_REG, 2, 1, 0),
439SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX2_REG, 3, 1, 0),
440SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX2_REG, 4, 1, 0),
441SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX2_REG, 5, 1, 0),
442SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT1_TX2_REG, 6, 1, 0),
443SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT1_TX2_REG, 7, 1, 0),
444};
445
446static const struct snd_kcontrol_new lm49453_port1_tx3_mixer[] = {
447SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX3_REG, 0, 1, 0),
448SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX3_REG, 1, 1, 0),
449SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX3_REG, 2, 1, 0),
450SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX3_REG, 3, 1, 0),
451SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX3_REG, 4, 1, 0),
452SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX3_REG, 5, 1, 0),
453SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_PORT1_TX3_REG, 6, 1, 0),
454};
455
456static const struct snd_kcontrol_new lm49453_port1_tx4_mixer[] = {
457SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX4_REG, 0, 1, 0),
458SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX4_REG, 1, 1, 0),
459SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX4_REG, 2, 1, 0),
460SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX4_REG, 3, 1, 0),
461SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX4_REG, 4, 1, 0),
462SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX4_REG, 5, 1, 0),
463SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_PORT1_TX4_REG, 6, 1, 0),
464};
465
466static const struct snd_kcontrol_new lm49453_port1_tx5_mixer[] = {
467SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX5_REG, 0, 1, 0),
468SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX5_REG, 1, 1, 0),
469SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX5_REG, 2, 1, 0),
470SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX5_REG, 3, 1, 0),
471SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX5_REG, 4, 1, 0),
472SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX5_REG, 5, 1, 0),
473SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_PORT1_TX5_REG, 6, 1, 0),
474};
475
476static const struct snd_kcontrol_new lm49453_port1_tx6_mixer[] = {
477SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX6_REG, 0, 1, 0),
478SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX6_REG, 1, 1, 0),
479SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX6_REG, 2, 1, 0),
480SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX6_REG, 3, 1, 0),
481SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX6_REG, 4, 1, 0),
482SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX6_REG, 5, 1, 0),
483SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_PORT1_TX6_REG, 6, 1, 0),
484};
485
486static const struct snd_kcontrol_new lm49453_port1_tx7_mixer[] = {
487SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX7_REG, 0, 1, 0),
488SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX7_REG, 1, 1, 0),
489SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX7_REG, 2, 1, 0),
490SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX7_REG, 3, 1, 0),
491SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX7_REG, 4, 1, 0),
492SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX7_REG, 5, 1, 0),
493SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_PORT1_TX7_REG, 6, 1, 0),
494};
495
496static const struct snd_kcontrol_new lm49453_port1_tx8_mixer[] = {
497SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX8_REG, 0, 1, 0),
498SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX8_REG, 1, 1, 0),
499SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX8_REG, 2, 1, 0),
500SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX8_REG, 3, 1, 0),
501SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX8_REG, 4, 1, 0),
502SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX8_REG, 5, 1, 0),
503SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_PORT1_TX8_REG, 6, 1, 0),
504};
505
506static const struct snd_kcontrol_new lm49453_port2_tx1_mixer[] = {
507SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX1_REG, 0, 1, 0),
508SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX1_REG, 1, 1, 0),
509SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX1_REG, 2, 1, 0),
510SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX1_REG, 3, 1, 0),
511SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX1_REG, 4, 1, 0),
512SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX1_REG, 5, 1, 0),
513SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT2_TX1_REG, 6, 1, 0),
514SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT2_TX1_REG, 7, 1, 0),
515};
516
517static const struct snd_kcontrol_new lm49453_port2_tx2_mixer[] = {
518SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX2_REG, 0, 1, 0),
519SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX2_REG, 1, 1, 0),
520SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX2_REG, 2, 1, 0),
521SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX2_REG, 3, 1, 0),
522SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX2_REG, 4, 1, 0),
523SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX2_REG, 5, 1, 0),
524SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT2_TX2_REG, 6, 1, 0),
525SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT2_TX2_REG, 7, 1, 0),
526};
527
528/* TLV Declarations */
529static const DECLARE_TLV_DB_SCALE(digital_tlv, -7650, 150, 1);
530static const DECLARE_TLV_DB_SCALE(port_tlv, 0, 600, 0);
531
532static const struct snd_kcontrol_new lm49453_sidetone_mixer_controls[] = {
533/* Sidetone supports mono only */
534SOC_DAPM_SINGLE_TLV("Sidetone ADCL Volume", LM49453_P0_STN_VOL_ADCL_REG,
535 0, 0x3F, 0, digital_tlv),
536SOC_DAPM_SINGLE_TLV("Sidetone ADCR Volume", LM49453_P0_STN_VOL_ADCR_REG,
537 0, 0x3F, 0, digital_tlv),
538SOC_DAPM_SINGLE_TLV("Sidetone DMIC1L Volume", LM49453_P0_STN_VOL_DMIC1L_REG,
539 0, 0x3F, 0, digital_tlv),
540SOC_DAPM_SINGLE_TLV("Sidetone DMIC1R Volume", LM49453_P0_STN_VOL_DMIC1R_REG,
541 0, 0x3F, 0, digital_tlv),
542SOC_DAPM_SINGLE_TLV("Sidetone DMIC2L Volume", LM49453_P0_STN_VOL_DMIC2L_REG,
543 0, 0x3F, 0, digital_tlv),
544SOC_DAPM_SINGLE_TLV("Sidetone DMIC2R Volume", LM49453_P0_STN_VOL_DMIC2R_REG,
545 0, 0x3F, 0, digital_tlv),
546};
547
548static const struct snd_kcontrol_new lm49453_snd_controls[] = {
549 /* mic1 and mic2 supports mono only */
550 SOC_SINGLE_TLV("Mic1 Volume", LM49453_P0_ADC_LEVELL_REG, 0, 6,
551 0, digital_tlv),
552 SOC_SINGLE_TLV("Mic2 Volume", LM49453_P0_ADC_LEVELR_REG, 0, 6,
553 0, digital_tlv),
554
555 SOC_DOUBLE_R_TLV("DMIC1 Volume", LM49453_P0_DMIC1_LEVELL_REG,
556 LM49453_P0_DMIC1_LEVELR_REG, 0, 6, 0, digital_tlv),
557 SOC_DOUBLE_R_TLV("DMIC2 Volume", LM49453_P0_DMIC2_LEVELL_REG,
558 LM49453_P0_DMIC2_LEVELR_REG, 0, 6, 0, digital_tlv),
559
560 SOC_DAPM_ENUM("Mic2Mode", lm49453_mic2mode_enum),
561 SOC_DAPM_ENUM("DMIC12 SRC", lm49453_dmic12_cfg_enum),
562 SOC_DAPM_ENUM("DMIC34 SRC", lm49453_dmic34_cfg_enum),
563
564 /* Capture path filter enable */
565 SOC_SINGLE("DMIC1 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
566 0, 1, 0),
567 SOC_SINGLE("DMIC2 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
568 1, 1, 0),
569 SOC_SINGLE("ADC HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
570 2, 1, 0),
571
572 SOC_DOUBLE_R_TLV("DAC HP Volume", LM49453_P0_DAC_HP_LEVELL_REG,
573 LM49453_P0_DAC_HP_LEVELR_REG, 0, 6, 0, digital_tlv),
574 SOC_DOUBLE_R_TLV("DAC LO Volume", LM49453_P0_DAC_LO_LEVELL_REG,
575 LM49453_P0_DAC_LO_LEVELR_REG, 0, 6, 0, digital_tlv),
576 SOC_DOUBLE_R_TLV("DAC LS Volume", LM49453_P0_DAC_LS_LEVELL_REG,
577 LM49453_P0_DAC_LS_LEVELR_REG, 0, 6, 0, digital_tlv),
578 SOC_DOUBLE_R_TLV("DAC HA Volume", LM49453_P0_DAC_HA_LEVELL_REG,
579 LM49453_P0_DAC_HA_LEVELR_REG, 0, 6, 0, digital_tlv),
580
581 SOC_SINGLE_TLV("EP Volume", LM49453_P0_DAC_LS_LEVELL_REG,
582 0, 6, 0, digital_tlv),
583
584 SOC_SINGLE_TLV("PORT1_1_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
585 0, 3, 0, port_tlv),
586 SOC_SINGLE_TLV("PORT1_2_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
587 2, 3, 0, port_tlv),
588 SOC_SINGLE_TLV("PORT1_3_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
589 4, 3, 0, port_tlv),
590 SOC_SINGLE_TLV("PORT1_4_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
591 6, 3, 0, port_tlv),
592 SOC_SINGLE_TLV("PORT1_5_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
593 0, 3, 0, port_tlv),
594 SOC_SINGLE_TLV("PORT1_6_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
595 2, 3, 0, port_tlv),
596 SOC_SINGLE_TLV("PORT1_7_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
597 4, 3, 0, port_tlv),
598 SOC_SINGLE_TLV("PORT1_8_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
599 6, 3, 0, port_tlv),
600
601 SOC_SINGLE_TLV("PORT2_1_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
602 0, 3, 0, port_tlv),
603 SOC_SINGLE_TLV("PORT2_2_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
604 2, 3, 0, port_tlv),
605
606 SOC_SINGLE("Port1 Playback Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
607 1, 1, 0),
608 SOC_SINGLE("Port2 Playback Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
609 1, 1, 0),
610 SOC_SINGLE("Port1 Capture Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
611 2, 1, 0),
612 SOC_SINGLE("Port2 Capture Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
613 2, 1, 0)
614
615};
616
617/* DAPM widgets */
618static const struct snd_soc_dapm_widget lm49453_dapm_widgets[] = {
619
620 /* All end points HP,EP, LS, Lineout and Haptic */
621 SND_SOC_DAPM_OUTPUT("HPOUTL"),
622 SND_SOC_DAPM_OUTPUT("HPOUTR"),
623 SND_SOC_DAPM_OUTPUT("EPOUT"),
624 SND_SOC_DAPM_OUTPUT("LSOUTL"),
625 SND_SOC_DAPM_OUTPUT("LSOUTR"),
626 SND_SOC_DAPM_OUTPUT("LOOUTR"),
627 SND_SOC_DAPM_OUTPUT("LOOUTL"),
628 SND_SOC_DAPM_OUTPUT("HAOUTL"),
629 SND_SOC_DAPM_OUTPUT("HAOUTR"),
630
631 SND_SOC_DAPM_INPUT("AMIC1"),
632 SND_SOC_DAPM_INPUT("AMIC2"),
633 SND_SOC_DAPM_INPUT("DMIC1DAT"),
634 SND_SOC_DAPM_INPUT("DMIC2DAT"),
635 SND_SOC_DAPM_INPUT("AUXL"),
636 SND_SOC_DAPM_INPUT("AUXR"),
637
638 SND_SOC_DAPM_PGA("PORT1_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
639 SND_SOC_DAPM_PGA("PORT1_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
640 SND_SOC_DAPM_PGA("PORT1_3_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
641 SND_SOC_DAPM_PGA("PORT1_4_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
642 SND_SOC_DAPM_PGA("PORT1_5_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
643 SND_SOC_DAPM_PGA("PORT1_6_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
644 SND_SOC_DAPM_PGA("PORT1_7_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
645 SND_SOC_DAPM_PGA("PORT1_8_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
646 SND_SOC_DAPM_PGA("PORT2_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
647 SND_SOC_DAPM_PGA("PORT2_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
648
649 SND_SOC_DAPM_SUPPLY("AMIC1Bias", LM49453_P0_MICL_REG, 6, 0, NULL, 0),
650 SND_SOC_DAPM_SUPPLY("AMIC2Bias", LM49453_P0_MICR_REG, 6, 0, NULL, 0),
651
652 /* playback path driver enables */
653 SND_SOC_DAPM_OUT_DRV("Headset Switch",
654 LM49453_P0_PMC_SETUP_REG, 0, 0, NULL, 0),
655 SND_SOC_DAPM_OUT_DRV("Earpiece Switch",
656 LM49453_P0_EP_REG, 0, 0, NULL, 0),
657 SND_SOC_DAPM_OUT_DRV("Speaker Left Switch",
658 LM49453_P0_DIS_PKVL_FB_REG, 0, 1, NULL, 0),
659 SND_SOC_DAPM_OUT_DRV("Speaker Right Switch",
660 LM49453_P0_DIS_PKVL_FB_REG, 1, 1, NULL, 0),
661 SND_SOC_DAPM_OUT_DRV("Haptic Left Switch",
662 LM49453_P0_DIS_PKVL_FB_REG, 2, 1, NULL, 0),
663 SND_SOC_DAPM_OUT_DRV("Haptic Right Switch",
664 LM49453_P0_DIS_PKVL_FB_REG, 3, 1, NULL, 0),
665
666 /* DAC */
667 SND_SOC_DAPM_DAC("HPL DAC", "Headset", SND_SOC_NOPM, 0, 0),
668 SND_SOC_DAPM_DAC("HPR DAC", "Headset", SND_SOC_NOPM, 0, 0),
669 SND_SOC_DAPM_DAC("LSL DAC", "Speaker", SND_SOC_NOPM, 0, 0),
670 SND_SOC_DAPM_DAC("LSR DAC", "Speaker", SND_SOC_NOPM, 0, 0),
671 SND_SOC_DAPM_DAC("HAL DAC", "Haptic", SND_SOC_NOPM, 0, 0),
672 SND_SOC_DAPM_DAC("HAR DAC", "Haptic", SND_SOC_NOPM, 0, 0),
673 SND_SOC_DAPM_DAC("LOL DAC", "Lineout", SND_SOC_NOPM, 0, 0),
674 SND_SOC_DAPM_DAC("LOR DAC", "Lineout", SND_SOC_NOPM, 0, 0),
675
676
677 SND_SOC_DAPM_PGA("AUXL Input",
678 LM49453_P0_ANALOG_MIXER_ADC_REG, 2, 0, NULL, 0),
679 SND_SOC_DAPM_PGA("AUXR Input",
680 LM49453_P0_ANALOG_MIXER_ADC_REG, 3, 0, NULL, 0),
681
682 SND_SOC_DAPM_PGA("Sidetone", SND_SOC_NOPM, 0, 0, NULL, 0),
683
684 /* ADC */
685 SND_SOC_DAPM_ADC("DMIC1 Left", "Capture", SND_SOC_NOPM, 1, 0),
686 SND_SOC_DAPM_ADC("DMIC1 Right", "Capture", SND_SOC_NOPM, 1, 0),
687 SND_SOC_DAPM_ADC("DMIC2 Left", "Capture", SND_SOC_NOPM, 1, 0),
688 SND_SOC_DAPM_ADC("DMIC2 Right", "Capture", SND_SOC_NOPM, 1, 0),
689
690 SND_SOC_DAPM_ADC("ADC Left", "Capture", SND_SOC_NOPM, 1, 0),
691 SND_SOC_DAPM_ADC("ADC Right", "Capture", SND_SOC_NOPM, 0, 0),
692
693 SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 0, 0,
694 &lm49453_adcl_mux_control),
695 SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
696 &lm49453_adcr_mux_control),
697
698 SND_SOC_DAPM_MUX("Mic1 Input",
699 SND_SOC_NOPM, 0, 0, &lm49453_adcl_mux_control),
700
701 SND_SOC_DAPM_MUX("Mic2 Input",
702 SND_SOC_NOPM, 0, 0, &lm49453_adcr_mux_control),
703
704 /* AIF */
705 SND_SOC_DAPM_AIF_IN("PORT1_SDI", NULL, 0,
706 LM49453_P0_PULL_CONFIG1_REG, 2, 0),
707 SND_SOC_DAPM_AIF_IN("PORT2_SDI", NULL, 0,
708 LM49453_P0_PULL_CONFIG1_REG, 6, 0),
709
710 SND_SOC_DAPM_AIF_OUT("PORT1_SDO", NULL, 0,
711 LM49453_P0_PULL_CONFIG1_REG, 3, 0),
712 SND_SOC_DAPM_AIF_OUT("PORT2_SDO", NULL, 0,
713 LM49453_P0_PULL_CONFIG1_REG, 7, 0),
714
715 /* Port1 TX controls */
716 SND_SOC_DAPM_OUT_DRV("P1_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
717 SND_SOC_DAPM_OUT_DRV("P1_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
718 SND_SOC_DAPM_OUT_DRV("P1_3_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
719 SND_SOC_DAPM_OUT_DRV("P1_4_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
720 SND_SOC_DAPM_OUT_DRV("P1_5_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
721 SND_SOC_DAPM_OUT_DRV("P1_6_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
722 SND_SOC_DAPM_OUT_DRV("P1_7_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
723 SND_SOC_DAPM_OUT_DRV("P1_8_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
724
725 /* Port2 TX controls */
726 SND_SOC_DAPM_OUT_DRV("P2_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
727 SND_SOC_DAPM_OUT_DRV("P2_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
728
729 /* Sidetone Mixer */
730 SND_SOC_DAPM_MIXER("Sidetone Mixer", SND_SOC_NOPM, 0, 0,
731 lm49453_sidetone_mixer_controls,
732 ARRAY_SIZE(lm49453_sidetone_mixer_controls)),
733
734 /* DAC MIXERS */
735 SND_SOC_DAPM_MIXER("HPL Mixer", SND_SOC_NOPM, 0, 0,
736 lm49453_headset_left_mixer,
737 ARRAY_SIZE(lm49453_headset_left_mixer)),
738 SND_SOC_DAPM_MIXER("HPR Mixer", SND_SOC_NOPM, 0, 0,
739 lm49453_headset_right_mixer,
740 ARRAY_SIZE(lm49453_headset_right_mixer)),
741 SND_SOC_DAPM_MIXER("LOL Mixer", SND_SOC_NOPM, 0, 0,
742 lm49453_lineout_left_mixer,
743 ARRAY_SIZE(lm49453_lineout_left_mixer)),
744 SND_SOC_DAPM_MIXER("LOR Mixer", SND_SOC_NOPM, 0, 0,
745 lm49453_lineout_right_mixer,
746 ARRAY_SIZE(lm49453_lineout_right_mixer)),
747 SND_SOC_DAPM_MIXER("LSL Mixer", SND_SOC_NOPM, 0, 0,
748 lm49453_speaker_left_mixer,
749 ARRAY_SIZE(lm49453_speaker_left_mixer)),
750 SND_SOC_DAPM_MIXER("LSR Mixer", SND_SOC_NOPM, 0, 0,
751 lm49453_speaker_right_mixer,
752 ARRAY_SIZE(lm49453_speaker_right_mixer)),
753 SND_SOC_DAPM_MIXER("HAL Mixer", SND_SOC_NOPM, 0, 0,
754 lm49453_haptic_left_mixer,
755 ARRAY_SIZE(lm49453_haptic_left_mixer)),
756 SND_SOC_DAPM_MIXER("HAR Mixer", SND_SOC_NOPM, 0, 0,
757 lm49453_haptic_right_mixer,
758 ARRAY_SIZE(lm49453_haptic_right_mixer)),
759
760 /* Capture Mixer */
761 SND_SOC_DAPM_MIXER("Port1_1 Mixer", SND_SOC_NOPM, 0, 0,
762 lm49453_port1_tx1_mixer,
763 ARRAY_SIZE(lm49453_port1_tx1_mixer)),
764 SND_SOC_DAPM_MIXER("Port1_2 Mixer", SND_SOC_NOPM, 0, 0,
765 lm49453_port1_tx2_mixer,
766 ARRAY_SIZE(lm49453_port1_tx2_mixer)),
767 SND_SOC_DAPM_MIXER("Port1_3 Mixer", SND_SOC_NOPM, 0, 0,
768 lm49453_port1_tx3_mixer,
769 ARRAY_SIZE(lm49453_port1_tx3_mixer)),
770 SND_SOC_DAPM_MIXER("Port1_4 Mixer", SND_SOC_NOPM, 0, 0,
771 lm49453_port1_tx4_mixer,
772 ARRAY_SIZE(lm49453_port1_tx4_mixer)),
773 SND_SOC_DAPM_MIXER("Port1_5 Mixer", SND_SOC_NOPM, 0, 0,
774 lm49453_port1_tx5_mixer,
775 ARRAY_SIZE(lm49453_port1_tx5_mixer)),
776 SND_SOC_DAPM_MIXER("Port1_6 Mixer", SND_SOC_NOPM, 0, 0,
777 lm49453_port1_tx6_mixer,
778 ARRAY_SIZE(lm49453_port1_tx6_mixer)),
779 SND_SOC_DAPM_MIXER("Port1_7 Mixer", SND_SOC_NOPM, 0, 0,
780 lm49453_port1_tx7_mixer,
781 ARRAY_SIZE(lm49453_port1_tx7_mixer)),
782 SND_SOC_DAPM_MIXER("Port1_8 Mixer", SND_SOC_NOPM, 0, 0,
783 lm49453_port1_tx8_mixer,
784 ARRAY_SIZE(lm49453_port1_tx8_mixer)),
785
786 SND_SOC_DAPM_MIXER("Port2_1 Mixer", SND_SOC_NOPM, 0, 0,
787 lm49453_port2_tx1_mixer,
788 ARRAY_SIZE(lm49453_port2_tx1_mixer)),
789 SND_SOC_DAPM_MIXER("Port2_2 Mixer", SND_SOC_NOPM, 0, 0,
790 lm49453_port2_tx2_mixer,
791 ARRAY_SIZE(lm49453_port2_tx2_mixer)),
792};
793
794static const struct snd_soc_dapm_route lm49453_audio_map[] = {
795 /* Port SDI mapping */
796 { "PORT1_1_RX", "Port1 Playback Switch", "PORT1_SDI" },
797 { "PORT1_2_RX", "Port1 Playback Switch", "PORT1_SDI" },
798 { "PORT1_3_RX", "Port1 Playback Switch", "PORT1_SDI" },
799 { "PORT1_4_RX", "Port1 Playback Switch", "PORT1_SDI" },
800 { "PORT1_5_RX", "Port1 Playback Switch", "PORT1_SDI" },
801 { "PORT1_6_RX", "Port1 Playback Switch", "PORT1_SDI" },
802 { "PORT1_7_RX", "Port1 Playback Switch", "PORT1_SDI" },
803 { "PORT1_8_RX", "Port1 Playback Switch", "PORT1_SDI" },
804
805 { "PORT2_1_RX", "Port2 Playback Switch", "PORT2_SDI" },
806 { "PORT2_2_RX", "Port2 Playback Switch", "PORT2_SDI" },
807
808 /* HP mapping */
809 { "HPL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
810 { "HPL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
811 { "HPL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
812 { "HPL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
813 { "HPL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
814 { "HPL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
815 { "HPL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
816 { "HPL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
817
818 { "HPL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
819 { "HPL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
820
821 { "HPL Mixer", "ADCL Switch", "ADC Left" },
822 { "HPL Mixer", "ADCR Switch", "ADC Right" },
823 { "HPL Mixer", "DMIC1L Switch", "DMIC1 Left" },
824 { "HPL Mixer", "DMIC1R Switch", "DMIC1 Right" },
825 { "HPL Mixer", "DMIC2L Switch", "DMIC2 Left" },
826 { "HPL Mixer", "DMIC2R Switch", "DMIC2 Right" },
827 { "HPL Mixer", "Sidetone Switch", "Sidetone" },
828
829 { "HPL DAC", NULL, "HPL Mixer" },
830
831 { "HPR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
832 { "HPR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
833 { "HPR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
834 { "HPR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
835 { "HPR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
836 { "HPR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
837 { "HPR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
838 { "HPR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
839
840 /* Port 2 */
841 { "HPR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
842 { "HPR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
843
844 { "HPR Mixer", "ADCL Switch", "ADC Left" },
845 { "HPR Mixer", "ADCR Switch", "ADC Right" },
846 { "HPR Mixer", "DMIC1L Switch", "DMIC1 Left" },
847 { "HPR Mixer", "DMIC1R Switch", "DMIC1 Right" },
848 { "HPR Mixer", "DMIC2L Switch", "DMIC2 Left" },
849 { "HPR Mixer", "DMIC2L Switch", "DMIC2 Right" },
850 { "HPR Mixer", "Sidetone Switch", "Sidetone" },
851
852 { "HPR DAC", NULL, "HPR Mixer" },
853
854 { "HPOUTL", "Headset Switch", "HPL DAC"},
855 { "HPOUTR", "Headset Switch", "HPR DAC"},
856
857 /* EP map */
858 { "EPOUT", "Earpiece Switch", "HPL DAC" },
859
860 /* Speaker map */
861 { "LSL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
862 { "LSL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
863 { "LSL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
864 { "LSL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
865 { "LSL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
866 { "LSL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
867 { "LSL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
868 { "LSL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
869
870 /* Port 2 */
871 { "LSL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
872 { "LSL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
873
874 { "LSL Mixer", "ADCL Switch", "ADC Left" },
875 { "LSL Mixer", "ADCR Switch", "ADC Right" },
876 { "LSL Mixer", "DMIC1L Switch", "DMIC1 Left" },
877 { "LSL Mixer", "DMIC1R Switch", "DMIC1 Right" },
878 { "LSL Mixer", "DMIC2L Switch", "DMIC2 Left" },
879 { "LSL Mixer", "DMIC2R Switch", "DMIC2 Right" },
880 { "LSL Mixer", "Sidetone Switch", "Sidetone" },
881
882 { "LSL DAC", NULL, "LSL Mixer" },
883
884 { "LSR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
885 { "LSR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
886 { "LSR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
887 { "LSR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
888 { "LSR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
889 { "LSR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
890 { "LSR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
891 { "LSR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
892
893 /* Port 2 */
894 { "LSR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
895 { "LSR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
896
897 { "LSR Mixer", "ADCL Switch", "ADC Left" },
898 { "LSR Mixer", "ADCR Switch", "ADC Right" },
899 { "LSR Mixer", "DMIC1L Switch", "DMIC1 Left" },
900 { "LSR Mixer", "DMIC1R Switch", "DMIC1 Right" },
901 { "LSR Mixer", "DMIC2L Switch", "DMIC2 Left" },
902 { "LSR Mixer", "DMIC2R Switch", "DMIC2 Right" },
903 { "LSR Mixer", "Sidetone Switch", "Sidetone" },
904
905 { "LSR DAC", NULL, "LSR Mixer" },
906
907 { "LSOUTL", "Speaker Left Switch", "LSL DAC"},
908 { "LSOUTR", "Speaker Left Switch", "LSR DAC"},
909
910 /* Haptic map */
911 { "HAL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
912 { "HAL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
913 { "HAL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
914 { "HAL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
915 { "HAL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
916 { "HAL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
917 { "HAL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
918 { "HAL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
919
920 /* Port 2 */
921 { "HAL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
922 { "HAL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
923
924 { "HAL Mixer", "ADCL Switch", "ADC Left" },
925 { "HAL Mixer", "ADCR Switch", "ADC Right" },
926 { "HAL Mixer", "DMIC1L Switch", "DMIC1 Left" },
927 { "HAL Mixer", "DMIC1R Switch", "DMIC1 Right" },
928 { "HAL Mixer", "DMIC2L Switch", "DMIC2 Left" },
929 { "HAL Mixer", "DMIC2R Switch", "DMIC2 Right" },
930 { "HAL Mixer", "Sidetone Switch", "Sidetone" },
931
932 { "HAL DAC", NULL, "HAL Mixer" },
933
934 { "HAR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
935 { "HAR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
936 { "HAR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
937 { "HAR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
938 { "HAR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
939 { "HAR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
940 { "HAR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
941 { "HAR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
942
943 /* Port 2 */
944 { "HAR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
945 { "HAR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
946
947 { "HAR Mixer", "ADCL Switch", "ADC Left" },
948 { "HAR Mixer", "ADCR Switch", "ADC Right" },
949 { "HAR Mixer", "DMIC1L Switch", "DMIC1 Left" },
950 { "HAR Mixer", "DMIC1R Switch", "DMIC1 Right" },
951 { "HAR Mixer", "DMIC2L Switch", "DMIC2 Left" },
952 { "HAR Mixer", "DMIC2R Switch", "DMIC2 Right" },
953 { "HAR Mixer", "Sideton Switch", "Sidetone" },
954
955 { "HAR DAC", NULL, "HAR Mixer" },
956
957 { "HAOUTL", "Haptic Left Switch", "HAL DAC" },
958 { "HAOUTR", "Haptic Right Switch", "HAR DAC" },
959
960 /* Lineout map */
961 { "LOL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
962 { "LOL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
963 { "LOL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
964 { "LOL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
965 { "LOL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
966 { "LOL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
967 { "LOL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
968 { "LOL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
969
970 /* Port 2 */
971 { "LOL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
972 { "LOL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
973
974 { "LOL Mixer", "ADCL Switch", "ADC Left" },
975 { "LOL Mixer", "ADCR Switch", "ADC Right" },
976 { "LOL Mixer", "DMIC1L Switch", "DMIC1 Left" },
977 { "LOL Mixer", "DMIC1R Switch", "DMIC1 Right" },
978 { "LOL Mixer", "DMIC2L Switch", "DMIC2 Left" },
979 { "LOL Mixer", "DMIC2R Switch", "DMIC2 Right" },
980 { "LOL Mixer", "Sidetone Switch", "Sidetone" },
981
982 { "LOL DAC", NULL, "LOL Mixer" },
983
984 { "LOR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
985 { "LOR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
986 { "LOR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
987 { "LOR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
988 { "LOR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
989 { "LOR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
990 { "LOR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
991 { "LOR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
992
993 /* Port 2 */
994 { "LOR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
995 { "LOR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
996
997 { "LOR Mixer", "ADCL Switch", "ADC Left" },
998 { "LOR Mixer", "ADCR Switch", "ADC Right" },
999 { "LOR Mixer", "DMIC1L Switch", "DMIC1 Left" },
1000 { "LOR Mixer", "DMIC1R Switch", "DMIC1 Right" },
1001 { "LOR Mixer", "DMIC2L Switch", "DMIC2 Left" },
1002 { "LOR Mixer", "DMIC2R Switch", "DMIC2 Right" },
1003 { "LOR Mixer", "Sidetone Switch", "Sidetone" },
1004
1005 { "LOR DAC", NULL, "LOR Mixer" },
1006
1007 { "LOOUTL", NULL, "LOL DAC" },
1008 { "LOOUTR", NULL, "LOR DAC" },
1009
1010 /* TX map */
1011 /* Port1 mappings */
1012 { "Port1_1 Mixer", "ADCL Switch", "ADC Left" },
1013 { "Port1_1 Mixer", "ADCR Switch", "ADC Right" },
1014 { "Port1_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1015 { "Port1_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1016 { "Port1_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1017 { "Port1_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1018
1019 { "Port1_2 Mixer", "ADCL Switch", "ADC Left" },
1020 { "Port1_2 Mixer", "ADCR Switch", "ADC Right" },
1021 { "Port1_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1022 { "Port1_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1023 { "Port1_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1024 { "Port1_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1025
1026 { "Port1_3 Mixer", "ADCL Switch", "ADC Left" },
1027 { "Port1_3 Mixer", "ADCR Switch", "ADC Right" },
1028 { "Port1_3 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1029 { "Port1_3 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1030 { "Port1_3 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1031 { "Port1_3 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1032
1033 { "Port1_4 Mixer", "ADCL Switch", "ADC Left" },
1034 { "Port1_4 Mixer", "ADCR Switch", "ADC Right" },
1035 { "Port1_4 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1036 { "Port1_4 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1037 { "Port1_4 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1038 { "Port1_4 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1039
1040 { "Port1_5 Mixer", "ADCL Switch", "ADC Left" },
1041 { "Port1_5 Mixer", "ADCR Switch", "ADC Right" },
1042 { "Port1_5 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1043 { "Port1_5 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1044 { "Port1_5 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1045 { "Port1_5 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1046
1047 { "Port1_6 Mixer", "ADCL Switch", "ADC Left" },
1048 { "Port1_6 Mixer", "ADCR Switch", "ADC Right" },
1049 { "Port1_6 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1050 { "Port1_6 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1051 { "Port1_6 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1052 { "Port1_6 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1053
1054 { "Port1_7 Mixer", "ADCL Switch", "ADC Left" },
1055 { "Port1_7 Mixer", "ADCR Switch", "ADC Right" },
1056 { "Port1_7 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1057 { "Port1_7 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1058 { "Port1_7 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1059 { "Port1_7 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1060
1061 { "Port1_8 Mixer", "ADCL Switch", "ADC Left" },
1062 { "Port1_8 Mixer", "ADCR Switch", "ADC Right" },
1063 { "Port1_8 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1064 { "Port1_8 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1065 { "Port1_8 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1066 { "Port1_8 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1067
1068 { "Port2_1 Mixer", "ADCL Switch", "ADC Left" },
1069 { "Port2_1 Mixer", "ADCR Switch", "ADC Right" },
1070 { "Port2_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1071 { "Port2_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1072 { "Port2_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1073 { "Port2_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1074
1075 { "Port2_2 Mixer", "ADCL Switch", "ADC Left" },
1076 { "Port2_2 Mixer", "ADCR Switch", "ADC Right" },
1077 { "Port2_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1078 { "Port2_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1079 { "Port2_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1080 { "Port2_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1081
1082 { "P1_1_TX", NULL, "Port1_1 Mixer" },
1083 { "P1_2_TX", NULL, "Port1_2 Mixer" },
1084 { "P1_3_TX", NULL, "Port1_3 Mixer" },
1085 { "P1_4_TX", NULL, "Port1_4 Mixer" },
1086 { "P1_5_TX", NULL, "Port1_5 Mixer" },
1087 { "P1_6_TX", NULL, "Port1_6 Mixer" },
1088 { "P1_7_TX", NULL, "Port1_7 Mixer" },
1089 { "P1_8_TX", NULL, "Port1_8 Mixer" },
1090
1091 { "P2_1_TX", NULL, "Port2_1 Mixer" },
1092 { "P2_2_TX", NULL, "Port2_2 Mixer" },
1093
1094 { "PORT1_SDO", "Port1 Capture Switch", "P1_1_TX"},
1095 { "PORT1_SDO", "Port1 Capture Switch", "P1_2_TX"},
1096 { "PORT1_SDO", "Port1 Capture Switch", "P1_3_TX"},
1097 { "PORT1_SDO", "Port1 Capture Switch", "P1_4_TX"},
1098 { "PORT1_SDO", "Port1 Capture Switch", "P1_5_TX"},
1099 { "PORT1_SDO", "Port1 Capture Switch", "P1_6_TX"},
1100 { "PORT1_SDO", "Port1 Capture Switch", "P1_7_TX"},
1101 { "PORT1_SDO", "Port1 Capture Switch", "P1_8_TX"},
1102
1103 { "PORT2_SDO", "Port2 Capture Switch", "P2_1_TX"},
1104 { "PORT2_SDO", "Port2 Capture Switch", "P2_2_TX"},
1105
1106 { "Mic1 Input", NULL, "AMIC1" },
1107 { "Mic2 Input", NULL, "AMIC2" },
1108
1109 { "AUXL Input", NULL, "AUXL" },
1110 { "AUXR Input", NULL, "AUXR" },
1111
1112 /* AUX connections */
1113 { "ADCL Mux", "Aux_L", "AUXL Input" },
1114 { "ADCL Mux", "MIC1", "Mic1 Input" },
1115
1116 { "ADCR Mux", "Aux_R", "AUXR Input" },
1117 { "ADCR Mux", "MIC2", "Mic2 Input" },
1118
1119 /* ADC connection */
1120 { "ADC Left", NULL, "ADCL Mux"},
1121 { "ADC Right", NULL, "ADCR Mux"},
1122
1123 { "DMIC1 Left", NULL, "DMIC1DAT"},
1124 { "DMIC1 Right", NULL, "DMIC1DAT"},
1125 { "DMIC2 Left", NULL, "DMIC2DAT"},
1126 { "DMIC2 Right", NULL, "DMIC2DAT"},
1127
1128 /* Sidetone map */
1129 { "Sidetone Mixer", NULL, "ADC Left" },
1130 { "Sidetone Mixer", NULL, "ADC Right" },
1131 { "Sidetone Mixer", NULL, "DMIC1 Left" },
1132 { "Sidetone Mixer", NULL, "DMIC1 Right" },
1133 { "Sidetone Mixer", NULL, "DMIC2 Left" },
1134 { "Sidetone Mixer", NULL, "DMIC2 Right" },
1135
1136 { "Sidetone", "Sidetone Switch", "Sidetone Mixer" },
1137};
1138
1139static int lm49453_hw_params(struct snd_pcm_substream *substream,
1140 struct snd_pcm_hw_params *params,
1141 struct snd_soc_dai *dai)
1142{
1143 struct snd_soc_codec *codec = dai->codec;
1144 struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1145 u16 clk_div = 0;
1146
1147 lm49453->fs_rate = params_rate(params);
1148
1149 /* Setting DAC clock dividers based on substream sample rate. */
1150 switch (lm49453->fs_rate) {
1151 case 8000:
1152 case 16000:
1153 case 32000:
1154 case 24000:
1155 case 48000:
1156 clk_div = 256;
1157 break;
1158 case 11025:
1159 case 22050:
1160 case 44100:
1161 clk_div = 216;
1162 break;
1163 case 96000:
1164 clk_div = 127;
1165 break;
1166 default:
1167 return -EINVAL;
1168 }
1169
1170 snd_soc_write(codec, LM49453_P0_ADC_CLK_DIV_REG, clk_div);
1171 snd_soc_write(codec, LM49453_P0_DAC_HP_CLK_DIV_REG, clk_div);
1172
1173 return 0;
1174}
1175
1176static int lm49453_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1177{
1178 struct snd_soc_codec *codec = codec_dai->codec;
1179
1180 u16 aif_val;
1181 int mode = 0;
1182 int clk_phase = 0;
1183 int clk_shift = 0;
1184
1185 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1186 case SND_SOC_DAIFMT_CBS_CFS:
1187 aif_val = 0;
1188 break;
1189 case SND_SOC_DAIFMT_CBS_CFM:
1190 aif_val = LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
1191 break;
1192 case SND_SOC_DAIFMT_CBM_CFS:
1193 aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS;
1194 break;
1195 case SND_SOC_DAIFMT_CBM_CFM:
1196 aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS |
1197 LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
1198 break;
1199 default:
1200 return -EINVAL;
1201 }
1202
1203
1204 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1205 case SND_SOC_DAIFMT_I2S:
1206 break;
1207 case SND_SOC_DAIFMT_DSP_A:
1208 mode = 1;
1209 clk_phase = (1 << 5);
1210 clk_shift = 1;
1211 break;
1212 case SND_SOC_DAIFMT_DSP_B:
1213 mode = 1;
1214 clk_phase = (1 << 5);
1215 clk_shift = 0;
1216 break;
1217 default:
1218 return -EINVAL;
1219 }
1220
1221 snd_soc_update_bits(codec, LM49453_P0_AUDIO_PORT1_BASIC_REG,
1222 LM49453_AUDIO_PORT1_BASIC_FMT_MASK|BIT(1)|BIT(5),
1223 (aif_val | mode | clk_phase));
1224
1225 snd_soc_write(codec, LM49453_P0_AUDIO_PORT1_RX_MSB_REG, clk_shift);
1226
1227 return 0;
1228}
1229
1230static int lm49453_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1231 unsigned int freq, int dir)
1232{
1233 struct snd_soc_codec *codec = dai->codec;
1234 u16 pll_clk = 0;
1235
1236 switch (freq) {
1237 case 12288000:
1238 case 26000000:
1239 case 19200000:
1240 /* pll clk slection */
1241 pll_clk = 0;
1242 break;
1243 case 48000:
1244 case 32576:
1245 /* fll clk slection */
1246 pll_clk = BIT(4);
1247 return 0;
1248 default:
1249 return -EINVAL;
1250 }
1251
1252 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG, BIT(4), pll_clk);
1253
1254 return 0;
1255}
1256
1257static int lm49453_hp_mute(struct snd_soc_dai *dai, int mute)
1258{
1259 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(1)|BIT(0),
1260 (mute ? (BIT(1)|BIT(0)) : 0));
1261 return 0;
1262}
1263
1264static int lm49453_lo_mute(struct snd_soc_dai *dai, int mute)
1265{
1266 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(3)|BIT(2),
1267 (mute ? (BIT(3)|BIT(2)) : 0));
1268 return 0;
1269}
1270
1271static int lm49453_ls_mute(struct snd_soc_dai *dai, int mute)
1272{
1273 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(5)|BIT(4),
1274 (mute ? (BIT(5)|BIT(4)) : 0));
1275 return 0;
1276}
1277
1278static int lm49453_ep_mute(struct snd_soc_dai *dai, int mute)
1279{
1280 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(4),
1281 (mute ? BIT(4) : 0));
1282 return 0;
1283}
1284
1285static int lm49453_ha_mute(struct snd_soc_dai *dai, int mute)
1286{
1287 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(7)|BIT(6),
1288 (mute ? (BIT(7)|BIT(6)) : 0));
1289 return 0;
1290}
1291
1292static int lm49453_set_bias_level(struct snd_soc_codec *codec,
1293 enum snd_soc_bias_level level)
1294{
1295 struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1296
1297 switch (level) {
1298 case SND_SOC_BIAS_ON:
1299 case SND_SOC_BIAS_PREPARE:
1300 break;
1301
1302 case SND_SOC_BIAS_STANDBY:
1303 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1304 regcache_sync(lm49453->regmap);
1305
1306 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
1307 LM49453_PMC_SETUP_CHIP_EN, LM49453_CHIP_EN);
1308 break;
1309
1310 case SND_SOC_BIAS_OFF:
1311 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
1312 LM49453_PMC_SETUP_CHIP_EN, 0);
1313 break;
1314 }
1315
1316 codec->dapm.bias_level = level;
1317
1318 return 0;
1319}
1320
1321/* Formates supported by LM49453 driver. */
1322#define LM49453_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1323 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1324
1325static struct snd_soc_dai_ops lm49453_headset_dai_ops = {
1326 .hw_params = lm49453_hw_params,
1327 .set_sysclk = lm49453_set_dai_sysclk,
1328 .set_fmt = lm49453_set_dai_fmt,
1329 .digital_mute = lm49453_hp_mute,
1330};
1331
1332static struct snd_soc_dai_ops lm49453_speaker_dai_ops = {
1333 .hw_params = lm49453_hw_params,
1334 .set_sysclk = lm49453_set_dai_sysclk,
1335 .set_fmt = lm49453_set_dai_fmt,
1336 .digital_mute = lm49453_ls_mute,
1337};
1338
1339static struct snd_soc_dai_ops lm49453_haptic_dai_ops = {
1340 .hw_params = lm49453_hw_params,
1341 .set_sysclk = lm49453_set_dai_sysclk,
1342 .set_fmt = lm49453_set_dai_fmt,
1343 .digital_mute = lm49453_ha_mute,
1344};
1345
1346static struct snd_soc_dai_ops lm49453_ep_dai_ops = {
1347 .hw_params = lm49453_hw_params,
1348 .set_sysclk = lm49453_set_dai_sysclk,
1349 .set_fmt = lm49453_set_dai_fmt,
1350 .digital_mute = lm49453_ep_mute,
1351};
1352
1353static struct snd_soc_dai_ops lm49453_lineout_dai_ops = {
1354 .hw_params = lm49453_hw_params,
1355 .set_sysclk = lm49453_set_dai_sysclk,
1356 .set_fmt = lm49453_set_dai_fmt,
1357 .digital_mute = lm49453_lo_mute,
1358};
1359
1360/* LM49453 dai structure. */
1361static const struct snd_soc_dai_driver lm49453_dai[] = {
1362 {
1363 .name = "LM49453 Headset",
1364 .playback = {
1365 .stream_name = "Headset",
1366 .channels_min = 2,
1367 .channels_max = 2,
1368 .rates = SNDRV_PCM_RATE_8000_192000,
1369 .formats = LM49453_FORMATS,
1370 },
1371 .capture = {
1372 .stream_name = "Capture",
1373 .channels_min = 1,
1374 .channels_max = 5,
1375 .rates = SNDRV_PCM_RATE_8000_192000,
1376 .formats = LM49453_FORMATS,
1377 },
1378 .ops = &lm49453_headset_dai_ops,
1379 .symmetric_rates = 1,
1380 },
1381 {
1382 .name = "LM49453 Speaker",
1383 .playback = {
1384 .stream_name = "Speaker",
1385 .channels_min = 2,
1386 .channels_max = 2,
1387 .rates = SNDRV_PCM_RATE_8000_192000,
1388 .formats = LM49453_FORMATS,
1389 },
1390 .ops = &lm49453_speaker_dai_ops,
1391 },
1392 {
1393 .name = "LM49453 Haptic",
1394 .playback = {
1395 .stream_name = "Haptic",
1396 .channels_min = 2,
1397 .channels_max = 2,
1398 .rates = SNDRV_PCM_RATE_8000_192000,
1399 .formats = LM49453_FORMATS,
1400 },
1401 .ops = &lm49453_haptic_dai_ops,
1402 },
1403 {
1404 .name = "LM49453 Earpiece",
1405 .playback = {
1406 .stream_name = "Earpiece",
1407 .channels_min = 1,
1408 .channels_max = 1,
1409 .rates = SNDRV_PCM_RATE_8000_192000,
1410 .formats = LM49453_FORMATS,
1411 },
1412 .ops = &lm49453_ep_dai_ops,
1413 },
1414 {
1415 .name = "LM49453 line out",
1416 .playback = {
1417 .stream_name = "Lineout",
1418 .channels_min = 2,
1419 .channels_max = 2,
1420 .rates = SNDRV_PCM_RATE_8000_192000,
1421 .formats = LM49453_FORMATS,
1422 },
1423 .ops = &lm49453_lineout_dai_ops,
1424 },
1425};
1426
1427static int lm49453_suspend(struct snd_soc_codec *codec)
1428{
1429 lm49453_set_bias_level(codec, SND_SOC_BIAS_OFF);
1430 return 0;
1431}
1432
1433static int lm49453_resume(struct snd_soc_codec *codec)
1434{
1435 lm49453_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1436 return 0;
1437}
1438
1439static int lm49453_probe(struct snd_soc_codec *codec)
1440{
1441 struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1442 int ret = 0;
1443
1444 codec->control_data = lm49453->regmap;
1445
1446 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
1447 if (ret < 0) {
1448 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1449 return ret;
1450 }
1451
1452 return 0;
1453}
1454
1455/* power down chip */
1456static int lm49453_remove(struct snd_soc_codec *codec)
1457{
1458 lm49453_set_bias_level(codec, SND_SOC_BIAS_OFF);
1459 return 0;
1460}
1461
1462static struct snd_soc_codec_driver soc_codec_dev_lm49453 = {
1463 .probe = lm49453_probe,
1464 .remove = lm49453_remove,
1465 .suspend = lm49453_suspend,
1466 .resume = lm49453_resume,
1467 .set_bias_level = lm49453_set_bias_level,
1468 .controls = lm49453_snd_controls,
1469 .num_controls = ARRAY_SIZE(lm49453_snd_controls),
1470 .dapm_widgets = lm49453_dapm_widgets,
1471 .num_dapm_widgets = ARRAY_SIZE(lm49453_dapm_widgets),
1472 .dapm_routes = lm49453_audio_map,
1473 .num_dapm_routes = ARRAY_SIZE(lm49453_audio_map),
1474 .idle_bias_off = true,
1475};
1476
1477static const struct regmap_config lm49453_regmap_config = {
1478 .reg_bits = 8,
1479 .val_bits = 8,
1480
1481 .max_register = LM49453_MAX_REGISTER,
1482 .reg_defaults = lm49453_reg_defs,
1483 .num_reg_defaults = ARRAY_SIZE(lm49453_reg_defs),
1484 .cache_type = REGCACHE_RBTREE,
1485};
1486
1487static __devinit int lm49453_i2c_probe(struct i2c_client *i2c,
1488 const struct i2c_device_id *id)
1489{
1490 struct lm49453_priv *lm49453;
1491 int ret = 0;
1492
1493 lm49453 = devm_kzalloc(&i2c->dev, sizeof(struct lm49453_priv),
1494 GFP_KERNEL);
1495
1496 if (lm49453 == NULL)
1497 return -ENOMEM;
1498
1499 i2c_set_clientdata(i2c, lm49453);
1500
1501 lm49453->regmap = regmap_init_i2c(i2c, &lm49453_regmap_config);
1502 if (IS_ERR(lm49453->regmap)) {
1503 ret = PTR_ERR(lm49453->regmap);
1504 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1505 ret);
1506 return ret;
1507 }
1508
1509 ret = snd_soc_register_codec(&i2c->dev,
1510 &soc_codec_dev_lm49453,
1511 lm49453_dai, ARRAY_SIZE(lm49453_dai));
1512 if (ret < 0) {
1513 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1514 regmap_exit(lm49453->regmap);
1515 return ret;
1516 }
1517
1518 return ret;
1519}
1520
1521static int __devexit lm49453_i2c_remove(struct i2c_client *client)
1522{
1523 struct lm49453_priv *lm49453 = i2c_get_clientdata(client);
1524
1525 snd_soc_unregister_codec(&client->dev);
1526 regmap_exit(lm49453->regmap);
1527 return 0;
1528}
1529
1530static const struct i2c_device_id lm49453_i2c_id[] = {
1531 { "lm49453", 0 },
1532 { }
1533};
1534MODULE_DEVICE_TABLE(i2c, lm49453_i2c_id);
1535
1536static struct i2c_driver lm49453_i2c_driver = {
1537 .driver = {
1538 .name = "lm49453",
1539 .owner = THIS_MODULE,
1540 },
1541 .probe = lm49453_i2c_probe,
1542 .remove = __devexit_p(lm49453_i2c_remove),
1543 .id_table = lm49453_i2c_id,
1544};
1545
1546module_i2c_driver(lm49453_i2c_driver);
1547
1548MODULE_DESCRIPTION("ASoC LM49453 driver");
1549MODULE_AUTHOR("M R Swami Reddy <MR.Swami.Reddy@ti.com>");
1550MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/lm49453.h b/sound/soc/codecs/lm49453.h
new file mode 100644
index 000000000000..a63cfa5c0883
--- /dev/null
+++ b/sound/soc/codecs/lm49453.h
@@ -0,0 +1,380 @@
1/*
2 * lm49453.h - LM49453 ALSA Soc Audio drive
3 *
4 * Copyright (c) 2012 Texas Instruments, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 */
11
12#ifndef _LM49453_H
13#define _LM49453_H
14
15#include <linux/bitops.h>
16
17/* LM49453_P0 register space for page0 */
18#define LM49453_P0_PMC_SETUP_REG 0x00
19#define LM49453_P0_PLL_CLK_SEL1_REG 0x01
20#define LM49453_P0_PLL_CLK_SEL2_REG 0x02
21#define LM49453_P0_PMC_CLK_DIV_REG 0x03
22#define LM49453_P0_HSDET_CLK_DIV_REG 0x04
23#define LM49453_P0_DMIC_CLK_DIV_REG 0x05
24#define LM49453_P0_ADC_CLK_DIV_REG 0x06
25#define LM49453_P0_DAC_OT_CLK_DIV_REG 0x07
26#define LM49453_P0_PLL_HF_M_REG 0x08
27#define LM49453_P0_PLL_LF_M_REG 0x09
28#define LM49453_P0_PLL_NL_REG 0x0A
29#define LM49453_P0_PLL_N_MODL_REG 0x0B
30#define LM49453_P0_PLL_N_MODH_REG 0x0C
31#define LM49453_P0_PLL_P1_REG 0x0D
32#define LM49453_P0_PLL_P2_REG 0x0E
33#define LM49453_P0_FLL_REF_FREQL_REG 0x0F
34#define LM49453_P0_FLL_REF_FREQH_REG 0x10
35#define LM49453_P0_VCO_TARGETLL_REG 0x11
36#define LM49453_P0_VCO_TARGETLH_REG 0x12
37#define LM49453_P0_VCO_TARGETHL_REG 0x13
38#define LM49453_P0_VCO_TARGETHH_REG 0x14
39#define LM49453_P0_PLL_CONFIG_REG 0x15
40#define LM49453_P0_DAC_CLK_SEL_REG 0x16
41#define LM49453_P0_DAC_HP_CLK_DIV_REG 0x17
42
43/* Analog Mixer Input Stages */
44#define LM49453_P0_MICL_REG 0x20
45#define LM49453_P0_MICR_REG 0x21
46#define LM49453_P0_EP_REG 0x24
47#define LM49453_P0_DIS_PKVL_FB_REG 0x25
48
49/* Analog Mixer Output Stages */
50#define LM49453_P0_ANALOG_MIXER_ADC_REG 0x2E
51
52/*ADC or DAC */
53#define LM49453_P0_ADC_DSP_REG 0x30
54#define LM49453_P0_DAC_DSP_REG 0x31
55
56/* EFFECTS ENABLES */
57#define LM49453_P0_ADC_FX_ENABLES_REG 0x33
58
59/* GPIO */
60#define LM49453_P0_GPIO1_REG 0x38
61#define LM49453_P0_GPIO2_REG 0x39
62#define LM49453_P0_GPIO3_REG 0x3A
63#define LM49453_P0_HAP_CTL_REG 0x3B
64#define LM49453_P0_HAP_FREQ_PROG_LEFTL_REG 0x3C
65#define LM49453_P0_HAP_FREQ_PROG_LEFTH_REG 0x3D
66#define LM49453_P0_HAP_FREQ_PROG_RIGHTL_REG 0x3E
67#define LM49453_P0_HAP_FREQ_PROG_RIGHTH_REG 0x3F
68
69/* DIGITAL MIXER */
70#define LM49453_P0_DMIX_CLK_SEL_REG 0x40
71#define LM49453_P0_PORT1_RX_LVL1_REG 0x41
72#define LM49453_P0_PORT1_RX_LVL2_REG 0x42
73#define LM49453_P0_PORT2_RX_LVL_REG 0x43
74#define LM49453_P0_PORT1_TX1_REG 0x44
75#define LM49453_P0_PORT1_TX2_REG 0x45
76#define LM49453_P0_PORT1_TX3_REG 0x46
77#define LM49453_P0_PORT1_TX4_REG 0x47
78#define LM49453_P0_PORT1_TX5_REG 0x48
79#define LM49453_P0_PORT1_TX6_REG 0x49
80#define LM49453_P0_PORT1_TX7_REG 0x4A
81#define LM49453_P0_PORT1_TX8_REG 0x4B
82#define LM49453_P0_PORT2_TX1_REG 0x4C
83#define LM49453_P0_PORT2_TX2_REG 0x4D
84#define LM49453_P0_STN_SEL_REG 0x4F
85#define LM49453_P0_DACHPL1_REG 0x50
86#define LM49453_P0_DACHPL2_REG 0x51
87#define LM49453_P0_DACHPR1_REG 0x52
88#define LM49453_P0_DACHPR2_REG 0x53
89#define LM49453_P0_DACLOL1_REG 0x54
90#define LM49453_P0_DACLOL2_REG 0x55
91#define LM49453_P0_DACLOR1_REG 0x56
92#define LM49453_P0_DACLOR2_REG 0x57
93#define LM49453_P0_DACLSL1_REG 0x58
94#define LM49453_P0_DACLSL2_REG 0x59
95#define LM49453_P0_DACLSR1_REG 0x5A
96#define LM49453_P0_DACLSR2_REG 0x5B
97#define LM49453_P0_DACHAL1_REG 0x5C
98#define LM49453_P0_DACHAL2_REG 0x5D
99#define LM49453_P0_DACHAR1_REG 0x5E
100#define LM49453_P0_DACHAR2_REG 0x5F
101
102/* AUDIO PORT 1 (TDM) */
103#define LM49453_P0_AUDIO_PORT1_BASIC_REG 0x60
104#define LM49453_P0_AUDIO_PORT1_CLK_GEN1_REG 0x61
105#define LM49453_P0_AUDIO_PORT1_CLK_GEN2_REG 0x62
106#define LM49453_P0_AUDIO_PORT1_CLK_GEN3_REG 0x63
107#define LM49453_P0_AUDIO_PORT1_SYNC_RATE_REG 0x64
108#define LM49453_P0_AUDIO_PORT1_SYNC_SDO_SETUP_REG 0x65
109#define LM49453_P0_AUDIO_PORT1_DATA_WIDTH_REG 0x66
110#define LM49453_P0_AUDIO_PORT1_RX_MSB_REG 0x67
111#define LM49453_P0_AUDIO_PORT1_TX_MSB_REG 0x68
112#define LM49453_P0_AUDIO_PORT1_TDM_CHANNELS_REG 0x69
113
114/* AUDIO PORT 2 */
115#define LM49453_P0_AUDIO_PORT2_BASIC_REG 0x6A
116#define LM49453_P0_AUDIO_PORT2_CLK_GEN1_REG 0x6B
117#define LM49453_P0_AUDIO_PORT2_CLK_GEN2_REG 0x6C
118#define LM49453_P0_AUDIO_PORT2_SYNC_GEN_REG 0x6D
119#define LM49453_P0_AUDIO_PORT2_DATA_WIDTH_REG 0x6E
120#define LM49453_P0_AUDIO_PORT2_RX_MODE_REG 0x6F
121#define LM49453_P0_AUDIO_PORT2_TX_MODE_REG 0x70
122
123/* SAMPLE RATE */
124#define LM49453_P0_PORT1_SR_LSB_REG 0x79
125#define LM49453_P0_PORT1_SR_MSB_REG 0x7A
126#define LM49453_P0_PORT2_SR_LSB_REG 0x7B
127#define LM49453_P0_PORT2_SR_MSB_REG 0x7C
128
129/* EFFECTS - HPFs */
130#define LM49453_P0_HPF_REG 0x80
131
132/* EFFECTS ADC ALC */
133#define LM49453_P0_ADC_ALC1_REG 0x82
134#define LM49453_P0_ADC_ALC2_REG 0x83
135#define LM49453_P0_ADC_ALC3_REG 0x84
136#define LM49453_P0_ADC_ALC4_REG 0x85
137#define LM49453_P0_ADC_ALC5_REG 0x86
138#define LM49453_P0_ADC_ALC6_REG 0x87
139#define LM49453_P0_ADC_ALC7_REG 0x88
140#define LM49453_P0_ADC_ALC8_REG 0x89
141#define LM49453_P0_DMIC1_LEVELL_REG 0x8A
142#define LM49453_P0_DMIC1_LEVELR_REG 0x8B
143#define LM49453_P0_DMIC2_LEVELL_REG 0x8C
144#define LM49453_P0_DMIC2_LEVELR_REG 0x8D
145#define LM49453_P0_ADC_LEVELL_REG 0x8E
146#define LM49453_P0_ADC_LEVELR_REG 0x8F
147#define LM49453_P0_DAC_HP_LEVELL_REG 0x90
148#define LM49453_P0_DAC_HP_LEVELR_REG 0x91
149#define LM49453_P0_DAC_LO_LEVELL_REG 0x92
150#define LM49453_P0_DAC_LO_LEVELR_REG 0x93
151#define LM49453_P0_DAC_LS_LEVELL_REG 0x94
152#define LM49453_P0_DAC_LS_LEVELR_REG 0x95
153#define LM49453_P0_DAC_HA_LEVELL_REG 0x96
154#define LM49453_P0_DAC_HA_LEVELR_REG 0x97
155#define LM49453_P0_SOFT_MUTE_REG 0x98
156#define LM49453_P0_DMIC_MUTE_CFG_REG 0x99
157#define LM49453_P0_ADC_MUTE_CFG_REG 0x9A
158#define LM49453_P0_DAC_MUTE_CFG_REG 0x9B
159
160/*DIGITAL MIC1 */
161#define LM49453_P0_DIGITAL_MIC1_CONFIG_REG 0xB0
162#define LM49453_P0_DIGITAL_MIC1_DATA_DELAYL_REG 0xB1
163#define LM49453_P0_DIGITAL_MIC1_DATA_DELAYR_REG 0xB2
164
165/*DIGITAL MIC2 */
166#define LM49453_P0_DIGITAL_MIC2_CONFIG_REG 0xB3
167#define LM49453_P0_DIGITAL_MIC2_DATA_DELAYL_REG 0xB4
168#define LM49453_P0_DIGITAL_MIC2_DATA_DELAYR_REG 0xB5
169
170/* ADC DECIMATOR */
171#define LM49453_P0_ADC_DECIMATOR_REG 0xB6
172
173/* DAC CONFIGURE */
174#define LM49453_P0_DAC_CONFIG_REG 0xB7
175
176/* SIDETONE */
177#define LM49453_P0_STN_VOL_ADCL_REG 0xB8
178#define LM49453_P0_STN_VOL_ADCR_REG 0xB9
179#define LM49453_P0_STN_VOL_DMIC1L_REG 0xBA
180#define LM49453_P0_STN_VOL_DMIC1R_REG 0xBB
181#define LM49453_P0_STN_VOL_DMIC2L_REG 0xBC
182#define LM49453_P0_STN_VOL_DMIC2R_REG 0xBD
183
184/* ADC/DAC CLIPPING MONITORS (Read Only/Write to Clear) */
185#define LM49453_P0_ADC_DEC_CLIP_REG 0xC2
186#define LM49453_P0_ADC_HPF_CLIP_REG 0xC3
187#define LM49453_P0_ADC_LVL_CLIP_REG 0xC4
188#define LM49453_P0_DAC_LVL_CLIP_REG 0xC5
189
190/* ADC ALC EFFECT MONITORS (Read Only) */
191#define LM49453_P0_ADC_LVLMONL_REG 0xC8
192#define LM49453_P0_ADC_LVLMONR_REG 0xC9
193#define LM49453_P0_ADC_ALCMONL_REG 0xCA
194#define LM49453_P0_ADC_ALCMONR_REG 0xCB
195#define LM49453_P0_ADC_MUTED_REG 0xCC
196#define LM49453_P0_DAC_MUTED_REG 0xCD
197
198/* HEADSET DETECT */
199#define LM49453_P0_HSD_PPB_LONG_CNT_LIMITL_REG 0xD0
200#define LM49453_P0_HSD_PPB_LONG_CNT_LIMITR_REG 0xD1
201#define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITL_REG 0xD2
202#define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITH_REG 0xD3
203#define LM49453_P0_HSD_TIMEOUT1_REG 0xD4
204#define LM49453_P0_HSD_TIMEOUT2_REG 0xD5
205#define LM49453_P0_HSD_TIMEOUT3_REG 0xD6
206#define LM49453_P0_HSD_PIN3_4_CFG_REG 0xD7
207#define LM49453_P0_HSD_IRQ1_REG 0xD8
208#define LM49453_P0_HSD_IRQ2_REG 0xD9
209#define LM49453_P0_HSD_IRQ3_REG 0xDA
210#define LM49453_P0_HSD_IRQ4_REG 0xDB
211#define LM49453_P0_HSD_IRQ_MASK1_REG 0xDC
212#define LM49453_P0_HSD_IRQ_MASK2_REG 0xDD
213#define LM49453_P0_HSD_IRQ_MASK3_REG 0xDE
214#define LM49453_P0_HSD_R_HPLL_REG 0xE0
215#define LM49453_P0_HSD_R_HPLH_REG 0xE1
216#define LM49453_P0_HSD_R_HPLU_REG 0xE2
217#define LM49453_P0_HSD_R_HPRL_REG 0xE3
218#define LM49453_P0_HSD_R_HPRH_REG 0xE4
219#define LM49453_P0_HSD_R_HPRU_REG 0xE5
220#define LM49453_P0_HSD_VEL_L_FINALL_REG 0xE6
221#define LM49453_P0_HSD_VEL_L_FINALH_REG 0xE7
222#define LM49453_P0_HSD_VEL_L_FINALU_REG 0xE8
223#define LM49453_P0_HSD_RO_FINALL_REG 0xE9
224#define LM49453_P0_HSD_RO_FINALH_REG 0xEA
225#define LM49453_P0_HSD_RO_FINALU_REG 0xEB
226#define LM49453_P0_HSD_VMIC_BIAS_FINALL_REG 0xEC
227#define LM49453_P0_HSD_VMIC_BIAS_FINALH_REG 0xED
228#define LM49453_P0_HSD_VMIC_BIAS_FINALU_REG 0xEE
229#define LM49453_P0_HSD_PIN_CONFIG_REG 0xEF
230#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS1_REG 0xF1
231#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS2_REG 0xF2
232#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS3_REG 0xF3
233#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEL_REG 0xF4
234#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEH_REG 0xF5
235
236/* I/O PULLDOWN CONFIG */
237#define LM49453_P0_PULL_CONFIG1_REG 0xF8
238#define LM49453_P0_PULL_CONFIG2_REG 0xF9
239#define LM49453_P0_PULL_CONFIG3_REG 0xFA
240
241/* RESET */
242#define LM49453_P0_RESET_REG 0xFE
243
244/* PAGE */
245#define LM49453_PAGE_REG 0xFF
246
247#define LM49453_MAX_REGISTER (0xFF+1)
248
249/* LM49453_P0_PMC_SETUP_REG (0x00h) */
250#define LM49453_PMC_SETUP_CHIP_EN (BIT(1)|BIT(0))
251#define LM49453_PMC_SETUP_PLL_EN BIT(2)
252#define LM49453_PMC_SETUP_PLL_P2_EN BIT(3)
253#define LM49453_PMC_SETUP_PLL_FLL BIT(4)
254#define LM49453_PMC_SETUP_MCLK_OVER BIT(5)
255#define LM49453_PMC_SETUP_RTC_CLK_OVER BIT(6)
256#define LM49453_PMC_SETUP_CHIP_ACTIVE BIT(7)
257
258/* Chip Enable bits */
259#define LM49453_CHIP_EN_SHUTDOWN 0x00
260#define LM49453_CHIP_EN 0x01
261#define LM49453_CHIP_EN_HSD_DETECT 0x02
262#define LM49453_CHIP_EN_INVALID_HSD 0x03
263
264/* LM49453_P0_PLL_CLK_SEL1_REG (0x01h) */
265#define LM49453_CLK_SEL1_MCLK_SEL 0x11
266#define LM49453_CLK_SEL1_RTC_SEL 0x11
267#define LM49453_CLK_SEL1_PORT1_SEL 0x10
268#define LM49453_CLK_SEL1_PORT2_SEL 0x11
269
270/* LM49453_P0_PLL_CLK_SEL2_REG (0x02h) */
271#define LM49453_CLK_SEL2_ADC_CLK_SEL 0x38
272
273/* LM49453_P0_FLL_REF_FREQL_REG (0x0F) */
274#define LM49453_FLL_REF_FREQ_VAL 0x8ca0001
275
276/* LM49453_P0_VCO_TARGETLL_REG (0x11) */
277#define LM49453_VCO_TARGET_VAL 0x8ca0001
278
279/* LM49453_P0_ADC_DSP_REG (0x30h) */
280#define LM49453_ADC_DSP_ADC_MUTEL BIT(0)
281#define LM49453_ADC_DSP_ADC_MUTER BIT(1)
282#define LM49453_ADC_DSP_DMIC1_MUTEL BIT(2)
283#define LM49453_ADC_DSP_DMIC1_MUTER BIT(3)
284#define LM49453_ADC_DSP_DMIC2_MUTEL BIT(4)
285#define LM49453_ADC_DSP_DMIC2_MUTER BIT(5)
286#define LM49453_ADC_DSP_MUTE_ALL 0x3F
287
288/* LM49453_P0_DAC_DSP_REG (0x31h) */
289#define LM49453_DAC_DSP_MUTE_ALL 0xFF
290
291/* LM49453_P0_AUDIO_PORT1_BASIC_REG (0x60h) */
292#define LM49453_AUDIO_PORT1_BASIC_FMT_MASK (BIT(4)|BIT(3))
293#define LM49453_AUDIO_PORT1_BASIC_CLK_MS BIT(3)
294#define LM49453_AUDIO_PORT1_BASIC_SYNC_MS BIT(4)
295
296/* LM49453_P0_RESET_REG (0xFEh) */
297#define LM49453_RESET_REG_RST BIT(0)
298
299/* Page select register bits (0xFF) */
300#define LM49453_PAGE0_SELECT 0x0
301#define LM49453_PAGE1_SELECT 0x1
302
303/* LM49453_P0_HSD_PIN3_4_CFG_REG (Jack Pin config - 0xD7) */
304#define LM49453_JACK_DISABLE 0x00
305#define LM49453_JACK_CONFIG1 0x01
306#define LM49453_JACK_CONFIG2 0x02
307#define LM49453_JACK_CONFIG3 0x03
308#define LM49453_JACK_CONFIG4 0x04
309#define LM49453_JACK_CONFIG5 0x05
310
311/* Page 1 REGISTERS */
312
313/* SIDETONE */
314#define LM49453_P1_SIDETONE_SA0L_REG 0x80
315#define LM49453_P1_SIDETONE_SA0H_REG 0x81
316#define LM49453_P1_SIDETONE_SAB0U_REG 0x82
317#define LM49453_P1_SIDETONE_SB0L_REG 0x83
318#define LM49453_P1_SIDETONE_SB0H_REG 0x84
319#define LM49453_P1_SIDETONE_SH0L_REG 0x85
320#define LM49453_P1_SIDETONE_SH0H_REG 0x86
321#define LM49453_P1_SIDETONE_SH0U_REG 0x87
322#define LM49453_P1_SIDETONE_SA1L_REG 0x88
323#define LM49453_P1_SIDETONE_SA1H_REG 0x89
324#define LM49453_P1_SIDETONE_SAB1U_REG 0x8A
325#define LM49453_P1_SIDETONE_SB1L_REG 0x8B
326#define LM49453_P1_SIDETONE_SB1H_REG 0x8C
327#define LM49453_P1_SIDETONE_SH1L_REG 0x8D
328#define LM49453_P1_SIDETONE_SH1H_REG 0x8E
329#define LM49453_P1_SIDETONE_SH1U_REG 0x8F
330#define LM49453_P1_SIDETONE_SA2L_REG 0x90
331#define LM49453_P1_SIDETONE_SA2H_REG 0x91
332#define LM49453_P1_SIDETONE_SAB2U_REG 0x92
333#define LM49453_P1_SIDETONE_SB2L_REG 0x93
334#define LM49453_P1_SIDETONE_SB2H_REG 0x94
335#define LM49453_P1_SIDETONE_SH2L_REG 0x95
336#define LM49453_P1_SIDETONE_SH2H_REG 0x96
337#define LM49453_P1_SIDETONE_SH2U_REG 0x97
338#define LM49453_P1_SIDETONE_SA3L_REG 0x98
339#define LM49453_P1_SIDETONE_SA3H_REG 0x99
340#define LM49453_P1_SIDETONE_SAB3U_REG 0x9A
341#define LM49453_P1_SIDETONE_SB3L_REG 0x9B
342#define LM49453_P1_SIDETONE_SB3H_REG 0x9C
343#define LM49453_P1_SIDETONE_SH3L_REG 0x9D
344#define LM49453_P1_SIDETONE_SH3H_REG 0x9E
345#define LM49453_P1_SIDETONE_SH3U_REG 0x9F
346#define LM49453_P1_SIDETONE_SA4L_REG 0xA0
347#define LM49453_P1_SIDETONE_SA4H_REG 0xA1
348#define LM49453_P1_SIDETONE_SAB4U_REG 0xA2
349#define LM49453_P1_SIDETONE_SB4L_REG 0xA3
350#define LM49453_P1_SIDETONE_SB4H_REG 0xA4
351#define LM49453_P1_SIDETONE_SH4L_REG 0xA5
352#define LM49453_P1_SIDETONE_SH4H_REG 0xA6
353#define LM49453_P1_SIDETONE_SH4U_REG 0xA7
354#define LM49453_P1_SIDETONE_SA5L_REG 0xA8
355#define LM49453_P1_SIDETONE_SA5H_REG 0xA9
356#define LM49453_P1_SIDETONE_SAB5U_REG 0xAA
357#define LM49453_P1_SIDETONE_SB5L_REG 0xAB
358#define LM49453_P1_SIDETONE_SB5H_REG 0xAC
359#define LM49453_P1_SIDETONE_SH5L_REG 0xAD
360#define LM49453_P1_SIDETONE_SH5H_REG 0xAE
361#define LM49453_P1_SIDETONE_SH5U_REG 0xAF
362
363/* CHARGE PUMP CONFIG */
364#define LM49453_P1_CP_CONFIG1_REG 0xB0
365#define LM49453_P1_CP_CONFIG2_REG 0xB1
366#define LM49453_P1_CP_CONFIG3_REG 0xB2
367#define LM49453_P1_CP_CONFIG4_REG 0xB3
368#define LM49453_P1_CP_LA_VTH1L_REG 0xB4
369#define LM49453_P1_CP_LA_VTH1M_REG 0xB5
370#define LM49453_P1_CP_LA_VTH2L_REG 0xB6
371#define LM49453_P1_CP_LA_VTH2M_REG 0xB7
372#define LM49453_P1_CP_LA_VTH3L_REG 0xB8
373#define LM49453_P1_CP_LA_VTH3H_REG 0xB9
374#define LM49453_P1_CP_CLK_DIV_REG 0xBA
375
376/* DAC */
377#define LM49453_P1_DAC_CHOP_REG 0xC0
378
379#define LM49453_CLK_SRC_MCLK 1
380#endif
diff --git a/sound/soc/codecs/max98095.c b/sound/soc/codecs/max98095.c
index 0bb511a0388d..35179e2c23c9 100644
--- a/sound/soc/codecs/max98095.c
+++ b/sound/soc/codecs/max98095.c
@@ -24,6 +24,7 @@
24#include <linux/slab.h> 24#include <linux/slab.h>
25#include <asm/div64.h> 25#include <asm/div64.h>
26#include <sound/max98095.h> 26#include <sound/max98095.h>
27#include <sound/jack.h>
27#include "max98095.h" 28#include "max98095.h"
28 29
29enum max98095_type { 30enum max98095_type {
@@ -51,6 +52,8 @@ struct max98095_priv {
51 u8 lin_state; 52 u8 lin_state;
52 unsigned int mic1pre; 53 unsigned int mic1pre;
53 unsigned int mic2pre; 54 unsigned int mic2pre;
55 struct snd_soc_jack *headphone_jack;
56 struct snd_soc_jack *mic_jack;
54}; 57};
55 58
56static const u8 max98095_reg_def[M98095_REG_CNT] = { 59static const u8 max98095_reg_def[M98095_REG_CNT] = {
@@ -2173,9 +2176,125 @@ static void max98095_handle_pdata(struct snd_soc_codec *codec)
2173 max98095_handle_bq_pdata(codec); 2176 max98095_handle_bq_pdata(codec);
2174} 2177}
2175 2178
2179static irqreturn_t max98095_report_jack(int irq, void *data)
2180{
2181 struct snd_soc_codec *codec = data;
2182 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2183 unsigned int value;
2184 int hp_report = 0;
2185 int mic_report = 0;
2186
2187 /* Read the Jack Status Register */
2188 value = snd_soc_read(codec, M98095_007_JACK_AUTO_STS);
2189
2190 /* If ddone is not set, then detection isn't finished yet */
2191 if ((value & M98095_DDONE) == 0)
2192 return IRQ_NONE;
2193
2194 /* if hp, check its bit, and if set, clear it */
2195 if ((value & M98095_HP_IN || value & M98095_LO_IN) &&
2196 max98095->headphone_jack)
2197 hp_report |= SND_JACK_HEADPHONE;
2198
2199 /* if mic, check its bit, and if set, clear it */
2200 if ((value & M98095_MIC_IN) && max98095->mic_jack)
2201 mic_report |= SND_JACK_MICROPHONE;
2202
2203 if (max98095->headphone_jack == max98095->mic_jack) {
2204 snd_soc_jack_report(max98095->headphone_jack,
2205 hp_report | mic_report,
2206 SND_JACK_HEADSET);
2207 } else {
2208 if (max98095->headphone_jack)
2209 snd_soc_jack_report(max98095->headphone_jack,
2210 hp_report, SND_JACK_HEADPHONE);
2211 if (max98095->mic_jack)
2212 snd_soc_jack_report(max98095->mic_jack,
2213 mic_report, SND_JACK_MICROPHONE);
2214 }
2215
2216 return IRQ_HANDLED;
2217}
2218
2219int max98095_jack_detect_enable(struct snd_soc_codec *codec)
2220{
2221 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2222 int ret = 0;
2223 int detect_enable = M98095_JDEN;
2224 unsigned int slew = M98095_DEFAULT_SLEW_DELAY;
2225
2226 if (max98095->pdata->jack_detect_pin5en)
2227 detect_enable |= M98095_PIN5EN;
2228
2229 if (max98095->pdata->jack_detect_delay)
2230 slew = max98095->pdata->jack_detect_delay;
2231
2232 ret = snd_soc_write(codec, M98095_08E_JACK_DC_SLEW, slew);
2233 if (ret < 0) {
2234 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2235 return ret;
2236 }
2237
2238 /* configure auto detection to be enabled */
2239 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, detect_enable);
2240 if (ret < 0) {
2241 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2242 return ret;
2243 }
2244
2245 return ret;
2246}
2247
2248int max98095_jack_detect_disable(struct snd_soc_codec *codec)
2249{
2250 int ret = 0;
2251
2252 /* configure auto detection to be disabled */
2253 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, 0x0);
2254 if (ret < 0) {
2255 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret);
2256 return ret;
2257 }
2258
2259 return ret;
2260}
2261
2262int max98095_jack_detect(struct snd_soc_codec *codec,
2263 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
2264{
2265 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2266 struct i2c_client *client = to_i2c_client(codec->dev);
2267 int ret = 0;
2268
2269 max98095->headphone_jack = hp_jack;
2270 max98095->mic_jack = mic_jack;
2271
2272 /* only progress if we have at least 1 jack pointer */
2273 if (!hp_jack && !mic_jack)
2274 return -EINVAL;
2275
2276 max98095_jack_detect_enable(codec);
2277
2278 /* enable interrupts for headphone jack detection */
2279 ret = snd_soc_update_bits(codec, M98095_013_JACK_INT_EN,
2280 M98095_IDDONE, M98095_IDDONE);
2281 if (ret < 0) {
2282 dev_err(codec->dev, "Failed to cfg jack irqs %d\n", ret);
2283 return ret;
2284 }
2285
2286 max98095_report_jack(client->irq, codec);
2287 return 0;
2288}
2289
2176#ifdef CONFIG_PM 2290#ifdef CONFIG_PM
2177static int max98095_suspend(struct snd_soc_codec *codec) 2291static int max98095_suspend(struct snd_soc_codec *codec)
2178{ 2292{
2293 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2294
2295 if (max98095->headphone_jack || max98095->mic_jack)
2296 max98095_jack_detect_disable(codec);
2297
2179 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF); 2298 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF);
2180 2299
2181 return 0; 2300 return 0;
@@ -2183,8 +2302,16 @@ static int max98095_suspend(struct snd_soc_codec *codec)
2183 2302
2184static int max98095_resume(struct snd_soc_codec *codec) 2303static int max98095_resume(struct snd_soc_codec *codec)
2185{ 2304{
2305 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2306 struct i2c_client *client = to_i2c_client(codec->dev);
2307
2186 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2308 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2187 2309
2310 if (max98095->headphone_jack || max98095->mic_jack) {
2311 max98095_jack_detect_enable(codec);
2312 max98095_report_jack(client->irq, codec);
2313 }
2314
2188 return 0; 2315 return 0;
2189} 2316}
2190#else 2317#else
@@ -2227,6 +2354,7 @@ static int max98095_probe(struct snd_soc_codec *codec)
2227{ 2354{
2228 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2355 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2229 struct max98095_cdata *cdata; 2356 struct max98095_cdata *cdata;
2357 struct i2c_client *client;
2230 int ret = 0; 2358 int ret = 0;
2231 2359
2232 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); 2360 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
@@ -2238,6 +2366,8 @@ static int max98095_probe(struct snd_soc_codec *codec)
2238 /* reset the codec, the DSP core, and disable all interrupts */ 2366 /* reset the codec, the DSP core, and disable all interrupts */
2239 max98095_reset(codec); 2367 max98095_reset(codec);
2240 2368
2369 client = to_i2c_client(codec->dev);
2370
2241 /* initialize private data */ 2371 /* initialize private data */
2242 2372
2243 max98095->sysclk = (unsigned)-1; 2373 max98095->sysclk = (unsigned)-1;
@@ -2266,11 +2396,23 @@ static int max98095_probe(struct snd_soc_codec *codec)
2266 max98095->mic1pre = 0; 2396 max98095->mic1pre = 0;
2267 max98095->mic2pre = 0; 2397 max98095->mic2pre = 0;
2268 2398
2399 if (client->irq) {
2400 /* register an audio interrupt */
2401 ret = request_threaded_irq(client->irq, NULL,
2402 max98095_report_jack,
2403 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2404 "max98095", codec);
2405 if (ret) {
2406 dev_err(codec->dev, "Failed to request IRQ: %d\n", ret);
2407 goto err_access;
2408 }
2409 }
2410
2269 ret = snd_soc_read(codec, M98095_0FF_REV_ID); 2411 ret = snd_soc_read(codec, M98095_0FF_REV_ID);
2270 if (ret < 0) { 2412 if (ret < 0) {
2271 dev_err(codec->dev, "Failure reading hardware revision: %d\n", 2413 dev_err(codec->dev, "Failure reading hardware revision: %d\n",
2272 ret); 2414 ret);
2273 goto err_access; 2415 goto err_irq;
2274 } 2416 }
2275 dev_info(codec->dev, "Hardware revision: %c\n", ret - 0x40 + 'A'); 2417 dev_info(codec->dev, "Hardware revision: %c\n", ret - 0x40 + 'A');
2276 2418
@@ -2306,14 +2448,28 @@ static int max98095_probe(struct snd_soc_codec *codec)
2306 2448
2307 max98095_add_widgets(codec); 2449 max98095_add_widgets(codec);
2308 2450
2451 return 0;
2452
2453err_irq:
2454 if (client->irq)
2455 free_irq(client->irq, codec);
2309err_access: 2456err_access:
2310 return ret; 2457 return ret;
2311} 2458}
2312 2459
2313static int max98095_remove(struct snd_soc_codec *codec) 2460static int max98095_remove(struct snd_soc_codec *codec)
2314{ 2461{
2462 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
2463 struct i2c_client *client = to_i2c_client(codec->dev);
2464
2315 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF); 2465 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF);
2316 2466
2467 if (max98095->headphone_jack || max98095->mic_jack)
2468 max98095_jack_detect_disable(codec);
2469
2470 if (client->irq)
2471 free_irq(client->irq, codec);
2472
2317 return 0; 2473 return 0;
2318} 2474}
2319 2475
diff --git a/sound/soc/codecs/max98095.h b/sound/soc/codecs/max98095.h
index 891584a0eb03..2ebbe4e894bf 100644
--- a/sound/soc/codecs/max98095.h
+++ b/sound/soc/codecs/max98095.h
@@ -175,11 +175,23 @@
175 175
176/* MAX98095 Registers Bit Fields */ 176/* MAX98095 Registers Bit Fields */
177 177
178/* M98095_007_JACK_AUTO_STS */
179 #define M98095_MIC_IN (1<<3)
180 #define M98095_LO_IN (1<<5)
181 #define M98095_HP_IN (1<<6)
182 #define M98095_DDONE (1<<7)
183
178/* M98095_00F_HOST_CFG */ 184/* M98095_00F_HOST_CFG */
179 #define M98095_SEG (1<<0) 185 #define M98095_SEG (1<<0)
180 #define M98095_XTEN (1<<1) 186 #define M98095_XTEN (1<<1)
181 #define M98095_MDLLEN (1<<2) 187 #define M98095_MDLLEN (1<<2)
182 188
189/* M98095_013_JACK_INT_EN */
190 #define M98095_IMIC_IN (1<<3)
191 #define M98095_ILO_IN (1<<5)
192 #define M98095_IHP_IN (1<<6)
193 #define M98095_IDDONE (1<<7)
194
183/* M98095_027_DAI1_CLKMODE, M98095_031_DAI2_CLKMODE, M98095_03B_DAI3_CLKMODE */ 195/* M98095_027_DAI1_CLKMODE, M98095_031_DAI2_CLKMODE, M98095_03B_DAI3_CLKMODE */
184 #define M98095_CLKMODE_MASK 0xFF 196 #define M98095_CLKMODE_MASK 0xFF
185 197
@@ -255,6 +267,10 @@
255 #define M98095_EQ2EN (1<<1) 267 #define M98095_EQ2EN (1<<1)
256 #define M98095_EQ1EN (1<<0) 268 #define M98095_EQ1EN (1<<0)
257 269
270/* M98095_089_JACK_DET_AUTO */
271 #define M98095_PIN5EN (1<<2)
272 #define M98095_JDEN (1<<7)
273
258/* M98095_090_PWR_EN_IN */ 274/* M98095_090_PWR_EN_IN */
259 #define M98095_INEN (1<<7) 275 #define M98095_INEN (1<<7)
260 #define M98095_MB2EN (1<<3) 276 #define M98095_MB2EN (1<<3)
@@ -296,4 +312,10 @@
296#define M98095_174_DAI1_BQ_BASE 0x74 312#define M98095_174_DAI1_BQ_BASE 0x74
297#define M98095_17E_DAI2_BQ_BASE 0x7E 313#define M98095_17E_DAI2_BQ_BASE 0x7E
298 314
315/* Default Delay used in Slew Rate Calculation for Jack detection */
316#define M98095_DEFAULT_SLEW_DELAY 0x18
317
318extern int max98095_jack_detect(struct snd_soc_codec *codec,
319 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack);
320
299#endif 321#endif
diff --git a/sound/soc/codecs/mc13783.c b/sound/soc/codecs/mc13783.c
new file mode 100644
index 000000000000..6276e352125f
--- /dev/null
+++ b/sound/soc/codecs/mc13783.c
@@ -0,0 +1,786 @@
1/*
2 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
3 * Copyright 2009 Sascha Hauer, s.hauer@pengutronix.de
4 * Copyright 2012 Philippe Retornaz, philippe.retornaz@epfl.ch
5 *
6 * Initial development of this code was funded by
7 * Phytec Messtechnik GmbH, http://www.phytec.de
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21 * MA 02110-1301, USA.
22 */
23#include <linux/module.h>
24#include <linux/device.h>
25#include <linux/mfd/mc13xxx.h>
26#include <linux/slab.h>
27#include <sound/core.h>
28#include <sound/control.h>
29#include <sound/pcm.h>
30#include <sound/soc.h>
31#include <sound/initval.h>
32#include <sound/soc-dapm.h>
33
34#include "mc13783.h"
35
36#define MC13783_AUDIO_RX0 36
37#define MC13783_AUDIO_RX1 37
38#define MC13783_AUDIO_TX 38
39#define MC13783_SSI_NETWORK 39
40#define MC13783_AUDIO_CODEC 40
41#define MC13783_AUDIO_DAC 41
42
43#define AUDIO_RX0_ALSPEN (1 << 5)
44#define AUDIO_RX0_ALSPSEL (1 << 7)
45#define AUDIO_RX0_ADDCDC (1 << 21)
46#define AUDIO_RX0_ADDSTDC (1 << 22)
47#define AUDIO_RX0_ADDRXIN (1 << 23)
48
49#define AUDIO_RX1_PGARXEN (1 << 0);
50#define AUDIO_RX1_PGASTEN (1 << 5)
51#define AUDIO_RX1_ARXINEN (1 << 10)
52
53#define AUDIO_TX_AMC1REN (1 << 5)
54#define AUDIO_TX_AMC1LEN (1 << 7)
55#define AUDIO_TX_AMC2EN (1 << 9)
56#define AUDIO_TX_ATXINEN (1 << 11)
57#define AUDIO_TX_RXINREC (1 << 13)
58
59#define SSI_NETWORK_CDCTXRXSLOT(x) (((x) & 0x3) << 2)
60#define SSI_NETWORK_CDCTXSECSLOT(x) (((x) & 0x3) << 4)
61#define SSI_NETWORK_CDCRXSECSLOT(x) (((x) & 0x3) << 6)
62#define SSI_NETWORK_CDCRXSECGAIN(x) (((x) & 0x3) << 8)
63#define SSI_NETWORK_CDCSUMGAIN(x) (1 << 10)
64#define SSI_NETWORK_CDCFSDLY(x) (1 << 11)
65#define SSI_NETWORK_DAC_SLOTS_8 (1 << 12)
66#define SSI_NETWORK_DAC_SLOTS_4 (2 << 12)
67#define SSI_NETWORK_DAC_SLOTS_2 (3 << 12)
68#define SSI_NETWORK_DAC_SLOT_MASK (3 << 12)
69#define SSI_NETWORK_DAC_RXSLOT_0_1 (0 << 14)
70#define SSI_NETWORK_DAC_RXSLOT_2_3 (1 << 14)
71#define SSI_NETWORK_DAC_RXSLOT_4_5 (2 << 14)
72#define SSI_NETWORK_DAC_RXSLOT_6_7 (3 << 14)
73#define SSI_NETWORK_DAC_RXSLOT_MASK (3 << 14)
74#define SSI_NETWORK_STDCRXSECSLOT(x) (((x) & 0x3) << 16)
75#define SSI_NETWORK_STDCRXSECGAIN(x) (((x) & 0x3) << 18)
76#define SSI_NETWORK_STDCSUMGAIN (1 << 20)
77
78/*
79 * MC13783_AUDIO_CODEC and MC13783_AUDIO_DAC mostly share the same
80 * register layout
81 */
82#define AUDIO_SSI_SEL (1 << 0)
83#define AUDIO_CLK_SEL (1 << 1)
84#define AUDIO_CSM (1 << 2)
85#define AUDIO_BCL_INV (1 << 3)
86#define AUDIO_CFS_INV (1 << 4)
87#define AUDIO_CFS(x) (((x) & 0x3) << 5)
88#define AUDIO_CLK(x) (((x) & 0x7) << 7)
89#define AUDIO_C_EN (1 << 11)
90#define AUDIO_C_CLK_EN (1 << 12)
91#define AUDIO_C_RESET (1 << 15)
92
93#define AUDIO_CODEC_CDCFS8K16K (1 << 10)
94#define AUDIO_DAC_CFS_DLY_B (1 << 10)
95
96struct mc13783_priv {
97 struct snd_soc_codec codec;
98 struct mc13xxx *mc13xxx;
99
100 enum mc13783_ssi_port adc_ssi_port;
101 enum mc13783_ssi_port dac_ssi_port;
102};
103
104static unsigned int mc13783_read(struct snd_soc_codec *codec,
105 unsigned int reg)
106{
107 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
108 unsigned int value = 0;
109
110 mc13xxx_lock(priv->mc13xxx);
111
112 mc13xxx_reg_read(priv->mc13xxx, reg, &value);
113
114 mc13xxx_unlock(priv->mc13xxx);
115
116 return value;
117}
118
119static int mc13783_write(struct snd_soc_codec *codec,
120 unsigned int reg, unsigned int value)
121{
122 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
123 int ret;
124
125 mc13xxx_lock(priv->mc13xxx);
126
127 ret = mc13xxx_reg_write(priv->mc13xxx, reg, value);
128
129 mc13xxx_unlock(priv->mc13xxx);
130
131 return ret;
132}
133
134/* Mapping between sample rates and register value */
135static unsigned int mc13783_rates[] = {
136 8000, 11025, 12000, 16000,
137 22050, 24000, 32000, 44100,
138 48000, 64000, 96000
139};
140
141static int mc13783_pcm_hw_params_dac(struct snd_pcm_substream *substream,
142 struct snd_pcm_hw_params *params,
143 struct snd_soc_dai *dai)
144{
145 struct snd_soc_pcm_runtime *rtd = substream->private_data;
146 struct snd_soc_codec *codec = rtd->codec;
147 unsigned int rate = params_rate(params);
148 int i;
149
150 for (i = 0; i < ARRAY_SIZE(mc13783_rates); i++) {
151 if (rate == mc13783_rates[i]) {
152 snd_soc_update_bits(codec, MC13783_AUDIO_DAC,
153 0xf << 17, i << 17);
154 return 0;
155 }
156 }
157
158 return -EINVAL;
159}
160
161static int mc13783_pcm_hw_params_codec(struct snd_pcm_substream *substream,
162 struct snd_pcm_hw_params *params,
163 struct snd_soc_dai *dai)
164{
165 struct snd_soc_pcm_runtime *rtd = substream->private_data;
166 struct snd_soc_codec *codec = rtd->codec;
167 unsigned int rate = params_rate(params);
168 unsigned int val;
169
170 switch (rate) {
171 case 8000:
172 val = 0;
173 break;
174 case 16000:
175 val = AUDIO_CODEC_CDCFS8K16K;
176 break;
177 default:
178 return -EINVAL;
179 }
180
181 snd_soc_update_bits(codec, MC13783_AUDIO_CODEC, AUDIO_CODEC_CDCFS8K16K,
182 val);
183
184 return 0;
185}
186
187static int mc13783_pcm_hw_params_sync(struct snd_pcm_substream *substream,
188 struct snd_pcm_hw_params *params,
189 struct snd_soc_dai *dai)
190{
191 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
192 return mc13783_pcm_hw_params_dac(substream, params, dai);
193 else
194 return mc13783_pcm_hw_params_codec(substream, params, dai);
195}
196
197static int mc13783_set_fmt(struct snd_soc_dai *dai, unsigned int fmt,
198 unsigned int reg)
199{
200 struct snd_soc_codec *codec = dai->codec;
201 unsigned int val = 0;
202 unsigned int mask = AUDIO_CFS(3) | AUDIO_BCL_INV | AUDIO_CFS_INV |
203 AUDIO_CSM | AUDIO_C_CLK_EN | AUDIO_C_RESET;
204
205
206 /* DAI mode */
207 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
208 case SND_SOC_DAIFMT_I2S:
209 val |= AUDIO_CFS(2);
210 break;
211 case SND_SOC_DAIFMT_DSP_A:
212 val |= AUDIO_CFS(1);
213 break;
214 default:
215 return -EINVAL;
216 }
217
218 /* DAI clock inversion */
219 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
220 case SND_SOC_DAIFMT_NB_NF:
221 val |= AUDIO_BCL_INV;
222 break;
223 case SND_SOC_DAIFMT_NB_IF:
224 val |= AUDIO_BCL_INV | AUDIO_CFS_INV;
225 break;
226 case SND_SOC_DAIFMT_IB_NF:
227 break;
228 case SND_SOC_DAIFMT_IB_IF:
229 val |= AUDIO_CFS_INV;
230 break;
231 }
232
233 /* DAI clock master masks */
234 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
235 case SND_SOC_DAIFMT_CBM_CFM:
236 val |= AUDIO_C_CLK_EN;
237 break;
238 case SND_SOC_DAIFMT_CBS_CFS:
239 val |= AUDIO_CSM;
240 break;
241 case SND_SOC_DAIFMT_CBM_CFS:
242 case SND_SOC_DAIFMT_CBS_CFM:
243 return -EINVAL;
244 }
245
246 val |= AUDIO_C_RESET;
247
248 snd_soc_update_bits(codec, reg, mask, val);
249
250 return 0;
251}
252
253static int mc13783_set_fmt_async(struct snd_soc_dai *dai, unsigned int fmt)
254{
255 if (dai->id == MC13783_ID_STEREO_DAC)
256 return mc13783_set_fmt(dai, fmt, MC13783_AUDIO_DAC);
257 else
258 return mc13783_set_fmt(dai, fmt, MC13783_AUDIO_CODEC);
259}
260
261static int mc13783_set_fmt_sync(struct snd_soc_dai *dai, unsigned int fmt)
262{
263 int ret;
264
265 ret = mc13783_set_fmt(dai, fmt, MC13783_AUDIO_DAC);
266 if (ret)
267 return ret;
268
269 /*
270 * In synchronous mode force the voice codec into slave mode
271 * so that the clock / framesync from the stereo DAC is used
272 */
273 fmt &= ~SND_SOC_DAIFMT_MASTER_MASK;
274 fmt |= SND_SOC_DAIFMT_CBS_CFS;
275 ret = mc13783_set_fmt(dai, fmt, MC13783_AUDIO_CODEC);
276
277 return ret;
278}
279
280static int mc13783_sysclk[] = {
281 13000000,
282 15360000,
283 16800000,
284 -1,
285 26000000,
286 -1, /* 12000000, invalid for voice codec */
287 -1, /* 3686400, invalid for voice codec */
288 33600000,
289};
290
291static int mc13783_set_sysclk(struct snd_soc_dai *dai,
292 int clk_id, unsigned int freq, int dir,
293 unsigned int reg)
294{
295 struct snd_soc_codec *codec = dai->codec;
296 int clk;
297 unsigned int val = 0;
298 unsigned int mask = AUDIO_CLK(0x7) | AUDIO_CLK_SEL;
299
300 for (clk = 0; clk < ARRAY_SIZE(mc13783_sysclk); clk++) {
301 if (mc13783_sysclk[clk] < 0)
302 continue;
303 if (mc13783_sysclk[clk] == freq)
304 break;
305 }
306
307 if (clk == ARRAY_SIZE(mc13783_sysclk))
308 return -EINVAL;
309
310 if (clk_id == MC13783_CLK_CLIB)
311 val |= AUDIO_CLK_SEL;
312
313 val |= AUDIO_CLK(clk);
314
315 snd_soc_update_bits(codec, reg, mask, val);
316
317 return 0;
318}
319
320static int mc13783_set_sysclk_dac(struct snd_soc_dai *dai,
321 int clk_id, unsigned int freq, int dir)
322{
323 return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_DAC);
324}
325
326static int mc13783_set_sysclk_codec(struct snd_soc_dai *dai,
327 int clk_id, unsigned int freq, int dir)
328{
329 return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_CODEC);
330}
331
332static int mc13783_set_sysclk_sync(struct snd_soc_dai *dai,
333 int clk_id, unsigned int freq, int dir)
334{
335 int ret;
336
337 ret = mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_DAC);
338 if (ret)
339 return ret;
340
341 return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_CODEC);
342}
343
344static int mc13783_set_tdm_slot_dac(struct snd_soc_dai *dai,
345 unsigned int tx_mask, unsigned int rx_mask, int slots,
346 int slot_width)
347{
348 struct snd_soc_codec *codec = dai->codec;
349 unsigned int val = 0;
350 unsigned int mask = SSI_NETWORK_DAC_SLOT_MASK |
351 SSI_NETWORK_DAC_RXSLOT_MASK;
352
353 switch (slots) {
354 case 2:
355 val |= SSI_NETWORK_DAC_SLOTS_2;
356 break;
357 case 4:
358 val |= SSI_NETWORK_DAC_SLOTS_4;
359 break;
360 case 8:
361 val |= SSI_NETWORK_DAC_SLOTS_8;
362 break;
363 default:
364 return -EINVAL;
365 }
366
367 switch (rx_mask) {
368 case 0xfffffffc:
369 val |= SSI_NETWORK_DAC_RXSLOT_0_1;
370 break;
371 case 0xfffffff3:
372 val |= SSI_NETWORK_DAC_RXSLOT_2_3;
373 break;
374 case 0xffffffcf:
375 val |= SSI_NETWORK_DAC_RXSLOT_4_5;
376 break;
377 case 0xffffff3f:
378 val |= SSI_NETWORK_DAC_RXSLOT_6_7;
379 break;
380 default:
381 return -EINVAL;
382 };
383
384 snd_soc_update_bits(codec, MC13783_SSI_NETWORK, mask, val);
385
386 return 0;
387}
388
389static int mc13783_set_tdm_slot_codec(struct snd_soc_dai *dai,
390 unsigned int tx_mask, unsigned int rx_mask, int slots,
391 int slot_width)
392{
393 struct snd_soc_codec *codec = dai->codec;
394 unsigned int val = 0;
395 unsigned int mask = 0x3f;
396
397 if (slots != 4)
398 return -EINVAL;
399
400 if (tx_mask != 0xfffffffc)
401 return -EINVAL;
402
403 val |= (0x00 << 2); /* primary timeslot RX/TX(?) is 0 */
404 val |= (0x01 << 4); /* secondary timeslot TX is 1 */
405
406 snd_soc_update_bits(codec, MC13783_SSI_NETWORK, mask, val);
407
408 return 0;
409}
410
411static int mc13783_set_tdm_slot_sync(struct snd_soc_dai *dai,
412 unsigned int tx_mask, unsigned int rx_mask, int slots,
413 int slot_width)
414{
415 int ret;
416
417 ret = mc13783_set_tdm_slot_dac(dai, tx_mask, rx_mask, slots,
418 slot_width);
419 if (ret)
420 return ret;
421
422 ret = mc13783_set_tdm_slot_codec(dai, tx_mask, rx_mask, slots,
423 slot_width);
424
425 return ret;
426}
427
428static const struct snd_kcontrol_new mc1l_amp_ctl =
429 SOC_DAPM_SINGLE("Switch", 38, 7, 1, 0);
430
431static const struct snd_kcontrol_new mc1r_amp_ctl =
432 SOC_DAPM_SINGLE("Switch", 38, 5, 1, 0);
433
434static const struct snd_kcontrol_new mc2_amp_ctl =
435 SOC_DAPM_SINGLE("Switch", 38, 9, 1, 0);
436
437static const struct snd_kcontrol_new atx_amp_ctl =
438 SOC_DAPM_SINGLE("Switch", 38, 11, 1, 0);
439
440
441/* Virtual mux. The chip does the input selection automatically
442 * as soon as we enable one input. */
443static const char * const adcl_enum_text[] = {
444 "MC1L", "RXINL",
445};
446
447static const struct soc_enum adcl_enum =
448 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(adcl_enum_text), adcl_enum_text);
449
450static const struct snd_kcontrol_new left_input_mux =
451 SOC_DAPM_ENUM_VIRT("Route", adcl_enum);
452
453static const char * const adcr_enum_text[] = {
454 "MC1R", "MC2", "RXINR", "TXIN",
455};
456
457static const struct soc_enum adcr_enum =
458 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(adcr_enum_text), adcr_enum_text);
459
460static const struct snd_kcontrol_new right_input_mux =
461 SOC_DAPM_ENUM_VIRT("Route", adcr_enum);
462
463static const struct snd_kcontrol_new samp_ctl =
464 SOC_DAPM_SINGLE("Switch", 36, 3, 1, 0);
465
466static const struct snd_kcontrol_new lamp_ctl =
467 SOC_DAPM_SINGLE("Switch", 36, 5, 1, 0);
468
469static const struct snd_kcontrol_new hlamp_ctl =
470 SOC_DAPM_SINGLE("Switch", 36, 10, 1, 0);
471
472static const struct snd_kcontrol_new hramp_ctl =
473 SOC_DAPM_SINGLE("Switch", 36, 9, 1, 0);
474
475static const struct snd_kcontrol_new llamp_ctl =
476 SOC_DAPM_SINGLE("Switch", 36, 16, 1, 0);
477
478static const struct snd_kcontrol_new lramp_ctl =
479 SOC_DAPM_SINGLE("Switch", 36, 15, 1, 0);
480
481static const struct snd_soc_dapm_widget mc13783_dapm_widgets[] = {
482/* Input */
483 SND_SOC_DAPM_INPUT("MC1LIN"),
484 SND_SOC_DAPM_INPUT("MC1RIN"),
485 SND_SOC_DAPM_INPUT("MC2IN"),
486 SND_SOC_DAPM_INPUT("RXINR"),
487 SND_SOC_DAPM_INPUT("RXINL"),
488 SND_SOC_DAPM_INPUT("TXIN"),
489
490 SND_SOC_DAPM_SUPPLY("MC1 Bias", 38, 0, 0, NULL, 0),
491 SND_SOC_DAPM_SUPPLY("MC2 Bias", 38, 1, 0, NULL, 0),
492
493 SND_SOC_DAPM_SWITCH("MC1L Amp", 38, 7, 0, &mc1l_amp_ctl),
494 SND_SOC_DAPM_SWITCH("MC1R Amp", 38, 5, 0, &mc1r_amp_ctl),
495 SND_SOC_DAPM_SWITCH("MC2 Amp", 38, 9, 0, &mc2_amp_ctl),
496 SND_SOC_DAPM_SWITCH("TXIN Amp", 38, 11, 0, &atx_amp_ctl),
497
498 SND_SOC_DAPM_VIRT_MUX("PGA Left Input Mux", SND_SOC_NOPM, 0, 0,
499 &left_input_mux),
500 SND_SOC_DAPM_VIRT_MUX("PGA Right Input Mux", SND_SOC_NOPM, 0, 0,
501 &right_input_mux),
502
503 SND_SOC_DAPM_PGA("PGA Left Input", SND_SOC_NOPM, 0, 0, NULL, 0),
504 SND_SOC_DAPM_PGA("PGA Right Input", SND_SOC_NOPM, 0, 0, NULL, 0),
505
506 SND_SOC_DAPM_ADC("ADC", "Capture", 40, 11, 0),
507 SND_SOC_DAPM_SUPPLY("ADC_Reset", 40, 15, 0, NULL, 0),
508
509/* Output */
510 SND_SOC_DAPM_SUPPLY("DAC_E", 41, 11, 0, NULL, 0),
511 SND_SOC_DAPM_SUPPLY("DAC_Reset", 41, 15, 0, NULL, 0),
512 SND_SOC_DAPM_OUTPUT("RXOUTL"),
513 SND_SOC_DAPM_OUTPUT("RXOUTR"),
514 SND_SOC_DAPM_OUTPUT("HSL"),
515 SND_SOC_DAPM_OUTPUT("HSR"),
516 SND_SOC_DAPM_OUTPUT("LSP"),
517 SND_SOC_DAPM_OUTPUT("SP"),
518
519 SND_SOC_DAPM_SWITCH("Speaker Amp", 36, 3, 0, &samp_ctl),
520 SND_SOC_DAPM_SWITCH("Loudspeaker Amp", SND_SOC_NOPM, 0, 0, &lamp_ctl),
521 SND_SOC_DAPM_SWITCH("Headset Amp Left", 36, 10, 0, &hlamp_ctl),
522 SND_SOC_DAPM_SWITCH("Headset Amp Right", 36, 9, 0, &hramp_ctl),
523 SND_SOC_DAPM_SWITCH("Line out Amp Left", 36, 16, 0, &llamp_ctl),
524 SND_SOC_DAPM_SWITCH("Line out Amp Right", 36, 15, 0, &lramp_ctl),
525 SND_SOC_DAPM_DAC("DAC", "Playback", 36, 22, 0),
526 SND_SOC_DAPM_PGA("DAC PGA", 37, 5, 0, NULL, 0),
527};
528
529static struct snd_soc_dapm_route mc13783_routes[] = {
530/* Input */
531 { "MC1L Amp", NULL, "MC1LIN"},
532 { "MC1R Amp", NULL, "MC1RIN" },
533 { "MC2 Amp", NULL, "MC2IN" },
534 { "TXIN Amp", NULL, "TXIN"},
535
536 { "PGA Left Input Mux", "MC1L", "MC1L Amp" },
537 { "PGA Left Input Mux", "RXINL", "RXINL"},
538 { "PGA Right Input Mux", "MC1R", "MC1R Amp" },
539 { "PGA Right Input Mux", "MC2", "MC2 Amp"},
540 { "PGA Right Input Mux", "TXIN", "TXIN Amp"},
541 { "PGA Right Input Mux", "RXINR", "RXINR"},
542
543 { "PGA Left Input", NULL, "PGA Left Input Mux"},
544 { "PGA Right Input", NULL, "PGA Right Input Mux"},
545
546 { "ADC", NULL, "PGA Left Input"},
547 { "ADC", NULL, "PGA Right Input"},
548 { "ADC", NULL, "ADC_Reset"},
549
550/* Output */
551 { "HSL", NULL, "Headset Amp Left" },
552 { "HSR", NULL, "Headset Amp Right"},
553 { "RXOUTL", NULL, "Line out Amp Left"},
554 { "RXOUTR", NULL, "Line out Amp Right"},
555 { "SP", NULL, "Speaker Amp"},
556 { "Speaker Amp", NULL, "DAC PGA"},
557 { "LSP", NULL, "DAC PGA"},
558 { "Headset Amp Left", NULL, "DAC PGA"},
559 { "Headset Amp Right", NULL, "DAC PGA"},
560 { "Line out Amp Left", NULL, "DAC PGA"},
561 { "Line out Amp Right", NULL, "DAC PGA"},
562 { "DAC PGA", NULL, "DAC"},
563 { "DAC", NULL, "DAC_E"},
564};
565
566static const char * const mc13783_3d_mixer[] = {"Stereo", "Phase Mix",
567 "Mono", "Mono Mix"};
568
569static const struct soc_enum mc13783_enum_3d_mixer =
570 SOC_ENUM_SINGLE(MC13783_AUDIO_RX1, 16, ARRAY_SIZE(mc13783_3d_mixer),
571 mc13783_3d_mixer);
572
573static struct snd_kcontrol_new mc13783_control_list[] = {
574 SOC_SINGLE("Loudspeaker enable", MC13783_AUDIO_RX0, 5, 1, 0),
575 SOC_SINGLE("PCM Playback Volume", MC13783_AUDIO_RX1, 6, 15, 0),
576 SOC_DOUBLE("PCM Capture Volume", MC13783_AUDIO_TX, 19, 14, 31, 0),
577 SOC_ENUM("3D Control", mc13783_enum_3d_mixer),
578};
579
580static int mc13783_probe(struct snd_soc_codec *codec)
581{
582 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
583
584 mc13xxx_lock(priv->mc13xxx);
585
586 /* these are the reset values */
587 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893);
588 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX1, 0x00d35A);
589 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_TX, 0x420000);
590 mc13xxx_reg_write(priv->mc13xxx, MC13783_SSI_NETWORK, 0x013060);
591 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_CODEC, 0x180027);
592 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_DAC, 0x0e0004);
593
594 if (priv->adc_ssi_port == MC13783_SSI1_PORT)
595 mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_CODEC,
596 AUDIO_SSI_SEL, 0);
597 else
598 mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_CODEC,
599 0, AUDIO_SSI_SEL);
600
601 if (priv->dac_ssi_port == MC13783_SSI1_PORT)
602 mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_DAC,
603 AUDIO_SSI_SEL, 0);
604 else
605 mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_DAC,
606 0, AUDIO_SSI_SEL);
607
608 mc13xxx_unlock(priv->mc13xxx);
609
610 return 0;
611}
612
613static int mc13783_remove(struct snd_soc_codec *codec)
614{
615 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
616
617 mc13xxx_lock(priv->mc13xxx);
618
619 /* Make sure VAUDIOON is off */
620 mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_RX0, 0x3, 0);
621
622 mc13xxx_unlock(priv->mc13xxx);
623
624 return 0;
625}
626
627#define MC13783_RATES_RECORD (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000)
628
629#define MC13783_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
630 SNDRV_PCM_FMTBIT_S24_LE)
631
632static struct snd_soc_dai_ops mc13783_ops_dac = {
633 .hw_params = mc13783_pcm_hw_params_dac,
634 .set_fmt = mc13783_set_fmt_async,
635 .set_sysclk = mc13783_set_sysclk_dac,
636 .set_tdm_slot = mc13783_set_tdm_slot_dac,
637};
638
639static struct snd_soc_dai_ops mc13783_ops_codec = {
640 .hw_params = mc13783_pcm_hw_params_codec,
641 .set_fmt = mc13783_set_fmt_async,
642 .set_sysclk = mc13783_set_sysclk_codec,
643 .set_tdm_slot = mc13783_set_tdm_slot_codec,
644};
645
646/*
647 * The mc13783 has two SSI ports, both of them can be routed either
648 * to the voice codec or the stereo DAC. When two different SSI ports
649 * are used for the voice codec and the stereo DAC we can do different
650 * formats and sysclock settings for playback and capture
651 * (mc13783-hifi-playback and mc13783-hifi-capture). Using the same port
652 * forces us to use symmetric rates (mc13783-hifi).
653 */
654static struct snd_soc_dai_driver mc13783_dai_async[] = {
655 {
656 .name = "mc13783-hifi-playback",
657 .id = MC13783_ID_STEREO_DAC,
658 .playback = {
659 .stream_name = "Playback",
660 .channels_min = 1,
661 .channels_max = 2,
662 .rates = SNDRV_PCM_RATE_8000_96000,
663 .formats = MC13783_FORMATS,
664 },
665 .ops = &mc13783_ops_dac,
666 }, {
667 .name = "mc13783-hifi-capture",
668 .id = MC13783_ID_STEREO_CODEC,
669 .capture = {
670 .stream_name = "Capture",
671 .channels_min = 1,
672 .channels_max = 2,
673 .rates = MC13783_RATES_RECORD,
674 .formats = MC13783_FORMATS,
675 },
676 .ops = &mc13783_ops_codec,
677 },
678};
679
680static struct snd_soc_dai_ops mc13783_ops_sync = {
681 .hw_params = mc13783_pcm_hw_params_sync,
682 .set_fmt = mc13783_set_fmt_sync,
683 .set_sysclk = mc13783_set_sysclk_sync,
684 .set_tdm_slot = mc13783_set_tdm_slot_sync,
685};
686
687static struct snd_soc_dai_driver mc13783_dai_sync[] = {
688 {
689 .name = "mc13783-hifi",
690 .id = MC13783_ID_SYNC,
691 .playback = {
692 .stream_name = "Playback",
693 .channels_min = 1,
694 .channels_max = 2,
695 .rates = SNDRV_PCM_RATE_8000_96000,
696 .formats = MC13783_FORMATS,
697 },
698 .capture = {
699 .stream_name = "Capture",
700 .channels_min = 1,
701 .channels_max = 2,
702 .rates = MC13783_RATES_RECORD,
703 .formats = MC13783_FORMATS,
704 },
705 .ops = &mc13783_ops_sync,
706 .symmetric_rates = 1,
707 }
708};
709
710static struct snd_soc_codec_driver soc_codec_dev_mc13783 = {
711 .probe = mc13783_probe,
712 .remove = mc13783_remove,
713 .read = mc13783_read,
714 .write = mc13783_write,
715 .controls = mc13783_control_list,
716 .num_controls = ARRAY_SIZE(mc13783_control_list),
717 .dapm_widgets = mc13783_dapm_widgets,
718 .num_dapm_widgets = ARRAY_SIZE(mc13783_dapm_widgets),
719 .dapm_routes = mc13783_routes,
720 .num_dapm_routes = ARRAY_SIZE(mc13783_routes),
721};
722
723static int mc13783_codec_probe(struct platform_device *pdev)
724{
725 struct mc13xxx *mc13xxx;
726 struct mc13783_priv *priv;
727 struct mc13xxx_codec_platform_data *pdata = pdev->dev.platform_data;
728 int ret;
729
730 mc13xxx = dev_get_drvdata(pdev->dev.parent);
731
732
733 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
734 if (priv == NULL)
735 return -ENOMEM;
736
737 dev_set_drvdata(&pdev->dev, priv);
738 priv->mc13xxx = mc13xxx;
739 if (pdata) {
740 priv->adc_ssi_port = pdata->adc_ssi_port;
741 priv->dac_ssi_port = pdata->dac_ssi_port;
742 } else {
743 priv->adc_ssi_port = MC13783_SSI1_PORT;
744 priv->dac_ssi_port = MC13783_SSI2_PORT;
745 }
746
747 if (priv->adc_ssi_port == priv->dac_ssi_port)
748 ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_mc13783,
749 mc13783_dai_sync, ARRAY_SIZE(mc13783_dai_sync));
750 else
751 ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_mc13783,
752 mc13783_dai_async, ARRAY_SIZE(mc13783_dai_async));
753
754 if (ret)
755 goto err_register_codec;
756
757 return 0;
758
759err_register_codec:
760 dev_err(&pdev->dev, "register codec failed with %d\n", ret);
761
762 return ret;
763}
764
765static int mc13783_codec_remove(struct platform_device *pdev)
766{
767 snd_soc_unregister_codec(&pdev->dev);
768
769 return 0;
770}
771
772static struct platform_driver mc13783_codec_driver = {
773 .driver = {
774 .name = "mc13783-codec",
775 .owner = THIS_MODULE,
776 },
777 .probe = mc13783_codec_probe,
778 .remove = __devexit_p(mc13783_codec_remove),
779};
780
781module_platform_driver(mc13783_codec_driver);
782
783MODULE_DESCRIPTION("ASoC MC13783 driver");
784MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
785MODULE_AUTHOR("Philippe Retornaz <philippe.retornaz@epfl.ch>");
786MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/mc13783.h b/sound/soc/codecs/mc13783.h
new file mode 100644
index 000000000000..3a6d1993a217
--- /dev/null
+++ b/sound/soc/codecs/mc13783.h
@@ -0,0 +1,28 @@
1/*
2 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software Foundation, Inc.
15 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
16 */
17
18#ifndef MC13783_MIXER_H
19#define MC13783_MIXER_H
20
21#define MC13783_CLK_CLIA 1
22#define MC13783_CLK_CLIB 2
23
24#define MC13783_ID_STEREO_DAC 1
25#define MC13783_ID_STEREO_CODEC 2
26#define MC13783_ID_SYNC 3
27
28#endif /* MC13783_MIXER_H */
diff --git a/sound/soc/codecs/ml26124.c b/sound/soc/codecs/ml26124.c
new file mode 100644
index 000000000000..22cb5bf59273
--- /dev/null
+++ b/sound/soc/codecs/ml26124.c
@@ -0,0 +1,681 @@
1/*
2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
21#include <linux/delay.h>
22#include <linux/pm.h>
23#include <linux/i2c.h>
24#include <linux/slab.h>
25#include <linux/platform_device.h>
26#include <linux/regmap.h>
27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/tlv.h>
32#include "ml26124.h"
33
34#define DVOL_CTL_DVMUTE_ON BIT(4) /* Digital volume MUTE On */
35#define DVOL_CTL_DVMUTE_OFF 0 /* Digital volume MUTE Off */
36#define ML26124_SAI_NO_DELAY BIT(1)
37#define ML26124_SAI_FRAME_SYNC (BIT(5) | BIT(0)) /* For mono (Telecodec) */
38#define ML26134_CACHESIZE 212
39#define ML26124_VMID BIT(1)
40#define ML26124_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 |\
41 SNDRV_PCM_RATE_48000)
42#define ML26124_FORMATS (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |\
43 SNDRV_PCM_FMTBIT_S32_LE)
44#define ML26124_NUM_REGISTER ML26134_CACHESIZE
45
46struct ml26124_priv {
47 u32 mclk;
48 u32 rate;
49 struct regmap *regmap;
50 int clk_in;
51 struct snd_pcm_substream *substream;
52};
53
54struct clk_coeff {
55 u32 mclk;
56 u32 rate;
57 u8 pllnl;
58 u8 pllnh;
59 u8 pllml;
60 u8 pllmh;
61 u8 plldiv;
62};
63
64/* ML26124 configuration */
65static const DECLARE_TLV_DB_SCALE(digital_tlv, -7150, 50, 0);
66
67static const DECLARE_TLV_DB_SCALE(alclvl, -2250, 150, 0);
68static const DECLARE_TLV_DB_SCALE(mingain, -1200, 600, 0);
69static const DECLARE_TLV_DB_SCALE(maxgain, -675, 600, 0);
70static const DECLARE_TLV_DB_SCALE(boost_vol, -1200, 75, 0);
71static const DECLARE_TLV_DB_SCALE(ngth, -7650, 150, 0);
72
73static const char * const ml26124_companding[] = {"16bit PCM", "u-law",
74 "A-law"};
75
76static const struct soc_enum ml26124_adc_companding_enum
77 = SOC_ENUM_SINGLE(ML26124_SAI_TRANS_CTL, 6, 3, ml26124_companding);
78
79static const struct soc_enum ml26124_dac_companding_enum
80 = SOC_ENUM_SINGLE(ML26124_SAI_RCV_CTL, 6, 3, ml26124_companding);
81
82static const struct snd_kcontrol_new ml26124_snd_controls[] = {
83 SOC_SINGLE_TLV("Capture Digital Volume", ML26124_RECORD_DIG_VOL, 0,
84 0xff, 1, digital_tlv),
85 SOC_SINGLE_TLV("Playback Digital Volume", ML26124_PLBAK_DIG_VOL, 0,
86 0xff, 1, digital_tlv),
87 SOC_SINGLE_TLV("Digital Boost Volume", ML26124_DIGI_BOOST_VOL, 0,
88 0x3f, 0, boost_vol),
89 SOC_SINGLE_TLV("EQ Band0 Volume", ML26124_EQ_GAIN_BRAND0, 0,
90 0xff, 1, digital_tlv),
91 SOC_SINGLE_TLV("EQ Band1 Volume", ML26124_EQ_GAIN_BRAND1, 0,
92 0xff, 1, digital_tlv),
93 SOC_SINGLE_TLV("EQ Band2 Volume", ML26124_EQ_GAIN_BRAND2, 0,
94 0xff, 1, digital_tlv),
95 SOC_SINGLE_TLV("EQ Band3 Volume", ML26124_EQ_GAIN_BRAND3, 0,
96 0xff, 1, digital_tlv),
97 SOC_SINGLE_TLV("EQ Band4 Volume", ML26124_EQ_GAIN_BRAND4, 0,
98 0xff, 1, digital_tlv),
99 SOC_SINGLE_TLV("ALC Target Level", ML26124_ALC_TARGET_LEV, 0,
100 0xf, 1, alclvl),
101 SOC_SINGLE_TLV("ALC Min Input Volume", ML26124_ALC_MAXMIN_GAIN, 0,
102 7, 0, mingain),
103 SOC_SINGLE_TLV("ALC Max Input Volume", ML26124_ALC_MAXMIN_GAIN, 4,
104 7, 1, maxgain),
105 SOC_SINGLE_TLV("Playback Limiter Min Input Volume",
106 ML26124_PL_MAXMIN_GAIN, 0, 7, 0, mingain),
107 SOC_SINGLE_TLV("Playback Limiter Max Input Volume",
108 ML26124_PL_MAXMIN_GAIN, 4, 7, 1, maxgain),
109 SOC_SINGLE_TLV("Playback Boost Volume", ML26124_PLYBAK_BOST_VOL, 0,
110 0x3f, 0, boost_vol),
111 SOC_SINGLE("DC High Pass Filter Switch", ML26124_FILTER_EN, 0, 1, 0),
112 SOC_SINGLE("Noise High Pass Filter Switch", ML26124_FILTER_EN, 1, 1, 0),
113 SOC_SINGLE("ZC Switch", ML26124_PW_ZCCMP_PW_MNG, 1,
114 1, 0),
115 SOC_SINGLE("EQ Band0 Switch", ML26124_FILTER_EN, 2, 1, 0),
116 SOC_SINGLE("EQ Band1 Switch", ML26124_FILTER_EN, 3, 1, 0),
117 SOC_SINGLE("EQ Band2 Switch", ML26124_FILTER_EN, 4, 1, 0),
118 SOC_SINGLE("EQ Band3 Switch", ML26124_FILTER_EN, 5, 1, 0),
119 SOC_SINGLE("EQ Band4 Switch", ML26124_FILTER_EN, 6, 1, 0),
120 SOC_SINGLE("Play Limiter", ML26124_DVOL_CTL, 0, 1, 0),
121 SOC_SINGLE("Capture Limiter", ML26124_DVOL_CTL, 1, 1, 0),
122 SOC_SINGLE("Digital Volume Fade Switch", ML26124_DVOL_CTL, 3, 1, 0),
123 SOC_SINGLE("Digital Switch", ML26124_DVOL_CTL, 4, 1, 0),
124 SOC_ENUM("DAC Companding", ml26124_dac_companding_enum),
125 SOC_ENUM("ADC Companding", ml26124_adc_companding_enum),
126};
127
128static const struct snd_kcontrol_new ml26124_output_mixer_controls[] = {
129 SOC_DAPM_SINGLE("DAC Switch", ML26124_SPK_AMP_OUT, 1, 1, 0),
130 SOC_DAPM_SINGLE("Line in loopback Switch", ML26124_SPK_AMP_OUT, 3, 1,
131 0),
132 SOC_DAPM_SINGLE("PGA Switch", ML26124_SPK_AMP_OUT, 5, 1, 0),
133};
134
135/* Input mux */
136static const char * const ml26124_input_select[] = {"Analog MIC SingleEnded in",
137 "Digital MIC in", "Analog MIC Differential in"};
138
139static const struct soc_enum ml26124_insel_enum =
140 SOC_ENUM_SINGLE(ML26124_MIC_IF_CTL, 0, 3, ml26124_input_select);
141
142static const struct snd_kcontrol_new ml26124_input_mux_controls =
143 SOC_DAPM_ENUM("Input Select", ml26124_insel_enum);
144
145static const struct snd_kcontrol_new ml26124_line_control =
146 SOC_DAPM_SINGLE("Switch", ML26124_PW_LOUT_PW_MNG, 1, 1, 0);
147
148static const struct snd_soc_dapm_widget ml26124_dapm_widgets[] = {
149 SND_SOC_DAPM_SUPPLY("MCLKEN", ML26124_CLK_EN, 0, 0, NULL, 0),
150 SND_SOC_DAPM_SUPPLY("PLLEN", ML26124_CLK_EN, 1, 0, NULL, 0),
151 SND_SOC_DAPM_SUPPLY("PLLOE", ML26124_CLK_EN, 2, 0, NULL, 0),
152 SND_SOC_DAPM_SUPPLY("MICBIAS", ML26124_PW_REF_PW_MNG, 2, 0, NULL, 0),
153 SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
154 &ml26124_output_mixer_controls[0],
155 ARRAY_SIZE(ml26124_output_mixer_controls)),
156 SND_SOC_DAPM_DAC("DAC", "Playback", ML26124_PW_DAC_PW_MNG, 1, 0),
157 SND_SOC_DAPM_ADC("ADC", "Capture", ML26124_PW_IN_PW_MNG, 1, 0),
158 SND_SOC_DAPM_PGA("PGA", ML26124_PW_IN_PW_MNG, 3, 0, NULL, 0),
159 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
160 &ml26124_input_mux_controls),
161 SND_SOC_DAPM_SWITCH("Line Out Enable", SND_SOC_NOPM, 0, 0,
162 &ml26124_line_control),
163 SND_SOC_DAPM_INPUT("MDIN"),
164 SND_SOC_DAPM_INPUT("MIN"),
165 SND_SOC_DAPM_INPUT("LIN"),
166 SND_SOC_DAPM_OUTPUT("SPOUT"),
167 SND_SOC_DAPM_OUTPUT("LOUT"),
168};
169
170static const struct snd_soc_dapm_route ml26124_intercon[] = {
171 /* Supply */
172 {"DAC", NULL, "MCLKEN"},
173 {"ADC", NULL, "MCLKEN"},
174 {"DAC", NULL, "PLLEN"},
175 {"ADC", NULL, "PLLEN"},
176 {"DAC", NULL, "PLLOE"},
177 {"ADC", NULL, "PLLOE"},
178
179 /* output mixer */
180 {"Output Mixer", "DAC Switch", "DAC"},
181 {"Output Mixer", "Line in loopback Switch", "LIN"},
182
183 /* outputs */
184 {"LOUT", NULL, "Output Mixer"},
185 {"SPOUT", NULL, "Output Mixer"},
186 {"Line Out Enable", NULL, "LOUT"},
187
188 /* input */
189 {"ADC", NULL, "Input Mux"},
190 {"Input Mux", "Analog MIC SingleEnded in", "PGA"},
191 {"Input Mux", "Analog MIC Differential in", "PGA"},
192 {"PGA", NULL, "MIN"},
193};
194
195/* PLLOutputFreq(Hz) = InputMclkFreq(Hz) * PLLM / (PLLN * PLLDIV) */
196static const struct clk_coeff coeff_div[] = {
197 {12288000, 16000, 0xc, 0x0, 0x20, 0x0, 0x4},
198 {12288000, 32000, 0xc, 0x0, 0x20, 0x0, 0x4},
199 {12288000, 48000, 0xc, 0x0, 0x30, 0x0, 0x4},
200};
201
202static struct reg_default ml26124_reg[] = {
203 /* CLOCK control Register */
204 {0x00, 0x00 }, /* Sampling Rate */
205 {0x02, 0x00}, /* PLL NL */
206 {0x04, 0x00}, /* PLLNH */
207 {0x06, 0x00}, /* PLLML */
208 {0x08, 0x00}, /* MLLMH */
209 {0x0a, 0x00}, /* PLLDIV */
210 {0x0c, 0x00}, /* Clock Enable */
211 {0x0e, 0x00}, /* CLK Input/Output Control */
212
213 /* System Control Register */
214 {0x10, 0x00}, /* Software RESET */
215 {0x12, 0x00}, /* Record/Playback Run */
216 {0x14, 0x00}, /* Mic Input/Output control */
217
218 /* Power Management Register */
219 {0x20, 0x00}, /* Reference Power Management */
220 {0x22, 0x00}, /* Input Power Management */
221 {0x24, 0x00}, /* DAC Power Management */
222 {0x26, 0x00}, /* SP-AMP Power Management */
223 {0x28, 0x00}, /* LINEOUT Power Management */
224 {0x2a, 0x00}, /* VIDEO Power Management */
225 {0x2e, 0x00}, /* AC-CMP Power Management */
226
227 /* Analog reference Control Register */
228 {0x30, 0x04}, /* MICBIAS Voltage Control */
229
230 /* Input/Output Amplifier Control Register */
231 {0x32, 0x10}, /* MIC Input Volume */
232 {0x38, 0x00}, /* Mic Boost Volume */
233 {0x3a, 0x33}, /* Speaker AMP Volume */
234 {0x48, 0x00}, /* AMP Volume Control Function Enable */
235 {0x4a, 0x00}, /* Amplifier Volume Fader Control */
236
237 /* Analog Path Control Register */
238 {0x54, 0x00}, /* Speaker AMP Output Control */
239 {0x5a, 0x00}, /* Mic IF Control */
240 {0xe8, 0x01}, /* Mic Select Control */
241
242 /* Audio Interface Control Register */
243 {0x60, 0x00}, /* SAI-Trans Control */
244 {0x62, 0x00}, /* SAI-Receive Control */
245 {0x64, 0x00}, /* SAI Mode select */
246
247 /* DSP Control Register */
248 {0x66, 0x01}, /* Filter Func Enable */
249 {0x68, 0x00}, /* Volume Control Func Enable */
250 {0x6A, 0x00}, /* Mixer & Volume Control*/
251 {0x6C, 0xff}, /* Record Digital Volume */
252 {0x70, 0xff}, /* Playback Digital Volume */
253 {0x72, 0x10}, /* Digital Boost Volume */
254 {0x74, 0xe7}, /* EQ gain Band0 */
255 {0x76, 0xe7}, /* EQ gain Band1 */
256 {0x78, 0xe7}, /* EQ gain Band2 */
257 {0x7A, 0xe7}, /* EQ gain Band3 */
258 {0x7C, 0xe7}, /* EQ gain Band4 */
259 {0x7E, 0x00}, /* HPF2 CutOff*/
260 {0x80, 0x00}, /* EQ Band0 Coef0L */
261 {0x82, 0x00}, /* EQ Band0 Coef0H */
262 {0x84, 0x00}, /* EQ Band0 Coef0L */
263 {0x86, 0x00}, /* EQ Band0 Coef0H */
264 {0x88, 0x00}, /* EQ Band1 Coef0L */
265 {0x8A, 0x00}, /* EQ Band1 Coef0H */
266 {0x8C, 0x00}, /* EQ Band1 Coef0L */
267 {0x8E, 0x00}, /* EQ Band1 Coef0H */
268 {0x90, 0x00}, /* EQ Band2 Coef0L */
269 {0x92, 0x00}, /* EQ Band2 Coef0H */
270 {0x94, 0x00}, /* EQ Band2 Coef0L */
271 {0x96, 0x00}, /* EQ Band2 Coef0H */
272 {0x98, 0x00}, /* EQ Band3 Coef0L */
273 {0x9A, 0x00}, /* EQ Band3 Coef0H */
274 {0x9C, 0x00}, /* EQ Band3 Coef0L */
275 {0x9E, 0x00}, /* EQ Band3 Coef0H */
276 {0xA0, 0x00}, /* EQ Band4 Coef0L */
277 {0xA2, 0x00}, /* EQ Band4 Coef0H */
278 {0xA4, 0x00}, /* EQ Band4 Coef0L */
279 {0xA6, 0x00}, /* EQ Band4 Coef0H */
280
281 /* ALC Control Register */
282 {0xb0, 0x00}, /* ALC Mode */
283 {0xb2, 0x02}, /* ALC Attack Time */
284 {0xb4, 0x03}, /* ALC Decay Time */
285 {0xb6, 0x00}, /* ALC Hold Time */
286 {0xb8, 0x0b}, /* ALC Target Level */
287 {0xba, 0x70}, /* ALC Max/Min Gain */
288 {0xbc, 0x00}, /* Noise Gate Threshold */
289 {0xbe, 0x00}, /* ALC ZeroCross TimeOut */
290
291 /* Playback Limiter Control Register */
292 {0xc0, 0x04}, /* PL Attack Time */
293 {0xc2, 0x05}, /* PL Decay Time */
294 {0xc4, 0x0d}, /* PL Target Level */
295 {0xc6, 0x70}, /* PL Max/Min Gain */
296 {0xc8, 0x10}, /* Playback Boost Volume */
297 {0xca, 0x00}, /* PL ZeroCross TimeOut */
298
299 /* Video Amplifier Control Register */
300 {0xd0, 0x01}, /* VIDEO AMP Gain Control */
301 {0xd2, 0x01}, /* VIDEO AMP Setup 1 */
302 {0xd4, 0x01}, /* VIDEO AMP Control2 */
303};
304
305/* Get sampling rate value of sampling rate setting register (0x0) */
306static inline int get_srate(int rate)
307{
308 int srate;
309
310 switch (rate) {
311 case 16000:
312 srate = 3;
313 break;
314 case 32000:
315 srate = 6;
316 break;
317 case 48000:
318 srate = 8;
319 break;
320 default:
321 return -EINVAL;
322 }
323 return srate;
324}
325
326static inline int get_coeff(int mclk, int rate)
327{
328 int i;
329
330 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
331 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
332 return i;
333 }
334 return -EINVAL;
335}
336
337static int ml26124_hw_params(struct snd_pcm_substream *substream,
338 struct snd_pcm_hw_params *hw_params,
339 struct snd_soc_dai *dai)
340{
341 struct snd_soc_codec *codec = dai->codec;
342 struct ml26124_priv *priv = snd_soc_codec_get_drvdata(codec);
343 int i = get_coeff(priv->mclk, params_rate(hw_params));
344
345 priv->substream = substream;
346 priv->rate = params_rate(hw_params);
347
348 if (priv->clk_in) {
349 switch (priv->mclk / params_rate(hw_params)) {
350 case 256:
351 snd_soc_update_bits(codec, ML26124_CLK_CTL,
352 BIT(0) | BIT(1), 1);
353 break;
354 case 512:
355 snd_soc_update_bits(codec, ML26124_CLK_CTL,
356 BIT(0) | BIT(1), 2);
357 break;
358 case 1024:
359 snd_soc_update_bits(codec, ML26124_CLK_CTL,
360 BIT(0) | BIT(1), 3);
361 break;
362 default:
363 dev_err(codec->dev, "Unsupported MCLKI\n");
364 break;
365 }
366 } else {
367 snd_soc_update_bits(codec, ML26124_CLK_CTL,
368 BIT(0) | BIT(1), 0);
369 }
370
371 switch (params_rate(hw_params)) {
372 case 16000:
373 snd_soc_update_bits(codec, ML26124_SMPLING_RATE, 0xf,
374 get_srate(params_rate(hw_params)));
375 snd_soc_update_bits(codec, ML26124_PLLNL, 0xff,
376 coeff_div[i].pllnl);
377 snd_soc_update_bits(codec, ML26124_PLLNH, 0x1,
378 coeff_div[i].pllnh);
379 snd_soc_update_bits(codec, ML26124_PLLML, 0xff,
380 coeff_div[i].pllml);
381 snd_soc_update_bits(codec, ML26124_PLLMH, 0x3f,
382 coeff_div[i].pllmh);
383 snd_soc_update_bits(codec, ML26124_PLLDIV, 0x1f,
384 coeff_div[i].plldiv);
385 break;
386 case 32000:
387 snd_soc_update_bits(codec, ML26124_SMPLING_RATE, 0xf,
388 get_srate(params_rate(hw_params)));
389 snd_soc_update_bits(codec, ML26124_PLLNL, 0xff,
390 coeff_div[i].pllnl);
391 snd_soc_update_bits(codec, ML26124_PLLNH, 0x1,
392 coeff_div[i].pllnh);
393 snd_soc_update_bits(codec, ML26124_PLLML, 0xff,
394 coeff_div[i].pllml);
395 snd_soc_update_bits(codec, ML26124_PLLMH, 0x3f,
396 coeff_div[i].pllmh);
397 snd_soc_update_bits(codec, ML26124_PLLDIV, 0x1f,
398 coeff_div[i].plldiv);
399 break;
400 case 48000:
401 snd_soc_update_bits(codec, ML26124_SMPLING_RATE, 0xf,
402 get_srate(params_rate(hw_params)));
403 snd_soc_update_bits(codec, ML26124_PLLNL, 0xff,
404 coeff_div[i].pllnl);
405 snd_soc_update_bits(codec, ML26124_PLLNH, 0x1,
406 coeff_div[i].pllnh);
407 snd_soc_update_bits(codec, ML26124_PLLML, 0xff,
408 coeff_div[i].pllml);
409 snd_soc_update_bits(codec, ML26124_PLLMH, 0x3f,
410 coeff_div[i].pllmh);
411 snd_soc_update_bits(codec, ML26124_PLLDIV, 0x1f,
412 coeff_div[i].plldiv);
413 break;
414 default:
415 pr_err("%s:this rate is no support for ml26124\n", __func__);
416 return -EINVAL;
417 }
418
419 return 0;
420}
421
422static int ml26124_mute(struct snd_soc_dai *dai, int mute)
423{
424 struct snd_soc_codec *codec = dai->codec;
425 struct ml26124_priv *priv = snd_soc_codec_get_drvdata(codec);
426
427 switch (priv->substream->stream) {
428 case SNDRV_PCM_STREAM_CAPTURE:
429 snd_soc_update_bits(codec, ML26124_REC_PLYBAK_RUN, BIT(0), 1);
430 break;
431 case SNDRV_PCM_STREAM_PLAYBACK:
432 snd_soc_update_bits(codec, ML26124_REC_PLYBAK_RUN, BIT(1), 2);
433 break;
434 }
435
436 if (mute)
437 snd_soc_update_bits(codec, ML26124_DVOL_CTL, BIT(4),
438 DVOL_CTL_DVMUTE_ON);
439 else
440 snd_soc_update_bits(codec, ML26124_DVOL_CTL, BIT(4),
441 DVOL_CTL_DVMUTE_OFF);
442
443 return 0;
444}
445
446static int ml26124_set_dai_fmt(struct snd_soc_dai *codec_dai,
447 unsigned int fmt)
448{
449 unsigned char mode;
450 struct snd_soc_codec *codec = codec_dai->codec;
451
452 /* set master/slave audio interface */
453 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
454 case SND_SOC_DAIFMT_CBM_CFM:
455 mode = 1;
456 break;
457 case SND_SOC_DAIFMT_CBS_CFS:
458 mode = 0;
459 break;
460 default:
461 return -EINVAL;
462 }
463 snd_soc_update_bits(codec, ML26124_SAI_MODE_SEL, BIT(0), mode);
464
465 /* interface format */
466 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
467 case SND_SOC_DAIFMT_I2S:
468 break;
469 default:
470 return -EINVAL;
471 }
472
473 /* clock inversion */
474 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
475 case SND_SOC_DAIFMT_NB_NF:
476 break;
477 default:
478 return -EINVAL;
479 }
480
481 return 0;
482}
483
484static int ml26124_set_dai_sysclk(struct snd_soc_dai *codec_dai,
485 int clk_id, unsigned int freq, int dir)
486{
487 struct snd_soc_codec *codec = codec_dai->codec;
488 struct ml26124_priv *priv = snd_soc_codec_get_drvdata(codec);
489
490 switch (clk_id) {
491 case ML26124_USE_PLLOUT:
492 priv->clk_in = ML26124_USE_PLLOUT;
493 break;
494 case ML26124_USE_MCLKI:
495 priv->clk_in = ML26124_USE_MCLKI;
496 break;
497 default:
498 return -EINVAL;
499 }
500
501 priv->mclk = freq;
502
503 return 0;
504}
505
506static int ml26124_set_bias_level(struct snd_soc_codec *codec,
507 enum snd_soc_bias_level level)
508{
509 struct ml26124_priv *priv = snd_soc_codec_get_drvdata(codec);
510
511 switch (level) {
512 case SND_SOC_BIAS_ON:
513 snd_soc_update_bits(codec, ML26124_PW_SPAMP_PW_MNG,
514 ML26124_R26_MASK, ML26124_BLT_PREAMP_ON);
515 msleep(100);
516 snd_soc_update_bits(codec, ML26124_PW_SPAMP_PW_MNG,
517 ML26124_R26_MASK,
518 ML26124_MICBEN_ON | ML26124_BLT_ALL_ON);
519 break;
520 case SND_SOC_BIAS_PREPARE:
521 break;
522 case SND_SOC_BIAS_STANDBY:
523 /* VMID ON */
524 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
525 snd_soc_update_bits(codec, ML26124_PW_REF_PW_MNG,
526 ML26124_VMID, ML26124_VMID);
527 msleep(500);
528 regcache_sync(priv->regmap);
529 }
530 break;
531 case SND_SOC_BIAS_OFF:
532 /* VMID OFF */
533 snd_soc_update_bits(codec, ML26124_PW_REF_PW_MNG,
534 ML26124_VMID, 0);
535 break;
536 }
537 codec->dapm.bias_level = level;
538 return 0;
539}
540
541static const struct snd_soc_dai_ops ml26124_dai_ops = {
542 .hw_params = ml26124_hw_params,
543 .digital_mute = ml26124_mute,
544 .set_fmt = ml26124_set_dai_fmt,
545 .set_sysclk = ml26124_set_dai_sysclk,
546};
547
548static struct snd_soc_dai_driver ml26124_dai = {
549 .name = "ml26124-hifi",
550 .playback = {
551 .stream_name = "Playback",
552 .channels_min = 1,
553 .channels_max = 2,
554 .rates = ML26124_RATES,
555 .formats = ML26124_FORMATS,},
556 .capture = {
557 .stream_name = "Capture",
558 .channels_min = 1,
559 .channels_max = 2,
560 .rates = ML26124_RATES,
561 .formats = ML26124_FORMATS,},
562 .ops = &ml26124_dai_ops,
563 .symmetric_rates = 1,
564};
565
566#ifdef CONFIG_PM
567static int ml26124_suspend(struct snd_soc_codec *codec)
568{
569 ml26124_set_bias_level(codec, SND_SOC_BIAS_OFF);
570
571 return 0;
572}
573
574static int ml26124_resume(struct snd_soc_codec *codec)
575{
576 ml26124_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
577
578 return 0;
579}
580#else
581#define ml26124_suspend NULL
582#define ml26124_resume NULL
583#endif
584
585static int ml26124_probe(struct snd_soc_codec *codec)
586{
587 int ret;
588 struct ml26124_priv *priv = snd_soc_codec_get_drvdata(codec);
589 codec->control_data = priv->regmap;
590
591 ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_REGMAP);
592 if (ret < 0) {
593 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
594 return ret;
595 }
596
597 /* Software Reset */
598 snd_soc_update_bits(codec, ML26124_SW_RST, 0x01, 1);
599 snd_soc_update_bits(codec, ML26124_SW_RST, 0x01, 0);
600
601 ml26124_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
602
603 return 0;
604}
605
606static struct snd_soc_codec_driver soc_codec_dev_ml26124 = {
607 .probe = ml26124_probe,
608 .suspend = ml26124_suspend,
609 .resume = ml26124_resume,
610 .set_bias_level = ml26124_set_bias_level,
611 .dapm_widgets = ml26124_dapm_widgets,
612 .num_dapm_widgets = ARRAY_SIZE(ml26124_dapm_widgets),
613 .dapm_routes = ml26124_intercon,
614 .num_dapm_routes = ARRAY_SIZE(ml26124_intercon),
615 .controls = ml26124_snd_controls,
616 .num_controls = ARRAY_SIZE(ml26124_snd_controls),
617};
618
619static const struct regmap_config ml26124_i2c_regmap = {
620 .val_bits = 8,
621 .reg_bits = 8,
622 .max_register = ML26124_NUM_REGISTER,
623 .reg_defaults = ml26124_reg,
624 .num_reg_defaults = ARRAY_SIZE(ml26124_reg),
625 .cache_type = REGCACHE_RBTREE,
626 .write_flag_mask = 0x01,
627};
628
629static __devinit int ml26124_i2c_probe(struct i2c_client *i2c,
630 const struct i2c_device_id *id)
631{
632 struct ml26124_priv *priv;
633 int ret;
634
635 priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
636 if (!priv)
637 return -ENOMEM;
638
639 i2c_set_clientdata(i2c, priv);
640
641 priv->regmap = regmap_init_i2c(i2c, &ml26124_i2c_regmap);
642 if (IS_ERR(priv->regmap)) {
643 ret = PTR_ERR(priv->regmap);
644 dev_err(&i2c->dev, "regmap_init_i2c() failed: %d\n", ret);
645 return ret;
646 }
647
648 return snd_soc_register_codec(&i2c->dev,
649 &soc_codec_dev_ml26124, &ml26124_dai, 1);
650}
651
652static __devexit int ml26124_i2c_remove(struct i2c_client *client)
653{
654 struct ml26124_priv *priv = i2c_get_clientdata(client);
655
656 snd_soc_unregister_codec(&client->dev);
657 regmap_exit(priv->regmap);
658 return 0;
659}
660
661static const struct i2c_device_id ml26124_i2c_id[] = {
662 { "ml26124", 0 },
663 { }
664};
665MODULE_DEVICE_TABLE(i2c, ml26124_i2c_id);
666
667static struct i2c_driver ml26124_i2c_driver = {
668 .driver = {
669 .name = "ml26124",
670 .owner = THIS_MODULE,
671 },
672 .probe = ml26124_i2c_probe,
673 .remove = __devexit_p(ml26124_i2c_remove),
674 .id_table = ml26124_i2c_id,
675};
676
677module_i2c_driver(ml26124_i2c_driver);
678
679MODULE_AUTHOR("Tomoya MORINAGA <tomoya.rohm@gmail.com>");
680MODULE_DESCRIPTION("LAPIS Semiconductor ML26124 ALSA SoC codec driver");
681MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/ml26124.h b/sound/soc/codecs/ml26124.h
new file mode 100644
index 000000000000..5ea0cbb8c46c
--- /dev/null
+++ b/sound/soc/codecs/ml26124.h
@@ -0,0 +1,184 @@
1/*
2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17
18#ifndef ML26124_H
19#define ML26124_H
20
21/* Clock Control Register */
22#define ML26124_SMPLING_RATE 0x00
23#define ML26124_PLLNL 0x02
24#define ML26124_PLLNH 0x04
25#define ML26124_PLLML 0x06
26#define ML26124_PLLMH 0x08
27#define ML26124_PLLDIV 0x0a
28#define ML26124_CLK_EN 0x0c
29#define ML26124_CLK_CTL 0x0e
30
31/* System Control Register */
32#define ML26124_SW_RST 0x10
33#define ML26124_REC_PLYBAK_RUN 0x12
34#define ML26124_MIC_TIM 0x14
35
36/* Power Mnagement Register */
37#define ML26124_PW_REF_PW_MNG 0x20
38#define ML26124_PW_IN_PW_MNG 0x22
39#define ML26124_PW_DAC_PW_MNG 0x24
40#define ML26124_PW_SPAMP_PW_MNG 0x26
41#define ML26124_PW_LOUT_PW_MNG 0x28
42#define ML26124_PW_VOUT_PW_MNG 0x2a
43#define ML26124_PW_ZCCMP_PW_MNG 0x2e
44
45/* Analog Reference Control Register */
46#define ML26124_PW_MICBIAS_VOL 0x30
47
48/* Input/Output Amplifier Control Register */
49#define ML26124_PW_MIC_IN_VOL 0x32
50#define ML26124_PW_MIC_BOST_VOL 0x38
51#define ML26124_PW_SPK_AMP_VOL 0x3a
52#define ML26124_PW_AMP_VOL_FUNC 0x48
53#define ML26124_PW_AMP_VOL_FADE 0x4a
54
55/* Analog Path Control Register */
56#define ML26124_SPK_AMP_OUT 0x54
57#define ML26124_MIC_IF_CTL 0x5a
58#define ML26124_MIC_SELECT 0xe8
59
60/* Audio Interface Control Register */
61#define ML26124_SAI_TRANS_CTL 0x60
62#define ML26124_SAI_RCV_CTL 0x62
63#define ML26124_SAI_MODE_SEL 0x64
64
65/* DSP Control Register */
66#define ML26124_FILTER_EN 0x66
67#define ML26124_DVOL_CTL 0x68
68#define ML26124_MIXER_VOL_CTL 0x6a
69#define ML26124_RECORD_DIG_VOL 0x6c
70#define ML26124_PLBAK_DIG_VOL 0x70
71#define ML26124_DIGI_BOOST_VOL 0x72
72#define ML26124_EQ_GAIN_BRAND0 0x74
73#define ML26124_EQ_GAIN_BRAND1 0x76
74#define ML26124_EQ_GAIN_BRAND2 0x78
75#define ML26124_EQ_GAIN_BRAND3 0x7a
76#define ML26124_EQ_GAIN_BRAND4 0x7c
77#define ML26124_HPF2_CUTOFF 0x7e
78#define ML26124_EQBRAND0_F0L 0x80
79#define ML26124_EQBRAND0_F0H 0x82
80#define ML26124_EQBRAND0_F1L 0x84
81#define ML26124_EQBRAND0_F1H 0x86
82#define ML26124_EQBRAND1_F0L 0x88
83#define ML26124_EQBRAND1_F0H 0x8a
84#define ML26124_EQBRAND1_F1L 0x8c
85#define ML26124_EQBRAND1_F1H 0x8e
86#define ML26124_EQBRAND2_F0L 0x90
87#define ML26124_EQBRAND2_F0H 0x92
88#define ML26124_EQBRAND2_F1L 0x94
89#define ML26124_EQBRAND2_F1H 0x96
90#define ML26124_EQBRAND3_F0L 0x98
91#define ML26124_EQBRAND3_F0H 0x9a
92#define ML26124_EQBRAND3_F1L 0x9c
93#define ML26124_EQBRAND3_F1H 0x9e
94#define ML26124_EQBRAND4_F0L 0xa0
95#define ML26124_EQBRAND4_F0H 0xa2
96#define ML26124_EQBRAND4_F1L 0xa4
97#define ML26124_EQBRAND4_F1H 0xa6
98
99/* ALC Control Register */
100#define ML26124_ALC_MODE 0xb0
101#define ML26124_ALC_ATTACK_TIM 0xb2
102#define ML26124_ALC_DECAY_TIM 0xb4
103#define ML26124_ALC_HOLD_TIM 0xb6
104#define ML26124_ALC_TARGET_LEV 0xb8
105#define ML26124_ALC_MAXMIN_GAIN 0xba
106#define ML26124_NOIS_GATE_THRSH 0xbc
107#define ML26124_ALC_ZERO_TIMOUT 0xbe
108
109/* Playback Limiter Control Register */
110#define ML26124_PL_ATTACKTIME 0xc0
111#define ML26124_PL_DECAYTIME 0xc2
112#define ML26124_PL_TARGETTIME 0xc4
113#define ML26124_PL_MAXMIN_GAIN 0xc6
114#define ML26124_PLYBAK_BOST_VOL 0xc8
115#define ML26124_PL_0CROSS_TIMOUT 0xca
116
117/* Video Amplifer Control Register */
118#define ML26124_VIDEO_AMP_GAIN_CTL 0xd0
119#define ML26124_VIDEO_AMP_SETUP1 0xd2
120#define ML26124_VIDEO_AMP_CTL2 0xd4
121
122/* Clock select for machine driver */
123#define ML26124_USE_PLL 0
124#define ML26124_USE_MCLKI_256FS 1
125#define ML26124_USE_MCLKI_512FS 2
126#define ML26124_USE_MCLKI_1024FS 3
127
128/* Register Mask */
129#define ML26124_R0_MASK 0xf
130#define ML26124_R2_MASK 0xff
131#define ML26124_R4_MASK 0x1
132#define ML26124_R6_MASK 0xf
133#define ML26124_R8_MASK 0x3f
134#define ML26124_Ra_MASK 0x1f
135#define ML26124_Rc_MASK 0x1f
136#define ML26124_Re_MASK 0x7
137#define ML26124_R10_MASK 0x1
138#define ML26124_R12_MASK 0x17
139#define ML26124_R14_MASK 0x3f
140#define ML26124_R20_MASK 0x47
141#define ML26124_R22_MASK 0xa
142#define ML26124_R24_MASK 0x2
143#define ML26124_R26_MASK 0x1f
144#define ML26124_R28_MASK 0x2
145#define ML26124_R2a_MASK 0x2
146#define ML26124_R2e_MASK 0x2
147#define ML26124_R30_MASK 0x7
148#define ML26124_R32_MASK 0x3f
149#define ML26124_R38_MASK 0x38
150#define ML26124_R3a_MASK 0x3f
151#define ML26124_R48_MASK 0x3
152#define ML26124_R4a_MASK 0x7
153#define ML26124_R54_MASK 0x2a
154#define ML26124_R5a_MASK 0x3
155#define ML26124_Re8_MASK 0x3
156#define ML26124_R60_MASK 0xff
157#define ML26124_R62_MASK 0xff
158#define ML26124_R64_MASK 0x1
159#define ML26124_R66_MASK 0xff
160#define ML26124_R68_MASK 0x3b
161#define ML26124_R6a_MASK 0xf3
162#define ML26124_R6c_MASK 0xff
163#define ML26124_R70_MASK 0xff
164
165#define ML26124_MCLKEN BIT(0)
166#define ML26124_PLLEN BIT(1)
167#define ML26124_PLLOE BIT(2)
168#define ML26124_MCLKOE BIT(3)
169
170#define ML26124_BLT_ALL_ON 0x1f
171#define ML26124_BLT_PREAMP_ON 0x13
172
173#define ML26124_MICBEN_ON BIT(2)
174
175enum ml26124_regs {
176 ML26124_MCLK = 0,
177};
178
179enum ml26124_clk_in {
180 ML26124_USE_PLLOUT = 0,
181 ML26124_USE_MCLKI,
182};
183
184#endif
diff --git a/sound/soc/codecs/omap-hdmi.c b/sound/soc/codecs/omap-hdmi.c
new file mode 100644
index 000000000000..1bf5c74f5f96
--- /dev/null
+++ b/sound/soc/codecs/omap-hdmi.c
@@ -0,0 +1,69 @@
1/*
2 * ALSA SoC codec driver for HDMI audio on OMAP processors.
3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 * Author: Ricardo Neri <ricardo.neri@ti.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21#include <linux/module.h>
22#include <sound/soc.h>
23
24#define DRV_NAME "hdmi-audio-codec"
25
26static struct snd_soc_codec_driver omap_hdmi_codec;
27
28static struct snd_soc_dai_driver omap_hdmi_codec_dai = {
29 .name = "omap-hdmi-hifi",
30 .playback = {
31 .channels_min = 2,
32 .channels_max = 8,
33 .rates = SNDRV_PCM_RATE_32000 |
34 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
35 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
36 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000,
37 .formats = SNDRV_PCM_FMTBIT_S16_LE |
38 SNDRV_PCM_FMTBIT_S24_LE,
39 },
40};
41
42static __devinit int omap_hdmi_codec_probe(struct platform_device *pdev)
43{
44 return snd_soc_register_codec(&pdev->dev, &omap_hdmi_codec,
45 &omap_hdmi_codec_dai, 1);
46}
47
48static __devexit int omap_hdmi_codec_remove(struct platform_device *pdev)
49{
50 snd_soc_unregister_codec(&pdev->dev);
51 return 0;
52}
53
54static struct platform_driver omap_hdmi_codec_driver = {
55 .driver = {
56 .name = DRV_NAME,
57 .owner = THIS_MODULE,
58 },
59
60 .probe = omap_hdmi_codec_probe,
61 .remove = __devexit_p(omap_hdmi_codec_remove),
62};
63
64module_platform_driver(omap_hdmi_codec_driver);
65
66MODULE_AUTHOR("Ricardo Neri <ricardo.neri@ti.com>");
67MODULE_DESCRIPTION("ASoC OMAP HDMI codec driver");
68MODULE_LICENSE("GPL");
69MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/sound/soc/codecs/rt5631.c b/sound/soc/codecs/rt5631.c
index 20c324c7c349..960d0e93cce9 100644
--- a/sound/soc/codecs/rt5631.c
+++ b/sound/soc/codecs/rt5631.c
@@ -18,7 +18,7 @@
18#include <linux/delay.h> 18#include <linux/delay.h>
19#include <linux/pm.h> 19#include <linux/pm.h>
20#include <linux/i2c.h> 20#include <linux/i2c.h>
21#include <linux/spi/spi.h> 21#include <linux/regmap.h>
22#include <sound/core.h> 22#include <sound/core.h>
23#include <sound/pcm.h> 23#include <sound/pcm.h>
24#include <sound/pcm_params.h> 24#include <sound/pcm_params.h>
@@ -30,6 +30,7 @@
30#include "rt5631.h" 30#include "rt5631.h"
31 31
32struct rt5631_priv { 32struct rt5631_priv {
33 struct regmap *regmap;
33 int codec_version; 34 int codec_version;
34 int master; 35 int master;
35 int sysclk; 36 int sysclk;
@@ -38,33 +39,33 @@ struct rt5631_priv {
38 int dmic_used_flag; 39 int dmic_used_flag;
39}; 40};
40 41
41static const u16 rt5631_reg[RT5631_VENDOR_ID2 + 1] = { 42static const struct reg_default rt5631_reg[] = {
42 [RT5631_SPK_OUT_VOL] = 0x8888, 43 { RT5631_SPK_OUT_VOL, 0x8888 },
43 [RT5631_HP_OUT_VOL] = 0x8080, 44 { RT5631_HP_OUT_VOL, 0x8080 },
44 [RT5631_MONO_AXO_1_2_VOL] = 0xa080, 45 { RT5631_MONO_AXO_1_2_VOL, 0xa080 },
45 [RT5631_AUX_IN_VOL] = 0x0808, 46 { RT5631_AUX_IN_VOL, 0x0808 },
46 [RT5631_ADC_REC_MIXER] = 0xf0f0, 47 { RT5631_ADC_REC_MIXER, 0xf0f0 },
47 [RT5631_VDAC_DIG_VOL] = 0x0010, 48 { RT5631_VDAC_DIG_VOL, 0x0010 },
48 [RT5631_OUTMIXER_L_CTRL] = 0xffc0, 49 { RT5631_OUTMIXER_L_CTRL, 0xffc0 },
49 [RT5631_OUTMIXER_R_CTRL] = 0xffc0, 50 { RT5631_OUTMIXER_R_CTRL, 0xffc0 },
50 [RT5631_AXO1MIXER_CTRL] = 0x88c0, 51 { RT5631_AXO1MIXER_CTRL, 0x88c0 },
51 [RT5631_AXO2MIXER_CTRL] = 0x88c0, 52 { RT5631_AXO2MIXER_CTRL, 0x88c0 },
52 [RT5631_DIG_MIC_CTRL] = 0x3000, 53 { RT5631_DIG_MIC_CTRL, 0x3000 },
53 [RT5631_MONO_INPUT_VOL] = 0x8808, 54 { RT5631_MONO_INPUT_VOL, 0x8808 },
54 [RT5631_SPK_MIXER_CTRL] = 0xf8f8, 55 { RT5631_SPK_MIXER_CTRL, 0xf8f8 },
55 [RT5631_SPK_MONO_OUT_CTRL] = 0xfc00, 56 { RT5631_SPK_MONO_OUT_CTRL, 0xfc00 },
56 [RT5631_SPK_MONO_HP_OUT_CTRL] = 0x4440, 57 { RT5631_SPK_MONO_HP_OUT_CTRL, 0x4440 },
57 [RT5631_SDP_CTRL] = 0x8000, 58 { RT5631_SDP_CTRL, 0x8000 },
58 [RT5631_MONO_SDP_CTRL] = 0x8000, 59 { RT5631_MONO_SDP_CTRL, 0x8000 },
59 [RT5631_STEREO_AD_DA_CLK_CTRL] = 0x2010, 60 { RT5631_STEREO_AD_DA_CLK_CTRL, 0x2010 },
60 [RT5631_GEN_PUR_CTRL_REG] = 0x0e00, 61 { RT5631_GEN_PUR_CTRL_REG, 0x0e00 },
61 [RT5631_INT_ST_IRQ_CTRL_2] = 0x071a, 62 { RT5631_INT_ST_IRQ_CTRL_2, 0x071a },
62 [RT5631_MISC_CTRL] = 0x2040, 63 { RT5631_MISC_CTRL, 0x2040 },
63 [RT5631_DEPOP_FUN_CTRL_2] = 0x8000, 64 { RT5631_DEPOP_FUN_CTRL_2, 0x8000 },
64 [RT5631_SOFT_VOL_CTRL] = 0x07e0, 65 { RT5631_SOFT_VOL_CTRL, 0x07e0 },
65 [RT5631_ALC_CTRL_1] = 0x0206, 66 { RT5631_ALC_CTRL_1, 0x0206 },
66 [RT5631_ALC_CTRL_3] = 0x2000, 67 { RT5631_ALC_CTRL_3, 0x2000 },
67 [RT5631_PSEUDO_SPATL_CTRL] = 0x0553, 68 { RT5631_PSEUDO_SPATL_CTRL, 0x0553 },
68}; 69};
69 70
70/** 71/**
@@ -96,8 +97,7 @@ static int rt5631_reset(struct snd_soc_codec *codec)
96 return snd_soc_write(codec, RT5631_RESET, 0); 97 return snd_soc_write(codec, RT5631_RESET, 0);
97} 98}
98 99
99static int rt5631_volatile_register(struct snd_soc_codec *codec, 100static bool rt5631_volatile_register(struct device *dev, unsigned int reg)
100 unsigned int reg)
101{ 101{
102 switch (reg) { 102 switch (reg) {
103 case RT5631_RESET: 103 case RT5631_RESET:
@@ -111,8 +111,7 @@ static int rt5631_volatile_register(struct snd_soc_codec *codec,
111 } 111 }
112} 112}
113 113
114static int rt5631_readable_register(struct snd_soc_codec *codec, 114static bool rt5631_readable_register(struct device *dev, unsigned int reg)
115 unsigned int reg)
116{ 115{
117 switch (reg) { 116 switch (reg) {
118 case RT5631_RESET: 117 case RT5631_RESET:
@@ -1361,8 +1360,7 @@ static int get_coeff(int mclk, int rate, int timesofbclk)
1361static int rt5631_hifi_pcm_params(struct snd_pcm_substream *substream, 1360static int rt5631_hifi_pcm_params(struct snd_pcm_substream *substream,
1362 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1361 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1363{ 1362{
1364 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1363 struct snd_soc_codec *codec = dai->codec;
1365 struct snd_soc_codec *codec = rtd->codec;
1366 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec); 1364 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
1367 int timesofbclk = 32, coeff; 1365 int timesofbclk = 32, coeff;
1368 unsigned int iface = 0; 1366 unsigned int iface = 0;
@@ -1544,6 +1542,8 @@ static int rt5631_codec_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1544static int rt5631_set_bias_level(struct snd_soc_codec *codec, 1542static int rt5631_set_bias_level(struct snd_soc_codec *codec,
1545 enum snd_soc_bias_level level) 1543 enum snd_soc_bias_level level)
1546{ 1544{
1545 struct rt5631_priv *rt5631 = snd_soc_codec_get_drvdata(codec);
1546
1547 switch (level) { 1547 switch (level) {
1548 case SND_SOC_BIAS_ON: 1548 case SND_SOC_BIAS_ON:
1549 case SND_SOC_BIAS_PREPARE: 1549 case SND_SOC_BIAS_PREPARE:
@@ -1561,8 +1561,8 @@ static int rt5631_set_bias_level(struct snd_soc_codec *codec,
1561 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3, 1561 snd_soc_update_bits(codec, RT5631_PWR_MANAG_ADD3,
1562 RT5631_PWR_FAST_VREF_CTRL, 1562 RT5631_PWR_FAST_VREF_CTRL,
1563 RT5631_PWR_FAST_VREF_CTRL); 1563 RT5631_PWR_FAST_VREF_CTRL);
1564 codec->cache_only = false; 1564 regcache_cache_only(rt5631->regmap, false);
1565 snd_soc_cache_sync(codec); 1565 regcache_sync(rt5631->regmap);
1566 } 1566 }
1567 break; 1567 break;
1568 1568
@@ -1587,7 +1587,9 @@ static int rt5631_probe(struct snd_soc_codec *codec)
1587 unsigned int val; 1587 unsigned int val;
1588 int ret; 1588 int ret;
1589 1589
1590 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); 1590 codec->control_data = rt5631->regmap;
1591
1592 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
1591 if (ret != 0) { 1593 if (ret != 0) {
1592 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1594 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1593 return ret; 1595 return ret;
@@ -1698,12 +1700,6 @@ static struct snd_soc_codec_driver soc_codec_dev_rt5631 = {
1698 .suspend = rt5631_suspend, 1700 .suspend = rt5631_suspend,
1699 .resume = rt5631_resume, 1701 .resume = rt5631_resume,
1700 .set_bias_level = rt5631_set_bias_level, 1702 .set_bias_level = rt5631_set_bias_level,
1701 .reg_cache_size = RT5631_VENDOR_ID2 + 1,
1702 .reg_word_size = sizeof(u16),
1703 .reg_cache_default = rt5631_reg,
1704 .volatile_register = rt5631_volatile_register,
1705 .readable_register = rt5631_readable_register,
1706 .reg_cache_step = 1,
1707 .controls = rt5631_snd_controls, 1703 .controls = rt5631_snd_controls,
1708 .num_controls = ARRAY_SIZE(rt5631_snd_controls), 1704 .num_controls = ARRAY_SIZE(rt5631_snd_controls),
1709 .dapm_widgets = rt5631_dapm_widgets, 1705 .dapm_widgets = rt5631_dapm_widgets,
@@ -1718,6 +1714,18 @@ static const struct i2c_device_id rt5631_i2c_id[] = {
1718}; 1714};
1719MODULE_DEVICE_TABLE(i2c, rt5631_i2c_id); 1715MODULE_DEVICE_TABLE(i2c, rt5631_i2c_id);
1720 1716
1717static const struct regmap_config rt5631_regmap_config = {
1718 .reg_bits = 8,
1719 .val_bits = 16,
1720
1721 .readable_reg = rt5631_readable_register,
1722 .volatile_reg = rt5631_volatile_register,
1723 .max_register = RT5631_VENDOR_ID2,
1724 .reg_defaults = rt5631_reg,
1725 .num_reg_defaults = ARRAY_SIZE(rt5631_reg),
1726 .cache_type = REGCACHE_RBTREE,
1727};
1728
1721static int rt5631_i2c_probe(struct i2c_client *i2c, 1729static int rt5631_i2c_probe(struct i2c_client *i2c,
1722 const struct i2c_device_id *id) 1730 const struct i2c_device_id *id)
1723{ 1731{
@@ -1731,6 +1739,10 @@ static int rt5631_i2c_probe(struct i2c_client *i2c,
1731 1739
1732 i2c_set_clientdata(i2c, rt5631); 1740 i2c_set_clientdata(i2c, rt5631);
1733 1741
1742 rt5631->regmap = devm_regmap_init_i2c(i2c, &rt5631_regmap_config);
1743 if (IS_ERR(rt5631->regmap))
1744 return PTR_ERR(rt5631->regmap);
1745
1734 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5631, 1746 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5631,
1735 rt5631_dai, ARRAY_SIZE(rt5631_dai)); 1747 rt5631_dai, ARRAY_SIZE(rt5631_dai));
1736 return ret; 1748 return ret;
@@ -1752,17 +1764,7 @@ static struct i2c_driver rt5631_i2c_driver = {
1752 .id_table = rt5631_i2c_id, 1764 .id_table = rt5631_i2c_id,
1753}; 1765};
1754 1766
1755static int __init rt5631_modinit(void) 1767module_i2c_driver(rt5631_i2c_driver);
1756{
1757 return i2c_add_driver(&rt5631_i2c_driver);
1758}
1759module_init(rt5631_modinit);
1760
1761static void __exit rt5631_modexit(void)
1762{
1763 i2c_del_driver(&rt5631_i2c_driver);
1764}
1765module_exit(rt5631_modexit);
1766 1768
1767MODULE_DESCRIPTION("ASoC RT5631 driver"); 1769MODULE_DESCRIPTION("ASoC RT5631 driver");
1768MODULE_AUTHOR("flove <flove@realtek.com>"); 1770MODULE_AUTHOR("flove <flove@realtek.com>");
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index c395ec370445..8af6a5245b18 100644
--- a/sound/soc/codecs/sgtl5000.c
+++ b/sound/soc/codecs/sgtl5000.c
@@ -84,8 +84,8 @@ static struct regulator_consumer_supply ldo_consumer[] = {
84 84
85static struct regulator_init_data ldo_init_data = { 85static struct regulator_init_data ldo_init_data = {
86 .constraints = { 86 .constraints = {
87 .min_uV = 850000, 87 .min_uV = 1200000,
88 .max_uV = 1600000, 88 .max_uV = 1200000,
89 .valid_modes_mask = REGULATOR_MODE_NORMAL, 89 .valid_modes_mask = REGULATOR_MODE_NORMAL,
90 .valid_ops_mask = REGULATOR_CHANGE_STATUS, 90 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
91 }, 91 },
@@ -197,9 +197,9 @@ static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
197 SND_SOC_DAPM_OUTPUT("HP_OUT"), 197 SND_SOC_DAPM_OUTPUT("HP_OUT"),
198 SND_SOC_DAPM_OUTPUT("LINE_OUT"), 198 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
199 199
200 SND_SOC_DAPM_MICBIAS_E("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0, 200 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
201 mic_bias_event, 201 mic_bias_event,
202 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 202 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
203 203
204 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0), 204 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
205 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0), 205 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
@@ -665,8 +665,7 @@ static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
665 struct snd_pcm_hw_params *params, 665 struct snd_pcm_hw_params *params,
666 struct snd_soc_dai *dai) 666 struct snd_soc_dai *dai)
667{ 667{
668 struct snd_soc_pcm_runtime *rtd = substream->private_data; 668 struct snd_soc_codec *codec = dai->codec;
669 struct snd_soc_codec *codec = rtd->codec;
670 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); 669 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
671 int channels = params_channels(params); 670 int channels = params_channels(params);
672 int i2s_ctl = 0; 671 int i2s_ctl = 0;
@@ -1455,17 +1454,7 @@ static struct i2c_driver sgtl5000_i2c_driver = {
1455 .id_table = sgtl5000_id, 1454 .id_table = sgtl5000_id,
1456}; 1455};
1457 1456
1458static int __init sgtl5000_modinit(void) 1457module_i2c_driver(sgtl5000_i2c_driver);
1459{
1460 return i2c_add_driver(&sgtl5000_i2c_driver);
1461}
1462module_init(sgtl5000_modinit);
1463
1464static void __exit sgtl5000_exit(void)
1465{
1466 i2c_del_driver(&sgtl5000_i2c_driver);
1467}
1468module_exit(sgtl5000_exit);
1469 1458
1470MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); 1459MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1471MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>"); 1460MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
diff --git a/sound/soc/codecs/ssm2602.c b/sound/soc/codecs/ssm2602.c
index de2b20544ceb..079066fef425 100644
--- a/sound/soc/codecs/ssm2602.c
+++ b/sound/soc/codecs/ssm2602.c
@@ -33,6 +33,7 @@
33#include <linux/pm.h> 33#include <linux/pm.h>
34#include <linux/i2c.h> 34#include <linux/i2c.h>
35#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
36#include <linux/regmap.h>
36#include <linux/slab.h> 37#include <linux/slab.h>
37#include <sound/core.h> 38#include <sound/core.h>
38#include <sound/pcm.h> 39#include <sound/pcm.h>
@@ -43,8 +44,6 @@
43 44
44#include "ssm2602.h" 45#include "ssm2602.h"
45 46
46#define SSM2602_VERSION "0.1"
47
48enum ssm2602_type { 47enum ssm2602_type {
49 SSM2602, 48 SSM2602,
50 SSM2604, 49 SSM2604,
@@ -53,10 +52,12 @@ enum ssm2602_type {
53/* codec private data */ 52/* codec private data */
54struct ssm2602_priv { 53struct ssm2602_priv {
55 unsigned int sysclk; 54 unsigned int sysclk;
56 enum snd_soc_control_type control_type; 55 struct snd_pcm_hw_constraint_list *sysclk_constraints;
57 struct snd_pcm_substream *master_substream; 56 struct snd_pcm_substream *master_substream;
58 struct snd_pcm_substream *slave_substream; 57 struct snd_pcm_substream *slave_substream;
59 58
59 struct regmap *regmap;
60
60 enum ssm2602_type type; 61 enum ssm2602_type type;
61 unsigned int clk_out_pwr; 62 unsigned int clk_out_pwr;
62}; 63};
@@ -73,7 +74,6 @@ static const u16 ssm2602_reg[SSM2602_CACHEREGNUM] = {
73 0x0000, 0x0000 74 0x0000, 0x0000
74}; 75};
75 76
76#define ssm2602_reset(c) snd_soc_write(c, SSM2602_RESET, 0)
77 77
78/*Appending several "None"s just for OSS mixer use*/ 78/*Appending several "None"s just for OSS mixer use*/
79static const char *ssm2602_input_select[] = { 79static const char *ssm2602_input_select[] = {
@@ -195,6 +195,24 @@ static const struct snd_soc_dapm_route ssm2604_routes[] = {
195 {"ADC", NULL, "Line Input"}, 195 {"ADC", NULL, "Line Input"},
196}; 196};
197 197
198static const unsigned int ssm2602_rates_12288000[] = {
199 8000, 32000, 48000, 96000,
200};
201
202static struct snd_pcm_hw_constraint_list ssm2602_constraints_12288000 = {
203 .list = ssm2602_rates_12288000,
204 .count = ARRAY_SIZE(ssm2602_rates_12288000),
205};
206
207static const unsigned int ssm2602_rates_11289600[] = {
208 8000, 44100, 88200,
209};
210
211static struct snd_pcm_hw_constraint_list ssm2602_constraints_11289600 = {
212 .list = ssm2602_rates_11289600,
213 .count = ARRAY_SIZE(ssm2602_rates_11289600),
214};
215
198struct ssm2602_coeff { 216struct ssm2602_coeff {
199 u32 mclk; 217 u32 mclk;
200 u32 rate; 218 u32 rate;
@@ -254,11 +272,10 @@ static int ssm2602_hw_params(struct snd_pcm_substream *substream,
254 struct snd_pcm_hw_params *params, 272 struct snd_pcm_hw_params *params,
255 struct snd_soc_dai *dai) 273 struct snd_soc_dai *dai)
256{ 274{
257 struct snd_soc_pcm_runtime *rtd = substream->private_data; 275 struct snd_soc_codec *codec = dai->codec;
258 struct snd_soc_codec *codec = rtd->codec;
259 struct ssm2602_priv *ssm2602 = snd_soc_codec_get_drvdata(codec); 276 struct ssm2602_priv *ssm2602 = snd_soc_codec_get_drvdata(codec);
260 u16 iface = snd_soc_read(codec, SSM2602_IFACE) & 0xfff3;
261 int srate = ssm2602_get_coeff(ssm2602->sysclk, params_rate(params)); 277 int srate = ssm2602_get_coeff(ssm2602->sysclk, params_rate(params));
278 unsigned int iface;
262 279
263 if (substream == ssm2602->slave_substream) { 280 if (substream == ssm2602->slave_substream) {
264 dev_dbg(codec->dev, "Ignoring hw_params for slave substream\n"); 281 dev_dbg(codec->dev, "Ignoring hw_params for slave substream\n");
@@ -268,31 +285,34 @@ static int ssm2602_hw_params(struct snd_pcm_substream *substream,
268 if (srate < 0) 285 if (srate < 0)
269 return srate; 286 return srate;
270 287
271 snd_soc_write(codec, SSM2602_SRATE, srate); 288 regmap_write(ssm2602->regmap, SSM2602_SRATE, srate);
272 289
273 /* bit size */ 290 /* bit size */
274 switch (params_format(params)) { 291 switch (params_format(params)) {
275 case SNDRV_PCM_FORMAT_S16_LE: 292 case SNDRV_PCM_FORMAT_S16_LE:
293 iface = 0x0;
276 break; 294 break;
277 case SNDRV_PCM_FORMAT_S20_3LE: 295 case SNDRV_PCM_FORMAT_S20_3LE:
278 iface |= 0x0004; 296 iface = 0x4;
279 break; 297 break;
280 case SNDRV_PCM_FORMAT_S24_LE: 298 case SNDRV_PCM_FORMAT_S24_LE:
281 iface |= 0x0008; 299 iface = 0x8;
282 break; 300 break;
283 case SNDRV_PCM_FORMAT_S32_LE: 301 case SNDRV_PCM_FORMAT_S32_LE:
284 iface |= 0x000c; 302 iface = 0xc;
285 break; 303 break;
304 default:
305 return -EINVAL;
286 } 306 }
287 snd_soc_write(codec, SSM2602_IFACE, iface); 307 regmap_update_bits(ssm2602->regmap, SSM2602_IFACE,
308 IFACE_AUDIO_DATA_LEN, iface);
288 return 0; 309 return 0;
289} 310}
290 311
291static int ssm2602_startup(struct snd_pcm_substream *substream, 312static int ssm2602_startup(struct snd_pcm_substream *substream,
292 struct snd_soc_dai *dai) 313 struct snd_soc_dai *dai)
293{ 314{
294 struct snd_soc_pcm_runtime *rtd = substream->private_data; 315 struct snd_soc_codec *codec = dai->codec;
295 struct snd_soc_codec *codec = rtd->codec;
296 struct ssm2602_priv *ssm2602 = snd_soc_codec_get_drvdata(codec); 316 struct ssm2602_priv *ssm2602 = snd_soc_codec_get_drvdata(codec);
297 struct snd_pcm_runtime *master_runtime; 317 struct snd_pcm_runtime *master_runtime;
298 318
@@ -322,14 +342,19 @@ static int ssm2602_startup(struct snd_pcm_substream *substream,
322 } else 342 } else
323 ssm2602->master_substream = substream; 343 ssm2602->master_substream = substream;
324 344
345 if (ssm2602->sysclk_constraints) {
346 snd_pcm_hw_constraint_list(substream->runtime, 0,
347 SNDRV_PCM_HW_PARAM_RATE,
348 ssm2602->sysclk_constraints);
349 }
350
325 return 0; 351 return 0;
326} 352}
327 353
328static void ssm2602_shutdown(struct snd_pcm_substream *substream, 354static void ssm2602_shutdown(struct snd_pcm_substream *substream,
329 struct snd_soc_dai *dai) 355 struct snd_soc_dai *dai)
330{ 356{
331 struct snd_soc_pcm_runtime *rtd = substream->private_data; 357 struct snd_soc_codec *codec = dai->codec;
332 struct snd_soc_codec *codec = rtd->codec;
333 struct ssm2602_priv *ssm2602 = snd_soc_codec_get_drvdata(codec); 358 struct ssm2602_priv *ssm2602 = snd_soc_codec_get_drvdata(codec);
334 359
335 if (ssm2602->master_substream == substream) 360 if (ssm2602->master_substream == substream)
@@ -341,14 +366,14 @@ static void ssm2602_shutdown(struct snd_pcm_substream *substream,
341 366
342static int ssm2602_mute(struct snd_soc_dai *dai, int mute) 367static int ssm2602_mute(struct snd_soc_dai *dai, int mute)
343{ 368{
344 struct snd_soc_codec *codec = dai->codec; 369 struct ssm2602_priv *ssm2602 = snd_soc_codec_get_drvdata(dai->codec);
345 370
346 if (mute) 371 if (mute)
347 snd_soc_update_bits(codec, SSM2602_APDIGI, 372 regmap_update_bits(ssm2602->regmap, SSM2602_APDIGI,
348 APDIGI_ENABLE_DAC_MUTE, 373 APDIGI_ENABLE_DAC_MUTE,
349 APDIGI_ENABLE_DAC_MUTE); 374 APDIGI_ENABLE_DAC_MUTE);
350 else 375 else
351 snd_soc_update_bits(codec, SSM2602_APDIGI, 376 regmap_update_bits(ssm2602->regmap, SSM2602_APDIGI,
352 APDIGI_ENABLE_DAC_MUTE, 0); 377 APDIGI_ENABLE_DAC_MUTE, 0);
353 return 0; 378 return 0;
354} 379}
@@ -364,16 +389,21 @@ static int ssm2602_set_dai_sysclk(struct snd_soc_dai *codec_dai,
364 return -EINVAL; 389 return -EINVAL;
365 390
366 switch (freq) { 391 switch (freq) {
367 case 11289600:
368 case 12000000:
369 case 12288000: 392 case 12288000:
370 case 16934400:
371 case 18432000: 393 case 18432000:
372 ssm2602->sysclk = freq; 394 ssm2602->sysclk_constraints = &ssm2602_constraints_12288000;
395 break;
396 case 11289600:
397 case 16934400:
398 ssm2602->sysclk_constraints = &ssm2602_constraints_11289600;
399 break;
400 case 12000000:
401 ssm2602->sysclk_constraints = NULL;
373 break; 402 break;
374 default: 403 default:
375 return -EINVAL; 404 return -EINVAL;
376 } 405 }
406 ssm2602->sysclk = freq;
377 } else { 407 } else {
378 unsigned int mask; 408 unsigned int mask;
379 409
@@ -393,7 +423,7 @@ static int ssm2602_set_dai_sysclk(struct snd_soc_dai *codec_dai,
393 else 423 else
394 ssm2602->clk_out_pwr &= ~mask; 424 ssm2602->clk_out_pwr &= ~mask;
395 425
396 snd_soc_update_bits(codec, SSM2602_PWR, 426 regmap_update_bits(ssm2602->regmap, SSM2602_PWR,
397 PWR_CLK_OUT_PDN | PWR_OSC_PDN, ssm2602->clk_out_pwr); 427 PWR_CLK_OUT_PDN | PWR_OSC_PDN, ssm2602->clk_out_pwr);
398 } 428 }
399 429
@@ -403,8 +433,8 @@ static int ssm2602_set_dai_sysclk(struct snd_soc_dai *codec_dai,
403static int ssm2602_set_dai_fmt(struct snd_soc_dai *codec_dai, 433static int ssm2602_set_dai_fmt(struct snd_soc_dai *codec_dai,
404 unsigned int fmt) 434 unsigned int fmt)
405{ 435{
406 struct snd_soc_codec *codec = codec_dai->codec; 436 struct ssm2602_priv *ssm2602 = snd_soc_codec_get_drvdata(codec_dai->codec);
407 u16 iface = 0; 437 unsigned int iface = 0;
408 438
409 /* set master/slave audio interface */ 439 /* set master/slave audio interface */
410 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 440 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -455,7 +485,7 @@ static int ssm2602_set_dai_fmt(struct snd_soc_dai *codec_dai,
455 } 485 }
456 486
457 /* set iface */ 487 /* set iface */
458 snd_soc_write(codec, SSM2602_IFACE, iface); 488 regmap_write(ssm2602->regmap, SSM2602_IFACE, iface);
459 return 0; 489 return 0;
460} 490}
461 491
@@ -467,7 +497,7 @@ static int ssm2602_set_bias_level(struct snd_soc_codec *codec,
467 switch (level) { 497 switch (level) {
468 case SND_SOC_BIAS_ON: 498 case SND_SOC_BIAS_ON:
469 /* vref/mid on, osc and clkout on if enabled */ 499 /* vref/mid on, osc and clkout on if enabled */
470 snd_soc_update_bits(codec, SSM2602_PWR, 500 regmap_update_bits(ssm2602->regmap, SSM2602_PWR,
471 PWR_POWER_OFF | PWR_CLK_OUT_PDN | PWR_OSC_PDN, 501 PWR_POWER_OFF | PWR_CLK_OUT_PDN | PWR_OSC_PDN,
472 ssm2602->clk_out_pwr); 502 ssm2602->clk_out_pwr);
473 break; 503 break;
@@ -475,13 +505,13 @@ static int ssm2602_set_bias_level(struct snd_soc_codec *codec,
475 break; 505 break;
476 case SND_SOC_BIAS_STANDBY: 506 case SND_SOC_BIAS_STANDBY:
477 /* everything off except vref/vmid, */ 507 /* everything off except vref/vmid, */
478 snd_soc_update_bits(codec, SSM2602_PWR, 508 regmap_update_bits(ssm2602->regmap, SSM2602_PWR,
479 PWR_POWER_OFF | PWR_CLK_OUT_PDN | PWR_OSC_PDN, 509 PWR_POWER_OFF | PWR_CLK_OUT_PDN | PWR_OSC_PDN,
480 PWR_CLK_OUT_PDN | PWR_OSC_PDN); 510 PWR_CLK_OUT_PDN | PWR_OSC_PDN);
481 break; 511 break;
482 case SND_SOC_BIAS_OFF: 512 case SND_SOC_BIAS_OFF:
483 /* everything off */ 513 /* everything off */
484 snd_soc_update_bits(codec, SSM2602_PWR, 514 regmap_update_bits(ssm2602->regmap, SSM2602_PWR,
485 PWR_POWER_OFF, PWR_POWER_OFF); 515 PWR_POWER_OFF, PWR_POWER_OFF);
486 break; 516 break;
487 517
@@ -540,12 +570,13 @@ static int ssm2602_resume(struct snd_soc_codec *codec)
540 570
541static int ssm2602_probe(struct snd_soc_codec *codec) 571static int ssm2602_probe(struct snd_soc_codec *codec)
542{ 572{
573 struct ssm2602_priv *ssm2602 = snd_soc_codec_get_drvdata(codec);
543 struct snd_soc_dapm_context *dapm = &codec->dapm; 574 struct snd_soc_dapm_context *dapm = &codec->dapm;
544 int ret; 575 int ret;
545 576
546 snd_soc_update_bits(codec, SSM2602_LOUT1V, 577 regmap_update_bits(ssm2602->regmap, SSM2602_LOUT1V,
547 LOUT1V_LRHP_BOTH, LOUT1V_LRHP_BOTH); 578 LOUT1V_LRHP_BOTH, LOUT1V_LRHP_BOTH);
548 snd_soc_update_bits(codec, SSM2602_ROUT1V, 579 regmap_update_bits(ssm2602->regmap, SSM2602_ROUT1V,
549 ROUT1V_RLHP_BOTH, ROUT1V_RLHP_BOTH); 580 ROUT1V_RLHP_BOTH, ROUT1V_RLHP_BOTH);
550 581
551 ret = snd_soc_add_codec_controls(codec, ssm2602_snd_controls, 582 ret = snd_soc_add_codec_controls(codec, ssm2602_snd_controls,
@@ -581,27 +612,26 @@ static int ssm260x_probe(struct snd_soc_codec *codec)
581 struct ssm2602_priv *ssm2602 = snd_soc_codec_get_drvdata(codec); 612 struct ssm2602_priv *ssm2602 = snd_soc_codec_get_drvdata(codec);
582 int ret; 613 int ret;
583 614
584 pr_info("ssm2602 Audio Codec %s", SSM2602_VERSION); 615 codec->control_data = ssm2602->regmap;
585 616 ret = snd_soc_codec_set_cache_io(codec, 0, 0, SND_SOC_REGMAP);
586 ret = snd_soc_codec_set_cache_io(codec, 7, 9, ssm2602->control_type);
587 if (ret < 0) { 617 if (ret < 0) {
588 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 618 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
589 return ret; 619 return ret;
590 } 620 }
591 621
592 ret = ssm2602_reset(codec); 622 ret = regmap_write(ssm2602->regmap, SSM2602_RESET, 0);
593 if (ret < 0) { 623 if (ret < 0) {
594 dev_err(codec->dev, "Failed to issue reset: %d\n", ret); 624 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
595 return ret; 625 return ret;
596 } 626 }
597 627
598 /* set the update bits */ 628 /* set the update bits */
599 snd_soc_update_bits(codec, SSM2602_LINVOL, 629 regmap_update_bits(ssm2602->regmap, SSM2602_LINVOL,
600 LINVOL_LRIN_BOTH, LINVOL_LRIN_BOTH); 630 LINVOL_LRIN_BOTH, LINVOL_LRIN_BOTH);
601 snd_soc_update_bits(codec, SSM2602_RINVOL, 631 regmap_update_bits(ssm2602->regmap, SSM2602_RINVOL,
602 RINVOL_RLIN_BOTH, RINVOL_RLIN_BOTH); 632 RINVOL_RLIN_BOTH, RINVOL_RLIN_BOTH);
603 /*select Line in as default input*/ 633 /*select Line in as default input*/
604 snd_soc_write(codec, SSM2602_APANA, APANA_SELECT_DAC | 634 regmap_write(ssm2602->regmap, SSM2602_APANA, APANA_SELECT_DAC |
605 APANA_ENABLE_MIC_BOOST); 635 APANA_ENABLE_MIC_BOOST);
606 636
607 switch (ssm2602->type) { 637 switch (ssm2602->type) {
@@ -634,9 +664,6 @@ static struct snd_soc_codec_driver soc_codec_dev_ssm2602 = {
634 .suspend = ssm2602_suspend, 664 .suspend = ssm2602_suspend,
635 .resume = ssm2602_resume, 665 .resume = ssm2602_resume,
636 .set_bias_level = ssm2602_set_bias_level, 666 .set_bias_level = ssm2602_set_bias_level,
637 .reg_cache_size = ARRAY_SIZE(ssm2602_reg),
638 .reg_word_size = sizeof(u16),
639 .reg_cache_default = ssm2602_reg,
640 667
641 .controls = ssm260x_snd_controls, 668 .controls = ssm260x_snd_controls,
642 .num_controls = ARRAY_SIZE(ssm260x_snd_controls), 669 .num_controls = ARRAY_SIZE(ssm260x_snd_controls),
@@ -646,6 +673,23 @@ static struct snd_soc_codec_driver soc_codec_dev_ssm2602 = {
646 .num_dapm_routes = ARRAY_SIZE(ssm260x_routes), 673 .num_dapm_routes = ARRAY_SIZE(ssm260x_routes),
647}; 674};
648 675
676static bool ssm2602_register_volatile(struct device *dev, unsigned int reg)
677{
678 return reg == SSM2602_RESET;
679}
680
681static const struct regmap_config ssm2602_regmap_config = {
682 .val_bits = 9,
683 .reg_bits = 7,
684
685 .max_register = SSM2602_RESET,
686 .volatile_reg = ssm2602_register_volatile,
687
688 .cache_type = REGCACHE_RBTREE,
689 .reg_defaults_raw = ssm2602_reg,
690 .num_reg_defaults_raw = ARRAY_SIZE(ssm2602_reg),
691};
692
649#if defined(CONFIG_SPI_MASTER) 693#if defined(CONFIG_SPI_MASTER)
650static int __devinit ssm2602_spi_probe(struct spi_device *spi) 694static int __devinit ssm2602_spi_probe(struct spi_device *spi)
651{ 695{
@@ -658,9 +702,12 @@ static int __devinit ssm2602_spi_probe(struct spi_device *spi)
658 return -ENOMEM; 702 return -ENOMEM;
659 703
660 spi_set_drvdata(spi, ssm2602); 704 spi_set_drvdata(spi, ssm2602);
661 ssm2602->control_type = SND_SOC_SPI;
662 ssm2602->type = SSM2602; 705 ssm2602->type = SSM2602;
663 706
707 ssm2602->regmap = devm_regmap_init_spi(spi, &ssm2602_regmap_config);
708 if (IS_ERR(ssm2602->regmap))
709 return PTR_ERR(ssm2602->regmap);
710
664 ret = snd_soc_register_codec(&spi->dev, 711 ret = snd_soc_register_codec(&spi->dev,
665 &soc_codec_dev_ssm2602, &ssm2602_dai, 1); 712 &soc_codec_dev_ssm2602, &ssm2602_dai, 1);
666 return ret; 713 return ret;
@@ -701,9 +748,12 @@ static int __devinit ssm2602_i2c_probe(struct i2c_client *i2c,
701 return -ENOMEM; 748 return -ENOMEM;
702 749
703 i2c_set_clientdata(i2c, ssm2602); 750 i2c_set_clientdata(i2c, ssm2602);
704 ssm2602->control_type = SND_SOC_I2C;
705 ssm2602->type = id->driver_data; 751 ssm2602->type = id->driver_data;
706 752
753 ssm2602->regmap = devm_regmap_init_i2c(i2c, &ssm2602_regmap_config);
754 if (IS_ERR(ssm2602->regmap))
755 return PTR_ERR(ssm2602->regmap);
756
707 ret = snd_soc_register_codec(&i2c->dev, 757 ret = snd_soc_register_codec(&i2c->dev,
708 &soc_codec_dev_ssm2602, &ssm2602_dai, 1); 758 &soc_codec_dev_ssm2602, &ssm2602_dai, 1);
709 return ret; 759 return ret;
diff --git a/sound/soc/codecs/sta32x.c b/sound/soc/codecs/sta32x.c
index 7db6fa515028..8d717f4b5a87 100644
--- a/sound/soc/codecs/sta32x.c
+++ b/sound/soc/codecs/sta32x.c
@@ -609,8 +609,7 @@ static int sta32x_hw_params(struct snd_pcm_substream *substream,
609 struct snd_pcm_hw_params *params, 609 struct snd_pcm_hw_params *params,
610 struct snd_soc_dai *dai) 610 struct snd_soc_dai *dai)
611{ 611{
612 struct snd_soc_pcm_runtime *rtd = substream->private_data; 612 struct snd_soc_codec *codec = dai->codec;
613 struct snd_soc_codec *codec = rtd->codec;
614 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec); 613 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
615 unsigned int rate; 614 unsigned int rate;
616 int i, mcs = -1, ir = -1; 615 int i, mcs = -1, ir = -1;
diff --git a/sound/soc/codecs/tlv320aic23.c b/sound/soc/codecs/tlv320aic23.c
index df1e07ffac32..31762ebdd774 100644
--- a/sound/soc/codecs/tlv320aic23.c
+++ b/sound/soc/codecs/tlv320aic23.c
@@ -34,8 +34,6 @@
34 34
35#include "tlv320aic23.h" 35#include "tlv320aic23.h"
36 36
37#define AIC23_VERSION "0.1"
38
39/* 37/*
40 * AIC23 register cache 38 * AIC23 register cache
41 */ 39 */
@@ -325,8 +323,7 @@ static int tlv320aic23_hw_params(struct snd_pcm_substream *substream,
325 struct snd_pcm_hw_params *params, 323 struct snd_pcm_hw_params *params,
326 struct snd_soc_dai *dai) 324 struct snd_soc_dai *dai)
327{ 325{
328 struct snd_soc_pcm_runtime *rtd = substream->private_data; 326 struct snd_soc_codec *codec = dai->codec;
329 struct snd_soc_codec *codec = rtd->codec;
330 u16 iface_reg; 327 u16 iface_reg;
331 int ret; 328 int ret;
332 struct aic23 *aic23 = snd_soc_codec_get_drvdata(codec); 329 struct aic23 *aic23 = snd_soc_codec_get_drvdata(codec);
@@ -371,8 +368,7 @@ static int tlv320aic23_hw_params(struct snd_pcm_substream *substream,
371static int tlv320aic23_pcm_prepare(struct snd_pcm_substream *substream, 368static int tlv320aic23_pcm_prepare(struct snd_pcm_substream *substream,
372 struct snd_soc_dai *dai) 369 struct snd_soc_dai *dai)
373{ 370{
374 struct snd_soc_pcm_runtime *rtd = substream->private_data; 371 struct snd_soc_codec *codec = dai->codec;
375 struct snd_soc_codec *codec = rtd->codec;
376 372
377 /* set active */ 373 /* set active */
378 snd_soc_write(codec, TLV320AIC23_ACTIVE, 0x0001); 374 snd_soc_write(codec, TLV320AIC23_ACTIVE, 0x0001);
@@ -383,8 +379,7 @@ static int tlv320aic23_pcm_prepare(struct snd_pcm_substream *substream,
383static void tlv320aic23_shutdown(struct snd_pcm_substream *substream, 379static void tlv320aic23_shutdown(struct snd_pcm_substream *substream,
384 struct snd_soc_dai *dai) 380 struct snd_soc_dai *dai)
385{ 381{
386 struct snd_soc_pcm_runtime *rtd = substream->private_data; 382 struct snd_soc_codec *codec = dai->codec;
387 struct snd_soc_codec *codec = rtd->codec;
388 struct aic23 *aic23 = snd_soc_codec_get_drvdata(codec); 383 struct aic23 *aic23 = snd_soc_codec_get_drvdata(codec);
389 384
390 /* deactivate */ 385 /* deactivate */
@@ -548,8 +543,6 @@ static int tlv320aic23_probe(struct snd_soc_codec *codec)
548 struct aic23 *aic23 = snd_soc_codec_get_drvdata(codec); 543 struct aic23 *aic23 = snd_soc_codec_get_drvdata(codec);
549 int ret; 544 int ret;
550 545
551 printk(KERN_INFO "AIC23 Audio Codec %s\n", AIC23_VERSION);
552
553 ret = snd_soc_codec_set_cache_io(codec, 7, 9, aic23->control_type); 546 ret = snd_soc_codec_set_cache_io(codec, 7, 9, aic23->control_type);
554 if (ret < 0) { 547 if (ret < 0) {
555 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 548 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
diff --git a/sound/soc/codecs/tlv320aic26.c b/sound/soc/codecs/tlv320aic26.c
index 802064b5030d..85944e953578 100644
--- a/sound/soc/codecs/tlv320aic26.c
+++ b/sound/soc/codecs/tlv320aic26.c
@@ -126,8 +126,7 @@ static int aic26_hw_params(struct snd_pcm_substream *substream,
126 struct snd_pcm_hw_params *params, 126 struct snd_pcm_hw_params *params,
127 struct snd_soc_dai *dai) 127 struct snd_soc_dai *dai)
128{ 128{
129 struct snd_soc_pcm_runtime *rtd = substream->private_data; 129 struct snd_soc_codec *codec = dai->codec;
130 struct snd_soc_codec *codec = rtd->codec;
131 struct aic26 *aic26 = snd_soc_codec_get_drvdata(codec); 130 struct aic26 *aic26 = snd_soc_codec_get_drvdata(codec);
132 int fsref, divisor, wlen, pval, jval, dval, qval; 131 int fsref, divisor, wlen, pval, jval, dval, qval;
133 u16 reg; 132 u16 reg;
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index 8d20f6ec20f3..64d2a4fa34b2 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -802,8 +802,7 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
802 struct snd_pcm_hw_params *params, 802 struct snd_pcm_hw_params *params,
803 struct snd_soc_dai *dai) 803 struct snd_soc_dai *dai)
804{ 804{
805 struct snd_soc_pcm_runtime *rtd = substream->private_data; 805 struct snd_soc_codec *codec = dai->codec;
806 struct snd_soc_codec *codec =rtd->codec;
807 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 806 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
808 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; 807 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
809 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; 808 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
@@ -1161,24 +1160,6 @@ static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1161 return 0; 1160 return 0;
1162} 1161}
1163 1162
1164void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1165 int headset_debounce, int button_debounce)
1166{
1167 u8 val;
1168
1169 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1170 << AIC3X_HEADSET_DETECT_SHIFT) |
1171 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1172 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1173 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1174 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1175
1176 if (detect & AIC3X_HEADSET_DETECT_MASK)
1177 val |= AIC3X_HEADSET_DETECT_ENABLED;
1178
1179 snd_soc_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
1180}
1181
1182#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 1163#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1183#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1164#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1184 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1165 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c
index 4587ddd0fbf8..0dd41077ab79 100644
--- a/sound/soc/codecs/tlv320dac33.c
+++ b/sound/soc/codecs/tlv320dac33.c
@@ -62,8 +62,10 @@
62#define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \ 62#define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
63 (((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate)))) 63 (((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate))))
64 64
65static void dac33_calculate_times(struct snd_pcm_substream *substream); 65static void dac33_calculate_times(struct snd_pcm_substream *substream,
66static int dac33_prepare_chip(struct snd_pcm_substream *substream); 66 struct snd_soc_codec *codec);
67static int dac33_prepare_chip(struct snd_pcm_substream *substream,
68 struct snd_soc_codec *codec);
67 69
68enum dac33_state { 70enum dac33_state {
69 DAC33_IDLE = 0, 71 DAC33_IDLE = 0,
@@ -427,8 +429,8 @@ static int dac33_playback_event(struct snd_soc_dapm_widget *w,
427 switch (event) { 429 switch (event) {
428 case SND_SOC_DAPM_PRE_PMU: 430 case SND_SOC_DAPM_PRE_PMU:
429 if (likely(dac33->substream)) { 431 if (likely(dac33->substream)) {
430 dac33_calculate_times(dac33->substream); 432 dac33_calculate_times(dac33->substream, w->codec);
431 dac33_prepare_chip(dac33->substream); 433 dac33_prepare_chip(dac33->substream, w->codec);
432 } 434 }
433 break; 435 break;
434 case SND_SOC_DAPM_POST_PMD: 436 case SND_SOC_DAPM_POST_PMD:
@@ -799,8 +801,7 @@ static void dac33_oscwait(struct snd_soc_codec *codec)
799static int dac33_startup(struct snd_pcm_substream *substream, 801static int dac33_startup(struct snd_pcm_substream *substream,
800 struct snd_soc_dai *dai) 802 struct snd_soc_dai *dai)
801{ 803{
802 struct snd_soc_pcm_runtime *rtd = substream->private_data; 804 struct snd_soc_codec *codec = dai->codec;
803 struct snd_soc_codec *codec = rtd->codec;
804 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 805 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
805 806
806 /* Stream started, save the substream pointer */ 807 /* Stream started, save the substream pointer */
@@ -812,8 +813,7 @@ static int dac33_startup(struct snd_pcm_substream *substream,
812static void dac33_shutdown(struct snd_pcm_substream *substream, 813static void dac33_shutdown(struct snd_pcm_substream *substream,
813 struct snd_soc_dai *dai) 814 struct snd_soc_dai *dai)
814{ 815{
815 struct snd_soc_pcm_runtime *rtd = substream->private_data; 816 struct snd_soc_codec *codec = dai->codec;
816 struct snd_soc_codec *codec = rtd->codec;
817 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 817 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
818 818
819 dac33->substream = NULL; 819 dac33->substream = NULL;
@@ -825,8 +825,7 @@ static int dac33_hw_params(struct snd_pcm_substream *substream,
825 struct snd_pcm_hw_params *params, 825 struct snd_pcm_hw_params *params,
826 struct snd_soc_dai *dai) 826 struct snd_soc_dai *dai)
827{ 827{
828 struct snd_soc_pcm_runtime *rtd = substream->private_data; 828 struct snd_soc_codec *codec = dai->codec;
829 struct snd_soc_codec *codec = rtd->codec;
830 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 829 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
831 830
832 /* Check parameters for validity */ 831 /* Check parameters for validity */
@@ -868,10 +867,9 @@ static int dac33_hw_params(struct snd_pcm_substream *substream,
868 * writes happens in different order, than dac33 might end up in unknown state. 867 * writes happens in different order, than dac33 might end up in unknown state.
869 * Use the known, working sequence of register writes to initialize the dac33. 868 * Use the known, working sequence of register writes to initialize the dac33.
870 */ 869 */
871static int dac33_prepare_chip(struct snd_pcm_substream *substream) 870static int dac33_prepare_chip(struct snd_pcm_substream *substream,
871 struct snd_soc_codec *codec)
872{ 872{
873 struct snd_soc_pcm_runtime *rtd = substream->private_data;
874 struct snd_soc_codec *codec = rtd->codec;
875 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 873 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
876 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp; 874 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
877 u8 aictrl_a, aictrl_b, fifoctrl_a; 875 u8 aictrl_a, aictrl_b, fifoctrl_a;
@@ -1067,10 +1065,9 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
1067 return 0; 1065 return 0;
1068} 1066}
1069 1067
1070static void dac33_calculate_times(struct snd_pcm_substream *substream) 1068static void dac33_calculate_times(struct snd_pcm_substream *substream,
1069 struct snd_soc_codec *codec)
1071{ 1070{
1072 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1073 struct snd_soc_codec *codec = rtd->codec;
1074 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1071 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1075 unsigned int period_size = substream->runtime->period_size; 1072 unsigned int period_size = substream->runtime->period_size;
1076 unsigned int rate = substream->runtime->rate; 1073 unsigned int rate = substream->runtime->rate;
@@ -1128,8 +1125,7 @@ static void dac33_calculate_times(struct snd_pcm_substream *substream)
1128static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd, 1125static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1129 struct snd_soc_dai *dai) 1126 struct snd_soc_dai *dai)
1130{ 1127{
1131 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1128 struct snd_soc_codec *codec = dai->codec;
1132 struct snd_soc_codec *codec = rtd->codec;
1133 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1129 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1134 int ret = 0; 1130 int ret = 0;
1135 1131
@@ -1161,8 +1157,7 @@ static snd_pcm_sframes_t dac33_dai_delay(
1161 struct snd_pcm_substream *substream, 1157 struct snd_pcm_substream *substream,
1162 struct snd_soc_dai *dai) 1158 struct snd_soc_dai *dai)
1163{ 1159{
1164 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1160 struct snd_soc_codec *codec = dai->codec;
1165 struct snd_soc_codec *codec = rtd->codec;
1166 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1161 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1167 unsigned long long t0, t1, t_now; 1162 unsigned long long t0, t1, t_now;
1168 unsigned int time_delta, uthr; 1163 unsigned int time_delta, uthr;
diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 170cf9a8fc79..391fcfc7b63b 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -1685,8 +1685,7 @@ static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1685static int twl4030_startup(struct snd_pcm_substream *substream, 1685static int twl4030_startup(struct snd_pcm_substream *substream,
1686 struct snd_soc_dai *dai) 1686 struct snd_soc_dai *dai)
1687{ 1687{
1688 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1688 struct snd_soc_codec *codec = dai->codec;
1689 struct snd_soc_codec *codec = rtd->codec;
1690 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); 1689 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1691 1690
1692 if (twl4030->master_substream) { 1691 if (twl4030->master_substream) {
@@ -1715,8 +1714,7 @@ static int twl4030_startup(struct snd_pcm_substream *substream,
1715static void twl4030_shutdown(struct snd_pcm_substream *substream, 1714static void twl4030_shutdown(struct snd_pcm_substream *substream,
1716 struct snd_soc_dai *dai) 1715 struct snd_soc_dai *dai)
1717{ 1716{
1718 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1717 struct snd_soc_codec *codec = dai->codec;
1719 struct snd_soc_codec *codec = rtd->codec;
1720 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); 1718 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1721 1719
1722 if (twl4030->master_substream == substream) 1720 if (twl4030->master_substream == substream)
@@ -1740,8 +1738,7 @@ static int twl4030_hw_params(struct snd_pcm_substream *substream,
1740 struct snd_pcm_hw_params *params, 1738 struct snd_pcm_hw_params *params,
1741 struct snd_soc_dai *dai) 1739 struct snd_soc_dai *dai)
1742{ 1740{
1743 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1741 struct snd_soc_codec *codec = dai->codec;
1744 struct snd_soc_codec *codec = rtd->codec;
1745 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); 1742 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1746 u8 mode, old_mode, format, old_format; 1743 u8 mode, old_mode, format, old_format;
1747 1744
@@ -1974,8 +1971,7 @@ static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1974static int twl4030_voice_startup(struct snd_pcm_substream *substream, 1971static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1975 struct snd_soc_dai *dai) 1972 struct snd_soc_dai *dai)
1976{ 1973{
1977 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1974 struct snd_soc_codec *codec = dai->codec;
1978 struct snd_soc_codec *codec = rtd->codec;
1979 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); 1975 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1980 u8 mode; 1976 u8 mode;
1981 1977
@@ -2007,8 +2003,7 @@ static int twl4030_voice_startup(struct snd_pcm_substream *substream,
2007static void twl4030_voice_shutdown(struct snd_pcm_substream *substream, 2003static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2008 struct snd_soc_dai *dai) 2004 struct snd_soc_dai *dai)
2009{ 2005{
2010 struct snd_soc_pcm_runtime *rtd = substream->private_data; 2006 struct snd_soc_codec *codec = dai->codec;
2011 struct snd_soc_codec *codec = rtd->codec;
2012 2007
2013 /* Enable voice digital filters */ 2008 /* Enable voice digital filters */
2014 twl4030_voice_enable(codec, substream->stream, 0); 2009 twl4030_voice_enable(codec, substream->stream, 0);
@@ -2017,8 +2012,7 @@ static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2017static int twl4030_voice_hw_params(struct snd_pcm_substream *substream, 2012static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2018 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 2013 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2019{ 2014{
2020 struct snd_soc_pcm_runtime *rtd = substream->private_data; 2015 struct snd_soc_codec *codec = dai->codec;
2021 struct snd_soc_codec *codec = rtd->codec;
2022 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); 2016 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2023 u8 old_mode, mode; 2017 u8 old_mode, mode;
2024 2018
diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c
index dc7509b9d53a..a36e9fcdf184 100644
--- a/sound/soc/codecs/twl6040.c
+++ b/sound/soc/codecs/twl6040.c
@@ -46,17 +46,6 @@
46#define TWL6040_OUTHF_0dB 0x03 46#define TWL6040_OUTHF_0dB 0x03
47#define TWL6040_OUTHF_M52dB 0x1D 47#define TWL6040_OUTHF_M52dB 0x1D
48 48
49#define TWL6040_RAMP_NONE 0
50#define TWL6040_RAMP_UP 1
51#define TWL6040_RAMP_DOWN 2
52
53#define TWL6040_HSL_VOL_MASK 0x0F
54#define TWL6040_HSL_VOL_SHIFT 0
55#define TWL6040_HSR_VOL_MASK 0xF0
56#define TWL6040_HSR_VOL_SHIFT 4
57#define TWL6040_HF_VOL_MASK 0x1F
58#define TWL6040_HF_VOL_SHIFT 0
59
60/* Shadow register used by the driver */ 49/* Shadow register used by the driver */
61#define TWL6040_REG_SW_SHADOW 0x2F 50#define TWL6040_REG_SW_SHADOW 0x2F
62#define TWL6040_CACHEREGNUM (TWL6040_REG_SW_SHADOW + 1) 51#define TWL6040_CACHEREGNUM (TWL6040_REG_SW_SHADOW + 1)
@@ -64,18 +53,6 @@
64/* TWL6040_REG_SW_SHADOW (0x2F) fields */ 53/* TWL6040_REG_SW_SHADOW (0x2F) fields */
65#define TWL6040_EAR_PATH_ENABLE 0x01 54#define TWL6040_EAR_PATH_ENABLE 0x01
66 55
67struct twl6040_output {
68 u16 active;
69 u16 left_vol;
70 u16 right_vol;
71 u16 left_step;
72 u16 right_step;
73 unsigned int step_delay;
74 u16 ramp;
75 struct delayed_work work;
76 struct completion ramp_done;
77};
78
79struct twl6040_jack_data { 56struct twl6040_jack_data {
80 struct snd_soc_jack *jack; 57 struct snd_soc_jack *jack;
81 struct delayed_work work; 58 struct delayed_work work;
@@ -100,8 +77,6 @@ struct twl6040_data {
100 struct snd_soc_codec *codec; 77 struct snd_soc_codec *codec;
101 struct workqueue_struct *workqueue; 78 struct workqueue_struct *workqueue;
102 struct mutex mutex; 79 struct mutex mutex;
103 struct twl6040_output headset;
104 struct twl6040_output handsfree;
105}; 80};
106 81
107/* 82/*
@@ -311,318 +286,6 @@ static void twl6040_restore_regs(struct snd_soc_codec *codec)
311 } 286 }
312} 287}
313 288
314/*
315 * Ramp HS PGA volume to minimise pops at stream startup and shutdown.
316 */
317static inline int twl6040_hs_ramp_step(struct snd_soc_codec *codec,
318 unsigned int left_step, unsigned int right_step)
319{
320
321 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
322 struct twl6040_output *headset = &priv->headset;
323 int left_complete = 0, right_complete = 0;
324 u8 reg, val;
325
326 /* left channel */
327 left_step = (left_step > 0xF) ? 0xF : left_step;
328 reg = twl6040_read_reg_cache(codec, TWL6040_REG_HSGAIN);
329 val = (~reg & TWL6040_HSL_VOL_MASK);
330
331 if (headset->ramp == TWL6040_RAMP_UP) {
332 /* ramp step up */
333 if (val < headset->left_vol) {
334 if (val + left_step > headset->left_vol)
335 val = headset->left_vol;
336 else
337 val += left_step;
338
339 reg &= ~TWL6040_HSL_VOL_MASK;
340 twl6040_write(codec, TWL6040_REG_HSGAIN,
341 (reg | (~val & TWL6040_HSL_VOL_MASK)));
342 } else {
343 left_complete = 1;
344 }
345 } else if (headset->ramp == TWL6040_RAMP_DOWN) {
346 /* ramp step down */
347 if (val > 0x0) {
348 if ((int)val - (int)left_step < 0)
349 val = 0;
350 else
351 val -= left_step;
352
353 reg &= ~TWL6040_HSL_VOL_MASK;
354 twl6040_write(codec, TWL6040_REG_HSGAIN, reg |
355 (~val & TWL6040_HSL_VOL_MASK));
356 } else {
357 left_complete = 1;
358 }
359 }
360
361 /* right channel */
362 right_step = (right_step > 0xF) ? 0xF : right_step;
363 reg = twl6040_read_reg_cache(codec, TWL6040_REG_HSGAIN);
364 val = (~reg & TWL6040_HSR_VOL_MASK) >> TWL6040_HSR_VOL_SHIFT;
365
366 if (headset->ramp == TWL6040_RAMP_UP) {
367 /* ramp step up */
368 if (val < headset->right_vol) {
369 if (val + right_step > headset->right_vol)
370 val = headset->right_vol;
371 else
372 val += right_step;
373
374 reg &= ~TWL6040_HSR_VOL_MASK;
375 twl6040_write(codec, TWL6040_REG_HSGAIN,
376 (reg | (~val << TWL6040_HSR_VOL_SHIFT)));
377 } else {
378 right_complete = 1;
379 }
380 } else if (headset->ramp == TWL6040_RAMP_DOWN) {
381 /* ramp step down */
382 if (val > 0x0) {
383 if ((int)val - (int)right_step < 0)
384 val = 0;
385 else
386 val -= right_step;
387
388 reg &= ~TWL6040_HSR_VOL_MASK;
389 twl6040_write(codec, TWL6040_REG_HSGAIN,
390 reg | (~val << TWL6040_HSR_VOL_SHIFT));
391 } else {
392 right_complete = 1;
393 }
394 }
395
396 return left_complete & right_complete;
397}
398
399/*
400 * Ramp HF PGA volume to minimise pops at stream startup and shutdown.
401 */
402static inline int twl6040_hf_ramp_step(struct snd_soc_codec *codec,
403 unsigned int left_step, unsigned int right_step)
404{
405 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
406 struct twl6040_output *handsfree = &priv->handsfree;
407 int left_complete = 0, right_complete = 0;
408 u16 reg, val;
409
410 /* left channel */
411 left_step = (left_step > 0x1D) ? 0x1D : left_step;
412 reg = twl6040_read_reg_cache(codec, TWL6040_REG_HFLGAIN);
413 reg = 0x1D - reg;
414 val = (reg & TWL6040_HF_VOL_MASK);
415 if (handsfree->ramp == TWL6040_RAMP_UP) {
416 /* ramp step up */
417 if (val < handsfree->left_vol) {
418 if (val + left_step > handsfree->left_vol)
419 val = handsfree->left_vol;
420 else
421 val += left_step;
422
423 reg &= ~TWL6040_HF_VOL_MASK;
424 twl6040_write(codec, TWL6040_REG_HFLGAIN,
425 reg | (0x1D - val));
426 } else {
427 left_complete = 1;
428 }
429 } else if (handsfree->ramp == TWL6040_RAMP_DOWN) {
430 /* ramp step down */
431 if (val > 0) {
432 if ((int)val - (int)left_step < 0)
433 val = 0;
434 else
435 val -= left_step;
436
437 reg &= ~TWL6040_HF_VOL_MASK;
438 twl6040_write(codec, TWL6040_REG_HFLGAIN,
439 reg | (0x1D - val));
440 } else {
441 left_complete = 1;
442 }
443 }
444
445 /* right channel */
446 right_step = (right_step > 0x1D) ? 0x1D : right_step;
447 reg = twl6040_read_reg_cache(codec, TWL6040_REG_HFRGAIN);
448 reg = 0x1D - reg;
449 val = (reg & TWL6040_HF_VOL_MASK);
450 if (handsfree->ramp == TWL6040_RAMP_UP) {
451 /* ramp step up */
452 if (val < handsfree->right_vol) {
453 if (val + right_step > handsfree->right_vol)
454 val = handsfree->right_vol;
455 else
456 val += right_step;
457
458 reg &= ~TWL6040_HF_VOL_MASK;
459 twl6040_write(codec, TWL6040_REG_HFRGAIN,
460 reg | (0x1D - val));
461 } else {
462 right_complete = 1;
463 }
464 } else if (handsfree->ramp == TWL6040_RAMP_DOWN) {
465 /* ramp step down */
466 if (val > 0) {
467 if ((int)val - (int)right_step < 0)
468 val = 0;
469 else
470 val -= right_step;
471
472 reg &= ~TWL6040_HF_VOL_MASK;
473 twl6040_write(codec, TWL6040_REG_HFRGAIN,
474 reg | (0x1D - val));
475 }
476 }
477
478 return left_complete & right_complete;
479}
480
481/*
482 * This work ramps both output PGAs at stream start/stop time to
483 * minimise pop associated with DAPM power switching.
484 */
485static void twl6040_pga_hs_work(struct work_struct *work)
486{
487 struct twl6040_data *priv =
488 container_of(work, struct twl6040_data, headset.work.work);
489 struct snd_soc_codec *codec = priv->codec;
490 struct twl6040_output *headset = &priv->headset;
491 int i, headset_complete;
492
493 /* do we need to ramp at all ? */
494 if (headset->ramp == TWL6040_RAMP_NONE)
495 return;
496
497 /* HS PGA gain range: 0x0 - 0xf (0 - 15) */
498 for (i = 0; i < 16; i++) {
499 headset_complete = twl6040_hs_ramp_step(codec,
500 headset->left_step,
501 headset->right_step);
502
503 /* ramp finished ? */
504 if (headset_complete)
505 break;
506
507 schedule_timeout_interruptible(
508 msecs_to_jiffies(headset->step_delay));
509 }
510
511 if (headset->ramp == TWL6040_RAMP_DOWN) {
512 headset->active = 0;
513 complete(&headset->ramp_done);
514 } else {
515 headset->active = 1;
516 }
517 headset->ramp = TWL6040_RAMP_NONE;
518}
519
520static void twl6040_pga_hf_work(struct work_struct *work)
521{
522 struct twl6040_data *priv =
523 container_of(work, struct twl6040_data, handsfree.work.work);
524 struct snd_soc_codec *codec = priv->codec;
525 struct twl6040_output *handsfree = &priv->handsfree;
526 int i, handsfree_complete;
527
528 /* do we need to ramp at all ? */
529 if (handsfree->ramp == TWL6040_RAMP_NONE)
530 return;
531
532 /*
533 * HF PGA gain range: 0x00 - 0x1d (0 - 29) */
534 for (i = 0; i < 30; i++) {
535 handsfree_complete = twl6040_hf_ramp_step(codec,
536 handsfree->left_step,
537 handsfree->right_step);
538
539 /* ramp finished ? */
540 if (handsfree_complete)
541 break;
542
543 schedule_timeout_interruptible(
544 msecs_to_jiffies(handsfree->step_delay));
545 }
546
547
548 if (handsfree->ramp == TWL6040_RAMP_DOWN) {
549 handsfree->active = 0;
550 complete(&handsfree->ramp_done);
551 } else
552 handsfree->active = 1;
553 handsfree->ramp = TWL6040_RAMP_NONE;
554}
555
556static int out_drv_event(struct snd_soc_dapm_widget *w,
557 struct snd_kcontrol *kcontrol, int event)
558{
559 struct snd_soc_codec *codec = w->codec;
560 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
561 struct twl6040_output *out;
562 struct delayed_work *work;
563
564 switch (w->shift) {
565 case 2: /* Headset output driver */
566 out = &priv->headset;
567 work = &out->work;
568 /*
569 * Make sure, that we do not mess up variables for already
570 * executing work.
571 */
572 cancel_delayed_work_sync(work);
573
574 out->left_step = priv->hs_left_step;
575 out->right_step = priv->hs_right_step;
576 out->step_delay = 5; /* 5 ms between volume ramp steps */
577 break;
578 case 4: /* Handsfree output driver */
579 out = &priv->handsfree;
580 work = &out->work;
581 /*
582 * Make sure, that we do not mess up variables for already
583 * executing work.
584 */
585 cancel_delayed_work_sync(work);
586
587 out->left_step = priv->hf_left_step;
588 out->right_step = priv->hf_right_step;
589 out->step_delay = 5; /* 5 ms between volume ramp steps */
590 break;
591 default:
592 return -1;
593 }
594
595 switch (event) {
596 case SND_SOC_DAPM_POST_PMU:
597 if (out->active)
598 break;
599
600 /* don't use volume ramp for power-up */
601 out->ramp = TWL6040_RAMP_UP;
602 out->left_step = out->left_vol;
603 out->right_step = out->right_vol;
604
605 queue_delayed_work(priv->workqueue, work, msecs_to_jiffies(1));
606 break;
607
608 case SND_SOC_DAPM_PRE_PMD:
609 if (!out->active)
610 break;
611
612 /* use volume ramp for power-down */
613 out->ramp = TWL6040_RAMP_DOWN;
614 INIT_COMPLETION(out->ramp_done);
615
616 queue_delayed_work(priv->workqueue, work, msecs_to_jiffies(1));
617
618 wait_for_completion_timeout(&out->ramp_done,
619 msecs_to_jiffies(2000));
620 break;
621 }
622
623 return 0;
624}
625
626/* set headset dac and driver power mode */ 289/* set headset dac and driver power mode */
627static int headset_power_mode(struct snd_soc_codec *codec, int high_perf) 290static int headset_power_mode(struct snd_soc_codec *codec, int high_perf)
628{ 291{
@@ -747,71 +410,6 @@ static irqreturn_t twl6040_audio_handler(int irq, void *data)
747 return IRQ_HANDLED; 410 return IRQ_HANDLED;
748} 411}
749 412
750static int twl6040_put_volsw(struct snd_kcontrol *kcontrol,
751 struct snd_ctl_elem_value *ucontrol)
752{
753 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
754 struct twl6040_data *twl6040_priv = snd_soc_codec_get_drvdata(codec);
755 struct twl6040_output *out = NULL;
756 struct soc_mixer_control *mc =
757 (struct soc_mixer_control *)kcontrol->private_value;
758 int ret;
759
760 /* For HS and HF we shadow the values and only actually write
761 * them out when active in order to ensure the amplifier comes on
762 * as quietly as possible. */
763 switch (mc->reg) {
764 case TWL6040_REG_HSGAIN:
765 out = &twl6040_priv->headset;
766 break;
767 case TWL6040_REG_HFLGAIN:
768 out = &twl6040_priv->handsfree;
769 break;
770 default:
771 dev_warn(codec->dev, "%s: Unexpected register: 0x%02x\n",
772 __func__, mc->reg);
773 return -EINVAL;
774 }
775
776 out->left_vol = ucontrol->value.integer.value[0];
777 out->right_vol = ucontrol->value.integer.value[1];
778 if (!out->active)
779 return 1;
780
781 ret = snd_soc_put_volsw(kcontrol, ucontrol);
782 if (ret < 0)
783 return ret;
784
785 return 1;
786}
787
788static int twl6040_get_volsw(struct snd_kcontrol *kcontrol,
789 struct snd_ctl_elem_value *ucontrol)
790{
791 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
792 struct twl6040_data *twl6040_priv = snd_soc_codec_get_drvdata(codec);
793 struct twl6040_output *out = &twl6040_priv->headset;
794 struct soc_mixer_control *mc =
795 (struct soc_mixer_control *)kcontrol->private_value;
796
797 switch (mc->reg) {
798 case TWL6040_REG_HSGAIN:
799 out = &twl6040_priv->headset;
800 break;
801 case TWL6040_REG_HFLGAIN:
802 out = &twl6040_priv->handsfree;
803 break;
804 default:
805 dev_warn(codec->dev, "%s: Unexpected register: 0x%02x\n",
806 __func__, mc->reg);
807 return -EINVAL;
808 }
809
810 ucontrol->value.integer.value[0] = out->left_vol;
811 ucontrol->value.integer.value[1] = out->right_vol;
812 return 0;
813}
814
815static int twl6040_soc_dapm_put_vibra_enum(struct snd_kcontrol *kcontrol, 413static int twl6040_soc_dapm_put_vibra_enum(struct snd_kcontrol *kcontrol,
816 struct snd_ctl_elem_value *ucontrol) 414 struct snd_ctl_elem_value *ucontrol)
817{ 415{
@@ -1076,12 +674,10 @@ static const struct snd_kcontrol_new twl6040_snd_controls[] = {
1076 TWL6040_REG_LINEGAIN, 0, 3, 7, 0, afm_amp_tlv), 674 TWL6040_REG_LINEGAIN, 0, 3, 7, 0, afm_amp_tlv),
1077 675
1078 /* Playback gains */ 676 /* Playback gains */
1079 SOC_DOUBLE_EXT_TLV("Headset Playback Volume", 677 SOC_DOUBLE_TLV("Headset Playback Volume",
1080 TWL6040_REG_HSGAIN, 0, 4, 0xF, 1, twl6040_get_volsw, 678 TWL6040_REG_HSGAIN, 0, 4, 0xF, 1, hs_tlv),
1081 twl6040_put_volsw, hs_tlv), 679 SOC_DOUBLE_R_TLV("Handsfree Playback Volume",
1082 SOC_DOUBLE_R_EXT_TLV("Handsfree Playback Volume", 680 TWL6040_REG_HFLGAIN, TWL6040_REG_HFRGAIN, 0, 0x1D, 1, hf_tlv),
1083 TWL6040_REG_HFLGAIN, TWL6040_REG_HFRGAIN, 0, 0x1D, 1,
1084 twl6040_get_volsw, twl6040_put_volsw, hf_tlv),
1085 SOC_SINGLE_TLV("Earphone Playback Volume", 681 SOC_SINGLE_TLV("Earphone Playback Volume",
1086 TWL6040_REG_EARCTL, 1, 0xF, 1, ep_tlv), 682 TWL6040_REG_EARCTL, 1, 0xF, 1, ep_tlv),
1087 683
@@ -1180,22 +776,14 @@ static const struct snd_soc_dapm_widget twl6040_dapm_widgets[] = {
1180 &auxr_switch_control), 776 &auxr_switch_control),
1181 777
1182 /* Analog playback drivers */ 778 /* Analog playback drivers */
1183 SND_SOC_DAPM_OUT_DRV_E("HF Left Driver", 779 SND_SOC_DAPM_OUT_DRV("HF Left Driver",
1184 TWL6040_REG_HFLCTL, 4, 0, NULL, 0, 780 TWL6040_REG_HFLCTL, 4, 0, NULL, 0),
1185 out_drv_event, 781 SND_SOC_DAPM_OUT_DRV("HF Right Driver",
1186 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 782 TWL6040_REG_HFRCTL, 4, 0, NULL, 0),
1187 SND_SOC_DAPM_OUT_DRV_E("HF Right Driver", 783 SND_SOC_DAPM_OUT_DRV("HS Left Driver",
1188 TWL6040_REG_HFRCTL, 4, 0, NULL, 0, 784 TWL6040_REG_HSLCTL, 2, 0, NULL, 0),
1189 out_drv_event, 785 SND_SOC_DAPM_OUT_DRV("HS Right Driver",
1190 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 786 TWL6040_REG_HSRCTL, 2, 0, NULL, 0),
1191 SND_SOC_DAPM_OUT_DRV_E("HS Left Driver",
1192 TWL6040_REG_HSLCTL, 2, 0, NULL, 0,
1193 out_drv_event,
1194 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1195 SND_SOC_DAPM_OUT_DRV_E("HS Right Driver",
1196 TWL6040_REG_HSRCTL, 2, 0, NULL, 0,
1197 out_drv_event,
1198 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1199 SND_SOC_DAPM_OUT_DRV_E("Earphone Driver", 787 SND_SOC_DAPM_OUT_DRV_E("Earphone Driver",
1200 TWL6040_REG_EARCTL, 0, 0, NULL, 0, 788 TWL6040_REG_EARCTL, 0, 0, NULL, 0,
1201 twl6040_ep_drv_event, 789 twl6040_ep_drv_event,
@@ -1339,8 +927,7 @@ static int twl6040_set_bias_level(struct snd_soc_codec *codec,
1339static int twl6040_startup(struct snd_pcm_substream *substream, 927static int twl6040_startup(struct snd_pcm_substream *substream,
1340 struct snd_soc_dai *dai) 928 struct snd_soc_dai *dai)
1341{ 929{
1342 struct snd_soc_pcm_runtime *rtd = substream->private_data; 930 struct snd_soc_codec *codec = dai->codec;
1343 struct snd_soc_codec *codec = rtd->codec;
1344 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); 931 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
1345 932
1346 snd_pcm_hw_constraint_list(substream->runtime, 0, 933 snd_pcm_hw_constraint_list(substream->runtime, 0,
@@ -1354,8 +941,7 @@ static int twl6040_hw_params(struct snd_pcm_substream *substream,
1354 struct snd_pcm_hw_params *params, 941 struct snd_pcm_hw_params *params,
1355 struct snd_soc_dai *dai) 942 struct snd_soc_dai *dai)
1356{ 943{
1357 struct snd_soc_pcm_runtime *rtd = substream->private_data; 944 struct snd_soc_codec *codec = dai->codec;
1358 struct snd_soc_codec *codec = rtd->codec;
1359 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); 945 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
1360 int rate; 946 int rate;
1361 947
@@ -1391,8 +977,7 @@ static int twl6040_hw_params(struct snd_pcm_substream *substream,
1391static int twl6040_prepare(struct snd_pcm_substream *substream, 977static int twl6040_prepare(struct snd_pcm_substream *substream,
1392 struct snd_soc_dai *dai) 978 struct snd_soc_dai *dai)
1393{ 979{
1394 struct snd_soc_pcm_runtime *rtd = substream->private_data; 980 struct snd_soc_codec *codec = dai->codec;
1395 struct snd_soc_codec *codec = rtd->codec;
1396 struct twl6040 *twl6040 = codec->control_data; 981 struct twl6040 *twl6040 = codec->control_data;
1397 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); 982 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
1398 int ret; 983 int ret;
@@ -1570,14 +1155,9 @@ static int twl6040_probe(struct snd_soc_codec *codec)
1570 } 1155 }
1571 1156
1572 INIT_DELAYED_WORK(&priv->hs_jack.work, twl6040_accessory_work); 1157 INIT_DELAYED_WORK(&priv->hs_jack.work, twl6040_accessory_work);
1573 INIT_DELAYED_WORK(&priv->headset.work, twl6040_pga_hs_work);
1574 INIT_DELAYED_WORK(&priv->handsfree.work, twl6040_pga_hf_work);
1575 1158
1576 mutex_init(&priv->mutex); 1159 mutex_init(&priv->mutex);
1577 1160
1578 init_completion(&priv->headset.ramp_done);
1579 init_completion(&priv->handsfree.ramp_done);
1580
1581 ret = request_threaded_irq(priv->plug_irq, NULL, twl6040_audio_handler, 1161 ret = request_threaded_irq(priv->plug_irq, NULL, twl6040_audio_handler,
1582 0, "twl6040_irq_plug", codec); 1162 0, "twl6040_irq_plug", codec);
1583 if (ret) { 1163 if (ret) {
diff --git a/sound/soc/codecs/uda134x.c b/sound/soc/codecs/uda134x.c
index 797b0dde2c68..6c3d43b8ee85 100644
--- a/sound/soc/codecs/uda134x.c
+++ b/sound/soc/codecs/uda134x.c
@@ -159,8 +159,7 @@ static int uda134x_mute(struct snd_soc_dai *dai, int mute)
159static int uda134x_startup(struct snd_pcm_substream *substream, 159static int uda134x_startup(struct snd_pcm_substream *substream,
160 struct snd_soc_dai *dai) 160 struct snd_soc_dai *dai)
161{ 161{
162 struct snd_soc_pcm_runtime *rtd = substream->private_data; 162 struct snd_soc_codec *codec = dai->codec;
163 struct snd_soc_codec *codec =rtd->codec;
164 struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec); 163 struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
165 struct snd_pcm_runtime *master_runtime; 164 struct snd_pcm_runtime *master_runtime;
166 165
@@ -191,8 +190,7 @@ static int uda134x_startup(struct snd_pcm_substream *substream,
191static void uda134x_shutdown(struct snd_pcm_substream *substream, 190static void uda134x_shutdown(struct snd_pcm_substream *substream,
192 struct snd_soc_dai *dai) 191 struct snd_soc_dai *dai)
193{ 192{
194 struct snd_soc_pcm_runtime *rtd = substream->private_data; 193 struct snd_soc_codec *codec = dai->codec;
195 struct snd_soc_codec *codec = rtd->codec;
196 struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec); 194 struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
197 195
198 if (uda134x->master_substream == substream) 196 if (uda134x->master_substream == substream)
diff --git a/sound/soc/codecs/uda1380.c b/sound/soc/codecs/uda1380.c
index 4f1b23d7e404..2502214b84ab 100644
--- a/sound/soc/codecs/uda1380.c
+++ b/sound/soc/codecs/uda1380.c
@@ -502,8 +502,7 @@ static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
502static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd, 502static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
503 struct snd_soc_dai *dai) 503 struct snd_soc_dai *dai)
504{ 504{
505 struct snd_soc_pcm_runtime *rtd = substream->private_data; 505 struct snd_soc_codec *codec = dai->codec;
506 struct snd_soc_codec *codec = rtd->codec;
507 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec); 506 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
508 int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER); 507 int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER);
509 508
@@ -528,8 +527,7 @@ static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
528 struct snd_pcm_hw_params *params, 527 struct snd_pcm_hw_params *params,
529 struct snd_soc_dai *dai) 528 struct snd_soc_dai *dai)
530{ 529{
531 struct snd_soc_pcm_runtime *rtd = substream->private_data; 530 struct snd_soc_codec *codec = dai->codec;
532 struct snd_soc_codec *codec = rtd->codec;
533 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK); 531 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
534 532
535 /* set WSPLL power and divider if running from this clock */ 533 /* set WSPLL power and divider if running from this clock */
diff --git a/sound/soc/codecs/wl1273.c b/sound/soc/codecs/wl1273.c
index 3d868dc40092..7b24d6d192e1 100644
--- a/sound/soc/codecs/wl1273.c
+++ b/sound/soc/codecs/wl1273.c
@@ -293,8 +293,7 @@ static const struct snd_kcontrol_new wl1273_controls[] = {
293static int wl1273_startup(struct snd_pcm_substream *substream, 293static int wl1273_startup(struct snd_pcm_substream *substream,
294 struct snd_soc_dai *dai) 294 struct snd_soc_dai *dai)
295{ 295{
296 struct snd_soc_pcm_runtime *rtd = substream->private_data; 296 struct snd_soc_codec *codec = dai->codec;
297 struct snd_soc_codec *codec = rtd->codec;
298 struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec); 297 struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(codec);
299 298
300 switch (wl1273->mode) { 299 switch (wl1273->mode) {
@@ -329,8 +328,7 @@ static int wl1273_hw_params(struct snd_pcm_substream *substream,
329 struct snd_pcm_hw_params *params, 328 struct snd_pcm_hw_params *params,
330 struct snd_soc_dai *dai) 329 struct snd_soc_dai *dai)
331{ 330{
332 struct snd_soc_pcm_runtime *rtd = substream->private_data; 331 struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(dai->codec);
333 struct wl1273_priv *wl1273 = snd_soc_codec_get_drvdata(rtd->codec);
334 struct wl1273_core *core = wl1273->core; 332 struct wl1273_core *core = wl1273->core;
335 unsigned int rate, width, r; 333 unsigned int rate, width, r;
336 334
diff --git a/sound/soc/codecs/wm1250-ev1.c b/sound/soc/codecs/wm1250-ev1.c
index aefb4f89be0e..e0b51e9f8b12 100644
--- a/sound/soc/codecs/wm1250-ev1.c
+++ b/sound/soc/codecs/wm1250-ev1.c
@@ -79,22 +79,65 @@ static const struct snd_soc_dapm_route wm1250_ev1_dapm_routes[] = {
79 { "WM1250 Output", NULL, "DAC" }, 79 { "WM1250 Output", NULL, "DAC" },
80}; 80};
81 81
82static int wm1250_ev1_hw_params(struct snd_pcm_substream *substream,
83 struct snd_pcm_hw_params *params,
84 struct snd_soc_dai *dai)
85{
86 struct wm1250_priv *wm1250 = snd_soc_codec_get_drvdata(dai->codec);
87
88 switch (params_rate(params)) {
89 case 8000:
90 gpio_set_value(wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL0].gpio,
91 1);
92 gpio_set_value(wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL1].gpio,
93 1);
94 break;
95 case 16000:
96 gpio_set_value(wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL0].gpio,
97 0);
98 gpio_set_value(wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL1].gpio,
99 1);
100 break;
101 case 32000:
102 gpio_set_value(wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL0].gpio,
103 1);
104 gpio_set_value(wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL1].gpio,
105 0);
106 break;
107 case 64000:
108 gpio_set_value(wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL0].gpio,
109 0);
110 gpio_set_value(wm1250->gpios[WM1250_EV1_GPIO_CLK_SEL1].gpio,
111 0);
112 break;
113 default:
114 return -EINVAL;
115 }
116
117 return 0;
118}
119
120static const struct snd_soc_dai_ops wm1250_ev1_ops = {
121 .hw_params = wm1250_ev1_hw_params,
122};
123
82static struct snd_soc_dai_driver wm1250_ev1_dai = { 124static struct snd_soc_dai_driver wm1250_ev1_dai = {
83 .name = "wm1250-ev1", 125 .name = "wm1250-ev1",
84 .playback = { 126 .playback = {
85 .stream_name = "Playback", 127 .stream_name = "Playback",
86 .channels_min = 1, 128 .channels_min = 1,
87 .channels_max = 1, 129 .channels_max = 2,
88 .rates = SNDRV_PCM_RATE_8000, 130 .rates = SNDRV_PCM_RATE_8000,
89 .formats = SNDRV_PCM_FMTBIT_S16_LE, 131 .formats = SNDRV_PCM_FMTBIT_S16_LE,
90 }, 132 },
91 .capture = { 133 .capture = {
92 .stream_name = "Capture", 134 .stream_name = "Capture",
93 .channels_min = 1, 135 .channels_min = 1,
94 .channels_max = 1, 136 .channels_max = 2,
95 .rates = SNDRV_PCM_RATE_8000, 137 .rates = SNDRV_PCM_RATE_8000,
96 .formats = SNDRV_PCM_FMTBIT_S16_LE, 138 .formats = SNDRV_PCM_FMTBIT_S16_LE,
97 }, 139 },
140 .ops = &wm1250_ev1_ops,
98}; 141};
99 142
100static struct snd_soc_codec_driver soc_codec_dev_wm1250_ev1 = { 143static struct snd_soc_codec_driver soc_codec_dev_wm1250_ev1 = {
@@ -215,23 +258,7 @@ static struct i2c_driver wm1250_ev1_i2c_driver = {
215 .id_table = wm1250_ev1_i2c_id, 258 .id_table = wm1250_ev1_i2c_id,
216}; 259};
217 260
218static int __init wm1250_ev1_modinit(void) 261module_i2c_driver(wm1250_ev1_i2c_driver);
219{
220 int ret = 0;
221
222 ret = i2c_add_driver(&wm1250_ev1_i2c_driver);
223 if (ret != 0)
224 pr_err("Failed to register WM1250-EV1 I2C driver: %d\n", ret);
225
226 return ret;
227}
228module_init(wm1250_ev1_modinit);
229
230static void __exit wm1250_ev1_exit(void)
231{
232 i2c_del_driver(&wm1250_ev1_i2c_driver);
233}
234module_exit(wm1250_ev1_exit);
235 262
236MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 263MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
237MODULE_DESCRIPTION("WM1250-EV1 audio I/O module driver"); 264MODULE_DESCRIPTION("WM1250-EV1 audio I/O module driver");
diff --git a/sound/soc/codecs/wm5100-tables.c b/sound/soc/codecs/wm5100-tables.c
index 9a18fae68204..e167207a19cc 100644
--- a/sound/soc/codecs/wm5100-tables.c
+++ b/sound/soc/codecs/wm5100-tables.c
@@ -32,7 +32,18 @@ bool wm5100_volatile_register(struct device *dev, unsigned int reg)
32 case WM5100_MIC_DETECT_3: 32 case WM5100_MIC_DETECT_3:
33 return 1; 33 return 1;
34 default: 34 default:
35 return 0; 35 if ((reg >= WM5100_DSP1_PM_0 && reg <= WM5100_DSP1_PM_1535) ||
36 (reg >= WM5100_DSP1_ZM_0 && reg <= WM5100_DSP1_ZM_2047) ||
37 (reg >= WM5100_DSP1_DM_0 && reg <= WM5100_DSP1_DM_511) ||
38 (reg >= WM5100_DSP2_PM_0 && reg <= WM5100_DSP2_PM_1535) ||
39 (reg >= WM5100_DSP2_ZM_0 && reg <= WM5100_DSP2_ZM_2047) ||
40 (reg >= WM5100_DSP2_DM_0 && reg <= WM5100_DSP2_DM_511) ||
41 (reg >= WM5100_DSP3_PM_0 && reg <= WM5100_DSP3_PM_1535) ||
42 (reg >= WM5100_DSP3_ZM_0 && reg <= WM5100_DSP3_ZM_2047) ||
43 (reg >= WM5100_DSP3_DM_0 && reg <= WM5100_DSP3_DM_511))
44 return 1;
45 else
46 return 0;
36 } 47 }
37} 48}
38 49
@@ -697,9 +708,110 @@ bool wm5100_readable_register(struct device *dev, unsigned int reg)
697 case WM5100_HPLPF3_2: 708 case WM5100_HPLPF3_2:
698 case WM5100_HPLPF4_1: 709 case WM5100_HPLPF4_1:
699 case WM5100_HPLPF4_2: 710 case WM5100_HPLPF4_2:
711 case WM5100_DSP1_CONTROL_1:
712 case WM5100_DSP1_CONTROL_2:
713 case WM5100_DSP1_CONTROL_3:
714 case WM5100_DSP1_CONTROL_4:
715 case WM5100_DSP1_CONTROL_5:
716 case WM5100_DSP1_CONTROL_6:
717 case WM5100_DSP1_CONTROL_7:
718 case WM5100_DSP1_CONTROL_8:
719 case WM5100_DSP1_CONTROL_9:
720 case WM5100_DSP1_CONTROL_10:
721 case WM5100_DSP1_CONTROL_11:
722 case WM5100_DSP1_CONTROL_12:
723 case WM5100_DSP1_CONTROL_13:
724 case WM5100_DSP1_CONTROL_14:
725 case WM5100_DSP1_CONTROL_15:
726 case WM5100_DSP1_CONTROL_16:
727 case WM5100_DSP1_CONTROL_17:
728 case WM5100_DSP1_CONTROL_18:
729 case WM5100_DSP1_CONTROL_19:
730 case WM5100_DSP1_CONTROL_20:
731 case WM5100_DSP1_CONTROL_21:
732 case WM5100_DSP1_CONTROL_22:
733 case WM5100_DSP1_CONTROL_23:
734 case WM5100_DSP1_CONTROL_24:
735 case WM5100_DSP1_CONTROL_25:
736 case WM5100_DSP1_CONTROL_26:
737 case WM5100_DSP1_CONTROL_27:
738 case WM5100_DSP1_CONTROL_28:
739 case WM5100_DSP1_CONTROL_29:
740 case WM5100_DSP1_CONTROL_30:
741 case WM5100_DSP2_CONTROL_1:
742 case WM5100_DSP2_CONTROL_2:
743 case WM5100_DSP2_CONTROL_3:
744 case WM5100_DSP2_CONTROL_4:
745 case WM5100_DSP2_CONTROL_5:
746 case WM5100_DSP2_CONTROL_6:
747 case WM5100_DSP2_CONTROL_7:
748 case WM5100_DSP2_CONTROL_8:
749 case WM5100_DSP2_CONTROL_9:
750 case WM5100_DSP2_CONTROL_10:
751 case WM5100_DSP2_CONTROL_11:
752 case WM5100_DSP2_CONTROL_12:
753 case WM5100_DSP2_CONTROL_13:
754 case WM5100_DSP2_CONTROL_14:
755 case WM5100_DSP2_CONTROL_15:
756 case WM5100_DSP2_CONTROL_16:
757 case WM5100_DSP2_CONTROL_17:
758 case WM5100_DSP2_CONTROL_18:
759 case WM5100_DSP2_CONTROL_19:
760 case WM5100_DSP2_CONTROL_20:
761 case WM5100_DSP2_CONTROL_21:
762 case WM5100_DSP2_CONTROL_22:
763 case WM5100_DSP2_CONTROL_23:
764 case WM5100_DSP2_CONTROL_24:
765 case WM5100_DSP2_CONTROL_25:
766 case WM5100_DSP2_CONTROL_26:
767 case WM5100_DSP2_CONTROL_27:
768 case WM5100_DSP2_CONTROL_28:
769 case WM5100_DSP2_CONTROL_29:
770 case WM5100_DSP2_CONTROL_30:
771 case WM5100_DSP3_CONTROL_1:
772 case WM5100_DSP3_CONTROL_2:
773 case WM5100_DSP3_CONTROL_3:
774 case WM5100_DSP3_CONTROL_4:
775 case WM5100_DSP3_CONTROL_5:
776 case WM5100_DSP3_CONTROL_6:
777 case WM5100_DSP3_CONTROL_7:
778 case WM5100_DSP3_CONTROL_8:
779 case WM5100_DSP3_CONTROL_9:
780 case WM5100_DSP3_CONTROL_10:
781 case WM5100_DSP3_CONTROL_11:
782 case WM5100_DSP3_CONTROL_12:
783 case WM5100_DSP3_CONTROL_13:
784 case WM5100_DSP3_CONTROL_14:
785 case WM5100_DSP3_CONTROL_15:
786 case WM5100_DSP3_CONTROL_16:
787 case WM5100_DSP3_CONTROL_17:
788 case WM5100_DSP3_CONTROL_18:
789 case WM5100_DSP3_CONTROL_19:
790 case WM5100_DSP3_CONTROL_20:
791 case WM5100_DSP3_CONTROL_21:
792 case WM5100_DSP3_CONTROL_22:
793 case WM5100_DSP3_CONTROL_23:
794 case WM5100_DSP3_CONTROL_24:
795 case WM5100_DSP3_CONTROL_25:
796 case WM5100_DSP3_CONTROL_26:
797 case WM5100_DSP3_CONTROL_27:
798 case WM5100_DSP3_CONTROL_28:
799 case WM5100_DSP3_CONTROL_29:
800 case WM5100_DSP3_CONTROL_30:
700 return 1; 801 return 1;
701 default: 802 default:
702 return 0; 803 if ((reg >= WM5100_DSP1_PM_0 && reg <= WM5100_DSP1_PM_1535) ||
804 (reg >= WM5100_DSP1_ZM_0 && reg <= WM5100_DSP1_ZM_2047) ||
805 (reg >= WM5100_DSP1_DM_0 && reg <= WM5100_DSP1_DM_511) ||
806 (reg >= WM5100_DSP2_PM_0 && reg <= WM5100_DSP2_PM_1535) ||
807 (reg >= WM5100_DSP2_ZM_0 && reg <= WM5100_DSP2_ZM_2047) ||
808 (reg >= WM5100_DSP2_DM_0 && reg <= WM5100_DSP2_DM_511) ||
809 (reg >= WM5100_DSP3_PM_0 && reg <= WM5100_DSP3_PM_1535) ||
810 (reg >= WM5100_DSP3_ZM_0 && reg <= WM5100_DSP3_ZM_2047) ||
811 (reg >= WM5100_DSP3_DM_0 && reg <= WM5100_DSP3_DM_511))
812 return 1;
813 else
814 return 0;
703 } 815 }
704} 816}
705 817
@@ -1361,4 +1473,13 @@ struct reg_default wm5100_reg_defaults[WM5100_REGISTER_COUNT] = {
1361 { 0x0EC9, 0x0000 }, /* R3785 - HPLPF3_2 */ 1473 { 0x0EC9, 0x0000 }, /* R3785 - HPLPF3_2 */
1362 { 0x0ECC, 0x0000 }, /* R3788 - HPLPF4_1 */ 1474 { 0x0ECC, 0x0000 }, /* R3788 - HPLPF4_1 */
1363 { 0x0ECD, 0x0000 }, /* R3789 - HPLPF4_2 */ 1475 { 0x0ECD, 0x0000 }, /* R3789 - HPLPF4_2 */
1476 { 0x0F02, 0x0000 }, /* R3842 - DSP1 Control 2 */
1477 { 0x0F03, 0x0000 }, /* R3843 - DSP1 Control 3 */
1478 { 0x0F04, 0x0000 }, /* R3844 - DSP1 Control 4 */
1479 { 0x1002, 0x0000 }, /* R4098 - DSP2 Control 2 */
1480 { 0x1003, 0x0000 }, /* R4099 - DSP2 Control 3 */
1481 { 0x1004, 0x0000 }, /* R4100 - DSP2 Control 4 */
1482 { 0x1102, 0x0000 }, /* R4354 - DSP3 Control 2 */
1483 { 0x1103, 0x0000 }, /* R4355 - DSP3 Control 3 */
1484 { 0x1104, 0x0000 }, /* R4356 - DSP3 Control 4 */
1364}; 1485};
diff --git a/sound/soc/codecs/wm5100.c b/sound/soc/codecs/wm5100.c
index b9c185ce64e4..cb6d5372103a 100644
--- a/sound/soc/codecs/wm5100.c
+++ b/sound/soc/codecs/wm5100.c
@@ -1265,29 +1265,12 @@ static const __devinitdata struct reg_default wm5100_reva_patches[] = {
1265 { WM5100_AUDIO_IF_3_19, 1 }, 1265 { WM5100_AUDIO_IF_3_19, 1 },
1266}; 1266};
1267 1267
1268static int wm5100_dai_to_base(struct snd_soc_dai *dai)
1269{
1270 switch (dai->id) {
1271 case 0:
1272 return WM5100_AUDIO_IF_1_1 - 1;
1273 case 1:
1274 return WM5100_AUDIO_IF_2_1 - 1;
1275 case 2:
1276 return WM5100_AUDIO_IF_3_1 - 1;
1277 default:
1278 BUG();
1279 return -EINVAL;
1280 }
1281}
1282
1283static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1268static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1284{ 1269{
1285 struct snd_soc_codec *codec = dai->codec; 1270 struct snd_soc_codec *codec = dai->codec;
1286 int lrclk, bclk, mask, base; 1271 int lrclk, bclk, mask, base;
1287 1272
1288 base = wm5100_dai_to_base(dai); 1273 base = dai->driver->base;
1289 if (base < 0)
1290 return base;
1291 1274
1292 lrclk = 0; 1275 lrclk = 0;
1293 bclk = 0; 1276 bclk = 0;
@@ -1414,9 +1397,7 @@ static int wm5100_hw_params(struct snd_pcm_substream *substream,
1414 int i, base, bclk, aif_rate, lrclk, wl, fl, sr; 1397 int i, base, bclk, aif_rate, lrclk, wl, fl, sr;
1415 int *bclk_rates; 1398 int *bclk_rates;
1416 1399
1417 base = wm5100_dai_to_base(dai); 1400 base = dai->driver->base;
1418 if (base < 0)
1419 return base;
1420 1401
1421 /* Data sizes if not using TDM */ 1402 /* Data sizes if not using TDM */
1422 wl = snd_pcm_format_width(params_format(params)); 1403 wl = snd_pcm_format_width(params_format(params));
@@ -1897,6 +1878,7 @@ static int wm5100_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
1897static struct snd_soc_dai_driver wm5100_dai[] = { 1878static struct snd_soc_dai_driver wm5100_dai[] = {
1898 { 1879 {
1899 .name = "wm5100-aif1", 1880 .name = "wm5100-aif1",
1881 .base = WM5100_AUDIO_IF_1_1 - 1,
1900 .playback = { 1882 .playback = {
1901 .stream_name = "AIF1 Playback", 1883 .stream_name = "AIF1 Playback",
1902 .channels_min = 2, 1884 .channels_min = 2,
@@ -1916,6 +1898,7 @@ static struct snd_soc_dai_driver wm5100_dai[] = {
1916 { 1898 {
1917 .name = "wm5100-aif2", 1899 .name = "wm5100-aif2",
1918 .id = 1, 1900 .id = 1,
1901 .base = WM5100_AUDIO_IF_2_1 - 1,
1919 .playback = { 1902 .playback = {
1920 .stream_name = "AIF2 Playback", 1903 .stream_name = "AIF2 Playback",
1921 .channels_min = 2, 1904 .channels_min = 2,
@@ -1935,6 +1918,7 @@ static struct snd_soc_dai_driver wm5100_dai[] = {
1935 { 1918 {
1936 .name = "wm5100-aif3", 1919 .name = "wm5100-aif3",
1937 .id = 2, 1920 .id = 2,
1921 .base = WM5100_AUDIO_IF_3_1 - 1,
1938 .playback = { 1922 .playback = {
1939 .stream_name = "AIF3 Playback", 1923 .stream_name = "AIF3 Playback",
1940 .channels_min = 2, 1924 .channels_min = 2,
@@ -2454,7 +2438,7 @@ static __devinit int wm5100_i2c_probe(struct i2c_client *i2c,
2454 2438
2455 wm5100->dev = &i2c->dev; 2439 wm5100->dev = &i2c->dev;
2456 2440
2457 wm5100->regmap = regmap_init_i2c(i2c, &wm5100_regmap); 2441 wm5100->regmap = devm_regmap_init_i2c(i2c, &wm5100_regmap);
2458 if (IS_ERR(wm5100->regmap)) { 2442 if (IS_ERR(wm5100->regmap)) {
2459 ret = PTR_ERR(wm5100->regmap); 2443 ret = PTR_ERR(wm5100->regmap);
2460 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 2444 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
@@ -2479,7 +2463,7 @@ static __devinit int wm5100_i2c_probe(struct i2c_client *i2c,
2479 if (ret != 0) { 2463 if (ret != 0) {
2480 dev_err(&i2c->dev, "Failed to request core supplies: %d\n", 2464 dev_err(&i2c->dev, "Failed to request core supplies: %d\n",
2481 ret); 2465 ret);
2482 goto err_regmap; 2466 goto err;
2483 } 2467 }
2484 2468
2485 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies), 2469 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
@@ -2487,7 +2471,7 @@ static __devinit int wm5100_i2c_probe(struct i2c_client *i2c,
2487 if (ret != 0) { 2471 if (ret != 0) {
2488 dev_err(&i2c->dev, "Failed to enable core supplies: %d\n", 2472 dev_err(&i2c->dev, "Failed to enable core supplies: %d\n",
2489 ret); 2473 ret);
2490 goto err_regmap; 2474 goto err;
2491 } 2475 }
2492 2476
2493 if (wm5100->pdata.ldo_ena) { 2477 if (wm5100->pdata.ldo_ena) {
@@ -2660,8 +2644,6 @@ err_ldo:
2660err_enable: 2644err_enable:
2661 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies), 2645 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2662 wm5100->core_supplies); 2646 wm5100->core_supplies);
2663err_regmap:
2664 regmap_exit(wm5100->regmap);
2665err: 2647err:
2666 return ret; 2648 return ret;
2667} 2649}
@@ -2682,7 +2664,6 @@ static __devexit int wm5100_i2c_remove(struct i2c_client *i2c)
2682 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0); 2664 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2683 gpio_free(wm5100->pdata.ldo_ena); 2665 gpio_free(wm5100->pdata.ldo_ena);
2684 } 2666 }
2685 regmap_exit(wm5100->regmap);
2686 2667
2687 return 0; 2668 return 0;
2688} 2669}
@@ -2749,17 +2730,7 @@ static struct i2c_driver wm5100_i2c_driver = {
2749 .id_table = wm5100_i2c_id, 2730 .id_table = wm5100_i2c_id,
2750}; 2731};
2751 2732
2752static int __init wm5100_modinit(void) 2733module_i2c_driver(wm5100_i2c_driver);
2753{
2754 return i2c_add_driver(&wm5100_i2c_driver);
2755}
2756module_init(wm5100_modinit);
2757
2758static void __exit wm5100_exit(void)
2759{
2760 i2c_del_driver(&wm5100_i2c_driver);
2761}
2762module_exit(wm5100_exit);
2763 2734
2764MODULE_DESCRIPTION("ASoC WM5100 driver"); 2735MODULE_DESCRIPTION("ASoC WM5100 driver");
2765MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 2736MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
diff --git a/sound/soc/codecs/wm5100.h b/sound/soc/codecs/wm5100.h
index 25cb6016f9d7..935a9b7fb274 100644
--- a/sound/soc/codecs/wm5100.h
+++ b/sound/soc/codecs/wm5100.h
@@ -709,6 +709,96 @@ int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
709#define WM5100_HPLPF3_2 0xEC9 709#define WM5100_HPLPF3_2 0xEC9
710#define WM5100_HPLPF4_1 0xECC 710#define WM5100_HPLPF4_1 0xECC
711#define WM5100_HPLPF4_2 0xECD 711#define WM5100_HPLPF4_2 0xECD
712#define WM5100_DSP1_CONTROL_1 0xF00
713#define WM5100_DSP1_CONTROL_2 0xF02
714#define WM5100_DSP1_CONTROL_3 0xF03
715#define WM5100_DSP1_CONTROL_4 0xF04
716#define WM5100_DSP1_CONTROL_5 0xF06
717#define WM5100_DSP1_CONTROL_6 0xF07
718#define WM5100_DSP1_CONTROL_7 0xF08
719#define WM5100_DSP1_CONTROL_8 0xF09
720#define WM5100_DSP1_CONTROL_9 0xF0A
721#define WM5100_DSP1_CONTROL_10 0xF0B
722#define WM5100_DSP1_CONTROL_11 0xF0C
723#define WM5100_DSP1_CONTROL_12 0xF0D
724#define WM5100_DSP1_CONTROL_13 0xF0F
725#define WM5100_DSP1_CONTROL_14 0xF10
726#define WM5100_DSP1_CONTROL_15 0xF11
727#define WM5100_DSP1_CONTROL_16 0xF12
728#define WM5100_DSP1_CONTROL_17 0xF13
729#define WM5100_DSP1_CONTROL_18 0xF14
730#define WM5100_DSP1_CONTROL_19 0xF16
731#define WM5100_DSP1_CONTROL_20 0xF17
732#define WM5100_DSP1_CONTROL_21 0xF18
733#define WM5100_DSP1_CONTROL_22 0xF1A
734#define WM5100_DSP1_CONTROL_23 0xF1B
735#define WM5100_DSP1_CONTROL_24 0xF1C
736#define WM5100_DSP1_CONTROL_25 0xF1E
737#define WM5100_DSP1_CONTROL_26 0xF20
738#define WM5100_DSP1_CONTROL_27 0xF21
739#define WM5100_DSP1_CONTROL_28 0xF22
740#define WM5100_DSP1_CONTROL_29 0xF23
741#define WM5100_DSP1_CONTROL_30 0xF24
742#define WM5100_DSP2_CONTROL_1 0x1000
743#define WM5100_DSP2_CONTROL_2 0x1002
744#define WM5100_DSP2_CONTROL_3 0x1003
745#define WM5100_DSP2_CONTROL_4 0x1004
746#define WM5100_DSP2_CONTROL_5 0x1006
747#define WM5100_DSP2_CONTROL_6 0x1007
748#define WM5100_DSP2_CONTROL_7 0x1008
749#define WM5100_DSP2_CONTROL_8 0x1009
750#define WM5100_DSP2_CONTROL_9 0x100A
751#define WM5100_DSP2_CONTROL_10 0x100B
752#define WM5100_DSP2_CONTROL_11 0x100C
753#define WM5100_DSP2_CONTROL_12 0x100D
754#define WM5100_DSP2_CONTROL_13 0x100F
755#define WM5100_DSP2_CONTROL_14 0x1010
756#define WM5100_DSP2_CONTROL_15 0x1011
757#define WM5100_DSP2_CONTROL_16 0x1012
758#define WM5100_DSP2_CONTROL_17 0x1013
759#define WM5100_DSP2_CONTROL_18 0x1014
760#define WM5100_DSP2_CONTROL_19 0x1016
761#define WM5100_DSP2_CONTROL_20 0x1017
762#define WM5100_DSP2_CONTROL_21 0x1018
763#define WM5100_DSP2_CONTROL_22 0x101A
764#define WM5100_DSP2_CONTROL_23 0x101B
765#define WM5100_DSP2_CONTROL_24 0x101C
766#define WM5100_DSP2_CONTROL_25 0x101E
767#define WM5100_DSP2_CONTROL_26 0x1020
768#define WM5100_DSP2_CONTROL_27 0x1021
769#define WM5100_DSP2_CONTROL_28 0x1022
770#define WM5100_DSP2_CONTROL_29 0x1023
771#define WM5100_DSP2_CONTROL_30 0x1024
772#define WM5100_DSP3_CONTROL_1 0x1100
773#define WM5100_DSP3_CONTROL_2 0x1102
774#define WM5100_DSP3_CONTROL_3 0x1103
775#define WM5100_DSP3_CONTROL_4 0x1104
776#define WM5100_DSP3_CONTROL_5 0x1106
777#define WM5100_DSP3_CONTROL_6 0x1107
778#define WM5100_DSP3_CONTROL_7 0x1108
779#define WM5100_DSP3_CONTROL_8 0x1109
780#define WM5100_DSP3_CONTROL_9 0x110A
781#define WM5100_DSP3_CONTROL_10 0x110B
782#define WM5100_DSP3_CONTROL_11 0x110C
783#define WM5100_DSP3_CONTROL_12 0x110D
784#define WM5100_DSP3_CONTROL_13 0x110F
785#define WM5100_DSP3_CONTROL_14 0x1110
786#define WM5100_DSP3_CONTROL_15 0x1111
787#define WM5100_DSP3_CONTROL_16 0x1112
788#define WM5100_DSP3_CONTROL_17 0x1113
789#define WM5100_DSP3_CONTROL_18 0x1114
790#define WM5100_DSP3_CONTROL_19 0x1116
791#define WM5100_DSP3_CONTROL_20 0x1117
792#define WM5100_DSP3_CONTROL_21 0x1118
793#define WM5100_DSP3_CONTROL_22 0x111A
794#define WM5100_DSP3_CONTROL_23 0x111B
795#define WM5100_DSP3_CONTROL_24 0x111C
796#define WM5100_DSP3_CONTROL_25 0x111E
797#define WM5100_DSP3_CONTROL_26 0x1120
798#define WM5100_DSP3_CONTROL_27 0x1121
799#define WM5100_DSP3_CONTROL_28 0x1122
800#define WM5100_DSP3_CONTROL_29 0x1123
801#define WM5100_DSP3_CONTROL_30 0x1124
712#define WM5100_DSP1_DM_0 0x4000 802#define WM5100_DSP1_DM_0 0x4000
713#define WM5100_DSP1_DM_1 0x4001 803#define WM5100_DSP1_DM_1 0x4001
714#define WM5100_DSP1_DM_2 0x4002 804#define WM5100_DSP1_DM_2 0x4002
@@ -4561,6 +4651,75 @@ int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack);
4561#define WM5100_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */ 4651#define WM5100_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */
4562 4652
4563/* 4653/*
4654 * R4132 (0x1024) - DSP2 Control 30
4655 */
4656#define WM5100_DSP2_RATE_MASK 0xC000 /* DSP2_RATE - [15:14] */
4657#define WM5100_DSP2_RATE_SHIFT 14 /* DSP2_RATE - [15:14] */
4658#define WM5100_DSP2_RATE_WIDTH 2 /* DSP2_RATE - [15:14] */
4659#define WM5100_DSP2_DBG_CLK_ENA 0x0008 /* DSP2_DBG_CLK_ENA */
4660#define WM5100_DSP2_DBG_CLK_ENA_MASK 0x0008 /* DSP2_DBG_CLK_ENA */
4661#define WM5100_DSP2_DBG_CLK_ENA_SHIFT 3 /* DSP2_DBG_CLK_ENA */
4662#define WM5100_DSP2_DBG_CLK_ENA_WIDTH 1 /* DSP2_DBG_CLK_ENA */
4663#define WM5100_DSP2_SYS_ENA 0x0004 /* DSP2_SYS_ENA */
4664#define WM5100_DSP2_SYS_ENA_MASK 0x0004 /* DSP2_SYS_ENA */
4665#define WM5100_DSP2_SYS_ENA_SHIFT 2 /* DSP2_SYS_ENA */
4666#define WM5100_DSP2_SYS_ENA_WIDTH 1 /* DSP2_SYS_ENA */
4667#define WM5100_DSP2_CORE_ENA 0x0002 /* DSP2_CORE_ENA */
4668#define WM5100_DSP2_CORE_ENA_MASK 0x0002 /* DSP2_CORE_ENA */
4669#define WM5100_DSP2_CORE_ENA_SHIFT 1 /* DSP2_CORE_ENA */
4670#define WM5100_DSP2_CORE_ENA_WIDTH 1 /* DSP2_CORE_ENA */
4671#define WM5100_DSP2_START 0x0001 /* DSP2_START */
4672#define WM5100_DSP2_START_MASK 0x0001 /* DSP2_START */
4673#define WM5100_DSP2_START_SHIFT 0 /* DSP2_START */
4674#define WM5100_DSP2_START_WIDTH 1 /* DSP2_START */
4675
4676/*
4677 * R3876 (0xF24) - DSP1 Control 30
4678 */
4679#define WM5100_DSP1_RATE_MASK 0xC000 /* DSP1_RATE - [15:14] */
4680#define WM5100_DSP1_RATE_SHIFT 14 /* DSP1_RATE - [15:14] */
4681#define WM5100_DSP1_RATE_WIDTH 2 /* DSP1_RATE - [15:14] */
4682#define WM5100_DSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
4683#define WM5100_DSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
4684#define WM5100_DSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
4685#define WM5100_DSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
4686#define WM5100_DSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
4687#define WM5100_DSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
4688#define WM5100_DSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
4689#define WM5100_DSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
4690#define WM5100_DSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
4691#define WM5100_DSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
4692#define WM5100_DSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
4693#define WM5100_DSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
4694#define WM5100_DSP1_START 0x0001 /* DSP1_START */
4695#define WM5100_DSP1_START_MASK 0x0001 /* DSP1_START */
4696#define WM5100_DSP1_START_SHIFT 0 /* DSP1_START */
4697#define WM5100_DSP1_START_WIDTH 1 /* DSP1_START */
4698
4699/*
4700 * R4388 (0x1124) - DSP3 Control 30
4701 */
4702#define WM5100_DSP3_RATE_MASK 0xC000 /* DSP3_RATE - [15:14] */
4703#define WM5100_DSP3_RATE_SHIFT 14 /* DSP3_RATE - [15:14] */
4704#define WM5100_DSP3_RATE_WIDTH 2 /* DSP3_RATE - [15:14] */
4705#define WM5100_DSP3_DBG_CLK_ENA 0x0008 /* DSP3_DBG_CLK_ENA */
4706#define WM5100_DSP3_DBG_CLK_ENA_MASK 0x0008 /* DSP3_DBG_CLK_ENA */
4707#define WM5100_DSP3_DBG_CLK_ENA_SHIFT 3 /* DSP3_DBG_CLK_ENA */
4708#define WM5100_DSP3_DBG_CLK_ENA_WIDTH 1 /* DSP3_DBG_CLK_ENA */
4709#define WM5100_DSP3_SYS_ENA 0x0004 /* DSP3_SYS_ENA */
4710#define WM5100_DSP3_SYS_ENA_MASK 0x0004 /* DSP3_SYS_ENA */
4711#define WM5100_DSP3_SYS_ENA_SHIFT 2 /* DSP3_SYS_ENA */
4712#define WM5100_DSP3_SYS_ENA_WIDTH 1 /* DSP3_SYS_ENA */
4713#define WM5100_DSP3_CORE_ENA 0x0002 /* DSP3_CORE_ENA */
4714#define WM5100_DSP3_CORE_ENA_MASK 0x0002 /* DSP3_CORE_ENA */
4715#define WM5100_DSP3_CORE_ENA_SHIFT 1 /* DSP3_CORE_ENA */
4716#define WM5100_DSP3_CORE_ENA_WIDTH 1 /* DSP3_CORE_ENA */
4717#define WM5100_DSP3_START 0x0001 /* DSP3_START */
4718#define WM5100_DSP3_START_MASK 0x0001 /* DSP3_START */
4719#define WM5100_DSP3_START_SHIFT 0 /* DSP3_START */
4720#define WM5100_DSP3_START_WIDTH 1 /* DSP3_START */
4721
4722/*
4564 * R16384 (0x4000) - DSP1 DM 0 4723 * R16384 (0x4000) - DSP1 DM 0
4565 */ 4724 */
4566#define WM5100_DSP1_DM_START_1_MASK 0x00FF /* DSP1_DM_START - [7:0] */ 4725#define WM5100_DSP1_DM_START_1_MASK 0x00FF /* DSP1_DM_START - [7:0] */
diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c
index aa12c6b6beeb..555ee146ae0d 100644
--- a/sound/soc/codecs/wm8350.c
+++ b/sound/soc/codecs/wm8350.c
@@ -71,13 +71,6 @@ struct wm8350_data {
71 int fll_freq_in; 71 int fll_freq_in;
72}; 72};
73 73
74static unsigned int wm8350_codec_cache_read(struct snd_soc_codec *codec,
75 unsigned int reg)
76{
77 struct wm8350 *wm8350 = codec->control_data;
78 return wm8350->reg_cache[reg];
79}
80
81static unsigned int wm8350_codec_read(struct snd_soc_codec *codec, 74static unsigned int wm8350_codec_read(struct snd_soc_codec *codec,
82 unsigned int reg) 75 unsigned int reg)
83{ 76{
@@ -99,7 +92,7 @@ static inline int wm8350_out1_ramp_step(struct snd_soc_codec *codec)
99{ 92{
100 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 93 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
101 struct wm8350_output *out1 = &wm8350_data->out1; 94 struct wm8350_output *out1 = &wm8350_data->out1;
102 struct wm8350 *wm8350 = codec->control_data; 95 struct wm8350 *wm8350 = wm8350_data->wm8350;
103 int left_complete = 0, right_complete = 0; 96 int left_complete = 0, right_complete = 0;
104 u16 reg, val; 97 u16 reg, val;
105 98
@@ -165,7 +158,7 @@ static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec)
165{ 158{
166 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 159 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
167 struct wm8350_output *out2 = &wm8350_data->out2; 160 struct wm8350_output *out2 = &wm8350_data->out2;
168 struct wm8350 *wm8350 = codec->control_data; 161 struct wm8350 *wm8350 = wm8350_data->wm8350;
169 int left_complete = 0, right_complete = 0; 162 int left_complete = 0, right_complete = 0;
170 u16 reg, val; 163 u16 reg, val;
171 164
@@ -360,8 +353,8 @@ static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
360 return ret; 353 return ret;
361 354
362 /* now hit the volume update bits (always bit 8) */ 355 /* now hit the volume update bits (always bit 8) */
363 val = wm8350_codec_read(codec, reg); 356 val = snd_soc_read(codec, reg);
364 wm8350_codec_write(codec, reg, val | WM8350_OUT1_VU); 357 snd_soc_write(codec, reg, val | WM8350_OUT1_VU);
365 return 1; 358 return 1;
366} 359}
367 360
@@ -781,7 +774,8 @@ static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
781 int clk_id, unsigned int freq, int dir) 774 int clk_id, unsigned int freq, int dir)
782{ 775{
783 struct snd_soc_codec *codec = codec_dai->codec; 776 struct snd_soc_codec *codec = codec_dai->codec;
784 struct wm8350 *wm8350 = codec->control_data; 777 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
778 struct wm8350 *wm8350 = wm8350_data->wm8350;
785 u16 fll_4; 779 u16 fll_4;
786 780
787 switch (clk_id) { 781 switch (clk_id) {
@@ -795,9 +789,9 @@ static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
795 case WM8350_MCLK_SEL_PLL_32K: 789 case WM8350_MCLK_SEL_PLL_32K:
796 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1, 790 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
797 WM8350_MCLK_SEL); 791 WM8350_MCLK_SEL);
798 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) & 792 fll_4 = snd_soc_read(codec, WM8350_FLL_CONTROL_4) &
799 ~WM8350_FLL_CLK_SRC_MASK; 793 ~WM8350_FLL_CLK_SRC_MASK;
800 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id); 794 snd_soc_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
801 break; 795 break;
802 } 796 }
803 797
@@ -819,39 +813,39 @@ static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
819 813
820 switch (div_id) { 814 switch (div_id) {
821 case WM8350_ADC_CLKDIV: 815 case WM8350_ADC_CLKDIV:
822 val = wm8350_codec_read(codec, WM8350_ADC_DIVIDER) & 816 val = snd_soc_read(codec, WM8350_ADC_DIVIDER) &
823 ~WM8350_ADC_CLKDIV_MASK; 817 ~WM8350_ADC_CLKDIV_MASK;
824 wm8350_codec_write(codec, WM8350_ADC_DIVIDER, val | div); 818 snd_soc_write(codec, WM8350_ADC_DIVIDER, val | div);
825 break; 819 break;
826 case WM8350_DAC_CLKDIV: 820 case WM8350_DAC_CLKDIV:
827 val = wm8350_codec_read(codec, WM8350_DAC_CLOCK_CONTROL) & 821 val = snd_soc_read(codec, WM8350_DAC_CLOCK_CONTROL) &
828 ~WM8350_DAC_CLKDIV_MASK; 822 ~WM8350_DAC_CLKDIV_MASK;
829 wm8350_codec_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div); 823 snd_soc_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div);
830 break; 824 break;
831 case WM8350_BCLK_CLKDIV: 825 case WM8350_BCLK_CLKDIV:
832 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) & 826 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) &
833 ~WM8350_BCLK_DIV_MASK; 827 ~WM8350_BCLK_DIV_MASK;
834 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div); 828 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
835 break; 829 break;
836 case WM8350_OPCLK_CLKDIV: 830 case WM8350_OPCLK_CLKDIV:
837 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) & 831 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) &
838 ~WM8350_OPCLK_DIV_MASK; 832 ~WM8350_OPCLK_DIV_MASK;
839 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div); 833 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
840 break; 834 break;
841 case WM8350_SYS_CLKDIV: 835 case WM8350_SYS_CLKDIV:
842 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) & 836 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) &
843 ~WM8350_MCLK_DIV_MASK; 837 ~WM8350_MCLK_DIV_MASK;
844 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div); 838 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
845 break; 839 break;
846 case WM8350_DACLR_CLKDIV: 840 case WM8350_DACLR_CLKDIV:
847 val = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) & 841 val = snd_soc_read(codec, WM8350_DAC_LR_RATE) &
848 ~WM8350_DACLRC_RATE_MASK; 842 ~WM8350_DACLRC_RATE_MASK;
849 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, val | div); 843 snd_soc_write(codec, WM8350_DAC_LR_RATE, val | div);
850 break; 844 break;
851 case WM8350_ADCLR_CLKDIV: 845 case WM8350_ADCLR_CLKDIV:
852 val = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) & 846 val = snd_soc_read(codec, WM8350_ADC_LR_RATE) &
853 ~WM8350_ADCLRC_RATE_MASK; 847 ~WM8350_ADCLRC_RATE_MASK;
854 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, val | div); 848 snd_soc_write(codec, WM8350_ADC_LR_RATE, val | div);
855 break; 849 break;
856 default: 850 default:
857 return -EINVAL; 851 return -EINVAL;
@@ -863,13 +857,13 @@ static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
863static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 857static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
864{ 858{
865 struct snd_soc_codec *codec = codec_dai->codec; 859 struct snd_soc_codec *codec = codec_dai->codec;
866 u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) & 860 u16 iface = snd_soc_read(codec, WM8350_AI_FORMATING) &
867 ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK); 861 ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
868 u16 master = wm8350_codec_read(codec, WM8350_AI_DAC_CONTROL) & 862 u16 master = snd_soc_read(codec, WM8350_AI_DAC_CONTROL) &
869 ~WM8350_BCLK_MSTR; 863 ~WM8350_BCLK_MSTR;
870 u16 dac_lrc = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) & 864 u16 dac_lrc = snd_soc_read(codec, WM8350_DAC_LR_RATE) &
871 ~WM8350_DACLRC_ENA; 865 ~WM8350_DACLRC_ENA;
872 u16 adc_lrc = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) & 866 u16 adc_lrc = snd_soc_read(codec, WM8350_ADC_LR_RATE) &
873 ~WM8350_ADCLRC_ENA; 867 ~WM8350_ADCLRC_ENA;
874 868
875 /* set master/slave audio interface */ 869 /* set master/slave audio interface */
@@ -922,42 +916,10 @@ static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
922 return -EINVAL; 916 return -EINVAL;
923 } 917 }
924 918
925 wm8350_codec_write(codec, WM8350_AI_FORMATING, iface); 919 snd_soc_write(codec, WM8350_AI_FORMATING, iface);
926 wm8350_codec_write(codec, WM8350_AI_DAC_CONTROL, master); 920 snd_soc_write(codec, WM8350_AI_DAC_CONTROL, master);
927 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, dac_lrc); 921 snd_soc_write(codec, WM8350_DAC_LR_RATE, dac_lrc);
928 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, adc_lrc); 922 snd_soc_write(codec, WM8350_ADC_LR_RATE, adc_lrc);
929 return 0;
930}
931
932static int wm8350_pcm_trigger(struct snd_pcm_substream *substream,
933 int cmd, struct snd_soc_dai *codec_dai)
934{
935 struct snd_soc_codec *codec = codec_dai->codec;
936 int master = wm8350_codec_cache_read(codec, WM8350_AI_DAC_CONTROL) &
937 WM8350_BCLK_MSTR;
938 int enabled = 0;
939
940 /* Check that the DACs or ADCs are enabled since they are
941 * required for LRC in master mode. The DACs or ADCs need a
942 * valid audio path i.e. pin -> ADC or DAC -> pin before
943 * the LRC will be enabled in master mode. */
944 if (!master || cmd != SNDRV_PCM_TRIGGER_START)
945 return 0;
946
947 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
948 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) &
949 (WM8350_ADCR_ENA | WM8350_ADCL_ENA);
950 } else {
951 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) &
952 (WM8350_DACR_ENA | WM8350_DACL_ENA);
953 }
954
955 if (!enabled) {
956 dev_err(codec->dev,
957 "%s: invalid audio path - no clocks available\n",
958 __func__);
959 return -EINVAL;
960 }
961 return 0; 923 return 0;
962} 924}
963 925
@@ -966,8 +928,9 @@ static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
966 struct snd_soc_dai *codec_dai) 928 struct snd_soc_dai *codec_dai)
967{ 929{
968 struct snd_soc_codec *codec = codec_dai->codec; 930 struct snd_soc_codec *codec = codec_dai->codec;
969 struct wm8350 *wm8350 = codec->control_data; 931 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
970 u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) & 932 struct wm8350 *wm8350 = wm8350_data->wm8350;
933 u16 iface = snd_soc_read(codec, WM8350_AI_FORMATING) &
971 ~WM8350_AIF_WL_MASK; 934 ~WM8350_AIF_WL_MASK;
972 935
973 /* bit size */ 936 /* bit size */
@@ -985,7 +948,7 @@ static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
985 break; 948 break;
986 } 949 }
987 950
988 wm8350_codec_write(codec, WM8350_AI_FORMATING, iface); 951 snd_soc_write(codec, WM8350_AI_FORMATING, iface);
989 952
990 /* The sloping stopband filter is recommended for use with 953 /* The sloping stopband filter is recommended for use with
991 * lower sample rates to improve performance. 954 * lower sample rates to improve performance.
@@ -1005,12 +968,15 @@ static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
1005static int wm8350_mute(struct snd_soc_dai *dai, int mute) 968static int wm8350_mute(struct snd_soc_dai *dai, int mute)
1006{ 969{
1007 struct snd_soc_codec *codec = dai->codec; 970 struct snd_soc_codec *codec = dai->codec;
1008 struct wm8350 *wm8350 = codec->control_data; 971 unsigned int val;
1009 972
1010 if (mute) 973 if (mute)
1011 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA); 974 val = WM8350_DAC_MUTE_ENA;
1012 else 975 else
1013 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA); 976 val = 0;
977
978 snd_soc_update_bits(codec, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA, val);
979
1014 return 0; 980 return 0;
1015} 981}
1016 982
@@ -1079,8 +1045,8 @@ static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
1079 unsigned int freq_out) 1045 unsigned int freq_out)
1080{ 1046{
1081 struct snd_soc_codec *codec = codec_dai->codec; 1047 struct snd_soc_codec *codec = codec_dai->codec;
1082 struct wm8350 *wm8350 = codec->control_data;
1083 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1048 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1049 struct wm8350 *wm8350 = priv->wm8350;
1084 struct _fll_div fll_div; 1050 struct _fll_div fll_div;
1085 int ret = 0; 1051 int ret = 0;
1086 u16 fll_1, fll_4; 1052 u16 fll_1, fll_4;
@@ -1104,17 +1070,17 @@ static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
1104 fll_div.ratio); 1070 fll_div.ratio);
1105 1071
1106 /* set up N.K & dividers */ 1072 /* set up N.K & dividers */
1107 fll_1 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_1) & 1073 fll_1 = snd_soc_read(codec, WM8350_FLL_CONTROL_1) &
1108 ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000); 1074 ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
1109 wm8350_codec_write(codec, WM8350_FLL_CONTROL_1, 1075 snd_soc_write(codec, WM8350_FLL_CONTROL_1,
1110 fll_1 | (fll_div.div << 8) | 0x50); 1076 fll_1 | (fll_div.div << 8) | 0x50);
1111 wm8350_codec_write(codec, WM8350_FLL_CONTROL_2, 1077 snd_soc_write(codec, WM8350_FLL_CONTROL_2,
1112 (fll_div.ratio << 11) | (fll_div. 1078 (fll_div.ratio << 11) | (fll_div.
1113 n & WM8350_FLL_N_MASK)); 1079 n & WM8350_FLL_N_MASK));
1114 wm8350_codec_write(codec, WM8350_FLL_CONTROL_3, fll_div.k); 1080 snd_soc_write(codec, WM8350_FLL_CONTROL_3, fll_div.k);
1115 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) & 1081 fll_4 = snd_soc_read(codec, WM8350_FLL_CONTROL_4) &
1116 ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF); 1082 ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
1117 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, 1083 snd_soc_write(codec, WM8350_FLL_CONTROL_4,
1118 fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) | 1084 fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
1119 (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0)); 1085 (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
1120 1086
@@ -1131,8 +1097,8 @@ static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
1131static int wm8350_set_bias_level(struct snd_soc_codec *codec, 1097static int wm8350_set_bias_level(struct snd_soc_codec *codec,
1132 enum snd_soc_bias_level level) 1098 enum snd_soc_bias_level level)
1133{ 1099{
1134 struct wm8350 *wm8350 = codec->control_data;
1135 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1100 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1101 struct wm8350 *wm8350 = priv->wm8350;
1136 struct wm8350_audio_platform_data *platform = 1102 struct wm8350_audio_platform_data *platform =
1137 wm8350->codec.platform_data; 1103 wm8350->codec.platform_data;
1138 u16 pm1; 1104 u16 pm1;
@@ -1339,35 +1305,36 @@ static void wm8350_hpr_work(struct work_struct *work)
1339 wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL); 1305 wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
1340} 1306}
1341 1307
1342static irqreturn_t wm8350_hp_jack_handler(int irq, void *data) 1308static irqreturn_t wm8350_hpl_jack_handler(int irq, void *data)
1343{ 1309{
1344 struct wm8350_data *priv = data; 1310 struct wm8350_data *priv = data;
1345 struct wm8350 *wm8350 = priv->wm8350; 1311 struct wm8350 *wm8350 = priv->wm8350;
1346 struct wm8350_jack_data *jack = NULL;
1347 1312
1348 switch (irq - wm8350->irq_base) {
1349 case WM8350_IRQ_CODEC_JCK_DET_L:
1350#ifndef CONFIG_SND_SOC_WM8350_MODULE 1313#ifndef CONFIG_SND_SOC_WM8350_MODULE
1351 trace_snd_soc_jack_irq("WM8350 HPL"); 1314 trace_snd_soc_jack_irq("WM8350 HPL");
1352#endif 1315#endif
1353 jack = &priv->hpl;
1354 break;
1355 1316
1356 case WM8350_IRQ_CODEC_JCK_DET_R: 1317 if (device_may_wakeup(wm8350->dev))
1318 pm_wakeup_event(wm8350->dev, 250);
1319
1320 schedule_delayed_work(&priv->hpl.work, 200);
1321
1322 return IRQ_HANDLED;
1323}
1324
1325static irqreturn_t wm8350_hpr_jack_handler(int irq, void *data)
1326{
1327 struct wm8350_data *priv = data;
1328 struct wm8350 *wm8350 = priv->wm8350;
1329
1357#ifndef CONFIG_SND_SOC_WM8350_MODULE 1330#ifndef CONFIG_SND_SOC_WM8350_MODULE
1358 trace_snd_soc_jack_irq("WM8350 HPR"); 1331 trace_snd_soc_jack_irq("WM8350 HPR");
1359#endif 1332#endif
1360 jack = &priv->hpr;
1361 break;
1362
1363 default:
1364 BUG();
1365 }
1366 1333
1367 if (device_may_wakeup(wm8350->dev)) 1334 if (device_may_wakeup(wm8350->dev))
1368 pm_wakeup_event(wm8350->dev, 250); 1335 pm_wakeup_event(wm8350->dev, 250);
1369 1336
1370 schedule_delayed_work(&jack->work, 200); 1337 schedule_delayed_work(&priv->hpr.work, 200);
1371 1338
1372 return IRQ_HANDLED; 1339 return IRQ_HANDLED;
1373} 1340}
@@ -1387,7 +1354,7 @@ int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which,
1387 struct snd_soc_jack *jack, int report) 1354 struct snd_soc_jack *jack, int report)
1388{ 1355{
1389 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1356 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1390 struct wm8350 *wm8350 = codec->control_data; 1357 struct wm8350 *wm8350 = priv->wm8350;
1391 int irq; 1358 int irq;
1392 int ena; 1359 int ena;
1393 1360
@@ -1418,7 +1385,14 @@ int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which,
1418 } 1385 }
1419 1386
1420 /* Sync status */ 1387 /* Sync status */
1421 wm8350_hp_jack_handler(irq + wm8350->irq_base, priv); 1388 switch (which) {
1389 case WM8350_JDL:
1390 wm8350_hpl_jack_handler(0, priv);
1391 break;
1392 case WM8350_JDR:
1393 wm8350_hpr_jack_handler(0, priv);
1394 break;
1395 }
1422 1396
1423 return 0; 1397 return 0;
1424} 1398}
@@ -1463,7 +1437,7 @@ int wm8350_mic_jack_detect(struct snd_soc_codec *codec,
1463 int detect_report, int short_report) 1437 int detect_report, int short_report)
1464{ 1438{
1465 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1439 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1466 struct wm8350 *wm8350 = codec->control_data; 1440 struct wm8350 *wm8350 = priv->wm8350;
1467 1441
1468 priv->mic.jack = jack; 1442 priv->mic.jack = jack;
1469 priv->mic.report = detect_report; 1443 priv->mic.report = detect_report;
@@ -1491,7 +1465,6 @@ EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);
1491static const struct snd_soc_dai_ops wm8350_dai_ops = { 1465static const struct snd_soc_dai_ops wm8350_dai_ops = {
1492 .hw_params = wm8350_pcm_hw_params, 1466 .hw_params = wm8350_pcm_hw_params,
1493 .digital_mute = wm8350_mute, 1467 .digital_mute = wm8350_mute,
1494 .trigger = wm8350_pcm_trigger,
1495 .set_fmt = wm8350_set_dai_fmt, 1468 .set_fmt = wm8350_set_dai_fmt,
1496 .set_sysclk = wm8350_set_dai_sysclk, 1469 .set_sysclk = wm8350_set_dai_sysclk,
1497 .set_pll = wm8350_set_fll, 1470 .set_pll = wm8350_set_fll,
@@ -1559,9 +1532,9 @@ static int wm8350_codec_probe(struct snd_soc_codec *codec)
1559 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1532 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1560 1533
1561 /* Enable robust clocking mode in ADC */ 1534 /* Enable robust clocking mode in ADC */
1562 wm8350_codec_write(codec, WM8350_SECURITY, 0xa7); 1535 snd_soc_write(codec, WM8350_SECURITY, 0xa7);
1563 wm8350_codec_write(codec, 0xde, 0x13); 1536 snd_soc_write(codec, 0xde, 0x13);
1564 wm8350_codec_write(codec, WM8350_SECURITY, 0); 1537 snd_soc_write(codec, WM8350_SECURITY, 0);
1565 1538
1566 /* read OUT1 & OUT2 volumes */ 1539 /* read OUT1 & OUT2 volumes */
1567 out1 = &priv->out1; 1540 out1 = &priv->out1;
@@ -1601,10 +1574,10 @@ static int wm8350_codec_probe(struct snd_soc_codec *codec)
1601 WM8350_JDL_ENA | WM8350_JDR_ENA); 1574 WM8350_JDL_ENA | WM8350_JDR_ENA);
1602 1575
1603 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, 1576 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
1604 wm8350_hp_jack_handler, 0, "Left jack detect", 1577 wm8350_hpl_jack_handler, 0, "Left jack detect",
1605 priv); 1578 priv);
1606 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, 1579 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
1607 wm8350_hp_jack_handler, 0, "Right jack detect", 1580 wm8350_hpr_jack_handler, 0, "Right jack detect",
1608 priv); 1581 priv);
1609 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, 1582 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD,
1610 wm8350_mic_handler, 0, "Microphone short", priv); 1583 wm8350_mic_handler, 0, "Microphone short", priv);
diff --git a/sound/soc/codecs/wm8400.c b/sound/soc/codecs/wm8400.c
index 898979d23010..5dc31ebcd0e7 100644
--- a/sound/soc/codecs/wm8400.c
+++ b/sound/soc/codecs/wm8400.c
@@ -138,8 +138,8 @@ static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
138 return ret; 138 return ret;
139 139
140 /* now hit the volume update bits (always bit 8) */ 140 /* now hit the volume update bits (always bit 8) */
141 val = wm8400_read(codec, reg); 141 val = snd_soc_read(codec, reg);
142 return wm8400_write(codec, reg, val | 0x0100); 142 return snd_soc_write(codec, reg, val | 0x0100);
143} 143}
144 144
145#define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \ 145#define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \
@@ -362,8 +362,8 @@ static int inmixer_event (struct snd_soc_dapm_widget *w,
362{ 362{
363 u16 reg, fakepower; 363 u16 reg, fakepower;
364 364
365 reg = wm8400_read(w->codec, WM8400_POWER_MANAGEMENT_2); 365 reg = snd_soc_read(w->codec, WM8400_POWER_MANAGEMENT_2);
366 fakepower = wm8400_read(w->codec, WM8400_INTDRIVBITS); 366 fakepower = snd_soc_read(w->codec, WM8400_INTDRIVBITS);
367 367
368 if (fakepower & ((1 << WM8400_INMIXL_PWR) | 368 if (fakepower & ((1 << WM8400_INMIXL_PWR) |
369 (1 << WM8400_AINLMUX_PWR))) { 369 (1 << WM8400_AINLMUX_PWR))) {
@@ -378,7 +378,7 @@ static int inmixer_event (struct snd_soc_dapm_widget *w,
378 } else { 378 } else {
379 reg &= ~WM8400_AINR_ENA; 379 reg &= ~WM8400_AINR_ENA;
380 } 380 }
381 wm8400_write(w->codec, WM8400_POWER_MANAGEMENT_2, reg); 381 snd_soc_write(w->codec, WM8400_POWER_MANAGEMENT_2, reg);
382 382
383 return 0; 383 return 0;
384} 384}
@@ -394,7 +394,7 @@ static int outmixer_event (struct snd_soc_dapm_widget *w,
394 394
395 switch (reg_shift) { 395 switch (reg_shift) {
396 case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) : 396 case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) :
397 reg = wm8400_read(w->codec, WM8400_OUTPUT_MIXER1); 397 reg = snd_soc_read(w->codec, WM8400_OUTPUT_MIXER1);
398 if (reg & WM8400_LDLO) { 398 if (reg & WM8400_LDLO) {
399 printk(KERN_WARNING 399 printk(KERN_WARNING
400 "Cannot set as Output Mixer 1 LDLO Set\n"); 400 "Cannot set as Output Mixer 1 LDLO Set\n");
@@ -402,7 +402,7 @@ static int outmixer_event (struct snd_soc_dapm_widget *w,
402 } 402 }
403 break; 403 break;
404 case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8): 404 case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8):
405 reg = wm8400_read(w->codec, WM8400_OUTPUT_MIXER2); 405 reg = snd_soc_read(w->codec, WM8400_OUTPUT_MIXER2);
406 if (reg & WM8400_RDRO) { 406 if (reg & WM8400_RDRO) {
407 printk(KERN_WARNING 407 printk(KERN_WARNING
408 "Cannot set as Output Mixer 2 RDRO Set\n"); 408 "Cannot set as Output Mixer 2 RDRO Set\n");
@@ -410,7 +410,7 @@ static int outmixer_event (struct snd_soc_dapm_widget *w,
410 } 410 }
411 break; 411 break;
412 case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8): 412 case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8):
413 reg = wm8400_read(w->codec, WM8400_SPEAKER_MIXER); 413 reg = snd_soc_read(w->codec, WM8400_SPEAKER_MIXER);
414 if (reg & WM8400_LDSPK) { 414 if (reg & WM8400_LDSPK) {
415 printk(KERN_WARNING 415 printk(KERN_WARNING
416 "Cannot set as Speaker Mixer LDSPK Set\n"); 416 "Cannot set as Speaker Mixer LDSPK Set\n");
@@ -418,7 +418,7 @@ static int outmixer_event (struct snd_soc_dapm_widget *w,
418 } 418 }
419 break; 419 break;
420 case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8): 420 case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8):
421 reg = wm8400_read(w->codec, WM8400_SPEAKER_MIXER); 421 reg = snd_soc_read(w->codec, WM8400_SPEAKER_MIXER);
422 if (reg & WM8400_RDSPK) { 422 if (reg & WM8400_RDSPK) {
423 printk(KERN_WARNING 423 printk(KERN_WARNING
424 "Cannot set as Speaker Mixer RDSPK Set\n"); 424 "Cannot set as Speaker Mixer RDSPK Set\n");
@@ -1021,13 +1021,13 @@ static int wm8400_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1021 wm8400->fll_in = freq_in; 1021 wm8400->fll_in = freq_in;
1022 1022
1023 /* We *must* disable the FLL before any changes */ 1023 /* We *must* disable the FLL before any changes */
1024 reg = wm8400_read(codec, WM8400_POWER_MANAGEMENT_2); 1024 reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_2);
1025 reg &= ~WM8400_FLL_ENA; 1025 reg &= ~WM8400_FLL_ENA;
1026 wm8400_write(codec, WM8400_POWER_MANAGEMENT_2, reg); 1026 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_2, reg);
1027 1027
1028 reg = wm8400_read(codec, WM8400_FLL_CONTROL_1); 1028 reg = snd_soc_read(codec, WM8400_FLL_CONTROL_1);
1029 reg &= ~WM8400_FLL_OSC_ENA; 1029 reg &= ~WM8400_FLL_OSC_ENA;
1030 wm8400_write(codec, WM8400_FLL_CONTROL_1, reg); 1030 snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg);
1031 1031
1032 if (!freq_out) 1032 if (!freq_out)
1033 return 0; 1033 return 0;
@@ -1035,15 +1035,15 @@ static int wm8400_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1035 reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK); 1035 reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK);
1036 reg |= WM8400_FLL_FRAC | factors.fratio; 1036 reg |= WM8400_FLL_FRAC | factors.fratio;
1037 reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT; 1037 reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT;
1038 wm8400_write(codec, WM8400_FLL_CONTROL_1, reg); 1038 snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg);
1039 1039
1040 wm8400_write(codec, WM8400_FLL_CONTROL_2, factors.k); 1040 snd_soc_write(codec, WM8400_FLL_CONTROL_2, factors.k);
1041 wm8400_write(codec, WM8400_FLL_CONTROL_3, factors.n); 1041 snd_soc_write(codec, WM8400_FLL_CONTROL_3, factors.n);
1042 1042
1043 reg = wm8400_read(codec, WM8400_FLL_CONTROL_4); 1043 reg = snd_soc_read(codec, WM8400_FLL_CONTROL_4);
1044 reg &= ~WM8400_FLL_OUTDIV_MASK; 1044 reg &= ~WM8400_FLL_OUTDIV_MASK;
1045 reg |= factors.outdiv; 1045 reg |= factors.outdiv;
1046 wm8400_write(codec, WM8400_FLL_CONTROL_4, reg); 1046 snd_soc_write(codec, WM8400_FLL_CONTROL_4, reg);
1047 1047
1048 return 0; 1048 return 0;
1049} 1049}
@@ -1057,8 +1057,8 @@ static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai,
1057 struct snd_soc_codec *codec = codec_dai->codec; 1057 struct snd_soc_codec *codec = codec_dai->codec;
1058 u16 audio1, audio3; 1058 u16 audio1, audio3;
1059 1059
1060 audio1 = wm8400_read(codec, WM8400_AUDIO_INTERFACE_1); 1060 audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1);
1061 audio3 = wm8400_read(codec, WM8400_AUDIO_INTERFACE_3); 1061 audio3 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_3);
1062 1062
1063 /* set master/slave audio interface */ 1063 /* set master/slave audio interface */
1064 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1064 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -1099,8 +1099,8 @@ static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai,
1099 return -EINVAL; 1099 return -EINVAL;
1100 } 1100 }
1101 1101
1102 wm8400_write(codec, WM8400_AUDIO_INTERFACE_1, audio1); 1102 snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1);
1103 wm8400_write(codec, WM8400_AUDIO_INTERFACE_3, audio3); 1103 snd_soc_write(codec, WM8400_AUDIO_INTERFACE_3, audio3);
1104 return 0; 1104 return 0;
1105} 1105}
1106 1106
@@ -1112,24 +1112,24 @@ static int wm8400_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1112 1112
1113 switch (div_id) { 1113 switch (div_id) {
1114 case WM8400_MCLK_DIV: 1114 case WM8400_MCLK_DIV:
1115 reg = wm8400_read(codec, WM8400_CLOCKING_2) & 1115 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
1116 ~WM8400_MCLK_DIV_MASK; 1116 ~WM8400_MCLK_DIV_MASK;
1117 wm8400_write(codec, WM8400_CLOCKING_2, reg | div); 1117 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
1118 break; 1118 break;
1119 case WM8400_DACCLK_DIV: 1119 case WM8400_DACCLK_DIV:
1120 reg = wm8400_read(codec, WM8400_CLOCKING_2) & 1120 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
1121 ~WM8400_DAC_CLKDIV_MASK; 1121 ~WM8400_DAC_CLKDIV_MASK;
1122 wm8400_write(codec, WM8400_CLOCKING_2, reg | div); 1122 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
1123 break; 1123 break;
1124 case WM8400_ADCCLK_DIV: 1124 case WM8400_ADCCLK_DIV:
1125 reg = wm8400_read(codec, WM8400_CLOCKING_2) & 1125 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
1126 ~WM8400_ADC_CLKDIV_MASK; 1126 ~WM8400_ADC_CLKDIV_MASK;
1127 wm8400_write(codec, WM8400_CLOCKING_2, reg | div); 1127 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
1128 break; 1128 break;
1129 case WM8400_BCLK_DIV: 1129 case WM8400_BCLK_DIV:
1130 reg = wm8400_read(codec, WM8400_CLOCKING_1) & 1130 reg = snd_soc_read(codec, WM8400_CLOCKING_1) &
1131 ~WM8400_BCLK_DIV_MASK; 1131 ~WM8400_BCLK_DIV_MASK;
1132 wm8400_write(codec, WM8400_CLOCKING_1, reg | div); 1132 snd_soc_write(codec, WM8400_CLOCKING_1, reg | div);
1133 break; 1133 break;
1134 default: 1134 default:
1135 return -EINVAL; 1135 return -EINVAL;
@@ -1145,9 +1145,8 @@ static int wm8400_hw_params(struct snd_pcm_substream *substream,
1145 struct snd_pcm_hw_params *params, 1145 struct snd_pcm_hw_params *params,
1146 struct snd_soc_dai *dai) 1146 struct snd_soc_dai *dai)
1147{ 1147{
1148 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1148 struct snd_soc_codec *codec = dai->codec;
1149 struct snd_soc_codec *codec = rtd->codec; 1149 u16 audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1);
1150 u16 audio1 = wm8400_read(codec, WM8400_AUDIO_INTERFACE_1);
1151 1150
1152 audio1 &= ~WM8400_AIF_WL_MASK; 1151 audio1 &= ~WM8400_AIF_WL_MASK;
1153 /* bit size */ 1152 /* bit size */
@@ -1165,19 +1164,19 @@ static int wm8400_hw_params(struct snd_pcm_substream *substream,
1165 break; 1164 break;
1166 } 1165 }
1167 1166
1168 wm8400_write(codec, WM8400_AUDIO_INTERFACE_1, audio1); 1167 snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1);
1169 return 0; 1168 return 0;
1170} 1169}
1171 1170
1172static int wm8400_mute(struct snd_soc_dai *dai, int mute) 1171static int wm8400_mute(struct snd_soc_dai *dai, int mute)
1173{ 1172{
1174 struct snd_soc_codec *codec = dai->codec; 1173 struct snd_soc_codec *codec = dai->codec;
1175 u16 val = wm8400_read(codec, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE; 1174 u16 val = snd_soc_read(codec, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE;
1176 1175
1177 if (mute) 1176 if (mute)
1178 wm8400_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE); 1177 snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
1179 else 1178 else
1180 wm8400_write(codec, WM8400_DAC_CTRL, val); 1179 snd_soc_write(codec, WM8400_DAC_CTRL, val);
1181 1180
1182 return 0; 1181 return 0;
1183} 1182}
@@ -1196,9 +1195,9 @@ static int wm8400_set_bias_level(struct snd_soc_codec *codec,
1196 1195
1197 case SND_SOC_BIAS_PREPARE: 1196 case SND_SOC_BIAS_PREPARE:
1198 /* VMID=2*50k */ 1197 /* VMID=2*50k */
1199 val = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1) & 1198 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) &
1200 ~WM8400_VMID_MODE_MASK; 1199 ~WM8400_VMID_MODE_MASK;
1201 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x2); 1200 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x2);
1202 break; 1201 break;
1203 1202
1204 case SND_SOC_BIAS_STANDBY: 1203 case SND_SOC_BIAS_STANDBY:
@@ -1212,74 +1211,74 @@ static int wm8400_set_bias_level(struct snd_soc_codec *codec,
1212 return ret; 1211 return ret;
1213 } 1212 }
1214 1213
1215 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, 1214 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1,
1216 WM8400_CODEC_ENA | WM8400_SYSCLK_ENA); 1215 WM8400_CODEC_ENA | WM8400_SYSCLK_ENA);
1217 1216
1218 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ 1217 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1219 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | 1218 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1220 WM8400_BUFDCOPEN | WM8400_POBCTRL); 1219 WM8400_BUFDCOPEN | WM8400_POBCTRL);
1221 1220
1222 msleep(50); 1221 msleep(50);
1223 1222
1224 /* Enable VREF & VMID at 2x50k */ 1223 /* Enable VREF & VMID at 2x50k */
1225 val = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1); 1224 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1226 val |= 0x2 | WM8400_VREF_ENA; 1225 val |= 0x2 | WM8400_VREF_ENA;
1227 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val); 1226 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1228 1227
1229 /* Enable BUFIOEN */ 1228 /* Enable BUFIOEN */
1230 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | 1229 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1231 WM8400_BUFDCOPEN | WM8400_POBCTRL | 1230 WM8400_BUFDCOPEN | WM8400_POBCTRL |
1232 WM8400_BUFIOEN); 1231 WM8400_BUFIOEN);
1233 1232
1234 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1233 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1235 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_BUFIOEN); 1234 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_BUFIOEN);
1236 } 1235 }
1237 1236
1238 /* VMID=2*300k */ 1237 /* VMID=2*300k */
1239 val = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1) & 1238 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) &
1240 ~WM8400_VMID_MODE_MASK; 1239 ~WM8400_VMID_MODE_MASK;
1241 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x4); 1240 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x4);
1242 break; 1241 break;
1243 1242
1244 case SND_SOC_BIAS_OFF: 1243 case SND_SOC_BIAS_OFF:
1245 /* Enable POBCTRL and SOFT_ST */ 1244 /* Enable POBCTRL and SOFT_ST */
1246 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | 1245 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1247 WM8400_POBCTRL | WM8400_BUFIOEN); 1246 WM8400_POBCTRL | WM8400_BUFIOEN);
1248 1247
1249 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ 1248 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1250 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | 1249 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1251 WM8400_BUFDCOPEN | WM8400_POBCTRL | 1250 WM8400_BUFDCOPEN | WM8400_POBCTRL |
1252 WM8400_BUFIOEN); 1251 WM8400_BUFIOEN);
1253 1252
1254 /* mute DAC */ 1253 /* mute DAC */
1255 val = wm8400_read(codec, WM8400_DAC_CTRL); 1254 val = snd_soc_read(codec, WM8400_DAC_CTRL);
1256 wm8400_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE); 1255 snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
1257 1256
1258 /* Enable any disabled outputs */ 1257 /* Enable any disabled outputs */
1259 val = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1); 1258 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1260 val |= WM8400_SPK_ENA | WM8400_OUT3_ENA | 1259 val |= WM8400_SPK_ENA | WM8400_OUT3_ENA |
1261 WM8400_OUT4_ENA | WM8400_LOUT_ENA | 1260 WM8400_OUT4_ENA | WM8400_LOUT_ENA |
1262 WM8400_ROUT_ENA; 1261 WM8400_ROUT_ENA;
1263 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val); 1262 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1264 1263
1265 /* Disable VMID */ 1264 /* Disable VMID */
1266 val &= ~WM8400_VMID_MODE_MASK; 1265 val &= ~WM8400_VMID_MODE_MASK;
1267 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val); 1266 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1268 1267
1269 msleep(300); 1268 msleep(300);
1270 1269
1271 /* Enable all output discharge bits */ 1270 /* Enable all output discharge bits */
1272 wm8400_write(codec, WM8400_ANTIPOP1, WM8400_DIS_LLINE | 1271 snd_soc_write(codec, WM8400_ANTIPOP1, WM8400_DIS_LLINE |
1273 WM8400_DIS_RLINE | WM8400_DIS_OUT3 | 1272 WM8400_DIS_RLINE | WM8400_DIS_OUT3 |
1274 WM8400_DIS_OUT4 | WM8400_DIS_LOUT | 1273 WM8400_DIS_OUT4 | WM8400_DIS_LOUT |
1275 WM8400_DIS_ROUT); 1274 WM8400_DIS_ROUT);
1276 1275
1277 /* Disable VREF */ 1276 /* Disable VREF */
1278 val &= ~WM8400_VREF_ENA; 1277 val &= ~WM8400_VREF_ENA;
1279 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val); 1278 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1280 1279
1281 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ 1280 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1282 wm8400_write(codec, WM8400_ANTIPOP2, 0x0); 1281 snd_soc_write(codec, WM8400_ANTIPOP2, 0x0);
1283 1282
1284 ret = regulator_bulk_disable(ARRAY_SIZE(power), 1283 ret = regulator_bulk_disable(ARRAY_SIZE(power),
1285 &power[0]); 1284 &power[0]);
@@ -1385,19 +1384,19 @@ static int wm8400_codec_probe(struct snd_soc_codec *codec)
1385 1384
1386 wm8400_codec_reset(codec); 1385 wm8400_codec_reset(codec);
1387 1386
1388 reg = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1); 1387 reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1389 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA); 1388 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA);
1390 1389
1391 /* Latch volume update bits */ 1390 /* Latch volume update bits */
1392 reg = wm8400_read(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME); 1391 reg = snd_soc_read(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME);
1393 wm8400_write(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME, 1392 snd_soc_write(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
1394 reg & WM8400_IPVU); 1393 reg & WM8400_IPVU);
1395 reg = wm8400_read(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME); 1394 reg = snd_soc_read(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME);
1396 wm8400_write(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, 1395 snd_soc_write(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
1397 reg & WM8400_IPVU); 1396 reg & WM8400_IPVU);
1398 1397
1399 wm8400_write(codec, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1398 snd_soc_write(codec, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1400 wm8400_write(codec, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); 1399 snd_soc_write(codec, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1401 1400
1402 if (!schedule_work(&priv->work)) { 1401 if (!schedule_work(&priv->work)) {
1403 ret = -EINVAL; 1402 ret = -EINVAL;
@@ -1414,8 +1413,8 @@ static int wm8400_codec_remove(struct snd_soc_codec *codec)
1414{ 1413{
1415 u16 reg; 1414 u16 reg;
1416 1415
1417 reg = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1); 1416 reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1418 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, 1417 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1,
1419 reg & (~WM8400_CODEC_ENA)); 1418 reg & (~WM8400_CODEC_ENA));
1420 1419
1421 regulator_bulk_free(ARRAY_SIZE(power), power); 1420 regulator_bulk_free(ARRAY_SIZE(power), power);
@@ -1428,7 +1427,7 @@ static struct snd_soc_codec_driver soc_codec_dev_wm8400 = {
1428 .remove = wm8400_codec_remove, 1427 .remove = wm8400_codec_remove,
1429 .suspend = wm8400_suspend, 1428 .suspend = wm8400_suspend,
1430 .resume = wm8400_resume, 1429 .resume = wm8400_resume,
1431 .read = wm8400_read, 1430 .read = snd_soc_read,
1432 .write = wm8400_write, 1431 .write = wm8400_write,
1433 .set_bias_level = wm8400_set_bias_level, 1432 .set_bias_level = wm8400_set_bias_level,
1434 1433
diff --git a/sound/soc/codecs/wm8510.c b/sound/soc/codecs/wm8510.c
index 9166126bd312..56a049555e2c 100644
--- a/sound/soc/codecs/wm8510.c
+++ b/sound/soc/codecs/wm8510.c
@@ -392,8 +392,7 @@ static int wm8510_pcm_hw_params(struct snd_pcm_substream *substream,
392 struct snd_pcm_hw_params *params, 392 struct snd_pcm_hw_params *params,
393 struct snd_soc_dai *dai) 393 struct snd_soc_dai *dai)
394{ 394{
395 struct snd_soc_pcm_runtime *rtd = substream->private_data; 395 struct snd_soc_codec *codec = dai->codec;
396 struct snd_soc_codec *codec = rtd->codec;
397 u16 iface = snd_soc_read(codec, WM8510_IFACE) & 0x19f; 396 u16 iface = snd_soc_read(codec, WM8510_IFACE) & 0x19f;
398 u16 adn = snd_soc_read(codec, WM8510_ADD) & 0x1f1; 397 u16 adn = snd_soc_read(codec, WM8510_ADD) & 0x1f1;
399 398
diff --git a/sound/soc/codecs/wm8523.c b/sound/soc/codecs/wm8523.c
index 7fea2c3bf7e7..1c3ffb290cdc 100644
--- a/sound/soc/codecs/wm8523.c
+++ b/sound/soc/codecs/wm8523.c
@@ -145,8 +145,7 @@ static int wm8523_hw_params(struct snd_pcm_substream *substream,
145 struct snd_pcm_hw_params *params, 145 struct snd_pcm_hw_params *params,
146 struct snd_soc_dai *dai) 146 struct snd_soc_dai *dai)
147{ 147{
148 struct snd_soc_pcm_runtime *rtd = substream->private_data; 148 struct snd_soc_codec *codec = dai->codec;
149 struct snd_soc_codec *codec = rtd->codec;
150 struct wm8523_priv *wm8523 = snd_soc_codec_get_drvdata(codec); 149 struct wm8523_priv *wm8523 = snd_soc_codec_get_drvdata(codec);
151 int i; 150 int i;
152 u16 aifctrl1 = snd_soc_read(codec, WM8523_AIF_CTRL1); 151 u16 aifctrl1 = snd_soc_read(codec, WM8523_AIF_CTRL1);
diff --git a/sound/soc/codecs/wm8728.c b/sound/soc/codecs/wm8728.c
index fc3d59e49084..1467f97dce21 100644
--- a/sound/soc/codecs/wm8728.c
+++ b/sound/soc/codecs/wm8728.c
@@ -88,8 +88,7 @@ static int wm8728_hw_params(struct snd_pcm_substream *substream,
88 struct snd_pcm_hw_params *params, 88 struct snd_pcm_hw_params *params,
89 struct snd_soc_dai *dai) 89 struct snd_soc_dai *dai)
90{ 90{
91 struct snd_soc_pcm_runtime *rtd = substream->private_data; 91 struct snd_soc_codec *codec = dai->codec;
92 struct snd_soc_codec *codec = rtd->codec;
93 u16 dac = snd_soc_read(codec, WM8728_DACCTL); 92 u16 dac = snd_soc_read(codec, WM8728_DACCTL);
94 93
95 dac &= ~0x18; 94 dac &= ~0x18;
diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c
index a32caa72bd7d..9d1b9b0271f1 100644
--- a/sound/soc/codecs/wm8731.c
+++ b/sound/soc/codecs/wm8731.c
@@ -635,16 +635,17 @@ static int __devinit wm8731_spi_probe(struct spi_device *spi)
635 struct wm8731_priv *wm8731; 635 struct wm8731_priv *wm8731;
636 int ret; 636 int ret;
637 637
638 wm8731 = kzalloc(sizeof(struct wm8731_priv), GFP_KERNEL); 638 wm8731 = devm_kzalloc(&spi->dev, sizeof(struct wm8731_priv),
639 GFP_KERNEL);
639 if (wm8731 == NULL) 640 if (wm8731 == NULL)
640 return -ENOMEM; 641 return -ENOMEM;
641 642
642 wm8731->regmap = regmap_init_spi(spi, &wm8731_regmap); 643 wm8731->regmap = devm_regmap_init_spi(spi, &wm8731_regmap);
643 if (IS_ERR(wm8731->regmap)) { 644 if (IS_ERR(wm8731->regmap)) {
644 ret = PTR_ERR(wm8731->regmap); 645 ret = PTR_ERR(wm8731->regmap);
645 dev_err(&spi->dev, "Failed to allocate register map: %d\n", 646 dev_err(&spi->dev, "Failed to allocate register map: %d\n",
646 ret); 647 ret);
647 goto err; 648 return ret;
648 } 649 }
649 650
650 spi_set_drvdata(spi, wm8731); 651 spi_set_drvdata(spi, wm8731);
@@ -653,25 +654,15 @@ static int __devinit wm8731_spi_probe(struct spi_device *spi)
653 &soc_codec_dev_wm8731, &wm8731_dai, 1); 654 &soc_codec_dev_wm8731, &wm8731_dai, 1);
654 if (ret != 0) { 655 if (ret != 0) {
655 dev_err(&spi->dev, "Failed to register CODEC: %d\n", ret); 656 dev_err(&spi->dev, "Failed to register CODEC: %d\n", ret);
656 goto err_regmap; 657 return ret;
657 } 658 }
658 659
659 return 0; 660 return 0;
660
661err_regmap:
662 regmap_exit(wm8731->regmap);
663err:
664 kfree(wm8731);
665 return ret;
666} 661}
667 662
668static int __devexit wm8731_spi_remove(struct spi_device *spi) 663static int __devexit wm8731_spi_remove(struct spi_device *spi)
669{ 664{
670 struct wm8731_priv *wm8731 = spi_get_drvdata(spi);
671
672 snd_soc_unregister_codec(&spi->dev); 665 snd_soc_unregister_codec(&spi->dev);
673 regmap_exit(wm8731->regmap);
674 kfree(wm8731);
675 return 0; 666 return 0;
676} 667}
677 668
@@ -693,16 +684,17 @@ static __devinit int wm8731_i2c_probe(struct i2c_client *i2c,
693 struct wm8731_priv *wm8731; 684 struct wm8731_priv *wm8731;
694 int ret; 685 int ret;
695 686
696 wm8731 = kzalloc(sizeof(struct wm8731_priv), GFP_KERNEL); 687 wm8731 = devm_kzalloc(&i2c->dev, sizeof(struct wm8731_priv),
688 GFP_KERNEL);
697 if (wm8731 == NULL) 689 if (wm8731 == NULL)
698 return -ENOMEM; 690 return -ENOMEM;
699 691
700 wm8731->regmap = regmap_init_i2c(i2c, &wm8731_regmap); 692 wm8731->regmap = devm_regmap_init_i2c(i2c, &wm8731_regmap);
701 if (IS_ERR(wm8731->regmap)) { 693 if (IS_ERR(wm8731->regmap)) {
702 ret = PTR_ERR(wm8731->regmap); 694 ret = PTR_ERR(wm8731->regmap);
703 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 695 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
704 ret); 696 ret);
705 goto err; 697 return ret;
706 } 698 }
707 699
708 i2c_set_clientdata(i2c, wm8731); 700 i2c_set_clientdata(i2c, wm8731);
@@ -711,24 +703,15 @@ static __devinit int wm8731_i2c_probe(struct i2c_client *i2c,
711 &soc_codec_dev_wm8731, &wm8731_dai, 1); 703 &soc_codec_dev_wm8731, &wm8731_dai, 1);
712 if (ret != 0) { 704 if (ret != 0) {
713 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret); 705 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
714 goto err_regmap; 706 return ret;
715 } 707 }
716 708
717 return 0; 709 return 0;
718
719err_regmap:
720 regmap_exit(wm8731->regmap);
721err:
722 kfree(wm8731);
723 return ret;
724} 710}
725 711
726static __devexit int wm8731_i2c_remove(struct i2c_client *client) 712static __devexit int wm8731_i2c_remove(struct i2c_client *client)
727{ 713{
728 struct wm8731_priv *wm8731 = i2c_get_clientdata(client);
729 snd_soc_unregister_codec(&client->dev); 714 snd_soc_unregister_codec(&client->dev);
730 regmap_exit(wm8731->regmap);
731 kfree(wm8731);
732 return 0; 715 return 0;
733} 716}
734 717
diff --git a/sound/soc/codecs/wm8737.c b/sound/soc/codecs/wm8737.c
index 4fe9d191e277..d0520124616d 100644
--- a/sound/soc/codecs/wm8737.c
+++ b/sound/soc/codecs/wm8737.c
@@ -329,8 +329,7 @@ static int wm8737_hw_params(struct snd_pcm_substream *substream,
329 struct snd_pcm_hw_params *params, 329 struct snd_pcm_hw_params *params,
330 struct snd_soc_dai *dai) 330 struct snd_soc_dai *dai)
331{ 331{
332 struct snd_soc_pcm_runtime *rtd = substream->private_data; 332 struct snd_soc_codec *codec = dai->codec;
333 struct snd_soc_codec *codec = rtd->codec;
334 struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec); 333 struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec);
335 int i; 334 int i;
336 u16 clocking = 0; 335 u16 clocking = 0;
diff --git a/sound/soc/codecs/wm8741.c b/sound/soc/codecs/wm8741.c
index 3941f50bf187..6e849cb04243 100644
--- a/sound/soc/codecs/wm8741.c
+++ b/sound/soc/codecs/wm8741.c
@@ -203,8 +203,7 @@ static int wm8741_hw_params(struct snd_pcm_substream *substream,
203 struct snd_pcm_hw_params *params, 203 struct snd_pcm_hw_params *params,
204 struct snd_soc_dai *dai) 204 struct snd_soc_dai *dai)
205{ 205{
206 struct snd_soc_pcm_runtime *rtd = substream->private_data; 206 struct snd_soc_codec *codec = dai->codec;
207 struct snd_soc_codec *codec = rtd->codec;
208 struct wm8741_priv *wm8741 = snd_soc_codec_get_drvdata(codec); 207 struct wm8741_priv *wm8741 = snd_soc_codec_get_drvdata(codec);
209 u16 iface = snd_soc_read(codec, WM8741_FORMAT_CONTROL) & 0x1FC; 208 u16 iface = snd_soc_read(codec, WM8741_FORMAT_CONTROL) & 0x1FC;
210 int i; 209 int i;
diff --git a/sound/soc/codecs/wm8750.c b/sound/soc/codecs/wm8750.c
index e4c50ce7d9c0..89151ca5e776 100644
--- a/sound/soc/codecs/wm8750.c
+++ b/sound/soc/codecs/wm8750.c
@@ -547,8 +547,7 @@ static int wm8750_pcm_hw_params(struct snd_pcm_substream *substream,
547 struct snd_pcm_hw_params *params, 547 struct snd_pcm_hw_params *params,
548 struct snd_soc_dai *dai) 548 struct snd_soc_dai *dai)
549{ 549{
550 struct snd_soc_pcm_runtime *rtd = substream->private_data; 550 struct snd_soc_codec *codec = dai->codec;
551 struct snd_soc_codec *codec = rtd->codec;
552 struct wm8750_priv *wm8750 = snd_soc_codec_get_drvdata(codec); 551 struct wm8750_priv *wm8750 = snd_soc_codec_get_drvdata(codec);
553 u16 iface = snd_soc_read(codec, WM8750_IFACE) & 0x1f3; 552 u16 iface = snd_soc_read(codec, WM8750_IFACE) & 0x1f3;
554 u16 srate = snd_soc_read(codec, WM8750_SRATE) & 0x1c0; 553 u16 srate = snd_soc_read(codec, WM8750_SRATE) & 0x1c0;
diff --git a/sound/soc/codecs/wm8753.c b/sound/soc/codecs/wm8753.c
index e27e7b62b365..a26482cd7654 100644
--- a/sound/soc/codecs/wm8753.c
+++ b/sound/soc/codecs/wm8753.c
@@ -931,8 +931,7 @@ static int wm8753_pcm_hw_params(struct snd_pcm_substream *substream,
931 struct snd_pcm_hw_params *params, 931 struct snd_pcm_hw_params *params,
932 struct snd_soc_dai *dai) 932 struct snd_soc_dai *dai)
933{ 933{
934 struct snd_soc_pcm_runtime *rtd = substream->private_data; 934 struct snd_soc_codec *codec = dai->codec;
935 struct snd_soc_codec *codec = rtd->codec;
936 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec); 935 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
937 u16 voice = snd_soc_read(codec, WM8753_PCM) & 0x01f3; 936 u16 voice = snd_soc_read(codec, WM8753_PCM) & 0x01f3;
938 u16 srate = snd_soc_read(codec, WM8753_SRATE1) & 0x017f; 937 u16 srate = snd_soc_read(codec, WM8753_SRATE1) & 0x017f;
@@ -1161,8 +1160,7 @@ static int wm8753_i2s_hw_params(struct snd_pcm_substream *substream,
1161 struct snd_pcm_hw_params *params, 1160 struct snd_pcm_hw_params *params,
1162 struct snd_soc_dai *dai) 1161 struct snd_soc_dai *dai)
1163{ 1162{
1164 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1163 struct snd_soc_codec *codec = dai->codec;
1165 struct snd_soc_codec *codec = rtd->codec;
1166 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec); 1164 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1167 u16 srate = snd_soc_read(codec, WM8753_SRATE1) & 0x01c0; 1165 u16 srate = snd_soc_read(codec, WM8753_SRATE1) & 0x01c0;
1168 u16 hifi = snd_soc_read(codec, WM8753_HIFI) & 0x01f3; 1166 u16 hifi = snd_soc_read(codec, WM8753_HIFI) & 0x01f3;
diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c
index f18c554efc98..077c9628c70d 100644
--- a/sound/soc/codecs/wm8900.c
+++ b/sound/soc/codecs/wm8900.c
@@ -610,8 +610,7 @@ static int wm8900_hw_params(struct snd_pcm_substream *substream,
610 struct snd_pcm_hw_params *params, 610 struct snd_pcm_hw_params *params,
611 struct snd_soc_dai *dai) 611 struct snd_soc_dai *dai)
612{ 612{
613 struct snd_soc_pcm_runtime *rtd = substream->private_data; 613 struct snd_soc_codec *codec = dai->codec;
614 struct snd_soc_codec *codec = rtd->codec;
615 u16 reg; 614 u16 reg;
616 615
617 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60; 616 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c
index c91fb2f99c13..86b8a2926591 100644
--- a/sound/soc/codecs/wm8903.c
+++ b/sound/soc/codecs/wm8903.c
@@ -1432,8 +1432,7 @@ static int wm8903_hw_params(struct snd_pcm_substream *substream,
1432 struct snd_pcm_hw_params *params, 1432 struct snd_pcm_hw_params *params,
1433 struct snd_soc_dai *dai) 1433 struct snd_soc_dai *dai)
1434{ 1434{
1435 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1435 struct snd_soc_codec *codec = dai->codec;
1436 struct snd_soc_codec *codec =rtd->codec;
1437 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); 1436 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1438 int fs = params_rate(params); 1437 int fs = params_rate(params);
1439 int bclk; 1438 int bclk;
diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c
index d2883affea3b..481a3d9cfe48 100644
--- a/sound/soc/codecs/wm8940.c
+++ b/sound/soc/codecs/wm8940.c
@@ -371,8 +371,7 @@ static int wm8940_i2s_hw_params(struct snd_pcm_substream *substream,
371 struct snd_pcm_hw_params *params, 371 struct snd_pcm_hw_params *params,
372 struct snd_soc_dai *dai) 372 struct snd_soc_dai *dai)
373{ 373{
374 struct snd_soc_pcm_runtime *rtd = substream->private_data; 374 struct snd_soc_codec *codec = dai->codec;
375 struct snd_soc_codec *codec = rtd->codec;
376 u16 iface = snd_soc_read(codec, WM8940_IFACE) & 0xFD9F; 375 u16 iface = snd_soc_read(codec, WM8940_IFACE) & 0xFD9F;
377 u16 addcntrl = snd_soc_read(codec, WM8940_ADDCNTRL) & 0xFFF1; 376 u16 addcntrl = snd_soc_read(codec, WM8940_ADDCNTRL) & 0xFFF1;
378 u16 companding = snd_soc_read(codec, 377 u16 companding = snd_soc_read(codec,
diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c
index 840d72086d04..8bc659d8dd2e 100644
--- a/sound/soc/codecs/wm8960.c
+++ b/sound/soc/codecs/wm8960.c
@@ -505,8 +505,7 @@ static int wm8960_hw_params(struct snd_pcm_substream *substream,
505 struct snd_pcm_hw_params *params, 505 struct snd_pcm_hw_params *params,
506 struct snd_soc_dai *dai) 506 struct snd_soc_dai *dai)
507{ 507{
508 struct snd_soc_pcm_runtime *rtd = substream->private_data; 508 struct snd_soc_codec *codec = dai->codec;
509 struct snd_soc_codec *codec = rtd->codec;
510 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); 509 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
511 u16 iface = snd_soc_read(codec, WM8960_IFACE1) & 0xfff3; 510 u16 iface = snd_soc_read(codec, WM8960_IFACE1) & 0xfff3;
512 int i; 511 int i;
diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c
index 15d467ff91b4..0cfce9999c89 100644
--- a/sound/soc/codecs/wm8962.c
+++ b/sound/soc/codecs/wm8962.c
@@ -1478,7 +1478,8 @@ static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1478 1478
1479static int wm8962_dsp2_write_config(struct snd_soc_codec *codec) 1479static int wm8962_dsp2_write_config(struct snd_soc_codec *codec)
1480{ 1480{
1481 return 0; 1481 return regcache_sync_region(codec->control_data,
1482 WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER);
1482} 1483}
1483 1484
1484static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val) 1485static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val)
@@ -1755,10 +1756,22 @@ SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
1755SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23, 1756SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
1756 WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv), 1757 WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
1757 1758
1759SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0),
1760SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA),
1761
1762SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0),
1763SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA),
1764
1765SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0),
1766SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA),
1767
1758WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT), 1768WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
1769SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148),
1759WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT), 1770WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
1760WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT), 1771WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
1772SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1),
1761WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT), 1773WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
1774SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30),
1762}; 1775};
1763 1776
1764static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = { 1777static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
@@ -2519,8 +2532,7 @@ static int wm8962_hw_params(struct snd_pcm_substream *substream,
2519 struct snd_pcm_hw_params *params, 2532 struct snd_pcm_hw_params *params,
2520 struct snd_soc_dai *dai) 2533 struct snd_soc_dai *dai)
2521{ 2534{
2522 struct snd_soc_pcm_runtime *rtd = substream->private_data; 2535 struct snd_soc_codec *codec = dai->codec;
2523 struct snd_soc_codec *codec = rtd->codec;
2524 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 2536 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2525 int i; 2537 int i;
2526 int aif0 = 0; 2538 int aif0 = 0;
diff --git a/sound/soc/codecs/wm8971.c b/sound/soc/codecs/wm8971.c
index 28fe59e3ce01..eef783f6b6d6 100644
--- a/sound/soc/codecs/wm8971.c
+++ b/sound/soc/codecs/wm8971.c
@@ -478,8 +478,7 @@ static int wm8971_pcm_hw_params(struct snd_pcm_substream *substream,
478 struct snd_pcm_hw_params *params, 478 struct snd_pcm_hw_params *params,
479 struct snd_soc_dai *dai) 479 struct snd_soc_dai *dai)
480{ 480{
481 struct snd_soc_pcm_runtime *rtd = substream->private_data; 481 struct snd_soc_codec *codec = dai->codec;
482 struct snd_soc_codec *codec = rtd->codec;
483 struct wm8971_priv *wm8971 = snd_soc_codec_get_drvdata(codec); 482 struct wm8971_priv *wm8971 = snd_soc_codec_get_drvdata(codec);
484 u16 iface = snd_soc_read(codec, WM8971_IFACE) & 0x1f3; 483 u16 iface = snd_soc_read(codec, WM8971_IFACE) & 0x1f3;
485 u16 srate = snd_soc_read(codec, WM8971_SRATE) & 0x1c0; 484 u16 srate = snd_soc_read(codec, WM8971_SRATE) & 0x1c0;
diff --git a/sound/soc/codecs/wm8978.c b/sound/soc/codecs/wm8978.c
index 72d5fdcd3cc2..a5be3adecf75 100644
--- a/sound/soc/codecs/wm8978.c
+++ b/sound/soc/codecs/wm8978.c
@@ -723,8 +723,7 @@ static int wm8978_hw_params(struct snd_pcm_substream *substream,
723 struct snd_pcm_hw_params *params, 723 struct snd_pcm_hw_params *params,
724 struct snd_soc_dai *dai) 724 struct snd_soc_dai *dai)
725{ 725{
726 struct snd_soc_pcm_runtime *rtd = substream->private_data; 726 struct snd_soc_codec *codec = dai->codec;
727 struct snd_soc_codec *codec = rtd->codec;
728 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec); 727 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
729 /* Word length mask = 0x60 */ 728 /* Word length mask = 0x60 */
730 u16 iface_ctl = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x60; 729 u16 iface_ctl = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x60;
diff --git a/sound/soc/codecs/wm8988.c b/sound/soc/codecs/wm8988.c
index 6cdf6a2bc283..1d4c5cf47b06 100644
--- a/sound/soc/codecs/wm8988.c
+++ b/sound/soc/codecs/wm8988.c
@@ -668,8 +668,7 @@ static int wm8988_pcm_hw_params(struct snd_pcm_substream *substream,
668 struct snd_pcm_hw_params *params, 668 struct snd_pcm_hw_params *params,
669 struct snd_soc_dai *dai) 669 struct snd_soc_dai *dai)
670{ 670{
671 struct snd_soc_pcm_runtime *rtd = substream->private_data; 671 struct snd_soc_codec *codec = dai->codec;
672 struct snd_soc_codec *codec = rtd->codec;
673 struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec); 672 struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
674 u16 iface = snd_soc_read(codec, WM8988_IFACE) & 0x1f3; 673 u16 iface = snd_soc_read(codec, WM8988_IFACE) & 0x1f3;
675 u16 srate = snd_soc_read(codec, WM8988_SRATE) & 0x180; 674 u16 srate = snd_soc_read(codec, WM8988_SRATE) & 0x180;
diff --git a/sound/soc/codecs/wm8990.c b/sound/soc/codecs/wm8990.c
index 9d242351e6e8..db63c97ddf51 100644
--- a/sound/soc/codecs/wm8990.c
+++ b/sound/soc/codecs/wm8990.c
@@ -1112,8 +1112,7 @@ static int wm8990_hw_params(struct snd_pcm_substream *substream,
1112 struct snd_pcm_hw_params *params, 1112 struct snd_pcm_hw_params *params,
1113 struct snd_soc_dai *dai) 1113 struct snd_soc_dai *dai)
1114{ 1114{
1115 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1115 struct snd_soc_codec *codec = dai->codec;
1116 struct snd_soc_codec *codec = rtd->codec;
1117 u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1); 1116 u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
1118 1117
1119 audio1 &= ~WM8990_AIF_WL_MASK; 1118 audio1 &= ~WM8990_AIF_WL_MASK;
diff --git a/sound/soc/codecs/wm8993.c b/sound/soc/codecs/wm8993.c
index d256a9340644..36acfccab999 100644
--- a/sound/soc/codecs/wm8993.c
+++ b/sound/soc/codecs/wm8993.c
@@ -218,7 +218,6 @@ struct wm8993_priv {
218 unsigned int sysclk_rate; 218 unsigned int sysclk_rate;
219 unsigned int fs; 219 unsigned int fs;
220 unsigned int bclk; 220 unsigned int bclk;
221 int class_w_users;
222 unsigned int fll_fref; 221 unsigned int fll_fref;
223 unsigned int fll_fout; 222 unsigned int fll_fout;
224 int fll_src; 223 int fll_src;
@@ -824,84 +823,6 @@ static int clk_sys_event(struct snd_soc_dapm_widget *w,
824 return 0; 823 return 0;
825} 824}
826 825
827/*
828 * When used with DAC outputs only the WM8993 charge pump supports
829 * operation in class W mode, providing very low power consumption
830 * when used with digital sources. Enable and disable this mode
831 * automatically depending on the mixer configuration.
832 *
833 * Currently the only supported paths are the direct DAC->headphone
834 * paths (which provide minimum power consumption anyway).
835 */
836static int class_w_put(struct snd_kcontrol *kcontrol,
837 struct snd_ctl_elem_value *ucontrol)
838{
839 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
840 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
841 struct snd_soc_codec *codec = widget->codec;
842 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
843 int ret;
844
845 /* Turn it off if we're using the main output mixer */
846 if (ucontrol->value.integer.value[0] == 0) {
847 if (wm8993->class_w_users == 0) {
848 dev_dbg(codec->dev, "Disabling Class W\n");
849 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
850 WM8993_CP_DYN_FREQ |
851 WM8993_CP_DYN_V,
852 0);
853 }
854 wm8993->class_w_users++;
855 wm8993->hubs_data.class_w = true;
856 }
857
858 /* Implement the change */
859 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
860
861 /* Enable it if we're using the direct DAC path */
862 if (ucontrol->value.integer.value[0] == 1) {
863 if (wm8993->class_w_users == 1) {
864 dev_dbg(codec->dev, "Enabling Class W\n");
865 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
866 WM8993_CP_DYN_FREQ |
867 WM8993_CP_DYN_V,
868 WM8993_CP_DYN_FREQ |
869 WM8993_CP_DYN_V);
870 }
871 wm8993->class_w_users--;
872 wm8993->hubs_data.class_w = false;
873 }
874
875 dev_dbg(codec->dev, "Indirect DAC use count now %d\n",
876 wm8993->class_w_users);
877
878 return ret;
879}
880
881#define SOC_DAPM_ENUM_W(xname, xenum) \
882{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
883 .info = snd_soc_info_enum_double, \
884 .get = snd_soc_dapm_get_enum_double, \
885 .put = class_w_put, \
886 .private_value = (unsigned long)&xenum }
887
888static const char *hp_mux_text[] = {
889 "Mixer",
890 "DAC",
891};
892
893static const struct soc_enum hpl_enum =
894 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text);
895
896static const struct snd_kcontrol_new hpl_mux =
897 SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum);
898
899static const struct soc_enum hpr_enum =
900 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text);
901
902static const struct snd_kcontrol_new hpr_mux =
903 SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum);
904
905static const struct snd_kcontrol_new left_speaker_mixer[] = { 826static const struct snd_kcontrol_new left_speaker_mixer[] = {
906SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0), 827SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
907SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0), 828SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
@@ -988,8 +909,8 @@ SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux),
988SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0), 909SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0),
989SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0), 910SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0),
990 911
991SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 912SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
992SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 913SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
993 914
994SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0, 915SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
995 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 916 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
@@ -1579,9 +1500,6 @@ static int wm8993_probe(struct snd_soc_codec *codec)
1579 return ret; 1500 return ret;
1580 } 1501 }
1581 1502
1582 /* By default we're using the output mixers */
1583 wm8993->class_w_users = 2;
1584
1585 /* Latch volume update bits and default ZC on */ 1503 /* Latch volume update bits and default ZC on */
1586 snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1504 snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
1587 WM8993_DAC_VU, WM8993_DAC_VU); 1505 WM8993_DAC_VU, WM8993_DAC_VU);
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index 2de12ebe43b5..993639d694ce 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -70,8 +70,8 @@ static const struct wm8958_micd_rate micdet_rates[] = {
70static const struct wm8958_micd_rate jackdet_rates[] = { 70static const struct wm8958_micd_rate jackdet_rates[] = {
71 { 32768, true, 0, 1 }, 71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 }, 72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 }, 73 { 44100 * 256, true, 10, 10 },
74 { 44100 * 256, false, 7, 10 }, 74 { 44100 * 256, false, 7, 8 },
75}; 75};
76 76
77static void wm8958_micd_set_rate(struct snd_soc_codec *codec) 77static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
@@ -82,7 +82,8 @@ static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
82 const struct wm8958_micd_rate *rates; 82 const struct wm8958_micd_rate *rates;
83 int num_rates; 83 int num_rates;
84 84
85 if (wm8994->jack_cb != wm8958_default_micdet) 85 if (!(wm8994->pdata && wm8994->pdata->micd_rates) &&
86 wm8994->jack_cb != wm8958_default_micdet)
86 return; 87 return;
87 88
88 idle = !wm8994->jack_mic; 89 idle = !wm8994->jack_mic;
@@ -118,6 +119,10 @@ static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
118 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT 119 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates[best].rate << WM8958_MICD_RATE_SHIFT; 120 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
120 121
122 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
123 rates[best].start, rates[best].rate, sysclk,
124 idle ? "idle" : "active");
125
121 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, 126 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
122 WM8958_MICD_BIAS_STARTTIME_MASK | 127 WM8958_MICD_BIAS_STARTTIME_MASK |
123 WM8958_MICD_RATE_MASK, val); 128 WM8958_MICD_RATE_MASK, val);
@@ -398,7 +403,7 @@ static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
398 wm8994->dac_rates[iface]); 403 wm8994->dac_rates[iface]);
399 404
400 /* The EQ will be disabled while reconfiguring it, remember the 405 /* The EQ will be disabled while reconfiguring it, remember the
401 * current configuration. 406 * current configuration.
402 */ 407 */
403 save = snd_soc_read(codec, base); 408 save = snd_soc_read(codec, base);
404 save &= WM8994_AIF1DAC1_EQ_ENA; 409 save &= WM8994_AIF1DAC1_EQ_ENA;
@@ -689,6 +694,9 @@ static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
689 if (!wm8994->jackdet || !wm8994->jack_cb) 694 if (!wm8994->jackdet || !wm8994->jack_cb)
690 return; 695 return;
691 696
697 if (!wm8994->jackdet || !wm8994->jack_cb)
698 return;
699
692 if (wm8994->active_refcount) 700 if (wm8994->active_refcount)
693 mode = WM1811_JACKDET_MODE_AUDIO; 701 mode = WM1811_JACKDET_MODE_AUDIO;
694 702
@@ -784,7 +792,7 @@ static void vmid_reference(struct snd_soc_codec *codec)
784 792
785 switch (wm8994->vmid_mode) { 793 switch (wm8994->vmid_mode) {
786 default: 794 default:
787 WARN_ON(0 == "Invalid VMID mode"); 795 WARN_ON(NULL == "Invalid VMID mode");
788 case WM8994_VMID_NORMAL: 796 case WM8994_VMID_NORMAL:
789 /* Startup bias, VMID ramp & buffer */ 797 /* Startup bias, VMID ramp & buffer */
790 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 798 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
@@ -937,27 +945,12 @@ static int vmid_event(struct snd_soc_dapm_widget *w,
937 return 0; 945 return 0;
938} 946}
939 947
940static void wm8994_update_class_w(struct snd_soc_codec *codec) 948static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
941{ 949{
942 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
943 int enable = 1;
944 int source = 0; /* GCC flow analysis can't track enable */ 950 int source = 0; /* GCC flow analysis can't track enable */
945 int reg, reg_r; 951 int reg, reg_r;
946 952
947 /* Only support direct DAC->headphone paths */ 953 /* We also need the same AIF source for L/R and only one path */
948 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
949 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
950 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
951 enable = 0;
952 }
953
954 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
955 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
956 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
957 enable = 0;
958 }
959
960 /* We also need the same setting for L/R and only one path */
961 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING); 954 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
962 switch (reg) { 955 switch (reg) {
963 case WM8994_AIF2DACL_TO_DAC1L: 956 case WM8994_AIF2DACL_TO_DAC1L:
@@ -974,30 +967,20 @@ static void wm8994_update_class_w(struct snd_soc_codec *codec)
974 break; 967 break;
975 default: 968 default:
976 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg); 969 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
977 enable = 0; 970 return false;
978 break;
979 } 971 }
980 972
981 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING); 973 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
982 if (reg_r != reg) { 974 if (reg_r != reg) {
983 dev_vdbg(codec->dev, "Left and right DAC mixers different\n"); 975 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
984 enable = 0; 976 return false;
985 } 977 }
986 978
987 if (enable) { 979 /* Set the source up */
988 dev_dbg(codec->dev, "Class W enabled\n"); 980 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
989 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 981 WM8994_CP_DYN_SRC_SEL_MASK, source);
990 WM8994_CP_DYN_PWR | 982
991 WM8994_CP_DYN_SRC_SEL_MASK, 983 return true;
992 source | WM8994_CP_DYN_PWR);
993 wm8994->hubs.class_w = true;
994
995 } else {
996 dev_dbg(codec->dev, "Class W disabled\n");
997 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
998 WM8994_CP_DYN_PWR, 0);
999 wm8994->hubs.class_w = false;
1000 }
1001} 984}
1002 985
1003static int aif1clk_ev(struct snd_soc_dapm_widget *w, 986static int aif1clk_ev(struct snd_soc_dapm_widget *w,
@@ -1280,45 +1263,6 @@ static int dac_ev(struct snd_soc_dapm_widget *w,
1280 return 0; 1263 return 0;
1281} 1264}
1282 1265
1283static const char *hp_mux_text[] = {
1284 "Mixer",
1285 "DAC",
1286};
1287
1288#define WM8994_HP_ENUM(xname, xenum) \
1289{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1290 .info = snd_soc_info_enum_double, \
1291 .get = snd_soc_dapm_get_enum_double, \
1292 .put = wm8994_put_hp_enum, \
1293 .private_value = (unsigned long)&xenum }
1294
1295static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1296 struct snd_ctl_elem_value *ucontrol)
1297{
1298 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1299 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1300 struct snd_soc_codec *codec = w->codec;
1301 int ret;
1302
1303 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1304
1305 wm8994_update_class_w(codec);
1306
1307 return ret;
1308}
1309
1310static const struct soc_enum hpl_enum =
1311 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1312
1313static const struct snd_kcontrol_new hpl_mux =
1314 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1315
1316static const struct soc_enum hpr_enum =
1317 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1318
1319static const struct snd_kcontrol_new hpr_mux =
1320 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1321
1322static const char *adc_mux_text[] = { 1266static const char *adc_mux_text[] = {
1323 "ADC", 1267 "ADC",
1324 "DMIC", 1268 "DMIC",
@@ -1430,7 +1374,7 @@ static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1430 1374
1431 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 1375 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1432 1376
1433 wm8994_update_class_w(codec); 1377 wm_hubs_update_class_w(codec);
1434 1378
1435 return ret; 1379 return ret;
1436} 1380}
@@ -1524,7 +1468,7 @@ static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1524 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum); 1468 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1525 1469
1526static const char *mono_pcm_out_text[] = { 1470static const char *mono_pcm_out_text[] = {
1527 "None", "AIF2ADCL", "AIF2ADCR", 1471 "None", "AIF2ADCL", "AIF2ADCR",
1528}; 1472};
1529 1473
1530static const struct soc_enum mono_pcm_out_enum = 1474static const struct soc_enum mono_pcm_out_enum =
@@ -1573,9 +1517,9 @@ SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1573SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1517SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1574 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer), 1518 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1575 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1519 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1576SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux, 1520SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1577 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1521 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1578SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux, 1522SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1579 late_enable_ev, SND_SOC_DAPM_PRE_PMU), 1523 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1580 1524
1581SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev) 1525SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
@@ -1591,8 +1535,8 @@ SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1591 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), 1535 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1592SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, 1536SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1593 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), 1537 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1594SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), 1538SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1595SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), 1539SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1596}; 1540};
1597 1541
1598static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = { 1542static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
@@ -1732,6 +1676,7 @@ SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1732}; 1676};
1733 1677
1734static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = { 1678static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1679SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1735SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux), 1680SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1736SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux), 1681SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1737SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux), 1682SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
@@ -1972,6 +1917,9 @@ static const struct snd_soc_dapm_route wm8958_intercon[] = {
1972 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" }, 1917 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1973 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" }, 1918 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1974 1919
1920 { "AIF3DACDAT", NULL, "AIF3" },
1921 { "AIF3ADCDAT", NULL, "AIF3" },
1922
1975 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" }, 1923 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1976 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" }, 1924 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1977 1925
@@ -2068,24 +2016,20 @@ static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2068 struct wm8994 *control = wm8994->wm8994; 2016 struct wm8994 *control = wm8994->wm8994;
2069 int reg_offset, ret; 2017 int reg_offset, ret;
2070 struct fll_div fll; 2018 struct fll_div fll;
2071 u16 reg, aif1, aif2; 2019 u16 reg, clk1, aif_reg, aif_src;
2072 unsigned long timeout; 2020 unsigned long timeout;
2073 bool was_enabled; 2021 bool was_enabled;
2074 2022
2075 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
2076 & WM8994_AIF1CLK_ENA;
2077
2078 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
2079 & WM8994_AIF2CLK_ENA;
2080
2081 switch (id) { 2023 switch (id) {
2082 case WM8994_FLL1: 2024 case WM8994_FLL1:
2083 reg_offset = 0; 2025 reg_offset = 0;
2084 id = 0; 2026 id = 0;
2027 aif_src = 0x10;
2085 break; 2028 break;
2086 case WM8994_FLL2: 2029 case WM8994_FLL2:
2087 reg_offset = 0x20; 2030 reg_offset = 0x20;
2088 id = 1; 2031 id = 1;
2032 aif_src = 0x18;
2089 break; 2033 break;
2090 default: 2034 default:
2091 return -EINVAL; 2035 return -EINVAL;
@@ -2127,16 +2071,33 @@ static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2127 if (ret < 0) 2071 if (ret < 0)
2128 return ret; 2072 return ret;
2129 2073
2130 /* Gate the AIF clocks while we reclock */ 2074 /* Make sure that we're not providing SYSCLK right now */
2131 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, 2075 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2132 WM8994_AIF1CLK_ENA, 0); 2076 if (clk1 & WM8994_SYSCLK_SRC)
2133 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, 2077 aif_reg = WM8994_AIF2_CLOCKING_1;
2134 WM8994_AIF2CLK_ENA, 0); 2078 else
2079 aif_reg = WM8994_AIF1_CLOCKING_1;
2080 reg = snd_soc_read(codec, aif_reg);
2081
2082 if ((reg & WM8994_AIF1CLK_ENA) &&
2083 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2084 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2085 id + 1);
2086 return -EBUSY;
2087 }
2135 2088
2136 /* We always need to disable the FLL while reconfiguring */ 2089 /* We always need to disable the FLL while reconfiguring */
2137 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, 2090 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2138 WM8994_FLL1_ENA, 0); 2091 WM8994_FLL1_ENA, 0);
2139 2092
2093 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2094 freq_in == freq_out && freq_out) {
2095 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2096 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2097 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2098 goto out;
2099 }
2100
2140 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) | 2101 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2141 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT); 2102 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2142 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset, 2103 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
@@ -2151,6 +2112,7 @@ static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2151 fll.n << WM8994_FLL1_N_SHIFT); 2112 fll.n << WM8994_FLL1_N_SHIFT);
2152 2113
2153 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, 2114 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2115 WM8958_FLL1_BYP |
2154 WM8994_FLL1_REFCLK_DIV_MASK | 2116 WM8994_FLL1_REFCLK_DIV_MASK |
2155 WM8994_FLL1_REFCLK_SRC_MASK, 2117 WM8994_FLL1_REFCLK_SRC_MASK,
2156 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) | 2118 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
@@ -2213,16 +2175,11 @@ static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2213 } 2175 }
2214 } 2176 }
2215 2177
2178out:
2216 wm8994->fll[id].in = freq_in; 2179 wm8994->fll[id].in = freq_in;
2217 wm8994->fll[id].out = freq_out; 2180 wm8994->fll[id].out = freq_out;
2218 wm8994->fll[id].src = src; 2181 wm8994->fll[id].src = src;
2219 2182
2220 /* Enable any gated AIF clocks */
2221 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2222 WM8994_AIF1CLK_ENA, aif1);
2223 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2224 WM8994_AIF2CLK_ENA, aif2);
2225
2226 configure_clock(codec); 2183 configure_clock(codec);
2227 2184
2228 return 0; 2185 return 0;
@@ -2290,7 +2247,7 @@ static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2290 2247
2291 case WM8994_SYSCLK_OPCLK: 2248 case WM8994_SYSCLK_OPCLK:
2292 /* Special case - a division (times 10) is given and 2249 /* Special case - a division (times 10) is given and
2293 * no effect on main clocking. 2250 * no effect on main clocking.
2294 */ 2251 */
2295 if (freq) { 2252 if (freq) {
2296 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) 2253 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
@@ -2792,33 +2749,6 @@ static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2792 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2749 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2793} 2750}
2794 2751
2795static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2796 struct snd_soc_dai *dai)
2797{
2798 struct snd_soc_codec *codec = dai->codec;
2799 int rate_reg = 0;
2800
2801 switch (dai->id) {
2802 case 1:
2803 rate_reg = WM8994_AIF1_RATE;
2804 break;
2805 case 2:
2806 rate_reg = WM8994_AIF2_RATE;
2807 break;
2808 default:
2809 break;
2810 }
2811
2812 /* If the DAI is idle then configure the divider tree for the
2813 * lowest output rate to save a little power if the clock is
2814 * still active (eg, because it is system clock).
2815 */
2816 if (rate_reg && !dai->playback_active && !dai->capture_active)
2817 snd_soc_update_bits(codec, rate_reg,
2818 WM8994_AIF1_SR_MASK |
2819 WM8994_AIF1CLK_RATE_MASK, 0x9);
2820}
2821
2822static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) 2752static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2823{ 2753{
2824 struct snd_soc_codec *codec = codec_dai->codec; 2754 struct snd_soc_codec *codec = codec_dai->codec;
@@ -2860,10 +2790,6 @@ static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2860 reg = WM8994_AIF2_MASTER_SLAVE; 2790 reg = WM8994_AIF2_MASTER_SLAVE;
2861 mask = WM8994_AIF2_TRI; 2791 mask = WM8994_AIF2_TRI;
2862 break; 2792 break;
2863 case 3:
2864 reg = WM8994_POWER_MANAGEMENT_6;
2865 mask = WM8994_AIF3_TRI;
2866 break;
2867 default: 2793 default:
2868 return -EINVAL; 2794 return -EINVAL;
2869 } 2795 }
@@ -2900,7 +2826,6 @@ static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2900 .set_sysclk = wm8994_set_dai_sysclk, 2826 .set_sysclk = wm8994_set_dai_sysclk,
2901 .set_fmt = wm8994_set_dai_fmt, 2827 .set_fmt = wm8994_set_dai_fmt,
2902 .hw_params = wm8994_hw_params, 2828 .hw_params = wm8994_hw_params,
2903 .shutdown = wm8994_aif_shutdown,
2904 .digital_mute = wm8994_aif_mute, 2829 .digital_mute = wm8994_aif_mute,
2905 .set_pll = wm8994_set_fll, 2830 .set_pll = wm8994_set_fll,
2906 .set_tristate = wm8994_set_tristate, 2831 .set_tristate = wm8994_set_tristate,
@@ -2910,7 +2835,6 @@ static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2910 .set_sysclk = wm8994_set_dai_sysclk, 2835 .set_sysclk = wm8994_set_dai_sysclk,
2911 .set_fmt = wm8994_set_dai_fmt, 2836 .set_fmt = wm8994_set_dai_fmt,
2912 .hw_params = wm8994_hw_params, 2837 .hw_params = wm8994_hw_params,
2913 .shutdown = wm8994_aif_shutdown,
2914 .digital_mute = wm8994_aif_mute, 2838 .digital_mute = wm8994_aif_mute,
2915 .set_pll = wm8994_set_fll, 2839 .set_pll = wm8994_set_fll,
2916 .set_tristate = wm8994_set_tristate, 2840 .set_tristate = wm8994_set_tristate,
@@ -2918,7 +2842,6 @@ static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2918 2842
2919static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = { 2843static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2920 .hw_params = wm8994_aif3_hw_params, 2844 .hw_params = wm8994_aif3_hw_params,
2921 .set_tristate = wm8994_set_tristate,
2922}; 2845};
2923 2846
2924static struct snd_soc_dai_driver wm8994_dai[] = { 2847static struct snd_soc_dai_driver wm8994_dai[] = {
@@ -3126,14 +3049,14 @@ static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3126 3049
3127 /* Expand the array... */ 3050 /* Expand the array... */
3128 t = krealloc(wm8994->retune_mobile_texts, 3051 t = krealloc(wm8994->retune_mobile_texts,
3129 sizeof(char *) * 3052 sizeof(char *) *
3130 (wm8994->num_retune_mobile_texts + 1), 3053 (wm8994->num_retune_mobile_texts + 1),
3131 GFP_KERNEL); 3054 GFP_KERNEL);
3132 if (t == NULL) 3055 if (t == NULL)
3133 continue; 3056 continue;
3134 3057
3135 /* ...store the new entry... */ 3058 /* ...store the new entry... */
3136 t[wm8994->num_retune_mobile_texts] = 3059 t[wm8994->num_retune_mobile_texts] =
3137 pdata->retune_mobile_cfgs[i].name; 3060 pdata->retune_mobile_cfgs[i].name;
3138 3061
3139 /* ...and remember the new version. */ 3062 /* ...and remember the new version. */
@@ -3304,25 +3227,25 @@ int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3304} 3227}
3305EXPORT_SYMBOL_GPL(wm8994_mic_detect); 3228EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3306 3229
3307static irqreturn_t wm8994_mic_irq(int irq, void *data) 3230static void wm8994_mic_work(struct work_struct *work)
3308{ 3231{
3309 struct wm8994_priv *priv = data; 3232 struct wm8994_priv *priv = container_of(work,
3310 struct snd_soc_codec *codec = priv->codec; 3233 struct wm8994_priv,
3311 int reg; 3234 mic_work.work);
3235 struct regmap *regmap = priv->wm8994->regmap;
3236 struct device *dev = priv->wm8994->dev;
3237 unsigned int reg;
3238 int ret;
3312 int report; 3239 int report;
3313 3240
3314#ifndef CONFIG_SND_SOC_WM8994_MODULE 3241 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3315 trace_snd_soc_jack_irq(dev_name(codec->dev)); 3242 if (ret < 0) {
3316#endif 3243 dev_err(dev, "Failed to read microphone status: %d\n",
3317 3244 ret);
3318 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2); 3245 return;
3319 if (reg < 0) {
3320 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3321 reg);
3322 return IRQ_HANDLED;
3323 } 3246 }
3324 3247
3325 dev_dbg(codec->dev, "Microphone status: %x\n", reg); 3248 dev_dbg(dev, "Microphone status: %x\n", reg);
3326 3249
3327 report = 0; 3250 report = 0;
3328 if (reg & WM8994_MIC1_DET_STS) { 3251 if (reg & WM8994_MIC1_DET_STS) {
@@ -3361,6 +3284,20 @@ static irqreturn_t wm8994_mic_irq(int irq, void *data)
3361 3284
3362 snd_soc_jack_report(priv->micdet[1].jack, report, 3285 snd_soc_jack_report(priv->micdet[1].jack, report,
3363 SND_JACK_HEADSET | SND_JACK_BTN_0); 3286 SND_JACK_HEADSET | SND_JACK_BTN_0);
3287}
3288
3289static irqreturn_t wm8994_mic_irq(int irq, void *data)
3290{
3291 struct wm8994_priv *priv = data;
3292 struct snd_soc_codec *codec = priv->codec;
3293
3294#ifndef CONFIG_SND_SOC_WM8994_MODULE
3295 trace_snd_soc_jack_irq(dev_name(codec->dev));
3296#endif
3297
3298 pm_wakeup_event(codec->dev, 300);
3299
3300 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
3364 3301
3365 return IRQ_HANDLED; 3302 return IRQ_HANDLED;
3366} 3303}
@@ -3415,9 +3352,6 @@ static void wm8958_default_micdet(u16 status, void *data)
3415 3352
3416 wm8958_micd_set_rate(codec); 3353 wm8958_micd_set_rate(codec);
3417 3354
3418 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3419 SND_JACK_HEADSET);
3420
3421 /* If we have jackdet that will detect removal */ 3355 /* If we have jackdet that will detect removal */
3422 if (wm8994->jackdet) { 3356 if (wm8994->jackdet) {
3423 mutex_lock(&wm8994->accdet_lock); 3357 mutex_lock(&wm8994->accdet_lock);
@@ -3430,14 +3364,13 @@ static void wm8958_default_micdet(u16 status, void *data)
3430 3364
3431 mutex_unlock(&wm8994->accdet_lock); 3365 mutex_unlock(&wm8994->accdet_lock);
3432 3366
3433 if (wm8994->pdata->jd_ext_cap) { 3367 if (wm8994->pdata->jd_ext_cap)
3434 mutex_lock(&codec->mutex);
3435 snd_soc_dapm_disable_pin(&codec->dapm, 3368 snd_soc_dapm_disable_pin(&codec->dapm,
3436 "MICBIAS2"); 3369 "MICBIAS2");
3437 snd_soc_dapm_sync(&codec->dapm);
3438 mutex_unlock(&codec->mutex);
3439 }
3440 } 3370 }
3371
3372 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3373 SND_JACK_HEADSET);
3441 } 3374 }
3442 3375
3443 /* Report short circuit as a button */ 3376 /* Report short circuit as a button */
@@ -3489,6 +3422,8 @@ static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3489 if (present) { 3422 if (present) {
3490 dev_dbg(codec->dev, "Jack detected\n"); 3423 dev_dbg(codec->dev, "Jack detected\n");
3491 3424
3425 wm8958_micd_set_rate(codec);
3426
3492 snd_soc_update_bits(codec, WM8958_MICBIAS2, 3427 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3493 WM8958_MICB2_DISCH, 0); 3428 WM8958_MICB2_DISCH, 0);
3494 3429
@@ -3526,16 +3461,11 @@ static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3526 3461
3527 /* If required for an external cap force MICBIAS on */ 3462 /* If required for an external cap force MICBIAS on */
3528 if (wm8994->pdata->jd_ext_cap) { 3463 if (wm8994->pdata->jd_ext_cap) {
3529 mutex_lock(&codec->mutex);
3530
3531 if (present) 3464 if (present)
3532 snd_soc_dapm_force_enable_pin(&codec->dapm, 3465 snd_soc_dapm_force_enable_pin(&codec->dapm,
3533 "MICBIAS2"); 3466 "MICBIAS2");
3534 else 3467 else
3535 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2"); 3468 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3536
3537 snd_soc_dapm_sync(&codec->dapm);
3538 mutex_unlock(&codec->mutex);
3539 } 3469 }
3540 3470
3541 if (present) 3471 if (present)
@@ -3740,6 +3670,7 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec)
3740 wm8994->codec = codec; 3670 wm8994->codec = codec;
3741 3671
3742 mutex_init(&wm8994->accdet_lock); 3672 mutex_init(&wm8994->accdet_lock);
3673 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3743 3674
3744 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) 3675 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3745 init_completion(&wm8994->fll_locked[i]); 3676 init_completion(&wm8994->fll_locked[i]);
@@ -3783,13 +3714,22 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec)
3783 case WM8958: 3714 case WM8958:
3784 wm8994->hubs.dcs_readback_mode = 1; 3715 wm8994->hubs.dcs_readback_mode = 1;
3785 wm8994->hubs.hp_startup_mode = 1; 3716 wm8994->hubs.hp_startup_mode = 1;
3717
3718 switch (wm8994->revision) {
3719 case 0:
3720 break;
3721 default:
3722 wm8994->fll_byp = true;
3723 break;
3724 }
3786 break; 3725 break;
3787 3726
3788 case WM1811: 3727 case WM1811:
3789 wm8994->hubs.dcs_readback_mode = 2; 3728 wm8994->hubs.dcs_readback_mode = 2;
3790 wm8994->hubs.no_series_update = 1; 3729 wm8994->hubs.no_series_update = 1;
3791 wm8994->hubs.hp_startup_mode = 1; 3730 wm8994->hubs.hp_startup_mode = 1;
3792 wm8994->hubs.no_cache_class_w = true; 3731 wm8994->hubs.no_cache_dac_hp_direct = true;
3732 wm8994->fll_byp = true;
3793 3733
3794 switch (wm8994->revision) { 3734 switch (wm8994->revision) {
3795 case 0: 3735 case 0:
@@ -4010,7 +3950,8 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec)
4010 break; 3950 break;
4011 } 3951 }
4012 3952
4013 wm8994_update_class_w(codec); 3953 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
3954 wm_hubs_update_class_w(codec);
4014 3955
4015 wm8994_handle_pdata(wm8994); 3956 wm8994_handle_pdata(wm8994);
4016 3957
@@ -4075,7 +4016,6 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec)
4075 ARRAY_SIZE(wm8994_dac_widgets)); 4016 ARRAY_SIZE(wm8994_dac_widgets));
4076 break; 4017 break;
4077 } 4018 }
4078
4079 4019
4080 wm_hubs_add_analogue_routes(codec, 0, 0); 4020 wm_hubs_add_analogue_routes(codec, 0, 0);
4081 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 4021 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
@@ -4140,7 +4080,7 @@ err_irq:
4140 return ret; 4080 return ret;
4141} 4081}
4142 4082
4143static int wm8994_codec_remove(struct snd_soc_codec *codec) 4083static int wm8994_codec_remove(struct snd_soc_codec *codec)
4144{ 4084{
4145 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 4085 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4146 struct wm8994 *control = wm8994->wm8994; 4086 struct wm8994 *control = wm8994->wm8994;
@@ -4181,14 +4121,10 @@ static int wm8994_codec_remove(struct snd_soc_codec *codec)
4181 free_irq(wm8994->micdet_irq, wm8994); 4121 free_irq(wm8994->micdet_irq, wm8994);
4182 break; 4122 break;
4183 } 4123 }
4184 if (wm8994->mbc) 4124 release_firmware(wm8994->mbc);
4185 release_firmware(wm8994->mbc); 4125 release_firmware(wm8994->mbc_vss);
4186 if (wm8994->mbc_vss) 4126 release_firmware(wm8994->enh_eq);
4187 release_firmware(wm8994->mbc_vss);
4188 if (wm8994->enh_eq)
4189 release_firmware(wm8994->enh_eq);
4190 kfree(wm8994->retune_mobile_texts); 4127 kfree(wm8994->retune_mobile_texts);
4191
4192 return 0; 4128 return 0;
4193} 4129}
4194 4130
diff --git a/sound/soc/codecs/wm8994.h b/sound/soc/codecs/wm8994.h
index c724112998d8..d77e06f0a675 100644
--- a/sound/soc/codecs/wm8994.h
+++ b/sound/soc/codecs/wm8994.h
@@ -12,6 +12,7 @@
12#include <sound/soc.h> 12#include <sound/soc.h>
13#include <linux/firmware.h> 13#include <linux/firmware.h>
14#include <linux/completion.h> 14#include <linux/completion.h>
15#include <linux/workqueue.h>
15 16
16#include "wm_hubs.h" 17#include "wm_hubs.h"
17 18
@@ -79,6 +80,7 @@ struct wm8994_priv {
79 struct wm8994_fll_config fll[2], fll_suspend[2]; 80 struct wm8994_fll_config fll[2], fll_suspend[2];
80 struct completion fll_locked[2]; 81 struct completion fll_locked[2];
81 bool fll_locked_irq; 82 bool fll_locked_irq;
83 bool fll_byp;
82 84
83 int vmid_refcount; 85 int vmid_refcount;
84 int active_refcount; 86 int active_refcount;
@@ -126,6 +128,7 @@ struct wm8994_priv {
126 128
127 struct mutex accdet_lock; 129 struct mutex accdet_lock;
128 struct wm8994_micdet micdet[2]; 130 struct wm8994_micdet micdet[2];
131 struct delayed_work mic_work;
129 bool mic_detecting; 132 bool mic_detecting;
130 bool jack_mic; 133 bool jack_mic;
131 int btn_mask; 134 int btn_mask;
diff --git a/sound/soc/codecs/wm8996.c b/sound/soc/codecs/wm8996.c
index 1fd635494045..8af422e38fd0 100644
--- a/sound/soc/codecs/wm8996.c
+++ b/sound/soc/codecs/wm8996.c
@@ -1770,7 +1770,13 @@ static int wm8996_set_bias_level(struct snd_soc_codec *codec,
1770 1770
1771 switch (level) { 1771 switch (level) {
1772 case SND_SOC_BIAS_ON: 1772 case SND_SOC_BIAS_ON:
1773 break;
1773 case SND_SOC_BIAS_PREPARE: 1774 case SND_SOC_BIAS_PREPARE:
1775 /* Put the MICBIASes into regulating mode */
1776 snd_soc_update_bits(codec, WM8996_MICBIAS_1,
1777 WM8996_MICB1_MODE, 0);
1778 snd_soc_update_bits(codec, WM8996_MICBIAS_2,
1779 WM8996_MICB2_MODE, 0);
1774 break; 1780 break;
1775 1781
1776 case SND_SOC_BIAS_STANDBY: 1782 case SND_SOC_BIAS_STANDBY:
@@ -1793,6 +1799,12 @@ static int wm8996_set_bias_level(struct snd_soc_codec *codec,
1793 regcache_cache_only(codec->control_data, false); 1799 regcache_cache_only(codec->control_data, false);
1794 regcache_sync(codec->control_data); 1800 regcache_sync(codec->control_data);
1795 } 1801 }
1802
1803 /* Bypass the MICBIASes for lowest power */
1804 snd_soc_update_bits(codec, WM8996_MICBIAS_1,
1805 WM8996_MICB1_MODE, WM8996_MICB1_MODE);
1806 snd_soc_update_bits(codec, WM8996_MICBIAS_2,
1807 WM8996_MICB2_MODE, WM8996_MICB2_MODE);
1796 break; 1808 break;
1797 1809
1798 case SND_SOC_BIAS_OFF: 1810 case SND_SOC_BIAS_OFF:
diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c
index 076c126ed9b1..9328270df16c 100644
--- a/sound/soc/codecs/wm9081.c
+++ b/sound/soc/codecs/wm9081.c
@@ -774,7 +774,7 @@ static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
774SND_SOC_DAPM_INPUT("IN1"), 774SND_SOC_DAPM_INPUT("IN1"),
775SND_SOC_DAPM_INPUT("IN2"), 775SND_SOC_DAPM_INPUT("IN2"),
776 776
777SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0), 777SND_SOC_DAPM_DAC("DAC", NULL, WM9081_POWER_MANAGEMENT, 0, 0),
778 778
779SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0, 779SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
780 mixer, ARRAY_SIZE(mixer)), 780 mixer, ARRAY_SIZE(mixer)),
@@ -799,6 +799,7 @@ SND_SOC_DAPM_SUPPLY("TSENSE", WM9081_POWER_MANAGEMENT, 7, 0, NULL, 0),
799static const struct snd_soc_dapm_route wm9081_audio_paths[] = { 799static const struct snd_soc_dapm_route wm9081_audio_paths[] = {
800 { "DAC", NULL, "CLK_SYS" }, 800 { "DAC", NULL, "CLK_SYS" },
801 { "DAC", NULL, "CLK_DSP" }, 801 { "DAC", NULL, "CLK_DSP" },
802 { "DAC", NULL, "AIF" },
802 803
803 { "Mixer", "IN1 Switch", "IN1" }, 804 { "Mixer", "IN1 Switch", "IN1" },
804 { "Mixer", "IN2 Switch", "IN2" }, 805 { "Mixer", "IN2 Switch", "IN2" },
@@ -1252,7 +1253,7 @@ static const struct snd_soc_dai_ops wm9081_dai_ops = {
1252static struct snd_soc_dai_driver wm9081_dai = { 1253static struct snd_soc_dai_driver wm9081_dai = {
1253 .name = "wm9081-hifi", 1254 .name = "wm9081-hifi",
1254 .playback = { 1255 .playback = {
1255 .stream_name = "HiFi Playback", 1256 .stream_name = "AIF",
1256 .channels_min = 1, 1257 .channels_min = 1,
1257 .channels_max = 2, 1258 .channels_max = 2,
1258 .rates = WM9081_RATES, 1259 .rates = WM9081_RATES,
diff --git a/sound/soc/codecs/wm9705.c b/sound/soc/codecs/wm9705.c
index cacc6a86b46f..e8e782a0c78d 100644
--- a/sound/soc/codecs/wm9705.c
+++ b/sound/soc/codecs/wm9705.c
@@ -236,9 +236,7 @@ static int ac97_write(struct snd_soc_codec *codec, unsigned int reg,
236static int ac97_prepare(struct snd_pcm_substream *substream, 236static int ac97_prepare(struct snd_pcm_substream *substream,
237 struct snd_soc_dai *dai) 237 struct snd_soc_dai *dai)
238{ 238{
239 struct snd_pcm_runtime *runtime = substream->runtime; 239 struct snd_soc_codec *codec = dai->codec;
240 struct snd_soc_pcm_runtime *rtd = substream->private_data;
241 struct snd_soc_codec *codec = rtd->codec;
242 int reg; 240 int reg;
243 u16 vra; 241 u16 vra;
244 242
@@ -250,7 +248,7 @@ static int ac97_prepare(struct snd_pcm_substream *substream,
250 else 248 else
251 reg = AC97_PCM_LR_ADC_RATE; 249 reg = AC97_PCM_LR_ADC_RATE;
252 250
253 return ac97_write(codec, reg, runtime->rate); 251 return ac97_write(codec, reg, substream->runtime->rate);
254} 252}
255 253
256#define WM9705_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | \ 254#define WM9705_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | \
diff --git a/sound/soc/codecs/wm9712.c b/sound/soc/codecs/wm9712.c
index b342ae50bcd6..a1541414d904 100644
--- a/sound/soc/codecs/wm9712.c
+++ b/sound/soc/codecs/wm9712.c
@@ -467,11 +467,10 @@ static int ac97_write(struct snd_soc_codec *codec, unsigned int reg,
467static int ac97_prepare(struct snd_pcm_substream *substream, 467static int ac97_prepare(struct snd_pcm_substream *substream,
468 struct snd_soc_dai *dai) 468 struct snd_soc_dai *dai)
469{ 469{
470 struct snd_pcm_runtime *runtime = substream->runtime; 470 struct snd_soc_codec *codec = dai->codec;
471 struct snd_soc_pcm_runtime *rtd = substream->private_data;
472 struct snd_soc_codec *codec =rtd->codec;
473 int reg; 471 int reg;
474 u16 vra; 472 u16 vra;
473 struct snd_pcm_runtime *runtime = substream->runtime;
475 474
476 vra = ac97_read(codec, AC97_EXTENDED_STATUS); 475 vra = ac97_read(codec, AC97_EXTENDED_STATUS);
477 ac97_write(codec, AC97_EXTENDED_STATUS, vra | 0x1); 476 ac97_write(codec, AC97_EXTENDED_STATUS, vra | 0x1);
@@ -487,10 +486,9 @@ static int ac97_prepare(struct snd_pcm_substream *substream,
487static int ac97_aux_prepare(struct snd_pcm_substream *substream, 486static int ac97_aux_prepare(struct snd_pcm_substream *substream,
488 struct snd_soc_dai *dai) 487 struct snd_soc_dai *dai)
489{ 488{
490 struct snd_pcm_runtime *runtime = substream->runtime; 489 struct snd_soc_codec *codec = dai->codec;
491 struct snd_soc_pcm_runtime *rtd = substream->private_data;
492 struct snd_soc_codec *codec = rtd->codec;
493 u16 vra, xsle; 490 u16 vra, xsle;
491 struct snd_pcm_runtime *runtime = substream->runtime;
494 492
495 vra = ac97_read(codec, AC97_EXTENDED_STATUS); 493 vra = ac97_read(codec, AC97_EXTENDED_STATUS);
496 ac97_write(codec, AC97_EXTENDED_STATUS, vra | 0x1); 494 ac97_write(codec, AC97_EXTENDED_STATUS, vra | 0x1);
diff --git a/sound/soc/codecs/wm_hubs.c b/sound/soc/codecs/wm_hubs.c
index 6c028c470601..dfe957a47f29 100644
--- a/sound/soc/codecs/wm_hubs.c
+++ b/sound/soc/codecs/wm_hubs.c
@@ -109,12 +109,103 @@ irqreturn_t wm_hubs_dcs_done(int irq, void *data)
109} 109}
110EXPORT_SYMBOL_GPL(wm_hubs_dcs_done); 110EXPORT_SYMBOL_GPL(wm_hubs_dcs_done);
111 111
112static bool wm_hubs_dac_hp_direct(struct snd_soc_codec *codec)
113{
114 int reg;
115
116 /* If we're going via the mixer we'll need to do additional checks */
117 reg = snd_soc_read(codec, WM8993_OUTPUT_MIXER1);
118 if (!(reg & WM8993_DACL_TO_HPOUT1L)) {
119 if (reg & ~WM8993_DACL_TO_MIXOUTL) {
120 dev_vdbg(codec->dev, "Analogue paths connected: %x\n",
121 reg & ~WM8993_DACL_TO_HPOUT1L);
122 return false;
123 } else {
124 dev_vdbg(codec->dev, "HPL connected to mixer\n");
125 }
126 } else {
127 dev_vdbg(codec->dev, "HPL connected to DAC\n");
128 }
129
130 reg = snd_soc_read(codec, WM8993_OUTPUT_MIXER2);
131 if (!(reg & WM8993_DACR_TO_HPOUT1R)) {
132 if (reg & ~WM8993_DACR_TO_MIXOUTR) {
133 dev_vdbg(codec->dev, "Analogue paths connected: %x\n",
134 reg & ~WM8993_DACR_TO_HPOUT1R);
135 return false;
136 } else {
137 dev_vdbg(codec->dev, "HPR connected to mixer\n");
138 }
139 } else {
140 dev_vdbg(codec->dev, "HPR connected to DAC\n");
141 }
142
143 return true;
144}
145
146struct wm_hubs_dcs_cache {
147 struct list_head list;
148 unsigned int left;
149 unsigned int right;
150 u16 dcs_cfg;
151};
152
153static bool wm_hubs_dcs_cache_get(struct snd_soc_codec *codec,
154 struct wm_hubs_dcs_cache **entry)
155{
156 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
157 struct wm_hubs_dcs_cache *cache;
158 unsigned int left, right;
159
160 left = snd_soc_read(codec, WM8993_LEFT_OUTPUT_VOLUME);
161 left &= WM8993_HPOUT1L_VOL_MASK;
162
163 right = snd_soc_read(codec, WM8993_RIGHT_OUTPUT_VOLUME);
164 right &= WM8993_HPOUT1R_VOL_MASK;
165
166 list_for_each_entry(cache, &hubs->dcs_cache, list) {
167 if (cache->left != left || cache->right != right)
168 continue;
169
170 *entry = cache;
171 return true;
172 }
173
174 return false;
175}
176
177static void wm_hubs_dcs_cache_set(struct snd_soc_codec *codec, u16 dcs_cfg)
178{
179 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
180 struct wm_hubs_dcs_cache *cache;
181
182 if (hubs->no_cache_dac_hp_direct)
183 return;
184
185 cache = devm_kzalloc(codec->dev, sizeof(*cache), GFP_KERNEL);
186 if (!cache) {
187 dev_err(codec->dev, "Failed to allocate DCS cache entry\n");
188 return;
189 }
190
191 cache->left = snd_soc_read(codec, WM8993_LEFT_OUTPUT_VOLUME);
192 cache->left &= WM8993_HPOUT1L_VOL_MASK;
193
194 cache->right = snd_soc_read(codec, WM8993_RIGHT_OUTPUT_VOLUME);
195 cache->right &= WM8993_HPOUT1R_VOL_MASK;
196
197 cache->dcs_cfg = dcs_cfg;
198
199 list_add_tail(&cache->list, &hubs->dcs_cache);
200}
201
112/* 202/*
113 * Startup calibration of the DC servo 203 * Startup calibration of the DC servo
114 */ 204 */
115static void calibrate_dc_servo(struct snd_soc_codec *codec) 205static void calibrate_dc_servo(struct snd_soc_codec *codec)
116{ 206{
117 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec); 207 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
208 struct wm_hubs_dcs_cache *cache;
118 s8 offset; 209 s8 offset;
119 u16 reg, reg_l, reg_r, dcs_cfg, dcs_reg; 210 u16 reg, reg_l, reg_r, dcs_cfg, dcs_reg;
120 211
@@ -129,10 +220,11 @@ static void calibrate_dc_servo(struct snd_soc_codec *codec)
129 220
130 /* If we're using a digital only path and have a previously 221 /* If we're using a digital only path and have a previously
131 * callibrated DC servo offset stored then use that. */ 222 * callibrated DC servo offset stored then use that. */
132 if (hubs->class_w && hubs->class_w_dcs) { 223 if (wm_hubs_dac_hp_direct(codec) &&
133 dev_dbg(codec->dev, "Using cached DC servo offset %x\n", 224 wm_hubs_dcs_cache_get(codec, &cache)) {
134 hubs->class_w_dcs); 225 dev_dbg(codec->dev, "Using cached DCS offset %x for %d,%d\n",
135 snd_soc_write(codec, dcs_reg, hubs->class_w_dcs); 226 cache->dcs_cfg, cache->left, cache->right);
227 snd_soc_write(codec, dcs_reg, cache->dcs_cfg);
136 wait_for_dc_servo(codec, 228 wait_for_dc_servo(codec,
137 WM8993_DCS_TRIG_DAC_WR_0 | 229 WM8993_DCS_TRIG_DAC_WR_0 |
138 WM8993_DCS_TRIG_DAC_WR_1); 230 WM8993_DCS_TRIG_DAC_WR_1);
@@ -207,8 +299,8 @@ static void calibrate_dc_servo(struct snd_soc_codec *codec)
207 299
208 /* Save the callibrated offset if we're in class W mode and 300 /* Save the callibrated offset if we're in class W mode and
209 * therefore don't have any analogue signal mixed in. */ 301 * therefore don't have any analogue signal mixed in. */
210 if (hubs->class_w && !hubs->no_cache_class_w) 302 if (wm_hubs_dac_hp_direct(codec))
211 hubs->class_w_dcs = dcs_cfg; 303 wm_hubs_dcs_cache_set(codec, dcs_cfg);
212} 304}
213 305
214/* 306/*
@@ -223,9 +315,6 @@ static int wm8993_put_dc_servo(struct snd_kcontrol *kcontrol,
223 315
224 ret = snd_soc_put_volsw(kcontrol, ucontrol); 316 ret = snd_soc_put_volsw(kcontrol, ucontrol);
225 317
226 /* Updating the analogue gains invalidates the DC servo cache */
227 hubs->class_w_dcs = 0;
228
229 /* If we're applying an offset correction then updating the 318 /* If we're applying an offset correction then updating the
230 * callibration would be likely to introduce further offsets. */ 319 * callibration would be likely to introduce further offsets. */
231 if (hubs->dcs_codes_l || hubs->dcs_codes_r || hubs->no_series_update) 320 if (hubs->dcs_codes_l || hubs->dcs_codes_r || hubs->no_series_update)
@@ -530,6 +619,86 @@ static int lineout_event(struct snd_soc_dapm_widget *w,
530 return 0; 619 return 0;
531} 620}
532 621
622void wm_hubs_update_class_w(struct snd_soc_codec *codec)
623{
624 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
625 int enable = WM8993_CP_DYN_V | WM8993_CP_DYN_FREQ;
626
627 if (!wm_hubs_dac_hp_direct(codec))
628 enable = false;
629
630 if (hubs->check_class_w_digital && !hubs->check_class_w_digital(codec))
631 enable = false;
632
633 dev_vdbg(codec->dev, "Class W %s\n", enable ? "enabled" : "disabled");
634
635 snd_soc_update_bits(codec, WM8993_CLASS_W_0,
636 WM8993_CP_DYN_V | WM8993_CP_DYN_FREQ, enable);
637}
638EXPORT_SYMBOL_GPL(wm_hubs_update_class_w);
639
640#define WM_HUBS_SINGLE_W(xname, reg, shift, max, invert) \
641{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
642 .info = snd_soc_info_volsw, \
643 .get = snd_soc_dapm_get_volsw, .put = class_w_put_volsw, \
644 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
645
646static int class_w_put_volsw(struct snd_kcontrol *kcontrol,
647 struct snd_ctl_elem_value *ucontrol)
648{
649 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
650 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
651 struct snd_soc_codec *codec = widget->codec;
652 int ret;
653
654 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
655
656 wm_hubs_update_class_w(codec);
657
658 return ret;
659}
660
661#define WM_HUBS_ENUM_W(xname, xenum) \
662{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
663 .info = snd_soc_info_enum_double, \
664 .get = snd_soc_dapm_get_enum_double, \
665 .put = class_w_put_double, \
666 .private_value = (unsigned long)&xenum }
667
668static int class_w_put_double(struct snd_kcontrol *kcontrol,
669 struct snd_ctl_elem_value *ucontrol)
670{
671 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
672 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
673 struct snd_soc_codec *codec = widget->codec;
674 int ret;
675
676 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
677
678 wm_hubs_update_class_w(codec);
679
680 return ret;
681}
682
683static const char *hp_mux_text[] = {
684 "Mixer",
685 "DAC",
686};
687
688static const struct soc_enum hpl_enum =
689 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text);
690
691const struct snd_kcontrol_new wm_hubs_hpl_mux =
692 WM_HUBS_ENUM_W("Left Headphone Mux", hpl_enum);
693EXPORT_SYMBOL_GPL(wm_hubs_hpl_mux);
694
695static const struct soc_enum hpr_enum =
696 SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text);
697
698const struct snd_kcontrol_new wm_hubs_hpr_mux =
699 WM_HUBS_ENUM_W("Right Headphone Mux", hpr_enum);
700EXPORT_SYMBOL_GPL(wm_hubs_hpr_mux);
701
533static const struct snd_kcontrol_new in1l_pga[] = { 702static const struct snd_kcontrol_new in1l_pga[] = {
534SOC_DAPM_SINGLE("IN1LP Switch", WM8993_INPUT_MIXER2, 5, 1, 0), 703SOC_DAPM_SINGLE("IN1LP Switch", WM8993_INPUT_MIXER2, 5, 1, 0),
535SOC_DAPM_SINGLE("IN1LN Switch", WM8993_INPUT_MIXER2, 4, 1, 0), 704SOC_DAPM_SINGLE("IN1LN Switch", WM8993_INPUT_MIXER2, 4, 1, 0),
@@ -561,25 +730,25 @@ SOC_DAPM_SINGLE("IN1R Switch", WM8993_INPUT_MIXER4, 5, 1, 0),
561}; 730};
562 731
563static const struct snd_kcontrol_new left_output_mixer[] = { 732static const struct snd_kcontrol_new left_output_mixer[] = {
564SOC_DAPM_SINGLE("Right Input Switch", WM8993_OUTPUT_MIXER1, 7, 1, 0), 733WM_HUBS_SINGLE_W("Right Input Switch", WM8993_OUTPUT_MIXER1, 7, 1, 0),
565SOC_DAPM_SINGLE("Left Input Switch", WM8993_OUTPUT_MIXER1, 6, 1, 0), 734WM_HUBS_SINGLE_W("Left Input Switch", WM8993_OUTPUT_MIXER1, 6, 1, 0),
566SOC_DAPM_SINGLE("IN2RN Switch", WM8993_OUTPUT_MIXER1, 5, 1, 0), 735WM_HUBS_SINGLE_W("IN2RN Switch", WM8993_OUTPUT_MIXER1, 5, 1, 0),
567SOC_DAPM_SINGLE("IN2LN Switch", WM8993_OUTPUT_MIXER1, 4, 1, 0), 736WM_HUBS_SINGLE_W("IN2LN Switch", WM8993_OUTPUT_MIXER1, 4, 1, 0),
568SOC_DAPM_SINGLE("IN2LP Switch", WM8993_OUTPUT_MIXER1, 1, 1, 0), 737WM_HUBS_SINGLE_W("IN2LP Switch", WM8993_OUTPUT_MIXER1, 1, 1, 0),
569SOC_DAPM_SINGLE("IN1R Switch", WM8993_OUTPUT_MIXER1, 3, 1, 0), 738WM_HUBS_SINGLE_W("IN1R Switch", WM8993_OUTPUT_MIXER1, 3, 1, 0),
570SOC_DAPM_SINGLE("IN1L Switch", WM8993_OUTPUT_MIXER1, 2, 1, 0), 739WM_HUBS_SINGLE_W("IN1L Switch", WM8993_OUTPUT_MIXER1, 2, 1, 0),
571SOC_DAPM_SINGLE("DAC Switch", WM8993_OUTPUT_MIXER1, 0, 1, 0), 740WM_HUBS_SINGLE_W("DAC Switch", WM8993_OUTPUT_MIXER1, 0, 1, 0),
572}; 741};
573 742
574static const struct snd_kcontrol_new right_output_mixer[] = { 743static const struct snd_kcontrol_new right_output_mixer[] = {
575SOC_DAPM_SINGLE("Left Input Switch", WM8993_OUTPUT_MIXER2, 7, 1, 0), 744WM_HUBS_SINGLE_W("Left Input Switch", WM8993_OUTPUT_MIXER2, 7, 1, 0),
576SOC_DAPM_SINGLE("Right Input Switch", WM8993_OUTPUT_MIXER2, 6, 1, 0), 745WM_HUBS_SINGLE_W("Right Input Switch", WM8993_OUTPUT_MIXER2, 6, 1, 0),
577SOC_DAPM_SINGLE("IN2LN Switch", WM8993_OUTPUT_MIXER2, 5, 1, 0), 746WM_HUBS_SINGLE_W("IN2LN Switch", WM8993_OUTPUT_MIXER2, 5, 1, 0),
578SOC_DAPM_SINGLE("IN2RN Switch", WM8993_OUTPUT_MIXER2, 4, 1, 0), 747WM_HUBS_SINGLE_W("IN2RN Switch", WM8993_OUTPUT_MIXER2, 4, 1, 0),
579SOC_DAPM_SINGLE("IN1L Switch", WM8993_OUTPUT_MIXER2, 3, 1, 0), 748WM_HUBS_SINGLE_W("IN1L Switch", WM8993_OUTPUT_MIXER2, 3, 1, 0),
580SOC_DAPM_SINGLE("IN1R Switch", WM8993_OUTPUT_MIXER2, 2, 1, 0), 749WM_HUBS_SINGLE_W("IN1R Switch", WM8993_OUTPUT_MIXER2, 2, 1, 0),
581SOC_DAPM_SINGLE("IN2RP Switch", WM8993_OUTPUT_MIXER2, 1, 1, 0), 750WM_HUBS_SINGLE_W("IN2RP Switch", WM8993_OUTPUT_MIXER2, 1, 1, 0),
582SOC_DAPM_SINGLE("DAC Switch", WM8993_OUTPUT_MIXER2, 0, 1, 0), 751WM_HUBS_SINGLE_W("DAC Switch", WM8993_OUTPUT_MIXER2, 0, 1, 0),
583}; 752};
584 753
585static const struct snd_kcontrol_new earpiece_mixer[] = { 754static const struct snd_kcontrol_new earpiece_mixer[] = {
@@ -943,6 +1112,7 @@ int wm_hubs_add_analogue_routes(struct snd_soc_codec *codec,
943 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec); 1112 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
944 struct snd_soc_dapm_context *dapm = &codec->dapm; 1113 struct snd_soc_dapm_context *dapm = &codec->dapm;
945 1114
1115 INIT_LIST_HEAD(&hubs->dcs_cache);
946 init_completion(&hubs->dcs_done); 1116 init_completion(&hubs->dcs_done);
947 1117
948 snd_soc_dapm_add_routes(dapm, analogue_routes, 1118 snd_soc_dapm_add_routes(dapm, analogue_routes,
diff --git a/sound/soc/codecs/wm_hubs.h b/sound/soc/codecs/wm_hubs.h
index 5705276f4943..da2dc899ce6d 100644
--- a/sound/soc/codecs/wm_hubs.h
+++ b/sound/soc/codecs/wm_hubs.h
@@ -16,6 +16,8 @@
16 16
17#include <linux/completion.h> 17#include <linux/completion.h>
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/list.h>
20#include <sound/control.h>
19 21
20struct snd_soc_codec; 22struct snd_soc_codec;
21 23
@@ -30,9 +32,9 @@ struct wm_hubs_data {
30 int series_startup; 32 int series_startup;
31 int no_series_update; 33 int no_series_update;
32 34
33 bool no_cache_class_w; 35 bool no_cache_dac_hp_direct;
34 bool class_w; 36 struct list_head dcs_cache;
35 u16 class_w_dcs; 37 bool (*check_class_w_digital)(struct snd_soc_codec *);
36 38
37 bool lineout1_se; 39 bool lineout1_se;
38 bool lineout1n_ena; 40 bool lineout1n_ena;
@@ -58,5 +60,9 @@ extern irqreturn_t wm_hubs_dcs_done(int irq, void *data);
58extern void wm_hubs_vmid_ena(struct snd_soc_codec *codec); 60extern void wm_hubs_vmid_ena(struct snd_soc_codec *codec);
59extern void wm_hubs_set_bias_level(struct snd_soc_codec *codec, 61extern void wm_hubs_set_bias_level(struct snd_soc_codec *codec,
60 enum snd_soc_bias_level level); 62 enum snd_soc_bias_level level);
63extern void wm_hubs_update_class_w(struct snd_soc_codec *codec);
64
65extern const struct snd_kcontrol_new wm_hubs_hpl_mux;
66extern const struct snd_kcontrol_new wm_hubs_hpr_mux;
61 67
62#endif 68#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 00:45:00 -0500