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-rw-r--r--sound/soc/codecs/88pm860x-codec.c30
-rw-r--r--sound/soc/codecs/Kconfig20
-rw-r--r--sound/soc/codecs/Makefile12
-rw-r--r--sound/soc/codecs/ad1836.c7
-rw-r--r--sound/soc/codecs/ad193x.c8
-rw-r--r--sound/soc/codecs/ad1980.c1
-rw-r--r--sound/soc/codecs/ak4535.c20
-rw-r--r--sound/soc/codecs/ak4642.c2
-rw-r--r--sound/soc/codecs/ak4671.c11
-rw-r--r--sound/soc/codecs/alc5623.c1117
-rw-r--r--sound/soc/codecs/alc5623.h161
-rw-r--r--sound/soc/codecs/cq93vc.c4
-rw-r--r--sound/soc/codecs/cs4270.c162
-rw-r--r--sound/soc/codecs/cs42l51.c7
-rw-r--r--sound/soc/codecs/cx20442.c16
-rw-r--r--sound/soc/codecs/da7210.c2
-rw-r--r--sound/soc/codecs/dmic.c81
-rw-r--r--sound/soc/codecs/jz4740.c11
-rw-r--r--sound/soc/codecs/max98088.c13
-rw-r--r--sound/soc/codecs/ssm2602.c10
-rw-r--r--sound/soc/codecs/stac9766.c2
-rw-r--r--sound/soc/codecs/tlv320aic23.c10
-rw-r--r--sound/soc/codecs/tlv320aic26.c5
-rw-r--r--sound/soc/codecs/tlv320aic3x.c71
-rw-r--r--sound/soc/codecs/tlv320dac33.c334
-rw-r--r--sound/soc/codecs/tpa6130a2.c99
-rw-r--r--sound/soc/codecs/tpa6130a2.h1
-rw-r--r--sound/soc/codecs/twl4030.c56
-rw-r--r--sound/soc/codecs/twl6040.c859
-rw-r--r--sound/soc/codecs/twl6040.h8
-rw-r--r--sound/soc/codecs/uda134x.c3
-rw-r--r--sound/soc/codecs/uda1380.c15
-rw-r--r--sound/soc/codecs/wl1273.c3
-rw-r--r--sound/soc/codecs/wm2000.c6
-rw-r--r--sound/soc/codecs/wm8350.c105
-rw-r--r--sound/soc/codecs/wm8400.c12
-rw-r--r--sound/soc/codecs/wm8510.c12
-rw-r--r--sound/soc/codecs/wm8523.c12
-rw-r--r--sound/soc/codecs/wm8580.c23
-rw-r--r--sound/soc/codecs/wm8711.c11
-rw-r--r--sound/soc/codecs/wm8728.c12
-rw-r--r--sound/soc/codecs/wm8731.c102
-rw-r--r--sound/soc/codecs/wm8737.c754
-rw-r--r--sound/soc/codecs/wm8737.h322
-rw-r--r--sound/soc/codecs/wm8741.c10
-rw-r--r--sound/soc/codecs/wm8750.c13
-rw-r--r--sound/soc/codecs/wm8753.c49
-rw-r--r--sound/soc/codecs/wm8770.c749
-rw-r--r--sound/soc/codecs/wm8770.h51
-rw-r--r--sound/soc/codecs/wm8776.c10
-rw-r--r--sound/soc/codecs/wm8804.c7
-rw-r--r--sound/soc/codecs/wm8900.c13
-rw-r--r--sound/soc/codecs/wm8903.c222
-rw-r--r--sound/soc/codecs/wm8903.h25
-rw-r--r--sound/soc/codecs/wm8904.c36
-rw-r--r--sound/soc/codecs/wm8940.c8
-rw-r--r--sound/soc/codecs/wm8955.c12
-rw-r--r--sound/soc/codecs/wm8960.c29
-rw-r--r--sound/soc/codecs/wm8961.c13
-rw-r--r--sound/soc/codecs/wm8962.c41
-rw-r--r--sound/soc/codecs/wm8971.c30
-rw-r--r--sound/soc/codecs/wm8974.c13
-rw-r--r--sound/soc/codecs/wm8978.c13
-rw-r--r--sound/soc/codecs/wm8985.c12
-rw-r--r--sound/soc/codecs/wm8988.c11
-rw-r--r--sound/soc/codecs/wm8990.c12
-rw-r--r--sound/soc/codecs/wm8993.c21
-rw-r--r--sound/soc/codecs/wm8994-tables.c3147
-rw-r--r--sound/soc/codecs/wm8994.c2544
-rw-r--r--sound/soc/codecs/wm8994.h14
-rw-r--r--sound/soc/codecs/wm8995.c1818
-rw-r--r--sound/soc/codecs/wm8995.h4269
-rw-r--r--sound/soc/codecs/wm9081.c15
-rw-r--r--sound/soc/codecs/wm9090.c18
-rw-r--r--sound/soc/codecs/wm9705.c7
-rw-r--r--sound/soc/codecs/wm9712.c10
-rw-r--r--sound/soc/codecs/wm9713.c9
-rw-r--r--sound/soc/codecs/wm_hubs.c108
-rw-r--r--sound/soc/codecs/wm_hubs.h3
79 files changed, 15066 insertions, 2828 deletions
diff --git a/sound/soc/codecs/88pm860x-codec.c b/sound/soc/codecs/88pm860x-codec.c
index 01d19e9f53f9..06b6981b8d6d 100644
--- a/sound/soc/codecs/88pm860x-codec.c
+++ b/sound/soc/codecs/88pm860x-codec.c
@@ -19,10 +19,10 @@
19#include <sound/pcm.h> 19#include <sound/pcm.h>
20#include <sound/pcm_params.h> 20#include <sound/pcm_params.h>
21#include <sound/soc.h> 21#include <sound/soc.h>
22#include <sound/soc-dapm.h>
23#include <sound/tlv.h> 22#include <sound/tlv.h>
24#include <sound/initval.h> 23#include <sound/initval.h>
25#include <sound/jack.h> 24#include <sound/jack.h>
25#include <trace/events/asoc.h>
26 26
27#include "88pm860x-codec.h" 27#include "88pm860x-codec.h"
28 28
@@ -146,7 +146,6 @@ struct pm860x_priv {
146 146
147 int irq[4]; 147 int irq[4];
148 unsigned char name[4][MAX_NAME_LEN]; 148 unsigned char name[4][MAX_NAME_LEN];
149 unsigned char reg_cache[REG_CACHE_SIZE];
150}; 149};
151 150
152/* -9450dB to 0dB in 150dB steps ( mute instead of -9450dB) */ 151/* -9450dB to 0dB in 150dB steps ( mute instead of -9450dB) */
@@ -1172,7 +1171,7 @@ static int pm860x_set_bias_level(struct snd_soc_codec *codec,
1172 break; 1171 break;
1173 1172
1174 case SND_SOC_BIAS_STANDBY: 1173 case SND_SOC_BIAS_STANDBY:
1175 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1174 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1176 /* Enable Audio PLL & Audio section */ 1175 /* Enable Audio PLL & Audio section */
1177 data = AUDIO_PLL | AUDIO_SECTION_RESET 1176 data = AUDIO_PLL | AUDIO_SECTION_RESET
1178 | AUDIO_SECTION_ON; 1177 | AUDIO_SECTION_ON;
@@ -1185,7 +1184,7 @@ static int pm860x_set_bias_level(struct snd_soc_codec *codec,
1185 pm860x_set_bits(codec->control_data, REG_MISC2, data, 0); 1184 pm860x_set_bits(codec->control_data, REG_MISC2, data, 0);
1186 break; 1185 break;
1187 } 1186 }
1188 codec->bias_level = level; 1187 codec->dapm.bias_level = level;
1189 return 0; 1188 return 0;
1190} 1189}
1191 1190
@@ -1263,6 +1262,12 @@ static irqreturn_t pm860x_codec_handler(int irq, void *data)
1263 mask = pm860x->det.hs_shrt | pm860x->det.hook_det | pm860x->det.lo_shrt 1262 mask = pm860x->det.hs_shrt | pm860x->det.hook_det | pm860x->det.lo_shrt
1264 | pm860x->det.hp_det; 1263 | pm860x->det.hp_det;
1265 1264
1265#ifndef CONFIG_SND_SOC_88PM860X_MODULE
1266 if (status & (HEADSET_STATUS | MIC_STATUS | SHORT_HS1 | SHORT_HS2 |
1267 SHORT_LO1 | SHORT_LO2))
1268 trace_snd_soc_jack_irq(dev_name(pm860x->codec->dev));
1269#endif
1270
1266 if ((pm860x->det.hp_det & SND_JACK_HEADPHONE) 1271 if ((pm860x->det.hp_det & SND_JACK_HEADPHONE)
1267 && (status & HEADSET_STATUS)) 1272 && (status & HEADSET_STATUS))
1268 report |= SND_JACK_HEADPHONE; 1273 report |= SND_JACK_HEADPHONE;
@@ -1346,6 +1351,7 @@ EXPORT_SYMBOL_GPL(pm860x_mic_jack_detect);
1346static int pm860x_probe(struct snd_soc_codec *codec) 1351static int pm860x_probe(struct snd_soc_codec *codec)
1347{ 1352{
1348 struct pm860x_priv *pm860x = snd_soc_codec_get_drvdata(codec); 1353 struct pm860x_priv *pm860x = snd_soc_codec_get_drvdata(codec);
1354 struct snd_soc_dapm_context *dapm = &codec->dapm;
1349 int i, ret; 1355 int i, ret;
1350 1356
1351 pm860x->codec = codec; 1357 pm860x->codec = codec;
@@ -1358,7 +1364,7 @@ static int pm860x_probe(struct snd_soc_codec *codec)
1358 pm860x->name[i], pm860x); 1364 pm860x->name[i], pm860x);
1359 if (ret < 0) { 1365 if (ret < 0) {
1360 dev_err(codec->dev, "Failed to request IRQ!\n"); 1366 dev_err(codec->dev, "Failed to request IRQ!\n");
1361 goto out_irq; 1367 goto out;
1362 } 1368 }
1363 } 1369 }
1364 1370
@@ -1369,22 +1375,20 @@ static int pm860x_probe(struct snd_soc_codec *codec)
1369 if (ret < 0) { 1375 if (ret < 0) {
1370 dev_err(codec->dev, "Failed to fill register cache: %d\n", 1376 dev_err(codec->dev, "Failed to fill register cache: %d\n",
1371 ret); 1377 ret);
1372 goto out_codec; 1378 goto out;
1373 } 1379 }
1374 1380
1375 snd_soc_add_controls(codec, pm860x_snd_controls, 1381 snd_soc_add_controls(codec, pm860x_snd_controls,
1376 ARRAY_SIZE(pm860x_snd_controls)); 1382 ARRAY_SIZE(pm860x_snd_controls));
1377 snd_soc_dapm_new_controls(codec, pm860x_dapm_widgets, 1383 snd_soc_dapm_new_controls(dapm, pm860x_dapm_widgets,
1378 ARRAY_SIZE(pm860x_dapm_widgets)); 1384 ARRAY_SIZE(pm860x_dapm_widgets));
1379 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 1385 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
1380 return 0; 1386 return 0;
1381 1387
1382out_codec: 1388out:
1383 i = 3; 1389 while (--i >= 0)
1384out_irq:
1385 for (; i >= 0; i--)
1386 free_irq(pm860x->irq[i], pm860x); 1390 free_irq(pm860x->irq[i], pm860x);
1387 return -EINVAL; 1391 return ret;
1388} 1392}
1389 1393
1390static int pm860x_remove(struct snd_soc_codec *codec) 1394static int pm860x_remove(struct snd_soc_codec *codec)
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 3b5690d28b8b..883a312bb293 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -22,6 +22,7 @@ config SND_SOC_ALL_CODECS
22 select SND_SOC_AK4535 if I2C 22 select SND_SOC_AK4535 if I2C
23 select SND_SOC_AK4642 if I2C 23 select SND_SOC_AK4642 if I2C
24 select SND_SOC_AK4671 if I2C 24 select SND_SOC_AK4671 if I2C
25 select SND_SOC_ALC5623 if I2C
25 select SND_SOC_CQ0093VC if MFD_DAVINCI_VOICECODEC 26 select SND_SOC_CQ0093VC if MFD_DAVINCI_VOICECODEC
26 select SND_SOC_CS42L51 if I2C 27 select SND_SOC_CS42L51 if I2C
27 select SND_SOC_CS4270 if I2C 28 select SND_SOC_CS4270 if I2C
@@ -54,9 +55,11 @@ config SND_SOC_ALL_CODECS
54 select SND_SOC_WM8727 55 select SND_SOC_WM8727
55 select SND_SOC_WM8728 if SND_SOC_I2C_AND_SPI 56 select SND_SOC_WM8728 if SND_SOC_I2C_AND_SPI
56 select SND_SOC_WM8731 if SND_SOC_I2C_AND_SPI 57 select SND_SOC_WM8731 if SND_SOC_I2C_AND_SPI
58 select SND_SOC_WM8737 if SND_SOC_I2C_AND_SPI
57 select SND_SOC_WM8741 if SND_SOC_I2C_AND_SPI 59 select SND_SOC_WM8741 if SND_SOC_I2C_AND_SPI
58 select SND_SOC_WM8750 if SND_SOC_I2C_AND_SPI 60 select SND_SOC_WM8750 if SND_SOC_I2C_AND_SPI
59 select SND_SOC_WM8753 if SND_SOC_I2C_AND_SPI 61 select SND_SOC_WM8753 if SND_SOC_I2C_AND_SPI
62 select SND_SOC_WM8770 if SPI_MASTER
60 select SND_SOC_WM8776 if SND_SOC_I2C_AND_SPI 63 select SND_SOC_WM8776 if SND_SOC_I2C_AND_SPI
61 select SND_SOC_WM8804 if SND_SOC_I2C_AND_SPI 64 select SND_SOC_WM8804 if SND_SOC_I2C_AND_SPI
62 select SND_SOC_WM8900 if I2C 65 select SND_SOC_WM8900 if I2C
@@ -75,6 +78,7 @@ config SND_SOC_ALL_CODECS
75 select SND_SOC_WM8990 if I2C 78 select SND_SOC_WM8990 if I2C
76 select SND_SOC_WM8993 if I2C 79 select SND_SOC_WM8993 if I2C
77 select SND_SOC_WM8994 if MFD_WM8994 80 select SND_SOC_WM8994 if MFD_WM8994
81 select SND_SOC_WM8995 if SND_SOC_I2C_AND_SPI
78 select SND_SOC_WM9081 if I2C 82 select SND_SOC_WM9081 if I2C
79 select SND_SOC_WM9090 if I2C 83 select SND_SOC_WM9090 if I2C
80 select SND_SOC_WM9705 if SND_SOC_AC97_BUS 84 select SND_SOC_WM9705 if SND_SOC_AC97_BUS
@@ -130,6 +134,9 @@ config SND_SOC_AK4642
130config SND_SOC_AK4671 134config SND_SOC_AK4671
131 tristate 135 tristate
132 136
137config SND_SOC_ALC5623
138 tristate
139
133config SND_SOC_CQ0093VC 140config SND_SOC_CQ0093VC
134 tristate 141 tristate
135 142
@@ -160,6 +167,9 @@ config SND_SOC_L3
160config SND_SOC_DA7210 167config SND_SOC_DA7210
161 tristate 168 tristate
162 169
170config SND_SOC_DMIC
171 tristate
172
163config SND_SOC_MAX98088 173config SND_SOC_MAX98088
164 tristate 174 tristate
165 175
@@ -231,6 +241,9 @@ config SND_SOC_WM8728
231config SND_SOC_WM8731 241config SND_SOC_WM8731
232 tristate 242 tristate
233 243
244config SND_SOC_WM8737
245 tristate
246
234config SND_SOC_WM8741 247config SND_SOC_WM8741
235 tristate 248 tristate
236 249
@@ -240,6 +253,9 @@ config SND_SOC_WM8750
240config SND_SOC_WM8753 253config SND_SOC_WM8753
241 tristate 254 tristate
242 255
256config SND_SOC_WM8770
257 tristate
258
243config SND_SOC_WM8776 259config SND_SOC_WM8776
244 tristate 260 tristate
245 261
@@ -294,6 +310,9 @@ config SND_SOC_WM8993
294config SND_SOC_WM8994 310config SND_SOC_WM8994
295 tristate 311 tristate
296 312
313config SND_SOC_WM8995
314 tristate
315
297config SND_SOC_WM9081 316config SND_SOC_WM9081
298 tristate 317 tristate
299 318
@@ -318,3 +337,4 @@ config SND_SOC_WM2000
318 337
319config SND_SOC_WM9090 338config SND_SOC_WM9090
320 tristate 339 tristate
340
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index f67a2d6f7a46..579af9c4f128 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -14,9 +14,11 @@ snd-soc-cs42l51-objs := cs42l51.o
14snd-soc-cs4270-objs := cs4270.o 14snd-soc-cs4270-objs := cs4270.o
15snd-soc-cx20442-objs := cx20442.o 15snd-soc-cx20442-objs := cx20442.o
16snd-soc-da7210-objs := da7210.o 16snd-soc-da7210-objs := da7210.o
17snd-soc-dmic-objs := dmic.o
17snd-soc-l3-objs := l3.o 18snd-soc-l3-objs := l3.o
18snd-soc-max98088-objs := max98088.o 19snd-soc-max98088-objs := max98088.o
19snd-soc-pcm3008-objs := pcm3008.o 20snd-soc-pcm3008-objs := pcm3008.o
21snd-soc-alc5623-objs := alc5623.o
20snd-soc-spdif-objs := spdif_transciever.o 22snd-soc-spdif-objs := spdif_transciever.o
21snd-soc-ssm2602-objs := ssm2602.o 23snd-soc-ssm2602-objs := ssm2602.o
22snd-soc-stac9766-objs := stac9766.o 24snd-soc-stac9766-objs := stac9766.o
@@ -38,9 +40,11 @@ snd-soc-wm8711-objs := wm8711.o
38snd-soc-wm8727-objs := wm8727.o 40snd-soc-wm8727-objs := wm8727.o
39snd-soc-wm8728-objs := wm8728.o 41snd-soc-wm8728-objs := wm8728.o
40snd-soc-wm8731-objs := wm8731.o 42snd-soc-wm8731-objs := wm8731.o
43snd-soc-wm8737-objs := wm8737.o
41snd-soc-wm8741-objs := wm8741.o 44snd-soc-wm8741-objs := wm8741.o
42snd-soc-wm8750-objs := wm8750.o 45snd-soc-wm8750-objs := wm8750.o
43snd-soc-wm8753-objs := wm8753.o 46snd-soc-wm8753-objs := wm8753.o
47snd-soc-wm8770-objs := wm8770.o
44snd-soc-wm8776-objs := wm8776.o 48snd-soc-wm8776-objs := wm8776.o
45snd-soc-wm8804-objs := wm8804.o 49snd-soc-wm8804-objs := wm8804.o
46snd-soc-wm8900-objs := wm8900.o 50snd-soc-wm8900-objs := wm8900.o
@@ -58,7 +62,8 @@ snd-soc-wm8985-objs := wm8985.o
58snd-soc-wm8988-objs := wm8988.o 62snd-soc-wm8988-objs := wm8988.o
59snd-soc-wm8990-objs := wm8990.o 63snd-soc-wm8990-objs := wm8990.o
60snd-soc-wm8993-objs := wm8993.o 64snd-soc-wm8993-objs := wm8993.o
61snd-soc-wm8994-objs := wm8994.o 65snd-soc-wm8994-objs := wm8994.o wm8994-tables.o
66snd-soc-wm8995-objs := wm8995.o
62snd-soc-wm9081-objs := wm9081.o 67snd-soc-wm9081-objs := wm9081.o
63snd-soc-wm9705-objs := wm9705.o 68snd-soc-wm9705-objs := wm9705.o
64snd-soc-wm9712-objs := wm9712.o 69snd-soc-wm9712-objs := wm9712.o
@@ -88,10 +93,12 @@ obj-$(CONFIG_SND_SOC_CS42L51) += snd-soc-cs42l51.o
88obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o 93obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o
89obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o 94obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o
90obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o 95obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o
96obj-$(CONFIG_SND_SOC_DMIC) += snd-soc-dmic.o
91obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o 97obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o
92obj-$(CONFIG_SND_SOC_JZ4740_CODEC) += snd-soc-jz4740-codec.o 98obj-$(CONFIG_SND_SOC_JZ4740_CODEC) += snd-soc-jz4740-codec.o
93obj-$(CONFIG_SND_SOC_MAX98088) += snd-soc-max98088.o 99obj-$(CONFIG_SND_SOC_MAX98088) += snd-soc-max98088.o
94obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o 100obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o
101obj-$(CONFIG_SND_SOC_ALC5623) += snd-soc-alc5623.o
95obj-$(CONFIG_SND_SOC_SPDIF) += snd-soc-spdif.o 102obj-$(CONFIG_SND_SOC_SPDIF) += snd-soc-spdif.o
96obj-$(CONFIG_SND_SOC_SSM2602) += snd-soc-ssm2602.o 103obj-$(CONFIG_SND_SOC_SSM2602) += snd-soc-ssm2602.o
97obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o 104obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o
@@ -113,9 +120,11 @@ obj-$(CONFIG_SND_SOC_WM8711) += snd-soc-wm8711.o
113obj-$(CONFIG_SND_SOC_WM8727) += snd-soc-wm8727.o 120obj-$(CONFIG_SND_SOC_WM8727) += snd-soc-wm8727.o
114obj-$(CONFIG_SND_SOC_WM8728) += snd-soc-wm8728.o 121obj-$(CONFIG_SND_SOC_WM8728) += snd-soc-wm8728.o
115obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o 122obj-$(CONFIG_SND_SOC_WM8731) += snd-soc-wm8731.o
123obj-$(CONFIG_SND_SOC_WM8737) += snd-soc-wm8737.o
116obj-$(CONFIG_SND_SOC_WM8741) += snd-soc-wm8741.o 124obj-$(CONFIG_SND_SOC_WM8741) += snd-soc-wm8741.o
117obj-$(CONFIG_SND_SOC_WM8750) += snd-soc-wm8750.o 125obj-$(CONFIG_SND_SOC_WM8750) += snd-soc-wm8750.o
118obj-$(CONFIG_SND_SOC_WM8753) += snd-soc-wm8753.o 126obj-$(CONFIG_SND_SOC_WM8753) += snd-soc-wm8753.o
127obj-$(CONFIG_SND_SOC_WM8770) += snd-soc-wm8770.o
119obj-$(CONFIG_SND_SOC_WM8776) += snd-soc-wm8776.o 128obj-$(CONFIG_SND_SOC_WM8776) += snd-soc-wm8776.o
120obj-$(CONFIG_SND_SOC_WM8804) += snd-soc-wm8804.o 129obj-$(CONFIG_SND_SOC_WM8804) += snd-soc-wm8804.o
121obj-$(CONFIG_SND_SOC_WM8900) += snd-soc-wm8900.o 130obj-$(CONFIG_SND_SOC_WM8900) += snd-soc-wm8900.o
@@ -134,6 +143,7 @@ obj-$(CONFIG_SND_SOC_WM8988) += snd-soc-wm8988.o
134obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o 143obj-$(CONFIG_SND_SOC_WM8990) += snd-soc-wm8990.o
135obj-$(CONFIG_SND_SOC_WM8993) += snd-soc-wm8993.o 144obj-$(CONFIG_SND_SOC_WM8993) += snd-soc-wm8993.o
136obj-$(CONFIG_SND_SOC_WM8994) += snd-soc-wm8994.o 145obj-$(CONFIG_SND_SOC_WM8994) += snd-soc-wm8994.o
146obj-$(CONFIG_SND_SOC_WM8995) += snd-soc-wm8995.o
137obj-$(CONFIG_SND_SOC_WM9081) += snd-soc-wm9081.o 147obj-$(CONFIG_SND_SOC_WM9081) += snd-soc-wm9081.o
138obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o 148obj-$(CONFIG_SND_SOC_WM9705) += snd-soc-wm9705.o
139obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o 149obj-$(CONFIG_SND_SOC_WM9712) += snd-soc-wm9712.o
diff --git a/sound/soc/codecs/ad1836.c b/sound/soc/codecs/ad1836.c
index d272534c8f84..ab63d52e36e1 100644
--- a/sound/soc/codecs/ad1836.c
+++ b/sound/soc/codecs/ad1836.c
@@ -27,7 +27,6 @@
27#include <sound/initval.h> 27#include <sound/initval.h>
28#include <sound/soc.h> 28#include <sound/soc.h>
29#include <sound/tlv.h> 29#include <sound/tlv.h>
30#include <sound/soc-dapm.h>
31#include <linux/spi/spi.h> 30#include <linux/spi/spi.h>
32#include "ad1836.h" 31#include "ad1836.h"
33 32
@@ -220,6 +219,7 @@ static struct snd_soc_dai_driver ad1836_dai = {
220static int ad1836_probe(struct snd_soc_codec *codec) 219static int ad1836_probe(struct snd_soc_codec *codec)
221{ 220{
222 struct ad1836_priv *ad1836 = snd_soc_codec_get_drvdata(codec); 221 struct ad1836_priv *ad1836 = snd_soc_codec_get_drvdata(codec);
222 struct snd_soc_dapm_context *dapm = &codec->dapm;
223 int ret = 0; 223 int ret = 0;
224 224
225 codec->control_data = ad1836->control_data; 225 codec->control_data = ad1836->control_data;
@@ -227,7 +227,6 @@ static int ad1836_probe(struct snd_soc_codec *codec)
227 if (ret < 0) { 227 if (ret < 0) {
228 dev_err(codec->dev, "failed to set cache I/O: %d\n", 228 dev_err(codec->dev, "failed to set cache I/O: %d\n",
229 ret); 229 ret);
230 kfree(ad1836);
231 return ret; 230 return ret;
232 } 231 }
233 232
@@ -252,9 +251,9 @@ static int ad1836_probe(struct snd_soc_codec *codec)
252 251
253 snd_soc_add_controls(codec, ad1836_snd_controls, 252 snd_soc_add_controls(codec, ad1836_snd_controls,
254 ARRAY_SIZE(ad1836_snd_controls)); 253 ARRAY_SIZE(ad1836_snd_controls));
255 snd_soc_dapm_new_controls(codec, ad1836_dapm_widgets, 254 snd_soc_dapm_new_controls(dapm, ad1836_dapm_widgets,
256 ARRAY_SIZE(ad1836_dapm_widgets)); 255 ARRAY_SIZE(ad1836_dapm_widgets));
257 snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths)); 256 snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
258 257
259 return ret; 258 return ret;
260} 259}
diff --git a/sound/soc/codecs/ad193x.c b/sound/soc/codecs/ad193x.c
index fa2834c91b9f..da46479bfcfa 100644
--- a/sound/soc/codecs/ad193x.c
+++ b/sound/soc/codecs/ad193x.c
@@ -19,12 +19,10 @@
19#include <sound/initval.h> 19#include <sound/initval.h>
20#include <sound/soc.h> 20#include <sound/soc.h>
21#include <sound/tlv.h> 21#include <sound/tlv.h>
22#include <sound/soc-dapm.h>
23#include "ad193x.h" 22#include "ad193x.h"
24 23
25/* codec private data */ 24/* codec private data */
26struct ad193x_priv { 25struct ad193x_priv {
27 u8 reg_cache[AD193X_NUM_REGS];
28 enum snd_soc_control_type bus_type; 26 enum snd_soc_control_type bus_type;
29 void *control_data; 27 void *control_data;
30 int sysclk; 28 int sysclk;
@@ -353,6 +351,7 @@ static struct snd_soc_dai_driver ad193x_dai = {
353static int ad193x_probe(struct snd_soc_codec *codec) 351static int ad193x_probe(struct snd_soc_codec *codec)
354{ 352{
355 struct ad193x_priv *ad193x = snd_soc_codec_get_drvdata(codec); 353 struct ad193x_priv *ad193x = snd_soc_codec_get_drvdata(codec);
354 struct snd_soc_dapm_context *dapm = &codec->dapm;
356 int ret; 355 int ret;
357 356
358 codec->control_data = ad193x->control_data; 357 codec->control_data = ad193x->control_data;
@@ -363,7 +362,6 @@ static int ad193x_probe(struct snd_soc_codec *codec)
363 if (ret < 0) { 362 if (ret < 0) {
364 dev_err(codec->dev, "failed to set cache I/O: %d\n", 363 dev_err(codec->dev, "failed to set cache I/O: %d\n",
365 ret); 364 ret);
366 kfree(ad193x);
367 return ret; 365 return ret;
368 } 366 }
369 367
@@ -385,9 +383,9 @@ static int ad193x_probe(struct snd_soc_codec *codec)
385 383
386 snd_soc_add_controls(codec, ad193x_snd_controls, 384 snd_soc_add_controls(codec, ad193x_snd_controls,
387 ARRAY_SIZE(ad193x_snd_controls)); 385 ARRAY_SIZE(ad193x_snd_controls));
388 snd_soc_dapm_new_controls(codec, ad193x_dapm_widgets, 386 snd_soc_dapm_new_controls(dapm, ad193x_dapm_widgets,
389 ARRAY_SIZE(ad193x_dapm_widgets)); 387 ARRAY_SIZE(ad193x_dapm_widgets));
390 snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths)); 388 snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
391 389
392 return ret; 390 return ret;
393} 391}
diff --git a/sound/soc/codecs/ad1980.c b/sound/soc/codecs/ad1980.c
index 410ccd5d41cd..34cb51ef2156 100644
--- a/sound/soc/codecs/ad1980.c
+++ b/sound/soc/codecs/ad1980.c
@@ -29,7 +29,6 @@
29#include <sound/ac97_codec.h> 29#include <sound/ac97_codec.h>
30#include <sound/initval.h> 30#include <sound/initval.h>
31#include <sound/soc.h> 31#include <sound/soc.h>
32#include <sound/soc-dapm.h>
33 32
34#include "ad1980.h" 33#include "ad1980.h"
35 34
diff --git a/sound/soc/codecs/ak4535.c b/sound/soc/codecs/ak4535.c
index cd88c8f32a38..8b38739c88f8 100644
--- a/sound/soc/codecs/ak4535.c
+++ b/sound/soc/codecs/ak4535.c
@@ -24,7 +24,6 @@
24#include <sound/pcm.h> 24#include <sound/pcm.h>
25#include <sound/pcm_params.h> 25#include <sound/pcm_params.h>
26#include <sound/soc.h> 26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h> 27#include <sound/initval.h>
29 28
30#include "ak4535.h" 29#include "ak4535.h"
@@ -290,10 +289,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
290 289
291static int ak4535_add_widgets(struct snd_soc_codec *codec) 290static int ak4535_add_widgets(struct snd_soc_codec *codec)
292{ 291{
293 snd_soc_dapm_new_controls(codec, ak4535_dapm_widgets, 292 struct snd_soc_dapm_context *dapm = &codec->dapm;
294 ARRAY_SIZE(ak4535_dapm_widgets));
295 293
296 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 294 snd_soc_dapm_new_controls(dapm, ak4535_dapm_widgets,
295 ARRAY_SIZE(ak4535_dapm_widgets));
296 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
297 297
298 return 0; 298 return 0;
299} 299}
@@ -366,9 +366,9 @@ static int ak4535_set_dai_fmt(struct snd_soc_dai *codec_dai,
366static int ak4535_mute(struct snd_soc_dai *dai, int mute) 366static int ak4535_mute(struct snd_soc_dai *dai, int mute)
367{ 367{
368 struct snd_soc_codec *codec = dai->codec; 368 struct snd_soc_codec *codec = dai->codec;
369 u16 mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC) & 0xffdf; 369 u16 mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC);
370 if (!mute) 370 if (!mute)
371 ak4535_write(codec, AK4535_DAC, mute_reg); 371 ak4535_write(codec, AK4535_DAC, mute_reg & ~0x20);
372 else 372 else
373 ak4535_write(codec, AK4535_DAC, mute_reg | 0x20); 373 ak4535_write(codec, AK4535_DAC, mute_reg | 0x20);
374 return 0; 374 return 0;
@@ -381,11 +381,11 @@ static int ak4535_set_bias_level(struct snd_soc_codec *codec,
381 381
382 switch (level) { 382 switch (level) {
383 case SND_SOC_BIAS_ON: 383 case SND_SOC_BIAS_ON:
384 mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC) & 0xffdf; 384 mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC);
385 ak4535_write(codec, AK4535_DAC, mute_reg); 385 ak4535_write(codec, AK4535_DAC, mute_reg & ~0x20);
386 break; 386 break;
387 case SND_SOC_BIAS_PREPARE: 387 case SND_SOC_BIAS_PREPARE:
388 mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC) & 0xffdf; 388 mute_reg = ak4535_read_reg_cache(codec, AK4535_DAC);
389 ak4535_write(codec, AK4535_DAC, mute_reg | 0x20); 389 ak4535_write(codec, AK4535_DAC, mute_reg | 0x20);
390 break; 390 break;
391 case SND_SOC_BIAS_STANDBY: 391 case SND_SOC_BIAS_STANDBY:
@@ -399,7 +399,7 @@ static int ak4535_set_bias_level(struct snd_soc_codec *codec,
399 ak4535_write(codec, AK4535_PM1, i & (~0x80)); 399 ak4535_write(codec, AK4535_PM1, i & (~0x80));
400 break; 400 break;
401 } 401 }
402 codec->bias_level = level; 402 codec->dapm.bias_level = level;
403 return 0; 403 return 0;
404} 404}
405 405
diff --git a/sound/soc/codecs/ak4642.c b/sound/soc/codecs/ak4642.c
index 90c90b7f4a2e..f00eba313dfd 100644
--- a/sound/soc/codecs/ak4642.c
+++ b/sound/soc/codecs/ak4642.c
@@ -26,7 +26,7 @@
26#include <linux/i2c.h> 26#include <linux/i2c.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/slab.h> 28#include <linux/slab.h>
29#include <sound/soc-dapm.h> 29#include <sound/soc.h>
30#include <sound/initval.h> 30#include <sound/initval.h>
31#include <sound/tlv.h> 31#include <sound/tlv.h>
32 32
diff --git a/sound/soc/codecs/ak4671.c b/sound/soc/codecs/ak4671.c
index 24f5f49bb9d2..2ec75abfa3e9 100644
--- a/sound/soc/codecs/ak4671.c
+++ b/sound/soc/codecs/ak4671.c
@@ -17,7 +17,6 @@
17#include <linux/delay.h> 17#include <linux/delay.h>
18#include <linux/slab.h> 18#include <linux/slab.h>
19#include <sound/soc.h> 19#include <sound/soc.h>
20#include <sound/soc-dapm.h>
21#include <sound/initval.h> 20#include <sound/initval.h>
22#include <sound/tlv.h> 21#include <sound/tlv.h>
23 22
@@ -28,7 +27,6 @@
28struct ak4671_priv { 27struct ak4671_priv {
29 enum snd_soc_control_type control_type; 28 enum snd_soc_control_type control_type;
30 void *control_data; 29 void *control_data;
31 u8 reg_cache[AK4671_CACHEREGNUM];
32}; 30};
33 31
34/* ak4671 register cache & default register settings */ 32/* ak4671 register cache & default register settings */
@@ -437,10 +435,11 @@ static const struct snd_soc_dapm_route intercon[] = {
437 435
438static int ak4671_add_widgets(struct snd_soc_codec *codec) 436static int ak4671_add_widgets(struct snd_soc_codec *codec)
439{ 437{
440 snd_soc_dapm_new_controls(codec, ak4671_dapm_widgets, 438 struct snd_soc_dapm_context *dapm = &codec->dapm;
441 ARRAY_SIZE(ak4671_dapm_widgets));
442 439
443 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 440 snd_soc_dapm_new_controls(dapm, ak4671_dapm_widgets,
441 ARRAY_SIZE(ak4671_dapm_widgets));
442 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
444 443
445 return 0; 444 return 0;
446} 445}
@@ -602,7 +601,7 @@ static int ak4671_set_bias_level(struct snd_soc_codec *codec,
602 snd_soc_write(codec, AK4671_AD_DA_POWER_MANAGEMENT, 0x00); 601 snd_soc_write(codec, AK4671_AD_DA_POWER_MANAGEMENT, 0x00);
603 break; 602 break;
604 } 603 }
605 codec->bias_level = level; 604 codec->dapm.bias_level = level;
606 return 0; 605 return 0;
607} 606}
608 607
diff --git a/sound/soc/codecs/alc5623.c b/sound/soc/codecs/alc5623.c
new file mode 100644
index 000000000000..4f377c9e868d
--- /dev/null
+++ b/sound/soc/codecs/alc5623.c
@@ -0,0 +1,1117 @@
1/*
2 * alc5623.c -- alc562[123] ALSA Soc Audio driver
3 *
4 * Copyright 2008 Realtek Microelectronics
5 * Author: flove <flove@realtek.com> Ethan <eku@marvell.com>
6 *
7 * Copyright 2010 Arnaud Patard <arnaud.patard@rtp-net.org>
8 *
9 *
10 * Based on WM8753.c
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/delay.h>
22#include <linux/pm.h>
23#include <linux/i2c.h>
24#include <linux/slab.h>
25#include <linux/platform_device.h>
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/tlv.h>
30#include <sound/soc.h>
31#include <sound/initval.h>
32#include <sound/alc5623.h>
33
34#include "alc5623.h"
35
36static int caps_charge = 2000;
37module_param(caps_charge, int, 0);
38MODULE_PARM_DESC(caps_charge, "ALC5623 cap charge time (msecs)");
39
40/* codec private data */
41struct alc5623_priv {
42 enum snd_soc_control_type control_type;
43 void *control_data;
44 struct mutex mutex;
45 u8 id;
46 unsigned int sysclk;
47 u16 reg_cache[ALC5623_VENDOR_ID2+2];
48 unsigned int add_ctrl;
49 unsigned int jack_det_ctrl;
50};
51
52static void alc5623_fill_cache(struct snd_soc_codec *codec)
53{
54 int i, step = codec->driver->reg_cache_step;
55 u16 *cache = codec->reg_cache;
56
57 /* not really efficient ... */
58 for (i = 0 ; i < codec->driver->reg_cache_size ; i += step)
59 cache[i] = codec->hw_read(codec, i);
60}
61
62static inline int alc5623_reset(struct snd_soc_codec *codec)
63{
64 return snd_soc_write(codec, ALC5623_RESET, 0);
65}
66
67static int amp_mixer_event(struct snd_soc_dapm_widget *w,
68 struct snd_kcontrol *kcontrol, int event)
69{
70 /* to power-on/off class-d amp generators/speaker */
71 /* need to write to 'index-46h' register : */
72 /* so write index num (here 0x46) to reg 0x6a */
73 /* and then 0xffff/0 to reg 0x6c */
74 snd_soc_write(w->codec, ALC5623_HID_CTRL_INDEX, 0x46);
75
76 switch (event) {
77 case SND_SOC_DAPM_PRE_PMU:
78 snd_soc_write(w->codec, ALC5623_HID_CTRL_DATA, 0xFFFF);
79 break;
80 case SND_SOC_DAPM_POST_PMD:
81 snd_soc_write(w->codec, ALC5623_HID_CTRL_DATA, 0);
82 break;
83 }
84
85 return 0;
86}
87
88/*
89 * ALC5623 Controls
90 */
91
92static const DECLARE_TLV_DB_SCALE(vol_tlv, -3450, 150, 0);
93static const DECLARE_TLV_DB_SCALE(hp_tlv, -4650, 150, 0);
94static const DECLARE_TLV_DB_SCALE(adc_rec_tlv, -1650, 150, 0);
95static const unsigned int boost_tlv[] = {
96 TLV_DB_RANGE_HEAD(3),
97 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
98 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
99 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
100};
101static const DECLARE_TLV_DB_SCALE(dig_tlv, 0, 600, 0);
102
103static const struct snd_kcontrol_new rt5621_vol_snd_controls[] = {
104 SOC_DOUBLE_TLV("Speaker Playback Volume",
105 ALC5623_SPK_OUT_VOL, 8, 0, 31, 1, hp_tlv),
106 SOC_DOUBLE("Speaker Playback Switch",
107 ALC5623_SPK_OUT_VOL, 15, 7, 1, 1),
108 SOC_DOUBLE_TLV("Headphone Playback Volume",
109 ALC5623_HP_OUT_VOL, 8, 0, 31, 1, hp_tlv),
110 SOC_DOUBLE("Headphone Playback Switch",
111 ALC5623_HP_OUT_VOL, 15, 7, 1, 1),
112};
113
114static const struct snd_kcontrol_new rt5622_vol_snd_controls[] = {
115 SOC_DOUBLE_TLV("Speaker Playback Volume",
116 ALC5623_SPK_OUT_VOL, 8, 0, 31, 1, hp_tlv),
117 SOC_DOUBLE("Speaker Playback Switch",
118 ALC5623_SPK_OUT_VOL, 15, 7, 1, 1),
119 SOC_DOUBLE_TLV("Line Playback Volume",
120 ALC5623_HP_OUT_VOL, 8, 0, 31, 1, hp_tlv),
121 SOC_DOUBLE("Line Playback Switch",
122 ALC5623_HP_OUT_VOL, 15, 7, 1, 1),
123};
124
125static const struct snd_kcontrol_new alc5623_vol_snd_controls[] = {
126 SOC_DOUBLE_TLV("Line Playback Volume",
127 ALC5623_SPK_OUT_VOL, 8, 0, 31, 1, hp_tlv),
128 SOC_DOUBLE("Line Playback Switch",
129 ALC5623_SPK_OUT_VOL, 15, 7, 1, 1),
130 SOC_DOUBLE_TLV("Headphone Playback Volume",
131 ALC5623_HP_OUT_VOL, 8, 0, 31, 1, hp_tlv),
132 SOC_DOUBLE("Headphone Playback Switch",
133 ALC5623_HP_OUT_VOL, 15, 7, 1, 1),
134};
135
136static const struct snd_kcontrol_new alc5623_snd_controls[] = {
137 SOC_DOUBLE_TLV("Auxout Playback Volume",
138 ALC5623_MONO_AUX_OUT_VOL, 8, 0, 31, 1, hp_tlv),
139 SOC_DOUBLE("Auxout Playback Switch",
140 ALC5623_MONO_AUX_OUT_VOL, 15, 7, 1, 1),
141 SOC_DOUBLE_TLV("PCM Playback Volume",
142 ALC5623_STEREO_DAC_VOL, 8, 0, 31, 1, vol_tlv),
143 SOC_DOUBLE_TLV("AuxI Capture Volume",
144 ALC5623_AUXIN_VOL, 8, 0, 31, 1, vol_tlv),
145 SOC_DOUBLE_TLV("LineIn Capture Volume",
146 ALC5623_LINE_IN_VOL, 8, 0, 31, 1, vol_tlv),
147 SOC_SINGLE_TLV("Mic1 Capture Volume",
148 ALC5623_MIC_VOL, 8, 31, 1, vol_tlv),
149 SOC_SINGLE_TLV("Mic2 Capture Volume",
150 ALC5623_MIC_VOL, 0, 31, 1, vol_tlv),
151 SOC_DOUBLE_TLV("Rec Capture Volume",
152 ALC5623_ADC_REC_GAIN, 7, 0, 31, 0, adc_rec_tlv),
153 SOC_SINGLE_TLV("Mic 1 Boost Volume",
154 ALC5623_MIC_CTRL, 10, 2, 0, boost_tlv),
155 SOC_SINGLE_TLV("Mic 2 Boost Volume",
156 ALC5623_MIC_CTRL, 8, 2, 0, boost_tlv),
157 SOC_SINGLE_TLV("Digital Boost Volume",
158 ALC5623_ADD_CTRL_REG, 4, 3, 0, dig_tlv),
159};
160
161/*
162 * DAPM Controls
163 */
164static const struct snd_kcontrol_new alc5623_hp_mixer_controls[] = {
165SOC_DAPM_SINGLE("LI2HP Playback Switch", ALC5623_LINE_IN_VOL, 15, 1, 1),
166SOC_DAPM_SINGLE("AUXI2HP Playback Switch", ALC5623_AUXIN_VOL, 15, 1, 1),
167SOC_DAPM_SINGLE("MIC12HP Playback Switch", ALC5623_MIC_ROUTING_CTRL, 15, 1, 1),
168SOC_DAPM_SINGLE("MIC22HP Playback Switch", ALC5623_MIC_ROUTING_CTRL, 7, 1, 1),
169SOC_DAPM_SINGLE("DAC2HP Playback Switch", ALC5623_STEREO_DAC_VOL, 15, 1, 1),
170};
171
172static const struct snd_kcontrol_new alc5623_hpl_mixer_controls[] = {
173SOC_DAPM_SINGLE("ADC2HP_L Playback Switch", ALC5623_ADC_REC_GAIN, 15, 1, 1),
174};
175
176static const struct snd_kcontrol_new alc5623_hpr_mixer_controls[] = {
177SOC_DAPM_SINGLE("ADC2HP_R Playback Switch", ALC5623_ADC_REC_GAIN, 14, 1, 1),
178};
179
180static const struct snd_kcontrol_new alc5623_mono_mixer_controls[] = {
181SOC_DAPM_SINGLE("ADC2MONO_L Playback Switch", ALC5623_ADC_REC_GAIN, 13, 1, 1),
182SOC_DAPM_SINGLE("ADC2MONO_R Playback Switch", ALC5623_ADC_REC_GAIN, 12, 1, 1),
183SOC_DAPM_SINGLE("LI2MONO Playback Switch", ALC5623_LINE_IN_VOL, 13, 1, 1),
184SOC_DAPM_SINGLE("AUXI2MONO Playback Switch", ALC5623_AUXIN_VOL, 13, 1, 1),
185SOC_DAPM_SINGLE("MIC12MONO Playback Switch", ALC5623_MIC_ROUTING_CTRL, 13, 1, 1),
186SOC_DAPM_SINGLE("MIC22MONO Playback Switch", ALC5623_MIC_ROUTING_CTRL, 5, 1, 1),
187SOC_DAPM_SINGLE("DAC2MONO Playback Switch", ALC5623_STEREO_DAC_VOL, 13, 1, 1),
188};
189
190static const struct snd_kcontrol_new alc5623_speaker_mixer_controls[] = {
191SOC_DAPM_SINGLE("LI2SPK Playback Switch", ALC5623_LINE_IN_VOL, 14, 1, 1),
192SOC_DAPM_SINGLE("AUXI2SPK Playback Switch", ALC5623_AUXIN_VOL, 14, 1, 1),
193SOC_DAPM_SINGLE("MIC12SPK Playback Switch", ALC5623_MIC_ROUTING_CTRL, 14, 1, 1),
194SOC_DAPM_SINGLE("MIC22SPK Playback Switch", ALC5623_MIC_ROUTING_CTRL, 6, 1, 1),
195SOC_DAPM_SINGLE("DAC2SPK Playback Switch", ALC5623_STEREO_DAC_VOL, 14, 1, 1),
196};
197
198/* Left Record Mixer */
199static const struct snd_kcontrol_new alc5623_captureL_mixer_controls[] = {
200SOC_DAPM_SINGLE("Mic1 Capture Switch", ALC5623_ADC_REC_MIXER, 14, 1, 1),
201SOC_DAPM_SINGLE("Mic2 Capture Switch", ALC5623_ADC_REC_MIXER, 13, 1, 1),
202SOC_DAPM_SINGLE("LineInL Capture Switch", ALC5623_ADC_REC_MIXER, 12, 1, 1),
203SOC_DAPM_SINGLE("Left AuxI Capture Switch", ALC5623_ADC_REC_MIXER, 11, 1, 1),
204SOC_DAPM_SINGLE("HPMixerL Capture Switch", ALC5623_ADC_REC_MIXER, 10, 1, 1),
205SOC_DAPM_SINGLE("SPKMixer Capture Switch", ALC5623_ADC_REC_MIXER, 9, 1, 1),
206SOC_DAPM_SINGLE("MonoMixer Capture Switch", ALC5623_ADC_REC_MIXER, 8, 1, 1),
207};
208
209/* Right Record Mixer */
210static const struct snd_kcontrol_new alc5623_captureR_mixer_controls[] = {
211SOC_DAPM_SINGLE("Mic1 Capture Switch", ALC5623_ADC_REC_MIXER, 6, 1, 1),
212SOC_DAPM_SINGLE("Mic2 Capture Switch", ALC5623_ADC_REC_MIXER, 5, 1, 1),
213SOC_DAPM_SINGLE("LineInR Capture Switch", ALC5623_ADC_REC_MIXER, 4, 1, 1),
214SOC_DAPM_SINGLE("Right AuxI Capture Switch", ALC5623_ADC_REC_MIXER, 3, 1, 1),
215SOC_DAPM_SINGLE("HPMixerR Capture Switch", ALC5623_ADC_REC_MIXER, 2, 1, 1),
216SOC_DAPM_SINGLE("SPKMixer Capture Switch", ALC5623_ADC_REC_MIXER, 1, 1, 1),
217SOC_DAPM_SINGLE("MonoMixer Capture Switch", ALC5623_ADC_REC_MIXER, 0, 1, 1),
218};
219
220static const char *alc5623_spk_n_sour_sel[] = {
221 "RN/-R", "RP/+R", "LN/-R", "Vmid" };
222static const char *alc5623_hpl_out_input_sel[] = {
223 "Vmid", "HP Left Mix"};
224static const char *alc5623_hpr_out_input_sel[] = {
225 "Vmid", "HP Right Mix"};
226static const char *alc5623_spkout_input_sel[] = {
227 "Vmid", "HPOut Mix", "Speaker Mix", "Mono Mix"};
228static const char *alc5623_aux_out_input_sel[] = {
229 "Vmid", "HPOut Mix", "Speaker Mix", "Mono Mix"};
230
231/* auxout output mux */
232static const struct soc_enum alc5623_aux_out_input_enum =
233SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 6, 4, alc5623_aux_out_input_sel);
234static const struct snd_kcontrol_new alc5623_auxout_mux_controls =
235SOC_DAPM_ENUM("Route", alc5623_aux_out_input_enum);
236
237/* speaker output mux */
238static const struct soc_enum alc5623_spkout_input_enum =
239SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 10, 4, alc5623_spkout_input_sel);
240static const struct snd_kcontrol_new alc5623_spkout_mux_controls =
241SOC_DAPM_ENUM("Route", alc5623_spkout_input_enum);
242
243/* headphone left output mux */
244static const struct soc_enum alc5623_hpl_out_input_enum =
245SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 9, 2, alc5623_hpl_out_input_sel);
246static const struct snd_kcontrol_new alc5623_hpl_out_mux_controls =
247SOC_DAPM_ENUM("Route", alc5623_hpl_out_input_enum);
248
249/* headphone right output mux */
250static const struct soc_enum alc5623_hpr_out_input_enum =
251SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 8, 2, alc5623_hpr_out_input_sel);
252static const struct snd_kcontrol_new alc5623_hpr_out_mux_controls =
253SOC_DAPM_ENUM("Route", alc5623_hpr_out_input_enum);
254
255/* speaker output N select */
256static const struct soc_enum alc5623_spk_n_sour_enum =
257SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 14, 4, alc5623_spk_n_sour_sel);
258static const struct snd_kcontrol_new alc5623_spkoutn_mux_controls =
259SOC_DAPM_ENUM("Route", alc5623_spk_n_sour_enum);
260
261static const struct snd_soc_dapm_widget alc5623_dapm_widgets[] = {
262/* Muxes */
263SND_SOC_DAPM_MUX("AuxOut Mux", SND_SOC_NOPM, 0, 0,
264 &alc5623_auxout_mux_controls),
265SND_SOC_DAPM_MUX("SpeakerOut Mux", SND_SOC_NOPM, 0, 0,
266 &alc5623_spkout_mux_controls),
267SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0,
268 &alc5623_hpl_out_mux_controls),
269SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0,
270 &alc5623_hpr_out_mux_controls),
271SND_SOC_DAPM_MUX("SpeakerOut N Mux", SND_SOC_NOPM, 0, 0,
272 &alc5623_spkoutn_mux_controls),
273
274/* output mixers */
275SND_SOC_DAPM_MIXER("HP Mix", SND_SOC_NOPM, 0, 0,
276 &alc5623_hp_mixer_controls[0],
277 ARRAY_SIZE(alc5623_hp_mixer_controls)),
278SND_SOC_DAPM_MIXER("HPR Mix", ALC5623_PWR_MANAG_ADD2, 4, 0,
279 &alc5623_hpr_mixer_controls[0],
280 ARRAY_SIZE(alc5623_hpr_mixer_controls)),
281SND_SOC_DAPM_MIXER("HPL Mix", ALC5623_PWR_MANAG_ADD2, 5, 0,
282 &alc5623_hpl_mixer_controls[0],
283 ARRAY_SIZE(alc5623_hpl_mixer_controls)),
284SND_SOC_DAPM_MIXER("HPOut Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
285SND_SOC_DAPM_MIXER("Mono Mix", ALC5623_PWR_MANAG_ADD2, 2, 0,
286 &alc5623_mono_mixer_controls[0],
287 ARRAY_SIZE(alc5623_mono_mixer_controls)),
288SND_SOC_DAPM_MIXER("Speaker Mix", ALC5623_PWR_MANAG_ADD2, 3, 0,
289 &alc5623_speaker_mixer_controls[0],
290 ARRAY_SIZE(alc5623_speaker_mixer_controls)),
291
292/* input mixers */
293SND_SOC_DAPM_MIXER("Left Capture Mix", ALC5623_PWR_MANAG_ADD2, 1, 0,
294 &alc5623_captureL_mixer_controls[0],
295 ARRAY_SIZE(alc5623_captureL_mixer_controls)),
296SND_SOC_DAPM_MIXER("Right Capture Mix", ALC5623_PWR_MANAG_ADD2, 0, 0,
297 &alc5623_captureR_mixer_controls[0],
298 ARRAY_SIZE(alc5623_captureR_mixer_controls)),
299
300SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
301 ALC5623_PWR_MANAG_ADD2, 9, 0),
302SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
303 ALC5623_PWR_MANAG_ADD2, 8, 0),
304SND_SOC_DAPM_MIXER("I2S Mix", ALC5623_PWR_MANAG_ADD1, 15, 0, NULL, 0),
305SND_SOC_DAPM_MIXER("AuxI Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
306SND_SOC_DAPM_MIXER("Line Mix", SND_SOC_NOPM, 0, 0, NULL, 0),
307SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
308 ALC5623_PWR_MANAG_ADD2, 7, 0),
309SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
310 ALC5623_PWR_MANAG_ADD2, 6, 0),
311SND_SOC_DAPM_PGA("Left Headphone", ALC5623_PWR_MANAG_ADD3, 10, 0, NULL, 0),
312SND_SOC_DAPM_PGA("Right Headphone", ALC5623_PWR_MANAG_ADD3, 9, 0, NULL, 0),
313SND_SOC_DAPM_PGA("SpeakerOut", ALC5623_PWR_MANAG_ADD3, 12, 0, NULL, 0),
314SND_SOC_DAPM_PGA("Left AuxOut", ALC5623_PWR_MANAG_ADD3, 14, 0, NULL, 0),
315SND_SOC_DAPM_PGA("Right AuxOut", ALC5623_PWR_MANAG_ADD3, 13, 0, NULL, 0),
316SND_SOC_DAPM_PGA("Left LineIn", ALC5623_PWR_MANAG_ADD3, 7, 0, NULL, 0),
317SND_SOC_DAPM_PGA("Right LineIn", ALC5623_PWR_MANAG_ADD3, 6, 0, NULL, 0),
318SND_SOC_DAPM_PGA("Left AuxI", ALC5623_PWR_MANAG_ADD3, 5, 0, NULL, 0),
319SND_SOC_DAPM_PGA("Right AuxI", ALC5623_PWR_MANAG_ADD3, 4, 0, NULL, 0),
320SND_SOC_DAPM_PGA("MIC1 PGA", ALC5623_PWR_MANAG_ADD3, 3, 0, NULL, 0),
321SND_SOC_DAPM_PGA("MIC2 PGA", ALC5623_PWR_MANAG_ADD3, 2, 0, NULL, 0),
322SND_SOC_DAPM_PGA("MIC1 Pre Amp", ALC5623_PWR_MANAG_ADD3, 1, 0, NULL, 0),
323SND_SOC_DAPM_PGA("MIC2 Pre Amp", ALC5623_PWR_MANAG_ADD3, 0, 0, NULL, 0),
324SND_SOC_DAPM_MICBIAS("Mic Bias1", ALC5623_PWR_MANAG_ADD1, 11, 0),
325
326SND_SOC_DAPM_OUTPUT("AUXOUTL"),
327SND_SOC_DAPM_OUTPUT("AUXOUTR"),
328SND_SOC_DAPM_OUTPUT("HPL"),
329SND_SOC_DAPM_OUTPUT("HPR"),
330SND_SOC_DAPM_OUTPUT("SPKOUT"),
331SND_SOC_DAPM_OUTPUT("SPKOUTN"),
332SND_SOC_DAPM_INPUT("LINEINL"),
333SND_SOC_DAPM_INPUT("LINEINR"),
334SND_SOC_DAPM_INPUT("AUXINL"),
335SND_SOC_DAPM_INPUT("AUXINR"),
336SND_SOC_DAPM_INPUT("MIC1"),
337SND_SOC_DAPM_INPUT("MIC2"),
338SND_SOC_DAPM_VMID("Vmid"),
339};
340
341static const char *alc5623_amp_names[] = {"AB Amp", "D Amp"};
342static const struct soc_enum alc5623_amp_enum =
343 SOC_ENUM_SINGLE(ALC5623_OUTPUT_MIXER_CTRL, 13, 2, alc5623_amp_names);
344static const struct snd_kcontrol_new alc5623_amp_mux_controls =
345 SOC_DAPM_ENUM("Route", alc5623_amp_enum);
346
347static const struct snd_soc_dapm_widget alc5623_dapm_amp_widgets[] = {
348SND_SOC_DAPM_PGA_E("D Amp", ALC5623_PWR_MANAG_ADD2, 14, 0, NULL, 0,
349 amp_mixer_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
350SND_SOC_DAPM_PGA("AB Amp", ALC5623_PWR_MANAG_ADD2, 15, 0, NULL, 0),
351SND_SOC_DAPM_MUX("AB-D Amp Mux", SND_SOC_NOPM, 0, 0,
352 &alc5623_amp_mux_controls),
353};
354
355static const struct snd_soc_dapm_route intercon[] = {
356 /* virtual mixer - mixes left & right channels */
357 {"I2S Mix", NULL, "Left DAC"},
358 {"I2S Mix", NULL, "Right DAC"},
359 {"Line Mix", NULL, "Right LineIn"},
360 {"Line Mix", NULL, "Left LineIn"},
361 {"AuxI Mix", NULL, "Left AuxI"},
362 {"AuxI Mix", NULL, "Right AuxI"},
363 {"AUXOUTL", NULL, "Left AuxOut"},
364 {"AUXOUTR", NULL, "Right AuxOut"},
365
366 /* HP mixer */
367 {"HPL Mix", "ADC2HP_L Playback Switch", "Left Capture Mix"},
368 {"HPL Mix", NULL, "HP Mix"},
369 {"HPR Mix", "ADC2HP_R Playback Switch", "Right Capture Mix"},
370 {"HPR Mix", NULL, "HP Mix"},
371 {"HP Mix", "LI2HP Playback Switch", "Line Mix"},
372 {"HP Mix", "AUXI2HP Playback Switch", "AuxI Mix"},
373 {"HP Mix", "MIC12HP Playback Switch", "MIC1 PGA"},
374 {"HP Mix", "MIC22HP Playback Switch", "MIC2 PGA"},
375 {"HP Mix", "DAC2HP Playback Switch", "I2S Mix"},
376
377 /* speaker mixer */
378 {"Speaker Mix", "LI2SPK Playback Switch", "Line Mix"},
379 {"Speaker Mix", "AUXI2SPK Playback Switch", "AuxI Mix"},
380 {"Speaker Mix", "MIC12SPK Playback Switch", "MIC1 PGA"},
381 {"Speaker Mix", "MIC22SPK Playback Switch", "MIC2 PGA"},
382 {"Speaker Mix", "DAC2SPK Playback Switch", "I2S Mix"},
383
384 /* mono mixer */
385 {"Mono Mix", "ADC2MONO_L Playback Switch", "Left Capture Mix"},
386 {"Mono Mix", "ADC2MONO_R Playback Switch", "Right Capture Mix"},
387 {"Mono Mix", "LI2MONO Playback Switch", "Line Mix"},
388 {"Mono Mix", "AUXI2MONO Playback Switch", "AuxI Mix"},
389 {"Mono Mix", "MIC12MONO Playback Switch", "MIC1 PGA"},
390 {"Mono Mix", "MIC22MONO Playback Switch", "MIC2 PGA"},
391 {"Mono Mix", "DAC2MONO Playback Switch", "I2S Mix"},
392
393 /* Left record mixer */
394 {"Left Capture Mix", "LineInL Capture Switch", "LINEINL"},
395 {"Left Capture Mix", "Left AuxI Capture Switch", "AUXINL"},
396 {"Left Capture Mix", "Mic1 Capture Switch", "MIC1 Pre Amp"},
397 {"Left Capture Mix", "Mic2 Capture Switch", "MIC2 Pre Amp"},
398 {"Left Capture Mix", "HPMixerL Capture Switch", "HPL Mix"},
399 {"Left Capture Mix", "SPKMixer Capture Switch", "Speaker Mix"},
400 {"Left Capture Mix", "MonoMixer Capture Switch", "Mono Mix"},
401
402 /*Right record mixer */
403 {"Right Capture Mix", "LineInR Capture Switch", "LINEINR"},
404 {"Right Capture Mix", "Right AuxI Capture Switch", "AUXINR"},
405 {"Right Capture Mix", "Mic1 Capture Switch", "MIC1 Pre Amp"},
406 {"Right Capture Mix", "Mic2 Capture Switch", "MIC2 Pre Amp"},
407 {"Right Capture Mix", "HPMixerR Capture Switch", "HPR Mix"},
408 {"Right Capture Mix", "SPKMixer Capture Switch", "Speaker Mix"},
409 {"Right Capture Mix", "MonoMixer Capture Switch", "Mono Mix"},
410
411 /* headphone left mux */
412 {"Left Headphone Mux", "HP Left Mix", "HPL Mix"},
413 {"Left Headphone Mux", "Vmid", "Vmid"},
414
415 /* headphone right mux */
416 {"Right Headphone Mux", "HP Right Mix", "HPR Mix"},
417 {"Right Headphone Mux", "Vmid", "Vmid"},
418
419 /* speaker out mux */
420 {"SpeakerOut Mux", "Vmid", "Vmid"},
421 {"SpeakerOut Mux", "HPOut Mix", "HPOut Mix"},
422 {"SpeakerOut Mux", "Speaker Mix", "Speaker Mix"},
423 {"SpeakerOut Mux", "Mono Mix", "Mono Mix"},
424
425 /* Mono/Aux Out mux */
426 {"AuxOut Mux", "Vmid", "Vmid"},
427 {"AuxOut Mux", "HPOut Mix", "HPOut Mix"},
428 {"AuxOut Mux", "Speaker Mix", "Speaker Mix"},
429 {"AuxOut Mux", "Mono Mix", "Mono Mix"},
430
431 /* output pga */
432 {"HPL", NULL, "Left Headphone"},
433 {"Left Headphone", NULL, "Left Headphone Mux"},
434 {"HPR", NULL, "Right Headphone"},
435 {"Right Headphone", NULL, "Right Headphone Mux"},
436 {"Left AuxOut", NULL, "AuxOut Mux"},
437 {"Right AuxOut", NULL, "AuxOut Mux"},
438
439 /* input pga */
440 {"Left LineIn", NULL, "LINEINL"},
441 {"Right LineIn", NULL, "LINEINR"},
442 {"Left AuxI", NULL, "AUXINL"},
443 {"Right AuxI", NULL, "AUXINR"},
444 {"MIC1 Pre Amp", NULL, "MIC1"},
445 {"MIC2 Pre Amp", NULL, "MIC2"},
446 {"MIC1 PGA", NULL, "MIC1 Pre Amp"},
447 {"MIC2 PGA", NULL, "MIC2 Pre Amp"},
448
449 /* left ADC */
450 {"Left ADC", NULL, "Left Capture Mix"},
451
452 /* right ADC */
453 {"Right ADC", NULL, "Right Capture Mix"},
454
455 {"SpeakerOut N Mux", "RN/-R", "SpeakerOut"},
456 {"SpeakerOut N Mux", "RP/+R", "SpeakerOut"},
457 {"SpeakerOut N Mux", "LN/-R", "SpeakerOut"},
458 {"SpeakerOut N Mux", "Vmid", "Vmid"},
459
460 {"SPKOUT", NULL, "SpeakerOut"},
461 {"SPKOUTN", NULL, "SpeakerOut N Mux"},
462};
463
464static const struct snd_soc_dapm_route intercon_spk[] = {
465 {"SpeakerOut", NULL, "SpeakerOut Mux"},
466};
467
468static const struct snd_soc_dapm_route intercon_amp_spk[] = {
469 {"AB Amp", NULL, "SpeakerOut Mux"},
470 {"D Amp", NULL, "SpeakerOut Mux"},
471 {"AB-D Amp Mux", "AB Amp", "AB Amp"},
472 {"AB-D Amp Mux", "D Amp", "D Amp"},
473 {"SpeakerOut", NULL, "AB-D Amp Mux"},
474};
475
476/* PLL divisors */
477struct _pll_div {
478 u32 pll_in;
479 u32 pll_out;
480 u16 regvalue;
481};
482
483/* Note : pll code from original alc5623 driver. Not sure of how good it is */
484/* usefull only for master mode */
485static const struct _pll_div codec_master_pll_div[] = {
486
487 { 2048000, 8192000, 0x0ea0},
488 { 3686400, 8192000, 0x4e27},
489 { 12000000, 8192000, 0x456b},
490 { 13000000, 8192000, 0x495f},
491 { 13100000, 8192000, 0x0320},
492 { 2048000, 11289600, 0xf637},
493 { 3686400, 11289600, 0x2f22},
494 { 12000000, 11289600, 0x3e2f},
495 { 13000000, 11289600, 0x4d5b},
496 { 13100000, 11289600, 0x363b},
497 { 2048000, 16384000, 0x1ea0},
498 { 3686400, 16384000, 0x9e27},
499 { 12000000, 16384000, 0x452b},
500 { 13000000, 16384000, 0x542f},
501 { 13100000, 16384000, 0x03a0},
502 { 2048000, 16934400, 0xe625},
503 { 3686400, 16934400, 0x9126},
504 { 12000000, 16934400, 0x4d2c},
505 { 13000000, 16934400, 0x742f},
506 { 13100000, 16934400, 0x3c27},
507 { 2048000, 22579200, 0x2aa0},
508 { 3686400, 22579200, 0x2f20},
509 { 12000000, 22579200, 0x7e2f},
510 { 13000000, 22579200, 0x742f},
511 { 13100000, 22579200, 0x3c27},
512 { 2048000, 24576000, 0x2ea0},
513 { 3686400, 24576000, 0xee27},
514 { 12000000, 24576000, 0x2915},
515 { 13000000, 24576000, 0x772e},
516 { 13100000, 24576000, 0x0d20},
517};
518
519static const struct _pll_div codec_slave_pll_div[] = {
520
521 { 1024000, 16384000, 0x3ea0},
522 { 1411200, 22579200, 0x3ea0},
523 { 1536000, 24576000, 0x3ea0},
524 { 2048000, 16384000, 0x1ea0},
525 { 2822400, 22579200, 0x1ea0},
526 { 3072000, 24576000, 0x1ea0},
527
528};
529
530static int alc5623_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
531 int source, unsigned int freq_in, unsigned int freq_out)
532{
533 int i;
534 struct snd_soc_codec *codec = codec_dai->codec;
535 int gbl_clk = 0, pll_div = 0;
536 u16 reg;
537
538 if (pll_id < ALC5623_PLL_FR_MCLK || pll_id > ALC5623_PLL_FR_BCK)
539 return -ENODEV;
540
541 /* Disable PLL power */
542 snd_soc_update_bits(codec, ALC5623_PWR_MANAG_ADD2,
543 ALC5623_PWR_ADD2_PLL,
544 0);
545
546 /* pll is not used in slave mode */
547 reg = snd_soc_read(codec, ALC5623_DAI_CONTROL);
548 if (reg & ALC5623_DAI_SDP_SLAVE_MODE)
549 return 0;
550
551 if (!freq_in || !freq_out)
552 return 0;
553
554 switch (pll_id) {
555 case ALC5623_PLL_FR_MCLK:
556 for (i = 0; i < ARRAY_SIZE(codec_master_pll_div); i++) {
557 if (codec_master_pll_div[i].pll_in == freq_in
558 && codec_master_pll_div[i].pll_out == freq_out) {
559 /* PLL source from MCLK */
560 pll_div = codec_master_pll_div[i].regvalue;
561 break;
562 }
563 }
564 break;
565 case ALC5623_PLL_FR_BCK:
566 for (i = 0; i < ARRAY_SIZE(codec_slave_pll_div); i++) {
567 if (codec_slave_pll_div[i].pll_in == freq_in
568 && codec_slave_pll_div[i].pll_out == freq_out) {
569 /* PLL source from Bitclk */
570 gbl_clk = ALC5623_GBL_CLK_PLL_SOUR_SEL_BITCLK;
571 pll_div = codec_slave_pll_div[i].regvalue;
572 break;
573 }
574 }
575 break;
576 default:
577 return -EINVAL;
578 }
579
580 if (!pll_div)
581 return -EINVAL;
582
583 snd_soc_write(codec, ALC5623_GLOBAL_CLK_CTRL_REG, gbl_clk);
584 snd_soc_write(codec, ALC5623_PLL_CTRL, pll_div);
585 snd_soc_update_bits(codec, ALC5623_PWR_MANAG_ADD2,
586 ALC5623_PWR_ADD2_PLL,
587 ALC5623_PWR_ADD2_PLL);
588 gbl_clk |= ALC5623_GBL_CLK_SYS_SOUR_SEL_PLL;
589 snd_soc_write(codec, ALC5623_GLOBAL_CLK_CTRL_REG, gbl_clk);
590
591 return 0;
592}
593
594struct _coeff_div {
595 u16 fs;
596 u16 regvalue;
597};
598
599/* codec hifi mclk (after PLL) clock divider coefficients */
600/* values inspired from column BCLK=32Fs of Appendix A table */
601static const struct _coeff_div coeff_div[] = {
602 {256*8, 0x3a69},
603 {384*8, 0x3c6b},
604 {256*4, 0x2a69},
605 {384*4, 0x2c6b},
606 {256*2, 0x1a69},
607 {384*2, 0x1c6b},
608 {256*1, 0x0a69},
609 {384*1, 0x0c6b},
610};
611
612static int get_coeff(struct snd_soc_codec *codec, int rate)
613{
614 struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec);
615 int i;
616
617 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
618 if (coeff_div[i].fs * rate == alc5623->sysclk)
619 return i;
620 }
621 return -EINVAL;
622}
623
624/*
625 * Clock after PLL and dividers
626 */
627static int alc5623_set_dai_sysclk(struct snd_soc_dai *codec_dai,
628 int clk_id, unsigned int freq, int dir)
629{
630 struct snd_soc_codec *codec = codec_dai->codec;
631 struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec);
632
633 switch (freq) {
634 case 8192000:
635 case 11289600:
636 case 12288000:
637 case 16384000:
638 case 16934400:
639 case 18432000:
640 case 22579200:
641 case 24576000:
642 alc5623->sysclk = freq;
643 return 0;
644 }
645 return -EINVAL;
646}
647
648static int alc5623_set_dai_fmt(struct snd_soc_dai *codec_dai,
649 unsigned int fmt)
650{
651 struct snd_soc_codec *codec = codec_dai->codec;
652 u16 iface = 0;
653
654 /* set master/slave audio interface */
655 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
656 case SND_SOC_DAIFMT_CBM_CFM:
657 iface = ALC5623_DAI_SDP_MASTER_MODE;
658 break;
659 case SND_SOC_DAIFMT_CBS_CFS:
660 iface = ALC5623_DAI_SDP_SLAVE_MODE;
661 break;
662 default:
663 return -EINVAL;
664 }
665
666 /* interface format */
667 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
668 case SND_SOC_DAIFMT_I2S:
669 iface |= ALC5623_DAI_I2S_DF_I2S;
670 break;
671 case SND_SOC_DAIFMT_RIGHT_J:
672 iface |= ALC5623_DAI_I2S_DF_RIGHT;
673 break;
674 case SND_SOC_DAIFMT_LEFT_J:
675 iface |= ALC5623_DAI_I2S_DF_LEFT;
676 break;
677 case SND_SOC_DAIFMT_DSP_A:
678 iface |= ALC5623_DAI_I2S_DF_PCM;
679 break;
680 case SND_SOC_DAIFMT_DSP_B:
681 iface |= ALC5623_DAI_I2S_DF_PCM | ALC5623_DAI_I2S_PCM_MODE;
682 break;
683 default:
684 return -EINVAL;
685 }
686
687 /* clock inversion */
688 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
689 case SND_SOC_DAIFMT_NB_NF:
690 break;
691 case SND_SOC_DAIFMT_IB_IF:
692 iface |= ALC5623_DAI_MAIN_I2S_BCLK_POL_CTRL;
693 break;
694 case SND_SOC_DAIFMT_IB_NF:
695 iface |= ALC5623_DAI_MAIN_I2S_BCLK_POL_CTRL;
696 break;
697 case SND_SOC_DAIFMT_NB_IF:
698 break;
699 default:
700 return -EINVAL;
701 }
702
703 return snd_soc_write(codec, ALC5623_DAI_CONTROL, iface);
704}
705
706static int alc5623_pcm_hw_params(struct snd_pcm_substream *substream,
707 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
708{
709 struct snd_soc_pcm_runtime *rtd = substream->private_data;
710 struct snd_soc_codec *codec = rtd->codec;
711 struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec);
712 int coeff, rate;
713 u16 iface;
714
715 iface = snd_soc_read(codec, ALC5623_DAI_CONTROL);
716 iface &= ~ALC5623_DAI_I2S_DL_MASK;
717
718 /* bit size */
719 switch (params_format(params)) {
720 case SNDRV_PCM_FORMAT_S16_LE:
721 iface |= ALC5623_DAI_I2S_DL_16;
722 break;
723 case SNDRV_PCM_FORMAT_S20_3LE:
724 iface |= ALC5623_DAI_I2S_DL_20;
725 break;
726 case SNDRV_PCM_FORMAT_S24_LE:
727 iface |= ALC5623_DAI_I2S_DL_24;
728 break;
729 case SNDRV_PCM_FORMAT_S32_LE:
730 iface |= ALC5623_DAI_I2S_DL_32;
731 break;
732 default:
733 return -EINVAL;
734 }
735
736 /* set iface & srate */
737 snd_soc_write(codec, ALC5623_DAI_CONTROL, iface);
738 rate = params_rate(params);
739 coeff = get_coeff(codec, rate);
740 if (coeff < 0)
741 return -EINVAL;
742
743 coeff = coeff_div[coeff].regvalue;
744 dev_dbg(codec->dev, "%s: sysclk=%d,rate=%d,coeff=0x%04x\n",
745 __func__, alc5623->sysclk, rate, coeff);
746 snd_soc_write(codec, ALC5623_STEREO_AD_DA_CLK_CTRL, coeff);
747
748 return 0;
749}
750
751static int alc5623_mute(struct snd_soc_dai *dai, int mute)
752{
753 struct snd_soc_codec *codec = dai->codec;
754 u16 hp_mute = ALC5623_MISC_M_DAC_L_INPUT | ALC5623_MISC_M_DAC_R_INPUT;
755 u16 mute_reg = snd_soc_read(codec, ALC5623_MISC_CTRL) & ~hp_mute;
756
757 if (mute)
758 mute_reg |= hp_mute;
759
760 return snd_soc_write(codec, ALC5623_MISC_CTRL, mute_reg);
761}
762
763#define ALC5623_ADD2_POWER_EN (ALC5623_PWR_ADD2_VREF \
764 | ALC5623_PWR_ADD2_DAC_REF_CIR)
765
766#define ALC5623_ADD3_POWER_EN (ALC5623_PWR_ADD3_MAIN_BIAS \
767 | ALC5623_PWR_ADD3_MIC1_BOOST_AD)
768
769#define ALC5623_ADD1_POWER_EN \
770 (ALC5623_PWR_ADD1_SHORT_CURR_DET_EN | ALC5623_PWR_ADD1_SOFTGEN_EN \
771 | ALC5623_PWR_ADD1_DEPOP_BUF_HP | ALC5623_PWR_ADD1_HP_OUT_AMP \
772 | ALC5623_PWR_ADD1_HP_OUT_ENH_AMP)
773
774#define ALC5623_ADD1_POWER_EN_5622 \
775 (ALC5623_PWR_ADD1_SHORT_CURR_DET_EN \
776 | ALC5623_PWR_ADD1_HP_OUT_AMP)
777
778static void enable_power_depop(struct snd_soc_codec *codec)
779{
780 struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec);
781
782 snd_soc_update_bits(codec, ALC5623_PWR_MANAG_ADD1,
783 ALC5623_PWR_ADD1_SOFTGEN_EN,
784 ALC5623_PWR_ADD1_SOFTGEN_EN);
785
786 snd_soc_write(codec, ALC5623_PWR_MANAG_ADD3, ALC5623_ADD3_POWER_EN);
787
788 snd_soc_update_bits(codec, ALC5623_MISC_CTRL,
789 ALC5623_MISC_HP_DEPOP_MODE2_EN,
790 ALC5623_MISC_HP_DEPOP_MODE2_EN);
791
792 msleep(500);
793
794 snd_soc_write(codec, ALC5623_PWR_MANAG_ADD2, ALC5623_ADD2_POWER_EN);
795
796 /* avoid writing '1' into 5622 reserved bits */
797 if (alc5623->id == 0x22)
798 snd_soc_write(codec, ALC5623_PWR_MANAG_ADD1,
799 ALC5623_ADD1_POWER_EN_5622);
800 else
801 snd_soc_write(codec, ALC5623_PWR_MANAG_ADD1,
802 ALC5623_ADD1_POWER_EN);
803
804 /* disable HP Depop2 */
805 snd_soc_update_bits(codec, ALC5623_MISC_CTRL,
806 ALC5623_MISC_HP_DEPOP_MODE2_EN,
807 0);
808
809}
810
811static int alc5623_set_bias_level(struct snd_soc_codec *codec,
812 enum snd_soc_bias_level level)
813{
814 switch (level) {
815 case SND_SOC_BIAS_ON:
816 enable_power_depop(codec);
817 break;
818 case SND_SOC_BIAS_PREPARE:
819 break;
820 case SND_SOC_BIAS_STANDBY:
821 /* everything off except vref/vmid, */
822 snd_soc_write(codec, ALC5623_PWR_MANAG_ADD2,
823 ALC5623_PWR_ADD2_VREF);
824 snd_soc_write(codec, ALC5623_PWR_MANAG_ADD3,
825 ALC5623_PWR_ADD3_MAIN_BIAS);
826 break;
827 case SND_SOC_BIAS_OFF:
828 /* everything off, dac mute, inactive */
829 snd_soc_write(codec, ALC5623_PWR_MANAG_ADD2, 0);
830 snd_soc_write(codec, ALC5623_PWR_MANAG_ADD3, 0);
831 snd_soc_write(codec, ALC5623_PWR_MANAG_ADD1, 0);
832 break;
833 }
834 codec->dapm.bias_level = level;
835 return 0;
836}
837
838#define ALC5623_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \
839 | SNDRV_PCM_FMTBIT_S24_LE \
840 | SNDRV_PCM_FMTBIT_S32_LE)
841
842static struct snd_soc_dai_ops alc5623_dai_ops = {
843 .hw_params = alc5623_pcm_hw_params,
844 .digital_mute = alc5623_mute,
845 .set_fmt = alc5623_set_dai_fmt,
846 .set_sysclk = alc5623_set_dai_sysclk,
847 .set_pll = alc5623_set_dai_pll,
848};
849
850static struct snd_soc_dai_driver alc5623_dai = {
851 .name = "alc5623-hifi",
852 .playback = {
853 .stream_name = "Playback",
854 .channels_min = 1,
855 .channels_max = 2,
856 .rate_min = 8000,
857 .rate_max = 48000,
858 .rates = SNDRV_PCM_RATE_8000_48000,
859 .formats = ALC5623_FORMATS,},
860 .capture = {
861 .stream_name = "Capture",
862 .channels_min = 1,
863 .channels_max = 2,
864 .rate_min = 8000,
865 .rate_max = 48000,
866 .rates = SNDRV_PCM_RATE_8000_48000,
867 .formats = ALC5623_FORMATS,},
868
869 .ops = &alc5623_dai_ops,
870};
871
872static int alc5623_suspend(struct snd_soc_codec *codec, pm_message_t mesg)
873{
874 alc5623_set_bias_level(codec, SND_SOC_BIAS_OFF);
875 return 0;
876}
877
878static int alc5623_resume(struct snd_soc_codec *codec)
879{
880 int i, step = codec->driver->reg_cache_step;
881 u16 *cache = codec->reg_cache;
882
883 /* Sync reg_cache with the hardware */
884 for (i = 2 ; i < codec->driver->reg_cache_size ; i += step)
885 snd_soc_write(codec, i, cache[i]);
886
887 alc5623_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
888
889 /* charge alc5623 caps */
890 if (codec->dapm.suspend_bias_level == SND_SOC_BIAS_ON) {
891 alc5623_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
892 codec->dapm.bias_level = SND_SOC_BIAS_ON;
893 alc5623_set_bias_level(codec, codec->dapm.bias_level);
894 }
895
896 return 0;
897}
898
899static int alc5623_probe(struct snd_soc_codec *codec)
900{
901 struct alc5623_priv *alc5623 = snd_soc_codec_get_drvdata(codec);
902 struct snd_soc_dapm_context *dapm = &codec->dapm;
903 int ret;
904
905 ret = snd_soc_codec_set_cache_io(codec, 8, 16, alc5623->control_type);
906 if (ret < 0) {
907 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
908 return ret;
909 }
910
911 alc5623_reset(codec);
912 alc5623_fill_cache(codec);
913
914 /* power on device */
915 alc5623_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
916
917 if (alc5623->add_ctrl) {
918 snd_soc_write(codec, ALC5623_ADD_CTRL_REG,
919 alc5623->add_ctrl);
920 }
921
922 if (alc5623->jack_det_ctrl) {
923 snd_soc_write(codec, ALC5623_JACK_DET_CTRL,
924 alc5623->jack_det_ctrl);
925 }
926
927 switch (alc5623->id) {
928 case 0x21:
929 snd_soc_add_controls(codec, rt5621_vol_snd_controls,
930 ARRAY_SIZE(rt5621_vol_snd_controls));
931 break;
932 case 0x22:
933 snd_soc_add_controls(codec, rt5622_vol_snd_controls,
934 ARRAY_SIZE(rt5622_vol_snd_controls));
935 break;
936 case 0x23:
937 snd_soc_add_controls(codec, alc5623_vol_snd_controls,
938 ARRAY_SIZE(alc5623_vol_snd_controls));
939 break;
940 default:
941 return -EINVAL;
942 }
943
944 snd_soc_add_controls(codec, alc5623_snd_controls,
945 ARRAY_SIZE(alc5623_snd_controls));
946
947 snd_soc_dapm_new_controls(dapm, alc5623_dapm_widgets,
948 ARRAY_SIZE(alc5623_dapm_widgets));
949
950 /* set up audio path interconnects */
951 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
952
953 switch (alc5623->id) {
954 case 0x21:
955 case 0x22:
956 snd_soc_dapm_new_controls(dapm, alc5623_dapm_amp_widgets,
957 ARRAY_SIZE(alc5623_dapm_amp_widgets));
958 snd_soc_dapm_add_routes(dapm, intercon_amp_spk,
959 ARRAY_SIZE(intercon_amp_spk));
960 break;
961 case 0x23:
962 snd_soc_dapm_add_routes(dapm, intercon_spk,
963 ARRAY_SIZE(intercon_spk));
964 break;
965 default:
966 return -EINVAL;
967 }
968
969 return ret;
970}
971
972/* power down chip */
973static int alc5623_remove(struct snd_soc_codec *codec)
974{
975 alc5623_set_bias_level(codec, SND_SOC_BIAS_OFF);
976 return 0;
977}
978
979static struct snd_soc_codec_driver soc_codec_device_alc5623 = {
980 .probe = alc5623_probe,
981 .remove = alc5623_remove,
982 .suspend = alc5623_suspend,
983 .resume = alc5623_resume,
984 .set_bias_level = alc5623_set_bias_level,
985 .reg_cache_size = ALC5623_VENDOR_ID2+2,
986 .reg_word_size = sizeof(u16),
987 .reg_cache_step = 2,
988};
989
990/*
991 * ALC5623 2 wire address is determined by A1 pin
992 * state during powerup.
993 * low = 0x1a
994 * high = 0x1b
995 */
996static int alc5623_i2c_probe(struct i2c_client *client,
997 const struct i2c_device_id *id)
998{
999 struct alc5623_platform_data *pdata;
1000 struct alc5623_priv *alc5623;
1001 int ret, vid1, vid2;
1002
1003 vid1 = i2c_smbus_read_word_data(client, ALC5623_VENDOR_ID1);
1004 if (vid1 < 0) {
1005 dev_err(&client->dev, "failed to read I2C\n");
1006 return -EIO;
1007 }
1008 vid1 = ((vid1 & 0xff) << 8) | (vid1 >> 8);
1009
1010 vid2 = i2c_smbus_read_byte_data(client, ALC5623_VENDOR_ID2);
1011 if (vid2 < 0) {
1012 dev_err(&client->dev, "failed to read I2C\n");
1013 return -EIO;
1014 }
1015
1016 if ((vid1 != 0x10ec) || (vid2 != id->driver_data)) {
1017 dev_err(&client->dev, "unknown or wrong codec\n");
1018 dev_err(&client->dev, "Expected %x:%lx, got %x:%x\n",
1019 0x10ec, id->driver_data,
1020 vid1, vid2);
1021 return -ENODEV;
1022 }
1023
1024 dev_dbg(&client->dev, "Found codec id : alc56%02x\n", vid2);
1025
1026 alc5623 = kzalloc(sizeof(struct alc5623_priv), GFP_KERNEL);
1027 if (alc5623 == NULL)
1028 return -ENOMEM;
1029
1030 pdata = client->dev.platform_data;
1031 if (pdata) {
1032 alc5623->add_ctrl = pdata->add_ctrl;
1033 alc5623->jack_det_ctrl = pdata->jack_det_ctrl;
1034 }
1035
1036 alc5623->id = vid2;
1037 switch (alc5623->id) {
1038 case 0x21:
1039 alc5623_dai.name = "alc5621-hifi";
1040 break;
1041 case 0x22:
1042 alc5623_dai.name = "alc5622-hifi";
1043 break;
1044 case 0x23:
1045 alc5623_dai.name = "alc5623-hifi";
1046 break;
1047 default:
1048 kfree(alc5623);
1049 return -EINVAL;
1050 }
1051
1052 i2c_set_clientdata(client, alc5623);
1053 alc5623->control_data = client;
1054 alc5623->control_type = SND_SOC_I2C;
1055 mutex_init(&alc5623->mutex);
1056
1057 ret = snd_soc_register_codec(&client->dev,
1058 &soc_codec_device_alc5623, &alc5623_dai, 1);
1059 if (ret != 0) {
1060 dev_err(&client->dev, "Failed to register codec: %d\n", ret);
1061 kfree(alc5623);
1062 }
1063
1064 return ret;
1065}
1066
1067static int alc5623_i2c_remove(struct i2c_client *client)
1068{
1069 struct alc5623_priv *alc5623 = i2c_get_clientdata(client);
1070
1071 snd_soc_unregister_codec(&client->dev);
1072 kfree(alc5623);
1073 return 0;
1074}
1075
1076static const struct i2c_device_id alc5623_i2c_table[] = {
1077 {"alc5621", 0x21},
1078 {"alc5622", 0x22},
1079 {"alc5623", 0x23},
1080 {}
1081};
1082MODULE_DEVICE_TABLE(i2c, alc5623_i2c_table);
1083
1084/* i2c codec control layer */
1085static struct i2c_driver alc5623_i2c_driver = {
1086 .driver = {
1087 .name = "alc562x-codec",
1088 .owner = THIS_MODULE,
1089 },
1090 .probe = alc5623_i2c_probe,
1091 .remove = __devexit_p(alc5623_i2c_remove),
1092 .id_table = alc5623_i2c_table,
1093};
1094
1095static int __init alc5623_modinit(void)
1096{
1097 int ret;
1098
1099 ret = i2c_add_driver(&alc5623_i2c_driver);
1100 if (ret != 0) {
1101 printk(KERN_ERR "%s: can't add i2c driver", __func__);
1102 return ret;
1103 }
1104
1105 return ret;
1106}
1107module_init(alc5623_modinit);
1108
1109static void __exit alc5623_modexit(void)
1110{
1111 i2c_del_driver(&alc5623_i2c_driver);
1112}
1113module_exit(alc5623_modexit);
1114
1115MODULE_DESCRIPTION("ASoC alc5621/2/3 driver");
1116MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
1117MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/alc5623.h b/sound/soc/codecs/alc5623.h
new file mode 100644
index 000000000000..f3d68260d425
--- /dev/null
+++ b/sound/soc/codecs/alc5623.h
@@ -0,0 +1,161 @@
1/*
2 * alc5623.h -- alc562[123] ALSA Soc Audio driver
3 *
4 * Copyright 2008 Realtek Microelectronics
5 * Copyright 2010 Arnaud Patard <arnaud.patard@rtp-net.org>
6 *
7 * Author: flove <flove@realtek.com>
8 * Arnaud Patard <arnaud.patard@rtp-net.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16#ifndef _ALC5623_H
17#define _ALC5623_H
18
19#define ALC5623_RESET 0x00
20/* 5621 5622 5623 */
21/* speaker output vol 2 2 */
22/* line output vol 4 2 */
23/* HP output vol 4 0 4 */
24#define ALC5623_SPK_OUT_VOL 0x02
25#define ALC5623_HP_OUT_VOL 0x04
26#define ALC5623_MONO_AUX_OUT_VOL 0x06
27#define ALC5623_AUXIN_VOL 0x08
28#define ALC5623_LINE_IN_VOL 0x0A
29#define ALC5623_STEREO_DAC_VOL 0x0C
30#define ALC5623_MIC_VOL 0x0E
31#define ALC5623_MIC_ROUTING_CTRL 0x10
32#define ALC5623_ADC_REC_GAIN 0x12
33#define ALC5623_ADC_REC_MIXER 0x14
34#define ALC5623_SOFT_VOL_CTRL_TIME 0x16
35/* ALC5623_OUTPUT_MIXER_CTRL : */
36/* same remark as for reg 2 line vs speaker */
37#define ALC5623_OUTPUT_MIXER_CTRL 0x1C
38#define ALC5623_MIC_CTRL 0x22
39
40#define ALC5623_DAI_CONTROL 0x34
41#define ALC5623_DAI_SDP_MASTER_MODE (0 << 15)
42#define ALC5623_DAI_SDP_SLAVE_MODE (1 << 15)
43#define ALC5623_DAI_I2S_PCM_MODE (1 << 14)
44#define ALC5623_DAI_MAIN_I2S_BCLK_POL_CTRL (1 << 7)
45#define ALC5623_DAI_ADC_DATA_L_R_SWAP (1 << 5)
46#define ALC5623_DAI_DAC_DATA_L_R_SWAP (1 << 4)
47#define ALC5623_DAI_I2S_DL_MASK (3 << 2)
48#define ALC5623_DAI_I2S_DL_32 (3 << 2)
49#define ALC5623_DAI_I2S_DL_24 (2 << 2)
50#define ALC5623_DAI_I2S_DL_20 (1 << 2)
51#define ALC5623_DAI_I2S_DL_16 (0 << 2)
52#define ALC5623_DAI_I2S_DF_PCM (3 << 0)
53#define ALC5623_DAI_I2S_DF_LEFT (2 << 0)
54#define ALC5623_DAI_I2S_DF_RIGHT (1 << 0)
55#define ALC5623_DAI_I2S_DF_I2S (0 << 0)
56
57#define ALC5623_STEREO_AD_DA_CLK_CTRL 0x36
58#define ALC5623_COMPANDING_CTRL 0x38
59
60#define ALC5623_PWR_MANAG_ADD1 0x3A
61#define ALC5623_PWR_ADD1_MAIN_I2S_EN (1 << 15)
62#define ALC5623_PWR_ADD1_ZC_DET_PD_EN (1 << 14)
63#define ALC5623_PWR_ADD1_MIC1_BIAS_EN (1 << 11)
64#define ALC5623_PWR_ADD1_SHORT_CURR_DET_EN (1 << 10)
65#define ALC5623_PWR_ADD1_SOFTGEN_EN (1 << 8) /* rsvd on 5622 */
66#define ALC5623_PWR_ADD1_DEPOP_BUF_HP (1 << 6) /* rsvd on 5622 */
67#define ALC5623_PWR_ADD1_HP_OUT_AMP (1 << 5)
68#define ALC5623_PWR_ADD1_HP_OUT_ENH_AMP (1 << 4) /* rsvd on 5622 */
69#define ALC5623_PWR_ADD1_DEPOP_BUF_AUX (1 << 2)
70#define ALC5623_PWR_ADD1_AUX_OUT_AMP (1 << 1)
71#define ALC5623_PWR_ADD1_AUX_OUT_ENH_AMP (1 << 0) /* rsvd on 5622 */
72
73#define ALC5623_PWR_MANAG_ADD2 0x3C
74#define ALC5623_PWR_ADD2_LINEOUT (1 << 15) /* rt5623 */
75#define ALC5623_PWR_ADD2_CLASS_AB (1 << 15) /* rt5621 */
76#define ALC5623_PWR_ADD2_CLASS_D (1 << 14) /* rt5621 */
77#define ALC5623_PWR_ADD2_VREF (1 << 13)
78#define ALC5623_PWR_ADD2_PLL (1 << 12)
79#define ALC5623_PWR_ADD2_DAC_REF_CIR (1 << 10)
80#define ALC5623_PWR_ADD2_L_DAC_CLK (1 << 9)
81#define ALC5623_PWR_ADD2_R_DAC_CLK (1 << 8)
82#define ALC5623_PWR_ADD2_L_ADC_CLK_GAIN (1 << 7)
83#define ALC5623_PWR_ADD2_R_ADC_CLK_GAIN (1 << 6)
84#define ALC5623_PWR_ADD2_L_HP_MIXER (1 << 5)
85#define ALC5623_PWR_ADD2_R_HP_MIXER (1 << 4)
86#define ALC5623_PWR_ADD2_SPK_MIXER (1 << 3)
87#define ALC5623_PWR_ADD2_MONO_MIXER (1 << 2)
88#define ALC5623_PWR_ADD2_L_ADC_REC_MIXER (1 << 1)
89#define ALC5623_PWR_ADD2_R_ADC_REC_MIXER (1 << 0)
90
91#define ALC5623_PWR_MANAG_ADD3 0x3E
92#define ALC5623_PWR_ADD3_MAIN_BIAS (1 << 15)
93#define ALC5623_PWR_ADD3_AUXOUT_L_VOL_AMP (1 << 14)
94#define ALC5623_PWR_ADD3_AUXOUT_R_VOL_AMP (1 << 13)
95#define ALC5623_PWR_ADD3_SPK_OUT (1 << 12)
96#define ALC5623_PWR_ADD3_HP_L_OUT_VOL (1 << 10)
97#define ALC5623_PWR_ADD3_HP_R_OUT_VOL (1 << 9)
98#define ALC5623_PWR_ADD3_LINEIN_L_VOL (1 << 7)
99#define ALC5623_PWR_ADD3_LINEIN_R_VOL (1 << 6)
100#define ALC5623_PWR_ADD3_AUXIN_L_VOL (1 << 5)
101#define ALC5623_PWR_ADD3_AUXIN_R_VOL (1 << 4)
102#define ALC5623_PWR_ADD3_MIC1_FUN_CTRL (1 << 3)
103#define ALC5623_PWR_ADD3_MIC2_FUN_CTRL (1 << 2)
104#define ALC5623_PWR_ADD3_MIC1_BOOST_AD (1 << 1)
105#define ALC5623_PWR_ADD3_MIC2_BOOST_AD (1 << 0)
106
107#define ALC5623_ADD_CTRL_REG 0x40
108
109#define ALC5623_GLOBAL_CLK_CTRL_REG 0x42
110#define ALC5623_GBL_CLK_SYS_SOUR_SEL_PLL (1 << 15)
111#define ALC5623_GBL_CLK_SYS_SOUR_SEL_MCLK (0 << 15)
112#define ALC5623_GBL_CLK_PLL_SOUR_SEL_BITCLK (1 << 14)
113#define ALC5623_GBL_CLK_PLL_SOUR_SEL_MCLK (0 << 14)
114#define ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV8 (3 << 1)
115#define ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV4 (2 << 1)
116#define ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV2 (1 << 1)
117#define ALC5623_GBL_CLK_PLL_DIV_RATIO_DIV1 (0 << 1)
118#define ALC5623_GBL_CLK_PLL_PRE_DIV2 (1 << 0)
119#define ALC5623_GBL_CLK_PLL_PRE_DIV1 (0 << 0)
120
121#define ALC5623_PLL_CTRL 0x44
122#define ALC5623_PLL_CTRL_N_VAL(n) (((n)&0xff) << 8)
123#define ALC5623_PLL_CTRL_K_VAL(k) (((k)&0x7) << 4)
124#define ALC5623_PLL_CTRL_M_VAL(m) ((m)&0xf)
125
126#define ALC5623_GPIO_OUTPUT_PIN_CTRL 0x4A
127#define ALC5623_GPIO_PIN_CONFIG 0x4C
128#define ALC5623_GPIO_PIN_POLARITY 0x4E
129#define ALC5623_GPIO_PIN_STICKY 0x50
130#define ALC5623_GPIO_PIN_WAKEUP 0x52
131#define ALC5623_GPIO_PIN_STATUS 0x54
132#define ALC5623_GPIO_PIN_SHARING 0x56
133#define ALC5623_OVER_CURR_STATUS 0x58
134#define ALC5623_JACK_DET_CTRL 0x5A
135
136#define ALC5623_MISC_CTRL 0x5E
137#define ALC5623_MISC_DISABLE_FAST_VREG (1 << 15)
138#define ALC5623_MISC_SPK_CLASS_AB_OC_PD (1 << 13) /* 5621 */
139#define ALC5623_MISC_SPK_CLASS_AB_OC_DET (1 << 12) /* 5621 */
140#define ALC5623_MISC_HP_DEPOP_MODE3_EN (1 << 10)
141#define ALC5623_MISC_HP_DEPOP_MODE2_EN (1 << 9)
142#define ALC5623_MISC_HP_DEPOP_MODE1_EN (1 << 8)
143#define ALC5623_MISC_AUXOUT_DEPOP_MODE3_EN (1 << 6)
144#define ALC5623_MISC_AUXOUT_DEPOP_MODE2_EN (1 << 5)
145#define ALC5623_MISC_AUXOUT_DEPOP_MODE1_EN (1 << 4)
146#define ALC5623_MISC_M_DAC_L_INPUT (1 << 3)
147#define ALC5623_MISC_M_DAC_R_INPUT (1 << 2)
148#define ALC5623_MISC_IRQOUT_INV_CTRL (1 << 0)
149
150#define ALC5623_PSEDUEO_SPATIAL_CTRL 0x60
151#define ALC5623_EQ_CTRL 0x62
152#define ALC5623_EQ_MODE_ENABLE 0x66
153#define ALC5623_AVC_CTRL 0x68
154#define ALC5623_HID_CTRL_INDEX 0x6A
155#define ALC5623_HID_CTRL_DATA 0x6C
156#define ALC5623_VENDOR_ID1 0x7C
157#define ALC5623_VENDOR_ID2 0x7E
158
159#define ALC5623_PLL_FR_MCLK 0
160#define ALC5623_PLL_FR_BCK 1
161#endif
diff --git a/sound/soc/codecs/cq93vc.c b/sound/soc/codecs/cq93vc.c
index 823643932dde..46dbfd067f79 100644
--- a/sound/soc/codecs/cq93vc.c
+++ b/sound/soc/codecs/cq93vc.c
@@ -36,8 +36,6 @@
36#include <sound/pcm.h> 36#include <sound/pcm.h>
37#include <sound/pcm_params.h> 37#include <sound/pcm_params.h>
38#include <sound/soc.h> 38#include <sound/soc.h>
39#include <sound/soc-dai.h>
40#include <sound/soc-dapm.h>
41#include <sound/initval.h> 39#include <sound/initval.h>
42 40
43#include <mach/dm365.h> 41#include <mach/dm365.h>
@@ -116,7 +114,7 @@ static int cq93vc_set_bias_level(struct snd_soc_codec *codec,
116 DAVINCI_VC_REG12_POWER_ALL_OFF); 114 DAVINCI_VC_REG12_POWER_ALL_OFF);
117 break; 115 break;
118 } 116 }
119 codec->bias_level = level; 117 codec->dapm.bias_level = level;
120 118
121 return 0; 119 return 0;
122} 120}
diff --git a/sound/soc/codecs/cs4270.c b/sound/soc/codecs/cs4270.c
index 6d4bdc609ac8..8b51245f2318 100644
--- a/sound/soc/codecs/cs4270.c
+++ b/sound/soc/codecs/cs4270.c
@@ -106,6 +106,21 @@
106#define CS4270_MUTE_DAC_A 0x01 106#define CS4270_MUTE_DAC_A 0x01
107#define CS4270_MUTE_DAC_B 0x02 107#define CS4270_MUTE_DAC_B 0x02
108 108
109/* Power-on default values for the registers
110 *
111 * This array contains the power-on default values of the registers, with the
112 * exception of the "CHIPID" register (01h). The lower four bits of that
113 * register contain the hardware revision, so it is treated as volatile.
114 *
115 * Also note that on the CS4270, the first readable register is 1, but ASoC
116 * assumes the first register is 0. Therfore, the array must have an entry for
117 * register 0, but we use cs4270_reg_is_readable() to tell ASoC that it can't
118 * be read.
119 */
120static const u8 cs4270_default_reg_cache[CS4270_LASTREG + 1] = {
121 0x00, 0x00, 0x00, 0x30, 0x00, 0x60, 0x20, 0x00, 0x00
122};
123
109static const char *supply_names[] = { 124static const char *supply_names[] = {
110 "va", "vd", "vlc" 125 "va", "vd", "vlc"
111}; 126};
@@ -114,7 +129,6 @@ static const char *supply_names[] = {
114struct cs4270_private { 129struct cs4270_private {
115 enum snd_soc_control_type control_type; 130 enum snd_soc_control_type control_type;
116 void *control_data; 131 void *control_data;
117 u8 reg_cache[CS4270_NUMREGS];
118 unsigned int mclk; /* Input frequency of the MCLK pin */ 132 unsigned int mclk; /* Input frequency of the MCLK pin */
119 unsigned int mode; /* The mode (I2S or left-justified) */ 133 unsigned int mode; /* The mode (I2S or left-justified) */
120 unsigned int slave_mode; 134 unsigned int slave_mode;
@@ -179,6 +193,20 @@ static struct cs4270_mode_ratios cs4270_mode_ratios[] = {
179/* The number of MCLK/LRCK ratios supported by the CS4270 */ 193/* The number of MCLK/LRCK ratios supported by the CS4270 */
180#define NUM_MCLK_RATIOS ARRAY_SIZE(cs4270_mode_ratios) 194#define NUM_MCLK_RATIOS ARRAY_SIZE(cs4270_mode_ratios)
181 195
196static int cs4270_reg_is_readable(unsigned int reg)
197{
198 return (reg >= CS4270_FIRSTREG) && (reg <= CS4270_LASTREG);
199}
200
201static int cs4270_reg_is_volatile(unsigned int reg)
202{
203 /* Unreadable registers are considered volatile */
204 if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG))
205 return 1;
206
207 return reg == CS4270_CHIPID;
208}
209
182/** 210/**
183 * cs4270_set_dai_sysclk - determine the CS4270 samples rates. 211 * cs4270_set_dai_sysclk - determine the CS4270 samples rates.
184 * @codec_dai: the codec DAI 212 * @codec_dai: the codec DAI
@@ -264,97 +292,6 @@ static int cs4270_set_dai_fmt(struct snd_soc_dai *codec_dai,
264} 292}
265 293
266/** 294/**
267 * cs4270_fill_cache - pre-fill the CS4270 register cache.
268 * @codec: the codec for this CS4270
269 *
270 * This function fills in the CS4270 register cache by reading the register
271 * values from the hardware.
272 *
273 * This CS4270 registers are cached to avoid excessive I2C I/O operations.
274 * After the initial read to pre-fill the cache, the CS4270 never updates
275 * the register values, so we won't have a cache coherency problem.
276 *
277 * We use the auto-increment feature of the CS4270 to read all registers in
278 * one shot.
279 */
280static int cs4270_fill_cache(struct snd_soc_codec *codec)
281{
282 u8 *cache = codec->reg_cache;
283 struct i2c_client *i2c_client = codec->control_data;
284 s32 length;
285
286 length = i2c_smbus_read_i2c_block_data(i2c_client,
287 CS4270_FIRSTREG | CS4270_I2C_INCR, CS4270_NUMREGS, cache);
288
289 if (length != CS4270_NUMREGS) {
290 dev_err(codec->dev, "i2c read failure, addr=0x%x\n",
291 i2c_client->addr);
292 return -EIO;
293 }
294
295 return 0;
296}
297
298/**
299 * cs4270_read_reg_cache - read from the CS4270 register cache.
300 * @codec: the codec for this CS4270
301 * @reg: the register to read
302 *
303 * This function returns the value for a given register. It reads only from
304 * the register cache, not the hardware itself.
305 *
306 * This CS4270 registers are cached to avoid excessive I2C I/O operations.
307 * After the initial read to pre-fill the cache, the CS4270 never updates
308 * the register values, so we won't have a cache coherency problem.
309 */
310static unsigned int cs4270_read_reg_cache(struct snd_soc_codec *codec,
311 unsigned int reg)
312{
313 u8 *cache = codec->reg_cache;
314
315 if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG))
316 return -EIO;
317
318 return cache[reg - CS4270_FIRSTREG];
319}
320
321/**
322 * cs4270_i2c_write - write to a CS4270 register via the I2C bus.
323 * @codec: the codec for this CS4270
324 * @reg: the register to write
325 * @value: the value to write to the register
326 *
327 * This function writes the given value to the given CS4270 register, and
328 * also updates the register cache.
329 *
330 * Note that we don't use the hw_write function pointer of snd_soc_codec.
331 * That's because it's too clunky: the hw_write_t prototype does not match
332 * i2c_smbus_write_byte_data(), and it's just another layer of overhead.
333 */
334static int cs4270_i2c_write(struct snd_soc_codec *codec, unsigned int reg,
335 unsigned int value)
336{
337 u8 *cache = codec->reg_cache;
338
339 if ((reg < CS4270_FIRSTREG) || (reg > CS4270_LASTREG))
340 return -EIO;
341
342 /* Only perform an I2C operation if the new value is different */
343 if (cache[reg - CS4270_FIRSTREG] != value) {
344 struct i2c_client *client = codec->control_data;
345 if (i2c_smbus_write_byte_data(client, reg, value)) {
346 dev_err(codec->dev, "i2c write failed\n");
347 return -EIO;
348 }
349
350 /* We've written to the hardware, so update the cache */
351 cache[reg - CS4270_FIRSTREG] = value;
352 }
353
354 return 0;
355}
356
357/**
358 * cs4270_hw_params - program the CS4270 with the given hardware parameters. 295 * cs4270_hw_params - program the CS4270 with the given hardware parameters.
359 * @substream: the audio stream 296 * @substream: the audio stream
360 * @params: the hardware parameters to set 297 * @params: the hardware parameters to set
@@ -551,15 +488,16 @@ static struct snd_soc_dai_driver cs4270_dai = {
551static int cs4270_probe(struct snd_soc_codec *codec) 488static int cs4270_probe(struct snd_soc_codec *codec)
552{ 489{
553 struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec); 490 struct cs4270_private *cs4270 = snd_soc_codec_get_drvdata(codec);
554 int i, ret, reg; 491 int i, ret;
555 492
556 codec->control_data = cs4270->control_data; 493 codec->control_data = cs4270->control_data;
557 494
558 /* The I2C interface is set up, so pre-fill our register cache */ 495 /* Tell ASoC what kind of I/O to use to read the registers. ASoC will
559 496 * then do the I2C transactions itself.
560 ret = cs4270_fill_cache(codec); 497 */
498 ret = snd_soc_codec_set_cache_io(codec, 8, 8, cs4270->control_type);
561 if (ret < 0) { 499 if (ret < 0) {
562 dev_err(codec->dev, "failed to fill register cache\n"); 500 dev_err(codec->dev, "failed to set cache I/O (ret=%i)\n", ret);
563 return ret; 501 return ret;
564 } 502 }
565 503
@@ -568,10 +506,7 @@ static int cs4270_probe(struct snd_soc_codec *codec)
568 * this feature disabled by default. An application (e.g. alsactl) can 506 * this feature disabled by default. An application (e.g. alsactl) can
569 * re-enabled it by using the controls. 507 * re-enabled it by using the controls.
570 */ 508 */
571 509 ret = snd_soc_update_bits(codec, CS4270_MUTE, CS4270_MUTE_AUTO, 0);
572 reg = cs4270_read_reg_cache(codec, CS4270_MUTE);
573 reg &= ~CS4270_MUTE_AUTO;
574 ret = cs4270_i2c_write(codec, CS4270_MUTE, reg);
575 if (ret < 0) { 510 if (ret < 0) {
576 dev_err(codec->dev, "i2c write failed\n"); 511 dev_err(codec->dev, "i2c write failed\n");
577 return ret; 512 return ret;
@@ -582,10 +517,8 @@ static int cs4270_probe(struct snd_soc_codec *codec)
582 * playback has started. An application (e.g. alsactl) can 517 * playback has started. An application (e.g. alsactl) can
583 * re-enabled it by using the controls. 518 * re-enabled it by using the controls.
584 */ 519 */
585 520 ret = snd_soc_update_bits(codec, CS4270_TRANS,
586 reg = cs4270_read_reg_cache(codec, CS4270_TRANS); 521 CS4270_TRANS_SOFT | CS4270_TRANS_ZERO, 0);
587 reg &= ~(CS4270_TRANS_SOFT | CS4270_TRANS_ZERO);
588 ret = cs4270_i2c_write(codec, CS4270_TRANS, reg);
589 if (ret < 0) { 522 if (ret < 0) {
590 dev_err(codec->dev, "i2c write failed\n"); 523 dev_err(codec->dev, "i2c write failed\n");
591 return ret; 524 return ret;
@@ -708,15 +641,16 @@ static int cs4270_soc_resume(struct snd_soc_codec *codec)
708 * Assign this variable to the codec_dev field of the machine driver's 641 * Assign this variable to the codec_dev field of the machine driver's
709 * snd_soc_device structure. 642 * snd_soc_device structure.
710 */ 643 */
711static struct snd_soc_codec_driver soc_codec_device_cs4270 = { 644static const struct snd_soc_codec_driver soc_codec_device_cs4270 = {
712 .probe = cs4270_probe, 645 .probe = cs4270_probe,
713 .remove = cs4270_remove, 646 .remove = cs4270_remove,
714 .suspend = cs4270_soc_suspend, 647 .suspend = cs4270_soc_suspend,
715 .resume = cs4270_soc_resume, 648 .resume = cs4270_soc_resume,
716 .read = cs4270_read_reg_cache, 649 .volatile_register = cs4270_reg_is_volatile,
717 .write = cs4270_i2c_write, 650 .readable_register = cs4270_reg_is_readable,
718 .reg_cache_size = CS4270_NUMREGS, 651 .reg_cache_size = CS4270_LASTREG + 1,
719 .reg_word_size = sizeof(u8), 652 .reg_word_size = sizeof(u8),
653 .reg_cache_default = cs4270_default_reg_cache,
720}; 654};
721 655
722/** 656/**
diff --git a/sound/soc/codecs/cs42l51.c b/sound/soc/codecs/cs42l51.c
index cb086eaf4e07..8fb7070108dd 100644
--- a/sound/soc/codecs/cs42l51.c
+++ b/sound/soc/codecs/cs42l51.c
@@ -26,7 +26,6 @@
26#include <linux/slab.h> 26#include <linux/slab.h>
27#include <sound/core.h> 27#include <sound/core.h>
28#include <sound/soc.h> 28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/tlv.h> 29#include <sound/tlv.h>
31#include <sound/initval.h> 30#include <sound/initval.h>
32#include <sound/pcm_params.h> 31#include <sound/pcm_params.h>
@@ -47,7 +46,6 @@ struct cs42l51_private {
47 unsigned int mclk; 46 unsigned int mclk;
48 unsigned int audio_mode; /* The mode (I2S or left-justified) */ 47 unsigned int audio_mode; /* The mode (I2S or left-justified) */
49 enum master_slave_mode func; 48 enum master_slave_mode func;
50 u8 reg_cache[CS42L51_NUMREGS];
51}; 49};
52 50
53#define CS42L51_FORMATS ( \ 51#define CS42L51_FORMATS ( \
@@ -519,6 +517,7 @@ static struct snd_soc_dai_driver cs42l51_dai = {
519static int cs42l51_probe(struct snd_soc_codec *codec) 517static int cs42l51_probe(struct snd_soc_codec *codec)
520{ 518{
521 struct cs42l51_private *cs42l51 = snd_soc_codec_get_drvdata(codec); 519 struct cs42l51_private *cs42l51 = snd_soc_codec_get_drvdata(codec);
520 struct snd_soc_dapm_context *dapm = &codec->dapm;
522 int ret, reg; 521 int ret, reg;
523 522
524 codec->control_data = cs42l51->control_data; 523 codec->control_data = cs42l51->control_data;
@@ -550,9 +549,9 @@ static int cs42l51_probe(struct snd_soc_codec *codec)
550 549
551 snd_soc_add_controls(codec, cs42l51_snd_controls, 550 snd_soc_add_controls(codec, cs42l51_snd_controls,
552 ARRAY_SIZE(cs42l51_snd_controls)); 551 ARRAY_SIZE(cs42l51_snd_controls));
553 snd_soc_dapm_new_controls(codec, cs42l51_dapm_widgets, 552 snd_soc_dapm_new_controls(dapm, cs42l51_dapm_widgets,
554 ARRAY_SIZE(cs42l51_dapm_widgets)); 553 ARRAY_SIZE(cs42l51_dapm_widgets));
555 snd_soc_dapm_add_routes(codec, cs42l51_routes, 554 snd_soc_dapm_add_routes(dapm, cs42l51_routes,
556 ARRAY_SIZE(cs42l51_routes)); 555 ARRAY_SIZE(cs42l51_routes));
557 556
558 return 0; 557 return 0;
diff --git a/sound/soc/codecs/cx20442.c b/sound/soc/codecs/cx20442.c
index e8d27c8f9ba3..03d1e860d229 100644
--- a/sound/soc/codecs/cx20442.c
+++ b/sound/soc/codecs/cx20442.c
@@ -18,7 +18,7 @@
18 18
19#include <sound/core.h> 19#include <sound/core.h>
20#include <sound/initval.h> 20#include <sound/initval.h>
21#include <sound/soc-dapm.h> 21#include <sound/soc.h>
22 22
23#include "cx20442.h" 23#include "cx20442.h"
24 24
@@ -26,7 +26,6 @@
26struct cx20442_priv { 26struct cx20442_priv {
27 enum snd_soc_control_type control_type; 27 enum snd_soc_control_type control_type;
28 void *control_data; 28 void *control_data;
29 u8 reg_cache[1];
30}; 29};
31 30
32#define CX20442_PM 0x0 31#define CX20442_PM 0x0
@@ -89,10 +88,11 @@ static const struct snd_soc_dapm_route cx20442_audio_map[] = {
89 88
90static int cx20442_add_widgets(struct snd_soc_codec *codec) 89static int cx20442_add_widgets(struct snd_soc_codec *codec)
91{ 90{
92 snd_soc_dapm_new_controls(codec, cx20442_dapm_widgets, 91 struct snd_soc_dapm_context *dapm = &codec->dapm;
93 ARRAY_SIZE(cx20442_dapm_widgets));
94 92
95 snd_soc_dapm_add_routes(codec, cx20442_audio_map, 93 snd_soc_dapm_new_controls(dapm, cx20442_dapm_widgets,
94 ARRAY_SIZE(cx20442_dapm_widgets));
95 snd_soc_dapm_add_routes(dapm, cx20442_audio_map,
96 ARRAY_SIZE(cx20442_audio_map)); 96 ARRAY_SIZE(cx20442_audio_map));
97 97
98 return 0; 98 return 0;
@@ -263,7 +263,7 @@ static void v253_close(struct tty_struct *tty)
263 /* Prevent the codec driver from further accessing the modem */ 263 /* Prevent the codec driver from further accessing the modem */
264 codec->hw_write = NULL; 264 codec->hw_write = NULL;
265 cx20442->control_data = NULL; 265 cx20442->control_data = NULL;
266 codec->pop_time = 0; 266 codec->card->pop_time = 0;
267} 267}
268 268
269/* Line discipline .hangup() */ 269/* Line discipline .hangup() */
@@ -291,7 +291,7 @@ static void v253_receive(struct tty_struct *tty,
291 /* Set up codec driver access to modem controls */ 291 /* Set up codec driver access to modem controls */
292 cx20442->control_data = tty; 292 cx20442->control_data = tty;
293 codec->hw_write = (hw_write_t)tty->ops->write; 293 codec->hw_write = (hw_write_t)tty->ops->write;
294 codec->pop_time = 1; 294 codec->card->pop_time = 1;
295 } 295 }
296} 296}
297 297
@@ -348,7 +348,7 @@ static int cx20442_codec_probe(struct snd_soc_codec *codec)
348 348
349 cx20442->control_data = NULL; 349 cx20442->control_data = NULL;
350 codec->hw_write = NULL; 350 codec->hw_write = NULL;
351 codec->pop_time = 0; 351 codec->card->pop_time = 0;
352 352
353 return 0; 353 return 0;
354} 354}
diff --git a/sound/soc/codecs/da7210.c b/sound/soc/codecs/da7210.c
index 58bb9b994811..92fd9d7a9221 100644
--- a/sound/soc/codecs/da7210.c
+++ b/sound/soc/codecs/da7210.c
@@ -21,7 +21,7 @@
21#include <linux/slab.h> 21#include <linux/slab.h>
22#include <sound/pcm.h> 22#include <sound/pcm.h>
23#include <sound/pcm_params.h> 23#include <sound/pcm_params.h>
24#include <sound/soc-dapm.h> 24#include <sound/soc.h>
25#include <sound/initval.h> 25#include <sound/initval.h>
26#include <sound/tlv.h> 26#include <sound/tlv.h>
27 27
diff --git a/sound/soc/codecs/dmic.c b/sound/soc/codecs/dmic.c
new file mode 100644
index 000000000000..57e9dac88d38
--- /dev/null
+++ b/sound/soc/codecs/dmic.c
@@ -0,0 +1,81 @@
1/*
2 * dmic.c -- SoC audio for Generic Digital MICs
3 *
4 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28
29static struct snd_soc_dai_driver dmic_dai = {
30 .name = "dmic-hifi",
31 .capture = {
32 .stream_name = "Capture",
33 .channels_min = 1,
34 .channels_max = 8,
35 .rates = SNDRV_PCM_RATE_CONTINUOUS,
36 .formats = SNDRV_PCM_FMTBIT_S32_LE
37 | SNDRV_PCM_FMTBIT_S24_LE
38 | SNDRV_PCM_FMTBIT_S16_LE,
39 },
40};
41
42static struct snd_soc_codec_driver soc_dmic = {};
43
44static int __devinit dmic_dev_probe(struct platform_device *pdev)
45{
46 return snd_soc_register_codec(&pdev->dev,
47 &soc_dmic, &dmic_dai, 1);
48}
49
50static int __devexit dmic_dev_remove(struct platform_device *pdev)
51{
52 snd_soc_unregister_codec(&pdev->dev);
53 return 0;
54}
55
56MODULE_ALIAS("platform:dmic-codec");
57
58static struct platform_driver dmic_driver = {
59 .driver = {
60 .name = "dmic-codec",
61 .owner = THIS_MODULE,
62 },
63 .probe = dmic_dev_probe,
64 .remove = __devexit_p(dmic_dev_remove),
65};
66
67static int __init dmic_init(void)
68{
69 return platform_driver_register(&dmic_driver);
70}
71module_init(dmic_init);
72
73static void __exit dmic_exit(void)
74{
75 platform_driver_unregister(&dmic_driver);
76}
77module_exit(dmic_exit);
78
79MODULE_DESCRIPTION("Generic DMIC driver");
80MODULE_AUTHOR("Liam Girdwood <lrg@slimlogic.co.uk>");
81MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/jz4740.c b/sound/soc/codecs/jz4740.c
index 16253ec9b022..f7cd346fd727 100644
--- a/sound/soc/codecs/jz4740.c
+++ b/sound/soc/codecs/jz4740.c
@@ -22,7 +22,6 @@
22#include <sound/pcm.h> 22#include <sound/pcm.h>
23#include <sound/pcm_params.h> 23#include <sound/pcm_params.h>
24#include <sound/initval.h> 24#include <sound/initval.h>
25#include <sound/soc-dapm.h>
26#include <sound/soc.h> 25#include <sound/soc.h>
27 26
28#define JZ4740_REG_CODEC_1 0x0 27#define JZ4740_REG_CODEC_1 0x0
@@ -266,7 +265,7 @@ static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec,
266 break; 265 break;
267 case SND_SOC_BIAS_STANDBY: 266 case SND_SOC_BIAS_STANDBY:
268 /* The only way to clear the suspend flag is to reset the codec */ 267 /* The only way to clear the suspend flag is to reset the codec */
269 if (codec->bias_level == SND_SOC_BIAS_OFF) 268 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
270 jz4740_codec_wakeup(codec); 269 jz4740_codec_wakeup(codec);
271 270
272 mask = JZ4740_CODEC_1_VREF_DISABLE | 271 mask = JZ4740_CODEC_1_VREF_DISABLE |
@@ -288,23 +287,25 @@ static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec,
288 break; 287 break;
289 } 288 }
290 289
291 codec->bias_level = level; 290 codec->dapm.bias_level = level;
292 291
293 return 0; 292 return 0;
294} 293}
295 294
296static int jz4740_codec_dev_probe(struct snd_soc_codec *codec) 295static int jz4740_codec_dev_probe(struct snd_soc_codec *codec)
297{ 296{
297 struct snd_soc_dapm_context *dapm = &codec->dapm;
298
298 snd_soc_update_bits(codec, JZ4740_REG_CODEC_1, 299 snd_soc_update_bits(codec, JZ4740_REG_CODEC_1,
299 JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE); 300 JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);
300 301
301 snd_soc_add_controls(codec, jz4740_codec_controls, 302 snd_soc_add_controls(codec, jz4740_codec_controls,
302 ARRAY_SIZE(jz4740_codec_controls)); 303 ARRAY_SIZE(jz4740_codec_controls));
303 304
304 snd_soc_dapm_new_controls(codec, jz4740_codec_dapm_widgets, 305 snd_soc_dapm_new_controls(dapm, jz4740_codec_dapm_widgets,
305 ARRAY_SIZE(jz4740_codec_dapm_widgets)); 306 ARRAY_SIZE(jz4740_codec_dapm_widgets));
306 307
307 snd_soc_dapm_add_routes(codec, jz4740_codec_dapm_routes, 308 snd_soc_dapm_add_routes(dapm, jz4740_codec_dapm_routes,
308 ARRAY_SIZE(jz4740_codec_dapm_routes)); 309 ARRAY_SIZE(jz4740_codec_dapm_routes));
309 310
310 snd_soc_dapm_new_widgets(codec); 311 snd_soc_dapm_new_widgets(codec);
diff --git a/sound/soc/codecs/max98088.c b/sound/soc/codecs/max98088.c
index 72f0dbc6e0f2..89498f9ad2e5 100644
--- a/sound/soc/codecs/max98088.c
+++ b/sound/soc/codecs/max98088.c
@@ -20,7 +20,6 @@
20#include <sound/pcm.h> 20#include <sound/pcm.h>
21#include <sound/pcm_params.h> 21#include <sound/pcm_params.h>
22#include <sound/soc.h> 22#include <sound/soc.h>
23#include <sound/soc-dapm.h>
24#include <sound/initval.h> 23#include <sound/initval.h>
25#include <sound/tlv.h> 24#include <sound/tlv.h>
26#include <linux/slab.h> 25#include <linux/slab.h>
@@ -1229,15 +1228,17 @@ static const struct snd_soc_dapm_route audio_map[] = {
1229 1228
1230static int max98088_add_widgets(struct snd_soc_codec *codec) 1229static int max98088_add_widgets(struct snd_soc_codec *codec)
1231{ 1230{
1232 snd_soc_dapm_new_controls(codec, max98088_dapm_widgets, 1231 struct snd_soc_dapm_context *dapm = &codec->dapm;
1232
1233 snd_soc_dapm_new_controls(dapm, max98088_dapm_widgets,
1233 ARRAY_SIZE(max98088_dapm_widgets)); 1234 ARRAY_SIZE(max98088_dapm_widgets));
1234 1235
1235 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 1236 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
1236 1237
1237 snd_soc_add_controls(codec, max98088_snd_controls, 1238 snd_soc_add_controls(codec, max98088_snd_controls,
1238 ARRAY_SIZE(max98088_snd_controls)); 1239 ARRAY_SIZE(max98088_snd_controls));
1239 1240
1240 snd_soc_dapm_new_widgets(codec); 1241 snd_soc_dapm_new_widgets(dapm);
1241 return 0; 1242 return 0;
1242} 1243}
1243 1244
@@ -1622,7 +1623,7 @@ static int max98088_set_bias_level(struct snd_soc_codec *codec,
1622 break; 1623 break;
1623 1624
1624 case SND_SOC_BIAS_STANDBY: 1625 case SND_SOC_BIAS_STANDBY:
1625 if (codec->bias_level == SND_SOC_BIAS_OFF) 1626 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1626 max98088_sync_cache(codec); 1627 max98088_sync_cache(codec);
1627 1628
1628 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN, 1629 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
@@ -1635,7 +1636,7 @@ static int max98088_set_bias_level(struct snd_soc_codec *codec,
1635 codec->cache_sync = 1; 1636 codec->cache_sync = 1;
1636 break; 1637 break;
1637 } 1638 }
1638 codec->bias_level = level; 1639 codec->dapm.bias_level = level;
1639 return 0; 1640 return 0;
1640} 1641}
1641 1642
diff --git a/sound/soc/codecs/ssm2602.c b/sound/soc/codecs/ssm2602.c
index 6f38d619bf8a..2727befd158e 100644
--- a/sound/soc/codecs/ssm2602.c
+++ b/sound/soc/codecs/ssm2602.c
@@ -38,7 +38,6 @@
38#include <sound/pcm.h> 38#include <sound/pcm.h>
39#include <sound/pcm_params.h> 39#include <sound/pcm_params.h>
40#include <sound/soc.h> 40#include <sound/soc.h>
41#include <sound/soc-dapm.h>
42#include <sound/initval.h> 41#include <sound/initval.h>
43 42
44#include "ssm2602.h" 43#include "ssm2602.h"
@@ -207,10 +206,11 @@ static const struct snd_soc_dapm_route audio_conn[] = {
207 206
208static int ssm2602_add_widgets(struct snd_soc_codec *codec) 207static int ssm2602_add_widgets(struct snd_soc_codec *codec)
209{ 208{
210 snd_soc_dapm_new_controls(codec, ssm2602_dapm_widgets, 209 struct snd_soc_dapm_context *dapm = &codec->dapm;
211 ARRAY_SIZE(ssm2602_dapm_widgets));
212 210
213 snd_soc_dapm_add_routes(codec, audio_conn, ARRAY_SIZE(audio_conn)); 211 snd_soc_dapm_new_controls(dapm, ssm2602_dapm_widgets,
212 ARRAY_SIZE(ssm2602_dapm_widgets));
213 snd_soc_dapm_add_routes(dapm, audio_conn, ARRAY_SIZE(audio_conn));
214 214
215 return 0; 215 return 0;
216} 216}
@@ -493,7 +493,7 @@ static int ssm2602_set_bias_level(struct snd_soc_codec *codec,
493 break; 493 break;
494 494
495 } 495 }
496 codec->bias_level = level; 496 codec->dapm.bias_level = level;
497 return 0; 497 return 0;
498} 498}
499 499
diff --git a/sound/soc/codecs/stac9766.c b/sound/soc/codecs/stac9766.c
index 061f9e5a497b..78b2b50271e2 100644
--- a/sound/soc/codecs/stac9766.c
+++ b/sound/soc/codecs/stac9766.c
@@ -236,7 +236,7 @@ static int stac9766_set_bias_level(struct snd_soc_codec *codec,
236 stac9766_ac97_write(codec, AC97_POWERDOWN, 0xffff); 236 stac9766_ac97_write(codec, AC97_POWERDOWN, 0xffff);
237 break; 237 break;
238 } 238 }
239 codec->bias_level = level; 239 codec->dapm.bias_level = level;
240 return 0; 240 return 0;
241} 241}
242 242
diff --git a/sound/soc/codecs/tlv320aic23.c b/sound/soc/codecs/tlv320aic23.c
index e8652b1ae326..54a30ef0ec8b 100644
--- a/sound/soc/codecs/tlv320aic23.c
+++ b/sound/soc/codecs/tlv320aic23.c
@@ -30,7 +30,6 @@
30#include <sound/pcm.h> 30#include <sound/pcm.h>
31#include <sound/pcm_params.h> 31#include <sound/pcm_params.h>
32#include <sound/soc.h> 32#include <sound/soc.h>
33#include <sound/soc-dapm.h>
34#include <sound/tlv.h> 33#include <sound/tlv.h>
35#include <sound/initval.h> 34#include <sound/initval.h>
36 35
@@ -391,11 +390,12 @@ static int set_sample_rate_control(struct snd_soc_codec *codec, int mclk,
391 390
392static int tlv320aic23_add_widgets(struct snd_soc_codec *codec) 391static int tlv320aic23_add_widgets(struct snd_soc_codec *codec)
393{ 392{
394 snd_soc_dapm_new_controls(codec, tlv320aic23_dapm_widgets, 393 struct snd_soc_dapm_context *dapm = &codec->dapm;
395 ARRAY_SIZE(tlv320aic23_dapm_widgets));
396 394
395 snd_soc_dapm_new_controls(dapm, tlv320aic23_dapm_widgets,
396 ARRAY_SIZE(tlv320aic23_dapm_widgets));
397 /* set up audio path interconnects */ 397 /* set up audio path interconnects */
398 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 398 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
399 399
400 return 0; 400 return 0;
401} 401}
@@ -574,7 +574,7 @@ static int tlv320aic23_set_bias_level(struct snd_soc_codec *codec,
574 tlv320aic23_write(codec, TLV320AIC23_PWR, 0xffff); 574 tlv320aic23_write(codec, TLV320AIC23_PWR, 0xffff);
575 break; 575 break;
576 } 576 }
577 codec->bias_level = level; 577 codec->dapm.bias_level = level;
578 return 0; 578 return 0;
579} 579}
580 580
diff --git a/sound/soc/codecs/tlv320aic26.c b/sound/soc/codecs/tlv320aic26.c
index 6b7d71ec0004..e2a7608d3944 100644
--- a/sound/soc/codecs/tlv320aic26.c
+++ b/sound/soc/codecs/tlv320aic26.c
@@ -18,7 +18,6 @@
18#include <sound/pcm.h> 18#include <sound/pcm.h>
19#include <sound/pcm_params.h> 19#include <sound/pcm_params.h>
20#include <sound/soc.h> 20#include <sound/soc.h>
21#include <sound/soc-dapm.h>
22#include <sound/initval.h> 21#include <sound/initval.h>
23 22
24#include "tlv320aic26.h" 23#include "tlv320aic26.h"
@@ -31,7 +30,6 @@ MODULE_LICENSE("GPL");
31struct aic26 { 30struct aic26 {
32 struct spi_device *spi; 31 struct spi_device *spi;
33 struct snd_soc_codec codec; 32 struct snd_soc_codec codec;
34 u16 reg_cache[AIC26_NUM_REGS]; /* shadow registers */
35 int master; 33 int master;
36 int datfm; 34 int datfm;
37 int mclk; 35 int mclk;
@@ -355,7 +353,6 @@ static DEVICE_ATTR(keyclick, 0644, aic26_keyclick_show, aic26_keyclick_set);
355 */ 353 */
356static int aic26_probe(struct snd_soc_codec *codec) 354static int aic26_probe(struct snd_soc_codec *codec)
357{ 355{
358 struct aic26 *aic26 = snd_soc_codec_get_drvdata(codec);
359 int ret, err, i, reg; 356 int ret, err, i, reg;
360 357
361 dev_info(codec->dev, "Probing AIC26 SoC CODEC driver\n"); 358 dev_info(codec->dev, "Probing AIC26 SoC CODEC driver\n");
@@ -373,7 +370,7 @@ static int aic26_probe(struct snd_soc_codec *codec)
373 aic26_reg_write(codec, AIC26_REG_AUDIO_CTRL3, reg); 370 aic26_reg_write(codec, AIC26_REG_AUDIO_CTRL3, reg);
374 371
375 /* Fill register cache */ 372 /* Fill register cache */
376 for (i = 0; i < ARRAY_SIZE(aic26->reg_cache); i++) 373 for (i = 0; i < codec->driver->reg_cache_size; i++)
377 aic26_reg_read(codec, i); 374 aic26_reg_read(codec, i);
378 375
379 /* Register the sysfs files for debugging */ 376 /* Register the sysfs files for debugging */
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index 77b8f9ae29be..3bedab26892f 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -46,7 +46,6 @@
46#include <sound/pcm.h> 46#include <sound/pcm.h>
47#include <sound/pcm_params.h> 47#include <sound/pcm_params.h>
48#include <sound/soc.h> 48#include <sound/soc.h>
49#include <sound/soc-dapm.h>
50#include <sound/initval.h> 49#include <sound/initval.h>
51#include <sound/tlv.h> 50#include <sound/tlv.h>
52#include <sound/tlv320aic3x.h> 51#include <sound/tlv320aic3x.h>
@@ -61,6 +60,8 @@ static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
61 "DRVDD", /* ADC Analog and Output Driver Voltage */ 60 "DRVDD", /* ADC Analog and Output Driver Voltage */
62}; 61};
63 62
63static LIST_HEAD(reset_list);
64
64struct aic3x_priv; 65struct aic3x_priv;
65 66
66struct aic3x_disable_nb { 67struct aic3x_disable_nb {
@@ -77,6 +78,7 @@ struct aic3x_priv {
77 struct aic3x_setup_data *setup; 78 struct aic3x_setup_data *setup;
78 void *control_data; 79 void *control_data;
79 unsigned int sysclk; 80 unsigned int sysclk;
81 struct list_head list;
80 int master; 82 int master;
81 int gpio_reset; 83 int gpio_reset;
82 int power; 84 int power;
@@ -183,7 +185,7 @@ static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
183 185
184 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { 186 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
185 /* find dapm widget path assoc with kcontrol */ 187 /* find dapm widget path assoc with kcontrol */
186 list_for_each_entry(path, &widget->codec->dapm_paths, list) { 188 list_for_each_entry(path, &widget->dapm->card->paths, list) {
187 if (path->kcontrol != kcontrol) 189 if (path->kcontrol != kcontrol)
188 continue; 190 continue;
189 191
@@ -199,7 +201,7 @@ static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
199 } 201 }
200 202
201 if (found) 203 if (found)
202 snd_soc_dapm_sync(widget->codec); 204 snd_soc_dapm_sync(widget->dapm);
203 } 205 }
204 206
205 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val); 207 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
@@ -788,17 +790,19 @@ static const struct snd_soc_dapm_route intercon_3007[] = {
788static int aic3x_add_widgets(struct snd_soc_codec *codec) 790static int aic3x_add_widgets(struct snd_soc_codec *codec)
789{ 791{
790 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 792 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
793 struct snd_soc_dapm_context *dapm = &codec->dapm;
791 794
792 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets, 795 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
793 ARRAY_SIZE(aic3x_dapm_widgets)); 796 ARRAY_SIZE(aic3x_dapm_widgets));
794 797
795 /* set up audio path interconnects */ 798 /* set up audio path interconnects */
796 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 799 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
797 800
798 if (aic3x->model == AIC3X_MODEL_3007) { 801 if (aic3x->model == AIC3X_MODEL_3007) {
799 snd_soc_dapm_new_controls(codec, aic3007_dapm_widgets, 802 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
800 ARRAY_SIZE(aic3007_dapm_widgets)); 803 ARRAY_SIZE(aic3007_dapm_widgets));
801 snd_soc_dapm_add_routes(codec, intercon_3007, ARRAY_SIZE(intercon_3007)); 804 snd_soc_dapm_add_routes(dapm, intercon_3007,
805 ARRAY_SIZE(intercon_3007));
802 } 806 }
803 807
804 return 0; 808 return 0;
@@ -1075,7 +1079,7 @@ static int aic3x_regulator_event(struct notifier_block *nb,
1075 * Put codec to reset and require cache sync as at least one 1079 * Put codec to reset and require cache sync as at least one
1076 * of the supplies was disabled 1080 * of the supplies was disabled
1077 */ 1081 */
1078 if (aic3x->gpio_reset >= 0) 1082 if (gpio_is_valid(aic3x->gpio_reset))
1079 gpio_set_value(aic3x->gpio_reset, 0); 1083 gpio_set_value(aic3x->gpio_reset, 0);
1080 aic3x->codec->cache_sync = 1; 1084 aic3x->codec->cache_sync = 1;
1081 } 1085 }
@@ -1102,7 +1106,7 @@ static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1102 if (!codec->cache_sync) 1106 if (!codec->cache_sync)
1103 goto out; 1107 goto out;
1104 1108
1105 if (aic3x->gpio_reset >= 0) { 1109 if (gpio_is_valid(aic3x->gpio_reset)) {
1106 udelay(1); 1110 udelay(1);
1107 gpio_set_value(aic3x->gpio_reset, 1); 1111 gpio_set_value(aic3x->gpio_reset, 1);
1108 } 1112 }
@@ -1135,7 +1139,7 @@ static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1135 case SND_SOC_BIAS_ON: 1139 case SND_SOC_BIAS_ON:
1136 break; 1140 break;
1137 case SND_SOC_BIAS_PREPARE: 1141 case SND_SOC_BIAS_PREPARE:
1138 if (codec->bias_level == SND_SOC_BIAS_STANDBY && 1142 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
1139 aic3x->master) { 1143 aic3x->master) {
1140 /* enable pll */ 1144 /* enable pll */
1141 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG); 1145 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
@@ -1146,7 +1150,7 @@ static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1146 case SND_SOC_BIAS_STANDBY: 1150 case SND_SOC_BIAS_STANDBY:
1147 if (!aic3x->power) 1151 if (!aic3x->power)
1148 aic3x_set_power(codec, 1); 1152 aic3x_set_power(codec, 1);
1149 if (codec->bias_level == SND_SOC_BIAS_PREPARE && 1153 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
1150 aic3x->master) { 1154 aic3x->master) {
1151 /* disable pll */ 1155 /* disable pll */
1152 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG); 1156 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
@@ -1159,7 +1163,7 @@ static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1159 aic3x_set_power(codec, 0); 1163 aic3x_set_power(codec, 0);
1160 break; 1164 break;
1161 } 1165 }
1162 codec->bias_level = level; 1166 codec->dapm.bias_level = level;
1163 1167
1164 return 0; 1168 return 0;
1165} 1169}
@@ -1344,14 +1348,28 @@ static int aic3x_init(struct snd_soc_codec *codec)
1344 return 0; 1348 return 0;
1345} 1349}
1346 1350
1351static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1352{
1353 struct aic3x_priv *a;
1354
1355 list_for_each_entry(a, &reset_list, list) {
1356 if (gpio_is_valid(aic3x->gpio_reset) &&
1357 aic3x->gpio_reset == a->gpio_reset)
1358 return true;
1359 }
1360
1361 return false;
1362}
1363
1347static int aic3x_probe(struct snd_soc_codec *codec) 1364static int aic3x_probe(struct snd_soc_codec *codec)
1348{ 1365{
1349 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1366 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1350 int ret, i; 1367 int ret, i;
1351 1368
1369 INIT_LIST_HEAD(&aic3x->list);
1352 codec->control_data = aic3x->control_data; 1370 codec->control_data = aic3x->control_data;
1353 aic3x->codec = codec; 1371 aic3x->codec = codec;
1354 codec->idle_bias_off = 1; 1372 codec->dapm.idle_bias_off = 1;
1355 1373
1356 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type); 1374 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1357 if (ret != 0) { 1375 if (ret != 0) {
@@ -1359,7 +1377,8 @@ static int aic3x_probe(struct snd_soc_codec *codec)
1359 return ret; 1377 return ret;
1360 } 1378 }
1361 1379
1362 if (aic3x->gpio_reset >= 0) { 1380 if (gpio_is_valid(aic3x->gpio_reset) &&
1381 !aic3x_is_shared_reset(aic3x)) {
1363 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset"); 1382 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1364 if (ret != 0) 1383 if (ret != 0)
1365 goto err_gpio; 1384 goto err_gpio;
@@ -1405,6 +1424,7 @@ static int aic3x_probe(struct snd_soc_codec *codec)
1405 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1); 1424 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
1406 1425
1407 aic3x_add_widgets(codec); 1426 aic3x_add_widgets(codec);
1427 list_add(&aic3x->list, &reset_list);
1408 1428
1409 return 0; 1429 return 0;
1410 1430
@@ -1414,10 +1434,10 @@ err_notif:
1414 &aic3x->disable_nb[i].nb); 1434 &aic3x->disable_nb[i].nb);
1415 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); 1435 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1416err_get: 1436err_get:
1417 if (aic3x->gpio_reset >= 0) 1437 if (gpio_is_valid(aic3x->gpio_reset) &&
1438 !aic3x_is_shared_reset(aic3x))
1418 gpio_free(aic3x->gpio_reset); 1439 gpio_free(aic3x->gpio_reset);
1419err_gpio: 1440err_gpio:
1420 kfree(aic3x);
1421 return ret; 1441 return ret;
1422} 1442}
1423 1443
@@ -1427,7 +1447,9 @@ static int aic3x_remove(struct snd_soc_codec *codec)
1427 int i; 1447 int i;
1428 1448
1429 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1449 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1430 if (aic3x->gpio_reset >= 0) { 1450 list_del(&aic3x->list);
1451 if (gpio_is_valid(aic3x->gpio_reset) &&
1452 !aic3x_is_shared_reset(aic3x)) {
1431 gpio_set_value(aic3x->gpio_reset, 0); 1453 gpio_set_value(aic3x->gpio_reset, 0);
1432 gpio_free(aic3x->gpio_reset); 1454 gpio_free(aic3x->gpio_reset);
1433 } 1455 }
@@ -1523,21 +1545,6 @@ static struct i2c_driver aic3x_i2c_driver = {
1523 .remove = aic3x_i2c_remove, 1545 .remove = aic3x_i2c_remove,
1524 .id_table = aic3x_i2c_id, 1546 .id_table = aic3x_i2c_id,
1525}; 1547};
1526
1527static inline void aic3x_i2c_init(void)
1528{
1529 int ret;
1530
1531 ret = i2c_add_driver(&aic3x_i2c_driver);
1532 if (ret)
1533 printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
1534 __func__, ret);
1535}
1536
1537static inline void aic3x_i2c_exit(void)
1538{
1539 i2c_del_driver(&aic3x_i2c_driver);
1540}
1541#endif 1548#endif
1542 1549
1543static int __init aic3x_modinit(void) 1550static int __init aic3x_modinit(void)
diff --git a/sound/soc/codecs/tlv320dac33.c b/sound/soc/codecs/tlv320dac33.c
index c5ab8c805771..71d7be8ac488 100644
--- a/sound/soc/codecs/tlv320dac33.c
+++ b/sound/soc/codecs/tlv320dac33.c
@@ -36,21 +36,21 @@
36#include <sound/pcm.h> 36#include <sound/pcm.h>
37#include <sound/pcm_params.h> 37#include <sound/pcm_params.h>
38#include <sound/soc.h> 38#include <sound/soc.h>
39#include <sound/soc-dapm.h>
40#include <sound/initval.h> 39#include <sound/initval.h>
41#include <sound/tlv.h> 40#include <sound/tlv.h>
42 41
43#include <sound/tlv320dac33-plat.h> 42#include <sound/tlv320dac33-plat.h>
44#include "tlv320dac33.h" 43#include "tlv320dac33.h"
45 44
46#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words, 45/*
47 * 6144 stereo */ 46 * The internal FIFO is 24576 bytes long
48#define DAC33_BUFFER_SIZE_SAMPLES 6144 47 * It can be configured to hold 16bit or 24bit samples
49 48 * In 16bit configuration the FIFO can hold 6144 stereo samples
50#define NSAMPLE_MAX 5700 49 * In 24bit configuration the FIFO can hold 4096 stereo samples
51 50 */
52#define MODE7_LTHR 10 51#define DAC33_FIFO_SIZE_16BIT 6144
53#define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10) 52#define DAC33_FIFO_SIZE_24BIT 4096
53#define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */
54 54
55#define BURST_BASEFREQ_HZ 49152000 55#define BURST_BASEFREQ_HZ 49152000
56 56
@@ -100,16 +100,11 @@ struct tlv320dac33_priv {
100 unsigned int refclk; 100 unsigned int refclk;
101 101
102 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */ 102 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
103 unsigned int nsample_min; /* nsample should not be lower than
104 * this */
105 unsigned int nsample_max; /* nsample should not be higher than
106 * this */
107 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */ 103 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
104 unsigned int fifo_size; /* Size of the FIFO in samples */
108 unsigned int nsample; /* burst read amount from host */ 105 unsigned int nsample; /* burst read amount from host */
109 int mode1_latency; /* latency caused by the i2c writes in 106 int mode1_latency; /* latency caused by the i2c writes in
110 * us */ 107 * us */
111 int auto_fifo_config; /* Configure the FIFO based on the
112 * period size */
113 u8 burst_bclkdiv; /* BCLK divider value in burst mode */ 108 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
114 unsigned int burst_rate; /* Interface speed in Burst modes */ 109 unsigned int burst_rate; /* Interface speed in Burst modes */
115 110
@@ -303,7 +298,6 @@ static void dac33_init_chip(struct snd_soc_codec *codec)
303 if (unlikely(!dac33->chip_power)) 298 if (unlikely(!dac33->chip_power))
304 return; 299 return;
305 300
306 /* 44-46: DAC Control Registers */
307 /* A : DAC sample rate Fsref/1.5 */ 301 /* A : DAC sample rate Fsref/1.5 */
308 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0)); 302 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
309 /* B : DAC src=normal, not muted */ 303 /* B : DAC src=normal, not muted */
@@ -316,8 +310,6 @@ static void dac33_init_chip(struct snd_soc_codec *codec)
316 clock source = internal osc (?) */ 310 clock source = internal osc (?) */
317 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN); 311 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
318 312
319 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
320
321 /* Restore only selected registers (gains mostly) */ 313 /* Restore only selected registers (gains mostly) */
322 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL, 314 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
323 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL)); 315 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
@@ -328,6 +320,10 @@ static void dac33_init_chip(struct snd_soc_codec *codec)
328 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL)); 320 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
329 dac33_write(codec, DAC33_LINER_TO_RLO_VOL, 321 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
330 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL)); 322 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
323
324 dac33_write(codec, DAC33_OUT_AMP_CTRL,
325 dac33_read_reg_cache(codec, DAC33_OUT_AMP_CTRL));
326
331} 327}
332 328
333static inline int dac33_read_id(struct snd_soc_codec *codec) 329static inline int dac33_read_id(struct snd_soc_codec *codec)
@@ -357,6 +353,21 @@ static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
357 dac33_write(codec, DAC33_PWR_CTRL, reg); 353 dac33_write(codec, DAC33_PWR_CTRL, reg);
358} 354}
359 355
356static inline void dac33_disable_digital(struct snd_soc_codec *codec)
357{
358 u8 reg;
359
360 /* Stop the DAI clock */
361 reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
362 reg &= ~DAC33_BCLKON;
363 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg);
364
365 /* Power down the Oscillator, and DACs */
366 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
367 reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
368 dac33_write(codec, DAC33_PWR_CTRL, reg);
369}
370
360static int dac33_hard_power(struct snd_soc_codec *codec, int power) 371static int dac33_hard_power(struct snd_soc_codec *codec, int power)
361{ 372{
362 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 373 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
@@ -405,7 +416,7 @@ exit:
405 return ret; 416 return ret;
406} 417}
407 418
408static int playback_event(struct snd_soc_dapm_widget *w, 419static int dac33_playback_event(struct snd_soc_dapm_widget *w,
409 struct snd_kcontrol *kcontrol, int event) 420 struct snd_kcontrol *kcontrol, int event)
410{ 421{
411 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec); 422 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
@@ -417,77 +428,13 @@ static int playback_event(struct snd_soc_dapm_widget *w,
417 dac33_prepare_chip(dac33->substream); 428 dac33_prepare_chip(dac33->substream);
418 } 429 }
419 break; 430 break;
431 case SND_SOC_DAPM_POST_PMD:
432 dac33_disable_digital(w->codec);
433 break;
420 } 434 }
421 return 0; 435 return 0;
422} 436}
423 437
424static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
425 struct snd_ctl_elem_value *ucontrol)
426{
427 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
428 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
429
430 ucontrol->value.integer.value[0] = dac33->nsample;
431
432 return 0;
433}
434
435static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
436 struct snd_ctl_elem_value *ucontrol)
437{
438 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
439 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
440 int ret = 0;
441
442 if (dac33->nsample == ucontrol->value.integer.value[0])
443 return 0;
444
445 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
446 ucontrol->value.integer.value[0] > dac33->nsample_max) {
447 ret = -EINVAL;
448 } else {
449 dac33->nsample = ucontrol->value.integer.value[0];
450 /* Re calculate the burst time */
451 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
452 dac33->nsample);
453 }
454
455 return ret;
456}
457
458static int dac33_get_uthr(struct snd_kcontrol *kcontrol,
459 struct snd_ctl_elem_value *ucontrol)
460{
461 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
462 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
463
464 ucontrol->value.integer.value[0] = dac33->uthr;
465
466 return 0;
467}
468
469static int dac33_set_uthr(struct snd_kcontrol *kcontrol,
470 struct snd_ctl_elem_value *ucontrol)
471{
472 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
473 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
474 int ret = 0;
475
476 if (dac33->substream)
477 return -EBUSY;
478
479 if (dac33->uthr == ucontrol->value.integer.value[0])
480 return 0;
481
482 if (ucontrol->value.integer.value[0] < (MODE7_LTHR + 10) ||
483 ucontrol->value.integer.value[0] > MODE7_UTHR)
484 ret = -EINVAL;
485 else
486 dac33->uthr = ucontrol->value.integer.value[0];
487
488 return ret;
489}
490
491static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol, 438static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
492 struct snd_ctl_elem_value *ucontrol) 439 struct snd_ctl_elem_value *ucontrol)
493{ 440{
@@ -572,13 +519,6 @@ static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
572 dac33_get_fifo_mode, dac33_set_fifo_mode), 519 dac33_get_fifo_mode, dac33_set_fifo_mode),
573}; 520};
574 521
575static const struct snd_kcontrol_new dac33_fifo_snd_controls[] = {
576 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
577 dac33_get_nsample, dac33_set_nsample),
578 SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR, 0,
579 dac33_get_uthr, dac33_set_uthr),
580};
581
582/* Analog bypass */ 522/* Analog bypass */
583static const struct snd_kcontrol_new dac33_dapm_abypassl_control = 523static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
584 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1); 524 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
@@ -586,6 +526,25 @@ static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
586static const struct snd_kcontrol_new dac33_dapm_abypassr_control = 526static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
587 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1); 527 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
588 528
529/* LOP L/R invert selection */
530static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"};
531
532static const struct soc_enum dac33_left_lom_enum =
533 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 3,
534 ARRAY_SIZE(dac33_lr_lom_texts),
535 dac33_lr_lom_texts);
536
537static const struct snd_kcontrol_new dac33_dapm_left_lom_control =
538SOC_DAPM_ENUM("Route", dac33_left_lom_enum);
539
540static const struct soc_enum dac33_right_lom_enum =
541 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 2,
542 ARRAY_SIZE(dac33_lr_lom_texts),
543 dac33_lr_lom_texts);
544
545static const struct snd_kcontrol_new dac33_dapm_right_lom_control =
546SOC_DAPM_ENUM("Route", dac33_right_lom_enum);
547
589static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { 548static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
590 SND_SOC_DAPM_OUTPUT("LEFT_LO"), 549 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
591 SND_SOC_DAPM_OUTPUT("RIGHT_LO"), 550 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
@@ -593,8 +552,8 @@ static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
593 SND_SOC_DAPM_INPUT("LINEL"), 552 SND_SOC_DAPM_INPUT("LINEL"),
594 SND_SOC_DAPM_INPUT("LINER"), 553 SND_SOC_DAPM_INPUT("LINER"),
595 554
596 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0), 555 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
597 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0), 556 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
598 557
599 /* Analog bypass */ 558 /* Analog bypass */
600 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0, 559 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
@@ -602,12 +561,30 @@ static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
602 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0, 561 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
603 &dac33_dapm_abypassr_control), 562 &dac33_dapm_abypassr_control),
604 563
605 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power", 564 SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0,
565 &dac33_dapm_left_lom_control),
566 SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0,
567 &dac33_dapm_right_lom_control),
568 /*
569 * For DAPM path, when only the anlog bypass path is enabled, and the
570 * LOP inverted from the corresponding DAC side.
571 * This is needed, so we can attach the DAC power supply in this case.
572 */
573 SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
574 SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
575
576 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
606 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0), 577 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
607 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power", 578 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
608 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0), 579 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
609 580
610 SND_SOC_DAPM_PRE("Prepare Playback", playback_event), 581 SND_SOC_DAPM_SUPPLY("Left DAC Power",
582 DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
583 SND_SOC_DAPM_SUPPLY("Right DAC Power",
584 DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
585
586 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
587 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
611}; 588};
612 589
613static const struct snd_soc_dapm_route audio_map[] = { 590static const struct snd_soc_dapm_route audio_map[] = {
@@ -615,24 +592,39 @@ static const struct snd_soc_dapm_route audio_map[] = {
615 {"Analog Left Bypass", "Switch", "LINEL"}, 592 {"Analog Left Bypass", "Switch", "LINEL"},
616 {"Analog Right Bypass", "Switch", "LINER"}, 593 {"Analog Right Bypass", "Switch", "LINER"},
617 594
618 {"Output Left Amp Power", NULL, "DACL"}, 595 {"Output Left Amplifier", NULL, "DACL"},
619 {"Output Right Amp Power", NULL, "DACR"}, 596 {"Output Right Amplifier", NULL, "DACR"},
620 597
621 {"Output Left Amp Power", NULL, "Analog Left Bypass"}, 598 {"Left Bypass PGA", NULL, "Analog Left Bypass"},
622 {"Output Right Amp Power", NULL, "Analog Right Bypass"}, 599 {"Right Bypass PGA", NULL, "Analog Right Bypass"},
600
601 {"Left LOM Inverted From", "DAC", "Left Bypass PGA"},
602 {"Right LOM Inverted From", "DAC", "Right Bypass PGA"},
603 {"Left LOM Inverted From", "LOP", "Analog Left Bypass"},
604 {"Right LOM Inverted From", "LOP", "Analog Right Bypass"},
605
606 {"Output Left Amplifier", NULL, "Left LOM Inverted From"},
607 {"Output Right Amplifier", NULL, "Right LOM Inverted From"},
608
609 {"DACL", NULL, "Left DAC Power"},
610 {"DACR", NULL, "Right DAC Power"},
611
612 {"Left Bypass PGA", NULL, "Left DAC Power"},
613 {"Right Bypass PGA", NULL, "Right DAC Power"},
623 614
624 /* output */ 615 /* output */
625 {"LEFT_LO", NULL, "Output Left Amp Power"}, 616 {"LEFT_LO", NULL, "Output Left Amplifier"},
626 {"RIGHT_LO", NULL, "Output Right Amp Power"}, 617 {"RIGHT_LO", NULL, "Output Right Amplifier"},
627}; 618};
628 619
629static int dac33_add_widgets(struct snd_soc_codec *codec) 620static int dac33_add_widgets(struct snd_soc_codec *codec)
630{ 621{
631 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets, 622 struct snd_soc_dapm_context *dapm = &codec->dapm;
632 ARRAY_SIZE(dac33_dapm_widgets));
633 623
624 snd_soc_dapm_new_controls(dapm, dac33_dapm_widgets,
625 ARRAY_SIZE(dac33_dapm_widgets));
634 /* set up audio path interconnects */ 626 /* set up audio path interconnects */
635 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 627 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
636 628
637 return 0; 629 return 0;
638} 630}
@@ -640,16 +632,18 @@ static int dac33_add_widgets(struct snd_soc_codec *codec)
640static int dac33_set_bias_level(struct snd_soc_codec *codec, 632static int dac33_set_bias_level(struct snd_soc_codec *codec,
641 enum snd_soc_bias_level level) 633 enum snd_soc_bias_level level)
642{ 634{
635 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
643 int ret; 636 int ret;
644 637
645 switch (level) { 638 switch (level) {
646 case SND_SOC_BIAS_ON: 639 case SND_SOC_BIAS_ON:
647 dac33_soft_power(codec, 1); 640 if (!dac33->substream)
641 dac33_soft_power(codec, 1);
648 break; 642 break;
649 case SND_SOC_BIAS_PREPARE: 643 case SND_SOC_BIAS_PREPARE:
650 break; 644 break;
651 case SND_SOC_BIAS_STANDBY: 645 case SND_SOC_BIAS_STANDBY:
652 if (codec->bias_level == SND_SOC_BIAS_OFF) { 646 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
653 /* Coming from OFF, switch on the codec */ 647 /* Coming from OFF, switch on the codec */
654 ret = dac33_hard_power(codec, 1); 648 ret = dac33_hard_power(codec, 1);
655 if (ret != 0) 649 if (ret != 0)
@@ -660,14 +654,14 @@ static int dac33_set_bias_level(struct snd_soc_codec *codec,
660 break; 654 break;
661 case SND_SOC_BIAS_OFF: 655 case SND_SOC_BIAS_OFF:
662 /* Do not power off, when the codec is already off */ 656 /* Do not power off, when the codec is already off */
663 if (codec->bias_level == SND_SOC_BIAS_OFF) 657 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
664 return 0; 658 return 0;
665 ret = dac33_hard_power(codec, 0); 659 ret = dac33_hard_power(codec, 0);
666 if (ret != 0) 660 if (ret != 0)
667 return ret; 661 return ret;
668 break; 662 break;
669 } 663 }
670 codec->bias_level = level; 664 codec->dapm.bias_level = level;
671 665
672 return 0; 666 return 0;
673} 667}
@@ -705,7 +699,7 @@ static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
705 spin_unlock_irq(&dac33->lock); 699 spin_unlock_irq(&dac33->lock);
706 700
707 dac33_write16(codec, DAC33_PREFILL_MSB, 701 dac33_write16(codec, DAC33_PREFILL_MSB,
708 DAC33_THRREG(MODE7_LTHR)); 702 DAC33_THRREG(DAC33_MODE7_MARGIN));
709 703
710 /* Enable Upper Threshold IRQ */ 704 /* Enable Upper Threshold IRQ */
711 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT); 705 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
@@ -815,6 +809,8 @@ static int dac33_startup(struct snd_pcm_substream *substream,
815 /* Stream started, save the substream pointer */ 809 /* Stream started, save the substream pointer */
816 dac33->substream = substream; 810 dac33->substream = substream;
817 811
812 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24);
813
818 return 0; 814 return 0;
819} 815}
820 816
@@ -826,18 +822,17 @@ static void dac33_shutdown(struct snd_pcm_substream *substream,
826 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 822 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
827 823
828 dac33->substream = NULL; 824 dac33->substream = NULL;
829
830 /* Reset the nSample restrictions */
831 dac33->nsample_min = 0;
832 dac33->nsample_max = NSAMPLE_MAX;
833} 825}
834 826
827#define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
828 (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
835static int dac33_hw_params(struct snd_pcm_substream *substream, 829static int dac33_hw_params(struct snd_pcm_substream *substream,
836 struct snd_pcm_hw_params *params, 830 struct snd_pcm_hw_params *params,
837 struct snd_soc_dai *dai) 831 struct snd_soc_dai *dai)
838{ 832{
839 struct snd_soc_pcm_runtime *rtd = substream->private_data; 833 struct snd_soc_pcm_runtime *rtd = substream->private_data;
840 struct snd_soc_codec *codec = rtd->codec; 834 struct snd_soc_codec *codec = rtd->codec;
835 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
841 836
842 /* Check parameters for validity */ 837 /* Check parameters for validity */
843 switch (params_rate(params)) { 838 switch (params_rate(params)) {
@@ -852,6 +847,12 @@ static int dac33_hw_params(struct snd_pcm_substream *substream,
852 847
853 switch (params_format(params)) { 848 switch (params_format(params)) {
854 case SNDRV_PCM_FORMAT_S16_LE: 849 case SNDRV_PCM_FORMAT_S16_LE:
850 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT;
851 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32);
852 break;
853 case SNDRV_PCM_FORMAT_S32_LE:
854 dac33->fifo_size = DAC33_FIFO_SIZE_24BIT;
855 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64);
855 break; 856 break;
856 default: 857 default:
857 dev_err(codec->dev, "unsupported format %d\n", 858 dev_err(codec->dev, "unsupported format %d\n",
@@ -906,6 +907,9 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
906 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16); 907 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
907 fifoctrl_a |= DAC33_WIDTH; 908 fifoctrl_a |= DAC33_WIDTH;
908 break; 909 break;
910 case SNDRV_PCM_FORMAT_S32_LE:
911 aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24);
912 break;
909 default: 913 default:
910 dev_err(codec->dev, "unsupported format %d\n", 914 dev_err(codec->dev, "unsupported format %d\n",
911 substream->runtime->format); 915 substream->runtime->format);
@@ -1040,7 +1044,10 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
1040 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 1044 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1041 dac33->burst_bclkdiv); 1045 dac33->burst_bclkdiv);
1042 else 1046 else
1043 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32); 1047 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
1048 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
1049 else
1050 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16);
1044 1051
1045 switch (dac33->fifo_mode) { 1052 switch (dac33->fifo_mode) {
1046 case DAC33_FIFO_MODE1: 1053 case DAC33_FIFO_MODE1:
@@ -1053,7 +1060,8 @@ static int dac33_prepare_chip(struct snd_pcm_substream *substream)
1053 * at the bottom, and also at the top of the FIFO 1060 * at the bottom, and also at the top of the FIFO
1054 */ 1061 */
1055 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr)); 1062 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
1056 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR)); 1063 dac33_write16(codec, DAC33_LTHR_MSB,
1064 DAC33_THRREG(DAC33_MODE7_MARGIN));
1057 break; 1065 break;
1058 default: 1066 default:
1059 break; 1067 break;
@@ -1082,42 +1090,21 @@ static void dac33_calculate_times(struct snd_pcm_substream *substream)
1082 /* Number of samples under i2c latency */ 1090 /* Number of samples under i2c latency */
1083 dac33->alarm_threshold = US_TO_SAMPLES(rate, 1091 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1084 dac33->mode1_latency); 1092 dac33->mode1_latency);
1085 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - 1093 nsample_limit = dac33->fifo_size - dac33->alarm_threshold;
1086 dac33->alarm_threshold; 1094
1087 1095 if (period_size <= dac33->alarm_threshold)
1088 if (dac33->auto_fifo_config) {
1089 if (period_size <= dac33->alarm_threshold)
1090 /*
1091 * Configure nSamaple to number of periods,
1092 * which covers the latency requironment.
1093 */
1094 dac33->nsample = period_size *
1095 ((dac33->alarm_threshold / period_size) +
1096 (dac33->alarm_threshold % period_size ?
1097 1 : 0));
1098 else if (period_size > nsample_limit)
1099 dac33->nsample = nsample_limit;
1100 else
1101 dac33->nsample = period_size;
1102 } else {
1103 /* nSample time shall not be shorter than i2c latency */
1104 dac33->nsample_min = dac33->alarm_threshold;
1105 /* 1096 /*
1106 * nSample should not be bigger than alsa buffer minus 1097 * Configure nSamaple to number of periods,
1107 * size of one period to avoid overruns 1098 * which covers the latency requironment.
1108 */ 1099 */
1109 dac33->nsample_max = substream->runtime->buffer_size - 1100 dac33->nsample = period_size *
1110 period_size; 1101 ((dac33->alarm_threshold / period_size) +
1111 1102 (dac33->alarm_threshold % period_size ?
1112 if (dac33->nsample_max > nsample_limit) 1103 1 : 0));
1113 dac33->nsample_max = nsample_limit; 1104 else if (period_size > nsample_limit)
1114 1105 dac33->nsample = nsample_limit;
1115 /* Correct the nSample if it is outside of the ranges */ 1106 else
1116 if (dac33->nsample < dac33->nsample_min) 1107 dac33->nsample = period_size;
1117 dac33->nsample = dac33->nsample_min;
1118 if (dac33->nsample > dac33->nsample_max)
1119 dac33->nsample = dac33->nsample_max;
1120 }
1121 1108
1122 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate, 1109 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1123 dac33->nsample); 1110 dac33->nsample);
@@ -1125,19 +1112,16 @@ static void dac33_calculate_times(struct snd_pcm_substream *substream)
1125 dac33->t_stamp2 = 0; 1112 dac33->t_stamp2 = 0;
1126 break; 1113 break;
1127 case DAC33_FIFO_MODE7: 1114 case DAC33_FIFO_MODE7:
1128 if (dac33->auto_fifo_config) { 1115 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
1129 dac33->uthr = UTHR_FROM_PERIOD_SIZE( 1116 dac33->burst_rate) + 9;
1130 period_size, 1117 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN))
1131 rate, 1118 dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN;
1132 dac33->burst_rate) + 9; 1119 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10))
1133 if (dac33->uthr > MODE7_UTHR) 1120 dac33->uthr = (DAC33_MODE7_MARGIN + 10);
1134 dac33->uthr = MODE7_UTHR; 1121
1135 if (dac33->uthr < (MODE7_LTHR + 10))
1136 dac33->uthr = (MODE7_LTHR + 10);
1137 }
1138 dac33->mode7_us_to_lthr = 1122 dac33->mode7_us_to_lthr =
1139 SAMPLES_TO_US(substream->runtime->rate, 1123 SAMPLES_TO_US(substream->runtime->rate,
1140 dac33->uthr - MODE7_LTHR + 1); 1124 dac33->uthr - DAC33_MODE7_MARGIN + 1);
1141 dac33->t_stamp1 = 0; 1125 dac33->t_stamp1 = 0;
1142 break; 1126 break;
1143 default: 1127 default:
@@ -1255,8 +1239,8 @@ static snd_pcm_sframes_t dac33_dai_delay(
1255 samples += (samples_in - samples_out); 1239 samples += (samples_in - samples_out);
1256 1240
1257 if (likely(samples > 0)) 1241 if (likely(samples > 0))
1258 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ? 1242 delay = samples > dac33->fifo_size ?
1259 DAC33_BUFFER_SIZE_SAMPLES : samples; 1243 dac33->fifo_size : samples;
1260 else 1244 else
1261 delay = 0; 1245 delay = 0;
1262 } 1246 }
@@ -1308,7 +1292,7 @@ static snd_pcm_sframes_t dac33_dai_delay(
1308 samples_in = US_TO_SAMPLES( 1292 samples_in = US_TO_SAMPLES(
1309 dac33->burst_rate, 1293 dac33->burst_rate,
1310 time_delta); 1294 time_delta);
1311 delay = MODE7_LTHR + samples_in - samples_out; 1295 delay = DAC33_MODE7_MARGIN + samples_in - samples_out;
1312 1296
1313 if (unlikely(delay > uthr)) 1297 if (unlikely(delay > uthr))
1314 delay = uthr; 1298 delay = uthr;
@@ -1415,7 +1399,7 @@ static int dac33_soc_probe(struct snd_soc_codec *codec)
1415 1399
1416 codec->control_data = dac33->control_data; 1400 codec->control_data = dac33->control_data;
1417 codec->hw_write = (hw_write_t) i2c_master_send; 1401 codec->hw_write = (hw_write_t) i2c_master_send;
1418 codec->idle_bias_off = 1; 1402 codec->dapm.idle_bias_off = 1;
1419 dac33->codec = codec; 1403 dac33->codec = codec;
1420 1404
1421 /* Read the tlv320dac33 ID registers */ 1405 /* Read the tlv320dac33 ID registers */
@@ -1459,14 +1443,10 @@ static int dac33_soc_probe(struct snd_soc_codec *codec)
1459 snd_soc_add_controls(codec, dac33_snd_controls, 1443 snd_soc_add_controls(codec, dac33_snd_controls,
1460 ARRAY_SIZE(dac33_snd_controls)); 1444 ARRAY_SIZE(dac33_snd_controls));
1461 /* Only add the FIFO controls, if we have valid IRQ number */ 1445 /* Only add the FIFO controls, if we have valid IRQ number */
1462 if (dac33->irq >= 0) { 1446 if (dac33->irq >= 0)
1463 snd_soc_add_controls(codec, dac33_mode_snd_controls, 1447 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1464 ARRAY_SIZE(dac33_mode_snd_controls)); 1448 ARRAY_SIZE(dac33_mode_snd_controls));
1465 /* FIFO usage controls only, if autoio config is not selected */ 1449
1466 if (!dac33->auto_fifo_config)
1467 snd_soc_add_controls(codec, dac33_fifo_snd_controls,
1468 ARRAY_SIZE(dac33_fifo_snd_controls));
1469 }
1470 dac33_add_widgets(codec); 1450 dac33_add_widgets(codec);
1471 1451
1472err_power: 1452err_power:
@@ -1515,7 +1495,7 @@ static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1515 1495
1516#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \ 1496#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1517 SNDRV_PCM_RATE_48000) 1497 SNDRV_PCM_RATE_48000)
1518#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE 1498#define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1519 1499
1520static struct snd_soc_dai_ops dac33_dai_ops = { 1500static struct snd_soc_dai_ops dac33_dai_ops = {
1521 .startup = dac33_startup, 1501 .startup = dac33_startup,
@@ -1563,17 +1543,11 @@ static int __devinit dac33_i2c_probe(struct i2c_client *client,
1563 1543
1564 dac33->power_gpio = pdata->power_gpio; 1544 dac33->power_gpio = pdata->power_gpio;
1565 dac33->burst_bclkdiv = pdata->burst_bclkdiv; 1545 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1566 /* Pre calculate the burst rate */
1567 dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
1568 dac33->keep_bclk = pdata->keep_bclk; 1546 dac33->keep_bclk = pdata->keep_bclk;
1569 dac33->auto_fifo_config = pdata->auto_fifo_config;
1570 dac33->mode1_latency = pdata->mode1_latency; 1547 dac33->mode1_latency = pdata->mode1_latency;
1571 if (!dac33->mode1_latency) 1548 if (!dac33->mode1_latency)
1572 dac33->mode1_latency = 10000; /* 10ms */ 1549 dac33->mode1_latency = 10000; /* 10ms */
1573 dac33->irq = client->irq; 1550 dac33->irq = client->irq;
1574 dac33->nsample = NSAMPLE_MAX;
1575 dac33->nsample_max = NSAMPLE_MAX;
1576 dac33->uthr = MODE7_UTHR;
1577 /* Disable FIFO use by default */ 1551 /* Disable FIFO use by default */
1578 dac33->fifo_mode = DAC33_FIFO_BYPASS; 1552 dac33->fifo_mode = DAC33_FIFO_BYPASS;
1579 1553
diff --git a/sound/soc/codecs/tpa6130a2.c b/sound/soc/codecs/tpa6130a2.c
index d2c243095673..1f1ac8110bef 100644
--- a/sound/soc/codecs/tpa6130a2.c
+++ b/sound/soc/codecs/tpa6130a2.c
@@ -29,7 +29,6 @@
29#include <linux/slab.h> 29#include <linux/slab.h>
30#include <sound/tpa6130a2-plat.h> 30#include <sound/tpa6130a2-plat.h>
31#include <sound/soc.h> 31#include <sound/soc.h>
32#include <sound/soc-dapm.h>
33#include <sound/tlv.h> 32#include <sound/tlv.h>
34 33
35#include "tpa6130a2.h" 34#include "tpa6130a2.h"
@@ -42,7 +41,7 @@ struct tpa6130a2_data {
42 unsigned char regs[TPA6130A2_CACHEREGNUM]; 41 unsigned char regs[TPA6130A2_CACHEREGNUM];
43 struct regulator *supply; 42 struct regulator *supply;
44 int power_gpio; 43 int power_gpio;
45 unsigned char power_state; 44 u8 power_state:1;
46 enum tpa_model id; 45 enum tpa_model id;
47}; 46};
48 47
@@ -117,7 +116,7 @@ static int tpa6130a2_initialize(void)
117 return ret; 116 return ret;
118} 117}
119 118
120static int tpa6130a2_power(int power) 119static int tpa6130a2_power(u8 power)
121{ 120{
122 struct tpa6130a2_data *data; 121 struct tpa6130a2_data *data;
123 u8 val; 122 u8 val;
@@ -127,17 +126,19 @@ static int tpa6130a2_power(int power)
127 data = i2c_get_clientdata(tpa6130a2_client); 126 data = i2c_get_clientdata(tpa6130a2_client);
128 127
129 mutex_lock(&data->mutex); 128 mutex_lock(&data->mutex);
130 if (power && !data->power_state) { 129 if (power == data->power_state)
131 /* Power on */ 130 goto exit;
132 if (data->power_gpio >= 0)
133 gpio_set_value(data->power_gpio, 1);
134 131
132 if (power) {
135 ret = regulator_enable(data->supply); 133 ret = regulator_enable(data->supply);
136 if (ret != 0) { 134 if (ret != 0) {
137 dev_err(&tpa6130a2_client->dev, 135 dev_err(&tpa6130a2_client->dev,
138 "Failed to enable supply: %d\n", ret); 136 "Failed to enable supply: %d\n", ret);
139 goto exit; 137 goto exit;
140 } 138 }
139 /* Power on */
140 if (data->power_gpio >= 0)
141 gpio_set_value(data->power_gpio, 1);
141 142
142 data->power_state = 1; 143 data->power_state = 1;
143 ret = tpa6130a2_initialize(); 144 ret = tpa6130a2_initialize();
@@ -150,12 +151,7 @@ static int tpa6130a2_power(int power)
150 data->power_state = 0; 151 data->power_state = 0;
151 goto exit; 152 goto exit;
152 } 153 }
153 154 } else {
154 /* Clear SWS */
155 val = tpa6130a2_read(TPA6130A2_REG_CONTROL);
156 val &= ~TPA6130A2_SWS;
157 tpa6130a2_i2c_write(TPA6130A2_REG_CONTROL, val);
158 } else if (!power && data->power_state) {
159 /* set SWS */ 155 /* set SWS */
160 val = tpa6130a2_read(TPA6130A2_REG_CONTROL); 156 val = tpa6130a2_read(TPA6130A2_REG_CONTROL);
161 val |= TPA6130A2_SWS; 157 val |= TPA6130A2_SWS;
@@ -300,6 +296,7 @@ static void tpa6130a2_channel_enable(u8 channel, int enable)
300 /* Enable amplifier */ 296 /* Enable amplifier */
301 val = tpa6130a2_read(TPA6130A2_REG_CONTROL); 297 val = tpa6130a2_read(TPA6130A2_REG_CONTROL);
302 val |= channel; 298 val |= channel;
299 val &= ~TPA6130A2_SWS;
303 tpa6130a2_i2c_write(TPA6130A2_REG_CONTROL, val); 300 tpa6130a2_i2c_write(TPA6130A2_REG_CONTROL, val);
304 301
305 /* Unmute channel */ 302 /* Unmute channel */
@@ -320,72 +317,24 @@ static void tpa6130a2_channel_enable(u8 channel, int enable)
320 } 317 }
321} 318}
322 319
323static int tpa6130a2_left_event(struct snd_soc_dapm_widget *w, 320int tpa6130a2_stereo_enable(struct snd_soc_codec *codec, int enable)
324 struct snd_kcontrol *kcontrol, int event)
325{
326 switch (event) {
327 case SND_SOC_DAPM_POST_PMU:
328 tpa6130a2_channel_enable(TPA6130A2_HP_EN_L, 1);
329 break;
330 case SND_SOC_DAPM_POST_PMD:
331 tpa6130a2_channel_enable(TPA6130A2_HP_EN_L, 0);
332 break;
333 }
334 return 0;
335}
336
337static int tpa6130a2_right_event(struct snd_soc_dapm_widget *w,
338 struct snd_kcontrol *kcontrol, int event)
339{
340 switch (event) {
341 case SND_SOC_DAPM_POST_PMU:
342 tpa6130a2_channel_enable(TPA6130A2_HP_EN_R, 1);
343 break;
344 case SND_SOC_DAPM_POST_PMD:
345 tpa6130a2_channel_enable(TPA6130A2_HP_EN_R, 0);
346 break;
347 }
348 return 0;
349}
350
351static int tpa6130a2_supply_event(struct snd_soc_dapm_widget *w,
352 struct snd_kcontrol *kcontrol, int event)
353{ 321{
354 int ret = 0; 322 int ret = 0;
355 323 if (enable) {
356 switch (event) {
357 case SND_SOC_DAPM_POST_PMU:
358 ret = tpa6130a2_power(1); 324 ret = tpa6130a2_power(1);
359 break; 325 if (ret < 0)
360 case SND_SOC_DAPM_POST_PMD: 326 return ret;
327 tpa6130a2_channel_enable(TPA6130A2_HP_EN_R | TPA6130A2_HP_EN_L,
328 1);
329 } else {
330 tpa6130a2_channel_enable(TPA6130A2_HP_EN_R | TPA6130A2_HP_EN_L,
331 0);
361 ret = tpa6130a2_power(0); 332 ret = tpa6130a2_power(0);
362 break;
363 } 333 }
334
364 return ret; 335 return ret;
365} 336}
366 337EXPORT_SYMBOL_GPL(tpa6130a2_stereo_enable);
367static const struct snd_soc_dapm_widget tpa6130a2_dapm_widgets[] = {
368 SND_SOC_DAPM_PGA_E("TPA6130A2 Left", SND_SOC_NOPM,
369 0, 0, NULL, 0, tpa6130a2_left_event,
370 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
371 SND_SOC_DAPM_PGA_E("TPA6130A2 Right", SND_SOC_NOPM,
372 0, 0, NULL, 0, tpa6130a2_right_event,
373 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
374 SND_SOC_DAPM_SUPPLY("TPA6130A2 Enable", SND_SOC_NOPM,
375 0, 0, tpa6130a2_supply_event,
376 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
377 /* Outputs */
378 SND_SOC_DAPM_OUTPUT("TPA6130A2 Headphone Left"),
379 SND_SOC_DAPM_OUTPUT("TPA6130A2 Headphone Right"),
380};
381
382static const struct snd_soc_dapm_route audio_map[] = {
383 {"TPA6130A2 Headphone Left", NULL, "TPA6130A2 Left"},
384 {"TPA6130A2 Headphone Right", NULL, "TPA6130A2 Right"},
385
386 {"TPA6130A2 Headphone Left", NULL, "TPA6130A2 Enable"},
387 {"TPA6130A2 Headphone Right", NULL, "TPA6130A2 Enable"},
388};
389 338
390int tpa6130a2_add_controls(struct snd_soc_codec *codec) 339int tpa6130a2_add_controls(struct snd_soc_codec *codec)
391{ 340{
@@ -396,18 +345,12 @@ int tpa6130a2_add_controls(struct snd_soc_codec *codec)
396 345
397 data = i2c_get_clientdata(tpa6130a2_client); 346 data = i2c_get_clientdata(tpa6130a2_client);
398 347
399 snd_soc_dapm_new_controls(codec, tpa6130a2_dapm_widgets,
400 ARRAY_SIZE(tpa6130a2_dapm_widgets));
401
402 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
403
404 if (data->id == TPA6140A2) 348 if (data->id == TPA6140A2)
405 return snd_soc_add_controls(codec, tpa6140a2_controls, 349 return snd_soc_add_controls(codec, tpa6140a2_controls,
406 ARRAY_SIZE(tpa6140a2_controls)); 350 ARRAY_SIZE(tpa6140a2_controls));
407 else 351 else
408 return snd_soc_add_controls(codec, tpa6130a2_controls, 352 return snd_soc_add_controls(codec, tpa6130a2_controls,
409 ARRAY_SIZE(tpa6130a2_controls)); 353 ARRAY_SIZE(tpa6130a2_controls));
410
411} 354}
412EXPORT_SYMBOL_GPL(tpa6130a2_add_controls); 355EXPORT_SYMBOL_GPL(tpa6130a2_add_controls);
413 356
diff --git a/sound/soc/codecs/tpa6130a2.h b/sound/soc/codecs/tpa6130a2.h
index 57e867fd86d1..5df49c8756b2 100644
--- a/sound/soc/codecs/tpa6130a2.h
+++ b/sound/soc/codecs/tpa6130a2.h
@@ -57,5 +57,6 @@
57#define TPA6130A2_VERSION_MASK (0x0f) 57#define TPA6130A2_VERSION_MASK (0x0f)
58 58
59extern int tpa6130a2_add_controls(struct snd_soc_codec *codec); 59extern int tpa6130a2_add_controls(struct snd_soc_codec *codec);
60extern int tpa6130a2_stereo_enable(struct snd_soc_codec *codec, int enable);
60 61
61#endif /* __TPA6130A2_H__ */ 62#endif /* __TPA6130A2_H__ */
diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index cbebec6ba1ba..e4d464b937d6 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -32,7 +32,6 @@
32#include <sound/pcm.h> 32#include <sound/pcm.h>
33#include <sound/pcm_params.h> 33#include <sound/pcm_params.h>
34#include <sound/soc.h> 34#include <sound/soc.h>
35#include <sound/soc-dapm.h>
36#include <sound/initval.h> 35#include <sound/initval.h>
37#include <sound/tlv.h> 36#include <sound/tlv.h>
38 37
@@ -233,6 +232,16 @@ static int twl4030_write(struct snd_soc_codec *codec,
233 return 0; 232 return 0;
234} 233}
235 234
235static inline void twl4030_wait_ms(int time)
236{
237 if (time < 60) {
238 time *= 1000;
239 usleep_range(time, time + 500);
240 } else {
241 msleep(time);
242 }
243}
244
236static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable) 245static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
237{ 246{
238 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); 247 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
@@ -338,10 +347,14 @@ static void twl4030_init_chip(struct snd_soc_codec *codec)
338 twl4030_write(codec, TWL4030_REG_ANAMICL, 347 twl4030_write(codec, TWL4030_REG_ANAMICL,
339 reg | TWL4030_CNCL_OFFSET_START); 348 reg | TWL4030_CNCL_OFFSET_START);
340 349
341 /* wait for offset cancellation to complete */ 350 /*
351 * Wait for offset cancellation to complete.
352 * Since this takes a while, do not slam the i2c.
353 * Start polling the status after ~20ms.
354 */
355 msleep(20);
342 do { 356 do {
343 /* this takes a little while, so don't slam i2c */ 357 usleep_range(1000, 2000);
344 udelay(2000);
345 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, 358 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
346 TWL4030_REG_ANAMICL); 359 TWL4030_REG_ANAMICL);
347 } while ((i++ < 100) && 360 } while ((i++ < 100) &&
@@ -725,9 +738,12 @@ static void headset_ramp(struct snd_soc_codec *codec, int ramp)
725 /* Base values for ramp delay calculation: 2^19 - 2^26 */ 738 /* Base values for ramp delay calculation: 2^19 - 2^26 */
726 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304, 739 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
727 8388608, 16777216, 33554432, 67108864}; 740 8388608, 16777216, 33554432, 67108864};
741 unsigned int delay;
728 742
729 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET); 743 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
730 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET); 744 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
745 delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
746 twl4030->sysclk) + 1;
731 747
732 /* Enable external mute control, this dramatically reduces 748 /* Enable external mute control, this dramatically reduces
733 * the pop-noise */ 749 * the pop-noise */
@@ -751,16 +767,14 @@ static void headset_ramp(struct snd_soc_codec *codec, int ramp)
751 hs_pop |= TWL4030_RAMP_EN; 767 hs_pop |= TWL4030_RAMP_EN;
752 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); 768 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
753 /* Wait ramp delay time + 1, so the VMID can settle */ 769 /* Wait ramp delay time + 1, so the VMID can settle */
754 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] / 770 twl4030_wait_ms(delay);
755 twl4030->sysclk) + 1);
756 } else { 771 } else {
757 /* Headset ramp-down _not_ according to 772 /* Headset ramp-down _not_ according to
758 * the TRM, but in a way that it is working */ 773 * the TRM, but in a way that it is working */
759 hs_pop &= ~TWL4030_RAMP_EN; 774 hs_pop &= ~TWL4030_RAMP_EN;
760 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); 775 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
761 /* Wait ramp delay time + 1, so the VMID can settle */ 776 /* Wait ramp delay time + 1, so the VMID can settle */
762 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] / 777 twl4030_wait_ms(delay);
763 twl4030->sysclk) + 1);
764 /* Bypass the reg_cache to mute the headset */ 778 /* Bypass the reg_cache to mute the headset */
765 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 779 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
766 hs_gain & (~0x0f), 780 hs_gain & (~0x0f),
@@ -835,7 +849,7 @@ static int digimic_event(struct snd_soc_dapm_widget *w,
835 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); 849 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
836 850
837 if (twl4030->digimic_delay) 851 if (twl4030->digimic_delay)
838 mdelay(twl4030->digimic_delay); 852 twl4030_wait_ms(twl4030->digimic_delay);
839 return 0; 853 return 0;
840} 854}
841 855
@@ -1621,10 +1635,11 @@ static const struct snd_soc_dapm_route intercon[] = {
1621 1635
1622static int twl4030_add_widgets(struct snd_soc_codec *codec) 1636static int twl4030_add_widgets(struct snd_soc_codec *codec)
1623{ 1637{
1624 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets, 1638 struct snd_soc_dapm_context *dapm = &codec->dapm;
1625 ARRAY_SIZE(twl4030_dapm_widgets));
1626 1639
1627 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 1640 snd_soc_dapm_new_controls(dapm, twl4030_dapm_widgets,
1641 ARRAY_SIZE(twl4030_dapm_widgets));
1642 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
1628 1643
1629 return 0; 1644 return 0;
1630} 1645}
@@ -1638,14 +1653,14 @@ static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1638 case SND_SOC_BIAS_PREPARE: 1653 case SND_SOC_BIAS_PREPARE:
1639 break; 1654 break;
1640 case SND_SOC_BIAS_STANDBY: 1655 case SND_SOC_BIAS_STANDBY:
1641 if (codec->bias_level == SND_SOC_BIAS_OFF) 1656 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1642 twl4030_codec_enable(codec, 1); 1657 twl4030_codec_enable(codec, 1);
1643 break; 1658 break;
1644 case SND_SOC_BIAS_OFF: 1659 case SND_SOC_BIAS_OFF:
1645 twl4030_codec_enable(codec, 0); 1660 twl4030_codec_enable(codec, 0);
1646 break; 1661 break;
1647 } 1662 }
1648 codec->bias_level = level; 1663 codec->dapm.bias_level = level;
1649 1664
1650 return 0; 1665 return 0;
1651} 1666}
@@ -1709,6 +1724,7 @@ static int twl4030_startup(struct snd_pcm_substream *substream,
1709 struct snd_soc_codec *codec = rtd->codec; 1724 struct snd_soc_codec *codec = rtd->codec;
1710 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); 1725 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1711 1726
1727 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24);
1712 if (twl4030->master_substream) { 1728 if (twl4030->master_substream) {
1713 twl4030->slave_substream = substream; 1729 twl4030->slave_substream = substream;
1714 /* The DAI has one configuration for playback and capture, so 1730 /* The DAI has one configuration for playback and capture, so
@@ -1833,7 +1849,7 @@ static int twl4030_hw_params(struct snd_pcm_substream *substream,
1833 case SNDRV_PCM_FORMAT_S16_LE: 1849 case SNDRV_PCM_FORMAT_S16_LE:
1834 format |= TWL4030_DATA_WIDTH_16S_16W; 1850 format |= TWL4030_DATA_WIDTH_16S_16W;
1835 break; 1851 break;
1836 case SNDRV_PCM_FORMAT_S24_LE: 1852 case SNDRV_PCM_FORMAT_S32_LE:
1837 format |= TWL4030_DATA_WIDTH_32S_24W; 1853 format |= TWL4030_DATA_WIDTH_32S_24W;
1838 break; 1854 break;
1839 default: 1855 default:
@@ -2166,7 +2182,7 @@ static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2166} 2182}
2167 2183
2168#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000) 2184#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
2169#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE) 2185#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2170 2186
2171static struct snd_soc_dai_ops twl4030_dai_hifi_ops = { 2187static struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
2172 .startup = twl4030_startup, 2188 .startup = twl4030_startup,
@@ -2245,7 +2261,7 @@ static int twl4030_soc_probe(struct snd_soc_codec *codec)
2245 snd_soc_codec_set_drvdata(codec, twl4030); 2261 snd_soc_codec_set_drvdata(codec, twl4030);
2246 /* Set the defaults, and power up the codec */ 2262 /* Set the defaults, and power up the codec */
2247 twl4030->sysclk = twl4030_codec_get_mclk() / 1000; 2263 twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
2248 codec->idle_bias_off = 1; 2264 codec->dapm.idle_bias_off = 1;
2249 2265
2250 twl4030_init_chip(codec); 2266 twl4030_init_chip(codec);
2251 2267
@@ -2257,9 +2273,12 @@ static int twl4030_soc_probe(struct snd_soc_codec *codec)
2257 2273
2258static int twl4030_soc_remove(struct snd_soc_codec *codec) 2274static int twl4030_soc_remove(struct snd_soc_codec *codec)
2259{ 2275{
2276 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2277
2260 /* Reset registers to their chip default before leaving */ 2278 /* Reset registers to their chip default before leaving */
2261 twl4030_reset_registers(codec); 2279 twl4030_reset_registers(codec);
2262 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); 2280 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2281 kfree(twl4030);
2263 return 0; 2282 return 0;
2264} 2283}
2265 2284
@@ -2291,10 +2310,7 @@ static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2291 2310
2292static int __devexit twl4030_codec_remove(struct platform_device *pdev) 2311static int __devexit twl4030_codec_remove(struct platform_device *pdev)
2293{ 2312{
2294 struct twl4030_priv *twl4030 = dev_get_drvdata(&pdev->dev);
2295
2296 snd_soc_unregister_codec(&pdev->dev); 2313 snd_soc_unregister_codec(&pdev->dev);
2297 kfree(twl4030);
2298 return 0; 2314 return 0;
2299} 2315}
2300 2316
diff --git a/sound/soc/codecs/twl6040.c b/sound/soc/codecs/twl6040.c
index 10f6e5214511..4bbf1b15a493 100644
--- a/sound/soc/codecs/twl6040.c
+++ b/sound/soc/codecs/twl6040.c
@@ -34,14 +34,46 @@
34#include <sound/pcm.h> 34#include <sound/pcm.h>
35#include <sound/pcm_params.h> 35#include <sound/pcm_params.h>
36#include <sound/soc.h> 36#include <sound/soc.h>
37#include <sound/soc-dapm.h>
38#include <sound/initval.h> 37#include <sound/initval.h>
39#include <sound/tlv.h> 38#include <sound/tlv.h>
40 39
41#include "twl6040.h" 40#include "twl6040.h"
42 41
43#define TWL6040_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) 42#define TWL6040_RATES SNDRV_PCM_RATE_8000_96000
44#define TWL6040_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) 43#define TWL6040_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
44
45#define TWL6040_OUTHS_0dB 0x00
46#define TWL6040_OUTHS_M30dB 0x0F
47#define TWL6040_OUTHF_0dB 0x03
48#define TWL6040_OUTHF_M52dB 0x1D
49
50#define TWL6040_RAMP_NONE 0
51#define TWL6040_RAMP_UP 1
52#define TWL6040_RAMP_DOWN 2
53
54#define TWL6040_HSL_VOL_MASK 0x0F
55#define TWL6040_HSL_VOL_SHIFT 0
56#define TWL6040_HSR_VOL_MASK 0xF0
57#define TWL6040_HSR_VOL_SHIFT 4
58#define TWL6040_HF_VOL_MASK 0x1F
59#define TWL6040_HF_VOL_SHIFT 0
60
61struct twl6040_output {
62 u16 active;
63 u16 left_vol;
64 u16 right_vol;
65 u16 left_step;
66 u16 right_step;
67 unsigned int step_delay;
68 u16 ramp;
69 u16 mute;
70 struct completion ramp_done;
71};
72
73struct twl6040_jack_data {
74 struct snd_soc_jack *jack;
75 int report;
76};
45 77
46/* codec private data */ 78/* codec private data */
47struct twl6040_data { 79struct twl6040_data {
@@ -53,6 +85,17 @@ struct twl6040_data {
53 unsigned int sysclk; 85 unsigned int sysclk;
54 struct snd_pcm_hw_constraint_list *sysclk_constraints; 86 struct snd_pcm_hw_constraint_list *sysclk_constraints;
55 struct completion ready; 87 struct completion ready;
88 struct twl6040_jack_data hs_jack;
89 struct snd_soc_codec *codec;
90 struct workqueue_struct *workqueue;
91 struct delayed_work delayed_work;
92 struct mutex mutex;
93 struct twl6040_output headset;
94 struct twl6040_output handsfree;
95 struct workqueue_struct *hf_workqueue;
96 struct workqueue_struct *hs_workqueue;
97 struct delayed_work hs_delayed_work;
98 struct delayed_work hf_delayed_work;
56}; 99};
57 100
58/* 101/*
@@ -201,7 +244,7 @@ static int twl6040_read_reg_volatile(struct snd_soc_codec *codec,
201 if (reg >= TWL6040_CACHEREGNUM) 244 if (reg >= TWL6040_CACHEREGNUM)
202 return -EIO; 245 return -EIO;
203 246
204 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &value, reg); 247 twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &value, reg);
205 twl6040_write_reg_cache(codec, reg, value); 248 twl6040_write_reg_cache(codec, reg, value);
206 249
207 return value; 250 return value;
@@ -217,7 +260,7 @@ static int twl6040_write(struct snd_soc_codec *codec,
217 return -EIO; 260 return -EIO;
218 261
219 twl6040_write_reg_cache(codec, reg, value); 262 twl6040_write_reg_cache(codec, reg, value);
220 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); 263 return twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, value, reg);
221} 264}
222 265
223static void twl6040_init_vio_regs(struct snd_soc_codec *codec) 266static void twl6040_init_vio_regs(struct snd_soc_codec *codec)
@@ -254,6 +297,305 @@ static void twl6040_init_vdd_regs(struct snd_soc_codec *codec)
254 } 297 }
255} 298}
256 299
300/*
301 * Ramp HS PGA volume to minimise pops at stream startup and shutdown.
302 */
303static inline int twl6040_hs_ramp_step(struct snd_soc_codec *codec,
304 unsigned int left_step, unsigned int right_step)
305{
306
307 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
308 struct twl6040_output *headset = &priv->headset;
309 int left_complete = 0, right_complete = 0;
310 u8 reg, val;
311
312 /* left channel */
313 left_step = (left_step > 0xF) ? 0xF : left_step;
314 reg = twl6040_read_reg_cache(codec, TWL6040_REG_HSGAIN);
315 val = (~reg & TWL6040_HSL_VOL_MASK);
316
317 if (headset->ramp == TWL6040_RAMP_UP) {
318 /* ramp step up */
319 if (val < headset->left_vol) {
320 val += left_step;
321 reg &= ~TWL6040_HSL_VOL_MASK;
322 twl6040_write(codec, TWL6040_REG_HSGAIN,
323 (reg | (~val & TWL6040_HSL_VOL_MASK)));
324 } else {
325 left_complete = 1;
326 }
327 } else if (headset->ramp == TWL6040_RAMP_DOWN) {
328 /* ramp step down */
329 if (val > 0x0) {
330 val -= left_step;
331 reg &= ~TWL6040_HSL_VOL_MASK;
332 twl6040_write(codec, TWL6040_REG_HSGAIN, reg |
333 (~val & TWL6040_HSL_VOL_MASK));
334 } else {
335 left_complete = 1;
336 }
337 }
338
339 /* right channel */
340 right_step = (right_step > 0xF) ? 0xF : right_step;
341 reg = twl6040_read_reg_cache(codec, TWL6040_REG_HSGAIN);
342 val = (~reg & TWL6040_HSR_VOL_MASK) >> TWL6040_HSR_VOL_SHIFT;
343
344 if (headset->ramp == TWL6040_RAMP_UP) {
345 /* ramp step up */
346 if (val < headset->right_vol) {
347 val += right_step;
348 reg &= ~TWL6040_HSR_VOL_MASK;
349 twl6040_write(codec, TWL6040_REG_HSGAIN,
350 (reg | (~val << TWL6040_HSR_VOL_SHIFT)));
351 } else {
352 right_complete = 1;
353 }
354 } else if (headset->ramp == TWL6040_RAMP_DOWN) {
355 /* ramp step down */
356 if (val > 0x0) {
357 val -= right_step;
358 reg &= ~TWL6040_HSR_VOL_MASK;
359 twl6040_write(codec, TWL6040_REG_HSGAIN,
360 reg | (~val << TWL6040_HSR_VOL_SHIFT));
361 } else {
362 right_complete = 1;
363 }
364 }
365
366 return left_complete & right_complete;
367}
368
369/*
370 * Ramp HF PGA volume to minimise pops at stream startup and shutdown.
371 */
372static inline int twl6040_hf_ramp_step(struct snd_soc_codec *codec,
373 unsigned int left_step, unsigned int right_step)
374{
375 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
376 struct twl6040_output *handsfree = &priv->handsfree;
377 int left_complete = 0, right_complete = 0;
378 u16 reg, val;
379
380 /* left channel */
381 left_step = (left_step > 0x1D) ? 0x1D : left_step;
382 reg = twl6040_read_reg_cache(codec, TWL6040_REG_HFLGAIN);
383 reg = 0x1D - reg;
384 val = (reg & TWL6040_HF_VOL_MASK);
385 if (handsfree->ramp == TWL6040_RAMP_UP) {
386 /* ramp step up */
387 if (val < handsfree->left_vol) {
388 val += left_step;
389 reg &= ~TWL6040_HF_VOL_MASK;
390 twl6040_write(codec, TWL6040_REG_HFLGAIN,
391 reg | (0x1D - val));
392 } else {
393 left_complete = 1;
394 }
395 } else if (handsfree->ramp == TWL6040_RAMP_DOWN) {
396 /* ramp step down */
397 if (val > 0) {
398 val -= left_step;
399 reg &= ~TWL6040_HF_VOL_MASK;
400 twl6040_write(codec, TWL6040_REG_HFLGAIN,
401 reg | (0x1D - val));
402 } else {
403 left_complete = 1;
404 }
405 }
406
407 /* right channel */
408 right_step = (right_step > 0x1D) ? 0x1D : right_step;
409 reg = twl6040_read_reg_cache(codec, TWL6040_REG_HFRGAIN);
410 reg = 0x1D - reg;
411 val = (reg & TWL6040_HF_VOL_MASK);
412 if (handsfree->ramp == TWL6040_RAMP_UP) {
413 /* ramp step up */
414 if (val < handsfree->right_vol) {
415 val += right_step;
416 reg &= ~TWL6040_HF_VOL_MASK;
417 twl6040_write(codec, TWL6040_REG_HFRGAIN,
418 reg | (0x1D - val));
419 } else {
420 right_complete = 1;
421 }
422 } else if (handsfree->ramp == TWL6040_RAMP_DOWN) {
423 /* ramp step down */
424 if (val > 0) {
425 val -= right_step;
426 reg &= ~TWL6040_HF_VOL_MASK;
427 twl6040_write(codec, TWL6040_REG_HFRGAIN,
428 reg | (0x1D - val));
429 }
430 }
431
432 return left_complete & right_complete;
433}
434
435/*
436 * This work ramps both output PGAs at stream start/stop time to
437 * minimise pop associated with DAPM power switching.
438 */
439static void twl6040_pga_hs_work(struct work_struct *work)
440{
441 struct twl6040_data *priv =
442 container_of(work, struct twl6040_data, hs_delayed_work.work);
443 struct snd_soc_codec *codec = priv->codec;
444 struct twl6040_output *headset = &priv->headset;
445 unsigned int delay = headset->step_delay;
446 int i, headset_complete;
447
448 /* do we need to ramp at all ? */
449 if (headset->ramp == TWL6040_RAMP_NONE)
450 return;
451
452 /* HS PGA volumes have 4 bits of resolution to ramp */
453 for (i = 0; i <= 16; i++) {
454 headset_complete = 1;
455 if (headset->ramp != TWL6040_RAMP_NONE)
456 headset_complete = twl6040_hs_ramp_step(codec,
457 headset->left_step,
458 headset->right_step);
459
460 /* ramp finished ? */
461 if (headset_complete)
462 break;
463
464 /*
465 * TODO: tune: delay is longer over 0dB
466 * as increases are larger.
467 */
468 if (i >= 8)
469 schedule_timeout_interruptible(msecs_to_jiffies(delay +
470 (delay >> 1)));
471 else
472 schedule_timeout_interruptible(msecs_to_jiffies(delay));
473 }
474
475 if (headset->ramp == TWL6040_RAMP_DOWN) {
476 headset->active = 0;
477 complete(&headset->ramp_done);
478 } else {
479 headset->active = 1;
480 }
481 headset->ramp = TWL6040_RAMP_NONE;
482}
483
484static void twl6040_pga_hf_work(struct work_struct *work)
485{
486 struct twl6040_data *priv =
487 container_of(work, struct twl6040_data, hf_delayed_work.work);
488 struct snd_soc_codec *codec = priv->codec;
489 struct twl6040_output *handsfree = &priv->handsfree;
490 unsigned int delay = handsfree->step_delay;
491 int i, handsfree_complete;
492
493 /* do we need to ramp at all ? */
494 if (handsfree->ramp == TWL6040_RAMP_NONE)
495 return;
496
497 /* HF PGA volumes have 5 bits of resolution to ramp */
498 for (i = 0; i <= 32; i++) {
499 handsfree_complete = 1;
500 if (handsfree->ramp != TWL6040_RAMP_NONE)
501 handsfree_complete = twl6040_hf_ramp_step(codec,
502 handsfree->left_step,
503 handsfree->right_step);
504
505 /* ramp finished ? */
506 if (handsfree_complete)
507 break;
508
509 /*
510 * TODO: tune: delay is longer over 0dB
511 * as increases are larger.
512 */
513 if (i >= 16)
514 schedule_timeout_interruptible(msecs_to_jiffies(delay +
515 (delay >> 1)));
516 else
517 schedule_timeout_interruptible(msecs_to_jiffies(delay));
518 }
519
520
521 if (handsfree->ramp == TWL6040_RAMP_DOWN) {
522 handsfree->active = 0;
523 complete(&handsfree->ramp_done);
524 } else
525 handsfree->active = 1;
526 handsfree->ramp = TWL6040_RAMP_NONE;
527}
528
529static int pga_event(struct snd_soc_dapm_widget *w,
530 struct snd_kcontrol *kcontrol, int event)
531{
532 struct snd_soc_codec *codec = w->codec;
533 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
534 struct twl6040_output *out;
535 struct delayed_work *work;
536 struct workqueue_struct *queue;
537
538 switch (w->shift) {
539 case 2:
540 case 3:
541 out = &priv->headset;
542 work = &priv->hs_delayed_work;
543 queue = priv->hs_workqueue;
544 out->step_delay = 5; /* 5 ms between volume ramp steps */
545 break;
546 case 4:
547 out = &priv->handsfree;
548 work = &priv->hf_delayed_work;
549 queue = priv->hf_workqueue;
550 out->step_delay = 5; /* 5 ms between volume ramp steps */
551 if (SND_SOC_DAPM_EVENT_ON(event))
552 priv->non_lp++;
553 else
554 priv->non_lp--;
555 break;
556 default:
557 return -1;
558 }
559
560 switch (event) {
561 case SND_SOC_DAPM_POST_PMU:
562 if (out->active)
563 break;
564
565 /* don't use volume ramp for power-up */
566 out->left_step = out->left_vol;
567 out->right_step = out->right_vol;
568
569 if (!delayed_work_pending(work)) {
570 out->ramp = TWL6040_RAMP_UP;
571 queue_delayed_work(queue, work,
572 msecs_to_jiffies(1));
573 }
574 break;
575
576 case SND_SOC_DAPM_PRE_PMD:
577 if (!out->active)
578 break;
579
580 if (!delayed_work_pending(work)) {
581 /* use volume ramp for power-down */
582 out->left_step = 1;
583 out->right_step = 1;
584 out->ramp = TWL6040_RAMP_DOWN;
585 INIT_COMPLETION(out->ramp_done);
586
587 queue_delayed_work(queue, work,
588 msecs_to_jiffies(1));
589
590 wait_for_completion_timeout(&out->ramp_done,
591 msecs_to_jiffies(2000));
592 }
593 break;
594 }
595
596 return 0;
597}
598
257/* twl6040 codec manual power-up sequence */ 599/* twl6040 codec manual power-up sequence */
258static void twl6040_power_up(struct snd_soc_codec *codec) 600static void twl6040_power_up(struct snd_soc_codec *codec)
259{ 601{
@@ -382,6 +724,47 @@ static int twl6040_power_mode_event(struct snd_soc_dapm_widget *w,
382 return 0; 724 return 0;
383} 725}
384 726
727void twl6040_hs_jack_report(struct snd_soc_codec *codec,
728 struct snd_soc_jack *jack, int report)
729{
730 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
731 int status;
732
733 mutex_lock(&priv->mutex);
734
735 /* Sync status */
736 status = twl6040_read_reg_volatile(codec, TWL6040_REG_STATUS);
737 if (status & TWL6040_PLUGCOMP)
738 snd_soc_jack_report(jack, report, report);
739 else
740 snd_soc_jack_report(jack, 0, report);
741
742 mutex_unlock(&priv->mutex);
743}
744
745void twl6040_hs_jack_detect(struct snd_soc_codec *codec,
746 struct snd_soc_jack *jack, int report)
747{
748 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
749 struct twl6040_jack_data *hs_jack = &priv->hs_jack;
750
751 hs_jack->jack = jack;
752 hs_jack->report = report;
753
754 twl6040_hs_jack_report(codec, hs_jack->jack, hs_jack->report);
755}
756EXPORT_SYMBOL_GPL(twl6040_hs_jack_detect);
757
758static void twl6040_accessory_work(struct work_struct *work)
759{
760 struct twl6040_data *priv = container_of(work,
761 struct twl6040_data, delayed_work.work);
762 struct snd_soc_codec *codec = priv->codec;
763 struct twl6040_jack_data *hs_jack = &priv->hs_jack;
764
765 twl6040_hs_jack_report(codec, hs_jack->jack, hs_jack->report);
766}
767
385/* audio interrupt handler */ 768/* audio interrupt handler */
386static irqreturn_t twl6040_naudint_handler(int irq, void *data) 769static irqreturn_t twl6040_naudint_handler(int irq, void *data)
387{ 770{
@@ -389,33 +772,180 @@ static irqreturn_t twl6040_naudint_handler(int irq, void *data)
389 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); 772 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
390 u8 intid; 773 u8 intid;
391 774
392 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &intid, TWL6040_REG_INTID); 775 twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &intid, TWL6040_REG_INTID);
393 776
394 switch (intid) { 777 if (intid & TWL6040_THINT)
395 case TWL6040_THINT:
396 dev_alert(codec->dev, "die temp over-limit detection\n"); 778 dev_alert(codec->dev, "die temp over-limit detection\n");
779
780 if ((intid & TWL6040_PLUGINT) || (intid & TWL6040_UNPLUGINT))
781 queue_delayed_work(priv->workqueue, &priv->delayed_work,
782 msecs_to_jiffies(200));
783
784 if (intid & TWL6040_HOOKINT)
785 dev_info(codec->dev, "hook detection\n");
786
787 if (intid & TWL6040_HFINT)
788 dev_alert(codec->dev, "hf drivers over current detection\n");
789
790 if (intid & TWL6040_VIBINT)
791 dev_alert(codec->dev, "vib drivers over current detection\n");
792
793 if (intid & TWL6040_READYINT)
794 complete(&priv->ready);
795
796 return IRQ_HANDLED;
797}
798
799static int twl6040_put_volsw(struct snd_kcontrol *kcontrol,
800 struct snd_ctl_elem_value *ucontrol)
801{
802 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
803 struct twl6040_data *twl6040_priv = snd_soc_codec_get_drvdata(codec);
804 struct twl6040_output *out = NULL;
805 struct soc_mixer_control *mc =
806 (struct soc_mixer_control *)kcontrol->private_value;
807 int ret;
808 unsigned int reg = mc->reg;
809
810 /* For HS and HF we shadow the values and only actually write
811 * them out when active in order to ensure the amplifier comes on
812 * as quietly as possible. */
813 switch (reg) {
814 case TWL6040_REG_HSGAIN:
815 out = &twl6040_priv->headset;
397 break; 816 break;
398 case TWL6040_PLUGINT: 817 default:
399 case TWL6040_UNPLUGINT:
400 case TWL6040_HOOKINT:
401 break; 818 break;
402 case TWL6040_HFINT: 819 }
403 dev_alert(codec->dev, "hf drivers over current detection\n"); 820
821 if (out) {
822 out->left_vol = ucontrol->value.integer.value[0];
823 out->right_vol = ucontrol->value.integer.value[1];
824 if (!out->active)
825 return 1;
826 }
827
828 ret = snd_soc_put_volsw(kcontrol, ucontrol);
829 if (ret < 0)
830 return ret;
831
832 return 1;
833}
834
835static int twl6040_get_volsw(struct snd_kcontrol *kcontrol,
836 struct snd_ctl_elem_value *ucontrol)
837{
838 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
839 struct twl6040_data *twl6040_priv = snd_soc_codec_get_drvdata(codec);
840 struct twl6040_output *out = &twl6040_priv->headset;
841 struct soc_mixer_control *mc =
842 (struct soc_mixer_control *)kcontrol->private_value;
843 unsigned int reg = mc->reg;
844
845 switch (reg) {
846 case TWL6040_REG_HSGAIN:
847 out = &twl6040_priv->headset;
848 ucontrol->value.integer.value[0] = out->left_vol;
849 ucontrol->value.integer.value[1] = out->right_vol;
850 return 0;
851
852 default:
404 break; 853 break;
405 case TWL6040_VIBINT: 854 }
406 dev_alert(codec->dev, "vib drivers over current detection\n"); 855
856 return snd_soc_get_volsw(kcontrol, ucontrol);
857}
858
859static int twl6040_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
860 struct snd_ctl_elem_value *ucontrol)
861{
862 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
863 struct twl6040_data *twl6040_priv = snd_soc_codec_get_drvdata(codec);
864 struct twl6040_output *out = NULL;
865 struct soc_mixer_control *mc =
866 (struct soc_mixer_control *)kcontrol->private_value;
867 int ret;
868 unsigned int reg = mc->reg;
869
870 /* For HS and HF we shadow the values and only actually write
871 * them out when active in order to ensure the amplifier comes on
872 * as quietly as possible. */
873 switch (reg) {
874 case TWL6040_REG_HFLGAIN:
875 case TWL6040_REG_HFRGAIN:
876 out = &twl6040_priv->handsfree;
407 break; 877 break;
408 case TWL6040_READYINT: 878 default:
409 complete(&priv->ready);
410 break; 879 break;
880 }
881
882 if (out) {
883 out->left_vol = ucontrol->value.integer.value[0];
884 out->right_vol = ucontrol->value.integer.value[1];
885 if (!out->active)
886 return 1;
887 }
888
889 ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
890 if (ret < 0)
891 return ret;
892
893 return 1;
894}
895
896static int twl6040_get_volsw_2r(struct snd_kcontrol *kcontrol,
897 struct snd_ctl_elem_value *ucontrol)
898{
899 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
900 struct twl6040_data *twl6040_priv = snd_soc_codec_get_drvdata(codec);
901 struct twl6040_output *out = &twl6040_priv->handsfree;
902 struct soc_mixer_control *mc =
903 (struct soc_mixer_control *)kcontrol->private_value;
904 unsigned int reg = mc->reg;
905
906 /* If these are cached registers use the cache */
907 switch (reg) {
908 case TWL6040_REG_HFLGAIN:
909 case TWL6040_REG_HFRGAIN:
910 out = &twl6040_priv->handsfree;
911 ucontrol->value.integer.value[0] = out->left_vol;
912 ucontrol->value.integer.value[1] = out->right_vol;
913 return 0;
914
411 default: 915 default:
412 dev_err(codec->dev, "unknown audio interrupt %d\n", intid);
413 break; 916 break;
414 } 917 }
415 918
416 return IRQ_HANDLED; 919 return snd_soc_get_volsw_2r(kcontrol, ucontrol);
417} 920}
418 921
922/* double control with volume update */
923#define SOC_TWL6040_DOUBLE_TLV(xname, xreg, shift_left, shift_right, xmax,\
924 xinvert, tlv_array)\
925{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
926 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
927 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
928 .tlv.p = (tlv_array), \
929 .info = snd_soc_info_volsw, .get = twl6040_get_volsw, \
930 .put = twl6040_put_volsw, \
931 .private_value = (unsigned long)&(struct soc_mixer_control) \
932 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
933 .max = xmax, .platform_max = xmax, .invert = xinvert} }
934
935/* double control with volume update */
936#define SOC_TWL6040_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax,\
937 xinvert, tlv_array)\
938{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
939 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
940 SNDRV_CTL_ELEM_ACCESS_READWRITE | \
941 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
942 .tlv.p = (tlv_array), \
943 .info = snd_soc_info_volsw_2r, \
944 .get = twl6040_get_volsw_2r, .put = twl6040_put_volsw_2r_vu, \
945 .private_value = (unsigned long)&(struct soc_mixer_control) \
946 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
947 .rshift = xshift, .max = xmax, .invert = xinvert}, }
948
419/* 949/*
420 * MICATT volume control: 950 * MICATT volume control:
421 * from -6 to 0 dB in 6 dB steps 951 * from -6 to 0 dB in 6 dB steps
@@ -424,9 +954,15 @@ static DECLARE_TLV_DB_SCALE(mic_preamp_tlv, -600, 600, 0);
424 954
425/* 955/*
426 * MICGAIN volume control: 956 * MICGAIN volume control:
427 * from 6 to 30 dB in 6 dB steps 957 * from -6 to 30 dB in 6 dB steps
428 */ 958 */
429static DECLARE_TLV_DB_SCALE(mic_amp_tlv, 600, 600, 0); 959static DECLARE_TLV_DB_SCALE(mic_amp_tlv, -600, 600, 0);
960
961/*
962 * AFMGAIN volume control:
963 * from 18 to 24 dB in 6 dB steps
964 */
965static DECLARE_TLV_DB_SCALE(afm_amp_tlv, 1800, 600, 0);
430 966
431/* 967/*
432 * HSGAIN volume control: 968 * HSGAIN volume control:
@@ -455,8 +991,30 @@ static const char *twl6040_amicr_texts[] =
455 {"Headset Mic", "Sub Mic", "Aux/FM Right", "Off"}; 991 {"Headset Mic", "Sub Mic", "Aux/FM Right", "Off"};
456 992
457static const struct soc_enum twl6040_enum[] = { 993static const struct soc_enum twl6040_enum[] = {
458 SOC_ENUM_SINGLE(TWL6040_REG_MICLCTL, 3, 3, twl6040_amicl_texts), 994 SOC_ENUM_SINGLE(TWL6040_REG_MICLCTL, 3, 4, twl6040_amicl_texts),
459 SOC_ENUM_SINGLE(TWL6040_REG_MICRCTL, 3, 3, twl6040_amicr_texts), 995 SOC_ENUM_SINGLE(TWL6040_REG_MICRCTL, 3, 4, twl6040_amicr_texts),
996};
997
998static const char *twl6040_hs_texts[] = {
999 "Off", "HS DAC", "Line-In amp"
1000};
1001
1002static const struct soc_enum twl6040_hs_enum[] = {
1003 SOC_ENUM_SINGLE(TWL6040_REG_HSLCTL, 5, ARRAY_SIZE(twl6040_hs_texts),
1004 twl6040_hs_texts),
1005 SOC_ENUM_SINGLE(TWL6040_REG_HSRCTL, 5, ARRAY_SIZE(twl6040_hs_texts),
1006 twl6040_hs_texts),
1007};
1008
1009static const char *twl6040_hf_texts[] = {
1010 "Off", "HF DAC", "Line-In amp"
1011};
1012
1013static const struct soc_enum twl6040_hf_enum[] = {
1014 SOC_ENUM_SINGLE(TWL6040_REG_HFLCTL, 2, ARRAY_SIZE(twl6040_hf_texts),
1015 twl6040_hf_texts),
1016 SOC_ENUM_SINGLE(TWL6040_REG_HFRCTL, 2, ARRAY_SIZE(twl6040_hf_texts),
1017 twl6040_hf_texts),
460}; 1018};
461 1019
462static const struct snd_kcontrol_new amicl_control = 1020static const struct snd_kcontrol_new amicl_control =
@@ -466,18 +1024,18 @@ static const struct snd_kcontrol_new amicr_control =
466 SOC_DAPM_ENUM("Route", twl6040_enum[1]); 1024 SOC_DAPM_ENUM("Route", twl6040_enum[1]);
467 1025
468/* Headset DAC playback switches */ 1026/* Headset DAC playback switches */
469static const struct snd_kcontrol_new hsdacl_switch_controls = 1027static const struct snd_kcontrol_new hsl_mux_controls =
470 SOC_DAPM_SINGLE("Switch", TWL6040_REG_HSLCTL, 5, 1, 0); 1028 SOC_DAPM_ENUM("Route", twl6040_hs_enum[0]);
471 1029
472static const struct snd_kcontrol_new hsdacr_switch_controls = 1030static const struct snd_kcontrol_new hsr_mux_controls =
473 SOC_DAPM_SINGLE("Switch", TWL6040_REG_HSRCTL, 5, 1, 0); 1031 SOC_DAPM_ENUM("Route", twl6040_hs_enum[1]);
474 1032
475/* Handsfree DAC playback switches */ 1033/* Handsfree DAC playback switches */
476static const struct snd_kcontrol_new hfdacl_switch_controls = 1034static const struct snd_kcontrol_new hfl_mux_controls =
477 SOC_DAPM_SINGLE("Switch", TWL6040_REG_HFLCTL, 2, 1, 0); 1035 SOC_DAPM_ENUM("Route", twl6040_hf_enum[0]);
478 1036
479static const struct snd_kcontrol_new hfdacr_switch_controls = 1037static const struct snd_kcontrol_new hfr_mux_controls =
480 SOC_DAPM_SINGLE("Switch", TWL6040_REG_HFRCTL, 2, 1, 0); 1038 SOC_DAPM_ENUM("Route", twl6040_hf_enum[1]);
481 1039
482static const struct snd_kcontrol_new ep_driver_switch_controls = 1040static const struct snd_kcontrol_new ep_driver_switch_controls =
483 SOC_DAPM_SINGLE("Switch", TWL6040_REG_EARCTL, 0, 1, 0); 1041 SOC_DAPM_SINGLE("Switch", TWL6040_REG_EARCTL, 0, 1, 0);
@@ -489,10 +1047,14 @@ static const struct snd_kcontrol_new twl6040_snd_controls[] = {
489 SOC_DOUBLE_TLV("Capture Volume", 1047 SOC_DOUBLE_TLV("Capture Volume",
490 TWL6040_REG_MICGAIN, 0, 3, 4, 0, mic_amp_tlv), 1048 TWL6040_REG_MICGAIN, 0, 3, 4, 0, mic_amp_tlv),
491 1049
1050 /* AFM gains */
1051 SOC_DOUBLE_TLV("Aux FM Volume",
1052 TWL6040_REG_LINEGAIN, 0, 4, 0xF, 0, afm_amp_tlv),
1053
492 /* Playback gains */ 1054 /* Playback gains */
493 SOC_DOUBLE_TLV("Headset Playback Volume", 1055 SOC_TWL6040_DOUBLE_TLV("Headset Playback Volume",
494 TWL6040_REG_HSGAIN, 0, 4, 0xF, 1, hs_tlv), 1056 TWL6040_REG_HSGAIN, 0, 4, 0xF, 1, hs_tlv),
495 SOC_DOUBLE_R_TLV("Handsfree Playback Volume", 1057 SOC_TWL6040_DOUBLE_R_TLV("Handsfree Playback Volume",
496 TWL6040_REG_HFLGAIN, TWL6040_REG_HFRGAIN, 0, 0x1D, 1, hf_tlv), 1058 TWL6040_REG_HFLGAIN, TWL6040_REG_HFRGAIN, 0, 0x1D, 1, hf_tlv),
497 SOC_SINGLE_TLV("Earphone Playback Volume", 1059 SOC_SINGLE_TLV("Earphone Playback Volume",
498 TWL6040_REG_EARCTL, 1, 0xF, 1, ep_tlv), 1060 TWL6040_REG_EARCTL, 1, 0xF, 1, ep_tlv),
@@ -525,6 +1087,12 @@ static const struct snd_soc_dapm_widget twl6040_dapm_widgets[] = {
525 SND_SOC_DAPM_PGA("MicAmpR", 1087 SND_SOC_DAPM_PGA("MicAmpR",
526 TWL6040_REG_MICRCTL, 0, 0, NULL, 0), 1088 TWL6040_REG_MICRCTL, 0, 0, NULL, 0),
527 1089
1090 /* Auxiliary FM PGAs */
1091 SND_SOC_DAPM_PGA("AFMAmpL",
1092 TWL6040_REG_MICLCTL, 1, 0, NULL, 0),
1093 SND_SOC_DAPM_PGA("AFMAmpR",
1094 TWL6040_REG_MICRCTL, 1, 0, NULL, 0),
1095
528 /* ADCs */ 1096 /* ADCs */
529 SND_SOC_DAPM_ADC("ADC Left", "Left Front Capture", 1097 SND_SOC_DAPM_ADC("ADC Left", "Left Front Capture",
530 TWL6040_REG_MICLCTL, 2, 0), 1098 TWL6040_REG_MICLCTL, 2, 0),
@@ -559,29 +1127,33 @@ static const struct snd_soc_dapm_widget twl6040_dapm_widgets[] = {
559 twl6040_power_mode_event, 1127 twl6040_power_mode_event,
560 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1128 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
561 1129
562 /* Analog playback switches */ 1130 SND_SOC_DAPM_MUX("HF Left Playback",
563 SND_SOC_DAPM_SWITCH("HSDAC Left Playback", 1131 SND_SOC_NOPM, 0, 0, &hfl_mux_controls),
564 SND_SOC_NOPM, 0, 0, &hsdacl_switch_controls), 1132 SND_SOC_DAPM_MUX("HF Right Playback",
565 SND_SOC_DAPM_SWITCH("HSDAC Right Playback", 1133 SND_SOC_NOPM, 0, 0, &hfr_mux_controls),
566 SND_SOC_NOPM, 0, 0, &hsdacr_switch_controls), 1134 /* Analog playback Muxes */
567 SND_SOC_DAPM_SWITCH("HFDAC Left Playback", 1135 SND_SOC_DAPM_MUX("HS Left Playback",
568 SND_SOC_NOPM, 0, 0, &hfdacl_switch_controls), 1136 SND_SOC_NOPM, 0, 0, &hsl_mux_controls),
569 SND_SOC_DAPM_SWITCH("HFDAC Right Playback", 1137 SND_SOC_DAPM_MUX("HS Right Playback",
570 SND_SOC_NOPM, 0, 0, &hfdacr_switch_controls), 1138 SND_SOC_NOPM, 0, 0, &hsr_mux_controls),
571 1139
572 /* Analog playback drivers */ 1140 /* Analog playback drivers */
573 SND_SOC_DAPM_PGA_E("Handsfree Left Driver", 1141 SND_SOC_DAPM_OUT_DRV_E("Handsfree Left Driver",
574 TWL6040_REG_HFLCTL, 4, 0, NULL, 0, 1142 TWL6040_REG_HFLCTL, 4, 0, NULL, 0,
575 twl6040_power_mode_event, 1143 pga_event,
576 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1144 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
577 SND_SOC_DAPM_PGA_E("Handsfree Right Driver", 1145 SND_SOC_DAPM_OUT_DRV_E("Handsfree Right Driver",
578 TWL6040_REG_HFRCTL, 4, 0, NULL, 0, 1146 TWL6040_REG_HFRCTL, 4, 0, NULL, 0,
579 twl6040_power_mode_event, 1147 pga_event,
580 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1148 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
581 SND_SOC_DAPM_PGA("Headset Left Driver", 1149 SND_SOC_DAPM_OUT_DRV_E("Headset Left Driver",
582 TWL6040_REG_HSLCTL, 2, 0, NULL, 0), 1150 TWL6040_REG_HSLCTL, 2, 0, NULL, 0,
583 SND_SOC_DAPM_PGA("Headset Right Driver", 1151 pga_event,
584 TWL6040_REG_HSRCTL, 2, 0, NULL, 0), 1152 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1153 SND_SOC_DAPM_OUT_DRV_E("Headset Right Driver",
1154 TWL6040_REG_HSRCTL, 2, 0, NULL, 0,
1155 pga_event,
1156 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
585 SND_SOC_DAPM_SWITCH_E("Earphone Driver", 1157 SND_SOC_DAPM_SWITCH_E("Earphone Driver",
586 SND_SOC_NOPM, 0, 0, &ep_driver_switch_controls, 1158 SND_SOC_NOPM, 0, 0, &ep_driver_switch_controls,
587 twl6040_power_mode_event, 1159 twl6040_power_mode_event,
@@ -611,12 +1183,18 @@ static const struct snd_soc_dapm_route intercon[] = {
611 {"ADC Left", NULL, "MicAmpL"}, 1183 {"ADC Left", NULL, "MicAmpL"},
612 {"ADC Right", NULL, "MicAmpR"}, 1184 {"ADC Right", NULL, "MicAmpR"},
613 1185
614 /* Headset playback path */ 1186 /* AFM path */
615 {"HSDAC Left Playback", "Switch", "HSDAC Left"}, 1187 {"AFMAmpL", "NULL", "AFML"},
616 {"HSDAC Right Playback", "Switch", "HSDAC Right"}, 1188 {"AFMAmpR", "NULL", "AFMR"},
1189
1190 {"HS Left Playback", "HS DAC", "HSDAC Left"},
1191 {"HS Left Playback", "Line-In amp", "AFMAmpL"},
617 1192
618 {"Headset Left Driver", NULL, "HSDAC Left Playback"}, 1193 {"HS Right Playback", "HS DAC", "HSDAC Right"},
619 {"Headset Right Driver", NULL, "HSDAC Right Playback"}, 1194 {"HS Right Playback", "Line-In amp", "AFMAmpR"},
1195
1196 {"Headset Left Driver", "NULL", "HS Left Playback"},
1197 {"Headset Right Driver", "NULL", "HS Right Playback"},
620 1198
621 {"HSOL", NULL, "Headset Left Driver"}, 1199 {"HSOL", NULL, "Headset Left Driver"},
622 {"HSOR", NULL, "Headset Right Driver"}, 1200 {"HSOR", NULL, "Headset Right Driver"},
@@ -625,12 +1203,14 @@ static const struct snd_soc_dapm_route intercon[] = {
625 {"Earphone Driver", "Switch", "HSDAC Left"}, 1203 {"Earphone Driver", "Switch", "HSDAC Left"},
626 {"EP", NULL, "Earphone Driver"}, 1204 {"EP", NULL, "Earphone Driver"},
627 1205
628 /* Handsfree playback path */ 1206 {"HF Left Playback", "HF DAC", "HFDAC Left"},
629 {"HFDAC Left Playback", "Switch", "HFDAC Left"}, 1207 {"HF Left Playback", "Line-In amp", "AFMAmpL"},
630 {"HFDAC Right Playback", "Switch", "HFDAC Right"}, 1208
1209 {"HF Right Playback", "HF DAC", "HFDAC Right"},
1210 {"HF Right Playback", "Line-In amp", "AFMAmpR"},
631 1211
632 {"HFDAC Left PGA", NULL, "HFDAC Left Playback"}, 1212 {"HFDAC Left PGA", NULL, "HF Left Playback"},
633 {"HFDAC Right PGA", NULL, "HFDAC Right Playback"}, 1213 {"HFDAC Right PGA", NULL, "HF Right Playback"},
634 1214
635 {"Handsfree Left Driver", "Switch", "HFDAC Left PGA"}, 1215 {"Handsfree Left Driver", "Switch", "HFDAC Left PGA"},
636 {"Handsfree Right Driver", "Switch", "HFDAC Right PGA"}, 1216 {"Handsfree Right Driver", "Switch", "HFDAC Right PGA"},
@@ -641,12 +1221,12 @@ static const struct snd_soc_dapm_route intercon[] = {
641 1221
642static int twl6040_add_widgets(struct snd_soc_codec *codec) 1222static int twl6040_add_widgets(struct snd_soc_codec *codec)
643{ 1223{
644 snd_soc_dapm_new_controls(codec, twl6040_dapm_widgets, 1224 struct snd_soc_dapm_context *dapm = &codec->dapm;
645 ARRAY_SIZE(twl6040_dapm_widgets));
646
647 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
648 1225
649 snd_soc_dapm_new_widgets(codec); 1226 snd_soc_dapm_new_controls(dapm, twl6040_dapm_widgets,
1227 ARRAY_SIZE(twl6040_dapm_widgets));
1228 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
1229 snd_soc_dapm_new_widgets(dapm);
650 1230
651 return 0; 1231 return 0;
652} 1232}
@@ -659,10 +1239,10 @@ static int twl6040_power_up_completion(struct snd_soc_codec *codec,
659 u8 intid; 1239 u8 intid;
660 1240
661 time_left = wait_for_completion_timeout(&priv->ready, 1241 time_left = wait_for_completion_timeout(&priv->ready,
662 msecs_to_jiffies(48)); 1242 msecs_to_jiffies(144));
663 1243
664 if (!time_left) { 1244 if (!time_left) {
665 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &intid, 1245 twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &intid,
666 TWL6040_REG_INTID); 1246 TWL6040_REG_INTID);
667 if (!(intid & TWL6040_READYINT)) { 1247 if (!(intid & TWL6040_READYINT)) {
668 dev_err(codec->dev, "timeout waiting for READYINT\n"); 1248 dev_err(codec->dev, "timeout waiting for READYINT\n");
@@ -713,6 +1293,15 @@ static int twl6040_set_bias_level(struct snd_soc_codec *codec,
713 1293
714 /* initialize vdd/vss registers with reg_cache */ 1294 /* initialize vdd/vss registers with reg_cache */
715 twl6040_init_vdd_regs(codec); 1295 twl6040_init_vdd_regs(codec);
1296
1297 /* Set external boost GPO */
1298 twl6040_write(codec, TWL6040_REG_GPOCTL, 0x02);
1299
1300 /* Set initial minimal gain values */
1301 twl6040_write(codec, TWL6040_REG_HSGAIN, 0xFF);
1302 twl6040_write(codec, TWL6040_REG_EARCTL, 0x1E);
1303 twl6040_write(codec, TWL6040_REG_HFLGAIN, 0x1D);
1304 twl6040_write(codec, TWL6040_REG_HFRGAIN, 0x1D);
716 break; 1305 break;
717 case SND_SOC_BIAS_OFF: 1306 case SND_SOC_BIAS_OFF:
718 if (!priv->codec_powered) 1307 if (!priv->codec_powered)
@@ -739,7 +1328,7 @@ static int twl6040_set_bias_level(struct snd_soc_codec *codec,
739 break; 1328 break;
740 } 1329 }
741 1330
742 codec->bias_level = level; 1331 codec->dapm.bias_level = level;
743 1332
744 return 0; 1333 return 0;
745} 1334}
@@ -772,23 +1361,6 @@ static int twl6040_startup(struct snd_pcm_substream *substream,
772 struct snd_soc_codec *codec = rtd->codec; 1361 struct snd_soc_codec *codec = rtd->codec;
773 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); 1362 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
774 1363
775 if (!priv->sysclk) {
776 dev_err(codec->dev,
777 "no mclk configured, call set_sysclk() on init\n");
778 return -EINVAL;
779 }
780
781 /*
782 * capture is not supported at 17.64 MHz,
783 * it's reserved for headset low-power playback scenario
784 */
785 if ((priv->sysclk == 17640000) && substream->stream) {
786 dev_err(codec->dev,
787 "capture mode is not supported at %dHz\n",
788 priv->sysclk);
789 return -EINVAL;
790 }
791
792 snd_pcm_hw_constraint_list(substream->runtime, 0, 1364 snd_pcm_hw_constraint_list(substream->runtime, 0,
793 SNDRV_PCM_HW_PARAM_RATE, 1365 SNDRV_PCM_HW_PARAM_RATE,
794 priv->sysclk_constraints); 1366 priv->sysclk_constraints);
@@ -814,10 +1386,17 @@ static int twl6040_hw_params(struct snd_pcm_substream *substream,
814 1386
815 rate = params_rate(params); 1387 rate = params_rate(params);
816 switch (rate) { 1388 switch (rate) {
1389 case 11250:
1390 case 22500:
1391 case 44100:
817 case 88200: 1392 case 88200:
818 lppllctl |= TWL6040_LPLLFIN; 1393 lppllctl |= TWL6040_LPLLFIN;
819 priv->sysclk = 17640000; 1394 priv->sysclk = 17640000;
820 break; 1395 break;
1396 case 8000:
1397 case 16000:
1398 case 32000:
1399 case 48000:
821 case 96000: 1400 case 96000:
822 lppllctl &= ~TWL6040_LPLLFIN; 1401 lppllctl &= ~TWL6040_LPLLFIN;
823 priv->sysclk = 19200000; 1402 priv->sysclk = 19200000;
@@ -832,31 +1411,37 @@ static int twl6040_hw_params(struct snd_pcm_substream *substream,
832 return 0; 1411 return 0;
833} 1412}
834 1413
835static int twl6040_trigger(struct snd_pcm_substream *substream, 1414static int twl6040_prepare(struct snd_pcm_substream *substream,
836 int cmd, struct snd_soc_dai *dai) 1415 struct snd_soc_dai *dai)
837{ 1416{
838 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1417 struct snd_soc_pcm_runtime *rtd = substream->private_data;
839 struct snd_soc_codec *codec = rtd->codec; 1418 struct snd_soc_codec *codec = rtd->codec;
840 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec); 1419 struct twl6040_data *priv = snd_soc_codec_get_drvdata(codec);
841 1420
842 switch (cmd) { 1421 if (!priv->sysclk) {
843 case SNDRV_PCM_TRIGGER_START: 1422 dev_err(codec->dev,
844 case SNDRV_PCM_TRIGGER_RESUME: 1423 "no mclk configured, call set_sysclk() on init\n");
845 /* 1424 return -EINVAL;
846 * low-power playback mode is restricted 1425 }
847 * for headset path only 1426
848 */ 1427 /*
849 if ((priv->sysclk == 17640000) && priv->non_lp) { 1428 * capture is not supported at 17.64 MHz,
1429 * it's reserved for headset low-power playback scenario
1430 */
1431 if ((priv->sysclk == 17640000) &&
1432 substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
1433 dev_err(codec->dev,
1434 "capture mode is not supported at %dHz\n",
1435 priv->sysclk);
1436 return -EINVAL;
1437 }
1438
1439 if ((priv->sysclk == 17640000) && priv->non_lp) {
850 dev_err(codec->dev, 1440 dev_err(codec->dev,
851 "some enabled paths aren't supported at %dHz\n", 1441 "some enabled paths aren't supported at %dHz\n",
852 priv->sysclk); 1442 priv->sysclk);
853 return -EPERM; 1443 return -EPERM;
854 }
855 break;
856 default:
857 break;
858 } 1444 }
859
860 return 0; 1445 return 0;
861} 1446}
862 1447
@@ -970,7 +1555,7 @@ static int twl6040_set_dai_sysclk(struct snd_soc_dai *codec_dai,
970static struct snd_soc_dai_ops twl6040_dai_ops = { 1555static struct snd_soc_dai_ops twl6040_dai_ops = {
971 .startup = twl6040_startup, 1556 .startup = twl6040_startup,
972 .hw_params = twl6040_hw_params, 1557 .hw_params = twl6040_hw_params,
973 .trigger = twl6040_trigger, 1558 .prepare = twl6040_prepare,
974 .set_sysclk = twl6040_set_dai_sysclk, 1559 .set_sysclk = twl6040_set_dai_sysclk,
975}; 1560};
976 1561
@@ -1004,6 +1589,7 @@ static int twl6040_suspend(struct snd_soc_codec *codec, pm_message_t state)
1004static int twl6040_resume(struct snd_soc_codec *codec) 1589static int twl6040_resume(struct snd_soc_codec *codec)
1005{ 1590{
1006 twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1591 twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1592 twl6040_set_bias_level(codec, codec->dapm.suspend_bias_level);
1007 1593
1008 return 0; 1594 return 0;
1009} 1595}
@@ -1018,24 +1604,41 @@ static int twl6040_probe(struct snd_soc_codec *codec)
1018 struct twl6040_data *priv; 1604 struct twl6040_data *priv;
1019 int audpwron, naudint; 1605 int audpwron, naudint;
1020 int ret = 0; 1606 int ret = 0;
1607 u8 icrev, intmr = TWL6040_ALLINT_MSK;
1021 1608
1022 priv = kzalloc(sizeof(struct twl6040_data), GFP_KERNEL); 1609 priv = kzalloc(sizeof(struct twl6040_data), GFP_KERNEL);
1023 if (priv == NULL) 1610 if (priv == NULL)
1024 return -ENOMEM; 1611 return -ENOMEM;
1025 snd_soc_codec_set_drvdata(codec, priv); 1612 snd_soc_codec_set_drvdata(codec, priv);
1026 1613
1027 if (twl_codec) { 1614 priv->codec = codec;
1615
1616 twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &icrev, TWL6040_REG_ASICREV);
1617
1618 if (twl_codec && (icrev > 0))
1028 audpwron = twl_codec->audpwron_gpio; 1619 audpwron = twl_codec->audpwron_gpio;
1029 naudint = twl_codec->naudint_irq; 1620 else
1030 } else {
1031 audpwron = -EINVAL; 1621 audpwron = -EINVAL;
1622
1623 if (twl_codec)
1624 naudint = twl_codec->naudint_irq;
1625 else
1032 naudint = 0; 1626 naudint = 0;
1033 }
1034 1627
1035 priv->audpwron = audpwron; 1628 priv->audpwron = audpwron;
1036 priv->naudint = naudint; 1629 priv->naudint = naudint;
1630 priv->workqueue = create_singlethread_workqueue("twl6040-codec");
1631
1632 if (!priv->workqueue)
1633 goto work_err;
1634
1635 INIT_DELAYED_WORK(&priv->delayed_work, twl6040_accessory_work);
1636
1637 mutex_init(&priv->mutex);
1037 1638
1038 init_completion(&priv->ready); 1639 init_completion(&priv->ready);
1640 init_completion(&priv->headset.ramp_done);
1641 init_completion(&priv->handsfree.ramp_done);
1039 1642
1040 if (gpio_is_valid(audpwron)) { 1643 if (gpio_is_valid(audpwron)) {
1041 ret = gpio_request(audpwron, "audpwron"); 1644 ret = gpio_request(audpwron, "audpwron");
@@ -1047,7 +1650,14 @@ static int twl6040_probe(struct snd_soc_codec *codec)
1047 goto gpio2_err; 1650 goto gpio2_err;
1048 1651
1049 priv->codec_powered = 0; 1652 priv->codec_powered = 0;
1653
1654 /* enable only codec ready interrupt */
1655 intmr &= ~(TWL6040_READYMSK | TWL6040_PLUGMSK);
1656
1657 /* reset interrupt status to allow correct power up sequence */
1658 twl6040_read_reg_volatile(codec, TWL6040_REG_INTID);
1050 } 1659 }
1660 twl6040_write(codec, TWL6040_REG_INTMR, intmr);
1051 1661
1052 if (naudint) { 1662 if (naudint) {
1053 /* audio interrupt */ 1663 /* audio interrupt */
@@ -1057,25 +1667,29 @@ static int twl6040_probe(struct snd_soc_codec *codec)
1057 "twl6040_codec", codec); 1667 "twl6040_codec", codec);
1058 if (ret) 1668 if (ret)
1059 goto gpio2_err; 1669 goto gpio2_err;
1060 } else {
1061 if (gpio_is_valid(audpwron)) {
1062 /* enable only codec ready interrupt */
1063 twl6040_write_reg_cache(codec, TWL6040_REG_INTMR,
1064 ~TWL6040_READYMSK & TWL6040_ALLINT_MSK);
1065 } else {
1066 /* no interrupts at all */
1067 twl6040_write_reg_cache(codec, TWL6040_REG_INTMR,
1068 TWL6040_ALLINT_MSK);
1069 }
1070 } 1670 }
1071 1671
1072 /* init vio registers */ 1672 /* init vio registers */
1073 twl6040_init_vio_regs(codec); 1673 twl6040_init_vio_regs(codec);
1074 1674
1675 priv->hf_workqueue = create_singlethread_workqueue("twl6040-hf");
1676 if (priv->hf_workqueue == NULL) {
1677 ret = -ENOMEM;
1678 goto irq_err;
1679 }
1680 priv->hs_workqueue = create_singlethread_workqueue("twl6040-hs");
1681 if (priv->hs_workqueue == NULL) {
1682 ret = -ENOMEM;
1683 goto wq_err;
1684 }
1685
1686 INIT_DELAYED_WORK(&priv->hs_delayed_work, twl6040_pga_hs_work);
1687 INIT_DELAYED_WORK(&priv->hf_delayed_work, twl6040_pga_hf_work);
1688
1075 /* power on device */ 1689 /* power on device */
1076 ret = twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1690 ret = twl6040_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1077 if (ret) 1691 if (ret)
1078 goto irq_err; 1692 goto bias_err;
1079 1693
1080 snd_soc_add_controls(codec, twl6040_snd_controls, 1694 snd_soc_add_controls(codec, twl6040_snd_controls,
1081 ARRAY_SIZE(twl6040_snd_controls)); 1695 ARRAY_SIZE(twl6040_snd_controls));
@@ -1083,6 +1697,10 @@ static int twl6040_probe(struct snd_soc_codec *codec)
1083 1697
1084 return 0; 1698 return 0;
1085 1699
1700bias_err:
1701 destroy_workqueue(priv->hs_workqueue);
1702wq_err:
1703 destroy_workqueue(priv->hf_workqueue);
1086irq_err: 1704irq_err:
1087 if (naudint) 1705 if (naudint)
1088 free_irq(naudint, codec); 1706 free_irq(naudint, codec);
@@ -1090,6 +1708,8 @@ gpio2_err:
1090 if (gpio_is_valid(audpwron)) 1708 if (gpio_is_valid(audpwron))
1091 gpio_free(audpwron); 1709 gpio_free(audpwron);
1092gpio1_err: 1710gpio1_err:
1711 destroy_workqueue(priv->workqueue);
1712work_err:
1093 kfree(priv); 1713 kfree(priv);
1094 return ret; 1714 return ret;
1095} 1715}
@@ -1108,6 +1728,9 @@ static int twl6040_remove(struct snd_soc_codec *codec)
1108 if (naudint) 1728 if (naudint)
1109 free_irq(naudint, codec); 1729 free_irq(naudint, codec);
1110 1730
1731 destroy_workqueue(priv->workqueue);
1732 destroy_workqueue(priv->hf_workqueue);
1733 destroy_workqueue(priv->hs_workqueue);
1111 kfree(priv); 1734 kfree(priv);
1112 1735
1113 return 0; 1736 return 0;
diff --git a/sound/soc/codecs/twl6040.h b/sound/soc/codecs/twl6040.h
index f7c77fa58a3c..23aeed0963e6 100644
--- a/sound/soc/codecs/twl6040.h
+++ b/sound/soc/codecs/twl6040.h
@@ -79,6 +79,7 @@
79 79
80/* INTMR (0x04) fields */ 80/* INTMR (0x04) fields */
81 81
82#define TWL6040_PLUGMSK 0x02
82#define TWL6040_READYMSK 0x40 83#define TWL6040_READYMSK 0x40
83#define TWL6040_ALLINT_MSK 0x7B 84#define TWL6040_ALLINT_MSK 0x7B
84 85
@@ -135,4 +136,11 @@
135#define TWL6040_HPPLL_ID 1 136#define TWL6040_HPPLL_ID 1
136#define TWL6040_LPPLL_ID 2 137#define TWL6040_LPPLL_ID 2
137 138
139/* STATUS (0x2E) fields */
140
141#define TWL6040_PLUGCOMP 0x02
142
143void twl6040_hs_jack_detect(struct snd_soc_codec *codec,
144 struct snd_soc_jack *jack, int report);
145
138#endif /* End of __TWL6040_H__ */ 146#endif /* End of __TWL6040_H__ */
diff --git a/sound/soc/codecs/uda134x.c b/sound/soc/codecs/uda134x.c
index 464f0cfa4c7a..e76847a9438b 100644
--- a/sound/soc/codecs/uda134x.c
+++ b/sound/soc/codecs/uda134x.c
@@ -19,7 +19,6 @@
19#include <sound/pcm.h> 19#include <sound/pcm.h>
20#include <sound/pcm_params.h> 20#include <sound/pcm_params.h>
21#include <sound/soc.h> 21#include <sound/soc.h>
22#include <sound/soc-dapm.h>
23#include <sound/initval.h> 22#include <sound/initval.h>
24 23
25#include <sound/uda134x.h> 24#include <sound/uda134x.h>
@@ -389,7 +388,7 @@ static int uda134x_set_bias_level(struct snd_soc_codec *codec,
389 pd->power(0); 388 pd->power(0);
390 break; 389 break;
391 } 390 }
392 codec->bias_level = level; 391 codec->dapm.bias_level = level;
393 return 0; 392 return 0;
394} 393}
395 394
diff --git a/sound/soc/codecs/uda1380.c b/sound/soc/codecs/uda1380.c
index 0c6c725736c6..c5ca8cfea60f 100644
--- a/sound/soc/codecs/uda1380.c
+++ b/sound/soc/codecs/uda1380.c
@@ -27,7 +27,6 @@
27#include <sound/control.h> 27#include <sound/control.h>
28#include <sound/initval.h> 28#include <sound/initval.h>
29#include <sound/soc.h> 29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/tlv.h> 30#include <sound/tlv.h>
32#include <sound/uda1380.h> 31#include <sound/uda1380.h>
33 32
@@ -36,7 +35,6 @@
36/* codec private data */ 35/* codec private data */
37struct uda1380_priv { 36struct uda1380_priv {
38 struct snd_soc_codec *codec; 37 struct snd_soc_codec *codec;
39 u16 reg_cache[UDA1380_CACHEREGNUM];
40 unsigned int dac_clk; 38 unsigned int dac_clk;
41 struct work_struct work; 39 struct work_struct work;
42 void *control_data; 40 void *control_data;
@@ -414,10 +412,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
414 412
415static int uda1380_add_widgets(struct snd_soc_codec *codec) 413static int uda1380_add_widgets(struct snd_soc_codec *codec)
416{ 414{
417 snd_soc_dapm_new_controls(codec, uda1380_dapm_widgets, 415 struct snd_soc_dapm_context *dapm = &codec->dapm;
418 ARRAY_SIZE(uda1380_dapm_widgets));
419 416
420 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 417 snd_soc_dapm_new_controls(dapm, uda1380_dapm_widgets,
418 ARRAY_SIZE(uda1380_dapm_widgets));
419 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
421 420
422 return 0; 421 return 0;
423} 422}
@@ -603,7 +602,7 @@ static int uda1380_set_bias_level(struct snd_soc_codec *codec,
603 int reg; 602 int reg;
604 struct uda1380_platform_data *pdata = codec->dev->platform_data; 603 struct uda1380_platform_data *pdata = codec->dev->platform_data;
605 604
606 if (codec->bias_level == level) 605 if (codec->dapm.bias_level == level)
607 return 0; 606 return 0;
608 607
609 switch (level) { 608 switch (level) {
@@ -613,7 +612,7 @@ static int uda1380_set_bias_level(struct snd_soc_codec *codec,
613 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm); 612 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
614 break; 613 break;
615 case SND_SOC_BIAS_STANDBY: 614 case SND_SOC_BIAS_STANDBY:
616 if (codec->bias_level == SND_SOC_BIAS_OFF) { 615 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
617 if (gpio_is_valid(pdata->gpio_power)) { 616 if (gpio_is_valid(pdata->gpio_power)) {
618 gpio_set_value(pdata->gpio_power, 1); 617 gpio_set_value(pdata->gpio_power, 1);
619 mdelay(1); 618 mdelay(1);
@@ -636,7 +635,7 @@ static int uda1380_set_bias_level(struct snd_soc_codec *codec,
636 for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++) 635 for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++)
637 set_bit(reg - 0x10, &uda1380_cache_dirty); 636 set_bit(reg - 0x10, &uda1380_cache_dirty);
638 } 637 }
639 codec->bias_level = level; 638 codec->dapm.bias_level = level;
640 return 0; 639 return 0;
641} 640}
642 641
diff --git a/sound/soc/codecs/wl1273.c b/sound/soc/codecs/wl1273.c
index 0c47c788ccdf..d3ffa2f0122a 100644
--- a/sound/soc/codecs/wl1273.c
+++ b/sound/soc/codecs/wl1273.c
@@ -25,8 +25,7 @@
25#include <linux/slab.h> 25#include <linux/slab.h>
26#include <sound/pcm.h> 26#include <sound/pcm.h>
27#include <sound/pcm_params.h> 27#include <sound/pcm_params.h>
28#include <sound/soc-dai.h> 28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h> 29#include <sound/initval.h>
31 30
32#include "wl1273.h" 31#include "wl1273.h"
diff --git a/sound/soc/codecs/wm2000.c b/sound/soc/codecs/wm2000.c
index 4bcd168794e1..80ddf4fd23db 100644
--- a/sound/soc/codecs/wm2000.c
+++ b/sound/soc/codecs/wm2000.c
@@ -36,7 +36,6 @@
36#include <sound/pcm.h> 36#include <sound/pcm.h>
37#include <sound/pcm_params.h> 37#include <sound/pcm_params.h>
38#include <sound/soc.h> 38#include <sound/soc.h>
39#include <sound/soc-dapm.h>
40#include <sound/initval.h> 39#include <sound/initval.h>
41#include <sound/tlv.h> 40#include <sound/tlv.h>
42 41
@@ -705,6 +704,7 @@ static const struct snd_soc_dapm_route audio_map[] = {
705/* Called from the machine driver */ 704/* Called from the machine driver */
706int wm2000_add_controls(struct snd_soc_codec *codec) 705int wm2000_add_controls(struct snd_soc_codec *codec)
707{ 706{
707 struct snd_soc_dapm_context *dapm = &codec->dapm;
708 int ret; 708 int ret;
709 709
710 if (!wm2000_i2c) { 710 if (!wm2000_i2c) {
@@ -712,12 +712,12 @@ int wm2000_add_controls(struct snd_soc_codec *codec)
712 return -ENODEV; 712 return -ENODEV;
713 } 713 }
714 714
715 ret = snd_soc_dapm_new_controls(codec, wm2000_dapm_widgets, 715 ret = snd_soc_dapm_new_controls(dapm, wm2000_dapm_widgets,
716 ARRAY_SIZE(wm2000_dapm_widgets)); 716 ARRAY_SIZE(wm2000_dapm_widgets));
717 if (ret < 0) 717 if (ret < 0)
718 return ret; 718 return ret;
719 719
720 ret = snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 720 ret = snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
721 if (ret < 0) 721 if (ret < 0)
722 return ret; 722 return ret;
723 723
diff --git a/sound/soc/codecs/wm8350.c b/sound/soc/codecs/wm8350.c
index 7611add7f8c3..6d6dc9efe914 100644
--- a/sound/soc/codecs/wm8350.c
+++ b/sound/soc/codecs/wm8350.c
@@ -24,9 +24,9 @@
24#include <sound/pcm.h> 24#include <sound/pcm.h>
25#include <sound/pcm_params.h> 25#include <sound/pcm_params.h>
26#include <sound/soc.h> 26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h> 27#include <sound/initval.h>
29#include <sound/tlv.h> 28#include <sound/tlv.h>
29#include <trace/events/asoc.h>
30 30
31#include "wm8350.h" 31#include "wm8350.h"
32 32
@@ -54,6 +54,7 @@ struct wm8350_output {
54 54
55struct wm8350_jack_data { 55struct wm8350_jack_data {
56 struct snd_soc_jack *jack; 56 struct snd_soc_jack *jack;
57 struct delayed_work work;
57 int report; 58 int report;
58 int short_report; 59 int short_report;
59}; 60};
@@ -230,8 +231,9 @@ static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec)
230 */ 231 */
231static void wm8350_pga_work(struct work_struct *work) 232static void wm8350_pga_work(struct work_struct *work)
232{ 233{
233 struct snd_soc_codec *codec = 234 struct snd_soc_dapm_context *dapm =
234 container_of(work, struct snd_soc_codec, delayed_work.work); 235 container_of(work, struct snd_soc_dapm_context, delayed_work.work);
236 struct snd_soc_codec *codec = dapm->codec;
235 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec); 237 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
236 struct wm8350_output *out1 = &wm8350_data->out1, 238 struct wm8350_output *out1 = &wm8350_data->out1,
237 *out2 = &wm8350_data->out2; 239 *out2 = &wm8350_data->out2;
@@ -302,8 +304,8 @@ static int pga_event(struct snd_soc_dapm_widget *w,
302 out->ramp = WM8350_RAMP_UP; 304 out->ramp = WM8350_RAMP_UP;
303 out->active = 1; 305 out->active = 1;
304 306
305 if (!delayed_work_pending(&codec->delayed_work)) 307 if (!delayed_work_pending(&codec->dapm.delayed_work))
306 schedule_delayed_work(&codec->delayed_work, 308 schedule_delayed_work(&codec->dapm.delayed_work,
307 msecs_to_jiffies(1)); 309 msecs_to_jiffies(1));
308 break; 310 break;
309 311
@@ -311,8 +313,8 @@ static int pga_event(struct snd_soc_dapm_widget *w,
311 out->ramp = WM8350_RAMP_DOWN; 313 out->ramp = WM8350_RAMP_DOWN;
312 out->active = 0; 314 out->active = 0;
313 315
314 if (!delayed_work_pending(&codec->delayed_work)) 316 if (!delayed_work_pending(&codec->dapm.delayed_work))
315 schedule_delayed_work(&codec->delayed_work, 317 schedule_delayed_work(&codec->dapm.delayed_work,
316 msecs_to_jiffies(1)); 318 msecs_to_jiffies(1));
317 break; 319 break;
318 } 320 }
@@ -786,9 +788,10 @@ static const struct snd_soc_dapm_route audio_map[] = {
786 788
787static int wm8350_add_widgets(struct snd_soc_codec *codec) 789static int wm8350_add_widgets(struct snd_soc_codec *codec)
788{ 790{
791 struct snd_soc_dapm_context *dapm = &codec->dapm;
789 int ret; 792 int ret;
790 793
791 ret = snd_soc_dapm_new_controls(codec, 794 ret = snd_soc_dapm_new_controls(dapm,
792 wm8350_dapm_widgets, 795 wm8350_dapm_widgets,
793 ARRAY_SIZE(wm8350_dapm_widgets)); 796 ARRAY_SIZE(wm8350_dapm_widgets));
794 if (ret != 0) { 797 if (ret != 0) {
@@ -797,7 +800,7 @@ static int wm8350_add_widgets(struct snd_soc_codec *codec)
797 } 800 }
798 801
799 /* set up audio paths */ 802 /* set up audio paths */
800 ret = snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 803 ret = snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
801 if (ret != 0) { 804 if (ret != 0) {
802 dev_err(codec->dev, "DAPM route register failed\n"); 805 dev_err(codec->dev, "DAPM route register failed\n");
803 return ret; 806 return ret;
@@ -1184,7 +1187,7 @@ static int wm8350_set_bias_level(struct snd_soc_codec *codec,
1184 break; 1187 break;
1185 1188
1186 case SND_SOC_BIAS_STANDBY: 1189 case SND_SOC_BIAS_STANDBY:
1187 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1190 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1188 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), 1191 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
1189 priv->supplies); 1192 priv->supplies);
1190 if (ret != 0) 1193 if (ret != 0)
@@ -1317,7 +1320,7 @@ static int wm8350_set_bias_level(struct snd_soc_codec *codec,
1317 priv->supplies); 1320 priv->supplies);
1318 break; 1321 break;
1319 } 1322 }
1320 codec->bias_level = level; 1323 codec->dapm.bias_level = level;
1321 return 0; 1324 return 0;
1322} 1325}
1323 1326
@@ -1334,45 +1337,69 @@ static int wm8350_resume(struct snd_soc_codec *codec)
1334 return 0; 1337 return 0;
1335} 1338}
1336 1339
1337static irqreturn_t wm8350_hp_jack_handler(int irq, void *data) 1340static void wm8350_hp_work(struct wm8350_data *priv,
1341 struct wm8350_jack_data *jack,
1342 u16 mask)
1338{ 1343{
1339 struct wm8350_data *priv = data;
1340 struct wm8350 *wm8350 = priv->codec.control_data; 1344 struct wm8350 *wm8350 = priv->codec.control_data;
1341 u16 reg; 1345 u16 reg;
1342 int report; 1346 int report;
1343 int mask; 1347
1348 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1349 if (reg & mask)
1350 report = jack->report;
1351 else
1352 report = 0;
1353
1354 snd_soc_jack_report(jack->jack, report, jack->report);
1355
1356}
1357
1358static void wm8350_hpl_work(struct work_struct *work)
1359{
1360 struct wm8350_data *priv =
1361 container_of(work, struct wm8350_data, hpl.work.work);
1362
1363 wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);
1364}
1365
1366static void wm8350_hpr_work(struct work_struct *work)
1367{
1368 struct wm8350_data *priv =
1369 container_of(work, struct wm8350_data, hpr.work.work);
1370
1371 wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
1372}
1373
1374static irqreturn_t wm8350_hp_jack_handler(int irq, void *data)
1375{
1376 struct wm8350_data *priv = data;
1377 struct wm8350 *wm8350 = priv->codec.control_data;
1344 struct wm8350_jack_data *jack = NULL; 1378 struct wm8350_jack_data *jack = NULL;
1345 1379
1346 switch (irq - wm8350->irq_base) { 1380 switch (irq - wm8350->irq_base) {
1347 case WM8350_IRQ_CODEC_JCK_DET_L: 1381 case WM8350_IRQ_CODEC_JCK_DET_L:
1382#ifndef CONFIG_SND_SOC_WM8350_MODULE
1383 trace_snd_soc_jack_irq("WM8350 HPL");
1384#endif
1348 jack = &priv->hpl; 1385 jack = &priv->hpl;
1349 mask = WM8350_JACK_L_LVL;
1350 break; 1386 break;
1351 1387
1352 case WM8350_IRQ_CODEC_JCK_DET_R: 1388 case WM8350_IRQ_CODEC_JCK_DET_R:
1389#ifndef CONFIG_SND_SOC_WM8350_MODULE
1390 trace_snd_soc_jack_irq("WM8350 HPR");
1391#endif
1353 jack = &priv->hpr; 1392 jack = &priv->hpr;
1354 mask = WM8350_JACK_R_LVL;
1355 break; 1393 break;
1356 1394
1357 default: 1395 default:
1358 BUG(); 1396 BUG();
1359 } 1397 }
1360 1398
1361 if (!jack->jack) { 1399 if (device_may_wakeup(wm8350->dev))
1362 dev_warn(wm8350->dev, "Jack interrupt called with no jack\n"); 1400 pm_wakeup_event(wm8350->dev, 250);
1363 return IRQ_NONE;
1364 }
1365
1366 /* Debounce */
1367 msleep(200);
1368
1369 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1370 if (reg & mask)
1371 report = jack->report;
1372 else
1373 report = 0;
1374 1401
1375 snd_soc_jack_report(jack->jack, report, jack->report); 1402 schedule_delayed_work(&jack->work, 200);
1376 1403
1377 return IRQ_HANDLED; 1404 return IRQ_HANDLED;
1378} 1405}
@@ -1436,6 +1463,10 @@ static irqreturn_t wm8350_mic_handler(int irq, void *data)
1436 u16 reg; 1463 u16 reg;
1437 int report = 0; 1464 int report = 0;
1438 1465
1466#ifndef CONFIG_SND_SOC_WM8350_MODULE
1467 trace_snd_soc_jack_irq("WM8350 mic");
1468#endif
1469
1439 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); 1470 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1440 if (reg & WM8350_JACK_MICSCD_LVL) 1471 if (reg & WM8350_JACK_MICSCD_LVL)
1441 report |= priv->mic.short_report; 1472 report |= priv->mic.short_report;
@@ -1550,7 +1581,9 @@ static int wm8350_codec_probe(struct snd_soc_codec *codec)
1550 /* Put the codec into reset if it wasn't already */ 1581 /* Put the codec into reset if it wasn't already */
1551 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1582 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1552 1583
1553 INIT_DELAYED_WORK(&codec->delayed_work, wm8350_pga_work); 1584 INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work);
1585 INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);
1586 INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);
1554 1587
1555 /* Enable the codec */ 1588 /* Enable the codec */
1556 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); 1589 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
@@ -1626,7 +1659,6 @@ static int wm8350_codec_remove(struct snd_soc_codec *codec)
1626{ 1659{
1627 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec); 1660 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1628 struct wm8350 *wm8350 = dev_get_platdata(codec->dev); 1661 struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
1629 int ret;
1630 1662
1631 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, 1663 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1632 WM8350_JDL_ENA | WM8350_JDR_ENA); 1664 WM8350_JDL_ENA | WM8350_JDR_ENA);
@@ -1641,15 +1673,12 @@ static int wm8350_codec_remove(struct snd_soc_codec *codec)
1641 priv->hpr.jack = NULL; 1673 priv->hpr.jack = NULL;
1642 priv->mic.jack = NULL; 1674 priv->mic.jack = NULL;
1643 1675
1644 /* cancel any work waiting to be queued. */ 1676 cancel_delayed_work_sync(&priv->hpl.work);
1645 ret = cancel_delayed_work(&codec->delayed_work); 1677 cancel_delayed_work_sync(&priv->hpr.work);
1646 1678
1647 /* if there was any work waiting then we run it now and 1679 /* if there was any work waiting then we run it now and
1648 * wait for its completion */ 1680 * wait for its completion */
1649 if (ret) { 1681 flush_delayed_work_sync(&codec->dapm.delayed_work);
1650 schedule_delayed_work(&codec->delayed_work, 0);
1651 flush_scheduled_work();
1652 }
1653 1682
1654 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF); 1683 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1655 1684
diff --git a/sound/soc/codecs/wm8400.c b/sound/soc/codecs/wm8400.c
index 850299786e02..3c3bc079167e 100644
--- a/sound/soc/codecs/wm8400.c
+++ b/sound/soc/codecs/wm8400.c
@@ -26,7 +26,6 @@
26#include <sound/pcm.h> 26#include <sound/pcm.h>
27#include <sound/pcm_params.h> 27#include <sound/pcm_params.h>
28#include <sound/soc.h> 28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h> 29#include <sound/initval.h>
31#include <sound/tlv.h> 30#include <sound/tlv.h>
32 31
@@ -911,10 +910,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
911 910
912static int wm8400_add_widgets(struct snd_soc_codec *codec) 911static int wm8400_add_widgets(struct snd_soc_codec *codec)
913{ 912{
914 snd_soc_dapm_new_controls(codec, wm8400_dapm_widgets, 913 struct snd_soc_dapm_context *dapm = &codec->dapm;
915 ARRAY_SIZE(wm8400_dapm_widgets));
916 914
917 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 915 snd_soc_dapm_new_controls(dapm, wm8400_dapm_widgets,
916 ARRAY_SIZE(wm8400_dapm_widgets));
917 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
918 918
919 return 0; 919 return 0;
920} 920}
@@ -1219,7 +1219,7 @@ static int wm8400_set_bias_level(struct snd_soc_codec *codec,
1219 break; 1219 break;
1220 1220
1221 case SND_SOC_BIAS_STANDBY: 1221 case SND_SOC_BIAS_STANDBY:
1222 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1222 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1223 ret = regulator_bulk_enable(ARRAY_SIZE(power), 1223 ret = regulator_bulk_enable(ARRAY_SIZE(power),
1224 &power[0]); 1224 &power[0]);
1225 if (ret != 0) { 1225 if (ret != 0) {
@@ -1306,7 +1306,7 @@ static int wm8400_set_bias_level(struct snd_soc_codec *codec,
1306 break; 1306 break;
1307 } 1307 }
1308 1308
1309 codec->bias_level = level; 1309 codec->dapm.bias_level = level;
1310 return 0; 1310 return 0;
1311} 1311}
1312 1312
diff --git a/sound/soc/codecs/wm8510.c b/sound/soc/codecs/wm8510.c
index 8f107095760e..db0dced74843 100644
--- a/sound/soc/codecs/wm8510.c
+++ b/sound/soc/codecs/wm8510.c
@@ -24,7 +24,6 @@
24#include <sound/pcm.h> 24#include <sound/pcm.h>
25#include <sound/pcm_params.h> 25#include <sound/pcm_params.h>
26#include <sound/soc.h> 26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h> 27#include <sound/initval.h>
29 28
30#include "wm8510.h" 29#include "wm8510.h"
@@ -216,10 +215,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
216 215
217static int wm8510_add_widgets(struct snd_soc_codec *codec) 216static int wm8510_add_widgets(struct snd_soc_codec *codec)
218{ 217{
219 snd_soc_dapm_new_controls(codec, wm8510_dapm_widgets, 218 struct snd_soc_dapm_context *dapm = &codec->dapm;
220 ARRAY_SIZE(wm8510_dapm_widgets));
221 219
222 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 220 snd_soc_dapm_new_controls(dapm, wm8510_dapm_widgets,
221 ARRAY_SIZE(wm8510_dapm_widgets));
222 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
223 223
224 return 0; 224 return 0;
225} 225}
@@ -478,7 +478,7 @@ static int wm8510_set_bias_level(struct snd_soc_codec *codec,
478 case SND_SOC_BIAS_STANDBY: 478 case SND_SOC_BIAS_STANDBY:
479 power1 |= WM8510_POWER1_BIASEN | WM8510_POWER1_BUFIOEN; 479 power1 |= WM8510_POWER1_BIASEN | WM8510_POWER1_BUFIOEN;
480 480
481 if (codec->bias_level == SND_SOC_BIAS_OFF) { 481 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
482 /* Initial cap charge at VMID 5k */ 482 /* Initial cap charge at VMID 5k */
483 snd_soc_write(codec, WM8510_POWER1, power1 | 0x3); 483 snd_soc_write(codec, WM8510_POWER1, power1 | 0x3);
484 mdelay(100); 484 mdelay(100);
@@ -495,7 +495,7 @@ static int wm8510_set_bias_level(struct snd_soc_codec *codec,
495 break; 495 break;
496 } 496 }
497 497
498 codec->bias_level = level; 498 codec->dapm.bias_level = level;
499 return 0; 499 return 0;
500} 500}
501 501
diff --git a/sound/soc/codecs/wm8523.c b/sound/soc/codecs/wm8523.c
index deca79ea2b4b..5eb2f501ce32 100644
--- a/sound/soc/codecs/wm8523.c
+++ b/sound/soc/codecs/wm8523.c
@@ -24,7 +24,6 @@
24#include <sound/pcm.h> 24#include <sound/pcm.h>
25#include <sound/pcm_params.h> 25#include <sound/pcm_params.h>
26#include <sound/soc.h> 26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h> 27#include <sound/initval.h>
29#include <sound/tlv.h> 28#include <sound/tlv.h>
30 29
@@ -109,10 +108,11 @@ static const struct snd_soc_dapm_route intercon[] = {
109 108
110static int wm8523_add_widgets(struct snd_soc_codec *codec) 109static int wm8523_add_widgets(struct snd_soc_codec *codec)
111{ 110{
112 snd_soc_dapm_new_controls(codec, wm8523_dapm_widgets, 111 struct snd_soc_dapm_context *dapm = &codec->dapm;
113 ARRAY_SIZE(wm8523_dapm_widgets));
114 112
115 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 113 snd_soc_dapm_new_controls(dapm, wm8523_dapm_widgets,
114 ARRAY_SIZE(wm8523_dapm_widgets));
115 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
116 116
117 return 0; 117 return 0;
118} 118}
@@ -327,7 +327,7 @@ static int wm8523_set_bias_level(struct snd_soc_codec *codec,
327 break; 327 break;
328 328
329 case SND_SOC_BIAS_STANDBY: 329 case SND_SOC_BIAS_STANDBY:
330 if (codec->bias_level == SND_SOC_BIAS_OFF) { 330 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
331 ret = regulator_bulk_enable(ARRAY_SIZE(wm8523->supplies), 331 ret = regulator_bulk_enable(ARRAY_SIZE(wm8523->supplies),
332 wm8523->supplies); 332 wm8523->supplies);
333 if (ret != 0) { 333 if (ret != 0) {
@@ -366,7 +366,7 @@ static int wm8523_set_bias_level(struct snd_soc_codec *codec,
366 wm8523->supplies); 366 wm8523->supplies);
367 break; 367 break;
368 } 368 }
369 codec->bias_level = level; 369 codec->dapm.bias_level = level;
370 return 0; 370 return 0;
371} 371}
372 372
diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c
index 8725d4e75431..8f6b5ee6645b 100644
--- a/sound/soc/codecs/wm8580.c
+++ b/sound/soc/codecs/wm8580.c
@@ -31,7 +31,6 @@
31#include <sound/pcm.h> 31#include <sound/pcm.h>
32#include <sound/pcm_params.h> 32#include <sound/pcm_params.h>
33#include <sound/soc.h> 33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/tlv.h> 34#include <sound/tlv.h>
36#include <sound/initval.h> 35#include <sound/initval.h>
37#include <asm/div64.h> 36#include <asm/div64.h>
@@ -191,7 +190,6 @@ static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
191struct wm8580_priv { 190struct wm8580_priv {
192 enum snd_soc_control_type control_type; 191 enum snd_soc_control_type control_type;
193 struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES]; 192 struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
194 u16 reg_cache[WM8580_MAX_REGISTER + 1];
195 struct pll_state a; 193 struct pll_state a;
196 struct pll_state b; 194 struct pll_state b;
197 int sysclk[2]; 195 int sysclk[2];
@@ -302,10 +300,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
302 300
303static int wm8580_add_widgets(struct snd_soc_codec *codec) 301static int wm8580_add_widgets(struct snd_soc_codec *codec)
304{ 302{
305 snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets, 303 struct snd_soc_dapm_context *dapm = &codec->dapm;
306 ARRAY_SIZE(wm8580_dapm_widgets));
307 304
308 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 305 snd_soc_dapm_new_controls(dapm, wm8580_dapm_widgets,
306 ARRAY_SIZE(wm8580_dapm_widgets));
307 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
309 308
310 return 0; 309 return 0;
311} 310}
@@ -507,13 +506,13 @@ static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
507 } 506 }
508 507
509 /* Look up the SYSCLK ratio; accept only exact matches */ 508 /* Look up the SYSCLK ratio; accept only exact matches */
510 ratio = wm8580->sysclk[dai->id] / params_rate(params); 509 ratio = wm8580->sysclk[dai->driver->id] / params_rate(params);
511 for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++) 510 for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
512 if (ratio == wm8580_sysclk_ratios[i]) 511 if (ratio == wm8580_sysclk_ratios[i])
513 break; 512 break;
514 if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) { 513 if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
515 dev_err(codec->dev, "Invalid clock ratio %d/%d\n", 514 dev_err(codec->dev, "Invalid clock ratio %d/%d\n",
516 wm8580->sysclk[dai->id], params_rate(params)); 515 wm8580->sysclk[dai->driver->id], params_rate(params));
517 return -EINVAL; 516 return -EINVAL;
518 } 517 }
519 paifa |= i; 518 paifa |= i;
@@ -716,7 +715,7 @@ static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
716 715
717 switch (clk_id) { 716 switch (clk_id) {
718 case WM8580_CLKSRC_ADCMCLK: 717 case WM8580_CLKSRC_ADCMCLK:
719 if (dai->id != WM8580_DAI_PAIFTX) 718 if (dai->driver->id != WM8580_DAI_PAIFTX)
720 return -EINVAL; 719 return -EINVAL;
721 sel = 0 << sel_shift; 720 sel = 0 << sel_shift;
722 break; 721 break;
@@ -735,7 +734,7 @@ static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
735 } 734 }
736 735
737 /* We really should validate PLL settings but not yet */ 736 /* We really should validate PLL settings but not yet */
738 wm8580->sysclk[dai->id] = freq; 737 wm8580->sysclk[dai->driver->id] = freq;
739 738
740 return snd_soc_update_bits(codec, WM8580_CLKSEL, sel_mask, sel); 739 return snd_soc_update_bits(codec, WM8580_CLKSEL, sel_mask, sel);
741} 740}
@@ -767,7 +766,7 @@ static int wm8580_set_bias_level(struct snd_soc_codec *codec,
767 break; 766 break;
768 767
769 case SND_SOC_BIAS_STANDBY: 768 case SND_SOC_BIAS_STANDBY:
770 if (codec->bias_level == SND_SOC_BIAS_OFF) { 769 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
771 /* Power up and get individual control of the DACs */ 770 /* Power up and get individual control of the DACs */
772 reg = snd_soc_read(codec, WM8580_PWRDN1); 771 reg = snd_soc_read(codec, WM8580_PWRDN1);
773 reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD); 772 reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD);
@@ -785,7 +784,7 @@ static int wm8580_set_bias_level(struct snd_soc_codec *codec,
785 snd_soc_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN); 784 snd_soc_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
786 break; 785 break;
787 } 786 }
788 codec->bias_level = level; 787 codec->dapm.bias_level = level;
789 return 0; 788 return 0;
790} 789}
791 790
@@ -905,7 +904,7 @@ static struct snd_soc_codec_driver soc_codec_dev_wm8580 = {
905 .set_bias_level = wm8580_set_bias_level, 904 .set_bias_level = wm8580_set_bias_level,
906 .reg_cache_size = ARRAY_SIZE(wm8580_reg), 905 .reg_cache_size = ARRAY_SIZE(wm8580_reg),
907 .reg_word_size = sizeof(u16), 906 .reg_word_size = sizeof(u16),
908 .reg_cache_default = &wm8580_reg, 907 .reg_cache_default = wm8580_reg,
909}; 908};
910 909
911#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 910#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
diff --git a/sound/soc/codecs/wm8711.c b/sound/soc/codecs/wm8711.c
index 54fbd76c8bca..97c30382d3ff 100644
--- a/sound/soc/codecs/wm8711.c
+++ b/sound/soc/codecs/wm8711.c
@@ -25,7 +25,6 @@
25#include <sound/pcm.h> 25#include <sound/pcm.h>
26#include <sound/pcm_params.h> 26#include <sound/pcm_params.h>
27#include <sound/soc.h> 27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/tlv.h> 28#include <sound/tlv.h>
30#include <sound/initval.h> 29#include <sound/initval.h>
31 30
@@ -34,7 +33,6 @@
34/* codec private data */ 33/* codec private data */
35struct wm8711_priv { 34struct wm8711_priv {
36 enum snd_soc_control_type bus_type; 35 enum snd_soc_control_type bus_type;
37 u16 reg_cache[WM8711_CACHEREGNUM];
38 unsigned int sysclk; 36 unsigned int sysclk;
39}; 37};
40 38
@@ -93,10 +91,11 @@ static const struct snd_soc_dapm_route intercon[] = {
93 91
94static int wm8711_add_widgets(struct snd_soc_codec *codec) 92static int wm8711_add_widgets(struct snd_soc_codec *codec)
95{ 93{
96 snd_soc_dapm_new_controls(codec, wm8711_dapm_widgets, 94 struct snd_soc_dapm_context *dapm = &codec->dapm;
97 ARRAY_SIZE(wm8711_dapm_widgets));
98 95
99 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 96 snd_soc_dapm_new_controls(dapm, wm8711_dapm_widgets,
97 ARRAY_SIZE(wm8711_dapm_widgets));
98 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
100 99
101 return 0; 100 return 0;
102} 101}
@@ -318,7 +317,7 @@ static int wm8711_set_bias_level(struct snd_soc_codec *codec,
318 snd_soc_write(codec, WM8711_PWR, 0xffff); 317 snd_soc_write(codec, WM8711_PWR, 0xffff);
319 break; 318 break;
320 } 319 }
321 codec->bias_level = level; 320 codec->dapm.bias_level = level;
322 return 0; 321 return 0;
323} 322}
324 323
diff --git a/sound/soc/codecs/wm8728.c b/sound/soc/codecs/wm8728.c
index 075f35e4f4cb..736b0352d0a7 100644
--- a/sound/soc/codecs/wm8728.c
+++ b/sound/soc/codecs/wm8728.c
@@ -23,7 +23,6 @@
23#include <sound/pcm.h> 23#include <sound/pcm.h>
24#include <sound/pcm_params.h> 24#include <sound/pcm_params.h>
25#include <sound/soc.h> 25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h> 26#include <sound/initval.h>
28#include <sound/tlv.h> 27#include <sound/tlv.h>
29 28
@@ -73,10 +72,11 @@ static const struct snd_soc_dapm_route intercon[] = {
73 72
74static int wm8728_add_widgets(struct snd_soc_codec *codec) 73static int wm8728_add_widgets(struct snd_soc_codec *codec)
75{ 74{
76 snd_soc_dapm_new_controls(codec, wm8728_dapm_widgets, 75 struct snd_soc_dapm_context *dapm = &codec->dapm;
77 ARRAY_SIZE(wm8728_dapm_widgets));
78 76
79 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 77 snd_soc_dapm_new_controls(dapm, wm8728_dapm_widgets,
78 ARRAY_SIZE(wm8728_dapm_widgets));
79 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
80 80
81 return 0; 81 return 0;
82} 82}
@@ -180,7 +180,7 @@ static int wm8728_set_bias_level(struct snd_soc_codec *codec,
180 case SND_SOC_BIAS_ON: 180 case SND_SOC_BIAS_ON:
181 case SND_SOC_BIAS_PREPARE: 181 case SND_SOC_BIAS_PREPARE:
182 case SND_SOC_BIAS_STANDBY: 182 case SND_SOC_BIAS_STANDBY:
183 if (codec->bias_level == SND_SOC_BIAS_OFF) { 183 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
184 /* Power everything up... */ 184 /* Power everything up... */
185 reg = snd_soc_read(codec, WM8728_DACCTL); 185 reg = snd_soc_read(codec, WM8728_DACCTL);
186 snd_soc_write(codec, WM8728_DACCTL, reg & ~0x4); 186 snd_soc_write(codec, WM8728_DACCTL, reg & ~0x4);
@@ -197,7 +197,7 @@ static int wm8728_set_bias_level(struct snd_soc_codec *codec,
197 snd_soc_write(codec, WM8728_DACCTL, reg | 0x4); 197 snd_soc_write(codec, WM8728_DACCTL, reg | 0x4);
198 break; 198 break;
199 } 199 }
200 codec->bias_level = level; 200 codec->dapm.bias_level = level;
201 return 0; 201 return 0;
202} 202}
203 203
diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c
index e725c09a3e79..0a67c31b2663 100644
--- a/sound/soc/codecs/wm8731.c
+++ b/sound/soc/codecs/wm8731.c
@@ -26,7 +26,6 @@
26#include <sound/pcm.h> 26#include <sound/pcm.h>
27#include <sound/pcm_params.h> 27#include <sound/pcm_params.h>
28#include <sound/soc.h> 28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h> 29#include <sound/initval.h>
31#include <sound/tlv.h> 30#include <sound/tlv.h>
32 31
@@ -44,9 +43,10 @@ static const char *wm8731_supply_names[WM8731_NUM_SUPPLIES] = {
44struct wm8731_priv { 43struct wm8731_priv {
45 enum snd_soc_control_type control_type; 44 enum snd_soc_control_type control_type;
46 struct regulator_bulk_data supplies[WM8731_NUM_SUPPLIES]; 45 struct regulator_bulk_data supplies[WM8731_NUM_SUPPLIES];
47 u16 reg_cache[WM8731_CACHEREGNUM];
48 unsigned int sysclk; 46 unsigned int sysclk;
49 int sysclk_type; 47 int sysclk_type;
48 int playback_fs;
49 bool deemph;
50}; 50};
51 51
52 52
@@ -65,16 +65,79 @@ static const u16 wm8731_reg[WM8731_CACHEREGNUM] = {
65#define wm8731_reset(c) snd_soc_write(c, WM8731_RESET, 0) 65#define wm8731_reset(c) snd_soc_write(c, WM8731_RESET, 0)
66 66
67static const char *wm8731_input_select[] = {"Line In", "Mic"}; 67static const char *wm8731_input_select[] = {"Line In", "Mic"};
68static const char *wm8731_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
69 68
70static const struct soc_enum wm8731_enum[] = { 69static const struct soc_enum wm8731_insel_enum =
71 SOC_ENUM_SINGLE(WM8731_APANA, 2, 2, wm8731_input_select), 70 SOC_ENUM_SINGLE(WM8731_APANA, 2, 2, wm8731_input_select);
72 SOC_ENUM_SINGLE(WM8731_APDIGI, 1, 4, wm8731_deemph), 71
73}; 72static int wm8731_deemph[] = { 0, 32000, 44100, 48000 };
73
74static int wm8731_set_deemph(struct snd_soc_codec *codec)
75{
76 struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec);
77 int val, i, best;
78
79 /* If we're using deemphasis select the nearest available sample
80 * rate.
81 */
82 if (wm8731->deemph) {
83 best = 1;
84 for (i = 2; i < ARRAY_SIZE(wm8731_deemph); i++) {
85 if (abs(wm8731_deemph[i] - wm8731->playback_fs) <
86 abs(wm8731_deemph[best] - wm8731->playback_fs))
87 best = i;
88 }
89
90 val = best << 1;
91 } else {
92 best = 0;
93 val = 0;
94 }
95
96 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
97 best, wm8731_deemph[best]);
98
99 return snd_soc_update_bits(codec, WM8731_APDIGI, 0x6, val);
100}
101
102static int wm8731_get_deemph(struct snd_kcontrol *kcontrol,
103 struct snd_ctl_elem_value *ucontrol)
104{
105 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
106 struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec);
107
108 ucontrol->value.enumerated.item[0] = wm8731->deemph;
109
110 return 0;
111}
112
113static int wm8731_put_deemph(struct snd_kcontrol *kcontrol,
114 struct snd_ctl_elem_value *ucontrol)
115{
116 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
117 struct wm8731_priv *wm8731 = snd_soc_codec_get_drvdata(codec);
118 int deemph = ucontrol->value.enumerated.item[0];
119 int ret = 0;
120
121 if (deemph > 1)
122 return -EINVAL;
123
124 mutex_lock(&codec->mutex);
125 if (wm8731->deemph != deemph) {
126 wm8731->deemph = deemph;
127
128 wm8731_set_deemph(codec);
129
130 ret = 1;
131 }
132 mutex_unlock(&codec->mutex);
133
134 return ret;
135}
74 136
75static const DECLARE_TLV_DB_SCALE(in_tlv, -3450, 150, 0); 137static const DECLARE_TLV_DB_SCALE(in_tlv, -3450, 150, 0);
76static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -1500, 300, 0); 138static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -1500, 300, 0);
77static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); 139static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
140static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 2000, 0);
78 141
79static const struct snd_kcontrol_new wm8731_snd_controls[] = { 142static const struct snd_kcontrol_new wm8731_snd_controls[] = {
80 143
@@ -87,7 +150,7 @@ SOC_DOUBLE_R_TLV("Capture Volume", WM8731_LINVOL, WM8731_RINVOL, 0, 31, 0,
87 in_tlv), 150 in_tlv),
88SOC_DOUBLE_R("Line Capture Switch", WM8731_LINVOL, WM8731_RINVOL, 7, 1, 1), 151SOC_DOUBLE_R("Line Capture Switch", WM8731_LINVOL, WM8731_RINVOL, 7, 1, 1),
89 152
90SOC_SINGLE("Mic Boost (+20dB)", WM8731_APANA, 0, 1, 0), 153SOC_SINGLE_TLV("Mic Boost Volume", WM8731_APANA, 0, 1, 0, mic_tlv),
91SOC_SINGLE("Mic Capture Switch", WM8731_APANA, 1, 1, 1), 154SOC_SINGLE("Mic Capture Switch", WM8731_APANA, 1, 1, 1),
92 155
93SOC_SINGLE_TLV("Sidetone Playback Volume", WM8731_APANA, 6, 3, 1, 156SOC_SINGLE_TLV("Sidetone Playback Volume", WM8731_APANA, 6, 3, 1,
@@ -96,7 +159,8 @@ SOC_SINGLE_TLV("Sidetone Playback Volume", WM8731_APANA, 6, 3, 1,
96SOC_SINGLE("ADC High Pass Filter Switch", WM8731_APDIGI, 0, 1, 1), 159SOC_SINGLE("ADC High Pass Filter Switch", WM8731_APDIGI, 0, 1, 1),
97SOC_SINGLE("Store DC Offset Switch", WM8731_APDIGI, 4, 1, 0), 160SOC_SINGLE("Store DC Offset Switch", WM8731_APDIGI, 4, 1, 0),
98 161
99SOC_ENUM("Playback De-emphasis", wm8731_enum[1]), 162SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
163 wm8731_get_deemph, wm8731_put_deemph),
100}; 164};
101 165
102/* Output Mixer */ 166/* Output Mixer */
@@ -108,7 +172,7 @@ SOC_DAPM_SINGLE("HiFi Playback Switch", WM8731_APANA, 4, 1, 0),
108 172
109/* Input mux */ 173/* Input mux */
110static const struct snd_kcontrol_new wm8731_input_mux_controls = 174static const struct snd_kcontrol_new wm8731_input_mux_controls =
111SOC_DAPM_ENUM("Input Select", wm8731_enum[0]); 175SOC_DAPM_ENUM("Input Select", wm8731_insel_enum);
112 176
113static const struct snd_soc_dapm_widget wm8731_dapm_widgets[] = { 177static const struct snd_soc_dapm_widget wm8731_dapm_widgets[] = {
114SND_SOC_DAPM_SUPPLY("OSC", WM8731_PWR, 5, 1, NULL, 0), 178SND_SOC_DAPM_SUPPLY("OSC", WM8731_PWR, 5, 1, NULL, 0),
@@ -165,10 +229,11 @@ static const struct snd_soc_dapm_route intercon[] = {
165 229
166static int wm8731_add_widgets(struct snd_soc_codec *codec) 230static int wm8731_add_widgets(struct snd_soc_codec *codec)
167{ 231{
168 snd_soc_dapm_new_controls(codec, wm8731_dapm_widgets, 232 struct snd_soc_dapm_context *dapm = &codec->dapm;
169 ARRAY_SIZE(wm8731_dapm_widgets));
170 233
171 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 234 snd_soc_dapm_new_controls(dapm, wm8731_dapm_widgets,
235 ARRAY_SIZE(wm8731_dapm_widgets));
236 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
172 237
173 return 0; 238 return 0;
174} 239}
@@ -239,6 +304,8 @@ static int wm8731_hw_params(struct snd_pcm_substream *substream,
239 u16 srate = (coeff_div[i].sr << 2) | 304 u16 srate = (coeff_div[i].sr << 2) |
240 (coeff_div[i].bosr << 1) | coeff_div[i].usb; 305 (coeff_div[i].bosr << 1) | coeff_div[i].usb;
241 306
307 wm8731->playback_fs = params_rate(params);
308
242 snd_soc_write(codec, WM8731_SRATE, srate); 309 snd_soc_write(codec, WM8731_SRATE, srate);
243 310
244 /* bit size */ 311 /* bit size */
@@ -253,6 +320,8 @@ static int wm8731_hw_params(struct snd_pcm_substream *substream,
253 break; 320 break;
254 } 321 }
255 322
323 wm8731_set_deemph(codec);
324
256 snd_soc_write(codec, WM8731_IFACE, iface); 325 snd_soc_write(codec, WM8731_IFACE, iface);
257 return 0; 326 return 0;
258} 327}
@@ -319,7 +388,7 @@ static int wm8731_set_dai_sysclk(struct snd_soc_dai *codec_dai,
319 return -EINVAL; 388 return -EINVAL;
320 } 389 }
321 390
322 snd_soc_dapm_sync(codec); 391 snd_soc_dapm_sync(&codec->dapm);
323 392
324 return 0; 393 return 0;
325} 394}
@@ -399,7 +468,7 @@ static int wm8731_set_bias_level(struct snd_soc_codec *codec,
399 case SND_SOC_BIAS_PREPARE: 468 case SND_SOC_BIAS_PREPARE:
400 break; 469 break;
401 case SND_SOC_BIAS_STANDBY: 470 case SND_SOC_BIAS_STANDBY:
402 if (codec->bias_level == SND_SOC_BIAS_OFF) { 471 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
403 ret = regulator_bulk_enable(ARRAY_SIZE(wm8731->supplies), 472 ret = regulator_bulk_enable(ARRAY_SIZE(wm8731->supplies),
404 wm8731->supplies); 473 wm8731->supplies);
405 if (ret != 0) 474 if (ret != 0)
@@ -428,7 +497,7 @@ static int wm8731_set_bias_level(struct snd_soc_codec *codec,
428 wm8731->supplies); 497 wm8731->supplies);
429 break; 498 break;
430 } 499 }
431 codec->bias_level = level; 500 codec->dapm.bias_level = level;
432 return 0; 501 return 0;
433} 502}
434 503
@@ -542,7 +611,6 @@ err_regulator_enable:
542err_regulator_get: 611err_regulator_get:
543 regulator_bulk_free(ARRAY_SIZE(wm8731->supplies), wm8731->supplies); 612 regulator_bulk_free(ARRAY_SIZE(wm8731->supplies), wm8731->supplies);
544 613
545 kfree(wm8731);
546 return ret; 614 return ret;
547} 615}
548 616
diff --git a/sound/soc/codecs/wm8737.c b/sound/soc/codecs/wm8737.c
new file mode 100644
index 000000000000..30c67d06a904
--- /dev/null
+++ b/sound/soc/codecs/wm8737.c
@@ -0,0 +1,754 @@
1/*
2 * wm8737.c -- WM8737 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/i2c.h>
19#include <linux/platform_device.h>
20#include <linux/regulator/consumer.h>
21#include <linux/spi/spi.h>
22#include <linux/slab.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30
31#include "wm8737.h"
32
33#define WM8737_NUM_SUPPLIES 4
34static const char *wm8737_supply_names[WM8737_NUM_SUPPLIES] = {
35 "DCVDD",
36 "DBVDD",
37 "AVDD",
38 "MVDD",
39};
40
41/* codec private data */
42struct wm8737_priv {
43 enum snd_soc_control_type control_type;
44 struct regulator_bulk_data supplies[WM8737_NUM_SUPPLIES];
45 unsigned int mclk;
46};
47
48static const u16 wm8737_reg[WM8737_REGISTER_COUNT] = {
49 0x00C3, /* R0 - Left PGA volume */
50 0x00C3, /* R1 - Right PGA volume */
51 0x0007, /* R2 - AUDIO path L */
52 0x0007, /* R3 - AUDIO path R */
53 0x0000, /* R4 - 3D Enhance */
54 0x0000, /* R5 - ADC Control */
55 0x0000, /* R6 - Power Management */
56 0x000A, /* R7 - Audio Format */
57 0x0000, /* R8 - Clocking */
58 0x000F, /* R9 - MIC Preamp Control */
59 0x0003, /* R10 - Misc Bias Control */
60 0x0000, /* R11 - Noise Gate */
61 0x007C, /* R12 - ALC1 */
62 0x0000, /* R13 - ALC2 */
63 0x0032, /* R14 - ALC3 */
64};
65
66static int wm8737_reset(struct snd_soc_codec *codec)
67{
68 return snd_soc_write(codec, WM8737_RESET, 0);
69}
70
71static const unsigned int micboost_tlv[] = {
72 TLV_DB_RANGE_HEAD(4),
73 0, 0, TLV_DB_SCALE_ITEM(1300, 0, 0),
74 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
75 2, 2, TLV_DB_SCALE_ITEM(2800, 0, 0),
76 3, 3, TLV_DB_SCALE_ITEM(3300, 0, 0),
77};
78static const DECLARE_TLV_DB_SCALE(pga_tlv, -9750, 50, 1);
79static const DECLARE_TLV_DB_SCALE(adc_tlv, -600, 600, 0);
80static const DECLARE_TLV_DB_SCALE(ng_tlv, -7800, 600, 0);
81static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -1200, 600, 0);
82static const DECLARE_TLV_DB_SCALE(alc_target_tlv, -1800, 100, 0);
83
84static const char *micbias_enum_text[] = {
85 "25%",
86 "50%",
87 "75%",
88 "100%",
89};
90
91static const struct soc_enum micbias_enum =
92 SOC_ENUM_SINGLE(WM8737_MIC_PREAMP_CONTROL, 0, 4, micbias_enum_text);
93
94static const char *low_cutoff_text[] = {
95 "Low", "High"
96};
97
98static const struct soc_enum low_3d =
99 SOC_ENUM_SINGLE(WM8737_3D_ENHANCE, 6, 2, low_cutoff_text);
100
101static const char *high_cutoff_text[] = {
102 "High", "Low"
103};
104
105static const struct soc_enum high_3d =
106 SOC_ENUM_SINGLE(WM8737_3D_ENHANCE, 5, 2, high_cutoff_text);
107
108static const char *alc_fn_text[] = {
109 "Disabled", "Right", "Left", "Stereo"
110};
111
112static const struct soc_enum alc_fn =
113 SOC_ENUM_SINGLE(WM8737_ALC1, 7, 4, alc_fn_text);
114
115static const char *alc_hold_text[] = {
116 "0", "2.67ms", "5.33ms", "10.66ms", "21.32ms", "42.64ms", "85.28ms",
117 "170.56ms", "341.12ms", "682.24ms", "1.364s", "2.728s", "5.458s",
118 "10.916s", "21.832s", "43.691s"
119};
120
121static const struct soc_enum alc_hold =
122 SOC_ENUM_SINGLE(WM8737_ALC2, 0, 16, alc_hold_text);
123
124static const char *alc_atk_text[] = {
125 "8.4ms", "16.8ms", "33.6ms", "67.2ms", "134.4ms", "268.8ms", "537.6ms",
126 "1.075s", "2.15s", "4.3s", "8.6s"
127};
128
129static const struct soc_enum alc_atk =
130 SOC_ENUM_SINGLE(WM8737_ALC3, 0, 11, alc_atk_text);
131
132static const char *alc_dcy_text[] = {
133 "33.6ms", "67.2ms", "134.4ms", "268.8ms", "537.6ms", "1.075s", "2.15s",
134 "4.3s", "8.6s", "17.2s", "34.41s"
135};
136
137static const struct soc_enum alc_dcy =
138 SOC_ENUM_SINGLE(WM8737_ALC3, 4, 11, alc_dcy_text);
139
140static const struct snd_kcontrol_new wm8737_snd_controls[] = {
141SOC_DOUBLE_R_TLV("Mic Boost Volume", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
142 6, 3, 0, micboost_tlv),
143SOC_DOUBLE_R("Mic Boost Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
144 4, 1, 0),
145SOC_DOUBLE("Mic ZC Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
146 3, 1, 0),
147
148SOC_DOUBLE_R_TLV("Capture Volume", WM8737_LEFT_PGA_VOLUME,
149 WM8737_RIGHT_PGA_VOLUME, 0, 255, 0, pga_tlv),
150SOC_DOUBLE("Capture ZC Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
151 2, 1, 0),
152
153SOC_DOUBLE("INPUT1 DC Bias Switch", WM8737_MISC_BIAS_CONTROL, 0, 1, 1, 0),
154
155SOC_ENUM("Mic PGA Bias", micbias_enum),
156SOC_SINGLE("ADC Low Power Switch", WM8737_ADC_CONTROL, 2, 1, 0),
157SOC_SINGLE("High Pass Filter Switch", WM8737_ADC_CONTROL, 0, 1, 1),
158SOC_DOUBLE("Polarity Invert Switch", WM8737_ADC_CONTROL, 5, 6, 1, 0),
159
160SOC_SINGLE("3D Switch", WM8737_3D_ENHANCE, 0, 1, 0),
161SOC_SINGLE("3D Depth", WM8737_3D_ENHANCE, 1, 15, 0),
162SOC_ENUM("3D Low Cut-off", low_3d),
163SOC_ENUM("3D High Cut-off", low_3d),
164SOC_SINGLE_TLV("3D ADC Volume", WM8737_3D_ENHANCE, 7, 1, 1, adc_tlv),
165
166SOC_SINGLE("Noise Gate Switch", WM8737_NOISE_GATE, 0, 1, 0),
167SOC_SINGLE_TLV("Noise Gate Threshold Volume", WM8737_NOISE_GATE, 2, 7, 0,
168 ng_tlv),
169
170SOC_ENUM("ALC", alc_fn),
171SOC_SINGLE_TLV("ALC Max Gain Volume", WM8737_ALC1, 4, 7, 0, alc_max_tlv),
172SOC_SINGLE_TLV("ALC Target Volume", WM8737_ALC1, 0, 15, 0, alc_target_tlv),
173SOC_ENUM("ALC Hold Time", alc_hold),
174SOC_SINGLE("ALC ZC Switch", WM8737_ALC2, 4, 1, 0),
175SOC_ENUM("ALC Attack Time", alc_atk),
176SOC_ENUM("ALC Decay Time", alc_dcy),
177};
178
179static const char *linsel_text[] = {
180 "LINPUT1", "LINPUT2", "LINPUT3", "LINPUT1 DC",
181};
182
183static const struct soc_enum linsel_enum =
184 SOC_ENUM_SINGLE(WM8737_AUDIO_PATH_L, 7, 4, linsel_text);
185
186static const struct snd_kcontrol_new linsel_mux =
187 SOC_DAPM_ENUM("LINSEL", linsel_enum);
188
189
190static const char *rinsel_text[] = {
191 "RINPUT1", "RINPUT2", "RINPUT3", "RINPUT1 DC",
192};
193
194static const struct soc_enum rinsel_enum =
195 SOC_ENUM_SINGLE(WM8737_AUDIO_PATH_R, 7, 4, rinsel_text);
196
197static const struct snd_kcontrol_new rinsel_mux =
198 SOC_DAPM_ENUM("RINSEL", rinsel_enum);
199
200static const char *bypass_text[] = {
201 "Direct", "Preamp"
202};
203
204static const struct soc_enum lbypass_enum =
205 SOC_ENUM_SINGLE(WM8737_MIC_PREAMP_CONTROL, 2, 2, bypass_text);
206
207static const struct snd_kcontrol_new lbypass_mux =
208 SOC_DAPM_ENUM("Left Bypass", lbypass_enum);
209
210
211static const struct soc_enum rbypass_enum =
212 SOC_ENUM_SINGLE(WM8737_MIC_PREAMP_CONTROL, 3, 2, bypass_text);
213
214static const struct snd_kcontrol_new rbypass_mux =
215 SOC_DAPM_ENUM("Left Bypass", rbypass_enum);
216
217static const struct snd_soc_dapm_widget wm8737_dapm_widgets[] = {
218SND_SOC_DAPM_INPUT("LINPUT1"),
219SND_SOC_DAPM_INPUT("LINPUT2"),
220SND_SOC_DAPM_INPUT("LINPUT3"),
221SND_SOC_DAPM_INPUT("RINPUT1"),
222SND_SOC_DAPM_INPUT("RINPUT2"),
223SND_SOC_DAPM_INPUT("RINPUT3"),
224SND_SOC_DAPM_INPUT("LACIN"),
225SND_SOC_DAPM_INPUT("RACIN"),
226
227SND_SOC_DAPM_MUX("LINSEL", SND_SOC_NOPM, 0, 0, &linsel_mux),
228SND_SOC_DAPM_MUX("RINSEL", SND_SOC_NOPM, 0, 0, &rinsel_mux),
229
230SND_SOC_DAPM_MUX("Left Preamp Mux", SND_SOC_NOPM, 0, 0, &lbypass_mux),
231SND_SOC_DAPM_MUX("Right Preamp Mux", SND_SOC_NOPM, 0, 0, &rbypass_mux),
232
233SND_SOC_DAPM_PGA("PGAL", WM8737_POWER_MANAGEMENT, 5, 0, NULL, 0),
234SND_SOC_DAPM_PGA("PGAR", WM8737_POWER_MANAGEMENT, 4, 0, NULL, 0),
235
236SND_SOC_DAPM_DAC("ADCL", NULL, WM8737_POWER_MANAGEMENT, 3, 0),
237SND_SOC_DAPM_DAC("ADCR", NULL, WM8737_POWER_MANAGEMENT, 2, 0),
238
239SND_SOC_DAPM_AIF_OUT("AIF", "Capture", 0, WM8737_POWER_MANAGEMENT, 6, 0),
240};
241
242static const struct snd_soc_dapm_route intercon[] = {
243 { "LINSEL", "LINPUT1", "LINPUT1" },
244 { "LINSEL", "LINPUT2", "LINPUT2" },
245 { "LINSEL", "LINPUT3", "LINPUT3" },
246 { "LINSEL", "LINPUT1 DC", "LINPUT1" },
247
248 { "RINSEL", "RINPUT1", "RINPUT1" },
249 { "RINSEL", "RINPUT2", "RINPUT2" },
250 { "RINSEL", "RINPUT3", "RINPUT3" },
251 { "RINSEL", "RINPUT1 DC", "RINPUT1" },
252
253 { "Left Preamp Mux", "Preamp", "LINSEL" },
254 { "Left Preamp Mux", "Direct", "LACIN" },
255
256 { "Right Preamp Mux", "Preamp", "RINSEL" },
257 { "Right Preamp Mux", "Direct", "RACIN" },
258
259 { "PGAL", NULL, "Left Preamp Mux" },
260 { "PGAR", NULL, "Right Preamp Mux" },
261
262 { "ADCL", NULL, "PGAL" },
263 { "ADCR", NULL, "PGAR" },
264
265 { "AIF", NULL, "ADCL" },
266 { "AIF", NULL, "ADCR" },
267};
268
269static int wm8737_add_widgets(struct snd_soc_codec *codec)
270{
271 struct snd_soc_dapm_context *dapm = &codec->dapm;
272
273 snd_soc_dapm_new_controls(dapm, wm8737_dapm_widgets,
274 ARRAY_SIZE(wm8737_dapm_widgets));
275 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
276
277 return 0;
278}
279
280/* codec mclk clock divider coefficients */
281static const struct {
282 u32 mclk;
283 u32 rate;
284 u8 usb;
285 u8 sr;
286} coeff_div[] = {
287 { 12288000, 8000, 0, 0x4 },
288 { 12288000, 12000, 0, 0x8 },
289 { 12288000, 16000, 0, 0xa },
290 { 12288000, 24000, 0, 0x1c },
291 { 12288000, 32000, 0, 0xc },
292 { 12288000, 48000, 0, 0 },
293 { 12288000, 96000, 0, 0xe },
294
295 { 11289600, 8000, 0, 0x14 },
296 { 11289600, 11025, 0, 0x18 },
297 { 11289600, 22050, 0, 0x1a },
298 { 11289600, 44100, 0, 0x10 },
299 { 11289600, 88200, 0, 0x1e },
300
301 { 18432000, 8000, 0, 0x5 },
302 { 18432000, 12000, 0, 0x9 },
303 { 18432000, 16000, 0, 0xb },
304 { 18432000, 24000, 0, 0x1b },
305 { 18432000, 32000, 0, 0xd },
306 { 18432000, 48000, 0, 0x1 },
307 { 18432000, 96000, 0, 0x1f },
308
309 { 16934400, 8000, 0, 0x15 },
310 { 16934400, 11025, 0, 0x19 },
311 { 16934400, 22050, 0, 0x1b },
312 { 16934400, 44100, 0, 0x11 },
313 { 16934400, 88200, 0, 0x1f },
314
315 { 12000000, 8000, 1, 0x4 },
316 { 12000000, 11025, 1, 0x19 },
317 { 12000000, 12000, 1, 0x8 },
318 { 12000000, 16000, 1, 0xa },
319 { 12000000, 22050, 1, 0x1b },
320 { 12000000, 24000, 1, 0x1c },
321 { 12000000, 32000, 1, 0xc },
322 { 12000000, 44100, 1, 0x11 },
323 { 12000000, 48000, 1, 0x0 },
324 { 12000000, 88200, 1, 0x1f },
325 { 12000000, 96000, 1, 0xe },
326};
327
328static int wm8737_hw_params(struct snd_pcm_substream *substream,
329 struct snd_pcm_hw_params *params,
330 struct snd_soc_dai *dai)
331{
332 struct snd_soc_pcm_runtime *rtd = substream->private_data;
333 struct snd_soc_codec *codec = rtd->codec;
334 struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec);
335 int i;
336 u16 clocking = 0;
337 u16 af = 0;
338
339 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
340 if (coeff_div[i].rate != params_rate(params))
341 continue;
342
343 if (coeff_div[i].mclk == wm8737->mclk)
344 break;
345
346 if (coeff_div[i].mclk == wm8737->mclk * 2) {
347 clocking |= WM8737_CLKDIV2;
348 break;
349 }
350 }
351
352 if (i == ARRAY_SIZE(coeff_div)) {
353 dev_err(codec->dev, "%dHz MCLK can't support %dHz\n",
354 wm8737->mclk, params_rate(params));
355 return -EINVAL;
356 }
357
358 clocking |= coeff_div[i].usb | (coeff_div[i].sr << WM8737_SR_SHIFT);
359
360 switch (params_format(params)) {
361 case SNDRV_PCM_FORMAT_S16_LE:
362 break;
363 case SNDRV_PCM_FORMAT_S20_3LE:
364 af |= 0x8;
365 break;
366 case SNDRV_PCM_FORMAT_S24_LE:
367 af |= 0x10;
368 break;
369 case SNDRV_PCM_FORMAT_S32_LE:
370 af |= 0x18;
371 break;
372 default:
373 return -EINVAL;
374 }
375
376 snd_soc_update_bits(codec, WM8737_AUDIO_FORMAT, WM8737_WL_MASK, af);
377 snd_soc_update_bits(codec, WM8737_CLOCKING,
378 WM8737_USB_MODE | WM8737_CLKDIV2 | WM8737_SR_MASK,
379 clocking);
380
381 return 0;
382}
383
384static int wm8737_set_dai_sysclk(struct snd_soc_dai *codec_dai,
385 int clk_id, unsigned int freq, int dir)
386{
387 struct snd_soc_codec *codec = codec_dai->codec;
388 struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec);
389 int i;
390
391 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
392 if (freq == coeff_div[i].mclk ||
393 freq == coeff_div[i].mclk * 2) {
394 wm8737->mclk = freq;
395 return 0;
396 }
397 }
398
399 dev_err(codec->dev, "MCLK rate %dHz not supported\n", freq);
400
401 return -EINVAL;
402}
403
404
405static int wm8737_set_dai_fmt(struct snd_soc_dai *codec_dai,
406 unsigned int fmt)
407{
408 struct snd_soc_codec *codec = codec_dai->codec;
409 u16 af = 0;
410
411 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
412 case SND_SOC_DAIFMT_CBM_CFM:
413 af |= WM8737_MS;
414 break;
415 case SND_SOC_DAIFMT_CBS_CFS:
416 break;
417 default:
418 return -EINVAL;
419 }
420
421 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
422 case SND_SOC_DAIFMT_I2S:
423 af |= 0x2;
424 break;
425 case SND_SOC_DAIFMT_RIGHT_J:
426 break;
427 case SND_SOC_DAIFMT_LEFT_J:
428 af |= 0x1;
429 break;
430 case SND_SOC_DAIFMT_DSP_A:
431 af |= 0x3;
432 break;
433 case SND_SOC_DAIFMT_DSP_B:
434 af |= 0x13;
435 break;
436 default:
437 return -EINVAL;
438 }
439
440 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
441 case SND_SOC_DAIFMT_NB_NF:
442 break;
443 case SND_SOC_DAIFMT_NB_IF:
444 af |= WM8737_LRP;
445 break;
446 default:
447 return -EINVAL;
448 }
449
450 snd_soc_update_bits(codec, WM8737_AUDIO_FORMAT,
451 WM8737_FORMAT_MASK | WM8737_LRP | WM8737_MS, af);
452
453 return 0;
454}
455
456static int wm8737_set_bias_level(struct snd_soc_codec *codec,
457 enum snd_soc_bias_level level)
458{
459 struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec);
460 int ret;
461
462 switch (level) {
463 case SND_SOC_BIAS_ON:
464 break;
465
466 case SND_SOC_BIAS_PREPARE:
467 /* VMID at 2*75k */
468 snd_soc_update_bits(codec, WM8737_MISC_BIAS_CONTROL,
469 WM8737_VMIDSEL_MASK, 0);
470 break;
471
472 case SND_SOC_BIAS_STANDBY:
473 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
474 ret = regulator_bulk_enable(ARRAY_SIZE(wm8737->supplies),
475 wm8737->supplies);
476 if (ret != 0) {
477 dev_err(codec->dev,
478 "Failed to enable supplies: %d\n",
479 ret);
480 return ret;
481 }
482
483 snd_soc_cache_sync(codec);
484
485 /* Fast VMID ramp at 2*2.5k */
486 snd_soc_update_bits(codec, WM8737_MISC_BIAS_CONTROL,
487 WM8737_VMIDSEL_MASK, 0x4);
488
489 /* Bring VMID up */
490 snd_soc_update_bits(codec, WM8737_POWER_MANAGEMENT,
491 WM8737_VMID_MASK |
492 WM8737_VREF_MASK,
493 WM8737_VMID_MASK |
494 WM8737_VREF_MASK);
495
496 msleep(500);
497 }
498
499 /* VMID at 2*300k */
500 snd_soc_update_bits(codec, WM8737_MISC_BIAS_CONTROL,
501 WM8737_VMIDSEL_MASK, 2);
502
503 break;
504
505 case SND_SOC_BIAS_OFF:
506 snd_soc_update_bits(codec, WM8737_POWER_MANAGEMENT,
507 WM8737_VMID_MASK | WM8737_VREF_MASK, 0);
508
509 regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies),
510 wm8737->supplies);
511 break;
512 }
513
514 codec->dapm.bias_level = level;
515 return 0;
516}
517
518#define WM8737_RATES SNDRV_PCM_RATE_8000_96000
519
520#define WM8737_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
521 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
522
523static struct snd_soc_dai_ops wm8737_dai_ops = {
524 .hw_params = wm8737_hw_params,
525 .set_sysclk = wm8737_set_dai_sysclk,
526 .set_fmt = wm8737_set_dai_fmt,
527};
528
529static struct snd_soc_dai_driver wm8737_dai = {
530 .name = "wm8737",
531 .capture = {
532 .stream_name = "Capture",
533 .channels_min = 2, /* Mono modes not yet supported */
534 .channels_max = 2,
535 .rates = WM8737_RATES,
536 .formats = WM8737_FORMATS,
537 },
538 .ops = &wm8737_dai_ops,
539};
540
541#ifdef CONFIG_PM
542static int wm8737_suspend(struct snd_soc_codec *codec, pm_message_t state)
543{
544 wm8737_set_bias_level(codec, SND_SOC_BIAS_OFF);
545 return 0;
546}
547
548static int wm8737_resume(struct snd_soc_codec *codec)
549{
550 wm8737_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
551 return 0;
552}
553#else
554#define wm8737_suspend NULL
555#define wm8737_resume NULL
556#endif
557
558static int wm8737_probe(struct snd_soc_codec *codec)
559{
560 struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec);
561 int ret, i;
562
563 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8737->control_type);
564 if (ret != 0) {
565 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
566 return ret;
567 }
568
569 for (i = 0; i < ARRAY_SIZE(wm8737->supplies); i++)
570 wm8737->supplies[i].supply = wm8737_supply_names[i];
571
572 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8737->supplies),
573 wm8737->supplies);
574 if (ret != 0) {
575 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
576 return ret;
577 }
578
579 ret = regulator_bulk_enable(ARRAY_SIZE(wm8737->supplies),
580 wm8737->supplies);
581 if (ret != 0) {
582 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
583 goto err_get;
584 }
585
586 ret = wm8737_reset(codec);
587 if (ret < 0) {
588 dev_err(codec->dev, "Failed to issue reset\n");
589 goto err_enable;
590 }
591
592 snd_soc_update_bits(codec, WM8737_LEFT_PGA_VOLUME, WM8737_LVU,
593 WM8737_LVU);
594 snd_soc_update_bits(codec, WM8737_RIGHT_PGA_VOLUME, WM8737_RVU,
595 WM8737_RVU);
596
597 wm8737_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
598
599 /* Bias level configuration will have done an extra enable */
600 regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);
601
602 snd_soc_add_controls(codec, wm8737_snd_controls,
603 ARRAY_SIZE(wm8737_snd_controls));
604 wm8737_add_widgets(codec);
605
606 return 0;
607
608err_enable:
609 regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);
610err_get:
611 regulator_bulk_free(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);
612
613 return ret;
614}
615
616static int wm8737_remove(struct snd_soc_codec *codec)
617{
618 struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec);
619
620 wm8737_set_bias_level(codec, SND_SOC_BIAS_OFF);
621 regulator_bulk_free(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);
622 return 0;
623}
624
625static struct snd_soc_codec_driver soc_codec_dev_wm8737 = {
626 .probe = wm8737_probe,
627 .remove = wm8737_remove,
628 .suspend = wm8737_suspend,
629 .resume = wm8737_resume,
630 .set_bias_level = wm8737_set_bias_level,
631
632 .reg_cache_size = WM8737_REGISTER_COUNT - 1, /* Skip reset */
633 .reg_word_size = sizeof(u16),
634 .reg_cache_default = wm8737_reg,
635};
636
637#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
638static __devinit int wm8737_i2c_probe(struct i2c_client *i2c,
639 const struct i2c_device_id *id)
640{
641 struct wm8737_priv *wm8737;
642 int ret;
643
644 wm8737 = kzalloc(sizeof(struct wm8737_priv), GFP_KERNEL);
645 if (wm8737 == NULL)
646 return -ENOMEM;
647
648 i2c_set_clientdata(i2c, wm8737);
649 wm8737->control_type = SND_SOC_I2C;
650
651 ret = snd_soc_register_codec(&i2c->dev,
652 &soc_codec_dev_wm8737, &wm8737_dai, 1);
653 if (ret < 0)
654 kfree(wm8737);
655 return ret;
656
657}
658
659static __devexit int wm8737_i2c_remove(struct i2c_client *client)
660{
661 snd_soc_unregister_codec(&client->dev);
662 kfree(i2c_get_clientdata(client));
663 return 0;
664}
665
666static const struct i2c_device_id wm8737_i2c_id[] = {
667 { "wm8737", 0 },
668 { }
669};
670MODULE_DEVICE_TABLE(i2c, wm8737_i2c_id);
671
672static struct i2c_driver wm8737_i2c_driver = {
673 .driver = {
674 .name = "wm8737",
675 .owner = THIS_MODULE,
676 },
677 .probe = wm8737_i2c_probe,
678 .remove = __devexit_p(wm8737_i2c_remove),
679 .id_table = wm8737_i2c_id,
680};
681#endif
682
683#if defined(CONFIG_SPI_MASTER)
684static int __devinit wm8737_spi_probe(struct spi_device *spi)
685{
686 struct wm8737_priv *wm8737;
687 int ret;
688
689 wm8737 = kzalloc(sizeof(struct wm8737_priv), GFP_KERNEL);
690 if (wm8737 == NULL)
691 return -ENOMEM;
692
693 wm8737->control_type = SND_SOC_SPI;
694 spi_set_drvdata(spi, wm8737);
695
696 ret = snd_soc_register_codec(&spi->dev,
697 &soc_codec_dev_wm8737, &wm8737_dai, 1);
698 if (ret < 0)
699 kfree(wm8737);
700 return ret;
701}
702
703static int __devexit wm8737_spi_remove(struct spi_device *spi)
704{
705 snd_soc_unregister_codec(&spi->dev);
706 kfree(spi_get_drvdata(spi));
707 return 0;
708}
709
710static struct spi_driver wm8737_spi_driver = {
711 .driver = {
712 .name = "wm8737",
713 .owner = THIS_MODULE,
714 },
715 .probe = wm8737_spi_probe,
716 .remove = __devexit_p(wm8737_spi_remove),
717};
718#endif /* CONFIG_SPI_MASTER */
719
720static int __init wm8737_modinit(void)
721{
722 int ret;
723#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
724 ret = i2c_add_driver(&wm8737_i2c_driver);
725 if (ret != 0) {
726 printk(KERN_ERR "Failed to register WM8737 I2C driver: %d\n",
727 ret);
728 }
729#endif
730#if defined(CONFIG_SPI_MASTER)
731 ret = spi_register_driver(&wm8737_spi_driver);
732 if (ret != 0) {
733 printk(KERN_ERR "Failed to register WM8737 SPI driver: %d\n",
734 ret);
735 }
736#endif
737 return 0;
738}
739module_init(wm8737_modinit);
740
741static void __exit wm8737_exit(void)
742{
743#if defined(CONFIG_SPI_MASTER)
744 spi_unregister_driver(&wm8737_spi_driver);
745#endif
746#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
747 i2c_del_driver(&wm8737_i2c_driver);
748#endif
749}
750module_exit(wm8737_exit);
751
752MODULE_DESCRIPTION("ASoC WM8737 driver");
753MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
754MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8737.h b/sound/soc/codecs/wm8737.h
new file mode 100644
index 000000000000..23d14c8ff6e7
--- /dev/null
+++ b/sound/soc/codecs/wm8737.h
@@ -0,0 +1,322 @@
1#ifndef _WM8737_H
2#define _WM8737_H
3
4/*
5 * wm8737.c -- WM8523 ALSA SoC Audio driver
6 *
7 * Copyright 2010 Wolfson Microelectronics plc
8 *
9 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16/*
17 * Register values.
18 */
19#define WM8737_LEFT_PGA_VOLUME 0x00
20#define WM8737_RIGHT_PGA_VOLUME 0x01
21#define WM8737_AUDIO_PATH_L 0x02
22#define WM8737_AUDIO_PATH_R 0x03
23#define WM8737_3D_ENHANCE 0x04
24#define WM8737_ADC_CONTROL 0x05
25#define WM8737_POWER_MANAGEMENT 0x06
26#define WM8737_AUDIO_FORMAT 0x07
27#define WM8737_CLOCKING 0x08
28#define WM8737_MIC_PREAMP_CONTROL 0x09
29#define WM8737_MISC_BIAS_CONTROL 0x0A
30#define WM8737_NOISE_GATE 0x0B
31#define WM8737_ALC1 0x0C
32#define WM8737_ALC2 0x0D
33#define WM8737_ALC3 0x0E
34#define WM8737_RESET 0x0F
35
36#define WM8737_REGISTER_COUNT 16
37#define WM8737_MAX_REGISTER 0x0F
38
39/*
40 * Field Definitions.
41 */
42
43/*
44 * R0 (0x00) - Left PGA volume
45 */
46#define WM8737_LVU 0x0100 /* LVU */
47#define WM8737_LVU_MASK 0x0100 /* LVU */
48#define WM8737_LVU_SHIFT 8 /* LVU */
49#define WM8737_LVU_WIDTH 1 /* LVU */
50#define WM8737_LINVOL_MASK 0x00FF /* LINVOL - [7:0] */
51#define WM8737_LINVOL_SHIFT 0 /* LINVOL - [7:0] */
52#define WM8737_LINVOL_WIDTH 8 /* LINVOL - [7:0] */
53
54/*
55 * R1 (0x01) - Right PGA volume
56 */
57#define WM8737_RVU 0x0100 /* RVU */
58#define WM8737_RVU_MASK 0x0100 /* RVU */
59#define WM8737_RVU_SHIFT 8 /* RVU */
60#define WM8737_RVU_WIDTH 1 /* RVU */
61#define WM8737_RINVOL_MASK 0x00FF /* RINVOL - [7:0] */
62#define WM8737_RINVOL_SHIFT 0 /* RINVOL - [7:0] */
63#define WM8737_RINVOL_WIDTH 8 /* RINVOL - [7:0] */
64
65/*
66 * R2 (0x02) - AUDIO path L
67 */
68#define WM8737_LINSEL_MASK 0x0180 /* LINSEL - [8:7] */
69#define WM8737_LINSEL_SHIFT 7 /* LINSEL - [8:7] */
70#define WM8737_LINSEL_WIDTH 2 /* LINSEL - [8:7] */
71#define WM8737_LMICBOOST_MASK 0x0060 /* LMICBOOST - [6:5] */
72#define WM8737_LMICBOOST_SHIFT 5 /* LMICBOOST - [6:5] */
73#define WM8737_LMICBOOST_WIDTH 2 /* LMICBOOST - [6:5] */
74#define WM8737_LMBE 0x0010 /* LMBE */
75#define WM8737_LMBE_MASK 0x0010 /* LMBE */
76#define WM8737_LMBE_SHIFT 4 /* LMBE */
77#define WM8737_LMBE_WIDTH 1 /* LMBE */
78#define WM8737_LMZC 0x0008 /* LMZC */
79#define WM8737_LMZC_MASK 0x0008 /* LMZC */
80#define WM8737_LMZC_SHIFT 3 /* LMZC */
81#define WM8737_LMZC_WIDTH 1 /* LMZC */
82#define WM8737_LPZC 0x0004 /* LPZC */
83#define WM8737_LPZC_MASK 0x0004 /* LPZC */
84#define WM8737_LPZC_SHIFT 2 /* LPZC */
85#define WM8737_LPZC_WIDTH 1 /* LPZC */
86#define WM8737_LZCTO_MASK 0x0003 /* LZCTO - [1:0] */
87#define WM8737_LZCTO_SHIFT 0 /* LZCTO - [1:0] */
88#define WM8737_LZCTO_WIDTH 2 /* LZCTO - [1:0] */
89
90/*
91 * R3 (0x03) - AUDIO path R
92 */
93#define WM8737_RINSEL_MASK 0x0180 /* RINSEL - [8:7] */
94#define WM8737_RINSEL_SHIFT 7 /* RINSEL - [8:7] */
95#define WM8737_RINSEL_WIDTH 2 /* RINSEL - [8:7] */
96#define WM8737_RMICBOOST_MASK 0x0060 /* RMICBOOST - [6:5] */
97#define WM8737_RMICBOOST_SHIFT 5 /* RMICBOOST - [6:5] */
98#define WM8737_RMICBOOST_WIDTH 2 /* RMICBOOST - [6:5] */
99#define WM8737_RMBE 0x0010 /* RMBE */
100#define WM8737_RMBE_MASK 0x0010 /* RMBE */
101#define WM8737_RMBE_SHIFT 4 /* RMBE */
102#define WM8737_RMBE_WIDTH 1 /* RMBE */
103#define WM8737_RMZC 0x0008 /* RMZC */
104#define WM8737_RMZC_MASK 0x0008 /* RMZC */
105#define WM8737_RMZC_SHIFT 3 /* RMZC */
106#define WM8737_RMZC_WIDTH 1 /* RMZC */
107#define WM8737_RPZC 0x0004 /* RPZC */
108#define WM8737_RPZC_MASK 0x0004 /* RPZC */
109#define WM8737_RPZC_SHIFT 2 /* RPZC */
110#define WM8737_RPZC_WIDTH 1 /* RPZC */
111#define WM8737_RZCTO_MASK 0x0003 /* RZCTO - [1:0] */
112#define WM8737_RZCTO_SHIFT 0 /* RZCTO - [1:0] */
113#define WM8737_RZCTO_WIDTH 2 /* RZCTO - [1:0] */
114
115/*
116 * R4 (0x04) - 3D Enhance
117 */
118#define WM8737_DIV2 0x0080 /* DIV2 */
119#define WM8737_DIV2_MASK 0x0080 /* DIV2 */
120#define WM8737_DIV2_SHIFT 7 /* DIV2 */
121#define WM8737_DIV2_WIDTH 1 /* DIV2 */
122#define WM8737_3DLC 0x0040 /* 3DLC */
123#define WM8737_3DLC_MASK 0x0040 /* 3DLC */
124#define WM8737_3DLC_SHIFT 6 /* 3DLC */
125#define WM8737_3DLC_WIDTH 1 /* 3DLC */
126#define WM8737_3DUC 0x0020 /* 3DUC */
127#define WM8737_3DUC_MASK 0x0020 /* 3DUC */
128#define WM8737_3DUC_SHIFT 5 /* 3DUC */
129#define WM8737_3DUC_WIDTH 1 /* 3DUC */
130#define WM8737_3DDEPTH_MASK 0x001E /* 3DDEPTH - [4:1] */
131#define WM8737_3DDEPTH_SHIFT 1 /* 3DDEPTH - [4:1] */
132#define WM8737_3DDEPTH_WIDTH 4 /* 3DDEPTH - [4:1] */
133#define WM8737_3DE 0x0001 /* 3DE */
134#define WM8737_3DE_MASK 0x0001 /* 3DE */
135#define WM8737_3DE_SHIFT 0 /* 3DE */
136#define WM8737_3DE_WIDTH 1 /* 3DE */
137
138/*
139 * R5 (0x05) - ADC Control
140 */
141#define WM8737_MONOMIX_MASK 0x0180 /* MONOMIX - [8:7] */
142#define WM8737_MONOMIX_SHIFT 7 /* MONOMIX - [8:7] */
143#define WM8737_MONOMIX_WIDTH 2 /* MONOMIX - [8:7] */
144#define WM8737_POLARITY_MASK 0x0060 /* POLARITY - [6:5] */
145#define WM8737_POLARITY_SHIFT 5 /* POLARITY - [6:5] */
146#define WM8737_POLARITY_WIDTH 2 /* POLARITY - [6:5] */
147#define WM8737_HPOR 0x0010 /* HPOR */
148#define WM8737_HPOR_MASK 0x0010 /* HPOR */
149#define WM8737_HPOR_SHIFT 4 /* HPOR */
150#define WM8737_HPOR_WIDTH 1 /* HPOR */
151#define WM8737_LP 0x0004 /* LP */
152#define WM8737_LP_MASK 0x0004 /* LP */
153#define WM8737_LP_SHIFT 2 /* LP */
154#define WM8737_LP_WIDTH 1 /* LP */
155#define WM8737_MONOUT 0x0002 /* MONOUT */
156#define WM8737_MONOUT_MASK 0x0002 /* MONOUT */
157#define WM8737_MONOUT_SHIFT 1 /* MONOUT */
158#define WM8737_MONOUT_WIDTH 1 /* MONOUT */
159#define WM8737_ADCHPD 0x0001 /* ADCHPD */
160#define WM8737_ADCHPD_MASK 0x0001 /* ADCHPD */
161#define WM8737_ADCHPD_SHIFT 0 /* ADCHPD */
162#define WM8737_ADCHPD_WIDTH 1 /* ADCHPD */
163
164/*
165 * R6 (0x06) - Power Management
166 */
167#define WM8737_VMID 0x0100 /* VMID */
168#define WM8737_VMID_MASK 0x0100 /* VMID */
169#define WM8737_VMID_SHIFT 8 /* VMID */
170#define WM8737_VMID_WIDTH 1 /* VMID */
171#define WM8737_VREF 0x0080 /* VREF */
172#define WM8737_VREF_MASK 0x0080 /* VREF */
173#define WM8737_VREF_SHIFT 7 /* VREF */
174#define WM8737_VREF_WIDTH 1 /* VREF */
175#define WM8737_AI 0x0040 /* AI */
176#define WM8737_AI_MASK 0x0040 /* AI */
177#define WM8737_AI_SHIFT 6 /* AI */
178#define WM8737_AI_WIDTH 1 /* AI */
179#define WM8737_PGL 0x0020 /* PGL */
180#define WM8737_PGL_MASK 0x0020 /* PGL */
181#define WM8737_PGL_SHIFT 5 /* PGL */
182#define WM8737_PGL_WIDTH 1 /* PGL */
183#define WM8737_PGR 0x0010 /* PGR */
184#define WM8737_PGR_MASK 0x0010 /* PGR */
185#define WM8737_PGR_SHIFT 4 /* PGR */
186#define WM8737_PGR_WIDTH 1 /* PGR */
187#define WM8737_ADL 0x0008 /* ADL */
188#define WM8737_ADL_MASK 0x0008 /* ADL */
189#define WM8737_ADL_SHIFT 3 /* ADL */
190#define WM8737_ADL_WIDTH 1 /* ADL */
191#define WM8737_ADR 0x0004 /* ADR */
192#define WM8737_ADR_MASK 0x0004 /* ADR */
193#define WM8737_ADR_SHIFT 2 /* ADR */
194#define WM8737_ADR_WIDTH 1 /* ADR */
195#define WM8737_MICBIAS_MASK 0x0003 /* MICBIAS - [1:0] */
196#define WM8737_MICBIAS_SHIFT 0 /* MICBIAS - [1:0] */
197#define WM8737_MICBIAS_WIDTH 2 /* MICBIAS - [1:0] */
198
199/*
200 * R7 (0x07) - Audio Format
201 */
202#define WM8737_SDODIS 0x0080 /* SDODIS */
203#define WM8737_SDODIS_MASK 0x0080 /* SDODIS */
204#define WM8737_SDODIS_SHIFT 7 /* SDODIS */
205#define WM8737_SDODIS_WIDTH 1 /* SDODIS */
206#define WM8737_MS 0x0040 /* MS */
207#define WM8737_MS_MASK 0x0040 /* MS */
208#define WM8737_MS_SHIFT 6 /* MS */
209#define WM8737_MS_WIDTH 1 /* MS */
210#define WM8737_LRP 0x0010 /* LRP */
211#define WM8737_LRP_MASK 0x0010 /* LRP */
212#define WM8737_LRP_SHIFT 4 /* LRP */
213#define WM8737_LRP_WIDTH 1 /* LRP */
214#define WM8737_WL_MASK 0x000C /* WL - [3:2] */
215#define WM8737_WL_SHIFT 2 /* WL - [3:2] */
216#define WM8737_WL_WIDTH 2 /* WL - [3:2] */
217#define WM8737_FORMAT_MASK 0x0003 /* FORMAT - [1:0] */
218#define WM8737_FORMAT_SHIFT 0 /* FORMAT - [1:0] */
219#define WM8737_FORMAT_WIDTH 2 /* FORMAT - [1:0] */
220
221/*
222 * R8 (0x08) - Clocking
223 */
224#define WM8737_AUTODETECT 0x0080 /* AUTODETECT */
225#define WM8737_AUTODETECT_MASK 0x0080 /* AUTODETECT */
226#define WM8737_AUTODETECT_SHIFT 7 /* AUTODETECT */
227#define WM8737_AUTODETECT_WIDTH 1 /* AUTODETECT */
228#define WM8737_CLKDIV2 0x0040 /* CLKDIV2 */
229#define WM8737_CLKDIV2_MASK 0x0040 /* CLKDIV2 */
230#define WM8737_CLKDIV2_SHIFT 6 /* CLKDIV2 */
231#define WM8737_CLKDIV2_WIDTH 1 /* CLKDIV2 */
232#define WM8737_SR_MASK 0x003E /* SR - [5:1] */
233#define WM8737_SR_SHIFT 1 /* SR - [5:1] */
234#define WM8737_SR_WIDTH 5 /* SR - [5:1] */
235#define WM8737_USB_MODE 0x0001 /* USB MODE */
236#define WM8737_USB_MODE_MASK 0x0001 /* USB MODE */
237#define WM8737_USB_MODE_SHIFT 0 /* USB MODE */
238#define WM8737_USB_MODE_WIDTH 1 /* USB MODE */
239
240/*
241 * R9 (0x09) - MIC Preamp Control
242 */
243#define WM8737_RBYPEN 0x0008 /* RBYPEN */
244#define WM8737_RBYPEN_MASK 0x0008 /* RBYPEN */
245#define WM8737_RBYPEN_SHIFT 3 /* RBYPEN */
246#define WM8737_RBYPEN_WIDTH 1 /* RBYPEN */
247#define WM8737_LBYPEN 0x0004 /* LBYPEN */
248#define WM8737_LBYPEN_MASK 0x0004 /* LBYPEN */
249#define WM8737_LBYPEN_SHIFT 2 /* LBYPEN */
250#define WM8737_LBYPEN_WIDTH 1 /* LBYPEN */
251#define WM8737_MBCTRL_MASK 0x0003 /* MBCTRL - [1:0] */
252#define WM8737_MBCTRL_SHIFT 0 /* MBCTRL - [1:0] */
253#define WM8737_MBCTRL_WIDTH 2 /* MBCTRL - [1:0] */
254
255/*
256 * R10 (0x0A) - Misc Bias Control
257 */
258#define WM8737_VMIDSEL_MASK 0x000C /* VMIDSEL - [3:2] */
259#define WM8737_VMIDSEL_SHIFT 2 /* VMIDSEL - [3:2] */
260#define WM8737_VMIDSEL_WIDTH 2 /* VMIDSEL - [3:2] */
261#define WM8737_LINPUT1_DC_BIAS_ENABLE 0x0002 /* LINPUT1 DC BIAS ENABLE */
262#define WM8737_LINPUT1_DC_BIAS_ENABLE_MASK 0x0002 /* LINPUT1 DC BIAS ENABLE */
263#define WM8737_LINPUT1_DC_BIAS_ENABLE_SHIFT 1 /* LINPUT1 DC BIAS ENABLE */
264#define WM8737_LINPUT1_DC_BIAS_ENABLE_WIDTH 1 /* LINPUT1 DC BIAS ENABLE */
265#define WM8737_RINPUT1_DC_BIAS_ENABLE 0x0001 /* RINPUT1 DC BIAS ENABLE */
266#define WM8737_RINPUT1_DC_BIAS_ENABLE_MASK 0x0001 /* RINPUT1 DC BIAS ENABLE */
267#define WM8737_RINPUT1_DC_BIAS_ENABLE_SHIFT 0 /* RINPUT1 DC BIAS ENABLE */
268#define WM8737_RINPUT1_DC_BIAS_ENABLE_WIDTH 1 /* RINPUT1 DC BIAS ENABLE */
269
270/*
271 * R11 (0x0B) - Noise Gate
272 */
273#define WM8737_NGTH_MASK 0x001C /* NGTH - [4:2] */
274#define WM8737_NGTH_SHIFT 2 /* NGTH - [4:2] */
275#define WM8737_NGTH_WIDTH 3 /* NGTH - [4:2] */
276#define WM8737_NGAT 0x0001 /* NGAT */
277#define WM8737_NGAT_MASK 0x0001 /* NGAT */
278#define WM8737_NGAT_SHIFT 0 /* NGAT */
279#define WM8737_NGAT_WIDTH 1 /* NGAT */
280
281/*
282 * R12 (0x0C) - ALC1
283 */
284#define WM8737_ALCSEL_MASK 0x0180 /* ALCSEL - [8:7] */
285#define WM8737_ALCSEL_SHIFT 7 /* ALCSEL - [8:7] */
286#define WM8737_ALCSEL_WIDTH 2 /* ALCSEL - [8:7] */
287#define WM8737_MAX_GAIN_MASK 0x0070 /* MAX GAIN - [6:4] */
288#define WM8737_MAX_GAIN_SHIFT 4 /* MAX GAIN - [6:4] */
289#define WM8737_MAX_GAIN_WIDTH 3 /* MAX GAIN - [6:4] */
290#define WM8737_ALCL_MASK 0x000F /* ALCL - [3:0] */
291#define WM8737_ALCL_SHIFT 0 /* ALCL - [3:0] */
292#define WM8737_ALCL_WIDTH 4 /* ALCL - [3:0] */
293
294/*
295 * R13 (0x0D) - ALC2
296 */
297#define WM8737_ALCZCE 0x0010 /* ALCZCE */
298#define WM8737_ALCZCE_MASK 0x0010 /* ALCZCE */
299#define WM8737_ALCZCE_SHIFT 4 /* ALCZCE */
300#define WM8737_ALCZCE_WIDTH 1 /* ALCZCE */
301#define WM8737_HLD_MASK 0x000F /* HLD - [3:0] */
302#define WM8737_HLD_SHIFT 0 /* HLD - [3:0] */
303#define WM8737_HLD_WIDTH 4 /* HLD - [3:0] */
304
305/*
306 * R14 (0x0E) - ALC3
307 */
308#define WM8737_DCY_MASK 0x00F0 /* DCY - [7:4] */
309#define WM8737_DCY_SHIFT 4 /* DCY - [7:4] */
310#define WM8737_DCY_WIDTH 4 /* DCY - [7:4] */
311#define WM8737_ATK_MASK 0x000F /* ATK - [3:0] */
312#define WM8737_ATK_SHIFT 0 /* ATK - [3:0] */
313#define WM8737_ATK_WIDTH 4 /* ATK - [3:0] */
314
315/*
316 * R15 (0x0F) - Reset
317 */
318#define WM8737_RESET_MASK 0x01FF /* RESET - [8:0] */
319#define WM8737_RESET_SHIFT 0 /* RESET - [8:0] */
320#define WM8737_RESET_WIDTH 9 /* RESET - [8:0] */
321
322#endif
diff --git a/sound/soc/codecs/wm8741.c b/sound/soc/codecs/wm8741.c
index aea60ef8aba7..494f2d31d75b 100644
--- a/sound/soc/codecs/wm8741.c
+++ b/sound/soc/codecs/wm8741.c
@@ -24,7 +24,6 @@
24#include <sound/pcm.h> 24#include <sound/pcm.h>
25#include <sound/pcm_params.h> 25#include <sound/pcm_params.h>
26#include <sound/soc.h> 26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h> 27#include <sound/initval.h>
29#include <sound/tlv.h> 28#include <sound/tlv.h>
30 29
@@ -94,10 +93,11 @@ static const struct snd_soc_dapm_route intercon[] = {
94 93
95static int wm8741_add_widgets(struct snd_soc_codec *codec) 94static int wm8741_add_widgets(struct snd_soc_codec *codec)
96{ 95{
97 snd_soc_dapm_new_controls(codec, wm8741_dapm_widgets, 96 struct snd_soc_dapm_context *dapm = &codec->dapm;
98 ARRAY_SIZE(wm8741_dapm_widgets));
99 97
100 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 98 snd_soc_dapm_new_controls(dapm, wm8741_dapm_widgets,
99 ARRAY_SIZE(wm8741_dapm_widgets));
100 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
101 101
102 return 0; 102 return 0;
103} 103}
@@ -455,7 +455,7 @@ static struct snd_soc_codec_driver soc_codec_dev_wm8741 = {
455 .resume = wm8741_resume, 455 .resume = wm8741_resume,
456 .reg_cache_size = ARRAY_SIZE(wm8741_reg_defaults), 456 .reg_cache_size = ARRAY_SIZE(wm8741_reg_defaults),
457 .reg_word_size = sizeof(u16), 457 .reg_word_size = sizeof(u16),
458 .reg_cache_default = &wm8741_reg_defaults, 458 .reg_cache_default = wm8741_reg_defaults,
459}; 459};
460 460
461#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 461#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
diff --git a/sound/soc/codecs/wm8750.c b/sound/soc/codecs/wm8750.c
index 6c924cd2cfd4..38f38fddd190 100644
--- a/sound/soc/codecs/wm8750.c
+++ b/sound/soc/codecs/wm8750.c
@@ -25,7 +25,6 @@
25#include <sound/pcm.h> 25#include <sound/pcm.h>
26#include <sound/pcm_params.h> 26#include <sound/pcm_params.h>
27#include <sound/soc.h> 27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h> 28#include <sound/initval.h>
30 29
31#include "wm8750.h" 30#include "wm8750.h"
@@ -53,7 +52,6 @@ static const u16 wm8750_reg[] = {
53struct wm8750_priv { 52struct wm8750_priv {
54 unsigned int sysclk; 53 unsigned int sysclk;
55 enum snd_soc_control_type control_type; 54 enum snd_soc_control_type control_type;
56 u16 reg_cache[ARRAY_SIZE(wm8750_reg)];
57}; 55};
58 56
59#define wm8750_reset(c) snd_soc_write(c, WM8750_RESET, 0) 57#define wm8750_reset(c) snd_soc_write(c, WM8750_RESET, 0)
@@ -399,10 +397,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
399 397
400static int wm8750_add_widgets(struct snd_soc_codec *codec) 398static int wm8750_add_widgets(struct snd_soc_codec *codec)
401{ 399{
402 snd_soc_dapm_new_controls(codec, wm8750_dapm_widgets, 400 struct snd_soc_dapm_context *dapm = &codec->dapm;
403 ARRAY_SIZE(wm8750_dapm_widgets));
404 401
405 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 402 snd_soc_dapm_new_controls(dapm, wm8750_dapm_widgets,
403 ARRAY_SIZE(wm8750_dapm_widgets));
404 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
406 405
407 return 0; 406 return 0;
408} 407}
@@ -615,7 +614,7 @@ static int wm8750_set_bias_level(struct snd_soc_codec *codec,
615 case SND_SOC_BIAS_PREPARE: 614 case SND_SOC_BIAS_PREPARE:
616 break; 615 break;
617 case SND_SOC_BIAS_STANDBY: 616 case SND_SOC_BIAS_STANDBY:
618 if (codec->bias_level == SND_SOC_BIAS_OFF) { 617 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
619 /* Set VMID to 5k */ 618 /* Set VMID to 5k */
620 snd_soc_write(codec, WM8750_PWR1, pwr_reg | 0x01c1); 619 snd_soc_write(codec, WM8750_PWR1, pwr_reg | 0x01c1);
621 620
@@ -630,7 +629,7 @@ static int wm8750_set_bias_level(struct snd_soc_codec *codec,
630 snd_soc_write(codec, WM8750_PWR1, 0x0001); 629 snd_soc_write(codec, WM8750_PWR1, 0x0001);
631 break; 630 break;
632 } 631 }
633 codec->bias_level = level; 632 codec->dapm.bias_level = level;
634 return 0; 633 return 0;
635} 634}
636 635
diff --git a/sound/soc/codecs/wm8753.c b/sound/soc/codecs/wm8753.c
index 87caae59e939..79b02ae125c5 100644
--- a/sound/soc/codecs/wm8753.c
+++ b/sound/soc/codecs/wm8753.c
@@ -45,7 +45,6 @@
45#include <sound/pcm.h> 45#include <sound/pcm.h>
46#include <sound/pcm_params.h> 46#include <sound/pcm_params.h>
47#include <sound/soc.h> 47#include <sound/soc.h>
48#include <sound/soc-dapm.h>
49#include <sound/initval.h> 48#include <sound/initval.h>
50#include <sound/tlv.h> 49#include <sound/tlv.h>
51#include <asm/div64.h> 50#include <asm/div64.h>
@@ -623,10 +622,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
623 622
624static int wm8753_add_widgets(struct snd_soc_codec *codec) 623static int wm8753_add_widgets(struct snd_soc_codec *codec)
625{ 624{
626 snd_soc_dapm_new_controls(codec, wm8753_dapm_widgets, 625 struct snd_soc_dapm_context *dapm = &codec->dapm;
627 ARRAY_SIZE(wm8753_dapm_widgets));
628 626
629 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 627 snd_soc_dapm_new_controls(dapm, wm8753_dapm_widgets,
628 ARRAY_SIZE(wm8753_dapm_widgets));
629 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
630 630
631 return 0; 631 return 0;
632} 632}
@@ -1245,7 +1245,7 @@ static int wm8753_set_bias_level(struct snd_soc_codec *codec,
1245 snd_soc_write(codec, WM8753_PWR1, 0x0001); 1245 snd_soc_write(codec, WM8753_PWR1, 0x0001);
1246 break; 1246 break;
1247 } 1247 }
1248 codec->bias_level = level; 1248 codec->dapm.bias_level = level;
1249 return 0; 1249 return 0;
1250} 1250}
1251 1251
@@ -1435,9 +1435,11 @@ static void wm8753_set_dai_mode(struct snd_soc_codec *codec,
1435 1435
1436static void wm8753_work(struct work_struct *work) 1436static void wm8753_work(struct work_struct *work)
1437{ 1437{
1438 struct snd_soc_codec *codec = 1438 struct snd_soc_dapm_context *dapm =
1439 container_of(work, struct snd_soc_codec, delayed_work.work); 1439 container_of(work, struct snd_soc_dapm_context,
1440 wm8753_set_bias_level(codec, codec->bias_level); 1440 delayed_work.work);
1441 struct snd_soc_codec *codec = dapm->codec;
1442 wm8753_set_bias_level(codec, dapm->bias_level);
1441} 1443}
1442 1444
1443static int wm8753_suspend(struct snd_soc_codec *codec, pm_message_t state) 1445static int wm8753_suspend(struct snd_soc_codec *codec, pm_message_t state)
@@ -1466,41 +1468,22 @@ static int wm8753_resume(struct snd_soc_codec *codec)
1466 wm8753_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1468 wm8753_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1467 1469
1468 /* charge wm8753 caps */ 1470 /* charge wm8753 caps */
1469 if (codec->suspend_bias_level == SND_SOC_BIAS_ON) { 1471 if (codec->dapm.suspend_bias_level == SND_SOC_BIAS_ON) {
1470 wm8753_set_bias_level(codec, SND_SOC_BIAS_PREPARE); 1472 wm8753_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
1471 codec->bias_level = SND_SOC_BIAS_ON; 1473 codec->dapm.bias_level = SND_SOC_BIAS_ON;
1472 schedule_delayed_work(&codec->delayed_work, 1474 schedule_delayed_work(&codec->dapm.delayed_work,
1473 msecs_to_jiffies(caps_charge)); 1475 msecs_to_jiffies(caps_charge));
1474 } 1476 }
1475 1477
1476 return 0; 1478 return 0;
1477} 1479}
1478 1480
1479/*
1480 * This function forces any delayed work to be queued and run.
1481 */
1482static int run_delayed_work(struct delayed_work *dwork)
1483{
1484 int ret;
1485
1486 /* cancel any work waiting to be queued. */
1487 ret = cancel_delayed_work(dwork);
1488
1489 /* if there was any work waiting then we run it now and
1490 * wait for it's completion */
1491 if (ret) {
1492 schedule_delayed_work(dwork, 0);
1493 flush_scheduled_work();
1494 }
1495 return ret;
1496}
1497
1498static int wm8753_probe(struct snd_soc_codec *codec) 1481static int wm8753_probe(struct snd_soc_codec *codec)
1499{ 1482{
1500 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec); 1483 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1501 int ret; 1484 int ret;
1502 1485
1503 INIT_DELAYED_WORK(&codec->delayed_work, wm8753_work); 1486 INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8753_work);
1504 1487
1505 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8753->control_type); 1488 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8753->control_type);
1506 if (ret < 0) { 1489 if (ret < 0) {
@@ -1519,7 +1502,7 @@ static int wm8753_probe(struct snd_soc_codec *codec)
1519 1502
1520 /* charge output caps */ 1503 /* charge output caps */
1521 wm8753_set_bias_level(codec, SND_SOC_BIAS_PREPARE); 1504 wm8753_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
1522 schedule_delayed_work(&codec->delayed_work, 1505 schedule_delayed_work(&codec->dapm.delayed_work,
1523 msecs_to_jiffies(caps_charge)); 1506 msecs_to_jiffies(caps_charge));
1524 1507
1525 /* set the update bits */ 1508 /* set the update bits */
@@ -1544,7 +1527,7 @@ static int wm8753_probe(struct snd_soc_codec *codec)
1544/* power down chip */ 1527/* power down chip */
1545static int wm8753_remove(struct snd_soc_codec *codec) 1528static int wm8753_remove(struct snd_soc_codec *codec)
1546{ 1529{
1547 run_delayed_work(&codec->delayed_work); 1530 flush_delayed_work_sync(&codec->dapm.delayed_work);
1548 wm8753_set_bias_level(codec, SND_SOC_BIAS_OFF); 1531 wm8753_set_bias_level(codec, SND_SOC_BIAS_OFF);
1549 1532
1550 return 0; 1533 return 0;
diff --git a/sound/soc/codecs/wm8770.c b/sound/soc/codecs/wm8770.c
new file mode 100644
index 000000000000..19b92baa9e8c
--- /dev/null
+++ b/sound/soc/codecs/wm8770.c
@@ -0,0 +1,749 @@
1/*
2 * wm8770.c -- WM8770 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
20#include <linux/regulator/consumer.h>
21#include <linux/slab.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/initval.h>
27#include <sound/tlv.h>
28
29#include "wm8770.h"
30
31#define WM8770_NUM_SUPPLIES 3
32static const char *wm8770_supply_names[WM8770_NUM_SUPPLIES] = {
33 "AVDD1",
34 "AVDD2",
35 "DVDD"
36};
37
38static const u16 wm8770_reg_defs[WM8770_CACHEREGNUM] = {
39 0x7f, 0x7f, 0x7f, 0x7f,
40 0x7f, 0x7f, 0x7f, 0x7f,
41 0x7f, 0xff, 0xff, 0xff,
42 0xff, 0xff, 0xff, 0xff,
43 0xff, 0xff, 0, 0x90, 0,
44 0, 0x22, 0x22, 0x3e,
45 0xc, 0xc, 0x100, 0x189,
46 0x189, 0x8770
47};
48
49struct wm8770_priv {
50 enum snd_soc_control_type control_type;
51 struct regulator_bulk_data supplies[WM8770_NUM_SUPPLIES];
52 struct notifier_block disable_nb[WM8770_NUM_SUPPLIES];
53 struct snd_soc_codec *codec;
54 int sysclk;
55};
56
57static int vout12supply_event(struct snd_soc_dapm_widget *w,
58 struct snd_kcontrol *kcontrol, int event);
59static int vout34supply_event(struct snd_soc_dapm_widget *w,
60 struct snd_kcontrol *kcontrol, int event);
61
62/*
63 * We can't use the same notifier block for more than one supply and
64 * there's no way I can see to get from a callback to the caller
65 * except container_of().
66 */
67#define WM8770_REGULATOR_EVENT(n) \
68static int wm8770_regulator_event_##n(struct notifier_block *nb, \
69 unsigned long event, void *data) \
70{ \
71 struct wm8770_priv *wm8770 = container_of(nb, struct wm8770_priv, \
72 disable_nb[n]); \
73 if (event & REGULATOR_EVENT_DISABLE) { \
74 wm8770->codec->cache_sync = 1; \
75 } \
76 return 0; \
77}
78
79WM8770_REGULATOR_EVENT(0)
80WM8770_REGULATOR_EVENT(1)
81WM8770_REGULATOR_EVENT(2)
82
83static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 100, 0);
84static const DECLARE_TLV_DB_SCALE(dac_dig_tlv, -12750, 50, 1);
85static const DECLARE_TLV_DB_SCALE(dac_alg_tlv, -12700, 100, 1);
86
87static const char *dac_phase_text[][2] = {
88 { "DAC1 Normal", "DAC1 Inverted" },
89 { "DAC2 Normal", "DAC2 Inverted" },
90 { "DAC3 Normal", "DAC3 Inverted" },
91 { "DAC4 Normal", "DAC4 Inverted" },
92};
93
94static const struct soc_enum dac_phase[] = {
95 SOC_ENUM_DOUBLE(WM8770_DACPHASE, 0, 1, 2, dac_phase_text[0]),
96 SOC_ENUM_DOUBLE(WM8770_DACPHASE, 2, 3, 2, dac_phase_text[1]),
97 SOC_ENUM_DOUBLE(WM8770_DACPHASE, 4, 5, 2, dac_phase_text[2]),
98 SOC_ENUM_DOUBLE(WM8770_DACPHASE, 6, 7, 2, dac_phase_text[3]),
99};
100
101static const struct snd_kcontrol_new wm8770_snd_controls[] = {
102 /* global DAC playback controls */
103 SOC_SINGLE_TLV("DAC Playback Volume", WM8770_MSDIGVOL, 0, 255, 0,
104 dac_dig_tlv),
105 SOC_SINGLE("DAC Playback Switch", WM8770_DACMUTE, 4, 1, 1),
106 SOC_SINGLE("DAC Playback ZC Switch", WM8770_DACCTRL1, 0, 1, 0),
107
108 /* global VOUT playback controls */
109 SOC_SINGLE_TLV("VOUT Playback Volume", WM8770_MSALGVOL, 0, 127, 0,
110 dac_alg_tlv),
111 SOC_SINGLE("VOUT Playback ZC Switch", WM8770_MSALGVOL, 7, 1, 0),
112
113 /* VOUT1/2/3/4 specific controls */
114 SOC_DOUBLE_R_TLV("VOUT1 Playback Volume", WM8770_VOUT1LVOL,
115 WM8770_VOUT1RVOL, 0, 127, 0, dac_alg_tlv),
116 SOC_DOUBLE_R("VOUT1 Playback ZC Switch", WM8770_VOUT1LVOL,
117 WM8770_VOUT1RVOL, 7, 1, 0),
118 SOC_DOUBLE_R_TLV("VOUT2 Playback Volume", WM8770_VOUT2LVOL,
119 WM8770_VOUT2RVOL, 0, 127, 0, dac_alg_tlv),
120 SOC_DOUBLE_R("VOUT2 Playback ZC Switch", WM8770_VOUT2LVOL,
121 WM8770_VOUT2RVOL, 7, 1, 0),
122 SOC_DOUBLE_R_TLV("VOUT3 Playback Volume", WM8770_VOUT3LVOL,
123 WM8770_VOUT3RVOL, 0, 127, 0, dac_alg_tlv),
124 SOC_DOUBLE_R("VOUT3 Playback ZC Switch", WM8770_VOUT3LVOL,
125 WM8770_VOUT3RVOL, 7, 1, 0),
126 SOC_DOUBLE_R_TLV("VOUT4 Playback Volume", WM8770_VOUT4LVOL,
127 WM8770_VOUT4RVOL, 0, 127, 0, dac_alg_tlv),
128 SOC_DOUBLE_R("VOUT4 Playback ZC Switch", WM8770_VOUT4LVOL,
129 WM8770_VOUT4RVOL, 7, 1, 0),
130
131 /* DAC1/2/3/4 specific controls */
132 SOC_DOUBLE_R_TLV("DAC1 Playback Volume", WM8770_DAC1LVOL,
133 WM8770_DAC1RVOL, 0, 255, 0, dac_dig_tlv),
134 SOC_SINGLE("DAC1 Deemphasis Switch", WM8770_DACCTRL2, 0, 1, 0),
135 SOC_ENUM("DAC1 Phase", dac_phase[0]),
136 SOC_DOUBLE_R_TLV("DAC2 Playback Volume", WM8770_DAC2LVOL,
137 WM8770_DAC2RVOL, 0, 255, 0, dac_dig_tlv),
138 SOC_SINGLE("DAC2 Deemphasis Switch", WM8770_DACCTRL2, 1, 1, 0),
139 SOC_ENUM("DAC2 Phase", dac_phase[1]),
140 SOC_DOUBLE_R_TLV("DAC3 Playback Volume", WM8770_DAC3LVOL,
141 WM8770_DAC3RVOL, 0, 255, 0, dac_dig_tlv),
142 SOC_SINGLE("DAC3 Deemphasis Switch", WM8770_DACCTRL2, 2, 1, 0),
143 SOC_ENUM("DAC3 Phase", dac_phase[2]),
144 SOC_DOUBLE_R_TLV("DAC4 Playback Volume", WM8770_DAC4LVOL,
145 WM8770_DAC4RVOL, 0, 255, 0, dac_dig_tlv),
146 SOC_SINGLE("DAC4 Deemphasis Switch", WM8770_DACCTRL2, 3, 1, 0),
147 SOC_ENUM("DAC4 Phase", dac_phase[3]),
148
149 /* ADC specific controls */
150 SOC_DOUBLE_R_TLV("Capture Volume", WM8770_ADCLCTRL, WM8770_ADCRCTRL,
151 0, 31, 0, adc_tlv),
152 SOC_DOUBLE_R("Capture Switch", WM8770_ADCLCTRL, WM8770_ADCRCTRL,
153 5, 1, 1),
154
155 /* other controls */
156 SOC_SINGLE("ADC 128x Oversampling Switch", WM8770_MSTRCTRL, 3, 1, 0),
157 SOC_SINGLE("ADC Highpass Filter Switch", WM8770_IFACECTRL, 8, 1, 1)
158};
159
160static const char *ain_text[] = {
161 "AIN1", "AIN2", "AIN3", "AIN4",
162 "AIN5", "AIN6", "AIN7", "AIN8"
163};
164
165static const struct soc_enum ain_enum =
166 SOC_ENUM_DOUBLE(WM8770_ADCMUX, 0, 4, 8, ain_text);
167
168static const struct snd_kcontrol_new ain_mux =
169 SOC_DAPM_ENUM("Capture Mux", ain_enum);
170
171static const struct snd_kcontrol_new vout1_mix_controls[] = {
172 SOC_DAPM_SINGLE("DAC1 Switch", WM8770_OUTMUX1, 0, 1, 0),
173 SOC_DAPM_SINGLE("AUX1 Switch", WM8770_OUTMUX1, 1, 1, 0),
174 SOC_DAPM_SINGLE("Bypass Switch", WM8770_OUTMUX1, 2, 1, 0)
175};
176
177static const struct snd_kcontrol_new vout2_mix_controls[] = {
178 SOC_DAPM_SINGLE("DAC2 Switch", WM8770_OUTMUX1, 3, 1, 0),
179 SOC_DAPM_SINGLE("AUX2 Switch", WM8770_OUTMUX1, 4, 1, 0),
180 SOC_DAPM_SINGLE("Bypass Switch", WM8770_OUTMUX1, 5, 1, 0)
181};
182
183static const struct snd_kcontrol_new vout3_mix_controls[] = {
184 SOC_DAPM_SINGLE("DAC3 Switch", WM8770_OUTMUX2, 0, 1, 0),
185 SOC_DAPM_SINGLE("AUX3 Switch", WM8770_OUTMUX2, 1, 1, 0),
186 SOC_DAPM_SINGLE("Bypass Switch", WM8770_OUTMUX2, 2, 1, 0)
187};
188
189static const struct snd_kcontrol_new vout4_mix_controls[] = {
190 SOC_DAPM_SINGLE("DAC4 Switch", WM8770_OUTMUX2, 3, 1, 0),
191 SOC_DAPM_SINGLE("Bypass Switch", WM8770_OUTMUX2, 4, 1, 0)
192};
193
194static const struct snd_soc_dapm_widget wm8770_dapm_widgets[] = {
195 SND_SOC_DAPM_INPUT("AUX1"),
196 SND_SOC_DAPM_INPUT("AUX2"),
197 SND_SOC_DAPM_INPUT("AUX3"),
198
199 SND_SOC_DAPM_INPUT("AIN1"),
200 SND_SOC_DAPM_INPUT("AIN2"),
201 SND_SOC_DAPM_INPUT("AIN3"),
202 SND_SOC_DAPM_INPUT("AIN4"),
203 SND_SOC_DAPM_INPUT("AIN5"),
204 SND_SOC_DAPM_INPUT("AIN6"),
205 SND_SOC_DAPM_INPUT("AIN7"),
206 SND_SOC_DAPM_INPUT("AIN8"),
207
208 SND_SOC_DAPM_MUX("Capture Mux", WM8770_ADCMUX, 8, 1, &ain_mux),
209
210 SND_SOC_DAPM_ADC("ADC", "Capture", WM8770_PWDNCTRL, 1, 1),
211
212 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8770_PWDNCTRL, 2, 1),
213 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8770_PWDNCTRL, 3, 1),
214 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8770_PWDNCTRL, 4, 1),
215 SND_SOC_DAPM_DAC("DAC4", "Playback", WM8770_PWDNCTRL, 5, 1),
216
217 SND_SOC_DAPM_SUPPLY("VOUT12 Supply", SND_SOC_NOPM, 0, 0,
218 vout12supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
219 SND_SOC_DAPM_SUPPLY("VOUT34 Supply", SND_SOC_NOPM, 0, 0,
220 vout34supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
221
222 SND_SOC_DAPM_MIXER("VOUT1 Mixer", SND_SOC_NOPM, 0, 0,
223 vout1_mix_controls, ARRAY_SIZE(vout1_mix_controls)),
224 SND_SOC_DAPM_MIXER("VOUT2 Mixer", SND_SOC_NOPM, 0, 0,
225 vout2_mix_controls, ARRAY_SIZE(vout2_mix_controls)),
226 SND_SOC_DAPM_MIXER("VOUT3 Mixer", SND_SOC_NOPM, 0, 0,
227 vout3_mix_controls, ARRAY_SIZE(vout3_mix_controls)),
228 SND_SOC_DAPM_MIXER("VOUT4 Mixer", SND_SOC_NOPM, 0, 0,
229 vout4_mix_controls, ARRAY_SIZE(vout4_mix_controls)),
230
231 SND_SOC_DAPM_OUTPUT("VOUT1"),
232 SND_SOC_DAPM_OUTPUT("VOUT2"),
233 SND_SOC_DAPM_OUTPUT("VOUT3"),
234 SND_SOC_DAPM_OUTPUT("VOUT4")
235};
236
237static const struct snd_soc_dapm_route wm8770_intercon[] = {
238 { "Capture Mux", "AIN1", "AIN1" },
239 { "Capture Mux", "AIN2", "AIN2" },
240 { "Capture Mux", "AIN3", "AIN3" },
241 { "Capture Mux", "AIN4", "AIN4" },
242 { "Capture Mux", "AIN5", "AIN5" },
243 { "Capture Mux", "AIN6", "AIN6" },
244 { "Capture Mux", "AIN7", "AIN7" },
245 { "Capture Mux", "AIN8", "AIN8" },
246
247 { "ADC", NULL, "Capture Mux" },
248
249 { "VOUT1 Mixer", NULL, "VOUT12 Supply" },
250 { "VOUT1 Mixer", "DAC1 Switch", "DAC1" },
251 { "VOUT1 Mixer", "AUX1 Switch", "AUX1" },
252 { "VOUT1 Mixer", "Bypass Switch", "Capture Mux" },
253
254 { "VOUT2 Mixer", NULL, "VOUT12 Supply" },
255 { "VOUT2 Mixer", "DAC2 Switch", "DAC2" },
256 { "VOUT2 Mixer", "AUX2 Switch", "AUX2" },
257 { "VOUT2 Mixer", "Bypass Switch", "Capture Mux" },
258
259 { "VOUT3 Mixer", NULL, "VOUT34 Supply" },
260 { "VOUT3 Mixer", "DAC3 Switch", "DAC3" },
261 { "VOUT3 Mixer", "AUX3 Switch", "AUX3" },
262 { "VOUT3 Mixer", "Bypass Switch", "Capture Mux" },
263
264 { "VOUT4 Mixer", NULL, "VOUT34 Supply" },
265 { "VOUT4 Mixer", "DAC4 Switch", "DAC4" },
266 { "VOUT4 Mixer", "Bypass Switch", "Capture Mux" },
267
268 { "VOUT1", NULL, "VOUT1 Mixer" },
269 { "VOUT2", NULL, "VOUT2 Mixer" },
270 { "VOUT3", NULL, "VOUT3 Mixer" },
271 { "VOUT4", NULL, "VOUT4 Mixer" }
272};
273
274static int vout12supply_event(struct snd_soc_dapm_widget *w,
275 struct snd_kcontrol *kcontrol, int event)
276{
277 struct snd_soc_codec *codec;
278
279 codec = w->codec;
280
281 switch (event) {
282 case SND_SOC_DAPM_PRE_PMU:
283 snd_soc_update_bits(codec, WM8770_OUTMUX1, 0x180, 0);
284 break;
285 case SND_SOC_DAPM_POST_PMD:
286 snd_soc_update_bits(codec, WM8770_OUTMUX1, 0x180, 0x180);
287 break;
288 }
289
290 return 0;
291}
292
293static int vout34supply_event(struct snd_soc_dapm_widget *w,
294 struct snd_kcontrol *kcontrol, int event)
295{
296 struct snd_soc_codec *codec;
297
298 codec = w->codec;
299
300 switch (event) {
301 case SND_SOC_DAPM_PRE_PMU:
302 snd_soc_update_bits(codec, WM8770_OUTMUX2, 0x180, 0);
303 break;
304 case SND_SOC_DAPM_POST_PMD:
305 snd_soc_update_bits(codec, WM8770_OUTMUX2, 0x180, 0x180);
306 break;
307 }
308
309 return 0;
310}
311
312static int wm8770_reset(struct snd_soc_codec *codec)
313{
314 return snd_soc_write(codec, WM8770_RESET, 0);
315}
316
317static int wm8770_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
318{
319 struct snd_soc_codec *codec;
320 int iface, master;
321
322 codec = dai->codec;
323
324 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
325 case SND_SOC_DAIFMT_CBM_CFM:
326 master = 0x100;
327 break;
328 case SND_SOC_DAIFMT_CBS_CFS:
329 master = 0;
330 break;
331 default:
332 return -EINVAL;
333 }
334
335 iface = 0;
336 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
337 case SND_SOC_DAIFMT_I2S:
338 iface |= 0x2;
339 break;
340 case SND_SOC_DAIFMT_RIGHT_J:
341 break;
342 case SND_SOC_DAIFMT_LEFT_J:
343 iface |= 0x1;
344 break;
345 default:
346 return -EINVAL;
347 }
348
349 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
350 case SND_SOC_DAIFMT_NB_NF:
351 break;
352 case SND_SOC_DAIFMT_IB_IF:
353 iface |= 0xc;
354 break;
355 case SND_SOC_DAIFMT_IB_NF:
356 iface |= 0x8;
357 break;
358 case SND_SOC_DAIFMT_NB_IF:
359 iface |= 0x4;
360 break;
361 default:
362 return -EINVAL;
363 }
364
365 snd_soc_update_bits(codec, WM8770_IFACECTRL, 0xf, iface);
366 snd_soc_update_bits(codec, WM8770_MSTRCTRL, 0x100, master);
367
368 return 0;
369}
370
371static const int mclk_ratios[] = {
372 128,
373 192,
374 256,
375 384,
376 512,
377 768
378};
379
380static int wm8770_hw_params(struct snd_pcm_substream *substream,
381 struct snd_pcm_hw_params *params,
382 struct snd_soc_dai *dai)
383{
384 struct snd_soc_codec *codec;
385 struct wm8770_priv *wm8770;
386 int i;
387 int iface;
388 int shift;
389 int ratio;
390
391 codec = dai->codec;
392 wm8770 = snd_soc_codec_get_drvdata(codec);
393
394 iface = 0;
395 switch (params_format(params)) {
396 case SNDRV_PCM_FORMAT_S16_LE:
397 break;
398 case SNDRV_PCM_FORMAT_S20_3LE:
399 iface |= 0x10;
400 break;
401 case SNDRV_PCM_FORMAT_S24_LE:
402 iface |= 0x20;
403 break;
404 case SNDRV_PCM_FORMAT_S32_LE:
405 iface |= 0x30;
406 break;
407 }
408
409 switch (substream->stream) {
410 case SNDRV_PCM_STREAM_PLAYBACK:
411 i = 0;
412 shift = 4;
413 break;
414 case SNDRV_PCM_STREAM_CAPTURE:
415 i = 2;
416 shift = 0;
417 break;
418 default:
419 return -EINVAL;
420 }
421
422 /* Only need to set MCLK/LRCLK ratio if we're master */
423 if (snd_soc_read(codec, WM8770_MSTRCTRL) & 0x100) {
424 for (; i < ARRAY_SIZE(mclk_ratios); ++i) {
425 ratio = wm8770->sysclk / params_rate(params);
426 if (ratio == mclk_ratios[i])
427 break;
428 }
429
430 if (i == ARRAY_SIZE(mclk_ratios)) {
431 dev_err(codec->dev,
432 "Unable to configure MCLK ratio %d/%d\n",
433 wm8770->sysclk, params_rate(params));
434 return -EINVAL;
435 }
436
437 dev_dbg(codec->dev, "MCLK is %dfs\n", mclk_ratios[i]);
438
439 snd_soc_update_bits(codec, WM8770_MSTRCTRL, 0x7 << shift,
440 i << shift);
441 }
442
443 snd_soc_update_bits(codec, WM8770_IFACECTRL, 0x30, iface);
444
445 return 0;
446}
447
448static int wm8770_mute(struct snd_soc_dai *dai, int mute)
449{
450 struct snd_soc_codec *codec;
451
452 codec = dai->codec;
453 return snd_soc_update_bits(codec, WM8770_DACMUTE, 0x10,
454 !!mute << 4);
455}
456
457static int wm8770_set_sysclk(struct snd_soc_dai *dai,
458 int clk_id, unsigned int freq, int dir)
459{
460 struct snd_soc_codec *codec;
461 struct wm8770_priv *wm8770;
462
463 codec = dai->codec;
464 wm8770 = snd_soc_codec_get_drvdata(codec);
465 wm8770->sysclk = freq;
466 return 0;
467}
468
469static void wm8770_sync_cache(struct snd_soc_codec *codec)
470{
471 int i;
472 u16 *cache;
473
474 if (!codec->cache_sync)
475 return;
476
477 codec->cache_only = 0;
478 cache = codec->reg_cache;
479 for (i = 0; i < codec->driver->reg_cache_size; i++) {
480 if (i == WM8770_RESET || cache[i] == wm8770_reg_defs[i])
481 continue;
482 snd_soc_write(codec, i, cache[i]);
483 }
484 codec->cache_sync = 0;
485}
486
487static int wm8770_set_bias_level(struct snd_soc_codec *codec,
488 enum snd_soc_bias_level level)
489{
490 int ret;
491 struct wm8770_priv *wm8770;
492
493 wm8770 = snd_soc_codec_get_drvdata(codec);
494
495 switch (level) {
496 case SND_SOC_BIAS_ON:
497 break;
498 case SND_SOC_BIAS_PREPARE:
499 break;
500 case SND_SOC_BIAS_STANDBY:
501 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
502 ret = regulator_bulk_enable(ARRAY_SIZE(wm8770->supplies),
503 wm8770->supplies);
504 if (ret) {
505 dev_err(codec->dev,
506 "Failed to enable supplies: %d\n",
507 ret);
508 return ret;
509 }
510 wm8770_sync_cache(codec);
511 /* global powerup */
512 snd_soc_write(codec, WM8770_PWDNCTRL, 0);
513 }
514 break;
515 case SND_SOC_BIAS_OFF:
516 /* global powerdown */
517 snd_soc_write(codec, WM8770_PWDNCTRL, 1);
518 regulator_bulk_disable(ARRAY_SIZE(wm8770->supplies),
519 wm8770->supplies);
520 break;
521 }
522
523 codec->dapm.bias_level = level;
524 return 0;
525}
526
527#define WM8770_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
528 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
529
530static struct snd_soc_dai_ops wm8770_dai_ops = {
531 .digital_mute = wm8770_mute,
532 .hw_params = wm8770_hw_params,
533 .set_fmt = wm8770_set_fmt,
534 .set_sysclk = wm8770_set_sysclk,
535};
536
537static struct snd_soc_dai_driver wm8770_dai = {
538 .name = "wm8770-hifi",
539 .playback = {
540 .stream_name = "Playback",
541 .channels_min = 2,
542 .channels_max = 2,
543 .rates = SNDRV_PCM_RATE_8000_192000,
544 .formats = WM8770_FORMATS
545 },
546 .capture = {
547 .stream_name = "Capture",
548 .channels_min = 2,
549 .channels_max = 2,
550 .rates = SNDRV_PCM_RATE_8000_96000,
551 .formats = WM8770_FORMATS
552 },
553 .ops = &wm8770_dai_ops,
554 .symmetric_rates = 1
555};
556
557#ifdef CONFIG_PM
558static int wm8770_suspend(struct snd_soc_codec *codec, pm_message_t state)
559{
560 wm8770_set_bias_level(codec, SND_SOC_BIAS_OFF);
561 return 0;
562}
563
564static int wm8770_resume(struct snd_soc_codec *codec)
565{
566 wm8770_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
567 return 0;
568}
569#else
570#define wm8770_suspend NULL
571#define wm8770_resume NULL
572#endif
573
574static int wm8770_probe(struct snd_soc_codec *codec)
575{
576 struct wm8770_priv *wm8770;
577 int ret;
578 int i;
579
580 wm8770 = snd_soc_codec_get_drvdata(codec);
581 wm8770->codec = codec;
582
583 codec->dapm.idle_bias_off = 1;
584
585 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8770->control_type);
586 if (ret < 0) {
587 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
588 return ret;
589 }
590
591 for (i = 0; i < ARRAY_SIZE(wm8770->supplies); i++)
592 wm8770->supplies[i].supply = wm8770_supply_names[i];
593
594 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8770->supplies),
595 wm8770->supplies);
596 if (ret) {
597 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
598 return ret;
599 }
600
601 wm8770->disable_nb[0].notifier_call = wm8770_regulator_event_0;
602 wm8770->disable_nb[1].notifier_call = wm8770_regulator_event_1;
603 wm8770->disable_nb[2].notifier_call = wm8770_regulator_event_2;
604
605 /* This should really be moved into the regulator core */
606 for (i = 0; i < ARRAY_SIZE(wm8770->supplies); i++) {
607 ret = regulator_register_notifier(wm8770->supplies[i].consumer,
608 &wm8770->disable_nb[i]);
609 if (ret) {
610 dev_err(codec->dev,
611 "Failed to register regulator notifier: %d\n",
612 ret);
613 }
614 }
615
616 ret = regulator_bulk_enable(ARRAY_SIZE(wm8770->supplies),
617 wm8770->supplies);
618 if (ret) {
619 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
620 goto err_reg_get;
621 }
622
623 ret = wm8770_reset(codec);
624 if (ret < 0) {
625 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
626 goto err_reg_enable;
627 }
628
629 wm8770_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
630
631 /* latch the volume update bits */
632 snd_soc_update_bits(codec, WM8770_MSDIGVOL, 0x100, 0x100);
633 snd_soc_update_bits(codec, WM8770_MSALGVOL, 0x100, 0x100);
634 snd_soc_update_bits(codec, WM8770_VOUT1RVOL, 0x100, 0x100);
635 snd_soc_update_bits(codec, WM8770_VOUT2RVOL, 0x100, 0x100);
636 snd_soc_update_bits(codec, WM8770_VOUT3RVOL, 0x100, 0x100);
637 snd_soc_update_bits(codec, WM8770_VOUT4RVOL, 0x100, 0x100);
638 snd_soc_update_bits(codec, WM8770_DAC1RVOL, 0x100, 0x100);
639 snd_soc_update_bits(codec, WM8770_DAC2RVOL, 0x100, 0x100);
640 snd_soc_update_bits(codec, WM8770_DAC3RVOL, 0x100, 0x100);
641 snd_soc_update_bits(codec, WM8770_DAC4RVOL, 0x100, 0x100);
642
643 /* mute all DACs */
644 snd_soc_update_bits(codec, WM8770_DACMUTE, 0x10, 0x10);
645
646 snd_soc_add_controls(codec, wm8770_snd_controls,
647 ARRAY_SIZE(wm8770_snd_controls));
648 snd_soc_dapm_new_controls(&codec->dapm, wm8770_dapm_widgets,
649 ARRAY_SIZE(wm8770_dapm_widgets));
650 snd_soc_dapm_add_routes(&codec->dapm, wm8770_intercon,
651 ARRAY_SIZE(wm8770_intercon));
652 return 0;
653
654err_reg_enable:
655 regulator_bulk_disable(ARRAY_SIZE(wm8770->supplies), wm8770->supplies);
656err_reg_get:
657 regulator_bulk_free(ARRAY_SIZE(wm8770->supplies), wm8770->supplies);
658 return ret;
659}
660
661static int wm8770_remove(struct snd_soc_codec *codec)
662{
663 struct wm8770_priv *wm8770;
664 int i;
665
666 wm8770 = snd_soc_codec_get_drvdata(codec);
667 wm8770_set_bias_level(codec, SND_SOC_BIAS_OFF);
668
669 for (i = 0; i < ARRAY_SIZE(wm8770->supplies); ++i)
670 regulator_unregister_notifier(wm8770->supplies[i].consumer,
671 &wm8770->disable_nb[i]);
672 regulator_bulk_free(ARRAY_SIZE(wm8770->supplies), wm8770->supplies);
673 return 0;
674}
675
676static struct snd_soc_codec_driver soc_codec_dev_wm8770 = {
677 .probe = wm8770_probe,
678 .remove = wm8770_remove,
679 .suspend = wm8770_suspend,
680 .resume = wm8770_resume,
681 .set_bias_level = wm8770_set_bias_level,
682 .reg_cache_size = ARRAY_SIZE(wm8770_reg_defs),
683 .reg_word_size = sizeof (u16),
684 .reg_cache_default = wm8770_reg_defs
685};
686
687#if defined(CONFIG_SPI_MASTER)
688static int __devinit wm8770_spi_probe(struct spi_device *spi)
689{
690 struct wm8770_priv *wm8770;
691 int ret;
692
693 wm8770 = kzalloc(sizeof(struct wm8770_priv), GFP_KERNEL);
694 if (!wm8770)
695 return -ENOMEM;
696
697 wm8770->control_type = SND_SOC_SPI;
698 spi_set_drvdata(spi, wm8770);
699
700 ret = snd_soc_register_codec(&spi->dev,
701 &soc_codec_dev_wm8770, &wm8770_dai, 1);
702 if (ret < 0)
703 kfree(wm8770);
704 return ret;
705}
706
707static int __devexit wm8770_spi_remove(struct spi_device *spi)
708{
709 snd_soc_unregister_codec(&spi->dev);
710 kfree(spi_get_drvdata(spi));
711 return 0;
712}
713
714static struct spi_driver wm8770_spi_driver = {
715 .driver = {
716 .name = "wm8770",
717 .owner = THIS_MODULE,
718 },
719 .probe = wm8770_spi_probe,
720 .remove = __devexit_p(wm8770_spi_remove)
721};
722#endif
723
724static int __init wm8770_modinit(void)
725{
726 int ret = 0;
727
728#if defined(CONFIG_SPI_MASTER)
729 ret = spi_register_driver(&wm8770_spi_driver);
730 if (ret) {
731 printk(KERN_ERR "Failed to register wm8770 SPI driver: %d\n",
732 ret);
733 }
734#endif
735 return ret;
736}
737module_init(wm8770_modinit);
738
739static void __exit wm8770_exit(void)
740{
741#if defined(CONFIG_SPI_MASTER)
742 spi_unregister_driver(&wm8770_spi_driver);
743#endif
744}
745module_exit(wm8770_exit);
746
747MODULE_DESCRIPTION("ASoC WM8770 driver");
748MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
749MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8770.h b/sound/soc/codecs/wm8770.h
new file mode 100644
index 000000000000..5f1b3bda6cc8
--- /dev/null
+++ b/sound/soc/codecs/wm8770.h
@@ -0,0 +1,51 @@
1/*
2 * wm8770.h -- WM8770 ASoC driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef _WM8770_H
14#define _WM8770_H
15
16/* Registers */
17#define WM8770_VOUT1LVOL 0
18#define WM8770_VOUT1RVOL 0x1
19#define WM8770_VOUT2LVOL 0x2
20#define WM8770_VOUT2RVOL 0x3
21#define WM8770_VOUT3LVOL 0x4
22#define WM8770_VOUT3RVOL 0x5
23#define WM8770_VOUT4LVOL 0x6
24#define WM8770_VOUT4RVOL 0x7
25#define WM8770_MSALGVOL 0x8
26#define WM8770_DAC1LVOL 0x9
27#define WM8770_DAC1RVOL 0xa
28#define WM8770_DAC2LVOL 0xb
29#define WM8770_DAC2RVOL 0xc
30#define WM8770_DAC3LVOL 0xd
31#define WM8770_DAC3RVOL 0xe
32#define WM8770_DAC4LVOL 0xf
33#define WM8770_DAC4RVOL 0x10
34#define WM8770_MSDIGVOL 0x11
35#define WM8770_DACPHASE 0x12
36#define WM8770_DACCTRL1 0x13
37#define WM8770_DACMUTE 0x14
38#define WM8770_DACCTRL2 0x15
39#define WM8770_IFACECTRL 0x16
40#define WM8770_MSTRCTRL 0x17
41#define WM8770_PWDNCTRL 0x18
42#define WM8770_ADCLCTRL 0x19
43#define WM8770_ADCRCTRL 0x1a
44#define WM8770_ADCMUX 0x1b
45#define WM8770_OUTMUX1 0x1c
46#define WM8770_OUTMUX2 0x1d
47#define WM8770_RESET 0x31
48
49#define WM8770_CACHEREGNUM 0x20
50
51#endif
diff --git a/sound/soc/codecs/wm8776.c b/sound/soc/codecs/wm8776.c
index 0132a27140ae..8e7953b1b790 100644
--- a/sound/soc/codecs/wm8776.c
+++ b/sound/soc/codecs/wm8776.c
@@ -25,7 +25,6 @@
25#include <sound/pcm.h> 25#include <sound/pcm.h>
26#include <sound/pcm_params.h> 26#include <sound/pcm_params.h>
27#include <sound/soc.h> 27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h> 28#include <sound/initval.h>
30#include <sound/tlv.h> 29#include <sound/tlv.h>
31 30
@@ -306,7 +305,7 @@ static int wm8776_set_bias_level(struct snd_soc_codec *codec,
306 case SND_SOC_BIAS_PREPARE: 305 case SND_SOC_BIAS_PREPARE:
307 break; 306 break;
308 case SND_SOC_BIAS_STANDBY: 307 case SND_SOC_BIAS_STANDBY:
309 if (codec->bias_level == SND_SOC_BIAS_OFF) { 308 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
310 /* Disable the global powerdown; DAPM does the rest */ 309 /* Disable the global powerdown; DAPM does the rest */
311 snd_soc_update_bits(codec, WM8776_PWRDOWN, 1, 0); 310 snd_soc_update_bits(codec, WM8776_PWRDOWN, 1, 0);
312 } 311 }
@@ -317,7 +316,7 @@ static int wm8776_set_bias_level(struct snd_soc_codec *codec,
317 break; 316 break;
318 } 317 }
319 318
320 codec->bias_level = level; 319 codec->dapm.bias_level = level;
321 return 0; 320 return 0;
322} 321}
323 322
@@ -404,6 +403,7 @@ static int wm8776_resume(struct snd_soc_codec *codec)
404static int wm8776_probe(struct snd_soc_codec *codec) 403static int wm8776_probe(struct snd_soc_codec *codec)
405{ 404{
406 struct wm8776_priv *wm8776 = snd_soc_codec_get_drvdata(codec); 405 struct wm8776_priv *wm8776 = snd_soc_codec_get_drvdata(codec);
406 struct snd_soc_dapm_context *dapm = &codec->dapm;
407 int ret = 0; 407 int ret = 0;
408 408
409 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8776->control_type); 409 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8776->control_type);
@@ -427,9 +427,9 @@ static int wm8776_probe(struct snd_soc_codec *codec)
427 427
428 snd_soc_add_controls(codec, wm8776_snd_controls, 428 snd_soc_add_controls(codec, wm8776_snd_controls,
429 ARRAY_SIZE(wm8776_snd_controls)); 429 ARRAY_SIZE(wm8776_snd_controls));
430 snd_soc_dapm_new_controls(codec, wm8776_dapm_widgets, 430 snd_soc_dapm_new_controls(dapm, wm8776_dapm_widgets,
431 ARRAY_SIZE(wm8776_dapm_widgets)); 431 ARRAY_SIZE(wm8776_dapm_widgets));
432 snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes)); 432 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
433 433
434 return ret; 434 return ret;
435} 435}
diff --git a/sound/soc/codecs/wm8804.c b/sound/soc/codecs/wm8804.c
index 4599e8e95aa2..6dae1b40c9f7 100644
--- a/sound/soc/codecs/wm8804.c
+++ b/sound/soc/codecs/wm8804.c
@@ -23,7 +23,6 @@
23#include <sound/pcm.h> 23#include <sound/pcm.h>
24#include <sound/pcm_params.h> 24#include <sound/pcm_params.h>
25#include <sound/soc.h> 25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h> 26#include <sound/initval.h>
28#include <sound/tlv.h> 27#include <sound/tlv.h>
29 28
@@ -515,7 +514,7 @@ static int wm8804_set_bias_level(struct snd_soc_codec *codec,
515 snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0); 514 snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
516 break; 515 break;
517 case SND_SOC_BIAS_STANDBY: 516 case SND_SOC_BIAS_STANDBY:
518 if (codec->bias_level == SND_SOC_BIAS_OFF) { 517 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
519 ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies), 518 ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
520 wm8804->supplies); 519 wm8804->supplies);
521 if (ret) { 520 if (ret) {
@@ -537,7 +536,7 @@ static int wm8804_set_bias_level(struct snd_soc_codec *codec,
537 break; 536 break;
538 } 537 }
539 538
540 codec->bias_level = level; 539 codec->dapm.bias_level = level;
541 return 0; 540 return 0;
542} 541}
543 542
@@ -581,7 +580,7 @@ static int wm8804_probe(struct snd_soc_codec *codec)
581 wm8804 = snd_soc_codec_get_drvdata(codec); 580 wm8804 = snd_soc_codec_get_drvdata(codec);
582 wm8804->codec = codec; 581 wm8804->codec = codec;
583 582
584 codec->idle_bias_off = 1; 583 codec->dapm.idle_bias_off = 1;
585 584
586 ret = snd_soc_codec_set_cache_io(codec, 8, 8, wm8804->control_type); 585 ret = snd_soc_codec_set_cache_io(codec, 8, 8, wm8804->control_type);
587 if (ret < 0) { 586 if (ret < 0) {
diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c
index aca4b1ea10bb..cd0959926d12 100644
--- a/sound/soc/codecs/wm8900.c
+++ b/sound/soc/codecs/wm8900.c
@@ -30,7 +30,6 @@
30#include <sound/pcm.h> 30#include <sound/pcm.h>
31#include <sound/pcm_params.h> 31#include <sound/pcm_params.h>
32#include <sound/soc.h> 32#include <sound/soc.h>
33#include <sound/soc-dapm.h>
34#include <sound/initval.h> 33#include <sound/initval.h>
35#include <sound/tlv.h> 34#include <sound/tlv.h>
36 35
@@ -140,7 +139,6 @@
140 139
141struct wm8900_priv { 140struct wm8900_priv {
142 enum snd_soc_control_type control_type; 141 enum snd_soc_control_type control_type;
143 u16 reg_cache[WM8900_MAXREG];
144 142
145 u32 fll_in; /* FLL input frequency */ 143 u32 fll_in; /* FLL input frequency */
146 u32 fll_out; /* FLL output frequency */ 144 u32 fll_out; /* FLL output frequency */
@@ -611,10 +609,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
611 609
612static int wm8900_add_widgets(struct snd_soc_codec *codec) 610static int wm8900_add_widgets(struct snd_soc_codec *codec)
613{ 611{
614 snd_soc_dapm_new_controls(codec, wm8900_dapm_widgets, 612 struct snd_soc_dapm_context *dapm = &codec->dapm;
615 ARRAY_SIZE(wm8900_dapm_widgets));
616 613
617 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 614 snd_soc_dapm_new_controls(dapm, wm8900_dapm_widgets,
615 ARRAY_SIZE(wm8900_dapm_widgets));
616 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
618 617
619 return 0; 618 return 0;
620} 619}
@@ -1051,7 +1050,7 @@ static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1051 1050
1052 case SND_SOC_BIAS_STANDBY: 1051 case SND_SOC_BIAS_STANDBY:
1053 /* Charge capacitors if initial power up */ 1052 /* Charge capacitors if initial power up */
1054 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1053 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1055 /* STARTUP_BIAS_ENA on */ 1054 /* STARTUP_BIAS_ENA on */
1056 snd_soc_write(codec, WM8900_REG_POWER1, 1055 snd_soc_write(codec, WM8900_REG_POWER1,
1057 WM8900_REG_POWER1_STARTUP_BIAS_ENA); 1056 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
@@ -1119,7 +1118,7 @@ static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1119 WM8900_REG_POWER2_SYSCLK_ENA); 1118 WM8900_REG_POWER2_SYSCLK_ENA);
1120 break; 1119 break;
1121 } 1120 }
1122 codec->bias_level = level; 1121 codec->dapm.bias_level = level;
1123 return 0; 1122 return 0;
1124} 1123}
1125 1124
diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c
index 622b60238a82..987476a5895f 100644
--- a/sound/soc/codecs/wm8903.c
+++ b/sound/soc/codecs/wm8903.c
@@ -29,9 +29,9 @@
29#include <sound/pcm_params.h> 29#include <sound/pcm_params.h>
30#include <sound/tlv.h> 30#include <sound/tlv.h>
31#include <sound/soc.h> 31#include <sound/soc.h>
32#include <sound/soc-dapm.h>
33#include <sound/initval.h> 32#include <sound/initval.h>
34#include <sound/wm8903.h> 33#include <sound/wm8903.h>
34#include <trace/events/asoc.h>
35 35
36#include "wm8903.h" 36#include "wm8903.h"
37 37
@@ -214,15 +214,14 @@ static u16 wm8903_reg_defaults[] = {
214 214
215struct wm8903_priv { 215struct wm8903_priv {
216 216
217 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
218
219 int sysclk; 217 int sysclk;
220 int irq; 218 int irq;
221 219
222 /* Reference counts */ 220 int fs;
221 int deemph;
222
223 /* Reference count */
223 int class_w_users; 224 int class_w_users;
224 int playback_active;
225 int capture_active;
226 225
227 struct completion wseq; 226 struct completion wseq;
228 227
@@ -231,9 +230,6 @@ struct wm8903_priv {
231 int mic_short; 230 int mic_short;
232 int mic_last_report; 231 int mic_last_report;
233 int mic_delay; 232 int mic_delay;
234
235 struct snd_pcm_substream *master_substream;
236 struct snd_pcm_substream *slave_substream;
237}; 233};
238 234
239static int wm8903_volatile_register(unsigned int reg) 235static int wm8903_volatile_register(unsigned int reg)
@@ -463,6 +459,72 @@ static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
463 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } 459 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
464 460
465 461
462static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
463
464static int wm8903_set_deemph(struct snd_soc_codec *codec)
465{
466 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
467 int val, i, best;
468
469 /* If we're using deemphasis select the nearest available sample
470 * rate.
471 */
472 if (wm8903->deemph) {
473 best = 1;
474 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
475 if (abs(wm8903_deemph[i] - wm8903->fs) <
476 abs(wm8903_deemph[best] - wm8903->fs))
477 best = i;
478 }
479
480 val = best << WM8903_DEEMPH_SHIFT;
481 } else {
482 best = 0;
483 val = 0;
484 }
485
486 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
487 best, wm8903_deemph[best]);
488
489 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
490 WM8903_DEEMPH_MASK, val);
491}
492
493static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
494 struct snd_ctl_elem_value *ucontrol)
495{
496 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
497 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
498
499 ucontrol->value.enumerated.item[0] = wm8903->deemph;
500
501 return 0;
502}
503
504static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
505 struct snd_ctl_elem_value *ucontrol)
506{
507 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
508 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
509 int deemph = ucontrol->value.enumerated.item[0];
510 int ret = 0;
511
512 if (deemph > 1)
513 return -EINVAL;
514
515 mutex_lock(&codec->mutex);
516 if (wm8903->deemph != deemph) {
517 wm8903->deemph = deemph;
518
519 wm8903_set_deemph(codec);
520
521 ret = 1;
522 }
523 mutex_unlock(&codec->mutex);
524
525 return ret;
526}
527
466/* ALSA can only do steps of .01dB */ 528/* ALSA can only do steps of .01dB */
467static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 529static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
468 530
@@ -475,6 +537,23 @@ static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
475static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0); 537static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
476static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0); 538static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
477 539
540static const char *hpf_mode_text[] = {
541 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
542};
543
544static const struct soc_enum hpf_mode =
545 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
546
547static const char *osr_text[] = {
548 "Low power", "High performance"
549};
550
551static const struct soc_enum adc_osr =
552 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
553
554static const struct soc_enum dac_osr =
555 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
556
478static const char *drc_slope_text[] = { 557static const char *drc_slope_text[] = {
479 "1", "1/2", "1/4", "1/8", "1/16", "0" 558 "1", "1/2", "1/4", "1/8", "1/16", "0"
480}; 559};
@@ -537,13 +616,6 @@ static const char *mute_mode_text[] = {
537static const struct soc_enum mute_mode = 616static const struct soc_enum mute_mode =
538 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text); 617 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
539 618
540static const char *dac_deemphasis_text[] = {
541 "Disabled", "32kHz", "44.1kHz", "48kHz"
542};
543
544static const struct soc_enum dac_deemphasis =
545 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
546
547static const char *companding_text[] = { 619static const char *companding_text[] = {
548 "ulaw", "alaw" 620 "ulaw", "alaw"
549}; 621};
@@ -613,6 +685,9 @@ SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
613 6, 1, 0), 685 6, 1, 0),
614 686
615/* ADCs */ 687/* ADCs */
688SOC_ENUM("ADC OSR", adc_osr),
689SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
690SOC_ENUM("HPF Mode", hpf_mode),
616SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), 691SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
617SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0), 692SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
618SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1), 693SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
@@ -642,14 +717,16 @@ SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
642 12, 0, digital_sidetone_tlv), 717 12, 0, digital_sidetone_tlv),
643 718
644/* DAC */ 719/* DAC */
720SOC_ENUM("DAC OSR", dac_osr),
645SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT, 721SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
646 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), 722 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
647SOC_ENUM("DAC Soft Mute Rate", soft_mute), 723SOC_ENUM("DAC Soft Mute Rate", soft_mute),
648SOC_ENUM("DAC Mute Mode", mute_mode), 724SOC_ENUM("DAC Mute Mode", mute_mode),
649SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0), 725SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
650SOC_ENUM("DAC De-emphasis", dac_deemphasis),
651SOC_ENUM("DAC Companding Mode", dac_companding), 726SOC_ENUM("DAC Companding Mode", dac_companding),
652SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0), 727SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
728SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
729 wm8903_get_deemph, wm8903_put_deemph),
653 730
654/* Headphones */ 731/* Headphones */
655SOC_DOUBLE_R("Headphone Switch", 732SOC_DOUBLE_R("Headphone Switch",
@@ -923,10 +1000,11 @@ static const struct snd_soc_dapm_route intercon[] = {
923 1000
924static int wm8903_add_widgets(struct snd_soc_codec *codec) 1001static int wm8903_add_widgets(struct snd_soc_codec *codec)
925{ 1002{
926 snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets, 1003 struct snd_soc_dapm_context *dapm = &codec->dapm;
927 ARRAY_SIZE(wm8903_dapm_widgets));
928 1004
929 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 1005 snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets,
1006 ARRAY_SIZE(wm8903_dapm_widgets));
1007 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
930 1008
931 return 0; 1009 return 0;
932} 1010}
@@ -934,7 +1012,7 @@ static int wm8903_add_widgets(struct snd_soc_codec *codec)
934static int wm8903_set_bias_level(struct snd_soc_codec *codec, 1012static int wm8903_set_bias_level(struct snd_soc_codec *codec,
935 enum snd_soc_bias_level level) 1013 enum snd_soc_bias_level level)
936{ 1014{
937 u16 reg, reg2; 1015 u16 reg;
938 1016
939 switch (level) { 1017 switch (level) {
940 case SND_SOC_BIAS_ON: 1018 case SND_SOC_BIAS_ON:
@@ -946,7 +1024,7 @@ static int wm8903_set_bias_level(struct snd_soc_codec *codec,
946 break; 1024 break;
947 1025
948 case SND_SOC_BIAS_STANDBY: 1026 case SND_SOC_BIAS_STANDBY:
949 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1027 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
950 snd_soc_write(codec, WM8903_CLOCK_RATES_2, 1028 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
951 WM8903_CLK_SYS_ENA); 1029 WM8903_CLK_SYS_ENA);
952 1030
@@ -958,23 +1036,15 @@ static int wm8903_set_bias_level(struct snd_soc_codec *codec,
958 wm8903_run_sequence(codec, 0); 1036 wm8903_run_sequence(codec, 0);
959 wm8903_sync_reg_cache(codec, codec->reg_cache); 1037 wm8903_sync_reg_cache(codec, codec->reg_cache);
960 1038
961 /* Enable low impedence charge pump output */
962 reg = snd_soc_read(codec,
963 WM8903_CONTROL_INTERFACE_TEST_1);
964 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
965 reg | WM8903_TEST_KEY);
966 reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1);
967 snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1,
968 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
969 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
970 reg);
971
972 /* By default no bypass paths are enabled so 1039 /* By default no bypass paths are enabled so
973 * enable Class W support. 1040 * enable Class W support.
974 */ 1041 */
975 dev_dbg(codec->dev, "Enabling Class W\n"); 1042 dev_dbg(codec->dev, "Enabling Class W\n");
976 snd_soc_write(codec, WM8903_CLASS_W_0, reg | 1043 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
977 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); 1044 WM8903_CP_DYN_FREQ |
1045 WM8903_CP_DYN_V,
1046 WM8903_CP_DYN_FREQ |
1047 WM8903_CP_DYN_V);
978 } 1048 }
979 1049
980 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0); 1050 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
@@ -991,7 +1061,7 @@ static int wm8903_set_bias_level(struct snd_soc_codec *codec,
991 break; 1061 break;
992 } 1062 }
993 1063
994 codec->bias_level = level; 1064 codec->dapm.bias_level = level;
995 1065
996 return 0; 1066 return 0;
997} 1067}
@@ -1222,58 +1292,6 @@ static struct {
1222 { 0, 0 }, 1292 { 0, 0 },
1223}; 1293};
1224 1294
1225static int wm8903_startup(struct snd_pcm_substream *substream,
1226 struct snd_soc_dai *dai)
1227{
1228 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1229 struct snd_soc_codec *codec = rtd->codec;
1230 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1231 struct snd_pcm_runtime *master_runtime;
1232
1233 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1234 wm8903->playback_active++;
1235 else
1236 wm8903->capture_active++;
1237
1238 /* The DAI has shared clocks so if we already have a playback or
1239 * capture going then constrain this substream to match it.
1240 */
1241 if (wm8903->master_substream) {
1242 master_runtime = wm8903->master_substream->runtime;
1243
1244 dev_dbg(codec->dev, "Constraining to %d bits\n",
1245 master_runtime->sample_bits);
1246
1247 snd_pcm_hw_constraint_minmax(substream->runtime,
1248 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1249 master_runtime->sample_bits,
1250 master_runtime->sample_bits);
1251
1252 wm8903->slave_substream = substream;
1253 } else
1254 wm8903->master_substream = substream;
1255
1256 return 0;
1257}
1258
1259static void wm8903_shutdown(struct snd_pcm_substream *substream,
1260 struct snd_soc_dai *dai)
1261{
1262 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1263 struct snd_soc_codec *codec = rtd->codec;
1264 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1265
1266 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1267 wm8903->playback_active--;
1268 else
1269 wm8903->capture_active--;
1270
1271 if (wm8903->master_substream == substream)
1272 wm8903->master_substream = wm8903->slave_substream;
1273
1274 wm8903->slave_substream = NULL;
1275}
1276
1277static int wm8903_hw_params(struct snd_pcm_substream *substream, 1295static int wm8903_hw_params(struct snd_pcm_substream *substream,
1278 struct snd_pcm_hw_params *params, 1296 struct snd_pcm_hw_params *params,
1279 struct snd_soc_dai *dai) 1297 struct snd_soc_dai *dai)
@@ -1298,11 +1316,6 @@ static int wm8903_hw_params(struct snd_pcm_substream *substream,
1298 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1); 1316 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1299 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); 1317 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1300 1318
1301 if (substream == wm8903->slave_substream) {
1302 dev_dbg(codec->dev, "Ignoring hw_params for slave substream\n");
1303 return 0;
1304 }
1305
1306 /* Enable sloping stopband filter for low sample rates */ 1319 /* Enable sloping stopband filter for low sample rates */
1307 if (fs <= 24000) 1320 if (fs <= 24000)
1308 dac_digital1 |= WM8903_DAC_SB_FILT; 1321 dac_digital1 |= WM8903_DAC_SB_FILT;
@@ -1320,19 +1333,6 @@ static int wm8903_hw_params(struct snd_pcm_substream *substream,
1320 } 1333 }
1321 } 1334 }
1322 1335
1323 /* Constraints should stop us hitting this but let's make sure */
1324 if (wm8903->capture_active)
1325 switch (sample_rates[dsp_config].rate) {
1326 case 88200:
1327 case 96000:
1328 dev_err(codec->dev, "%dHz unsupported by ADC\n",
1329 fs);
1330 return -EINVAL;
1331
1332 default:
1333 break;
1334 }
1335
1336 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate); 1336 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1337 clock1 &= ~WM8903_SAMPLE_RATE_MASK; 1337 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1338 clock1 |= sample_rates[dsp_config].value; 1338 clock1 |= sample_rates[dsp_config].value;
@@ -1428,6 +1428,9 @@ static int wm8903_hw_params(struct snd_pcm_substream *substream,
1428 aif2 |= bclk_divs[bclk_div].div; 1428 aif2 |= bclk_divs[bclk_div].div;
1429 aif3 |= bclk / fs; 1429 aif3 |= bclk / fs;
1430 1430
1431 wm8903->fs = params_rate(params);
1432 wm8903_set_deemph(codec);
1433
1431 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0); 1434 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1432 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1); 1435 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1433 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); 1436 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
@@ -1521,6 +1524,11 @@ static irqreturn_t wm8903_irq(int irq, void *data)
1521 mic_report = wm8903->mic_last_report; 1524 mic_report = wm8903->mic_last_report;
1522 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1); 1525 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1523 1526
1527#ifndef CONFIG_SND_SOC_WM8903_MODULE
1528 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1529 trace_snd_soc_jack_irq(dev_name(codec->dev));
1530#endif
1531
1524 if (int_val & WM8903_MICSHRT_EINT) { 1532 if (int_val & WM8903_MICSHRT_EINT) {
1525 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol); 1533 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1526 1534
@@ -1571,8 +1579,6 @@ static irqreturn_t wm8903_irq(int irq, void *data)
1571 SNDRV_PCM_FMTBIT_S24_LE) 1579 SNDRV_PCM_FMTBIT_S24_LE)
1572 1580
1573static struct snd_soc_dai_ops wm8903_dai_ops = { 1581static struct snd_soc_dai_ops wm8903_dai_ops = {
1574 .startup = wm8903_startup,
1575 .shutdown = wm8903_shutdown,
1576 .hw_params = wm8903_hw_params, 1582 .hw_params = wm8903_hw_params,
1577 .digital_mute = wm8903_digital_mute, 1583 .digital_mute = wm8903_digital_mute,
1578 .set_fmt = wm8903_set_dai_fmt, 1584 .set_fmt = wm8903_set_dai_fmt,
diff --git a/sound/soc/codecs/wm8903.h b/sound/soc/codecs/wm8903.h
index 996435e681e5..e8490f3edd03 100644
--- a/sound/soc/codecs/wm8903.h
+++ b/sound/soc/codecs/wm8903.h
@@ -19,10 +19,6 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec,
19 struct snd_soc_jack *jack, 19 struct snd_soc_jack *jack,
20 int det, int shrt); 20 int det, int shrt);
21 21
22#define WM8903_MCLK_DIV_2 1
23#define WM8903_CLK_SYS 2
24#define WM8903_BCLK 3
25#define WM8903_LRCLK 4
26 22
27/* 23/*
28 * Register values. 24 * Register values.
@@ -98,8 +94,6 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec,
98#define WM8903_INTERRUPT_STATUS_1_MASK 0x7A 94#define WM8903_INTERRUPT_STATUS_1_MASK 0x7A
99#define WM8903_INTERRUPT_POLARITY_1 0x7B 95#define WM8903_INTERRUPT_POLARITY_1 0x7B
100#define WM8903_INTERRUPT_CONTROL 0x7E 96#define WM8903_INTERRUPT_CONTROL 0x7E
101#define WM8903_CONTROL_INTERFACE_TEST_1 0x81
102#define WM8903_CHARGE_PUMP_TEST_1 0x95
103#define WM8903_CLOCK_RATE_TEST_4 0xA4 97#define WM8903_CLOCK_RATE_TEST_4 0xA4
104#define WM8903_ANALOGUE_OUTPUT_BIAS_0 0xAC 98#define WM8903_ANALOGUE_OUTPUT_BIAS_0 0xAC
105 99
@@ -1206,25 +1200,6 @@ extern int wm8903_mic_detect(struct snd_soc_codec *codec,
1206#define WM8903_IRQ_POL_WIDTH 1 /* IRQ_POL */ 1200#define WM8903_IRQ_POL_WIDTH 1 /* IRQ_POL */
1207 1201
1208/* 1202/*
1209 * R129 (0x81) - Control Interface Test 1
1210 */
1211#define WM8903_USER_KEY 0x0002 /* USER_KEY */
1212#define WM8903_USER_KEY_MASK 0x0002 /* USER_KEY */
1213#define WM8903_USER_KEY_SHIFT 1 /* USER_KEY */
1214#define WM8903_USER_KEY_WIDTH 1 /* USER_KEY */
1215#define WM8903_TEST_KEY 0x0001 /* TEST_KEY */
1216#define WM8903_TEST_KEY_MASK 0x0001 /* TEST_KEY */
1217#define WM8903_TEST_KEY_SHIFT 0 /* TEST_KEY */
1218#define WM8903_TEST_KEY_WIDTH 1 /* TEST_KEY */
1219
1220/*
1221 * R149 (0x95) - Charge Pump Test 1
1222 */
1223#define WM8903_CP_SW_KELVIN_MODE_MASK 0x0006 /* CP_SW_KELVIN_MODE - [2:1] */
1224#define WM8903_CP_SW_KELVIN_MODE_SHIFT 1 /* CP_SW_KELVIN_MODE - [2:1] */
1225#define WM8903_CP_SW_KELVIN_MODE_WIDTH 2 /* CP_SW_KELVIN_MODE - [2:1] */
1226
1227/*
1228 * R164 (0xA4) - Clock Rate Test 4 1203 * R164 (0xA4) - Clock Rate Test 4
1229 */ 1204 */
1230#define WM8903_ADC_DIG_MIC 0x0200 /* ADC_DIG_MIC */ 1205#define WM8903_ADC_DIG_MIC 0x0200 /* ADC_DIG_MIC */
diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c
index 1ec12eff0620..9de44a4c05c0 100644
--- a/sound/soc/codecs/wm8904.c
+++ b/sound/soc/codecs/wm8904.c
@@ -24,7 +24,6 @@
24#include <sound/pcm.h> 24#include <sound/pcm.h>
25#include <sound/pcm_params.h> 25#include <sound/pcm_params.h>
26#include <sound/soc.h> 26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h> 27#include <sound/initval.h>
29#include <sound/tlv.h> 28#include <sound/tlv.h>
30#include <sound/wm8904.h> 29#include <sound/wm8904.h>
@@ -1427,10 +1426,11 @@ static const struct snd_soc_dapm_route wm8912_intercon[] = {
1427static int wm8904_add_widgets(struct snd_soc_codec *codec) 1426static int wm8904_add_widgets(struct snd_soc_codec *codec)
1428{ 1427{
1429 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); 1428 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
1429 struct snd_soc_dapm_context *dapm = &codec->dapm;
1430 1430
1431 snd_soc_dapm_new_controls(codec, wm8904_core_dapm_widgets, 1431 snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets,
1432 ARRAY_SIZE(wm8904_core_dapm_widgets)); 1432 ARRAY_SIZE(wm8904_core_dapm_widgets));
1433 snd_soc_dapm_add_routes(codec, core_intercon, 1433 snd_soc_dapm_add_routes(dapm, core_intercon,
1434 ARRAY_SIZE(core_intercon)); 1434 ARRAY_SIZE(core_intercon));
1435 1435
1436 switch (wm8904->devtype) { 1436 switch (wm8904->devtype) {
@@ -1442,20 +1442,20 @@ static int wm8904_add_widgets(struct snd_soc_codec *codec)
1442 snd_soc_add_controls(codec, wm8904_snd_controls, 1442 snd_soc_add_controls(codec, wm8904_snd_controls,
1443 ARRAY_SIZE(wm8904_snd_controls)); 1443 ARRAY_SIZE(wm8904_snd_controls));
1444 1444
1445 snd_soc_dapm_new_controls(codec, wm8904_adc_dapm_widgets, 1445 snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets,
1446 ARRAY_SIZE(wm8904_adc_dapm_widgets)); 1446 ARRAY_SIZE(wm8904_adc_dapm_widgets));
1447 snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets, 1447 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
1448 ARRAY_SIZE(wm8904_dac_dapm_widgets)); 1448 ARRAY_SIZE(wm8904_dac_dapm_widgets));
1449 snd_soc_dapm_new_controls(codec, wm8904_dapm_widgets, 1449 snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets,
1450 ARRAY_SIZE(wm8904_dapm_widgets)); 1450 ARRAY_SIZE(wm8904_dapm_widgets));
1451 1451
1452 snd_soc_dapm_add_routes(codec, core_intercon, 1452 snd_soc_dapm_add_routes(dapm, core_intercon,
1453 ARRAY_SIZE(core_intercon)); 1453 ARRAY_SIZE(core_intercon));
1454 snd_soc_dapm_add_routes(codec, adc_intercon, 1454 snd_soc_dapm_add_routes(dapm, adc_intercon,
1455 ARRAY_SIZE(adc_intercon)); 1455 ARRAY_SIZE(adc_intercon));
1456 snd_soc_dapm_add_routes(codec, dac_intercon, 1456 snd_soc_dapm_add_routes(dapm, dac_intercon,
1457 ARRAY_SIZE(dac_intercon)); 1457 ARRAY_SIZE(dac_intercon));
1458 snd_soc_dapm_add_routes(codec, wm8904_intercon, 1458 snd_soc_dapm_add_routes(dapm, wm8904_intercon,
1459 ARRAY_SIZE(wm8904_intercon)); 1459 ARRAY_SIZE(wm8904_intercon));
1460 break; 1460 break;
1461 1461
@@ -1463,17 +1463,17 @@ static int wm8904_add_widgets(struct snd_soc_codec *codec)
1463 snd_soc_add_controls(codec, wm8904_dac_snd_controls, 1463 snd_soc_add_controls(codec, wm8904_dac_snd_controls,
1464 ARRAY_SIZE(wm8904_dac_snd_controls)); 1464 ARRAY_SIZE(wm8904_dac_snd_controls));
1465 1465
1466 snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets, 1466 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
1467 ARRAY_SIZE(wm8904_dac_dapm_widgets)); 1467 ARRAY_SIZE(wm8904_dac_dapm_widgets));
1468 1468
1469 snd_soc_dapm_add_routes(codec, dac_intercon, 1469 snd_soc_dapm_add_routes(dapm, dac_intercon,
1470 ARRAY_SIZE(dac_intercon)); 1470 ARRAY_SIZE(dac_intercon));
1471 snd_soc_dapm_add_routes(codec, wm8912_intercon, 1471 snd_soc_dapm_add_routes(dapm, wm8912_intercon,
1472 ARRAY_SIZE(wm8912_intercon)); 1472 ARRAY_SIZE(wm8912_intercon));
1473 break; 1473 break;
1474 } 1474 }
1475 1475
1476 snd_soc_dapm_new_widgets(codec); 1476 snd_soc_dapm_new_widgets(dapm);
1477 return 0; 1477 return 0;
1478} 1478}
1479 1479
@@ -1589,7 +1589,7 @@ static int wm8904_hw_params(struct snd_pcm_substream *substream,
1589 - wm8904->fs); 1589 - wm8904->fs);
1590 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { 1590 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1591 cur_val = abs((wm8904->sysclk_rate / 1591 cur_val = abs((wm8904->sysclk_rate /
1592 clk_sys_rates[i].ratio) - wm8904->fs);; 1592 clk_sys_rates[i].ratio) - wm8904->fs);
1593 if (cur_val < best_val) { 1593 if (cur_val < best_val) {
1594 best = i; 1594 best = i;
1595 best_val = cur_val; 1595 best_val = cur_val;
@@ -2138,7 +2138,7 @@ static int wm8904_set_bias_level(struct snd_soc_codec *codec,
2138 break; 2138 break;
2139 2139
2140 case SND_SOC_BIAS_STANDBY: 2140 case SND_SOC_BIAS_STANDBY:
2141 if (codec->bias_level == SND_SOC_BIAS_OFF) { 2141 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2142 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), 2142 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
2143 wm8904->supplies); 2143 wm8904->supplies);
2144 if (ret != 0) { 2144 if (ret != 0) {
@@ -2197,7 +2197,7 @@ static int wm8904_set_bias_level(struct snd_soc_codec *codec,
2197 wm8904->supplies); 2197 wm8904->supplies);
2198 break; 2198 break;
2199 } 2199 }
2200 codec->bias_level = level; 2200 codec->dapm.bias_level = level;
2201 return 0; 2201 return 0;
2202} 2202}
2203 2203
@@ -2373,7 +2373,7 @@ static int wm8904_probe(struct snd_soc_codec *codec)
2373 int ret, i; 2373 int ret, i;
2374 2374
2375 codec->cache_sync = 1; 2375 codec->cache_sync = 1;
2376 codec->idle_bias_off = 1; 2376 codec->dapm.idle_bias_off = 1;
2377 2377
2378 switch (wm8904->devtype) { 2378 switch (wm8904->devtype) {
2379 case WM8904: 2379 case WM8904:
diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c
index 23086e2c976a..25580e3ee7c4 100644
--- a/sound/soc/codecs/wm8940.c
+++ b/sound/soc/codecs/wm8940.c
@@ -35,7 +35,6 @@
35#include <sound/pcm.h> 35#include <sound/pcm.h>
36#include <sound/pcm_params.h> 36#include <sound/pcm_params.h>
37#include <sound/soc.h> 37#include <sound/soc.h>
38#include <sound/soc-dapm.h>
39#include <sound/initval.h> 38#include <sound/initval.h>
40#include <sound/tlv.h> 39#include <sound/tlv.h>
41 40
@@ -43,7 +42,6 @@
43 42
44struct wm8940_priv { 43struct wm8940_priv {
45 unsigned int sysclk; 44 unsigned int sysclk;
46 u16 reg_cache[WM8940_CACHEREGNUM];
47 enum snd_soc_control_type control_type; 45 enum snd_soc_control_type control_type;
48 void *control_data; 46 void *control_data;
49}; 47};
@@ -291,13 +289,14 @@ static const struct snd_soc_dapm_route audio_map[] = {
291 289
292static int wm8940_add_widgets(struct snd_soc_codec *codec) 290static int wm8940_add_widgets(struct snd_soc_codec *codec)
293{ 291{
292 struct snd_soc_dapm_context *dapm = &codec->dapm;
294 int ret; 293 int ret;
295 294
296 ret = snd_soc_dapm_new_controls(codec, wm8940_dapm_widgets, 295 ret = snd_soc_dapm_new_controls(dapm, wm8940_dapm_widgets,
297 ARRAY_SIZE(wm8940_dapm_widgets)); 296 ARRAY_SIZE(wm8940_dapm_widgets));
298 if (ret) 297 if (ret)
299 goto error_ret; 298 goto error_ret;
300 ret = snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 299 ret = snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
301 if (ret) 300 if (ret)
302 goto error_ret; 301 goto error_ret;
303 302
@@ -735,7 +734,6 @@ static int wm8940_probe(struct snd_soc_codec *codec)
735 return ret; 734 return ret;
736 735
737 return ret; 736 return ret;
738;
739} 737}
740 738
741static int wm8940_remove(struct snd_soc_codec *codec) 739static int wm8940_remove(struct snd_soc_codec *codec)
diff --git a/sound/soc/codecs/wm8955.c b/sound/soc/codecs/wm8955.c
index 2ac35b0be86a..7167dfc96aa7 100644
--- a/sound/soc/codecs/wm8955.c
+++ b/sound/soc/codecs/wm8955.c
@@ -23,7 +23,6 @@
23#include <sound/pcm.h> 23#include <sound/pcm.h>
24#include <sound/pcm_params.h> 24#include <sound/pcm_params.h>
25#include <sound/soc.h> 25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h> 26#include <sound/initval.h>
28#include <sound/tlv.h> 27#include <sound/tlv.h>
29#include <sound/wm8955.h> 28#include <sound/wm8955.h>
@@ -576,13 +575,14 @@ static const struct snd_soc_dapm_route wm8955_intercon[] = {
576 575
577static int wm8955_add_widgets(struct snd_soc_codec *codec) 576static int wm8955_add_widgets(struct snd_soc_codec *codec)
578{ 577{
578 struct snd_soc_dapm_context *dapm = &codec->dapm;
579
579 snd_soc_add_controls(codec, wm8955_snd_controls, 580 snd_soc_add_controls(codec, wm8955_snd_controls,
580 ARRAY_SIZE(wm8955_snd_controls)); 581 ARRAY_SIZE(wm8955_snd_controls));
581 582
582 snd_soc_dapm_new_controls(codec, wm8955_dapm_widgets, 583 snd_soc_dapm_new_controls(dapm, wm8955_dapm_widgets,
583 ARRAY_SIZE(wm8955_dapm_widgets)); 584 ARRAY_SIZE(wm8955_dapm_widgets));
584 585 snd_soc_dapm_add_routes(dapm, wm8955_intercon,
585 snd_soc_dapm_add_routes(codec, wm8955_intercon,
586 ARRAY_SIZE(wm8955_intercon)); 586 ARRAY_SIZE(wm8955_intercon));
587 587
588 return 0; 588 return 0;
@@ -786,7 +786,7 @@ static int wm8955_set_bias_level(struct snd_soc_codec *codec,
786 break; 786 break;
787 787
788 case SND_SOC_BIAS_STANDBY: 788 case SND_SOC_BIAS_STANDBY:
789 if (codec->bias_level == SND_SOC_BIAS_OFF) { 789 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
790 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies), 790 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
791 wm8955->supplies); 791 wm8955->supplies);
792 if (ret != 0) { 792 if (ret != 0) {
@@ -850,7 +850,7 @@ static int wm8955_set_bias_level(struct snd_soc_codec *codec,
850 wm8955->supplies); 850 wm8955->supplies);
851 break; 851 break;
852 } 852 }
853 codec->bias_level = level; 853 codec->dapm.bias_level = level;
854 return 0; 854 return 0;
855} 855}
856 856
diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c
index ff6ff2f529d2..4393394b7bc1 100644
--- a/sound/soc/codecs/wm8960.c
+++ b/sound/soc/codecs/wm8960.c
@@ -20,7 +20,6 @@
20#include <sound/pcm.h> 20#include <sound/pcm.h>
21#include <sound/pcm_params.h> 21#include <sound/pcm_params.h>
22#include <sound/soc.h> 22#include <sound/soc.h>
23#include <sound/soc-dapm.h>
24#include <sound/initval.h> 23#include <sound/initval.h>
25#include <sound/tlv.h> 24#include <sound/tlv.h>
26#include <sound/wm8960.h> 25#include <sound/wm8960.h>
@@ -72,7 +71,6 @@ static const u16 wm8960_reg[WM8960_CACHEREGNUM] = {
72}; 71};
73 72
74struct wm8960_priv { 73struct wm8960_priv {
75 u16 reg_cache[WM8960_CACHEREGNUM];
76 enum snd_soc_control_type control_type; 74 enum snd_soc_control_type control_type;
77 void *control_data; 75 void *control_data;
78 int (*set_bias_level)(struct snd_soc_codec *, 76 int (*set_bias_level)(struct snd_soc_codec *,
@@ -389,27 +387,28 @@ static int wm8960_add_widgets(struct snd_soc_codec *codec)
389{ 387{
390 struct wm8960_data *pdata = codec->dev->platform_data; 388 struct wm8960_data *pdata = codec->dev->platform_data;
391 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); 389 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
390 struct snd_soc_dapm_context *dapm = &codec->dapm;
392 struct snd_soc_dapm_widget *w; 391 struct snd_soc_dapm_widget *w;
393 392
394 snd_soc_dapm_new_controls(codec, wm8960_dapm_widgets, 393 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets,
395 ARRAY_SIZE(wm8960_dapm_widgets)); 394 ARRAY_SIZE(wm8960_dapm_widgets));
396 395
397 snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths)); 396 snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
398 397
399 /* In capless mode OUT3 is used to provide VMID for the 398 /* In capless mode OUT3 is used to provide VMID for the
400 * headphone outputs, otherwise it is used as a mono mixer. 399 * headphone outputs, otherwise it is used as a mono mixer.
401 */ 400 */
402 if (pdata && pdata->capless) { 401 if (pdata && pdata->capless) {
403 snd_soc_dapm_new_controls(codec, wm8960_dapm_widgets_capless, 402 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_capless,
404 ARRAY_SIZE(wm8960_dapm_widgets_capless)); 403 ARRAY_SIZE(wm8960_dapm_widgets_capless));
405 404
406 snd_soc_dapm_add_routes(codec, audio_paths_capless, 405 snd_soc_dapm_add_routes(dapm, audio_paths_capless,
407 ARRAY_SIZE(audio_paths_capless)); 406 ARRAY_SIZE(audio_paths_capless));
408 } else { 407 } else {
409 snd_soc_dapm_new_controls(codec, wm8960_dapm_widgets_out3, 408 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_out3,
410 ARRAY_SIZE(wm8960_dapm_widgets_out3)); 409 ARRAY_SIZE(wm8960_dapm_widgets_out3));
411 410
412 snd_soc_dapm_add_routes(codec, audio_paths_out3, 411 snd_soc_dapm_add_routes(dapm, audio_paths_out3,
413 ARRAY_SIZE(audio_paths_out3)); 412 ARRAY_SIZE(audio_paths_out3));
414 } 413 }
415 414
@@ -418,7 +417,9 @@ static int wm8960_add_widgets(struct snd_soc_codec *codec)
418 * list each time to find the desired power state do so now 417 * list each time to find the desired power state do so now
419 * and save the result. 418 * and save the result.
420 */ 419 */
421 list_for_each_entry(w, &codec->dapm_widgets, list) { 420 list_for_each_entry(w, &codec->card->widgets, list) {
421 if (w->dapm != &codec->dapm)
422 continue;
422 if (strcmp(w->name, "LOUT1 PGA") == 0) 423 if (strcmp(w->name, "LOUT1 PGA") == 0)
423 wm8960->lout1 = w; 424 wm8960->lout1 = w;
424 if (strcmp(w->name, "ROUT1 PGA") == 0) 425 if (strcmp(w->name, "ROUT1 PGA") == 0)
@@ -573,7 +574,7 @@ static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec,
573 break; 574 break;
574 575
575 case SND_SOC_BIAS_STANDBY: 576 case SND_SOC_BIAS_STANDBY:
576 if (codec->bias_level == SND_SOC_BIAS_OFF) { 577 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
577 /* Enable anti-pop features */ 578 /* Enable anti-pop features */
578 snd_soc_write(codec, WM8960_APOP1, 579 snd_soc_write(codec, WM8960_APOP1,
579 WM8960_POBCTRL | WM8960_SOFT_ST | 580 WM8960_POBCTRL | WM8960_SOFT_ST |
@@ -611,7 +612,7 @@ static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec,
611 break; 612 break;
612 } 613 }
613 614
614 codec->bias_level = level; 615 codec->dapm.bias_level = level;
615 616
616 return 0; 617 return 0;
617} 618}
@@ -627,7 +628,7 @@ static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec,
627 break; 628 break;
628 629
629 case SND_SOC_BIAS_PREPARE: 630 case SND_SOC_BIAS_PREPARE:
630 switch (codec->bias_level) { 631 switch (codec->dapm.bias_level) {
631 case SND_SOC_BIAS_STANDBY: 632 case SND_SOC_BIAS_STANDBY:
632 /* Enable anti pop mode */ 633 /* Enable anti pop mode */
633 snd_soc_update_bits(codec, WM8960_APOP1, 634 snd_soc_update_bits(codec, WM8960_APOP1,
@@ -682,7 +683,7 @@ static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec,
682 break; 683 break;
683 684
684 case SND_SOC_BIAS_STANDBY: 685 case SND_SOC_BIAS_STANDBY:
685 switch (codec->bias_level) { 686 switch (codec->dapm.bias_level) {
686 case SND_SOC_BIAS_PREPARE: 687 case SND_SOC_BIAS_PREPARE:
687 /* Disable HP discharge */ 688 /* Disable HP discharge */
688 snd_soc_update_bits(codec, WM8960_APOP2, 689 snd_soc_update_bits(codec, WM8960_APOP2,
@@ -706,7 +707,7 @@ static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec,
706 break; 707 break;
707 } 708 }
708 709
709 codec->bias_level = level; 710 codec->dapm.bias_level = level;
710 711
711 return 0; 712 return 0;
712} 713}
diff --git a/sound/soc/codecs/wm8961.c b/sound/soc/codecs/wm8961.c
index 8340485c9851..55252e7d02c9 100644
--- a/sound/soc/codecs/wm8961.c
+++ b/sound/soc/codecs/wm8961.c
@@ -23,7 +23,6 @@
23#include <sound/pcm.h> 23#include <sound/pcm.h>
24#include <sound/pcm_params.h> 24#include <sound/pcm_params.h>
25#include <sound/soc.h> 25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h> 26#include <sound/initval.h>
28#include <sound/tlv.h> 27#include <sound/tlv.h>
29 28
@@ -290,7 +289,6 @@ static u16 wm8961_reg_defaults[] = {
290struct wm8961_priv { 289struct wm8961_priv {
291 enum snd_soc_control_type control_type; 290 enum snd_soc_control_type control_type;
292 int sysclk; 291 int sysclk;
293 u16 reg_cache[WM8961_MAX_REGISTER];
294}; 292};
295 293
296static int wm8961_volatile_register(unsigned int reg) 294static int wm8961_volatile_register(unsigned int reg)
@@ -882,7 +880,7 @@ static int wm8961_set_bias_level(struct snd_soc_codec *codec,
882 break; 880 break;
883 881
884 case SND_SOC_BIAS_PREPARE: 882 case SND_SOC_BIAS_PREPARE:
885 if (codec->bias_level == SND_SOC_BIAS_STANDBY) { 883 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
886 /* Enable bias generation */ 884 /* Enable bias generation */
887 reg = snd_soc_read(codec, WM8961_ANTI_POP); 885 reg = snd_soc_read(codec, WM8961_ANTI_POP);
888 reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN; 886 reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
@@ -897,7 +895,7 @@ static int wm8961_set_bias_level(struct snd_soc_codec *codec,
897 break; 895 break;
898 896
899 case SND_SOC_BIAS_STANDBY: 897 case SND_SOC_BIAS_STANDBY:
900 if (codec->bias_level == SND_SOC_BIAS_PREPARE) { 898 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) {
901 /* VREF off */ 899 /* VREF off */
902 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1); 900 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
903 reg &= ~WM8961_VREF; 901 reg &= ~WM8961_VREF;
@@ -919,7 +917,7 @@ static int wm8961_set_bias_level(struct snd_soc_codec *codec,
919 break; 917 break;
920 } 918 }
921 919
922 codec->bias_level = level; 920 codec->dapm.bias_level = level;
923 921
924 return 0; 922 return 0;
925} 923}
@@ -959,6 +957,7 @@ static struct snd_soc_dai_driver wm8961_dai = {
959 957
960static int wm8961_probe(struct snd_soc_codec *codec) 958static int wm8961_probe(struct snd_soc_codec *codec)
961{ 959{
960 struct snd_soc_dapm_context *dapm = &codec->dapm;
962 int ret = 0; 961 int ret = 0;
963 u16 reg; 962 u16 reg;
964 963
@@ -1024,9 +1023,9 @@ static int wm8961_probe(struct snd_soc_codec *codec)
1024 1023
1025 snd_soc_add_controls(codec, wm8961_snd_controls, 1024 snd_soc_add_controls(codec, wm8961_snd_controls,
1026 ARRAY_SIZE(wm8961_snd_controls)); 1025 ARRAY_SIZE(wm8961_snd_controls));
1027 snd_soc_dapm_new_controls(codec, wm8961_dapm_widgets, 1026 snd_soc_dapm_new_controls(dapm, wm8961_dapm_widgets,
1028 ARRAY_SIZE(wm8961_dapm_widgets)); 1027 ARRAY_SIZE(wm8961_dapm_widgets));
1029 snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths)); 1028 snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
1030 1029
1031 return 0; 1030 return 0;
1032} 1031}
diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c
index 7c421cc837bd..b9cb1fcf8c92 100644
--- a/sound/soc/codecs/wm8962.c
+++ b/sound/soc/codecs/wm8962.c
@@ -29,10 +29,10 @@
29#include <sound/pcm.h> 29#include <sound/pcm.h>
30#include <sound/pcm_params.h> 30#include <sound/pcm_params.h>
31#include <sound/soc.h> 31#include <sound/soc.h>
32#include <sound/soc-dapm.h>
33#include <sound/initval.h> 32#include <sound/initval.h>
34#include <sound/tlv.h> 33#include <sound/tlv.h>
35#include <sound/wm8962.h> 34#include <sound/wm8962.h>
35#include <trace/events/asoc.h>
36 36
37#include "wm8962.h" 37#include "wm8962.h"
38 38
@@ -1956,7 +1956,7 @@ static int wm8962_readable_register(unsigned int reg)
1956 1956
1957static int wm8962_reset(struct snd_soc_codec *codec) 1957static int wm8962_reset(struct snd_soc_codec *codec)
1958{ 1958{
1959 return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0); 1959 return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0x6243);
1960} 1960}
1961 1961
1962static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0); 1962static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
@@ -2677,6 +2677,7 @@ static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2677static int wm8962_add_widgets(struct snd_soc_codec *codec) 2677static int wm8962_add_widgets(struct snd_soc_codec *codec)
2678{ 2678{
2679 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev); 2679 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
2680 struct snd_soc_dapm_context *dapm = &codec->dapm;
2680 2681
2681 snd_soc_add_controls(codec, wm8962_snd_controls, 2682 snd_soc_add_controls(codec, wm8962_snd_controls,
2682 ARRAY_SIZE(wm8962_snd_controls)); 2683 ARRAY_SIZE(wm8962_snd_controls));
@@ -2688,26 +2689,26 @@ static int wm8962_add_widgets(struct snd_soc_codec *codec)
2688 ARRAY_SIZE(wm8962_spk_stereo_controls)); 2689 ARRAY_SIZE(wm8962_spk_stereo_controls));
2689 2690
2690 2691
2691 snd_soc_dapm_new_controls(codec, wm8962_dapm_widgets, 2692 snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
2692 ARRAY_SIZE(wm8962_dapm_widgets)); 2693 ARRAY_SIZE(wm8962_dapm_widgets));
2693 if (pdata && pdata->spk_mono) 2694 if (pdata && pdata->spk_mono)
2694 snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_mono_widgets, 2695 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
2695 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets)); 2696 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2696 else 2697 else
2697 snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_stereo_widgets, 2698 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
2698 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets)); 2699 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2699 2700
2700 snd_soc_dapm_add_routes(codec, wm8962_intercon, 2701 snd_soc_dapm_add_routes(dapm, wm8962_intercon,
2701 ARRAY_SIZE(wm8962_intercon)); 2702 ARRAY_SIZE(wm8962_intercon));
2702 if (pdata && pdata->spk_mono) 2703 if (pdata && pdata->spk_mono)
2703 snd_soc_dapm_add_routes(codec, wm8962_spk_mono_intercon, 2704 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
2704 ARRAY_SIZE(wm8962_spk_mono_intercon)); 2705 ARRAY_SIZE(wm8962_spk_mono_intercon));
2705 else 2706 else
2706 snd_soc_dapm_add_routes(codec, wm8962_spk_stereo_intercon, 2707 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
2707 ARRAY_SIZE(wm8962_spk_stereo_intercon)); 2708 ARRAY_SIZE(wm8962_spk_stereo_intercon));
2708 2709
2709 2710
2710 snd_soc_dapm_disable_pin(codec, "Beep"); 2711 snd_soc_dapm_disable_pin(dapm, "Beep");
2711 2712
2712 return 0; 2713 return 0;
2713} 2714}
@@ -2814,7 +2815,7 @@ static int wm8962_set_bias_level(struct snd_soc_codec *codec,
2814 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 2815 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2815 int ret; 2816 int ret;
2816 2817
2817 if (level == codec->bias_level) 2818 if (level == codec->dapm.bias_level)
2818 return 0; 2819 return 0;
2819 2820
2820 switch (level) { 2821 switch (level) {
@@ -2828,7 +2829,7 @@ static int wm8962_set_bias_level(struct snd_soc_codec *codec,
2828 break; 2829 break;
2829 2830
2830 case SND_SOC_BIAS_STANDBY: 2831 case SND_SOC_BIAS_STANDBY:
2831 if (codec->bias_level == SND_SOC_BIAS_OFF) { 2832 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2832 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), 2833 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
2833 wm8962->supplies); 2834 wm8962->supplies);
2834 if (ret != 0) { 2835 if (ret != 0) {
@@ -2878,7 +2879,7 @@ static int wm8962_set_bias_level(struct snd_soc_codec *codec,
2878 wm8962->supplies); 2879 wm8962->supplies);
2879 break; 2880 break;
2880 } 2881 }
2881 codec->bias_level = level; 2882 codec->dapm.bias_level = level;
2882 return 0; 2883 return 0;
2883} 2884}
2884 2885
@@ -3348,6 +3349,12 @@ static irqreturn_t wm8962_irq(int irq, void *data)
3348 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { 3349 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
3349 dev_dbg(codec->dev, "Microphone event detected\n"); 3350 dev_dbg(codec->dev, "Microphone event detected\n");
3350 3351
3352#ifndef CONFIG_SND_SOC_WM8962_MODULE
3353 trace_snd_soc_jack_irq(dev_name(codec->dev));
3354#endif
3355
3356 pm_wakeup_event(codec->dev, 300);
3357
3351 schedule_delayed_work(&wm8962->mic_work, 3358 schedule_delayed_work(&wm8962->mic_work,
3352 msecs_to_jiffies(250)); 3359 msecs_to_jiffies(250));
3353 } 3360 }
@@ -3433,6 +3440,7 @@ static void wm8962_beep_work(struct work_struct *work)
3433 struct wm8962_priv *wm8962 = 3440 struct wm8962_priv *wm8962 =
3434 container_of(work, struct wm8962_priv, beep_work); 3441 container_of(work, struct wm8962_priv, beep_work);
3435 struct snd_soc_codec *codec = wm8962->codec; 3442 struct snd_soc_codec *codec = wm8962->codec;
3443 struct snd_soc_dapm_context *dapm = &codec->dapm;
3436 int i; 3444 int i;
3437 int reg = 0; 3445 int reg = 0;
3438 int best = 0; 3446 int best = 0;
@@ -3449,16 +3457,16 @@ static void wm8962_beep_work(struct work_struct *work)
3449 3457
3450 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT); 3458 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3451 3459
3452 snd_soc_dapm_enable_pin(codec, "Beep"); 3460 snd_soc_dapm_enable_pin(dapm, "Beep");
3453 } else { 3461 } else {
3454 dev_dbg(codec->dev, "Disabling beep\n"); 3462 dev_dbg(codec->dev, "Disabling beep\n");
3455 snd_soc_dapm_disable_pin(codec, "Beep"); 3463 snd_soc_dapm_disable_pin(dapm, "Beep");
3456 } 3464 }
3457 3465
3458 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, 3466 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
3459 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg); 3467 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3460 3468
3461 snd_soc_dapm_sync(codec); 3469 snd_soc_dapm_sync(dapm);
3462} 3470}
3463 3471
3464/* For usability define a way of injecting beep events for the device - 3472/* For usability define a way of injecting beep events for the device -
@@ -3706,7 +3714,7 @@ static int wm8962_probe(struct snd_soc_codec *codec)
3706 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work); 3714 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3707 3715
3708 codec->cache_sync = 1; 3716 codec->cache_sync = 1;
3709 codec->idle_bias_off = 1; 3717 codec->dapm.idle_bias_off = 1;
3710 3718
3711 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C); 3719 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
3712 if (ret != 0) { 3720 if (ret != 0) {
@@ -3865,7 +3873,6 @@ err_enable:
3865err_get: 3873err_get:
3866 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); 3874 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3867err: 3875err:
3868 kfree(wm8962);
3869 return ret; 3876 return ret;
3870} 3877}
3871 3878
diff --git a/sound/soc/codecs/wm8971.c b/sound/soc/codecs/wm8971.c
index 9f18db6e167c..572bb80627a4 100644
--- a/sound/soc/codecs/wm8971.c
+++ b/sound/soc/codecs/wm8971.c
@@ -25,7 +25,6 @@
25#include <sound/pcm.h> 25#include <sound/pcm.h>
26#include <sound/pcm_params.h> 26#include <sound/pcm_params.h>
27#include <sound/soc.h> 27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h> 28#include <sound/initval.h>
30 29
31#include "wm8971.h" 30#include "wm8971.h"
@@ -333,10 +332,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
333 332
334static int wm8971_add_widgets(struct snd_soc_codec *codec) 333static int wm8971_add_widgets(struct snd_soc_codec *codec)
335{ 334{
336 snd_soc_dapm_new_controls(codec, wm8971_dapm_widgets, 335 struct snd_soc_dapm_context *dapm = &codec->dapm;
337 ARRAY_SIZE(wm8971_dapm_widgets));
338 336
339 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 337 snd_soc_dapm_new_controls(dapm, wm8971_dapm_widgets,
338 ARRAY_SIZE(wm8971_dapm_widgets));
339 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
340 340
341 return 0; 341 return 0;
342} 342}
@@ -553,7 +553,7 @@ static int wm8971_set_bias_level(struct snd_soc_codec *codec,
553 snd_soc_write(codec, WM8971_PWR1, 0x0001); 553 snd_soc_write(codec, WM8971_PWR1, 0x0001);
554 break; 554 break;
555 } 555 }
556 codec->bias_level = level; 556 codec->dapm.bias_level = level;
557 return 0; 557 return 0;
558} 558}
559 559
@@ -590,9 +590,11 @@ static struct snd_soc_dai_driver wm8971_dai = {
590 590
591static void wm8971_work(struct work_struct *work) 591static void wm8971_work(struct work_struct *work)
592{ 592{
593 struct snd_soc_codec *codec = 593 struct snd_soc_dapm_context *dapm =
594 container_of(work, struct snd_soc_codec, delayed_work.work); 594 container_of(work, struct snd_soc_dapm_context,
595 wm8971_set_bias_level(codec, codec->bias_level); 595 delayed_work.work);
596 struct snd_soc_codec *codec = dapm->codec;
597 wm8971_set_bias_level(codec, codec->dapm.bias_level);
596} 598}
597 599
598static int wm8971_suspend(struct snd_soc_codec *codec, pm_message_t state) 600static int wm8971_suspend(struct snd_soc_codec *codec, pm_message_t state)
@@ -620,11 +622,11 @@ static int wm8971_resume(struct snd_soc_codec *codec)
620 wm8971_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 622 wm8971_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
621 623
622 /* charge wm8971 caps */ 624 /* charge wm8971 caps */
623 if (codec->suspend_bias_level == SND_SOC_BIAS_ON) { 625 if (codec->dapm.suspend_bias_level == SND_SOC_BIAS_ON) {
624 reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e; 626 reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e;
625 snd_soc_write(codec, WM8971_PWR1, reg | 0x01c0); 627 snd_soc_write(codec, WM8971_PWR1, reg | 0x01c0);
626 codec->bias_level = SND_SOC_BIAS_ON; 628 codec->dapm.bias_level = SND_SOC_BIAS_ON;
627 queue_delayed_work(wm8971_workq, &codec->delayed_work, 629 queue_delayed_work(wm8971_workq, &codec->dapm.delayed_work,
628 msecs_to_jiffies(1000)); 630 msecs_to_jiffies(1000));
629 } 631 }
630 632
@@ -643,7 +645,7 @@ static int wm8971_probe(struct snd_soc_codec *codec)
643 return ret; 645 return ret;
644 } 646 }
645 647
646 INIT_DELAYED_WORK(&codec->delayed_work, wm8971_work); 648 INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8971_work);
647 wm8971_workq = create_workqueue("wm8971"); 649 wm8971_workq = create_workqueue("wm8971");
648 if (wm8971_workq == NULL) 650 if (wm8971_workq == NULL)
649 return -ENOMEM; 651 return -ENOMEM;
@@ -653,8 +655,8 @@ static int wm8971_probe(struct snd_soc_codec *codec)
653 /* charge output caps - set vmid to 5k for quick power up */ 655 /* charge output caps - set vmid to 5k for quick power up */
654 reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e; 656 reg = snd_soc_read(codec, WM8971_PWR1) & 0xfe3e;
655 snd_soc_write(codec, WM8971_PWR1, reg | 0x01c0); 657 snd_soc_write(codec, WM8971_PWR1, reg | 0x01c0);
656 codec->bias_level = SND_SOC_BIAS_STANDBY; 658 codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
657 queue_delayed_work(wm8971_workq, &codec->delayed_work, 659 queue_delayed_work(wm8971_workq, &codec->dapm.delayed_work,
658 msecs_to_jiffies(1000)); 660 msecs_to_jiffies(1000));
659 661
660 /* set the update bits */ 662 /* set the update bits */
diff --git a/sound/soc/codecs/wm8974.c b/sound/soc/codecs/wm8974.c
index b4363f6d19b3..ca646a822444 100644
--- a/sound/soc/codecs/wm8974.c
+++ b/sound/soc/codecs/wm8974.c
@@ -23,7 +23,6 @@
23#include <sound/pcm.h> 23#include <sound/pcm.h>
24#include <sound/pcm_params.h> 24#include <sound/pcm_params.h>
25#include <sound/soc.h> 25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h> 26#include <sound/initval.h>
28#include <sound/tlv.h> 27#include <sound/tlv.h>
29 28
@@ -52,7 +51,6 @@ static const u16 wm8974_reg[WM8974_CACHEREGNUM] = {
52 51
53struct wm8974_priv { 52struct wm8974_priv {
54 enum snd_soc_control_type control_type; 53 enum snd_soc_control_type control_type;
55 u16 reg_cache[WM8974_CACHEREGNUM];
56}; 54};
57 55
58#define wm8974_reset(c) snd_soc_write(c, WM8974_RESET, 0) 56#define wm8974_reset(c) snd_soc_write(c, WM8974_RESET, 0)
@@ -274,10 +272,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
274 272
275static int wm8974_add_widgets(struct snd_soc_codec *codec) 273static int wm8974_add_widgets(struct snd_soc_codec *codec)
276{ 274{
277 snd_soc_dapm_new_controls(codec, wm8974_dapm_widgets, 275 struct snd_soc_dapm_context *dapm = &codec->dapm;
278 ARRAY_SIZE(wm8974_dapm_widgets));
279 276
280 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 277 snd_soc_dapm_new_controls(dapm, wm8974_dapm_widgets,
278 ARRAY_SIZE(wm8974_dapm_widgets));
279 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
281 280
282 return 0; 281 return 0;
283} 282}
@@ -530,7 +529,7 @@ static int wm8974_set_bias_level(struct snd_soc_codec *codec,
530 case SND_SOC_BIAS_STANDBY: 529 case SND_SOC_BIAS_STANDBY:
531 power1 |= WM8974_POWER1_BIASEN | WM8974_POWER1_BUFIOEN; 530 power1 |= WM8974_POWER1_BIASEN | WM8974_POWER1_BUFIOEN;
532 531
533 if (codec->bias_level == SND_SOC_BIAS_OFF) { 532 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
534 /* Initial cap charge at VMID 5k */ 533 /* Initial cap charge at VMID 5k */
535 snd_soc_write(codec, WM8974_POWER1, power1 | 0x3); 534 snd_soc_write(codec, WM8974_POWER1, power1 | 0x3);
536 mdelay(100); 535 mdelay(100);
@@ -547,7 +546,7 @@ static int wm8974_set_bias_level(struct snd_soc_codec *codec,
547 break; 546 break;
548 } 547 }
549 548
550 codec->bias_level = level; 549 codec->dapm.bias_level = level;
551 return 0; 550 return 0;
552} 551}
553 552
diff --git a/sound/soc/codecs/wm8978.c b/sound/soc/codecs/wm8978.c
index 13b979a71a7c..4bbc3442703f 100644
--- a/sound/soc/codecs/wm8978.c
+++ b/sound/soc/codecs/wm8978.c
@@ -24,7 +24,6 @@
24#include <sound/pcm.h> 24#include <sound/pcm.h>
25#include <sound/pcm_params.h> 25#include <sound/pcm_params.h>
26#include <sound/soc.h> 26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h> 27#include <sound/initval.h>
29#include <sound/tlv.h> 28#include <sound/tlv.h>
30#include <asm/div64.h> 29#include <asm/div64.h>
@@ -60,7 +59,6 @@ struct wm8978_priv {
60 unsigned int f_opclk; 59 unsigned int f_opclk;
61 int mclk_idx; 60 int mclk_idx;
62 enum wm8978_sysclk_src sysclk; 61 enum wm8978_sysclk_src sysclk;
63 u16 reg_cache[WM8978_CACHEREGNUM];
64}; 62};
65 63
66static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"}; 64static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"};
@@ -355,11 +353,12 @@ static const struct snd_soc_dapm_route audio_map[] = {
355 353
356static int wm8978_add_widgets(struct snd_soc_codec *codec) 354static int wm8978_add_widgets(struct snd_soc_codec *codec)
357{ 355{
358 snd_soc_dapm_new_controls(codec, wm8978_dapm_widgets, 356 struct snd_soc_dapm_context *dapm = &codec->dapm;
359 ARRAY_SIZE(wm8978_dapm_widgets));
360 357
358 snd_soc_dapm_new_controls(dapm, wm8978_dapm_widgets,
359 ARRAY_SIZE(wm8978_dapm_widgets));
361 /* set up the WM8978 audio map */ 360 /* set up the WM8978 audio map */
362 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 361 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
363 362
364 return 0; 363 return 0;
365} 364}
@@ -837,7 +836,7 @@ static int wm8978_set_bias_level(struct snd_soc_codec *codec,
837 /* bit 3: enable bias, bit 2: enable I/O tie off buffer */ 836 /* bit 3: enable bias, bit 2: enable I/O tie off buffer */
838 power1 |= 0xc; 837 power1 |= 0xc;
839 838
840 if (codec->bias_level == SND_SOC_BIAS_OFF) { 839 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
841 /* Initial cap charge at VMID 5k */ 840 /* Initial cap charge at VMID 5k */
842 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, 841 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1,
843 power1 | 0x3); 842 power1 | 0x3);
@@ -857,7 +856,7 @@ static int wm8978_set_bias_level(struct snd_soc_codec *codec,
857 856
858 dev_dbg(codec->dev, "%s: %d, %x\n", __func__, level, power1); 857 dev_dbg(codec->dev, "%s: %d, %x\n", __func__, level, power1);
859 858
860 codec->bias_level = level; 859 codec->dapm.bias_level = level;
861 return 0; 860 return 0;
862} 861}
863 862
diff --git a/sound/soc/codecs/wm8985.c b/sound/soc/codecs/wm8985.c
index fd2e7cca1228..bae510acdec8 100644
--- a/sound/soc/codecs/wm8985.c
+++ b/sound/soc/codecs/wm8985.c
@@ -26,7 +26,6 @@
26#include <sound/pcm.h> 26#include <sound/pcm.h>
27#include <sound/pcm_params.h> 27#include <sound/pcm_params.h>
28#include <sound/soc.h> 28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h> 29#include <sound/initval.h>
31#include <sound/tlv.h> 30#include <sound/tlv.h>
32 31
@@ -533,10 +532,11 @@ static int eqmode_put(struct snd_kcontrol *kcontrol,
533 532
534static int wm8985_add_widgets(struct snd_soc_codec *codec) 533static int wm8985_add_widgets(struct snd_soc_codec *codec)
535{ 534{
536 snd_soc_dapm_new_controls(codec, wm8985_dapm_widgets, 535 struct snd_soc_dapm_context *dapm = &codec->dapm;
537 ARRAY_SIZE(wm8985_dapm_widgets));
538 536
539 snd_soc_dapm_add_routes(codec, audio_map, 537 snd_soc_dapm_new_controls(dapm, wm8985_dapm_widgets,
538 ARRAY_SIZE(wm8985_dapm_widgets));
539 snd_soc_dapm_add_routes(dapm, audio_map,
540 ARRAY_SIZE(audio_map)); 540 ARRAY_SIZE(audio_map));
541 return 0; 541 return 0;
542} 542}
@@ -879,7 +879,7 @@ static int wm8985_set_bias_level(struct snd_soc_codec *codec,
879 1 << WM8985_VMIDSEL_SHIFT); 879 1 << WM8985_VMIDSEL_SHIFT);
880 break; 880 break;
881 case SND_SOC_BIAS_STANDBY: 881 case SND_SOC_BIAS_STANDBY:
882 if (codec->bias_level == SND_SOC_BIAS_OFF) { 882 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
883 ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies), 883 ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
884 wm8985->supplies); 884 wm8985->supplies);
885 if (ret) { 885 if (ret) {
@@ -939,7 +939,7 @@ static int wm8985_set_bias_level(struct snd_soc_codec *codec,
939 break; 939 break;
940 } 940 }
941 941
942 codec->bias_level = level; 942 codec->dapm.bias_level = level;
943 return 0; 943 return 0;
944} 944}
945 945
diff --git a/sound/soc/codecs/wm8988.c b/sound/soc/codecs/wm8988.c
index d7f259711970..d7170f1381aa 100644
--- a/sound/soc/codecs/wm8988.c
+++ b/sound/soc/codecs/wm8988.c
@@ -25,7 +25,6 @@
25#include <sound/pcm_params.h> 25#include <sound/pcm_params.h>
26#include <sound/tlv.h> 26#include <sound/tlv.h>
27#include <sound/soc.h> 27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h> 28#include <sound/initval.h>
30 29
31#include "wm8988.h" 30#include "wm8988.h"
@@ -54,7 +53,6 @@ struct wm8988_priv {
54 unsigned int sysclk; 53 unsigned int sysclk;
55 enum snd_soc_control_type control_type; 54 enum snd_soc_control_type control_type;
56 struct snd_pcm_hw_constraint_list *sysclk_constraints; 55 struct snd_pcm_hw_constraint_list *sysclk_constraints;
57 u16 reg_cache[WM8988_NUM_REG];
58}; 56};
59 57
60 58
@@ -677,7 +675,7 @@ static int wm8988_set_bias_level(struct snd_soc_codec *codec,
677 break; 675 break;
678 676
679 case SND_SOC_BIAS_STANDBY: 677 case SND_SOC_BIAS_STANDBY:
680 if (codec->bias_level == SND_SOC_BIAS_OFF) { 678 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
681 /* VREF, VMID=2x5k */ 679 /* VREF, VMID=2x5k */
682 snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x1c1); 680 snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x1c1);
683 681
@@ -693,7 +691,7 @@ static int wm8988_set_bias_level(struct snd_soc_codec *codec,
693 snd_soc_write(codec, WM8988_PWR1, 0x0000); 691 snd_soc_write(codec, WM8988_PWR1, 0x0000);
694 break; 692 break;
695 } 693 }
696 codec->bias_level = level; 694 codec->dapm.bias_level = level;
697 return 0; 695 return 0;
698} 696}
699 697
@@ -759,6 +757,7 @@ static int wm8988_resume(struct snd_soc_codec *codec)
759static int wm8988_probe(struct snd_soc_codec *codec) 757static int wm8988_probe(struct snd_soc_codec *codec)
760{ 758{
761 struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec); 759 struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
760 struct snd_soc_dapm_context *dapm = &codec->dapm;
762 int ret = 0; 761 int ret = 0;
763 u16 reg; 762 u16 reg;
764 763
@@ -790,9 +789,9 @@ static int wm8988_probe(struct snd_soc_codec *codec)
790 789
791 snd_soc_add_controls(codec, wm8988_snd_controls, 790 snd_soc_add_controls(codec, wm8988_snd_controls,
792 ARRAY_SIZE(wm8988_snd_controls)); 791 ARRAY_SIZE(wm8988_snd_controls));
793 snd_soc_dapm_new_controls(codec, wm8988_dapm_widgets, 792 snd_soc_dapm_new_controls(dapm, wm8988_dapm_widgets,
794 ARRAY_SIZE(wm8988_dapm_widgets)); 793 ARRAY_SIZE(wm8988_dapm_widgets));
795 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 794 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
796 795
797 return 0; 796 return 0;
798} 797}
diff --git a/sound/soc/codecs/wm8990.c b/sound/soc/codecs/wm8990.c
index 264828e4e67c..5c87a634fc04 100644
--- a/sound/soc/codecs/wm8990.c
+++ b/sound/soc/codecs/wm8990.c
@@ -23,7 +23,6 @@
23#include <sound/pcm.h> 23#include <sound/pcm.h>
24#include <sound/pcm_params.h> 24#include <sound/pcm_params.h>
25#include <sound/soc.h> 25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h> 26#include <sound/initval.h>
28#include <sound/tlv.h> 27#include <sound/tlv.h>
29#include <asm/div64.h> 28#include <asm/div64.h>
@@ -914,11 +913,12 @@ static const struct snd_soc_dapm_route audio_map[] = {
914 913
915static int wm8990_add_widgets(struct snd_soc_codec *codec) 914static int wm8990_add_widgets(struct snd_soc_codec *codec)
916{ 915{
917 snd_soc_dapm_new_controls(codec, wm8990_dapm_widgets, 916 struct snd_soc_dapm_context *dapm = &codec->dapm;
918 ARRAY_SIZE(wm8990_dapm_widgets));
919 917
918 snd_soc_dapm_new_controls(dapm, wm8990_dapm_widgets,
919 ARRAY_SIZE(wm8990_dapm_widgets));
920 /* set up the WM8990 audio map */ 920 /* set up the WM8990 audio map */
921 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 921 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
922 922
923 return 0; 923 return 0;
924} 924}
@@ -1170,7 +1170,7 @@ static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1170 break; 1170 break;
1171 1171
1172 case SND_SOC_BIAS_STANDBY: 1172 case SND_SOC_BIAS_STANDBY:
1173 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1173 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1174 /* Enable all output discharge bits */ 1174 /* Enable all output discharge bits */
1175 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE | 1175 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1176 WM8990_DIS_RLINE | WM8990_DIS_OUT3 | 1176 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
@@ -1266,7 +1266,7 @@ static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1266 break; 1266 break;
1267 } 1267 }
1268 1268
1269 codec->bias_level = level; 1269 codec->dapm.bias_level = level;
1270 return 0; 1270 return 0;
1271} 1271}
1272 1272
diff --git a/sound/soc/codecs/wm8993.c b/sound/soc/codecs/wm8993.c
index 589e3fa24734..18c0d9ce7c32 100644
--- a/sound/soc/codecs/wm8993.c
+++ b/sound/soc/codecs/wm8993.c
@@ -24,7 +24,6 @@
24#include <sound/pcm_params.h> 24#include <sound/pcm_params.h>
25#include <sound/tlv.h> 25#include <sound/tlv.h>
26#include <sound/soc.h> 26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h> 27#include <sound/initval.h>
29#include <sound/wm8993.h> 28#include <sound/wm8993.h>
30 29
@@ -226,7 +225,6 @@ static struct {
226 225
227struct wm8993_priv { 226struct wm8993_priv {
228 struct wm_hubs_data hubs_data; 227 struct wm_hubs_data hubs_data;
229 u16 reg_cache[WM8993_REGISTER_COUNT];
230 struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES]; 228 struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES];
231 struct wm8993_platform_data pdata; 229 struct wm8993_platform_data pdata;
232 enum snd_soc_control_type control_type; 230 enum snd_soc_control_type control_type;
@@ -735,6 +733,7 @@ static int class_w_put(struct snd_kcontrol *kcontrol,
735 0); 733 0);
736 } 734 }
737 wm8993->class_w_users++; 735 wm8993->class_w_users++;
736 wm8993->hubs_data.class_w = true;
738 } 737 }
739 738
740 /* Implement the change */ 739 /* Implement the change */
@@ -751,6 +750,7 @@ static int class_w_put(struct snd_kcontrol *kcontrol,
751 WM8993_CP_DYN_V); 750 WM8993_CP_DYN_V);
752 } 751 }
753 wm8993->class_w_users--; 752 wm8993->class_w_users--;
753 wm8993->hubs_data.class_w = false;
754 } 754 }
755 755
756 dev_dbg(codec->dev, "Indirect DAC use count now %d\n", 756 dev_dbg(codec->dev, "Indirect DAC use count now %d\n",
@@ -968,7 +968,7 @@ static int wm8993_set_bias_level(struct snd_soc_codec *codec,
968 break; 968 break;
969 969
970 case SND_SOC_BIAS_STANDBY: 970 case SND_SOC_BIAS_STANDBY:
971 if (codec->bias_level == SND_SOC_BIAS_OFF) { 971 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
972 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies), 972 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
973 wm8993->supplies); 973 wm8993->supplies);
974 if (ret != 0) 974 if (ret != 0)
@@ -1029,6 +1029,12 @@ static int wm8993_set_bias_level(struct snd_soc_codec *codec,
1029 WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA, 1029 WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
1030 0); 1030 0);
1031 1031
1032 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1033 WM8993_STARTUP_BIAS_ENA |
1034 WM8993_VMID_BUF_ENA |
1035 WM8993_VMID_RAMP_MASK |
1036 WM8993_BIAS_SRC, 0);
1037
1032#ifdef CONFIG_REGULATOR 1038#ifdef CONFIG_REGULATOR
1033 /* Post 2.6.34 we will be able to get a callback when 1039 /* Post 2.6.34 we will be able to get a callback when
1034 * the regulators are disabled which we can use but 1040 * the regulators are disabled which we can use but
@@ -1043,7 +1049,7 @@ static int wm8993_set_bias_level(struct snd_soc_codec *codec,
1043 break; 1049 break;
1044 } 1050 }
1045 1051
1046 codec->bias_level = level; 1052 codec->dapm.bias_level = level;
1047 1053
1048 return 0; 1054 return 0;
1049} 1055}
@@ -1225,7 +1231,7 @@ static int wm8993_hw_params(struct snd_pcm_substream *substream,
1225 - wm8993->fs); 1231 - wm8993->fs);
1226 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { 1232 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1227 cur_val = abs((wm8993->sysclk_rate / 1233 cur_val = abs((wm8993->sysclk_rate /
1228 clk_sys_rates[i].ratio) - wm8993->fs);; 1234 clk_sys_rates[i].ratio) - wm8993->fs);
1229 if (cur_val < best_val) { 1235 if (cur_val < best_val) {
1230 best = i; 1236 best = i;
1231 best_val = cur_val; 1237 best_val = cur_val;
@@ -1422,6 +1428,7 @@ static struct snd_soc_dai_driver wm8993_dai = {
1422static int wm8993_probe(struct snd_soc_codec *codec) 1428static int wm8993_probe(struct snd_soc_codec *codec)
1423{ 1429{
1424 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); 1430 struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1431 struct snd_soc_dapm_context *dapm = &codec->dapm;
1425 int ret, i, val; 1432 int ret, i, val;
1426 1433
1427 wm8993->hubs_data.hp_startup_mode = 1; 1434 wm8993->hubs_data.hp_startup_mode = 1;
@@ -1503,11 +1510,11 @@ static int wm8993_probe(struct snd_soc_codec *codec)
1503 ARRAY_SIZE(wm8993_eq_controls)); 1510 ARRAY_SIZE(wm8993_eq_controls));
1504 } 1511 }
1505 1512
1506 snd_soc_dapm_new_controls(codec, wm8993_dapm_widgets, 1513 snd_soc_dapm_new_controls(dapm, wm8993_dapm_widgets,
1507 ARRAY_SIZE(wm8993_dapm_widgets)); 1514 ARRAY_SIZE(wm8993_dapm_widgets));
1508 wm_hubs_add_analogue_controls(codec); 1515 wm_hubs_add_analogue_controls(codec);
1509 1516
1510 snd_soc_dapm_add_routes(codec, routes, ARRAY_SIZE(routes)); 1517 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
1511 wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff, 1518 wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff,
1512 wm8993->pdata.lineout2_diff); 1519 wm8993->pdata.lineout2_diff);
1513 1520
diff --git a/sound/soc/codecs/wm8994-tables.c b/sound/soc/codecs/wm8994-tables.c
new file mode 100644
index 000000000000..68e9b024dd48
--- /dev/null
+++ b/sound/soc/codecs/wm8994-tables.c
@@ -0,0 +1,3147 @@
1#include "wm8994.h"
2
3const struct wm8994_access_mask wm8994_access_masks[WM8994_CACHE_SIZE] = {
4 { 0xFFFF, 0xFFFF }, /* R0 - Software Reset */
5 { 0x3B37, 0x3B37 }, /* R1 - Power Management (1) */
6 { 0x6BF0, 0x6BF0 }, /* R2 - Power Management (2) */
7 { 0x3FF0, 0x3FF0 }, /* R3 - Power Management (3) */
8 { 0x3F3F, 0x3F3F }, /* R4 - Power Management (4) */
9 { 0x3F0F, 0x3F0F }, /* R5 - Power Management (5) */
10 { 0x003F, 0x003F }, /* R6 - Power Management (6) */
11 { 0x0000, 0x0000 }, /* R7 */
12 { 0x0000, 0x0000 }, /* R8 */
13 { 0x0000, 0x0000 }, /* R9 */
14 { 0x0000, 0x0000 }, /* R10 */
15 { 0x0000, 0x0000 }, /* R11 */
16 { 0x0000, 0x0000 }, /* R12 */
17 { 0x0000, 0x0000 }, /* R13 */
18 { 0x0000, 0x0000 }, /* R14 */
19 { 0x0000, 0x0000 }, /* R15 */
20 { 0x0000, 0x0000 }, /* R16 */
21 { 0x0000, 0x0000 }, /* R17 */
22 { 0x0000, 0x0000 }, /* R18 */
23 { 0x0000, 0x0000 }, /* R19 */
24 { 0x0000, 0x0000 }, /* R20 */
25 { 0x01C0, 0x01C0 }, /* R21 - Input Mixer (1) */
26 { 0x0000, 0x0000 }, /* R22 */
27 { 0x0000, 0x0000 }, /* R23 */
28 { 0x00DF, 0x01DF }, /* R24 - Left Line Input 1&2 Volume */
29 { 0x00DF, 0x01DF }, /* R25 - Left Line Input 3&4 Volume */
30 { 0x00DF, 0x01DF }, /* R26 - Right Line Input 1&2 Volume */
31 { 0x00DF, 0x01DF }, /* R27 - Right Line Input 3&4 Volume */
32 { 0x00FF, 0x01FF }, /* R28 - Left Output Volume */
33 { 0x00FF, 0x01FF }, /* R29 - Right Output Volume */
34 { 0x0077, 0x0077 }, /* R30 - Line Outputs Volume */
35 { 0x0030, 0x0030 }, /* R31 - HPOUT2 Volume */
36 { 0x00FF, 0x01FF }, /* R32 - Left OPGA Volume */
37 { 0x00FF, 0x01FF }, /* R33 - Right OPGA Volume */
38 { 0x007F, 0x007F }, /* R34 - SPKMIXL Attenuation */
39 { 0x017F, 0x017F }, /* R35 - SPKMIXR Attenuation */
40 { 0x003F, 0x003F }, /* R36 - SPKOUT Mixers */
41 { 0x003F, 0x003F }, /* R37 - ClassD */
42 { 0x00FF, 0x01FF }, /* R38 - Speaker Volume Left */
43 { 0x00FF, 0x01FF }, /* R39 - Speaker Volume Right */
44 { 0x00FF, 0x00FF }, /* R40 - Input Mixer (2) */
45 { 0x01B7, 0x01B7 }, /* R41 - Input Mixer (3) */
46 { 0x01B7, 0x01B7 }, /* R42 - Input Mixer (4) */
47 { 0x01C7, 0x01C7 }, /* R43 - Input Mixer (5) */
48 { 0x01C7, 0x01C7 }, /* R44 - Input Mixer (6) */
49 { 0x01FF, 0x01FF }, /* R45 - Output Mixer (1) */
50 { 0x01FF, 0x01FF }, /* R46 - Output Mixer (2) */
51 { 0x0FFF, 0x0FFF }, /* R47 - Output Mixer (3) */
52 { 0x0FFF, 0x0FFF }, /* R48 - Output Mixer (4) */
53 { 0x0FFF, 0x0FFF }, /* R49 - Output Mixer (5) */
54 { 0x0FFF, 0x0FFF }, /* R50 - Output Mixer (6) */
55 { 0x0038, 0x0038 }, /* R51 - HPOUT2 Mixer */
56 { 0x0077, 0x0077 }, /* R52 - Line Mixer (1) */
57 { 0x0077, 0x0077 }, /* R53 - Line Mixer (2) */
58 { 0x03FF, 0x03FF }, /* R54 - Speaker Mixer */
59 { 0x00C1, 0x00C1 }, /* R55 - Additional Control */
60 { 0x00F0, 0x00F0 }, /* R56 - AntiPOP (1) */
61 { 0x01EF, 0x01EF }, /* R57 - AntiPOP (2) */
62 { 0x00FF, 0x00FF }, /* R58 - MICBIAS */
63 { 0x000F, 0x000F }, /* R59 - LDO 1 */
64 { 0x0007, 0x0007 }, /* R60 - LDO 2 */
65 { 0x0000, 0x0000 }, /* R61 */
66 { 0x0000, 0x0000 }, /* R62 */
67 { 0x0000, 0x0000 }, /* R63 */
68 { 0x0000, 0x0000 }, /* R64 */
69 { 0x0000, 0x0000 }, /* R65 */
70 { 0x0000, 0x0000 }, /* R66 */
71 { 0x0000, 0x0000 }, /* R67 */
72 { 0x0000, 0x0000 }, /* R68 */
73 { 0x0000, 0x0000 }, /* R69 */
74 { 0x0000, 0x0000 }, /* R70 */
75 { 0x0000, 0x0000 }, /* R71 */
76 { 0x0000, 0x0000 }, /* R72 */
77 { 0x0000, 0x0000 }, /* R73 */
78 { 0x0000, 0x0000 }, /* R74 */
79 { 0x0000, 0x0000 }, /* R75 */
80 { 0x8000, 0x8000 }, /* R76 - Charge Pump (1) */
81 { 0x0000, 0x0000 }, /* R77 */
82 { 0x0000, 0x0000 }, /* R78 */
83 { 0x0000, 0x0000 }, /* R79 */
84 { 0x0000, 0x0000 }, /* R80 */
85 { 0x0301, 0x0301 }, /* R81 - Class W (1) */
86 { 0x0000, 0x0000 }, /* R82 */
87 { 0x0000, 0x0000 }, /* R83 */
88 { 0x333F, 0x333F }, /* R84 - DC Servo (1) */
89 { 0x0FEF, 0x0FEF }, /* R85 - DC Servo (2) */
90 { 0x0000, 0x0000 }, /* R86 */
91 { 0xFFFF, 0xFFFF }, /* R87 - DC Servo (4) */
92 { 0x0333, 0x0000 }, /* R88 - DC Servo Readback */
93 { 0x0000, 0x0000 }, /* R89 */
94 { 0x0000, 0x0000 }, /* R90 */
95 { 0x0000, 0x0000 }, /* R91 */
96 { 0x0000, 0x0000 }, /* R92 */
97 { 0x0000, 0x0000 }, /* R93 */
98 { 0x0000, 0x0000 }, /* R94 */
99 { 0x0000, 0x0000 }, /* R95 */
100 { 0x00EE, 0x00EE }, /* R96 - Analogue HP (1) */
101 { 0x0000, 0x0000 }, /* R97 */
102 { 0x0000, 0x0000 }, /* R98 */
103 { 0x0000, 0x0000 }, /* R99 */
104 { 0x0000, 0x0000 }, /* R100 */
105 { 0x0000, 0x0000 }, /* R101 */
106 { 0x0000, 0x0000 }, /* R102 */
107 { 0x0000, 0x0000 }, /* R103 */
108 { 0x0000, 0x0000 }, /* R104 */
109 { 0x0000, 0x0000 }, /* R105 */
110 { 0x0000, 0x0000 }, /* R106 */
111 { 0x0000, 0x0000 }, /* R107 */
112 { 0x0000, 0x0000 }, /* R108 */
113 { 0x0000, 0x0000 }, /* R109 */
114 { 0x0000, 0x0000 }, /* R110 */
115 { 0x0000, 0x0000 }, /* R111 */
116 { 0x0000, 0x0000 }, /* R112 */
117 { 0x0000, 0x0000 }, /* R113 */
118 { 0x0000, 0x0000 }, /* R114 */
119 { 0x0000, 0x0000 }, /* R115 */
120 { 0x0000, 0x0000 }, /* R116 */
121 { 0x0000, 0x0000 }, /* R117 */
122 { 0x0000, 0x0000 }, /* R118 */
123 { 0x0000, 0x0000 }, /* R119 */
124 { 0x0000, 0x0000 }, /* R120 */
125 { 0x0000, 0x0000 }, /* R121 */
126 { 0x0000, 0x0000 }, /* R122 */
127 { 0x0000, 0x0000 }, /* R123 */
128 { 0x0000, 0x0000 }, /* R124 */
129 { 0x0000, 0x0000 }, /* R125 */
130 { 0x0000, 0x0000 }, /* R126 */
131 { 0x0000, 0x0000 }, /* R127 */
132 { 0x0000, 0x0000 }, /* R128 */
133 { 0x0000, 0x0000 }, /* R129 */
134 { 0x0000, 0x0000 }, /* R130 */
135 { 0x0000, 0x0000 }, /* R131 */
136 { 0x0000, 0x0000 }, /* R132 */
137 { 0x0000, 0x0000 }, /* R133 */
138 { 0x0000, 0x0000 }, /* R134 */
139 { 0x0000, 0x0000 }, /* R135 */
140 { 0x0000, 0x0000 }, /* R136 */
141 { 0x0000, 0x0000 }, /* R137 */
142 { 0x0000, 0x0000 }, /* R138 */
143 { 0x0000, 0x0000 }, /* R139 */
144 { 0x0000, 0x0000 }, /* R140 */
145 { 0x0000, 0x0000 }, /* R141 */
146 { 0x0000, 0x0000 }, /* R142 */
147 { 0x0000, 0x0000 }, /* R143 */
148 { 0x0000, 0x0000 }, /* R144 */
149 { 0x0000, 0x0000 }, /* R145 */
150 { 0x0000, 0x0000 }, /* R146 */
151 { 0x0000, 0x0000 }, /* R147 */
152 { 0x0000, 0x0000 }, /* R148 */
153 { 0x0000, 0x0000 }, /* R149 */
154 { 0x0000, 0x0000 }, /* R150 */
155 { 0x0000, 0x0000 }, /* R151 */
156 { 0x0000, 0x0000 }, /* R152 */
157 { 0x0000, 0x0000 }, /* R153 */
158 { 0x0000, 0x0000 }, /* R154 */
159 { 0x0000, 0x0000 }, /* R155 */
160 { 0x0000, 0x0000 }, /* R156 */
161 { 0x0000, 0x0000 }, /* R157 */
162 { 0x0000, 0x0000 }, /* R158 */
163 { 0x0000, 0x0000 }, /* R159 */
164 { 0x0000, 0x0000 }, /* R160 */
165 { 0x0000, 0x0000 }, /* R161 */
166 { 0x0000, 0x0000 }, /* R162 */
167 { 0x0000, 0x0000 }, /* R163 */
168 { 0x0000, 0x0000 }, /* R164 */
169 { 0x0000, 0x0000 }, /* R165 */
170 { 0x0000, 0x0000 }, /* R166 */
171 { 0x0000, 0x0000 }, /* R167 */
172 { 0x0000, 0x0000 }, /* R168 */
173 { 0x0000, 0x0000 }, /* R169 */
174 { 0x0000, 0x0000 }, /* R170 */
175 { 0x0000, 0x0000 }, /* R171 */
176 { 0x0000, 0x0000 }, /* R172 */
177 { 0x0000, 0x0000 }, /* R173 */
178 { 0x0000, 0x0000 }, /* R174 */
179 { 0x0000, 0x0000 }, /* R175 */
180 { 0x0000, 0x0000 }, /* R176 */
181 { 0x0000, 0x0000 }, /* R177 */
182 { 0x0000, 0x0000 }, /* R178 */
183 { 0x0000, 0x0000 }, /* R179 */
184 { 0x0000, 0x0000 }, /* R180 */
185 { 0x0000, 0x0000 }, /* R181 */
186 { 0x0000, 0x0000 }, /* R182 */
187 { 0x0000, 0x0000 }, /* R183 */
188 { 0x0000, 0x0000 }, /* R184 */
189 { 0x0000, 0x0000 }, /* R185 */
190 { 0x0000, 0x0000 }, /* R186 */
191 { 0x0000, 0x0000 }, /* R187 */
192 { 0x0000, 0x0000 }, /* R188 */
193 { 0x0000, 0x0000 }, /* R189 */
194 { 0x0000, 0x0000 }, /* R190 */
195 { 0x0000, 0x0000 }, /* R191 */
196 { 0x0000, 0x0000 }, /* R192 */
197 { 0x0000, 0x0000 }, /* R193 */
198 { 0x0000, 0x0000 }, /* R194 */
199 { 0x0000, 0x0000 }, /* R195 */
200 { 0x0000, 0x0000 }, /* R196 */
201 { 0x0000, 0x0000 }, /* R197 */
202 { 0x0000, 0x0000 }, /* R198 */
203 { 0x0000, 0x0000 }, /* R199 */
204 { 0x0000, 0x0000 }, /* R200 */
205 { 0x0000, 0x0000 }, /* R201 */
206 { 0x0000, 0x0000 }, /* R202 */
207 { 0x0000, 0x0000 }, /* R203 */
208 { 0x0000, 0x0000 }, /* R204 */
209 { 0x0000, 0x0000 }, /* R205 */
210 { 0x0000, 0x0000 }, /* R206 */
211 { 0x0000, 0x0000 }, /* R207 */
212 { 0x0000, 0x0000 }, /* R208 */
213 { 0x0000, 0x0000 }, /* R209 */
214 { 0x0000, 0x0000 }, /* R210 */
215 { 0x0000, 0x0000 }, /* R211 */
216 { 0x0000, 0x0000 }, /* R212 */
217 { 0x0000, 0x0000 }, /* R213 */
218 { 0x0000, 0x0000 }, /* R214 */
219 { 0x0000, 0x0000 }, /* R215 */
220 { 0x0000, 0x0000 }, /* R216 */
221 { 0x0000, 0x0000 }, /* R217 */
222 { 0x0000, 0x0000 }, /* R218 */
223 { 0x0000, 0x0000 }, /* R219 */
224 { 0x0000, 0x0000 }, /* R220 */
225 { 0x0000, 0x0000 }, /* R221 */
226 { 0x0000, 0x0000 }, /* R222 */
227 { 0x0000, 0x0000 }, /* R223 */
228 { 0x0000, 0x0000 }, /* R224 */
229 { 0x0000, 0x0000 }, /* R225 */
230 { 0x0000, 0x0000 }, /* R226 */
231 { 0x0000, 0x0000 }, /* R227 */
232 { 0x0000, 0x0000 }, /* R228 */
233 { 0x0000, 0x0000 }, /* R229 */
234 { 0x0000, 0x0000 }, /* R230 */
235 { 0x0000, 0x0000 }, /* R231 */
236 { 0x0000, 0x0000 }, /* R232 */
237 { 0x0000, 0x0000 }, /* R233 */
238 { 0x0000, 0x0000 }, /* R234 */
239 { 0x0000, 0x0000 }, /* R235 */
240 { 0x0000, 0x0000 }, /* R236 */
241 { 0x0000, 0x0000 }, /* R237 */
242 { 0x0000, 0x0000 }, /* R238 */
243 { 0x0000, 0x0000 }, /* R239 */
244 { 0x0000, 0x0000 }, /* R240 */
245 { 0x0000, 0x0000 }, /* R241 */
246 { 0x0000, 0x0000 }, /* R242 */
247 { 0x0000, 0x0000 }, /* R243 */
248 { 0x0000, 0x0000 }, /* R244 */
249 { 0x0000, 0x0000 }, /* R245 */
250 { 0x0000, 0x0000 }, /* R246 */
251 { 0x0000, 0x0000 }, /* R247 */
252 { 0x0000, 0x0000 }, /* R248 */
253 { 0x0000, 0x0000 }, /* R249 */
254 { 0x0000, 0x0000 }, /* R250 */
255 { 0x0000, 0x0000 }, /* R251 */
256 { 0x0000, 0x0000 }, /* R252 */
257 { 0x0000, 0x0000 }, /* R253 */
258 { 0x0000, 0x0000 }, /* R254 */
259 { 0x0000, 0x0000 }, /* R255 */
260 { 0x000F, 0x0000 }, /* R256 - Chip Revision */
261 { 0x0074, 0x0074 }, /* R257 - Control Interface */
262 { 0x0000, 0x0000 }, /* R258 */
263 { 0x0000, 0x0000 }, /* R259 */
264 { 0x0000, 0x0000 }, /* R260 */
265 { 0x0000, 0x0000 }, /* R261 */
266 { 0x0000, 0x0000 }, /* R262 */
267 { 0x0000, 0x0000 }, /* R263 */
268 { 0x0000, 0x0000 }, /* R264 */
269 { 0x0000, 0x0000 }, /* R265 */
270 { 0x0000, 0x0000 }, /* R266 */
271 { 0x0000, 0x0000 }, /* R267 */
272 { 0x0000, 0x0000 }, /* R268 */
273 { 0x0000, 0x0000 }, /* R269 */
274 { 0x0000, 0x0000 }, /* R270 */
275 { 0x0000, 0x0000 }, /* R271 */
276 { 0x807F, 0x837F }, /* R272 - Write Sequencer Ctrl (1) */
277 { 0x017F, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
278 { 0x0000, 0x0000 }, /* R274 */
279 { 0x0000, 0x0000 }, /* R275 */
280 { 0x0000, 0x0000 }, /* R276 */
281 { 0x0000, 0x0000 }, /* R277 */
282 { 0x0000, 0x0000 }, /* R278 */
283 { 0x0000, 0x0000 }, /* R279 */
284 { 0x0000, 0x0000 }, /* R280 */
285 { 0x0000, 0x0000 }, /* R281 */
286 { 0x0000, 0x0000 }, /* R282 */
287 { 0x0000, 0x0000 }, /* R283 */
288 { 0x0000, 0x0000 }, /* R284 */
289 { 0x0000, 0x0000 }, /* R285 */
290 { 0x0000, 0x0000 }, /* R286 */
291 { 0x0000, 0x0000 }, /* R287 */
292 { 0x0000, 0x0000 }, /* R288 */
293 { 0x0000, 0x0000 }, /* R289 */
294 { 0x0000, 0x0000 }, /* R290 */
295 { 0x0000, 0x0000 }, /* R291 */
296 { 0x0000, 0x0000 }, /* R292 */
297 { 0x0000, 0x0000 }, /* R293 */
298 { 0x0000, 0x0000 }, /* R294 */
299 { 0x0000, 0x0000 }, /* R295 */
300 { 0x0000, 0x0000 }, /* R296 */
301 { 0x0000, 0x0000 }, /* R297 */
302 { 0x0000, 0x0000 }, /* R298 */
303 { 0x0000, 0x0000 }, /* R299 */
304 { 0x0000, 0x0000 }, /* R300 */
305 { 0x0000, 0x0000 }, /* R301 */
306 { 0x0000, 0x0000 }, /* R302 */
307 { 0x0000, 0x0000 }, /* R303 */
308 { 0x0000, 0x0000 }, /* R304 */
309 { 0x0000, 0x0000 }, /* R305 */
310 { 0x0000, 0x0000 }, /* R306 */
311 { 0x0000, 0x0000 }, /* R307 */
312 { 0x0000, 0x0000 }, /* R308 */
313 { 0x0000, 0x0000 }, /* R309 */
314 { 0x0000, 0x0000 }, /* R310 */
315 { 0x0000, 0x0000 }, /* R311 */
316 { 0x0000, 0x0000 }, /* R312 */
317 { 0x0000, 0x0000 }, /* R313 */
318 { 0x0000, 0x0000 }, /* R314 */
319 { 0x0000, 0x0000 }, /* R315 */
320 { 0x0000, 0x0000 }, /* R316 */
321 { 0x0000, 0x0000 }, /* R317 */
322 { 0x0000, 0x0000 }, /* R318 */
323 { 0x0000, 0x0000 }, /* R319 */
324 { 0x0000, 0x0000 }, /* R320 */
325 { 0x0000, 0x0000 }, /* R321 */
326 { 0x0000, 0x0000 }, /* R322 */
327 { 0x0000, 0x0000 }, /* R323 */
328 { 0x0000, 0x0000 }, /* R324 */
329 { 0x0000, 0x0000 }, /* R325 */
330 { 0x0000, 0x0000 }, /* R326 */
331 { 0x0000, 0x0000 }, /* R327 */
332 { 0x0000, 0x0000 }, /* R328 */
333 { 0x0000, 0x0000 }, /* R329 */
334 { 0x0000, 0x0000 }, /* R330 */
335 { 0x0000, 0x0000 }, /* R331 */
336 { 0x0000, 0x0000 }, /* R332 */
337 { 0x0000, 0x0000 }, /* R333 */
338 { 0x0000, 0x0000 }, /* R334 */
339 { 0x0000, 0x0000 }, /* R335 */
340 { 0x0000, 0x0000 }, /* R336 */
341 { 0x0000, 0x0000 }, /* R337 */
342 { 0x0000, 0x0000 }, /* R338 */
343 { 0x0000, 0x0000 }, /* R339 */
344 { 0x0000, 0x0000 }, /* R340 */
345 { 0x0000, 0x0000 }, /* R341 */
346 { 0x0000, 0x0000 }, /* R342 */
347 { 0x0000, 0x0000 }, /* R343 */
348 { 0x0000, 0x0000 }, /* R344 */
349 { 0x0000, 0x0000 }, /* R345 */
350 { 0x0000, 0x0000 }, /* R346 */
351 { 0x0000, 0x0000 }, /* R347 */
352 { 0x0000, 0x0000 }, /* R348 */
353 { 0x0000, 0x0000 }, /* R349 */
354 { 0x0000, 0x0000 }, /* R350 */
355 { 0x0000, 0x0000 }, /* R351 */
356 { 0x0000, 0x0000 }, /* R352 */
357 { 0x0000, 0x0000 }, /* R353 */
358 { 0x0000, 0x0000 }, /* R354 */
359 { 0x0000, 0x0000 }, /* R355 */
360 { 0x0000, 0x0000 }, /* R356 */
361 { 0x0000, 0x0000 }, /* R357 */
362 { 0x0000, 0x0000 }, /* R358 */
363 { 0x0000, 0x0000 }, /* R359 */
364 { 0x0000, 0x0000 }, /* R360 */
365 { 0x0000, 0x0000 }, /* R361 */
366 { 0x0000, 0x0000 }, /* R362 */
367 { 0x0000, 0x0000 }, /* R363 */
368 { 0x0000, 0x0000 }, /* R364 */
369 { 0x0000, 0x0000 }, /* R365 */
370 { 0x0000, 0x0000 }, /* R366 */
371 { 0x0000, 0x0000 }, /* R367 */
372 { 0x0000, 0x0000 }, /* R368 */
373 { 0x0000, 0x0000 }, /* R369 */
374 { 0x0000, 0x0000 }, /* R370 */
375 { 0x0000, 0x0000 }, /* R371 */
376 { 0x0000, 0x0000 }, /* R372 */
377 { 0x0000, 0x0000 }, /* R373 */
378 { 0x0000, 0x0000 }, /* R374 */
379 { 0x0000, 0x0000 }, /* R375 */
380 { 0x0000, 0x0000 }, /* R376 */
381 { 0x0000, 0x0000 }, /* R377 */
382 { 0x0000, 0x0000 }, /* R378 */
383 { 0x0000, 0x0000 }, /* R379 */
384 { 0x0000, 0x0000 }, /* R380 */
385 { 0x0000, 0x0000 }, /* R381 */
386 { 0x0000, 0x0000 }, /* R382 */
387 { 0x0000, 0x0000 }, /* R383 */
388 { 0x0000, 0x0000 }, /* R384 */
389 { 0x0000, 0x0000 }, /* R385 */
390 { 0x0000, 0x0000 }, /* R386 */
391 { 0x0000, 0x0000 }, /* R387 */
392 { 0x0000, 0x0000 }, /* R388 */
393 { 0x0000, 0x0000 }, /* R389 */
394 { 0x0000, 0x0000 }, /* R390 */
395 { 0x0000, 0x0000 }, /* R391 */
396 { 0x0000, 0x0000 }, /* R392 */
397 { 0x0000, 0x0000 }, /* R393 */
398 { 0x0000, 0x0000 }, /* R394 */
399 { 0x0000, 0x0000 }, /* R395 */
400 { 0x0000, 0x0000 }, /* R396 */
401 { 0x0000, 0x0000 }, /* R397 */
402 { 0x0000, 0x0000 }, /* R398 */
403 { 0x0000, 0x0000 }, /* R399 */
404 { 0x0000, 0x0000 }, /* R400 */
405 { 0x0000, 0x0000 }, /* R401 */
406 { 0x0000, 0x0000 }, /* R402 */
407 { 0x0000, 0x0000 }, /* R403 */
408 { 0x0000, 0x0000 }, /* R404 */
409 { 0x0000, 0x0000 }, /* R405 */
410 { 0x0000, 0x0000 }, /* R406 */
411 { 0x0000, 0x0000 }, /* R407 */
412 { 0x0000, 0x0000 }, /* R408 */
413 { 0x0000, 0x0000 }, /* R409 */
414 { 0x0000, 0x0000 }, /* R410 */
415 { 0x0000, 0x0000 }, /* R411 */
416 { 0x0000, 0x0000 }, /* R412 */
417 { 0x0000, 0x0000 }, /* R413 */
418 { 0x0000, 0x0000 }, /* R414 */
419 { 0x0000, 0x0000 }, /* R415 */
420 { 0x0000, 0x0000 }, /* R416 */
421 { 0x0000, 0x0000 }, /* R417 */
422 { 0x0000, 0x0000 }, /* R418 */
423 { 0x0000, 0x0000 }, /* R419 */
424 { 0x0000, 0x0000 }, /* R420 */
425 { 0x0000, 0x0000 }, /* R421 */
426 { 0x0000, 0x0000 }, /* R422 */
427 { 0x0000, 0x0000 }, /* R423 */
428 { 0x0000, 0x0000 }, /* R424 */
429 { 0x0000, 0x0000 }, /* R425 */
430 { 0x0000, 0x0000 }, /* R426 */
431 { 0x0000, 0x0000 }, /* R427 */
432 { 0x0000, 0x0000 }, /* R428 */
433 { 0x0000, 0x0000 }, /* R429 */
434 { 0x0000, 0x0000 }, /* R430 */
435 { 0x0000, 0x0000 }, /* R431 */
436 { 0x0000, 0x0000 }, /* R432 */
437 { 0x0000, 0x0000 }, /* R433 */
438 { 0x0000, 0x0000 }, /* R434 */
439 { 0x0000, 0x0000 }, /* R435 */
440 { 0x0000, 0x0000 }, /* R436 */
441 { 0x0000, 0x0000 }, /* R437 */
442 { 0x0000, 0x0000 }, /* R438 */
443 { 0x0000, 0x0000 }, /* R439 */
444 { 0x0000, 0x0000 }, /* R440 */
445 { 0x0000, 0x0000 }, /* R441 */
446 { 0x0000, 0x0000 }, /* R442 */
447 { 0x0000, 0x0000 }, /* R443 */
448 { 0x0000, 0x0000 }, /* R444 */
449 { 0x0000, 0x0000 }, /* R445 */
450 { 0x0000, 0x0000 }, /* R446 */
451 { 0x0000, 0x0000 }, /* R447 */
452 { 0x0000, 0x0000 }, /* R448 */
453 { 0x0000, 0x0000 }, /* R449 */
454 { 0x0000, 0x0000 }, /* R450 */
455 { 0x0000, 0x0000 }, /* R451 */
456 { 0x0000, 0x0000 }, /* R452 */
457 { 0x0000, 0x0000 }, /* R453 */
458 { 0x0000, 0x0000 }, /* R454 */
459 { 0x0000, 0x0000 }, /* R455 */
460 { 0x0000, 0x0000 }, /* R456 */
461 { 0x0000, 0x0000 }, /* R457 */
462 { 0x0000, 0x0000 }, /* R458 */
463 { 0x0000, 0x0000 }, /* R459 */
464 { 0x0000, 0x0000 }, /* R460 */
465 { 0x0000, 0x0000 }, /* R461 */
466 { 0x0000, 0x0000 }, /* R462 */
467 { 0x0000, 0x0000 }, /* R463 */
468 { 0x0000, 0x0000 }, /* R464 */
469 { 0x0000, 0x0000 }, /* R465 */
470 { 0x0000, 0x0000 }, /* R466 */
471 { 0x0000, 0x0000 }, /* R467 */
472 { 0x0000, 0x0000 }, /* R468 */
473 { 0x0000, 0x0000 }, /* R469 */
474 { 0x0000, 0x0000 }, /* R470 */
475 { 0x0000, 0x0000 }, /* R471 */
476 { 0x0000, 0x0000 }, /* R472 */
477 { 0x0000, 0x0000 }, /* R473 */
478 { 0x0000, 0x0000 }, /* R474 */
479 { 0x0000, 0x0000 }, /* R475 */
480 { 0x0000, 0x0000 }, /* R476 */
481 { 0x0000, 0x0000 }, /* R477 */
482 { 0x0000, 0x0000 }, /* R478 */
483 { 0x0000, 0x0000 }, /* R479 */
484 { 0x0000, 0x0000 }, /* R480 */
485 { 0x0000, 0x0000 }, /* R481 */
486 { 0x0000, 0x0000 }, /* R482 */
487 { 0x0000, 0x0000 }, /* R483 */
488 { 0x0000, 0x0000 }, /* R484 */
489 { 0x0000, 0x0000 }, /* R485 */
490 { 0x0000, 0x0000 }, /* R486 */
491 { 0x0000, 0x0000 }, /* R487 */
492 { 0x0000, 0x0000 }, /* R488 */
493 { 0x0000, 0x0000 }, /* R489 */
494 { 0x0000, 0x0000 }, /* R490 */
495 { 0x0000, 0x0000 }, /* R491 */
496 { 0x0000, 0x0000 }, /* R492 */
497 { 0x0000, 0x0000 }, /* R493 */
498 { 0x0000, 0x0000 }, /* R494 */
499 { 0x0000, 0x0000 }, /* R495 */
500 { 0x0000, 0x0000 }, /* R496 */
501 { 0x0000, 0x0000 }, /* R497 */
502 { 0x0000, 0x0000 }, /* R498 */
503 { 0x0000, 0x0000 }, /* R499 */
504 { 0x0000, 0x0000 }, /* R500 */
505 { 0x0000, 0x0000 }, /* R501 */
506 { 0x0000, 0x0000 }, /* R502 */
507 { 0x0000, 0x0000 }, /* R503 */
508 { 0x0000, 0x0000 }, /* R504 */
509 { 0x0000, 0x0000 }, /* R505 */
510 { 0x0000, 0x0000 }, /* R506 */
511 { 0x0000, 0x0000 }, /* R507 */
512 { 0x0000, 0x0000 }, /* R508 */
513 { 0x0000, 0x0000 }, /* R509 */
514 { 0x0000, 0x0000 }, /* R510 */
515 { 0x0000, 0x0000 }, /* R511 */
516 { 0x001F, 0x001F }, /* R512 - AIF1 Clocking (1) */
517 { 0x003F, 0x003F }, /* R513 - AIF1 Clocking (2) */
518 { 0x0000, 0x0000 }, /* R514 */
519 { 0x0000, 0x0000 }, /* R515 */
520 { 0x001F, 0x001F }, /* R516 - AIF2 Clocking (1) */
521 { 0x003F, 0x003F }, /* R517 - AIF2 Clocking (2) */
522 { 0x0000, 0x0000 }, /* R518 */
523 { 0x0000, 0x0000 }, /* R519 */
524 { 0x001F, 0x001F }, /* R520 - Clocking (1) */
525 { 0x0777, 0x0777 }, /* R521 - Clocking (2) */
526 { 0x0000, 0x0000 }, /* R522 */
527 { 0x0000, 0x0000 }, /* R523 */
528 { 0x0000, 0x0000 }, /* R524 */
529 { 0x0000, 0x0000 }, /* R525 */
530 { 0x0000, 0x0000 }, /* R526 */
531 { 0x0000, 0x0000 }, /* R527 */
532 { 0x00FF, 0x00FF }, /* R528 - AIF1 Rate */
533 { 0x00FF, 0x00FF }, /* R529 - AIF2 Rate */
534 { 0x000F, 0x0000 }, /* R530 - Rate Status */
535 { 0x0000, 0x0000 }, /* R531 */
536 { 0x0000, 0x0000 }, /* R532 */
537 { 0x0000, 0x0000 }, /* R533 */
538 { 0x0000, 0x0000 }, /* R534 */
539 { 0x0000, 0x0000 }, /* R535 */
540 { 0x0000, 0x0000 }, /* R536 */
541 { 0x0000, 0x0000 }, /* R537 */
542 { 0x0000, 0x0000 }, /* R538 */
543 { 0x0000, 0x0000 }, /* R539 */
544 { 0x0000, 0x0000 }, /* R540 */
545 { 0x0000, 0x0000 }, /* R541 */
546 { 0x0000, 0x0000 }, /* R542 */
547 { 0x0000, 0x0000 }, /* R543 */
548 { 0x0007, 0x0007 }, /* R544 - FLL1 Control (1) */
549 { 0x3F77, 0x3F77 }, /* R545 - FLL1 Control (2) */
550 { 0xFFFF, 0xFFFF }, /* R546 - FLL1 Control (3) */
551 { 0x7FEF, 0x7FEF }, /* R547 - FLL1 Control (4) */
552 { 0x1FDB, 0x1FDB }, /* R548 - FLL1 Control (5) */
553 { 0x0000, 0x0000 }, /* R549 */
554 { 0x0000, 0x0000 }, /* R550 */
555 { 0x0000, 0x0000 }, /* R551 */
556 { 0x0000, 0x0000 }, /* R552 */
557 { 0x0000, 0x0000 }, /* R553 */
558 { 0x0000, 0x0000 }, /* R554 */
559 { 0x0000, 0x0000 }, /* R555 */
560 { 0x0000, 0x0000 }, /* R556 */
561 { 0x0000, 0x0000 }, /* R557 */
562 { 0x0000, 0x0000 }, /* R558 */
563 { 0x0000, 0x0000 }, /* R559 */
564 { 0x0000, 0x0000 }, /* R560 */
565 { 0x0000, 0x0000 }, /* R561 */
566 { 0x0000, 0x0000 }, /* R562 */
567 { 0x0000, 0x0000 }, /* R563 */
568 { 0x0000, 0x0000 }, /* R564 */
569 { 0x0000, 0x0000 }, /* R565 */
570 { 0x0000, 0x0000 }, /* R566 */
571 { 0x0000, 0x0000 }, /* R567 */
572 { 0x0000, 0x0000 }, /* R568 */
573 { 0x0000, 0x0000 }, /* R569 */
574 { 0x0000, 0x0000 }, /* R570 */
575 { 0x0000, 0x0000 }, /* R571 */
576 { 0x0000, 0x0000 }, /* R572 */
577 { 0x0000, 0x0000 }, /* R573 */
578 { 0x0000, 0x0000 }, /* R574 */
579 { 0x0000, 0x0000 }, /* R575 */
580 { 0x0007, 0x0007 }, /* R576 - FLL2 Control (1) */
581 { 0x3F77, 0x3F77 }, /* R577 - FLL2 Control (2) */
582 { 0xFFFF, 0xFFFF }, /* R578 - FLL2 Control (3) */
583 { 0x7FEF, 0x7FEF }, /* R579 - FLL2 Control (4) */
584 { 0x1FDB, 0x1FDB }, /* R580 - FLL2 Control (5) */
585 { 0x0000, 0x0000 }, /* R581 */
586 { 0x0000, 0x0000 }, /* R582 */
587 { 0x0000, 0x0000 }, /* R583 */
588 { 0x0000, 0x0000 }, /* R584 */
589 { 0x0000, 0x0000 }, /* R585 */
590 { 0x0000, 0x0000 }, /* R586 */
591 { 0x0000, 0x0000 }, /* R587 */
592 { 0x0000, 0x0000 }, /* R588 */
593 { 0x0000, 0x0000 }, /* R589 */
594 { 0x0000, 0x0000 }, /* R590 */
595 { 0x0000, 0x0000 }, /* R591 */
596 { 0x0000, 0x0000 }, /* R592 */
597 { 0x0000, 0x0000 }, /* R593 */
598 { 0x0000, 0x0000 }, /* R594 */
599 { 0x0000, 0x0000 }, /* R595 */
600 { 0x0000, 0x0000 }, /* R596 */
601 { 0x0000, 0x0000 }, /* R597 */
602 { 0x0000, 0x0000 }, /* R598 */
603 { 0x0000, 0x0000 }, /* R599 */
604 { 0x0000, 0x0000 }, /* R600 */
605 { 0x0000, 0x0000 }, /* R601 */
606 { 0x0000, 0x0000 }, /* R602 */
607 { 0x0000, 0x0000 }, /* R603 */
608 { 0x0000, 0x0000 }, /* R604 */
609 { 0x0000, 0x0000 }, /* R605 */
610 { 0x0000, 0x0000 }, /* R606 */
611 { 0x0000, 0x0000 }, /* R607 */
612 { 0x0000, 0x0000 }, /* R608 */
613 { 0x0000, 0x0000 }, /* R609 */
614 { 0x0000, 0x0000 }, /* R610 */
615 { 0x0000, 0x0000 }, /* R611 */
616 { 0x0000, 0x0000 }, /* R612 */
617 { 0x0000, 0x0000 }, /* R613 */
618 { 0x0000, 0x0000 }, /* R614 */
619 { 0x0000, 0x0000 }, /* R615 */
620 { 0x0000, 0x0000 }, /* R616 */
621 { 0x0000, 0x0000 }, /* R617 */
622 { 0x0000, 0x0000 }, /* R618 */
623 { 0x0000, 0x0000 }, /* R619 */
624 { 0x0000, 0x0000 }, /* R620 */
625 { 0x0000, 0x0000 }, /* R621 */
626 { 0x0000, 0x0000 }, /* R622 */
627 { 0x0000, 0x0000 }, /* R623 */
628 { 0x0000, 0x0000 }, /* R624 */
629 { 0x0000, 0x0000 }, /* R625 */
630 { 0x0000, 0x0000 }, /* R626 */
631 { 0x0000, 0x0000 }, /* R627 */
632 { 0x0000, 0x0000 }, /* R628 */
633 { 0x0000, 0x0000 }, /* R629 */
634 { 0x0000, 0x0000 }, /* R630 */
635 { 0x0000, 0x0000 }, /* R631 */
636 { 0x0000, 0x0000 }, /* R632 */
637 { 0x0000, 0x0000 }, /* R633 */
638 { 0x0000, 0x0000 }, /* R634 */
639 { 0x0000, 0x0000 }, /* R635 */
640 { 0x0000, 0x0000 }, /* R636 */
641 { 0x0000, 0x0000 }, /* R637 */
642 { 0x0000, 0x0000 }, /* R638 */
643 { 0x0000, 0x0000 }, /* R639 */
644 { 0x0000, 0x0000 }, /* R640 */
645 { 0x0000, 0x0000 }, /* R641 */
646 { 0x0000, 0x0000 }, /* R642 */
647 { 0x0000, 0x0000 }, /* R643 */
648 { 0x0000, 0x0000 }, /* R644 */
649 { 0x0000, 0x0000 }, /* R645 */
650 { 0x0000, 0x0000 }, /* R646 */
651 { 0x0000, 0x0000 }, /* R647 */
652 { 0x0000, 0x0000 }, /* R648 */
653 { 0x0000, 0x0000 }, /* R649 */
654 { 0x0000, 0x0000 }, /* R650 */
655 { 0x0000, 0x0000 }, /* R651 */
656 { 0x0000, 0x0000 }, /* R652 */
657 { 0x0000, 0x0000 }, /* R653 */
658 { 0x0000, 0x0000 }, /* R654 */
659 { 0x0000, 0x0000 }, /* R655 */
660 { 0x0000, 0x0000 }, /* R656 */
661 { 0x0000, 0x0000 }, /* R657 */
662 { 0x0000, 0x0000 }, /* R658 */
663 { 0x0000, 0x0000 }, /* R659 */
664 { 0x0000, 0x0000 }, /* R660 */
665 { 0x0000, 0x0000 }, /* R661 */
666 { 0x0000, 0x0000 }, /* R662 */
667 { 0x0000, 0x0000 }, /* R663 */
668 { 0x0000, 0x0000 }, /* R664 */
669 { 0x0000, 0x0000 }, /* R665 */
670 { 0x0000, 0x0000 }, /* R666 */
671 { 0x0000, 0x0000 }, /* R667 */
672 { 0x0000, 0x0000 }, /* R668 */
673 { 0x0000, 0x0000 }, /* R669 */
674 { 0x0000, 0x0000 }, /* R670 */
675 { 0x0000, 0x0000 }, /* R671 */
676 { 0x0000, 0x0000 }, /* R672 */
677 { 0x0000, 0x0000 }, /* R673 */
678 { 0x0000, 0x0000 }, /* R674 */
679 { 0x0000, 0x0000 }, /* R675 */
680 { 0x0000, 0x0000 }, /* R676 */
681 { 0x0000, 0x0000 }, /* R677 */
682 { 0x0000, 0x0000 }, /* R678 */
683 { 0x0000, 0x0000 }, /* R679 */
684 { 0x0000, 0x0000 }, /* R680 */
685 { 0x0000, 0x0000 }, /* R681 */
686 { 0x0000, 0x0000 }, /* R682 */
687 { 0x0000, 0x0000 }, /* R683 */
688 { 0x0000, 0x0000 }, /* R684 */
689 { 0x0000, 0x0000 }, /* R685 */
690 { 0x0000, 0x0000 }, /* R686 */
691 { 0x0000, 0x0000 }, /* R687 */
692 { 0x0000, 0x0000 }, /* R688 */
693 { 0x0000, 0x0000 }, /* R689 */
694 { 0x0000, 0x0000 }, /* R690 */
695 { 0x0000, 0x0000 }, /* R691 */
696 { 0x0000, 0x0000 }, /* R692 */
697 { 0x0000, 0x0000 }, /* R693 */
698 { 0x0000, 0x0000 }, /* R694 */
699 { 0x0000, 0x0000 }, /* R695 */
700 { 0x0000, 0x0000 }, /* R696 */
701 { 0x0000, 0x0000 }, /* R697 */
702 { 0x0000, 0x0000 }, /* R698 */
703 { 0x0000, 0x0000 }, /* R699 */
704 { 0x0000, 0x0000 }, /* R700 */
705 { 0x0000, 0x0000 }, /* R701 */
706 { 0x0000, 0x0000 }, /* R702 */
707 { 0x0000, 0x0000 }, /* R703 */
708 { 0x0000, 0x0000 }, /* R704 */
709 { 0x0000, 0x0000 }, /* R705 */
710 { 0x0000, 0x0000 }, /* R706 */
711 { 0x0000, 0x0000 }, /* R707 */
712 { 0x0000, 0x0000 }, /* R708 */
713 { 0x0000, 0x0000 }, /* R709 */
714 { 0x0000, 0x0000 }, /* R710 */
715 { 0x0000, 0x0000 }, /* R711 */
716 { 0x0000, 0x0000 }, /* R712 */
717 { 0x0000, 0x0000 }, /* R713 */
718 { 0x0000, 0x0000 }, /* R714 */
719 { 0x0000, 0x0000 }, /* R715 */
720 { 0x0000, 0x0000 }, /* R716 */
721 { 0x0000, 0x0000 }, /* R717 */
722 { 0x0000, 0x0000 }, /* R718 */
723 { 0x0000, 0x0000 }, /* R719 */
724 { 0x0000, 0x0000 }, /* R720 */
725 { 0x0000, 0x0000 }, /* R721 */
726 { 0x0000, 0x0000 }, /* R722 */
727 { 0x0000, 0x0000 }, /* R723 */
728 { 0x0000, 0x0000 }, /* R724 */
729 { 0x0000, 0x0000 }, /* R725 */
730 { 0x0000, 0x0000 }, /* R726 */
731 { 0x0000, 0x0000 }, /* R727 */
732 { 0x0000, 0x0000 }, /* R728 */
733 { 0x0000, 0x0000 }, /* R729 */
734 { 0x0000, 0x0000 }, /* R730 */
735 { 0x0000, 0x0000 }, /* R731 */
736 { 0x0000, 0x0000 }, /* R732 */
737 { 0x0000, 0x0000 }, /* R733 */
738 { 0x0000, 0x0000 }, /* R734 */
739 { 0x0000, 0x0000 }, /* R735 */
740 { 0x0000, 0x0000 }, /* R736 */
741 { 0x0000, 0x0000 }, /* R737 */
742 { 0x0000, 0x0000 }, /* R738 */
743 { 0x0000, 0x0000 }, /* R739 */
744 { 0x0000, 0x0000 }, /* R740 */
745 { 0x0000, 0x0000 }, /* R741 */
746 { 0x0000, 0x0000 }, /* R742 */
747 { 0x0000, 0x0000 }, /* R743 */
748 { 0x0000, 0x0000 }, /* R744 */
749 { 0x0000, 0x0000 }, /* R745 */
750 { 0x0000, 0x0000 }, /* R746 */
751 { 0x0000, 0x0000 }, /* R747 */
752 { 0x0000, 0x0000 }, /* R748 */
753 { 0x0000, 0x0000 }, /* R749 */
754 { 0x0000, 0x0000 }, /* R750 */
755 { 0x0000, 0x0000 }, /* R751 */
756 { 0x0000, 0x0000 }, /* R752 */
757 { 0x0000, 0x0000 }, /* R753 */
758 { 0x0000, 0x0000 }, /* R754 */
759 { 0x0000, 0x0000 }, /* R755 */
760 { 0x0000, 0x0000 }, /* R756 */
761 { 0x0000, 0x0000 }, /* R757 */
762 { 0x0000, 0x0000 }, /* R758 */
763 { 0x0000, 0x0000 }, /* R759 */
764 { 0x0000, 0x0000 }, /* R760 */
765 { 0x0000, 0x0000 }, /* R761 */
766 { 0x0000, 0x0000 }, /* R762 */
767 { 0x0000, 0x0000 }, /* R763 */
768 { 0x0000, 0x0000 }, /* R764 */
769 { 0x0000, 0x0000 }, /* R765 */
770 { 0x0000, 0x0000 }, /* R766 */
771 { 0x0000, 0x0000 }, /* R767 */
772 { 0xE1F8, 0xE1F8 }, /* R768 - AIF1 Control (1) */
773 { 0xCD1F, 0xCD1F }, /* R769 - AIF1 Control (2) */
774 { 0xF000, 0xF000 }, /* R770 - AIF1 Master/Slave */
775 { 0x01F0, 0x01F0 }, /* R771 - AIF1 BCLK */
776 { 0x0FFF, 0x0FFF }, /* R772 - AIF1ADC LRCLK */
777 { 0x0FFF, 0x0FFF }, /* R773 - AIF1DAC LRCLK */
778 { 0x0003, 0x0003 }, /* R774 - AIF1DAC Data */
779 { 0x0003, 0x0003 }, /* R775 - AIF1ADC Data */
780 { 0x0000, 0x0000 }, /* R776 */
781 { 0x0000, 0x0000 }, /* R777 */
782 { 0x0000, 0x0000 }, /* R778 */
783 { 0x0000, 0x0000 }, /* R779 */
784 { 0x0000, 0x0000 }, /* R780 */
785 { 0x0000, 0x0000 }, /* R781 */
786 { 0x0000, 0x0000 }, /* R782 */
787 { 0x0000, 0x0000 }, /* R783 */
788 { 0xF1F8, 0xF1F8 }, /* R784 - AIF2 Control (1) */
789 { 0xFD1F, 0xFD1F }, /* R785 - AIF2 Control (2) */
790 { 0xF000, 0xF000 }, /* R786 - AIF2 Master/Slave */
791 { 0x01F0, 0x01F0 }, /* R787 - AIF2 BCLK */
792 { 0x0FFF, 0x0FFF }, /* R788 - AIF2ADC LRCLK */
793 { 0x0FFF, 0x0FFF }, /* R789 - AIF2DAC LRCLK */
794 { 0x0003, 0x0003 }, /* R790 - AIF2DAC Data */
795 { 0x0003, 0x0003 }, /* R791 - AIF2ADC Data */
796 { 0x0000, 0x0000 }, /* R792 */
797 { 0x0000, 0x0000 }, /* R793 */
798 { 0x0000, 0x0000 }, /* R794 */
799 { 0x0000, 0x0000 }, /* R795 */
800 { 0x0000, 0x0000 }, /* R796 */
801 { 0x0000, 0x0000 }, /* R797 */
802 { 0x0000, 0x0000 }, /* R798 */
803 { 0x0000, 0x0000 }, /* R799 */
804 { 0x0000, 0x0000 }, /* R800 */
805 { 0x0000, 0x0000 }, /* R801 */
806 { 0x0000, 0x0000 }, /* R802 */
807 { 0x0000, 0x0000 }, /* R803 */
808 { 0x0000, 0x0000 }, /* R804 */
809 { 0x0000, 0x0000 }, /* R805 */
810 { 0x0000, 0x0000 }, /* R806 */
811 { 0x0000, 0x0000 }, /* R807 */
812 { 0x0000, 0x0000 }, /* R808 */
813 { 0x0000, 0x0000 }, /* R809 */
814 { 0x0000, 0x0000 }, /* R810 */
815 { 0x0000, 0x0000 }, /* R811 */
816 { 0x0000, 0x0000 }, /* R812 */
817 { 0x0000, 0x0000 }, /* R813 */
818 { 0x0000, 0x0000 }, /* R814 */
819 { 0x0000, 0x0000 }, /* R815 */
820 { 0x0000, 0x0000 }, /* R816 */
821 { 0x0000, 0x0000 }, /* R817 */
822 { 0x0000, 0x0000 }, /* R818 */
823 { 0x0000, 0x0000 }, /* R819 */
824 { 0x0000, 0x0000 }, /* R820 */
825 { 0x0000, 0x0000 }, /* R821 */
826 { 0x0000, 0x0000 }, /* R822 */
827 { 0x0000, 0x0000 }, /* R823 */
828 { 0x0000, 0x0000 }, /* R824 */
829 { 0x0000, 0x0000 }, /* R825 */
830 { 0x0000, 0x0000 }, /* R826 */
831 { 0x0000, 0x0000 }, /* R827 */
832 { 0x0000, 0x0000 }, /* R828 */
833 { 0x0000, 0x0000 }, /* R829 */
834 { 0x0000, 0x0000 }, /* R830 */
835 { 0x0000, 0x0000 }, /* R831 */
836 { 0x0000, 0x0000 }, /* R832 */
837 { 0x0000, 0x0000 }, /* R833 */
838 { 0x0000, 0x0000 }, /* R834 */
839 { 0x0000, 0x0000 }, /* R835 */
840 { 0x0000, 0x0000 }, /* R836 */
841 { 0x0000, 0x0000 }, /* R837 */
842 { 0x0000, 0x0000 }, /* R838 */
843 { 0x0000, 0x0000 }, /* R839 */
844 { 0x0000, 0x0000 }, /* R840 */
845 { 0x0000, 0x0000 }, /* R841 */
846 { 0x0000, 0x0000 }, /* R842 */
847 { 0x0000, 0x0000 }, /* R843 */
848 { 0x0000, 0x0000 }, /* R844 */
849 { 0x0000, 0x0000 }, /* R845 */
850 { 0x0000, 0x0000 }, /* R846 */
851 { 0x0000, 0x0000 }, /* R847 */
852 { 0x0000, 0x0000 }, /* R848 */
853 { 0x0000, 0x0000 }, /* R849 */
854 { 0x0000, 0x0000 }, /* R850 */
855 { 0x0000, 0x0000 }, /* R851 */
856 { 0x0000, 0x0000 }, /* R852 */
857 { 0x0000, 0x0000 }, /* R853 */
858 { 0x0000, 0x0000 }, /* R854 */
859 { 0x0000, 0x0000 }, /* R855 */
860 { 0x0000, 0x0000 }, /* R856 */
861 { 0x0000, 0x0000 }, /* R857 */
862 { 0x0000, 0x0000 }, /* R858 */
863 { 0x0000, 0x0000 }, /* R859 */
864 { 0x0000, 0x0000 }, /* R860 */
865 { 0x0000, 0x0000 }, /* R861 */
866 { 0x0000, 0x0000 }, /* R862 */
867 { 0x0000, 0x0000 }, /* R863 */
868 { 0x0000, 0x0000 }, /* R864 */
869 { 0x0000, 0x0000 }, /* R865 */
870 { 0x0000, 0x0000 }, /* R866 */
871 { 0x0000, 0x0000 }, /* R867 */
872 { 0x0000, 0x0000 }, /* R868 */
873 { 0x0000, 0x0000 }, /* R869 */
874 { 0x0000, 0x0000 }, /* R870 */
875 { 0x0000, 0x0000 }, /* R871 */
876 { 0x0000, 0x0000 }, /* R872 */
877 { 0x0000, 0x0000 }, /* R873 */
878 { 0x0000, 0x0000 }, /* R874 */
879 { 0x0000, 0x0000 }, /* R875 */
880 { 0x0000, 0x0000 }, /* R876 */
881 { 0x0000, 0x0000 }, /* R877 */
882 { 0x0000, 0x0000 }, /* R878 */
883 { 0x0000, 0x0000 }, /* R879 */
884 { 0x0000, 0x0000 }, /* R880 */
885 { 0x0000, 0x0000 }, /* R881 */
886 { 0x0000, 0x0000 }, /* R882 */
887 { 0x0000, 0x0000 }, /* R883 */
888 { 0x0000, 0x0000 }, /* R884 */
889 { 0x0000, 0x0000 }, /* R885 */
890 { 0x0000, 0x0000 }, /* R886 */
891 { 0x0000, 0x0000 }, /* R887 */
892 { 0x0000, 0x0000 }, /* R888 */
893 { 0x0000, 0x0000 }, /* R889 */
894 { 0x0000, 0x0000 }, /* R890 */
895 { 0x0000, 0x0000 }, /* R891 */
896 { 0x0000, 0x0000 }, /* R892 */
897 { 0x0000, 0x0000 }, /* R893 */
898 { 0x0000, 0x0000 }, /* R894 */
899 { 0x0000, 0x0000 }, /* R895 */
900 { 0x0000, 0x0000 }, /* R896 */
901 { 0x0000, 0x0000 }, /* R897 */
902 { 0x0000, 0x0000 }, /* R898 */
903 { 0x0000, 0x0000 }, /* R899 */
904 { 0x0000, 0x0000 }, /* R900 */
905 { 0x0000, 0x0000 }, /* R901 */
906 { 0x0000, 0x0000 }, /* R902 */
907 { 0x0000, 0x0000 }, /* R903 */
908 { 0x0000, 0x0000 }, /* R904 */
909 { 0x0000, 0x0000 }, /* R905 */
910 { 0x0000, 0x0000 }, /* R906 */
911 { 0x0000, 0x0000 }, /* R907 */
912 { 0x0000, 0x0000 }, /* R908 */
913 { 0x0000, 0x0000 }, /* R909 */
914 { 0x0000, 0x0000 }, /* R910 */
915 { 0x0000, 0x0000 }, /* R911 */
916 { 0x0000, 0x0000 }, /* R912 */
917 { 0x0000, 0x0000 }, /* R913 */
918 { 0x0000, 0x0000 }, /* R914 */
919 { 0x0000, 0x0000 }, /* R915 */
920 { 0x0000, 0x0000 }, /* R916 */
921 { 0x0000, 0x0000 }, /* R917 */
922 { 0x0000, 0x0000 }, /* R918 */
923 { 0x0000, 0x0000 }, /* R919 */
924 { 0x0000, 0x0000 }, /* R920 */
925 { 0x0000, 0x0000 }, /* R921 */
926 { 0x0000, 0x0000 }, /* R922 */
927 { 0x0000, 0x0000 }, /* R923 */
928 { 0x0000, 0x0000 }, /* R924 */
929 { 0x0000, 0x0000 }, /* R925 */
930 { 0x0000, 0x0000 }, /* R926 */
931 { 0x0000, 0x0000 }, /* R927 */
932 { 0x0000, 0x0000 }, /* R928 */
933 { 0x0000, 0x0000 }, /* R929 */
934 { 0x0000, 0x0000 }, /* R930 */
935 { 0x0000, 0x0000 }, /* R931 */
936 { 0x0000, 0x0000 }, /* R932 */
937 { 0x0000, 0x0000 }, /* R933 */
938 { 0x0000, 0x0000 }, /* R934 */
939 { 0x0000, 0x0000 }, /* R935 */
940 { 0x0000, 0x0000 }, /* R936 */
941 { 0x0000, 0x0000 }, /* R937 */
942 { 0x0000, 0x0000 }, /* R938 */
943 { 0x0000, 0x0000 }, /* R939 */
944 { 0x0000, 0x0000 }, /* R940 */
945 { 0x0000, 0x0000 }, /* R941 */
946 { 0x0000, 0x0000 }, /* R942 */
947 { 0x0000, 0x0000 }, /* R943 */
948 { 0x0000, 0x0000 }, /* R944 */
949 { 0x0000, 0x0000 }, /* R945 */
950 { 0x0000, 0x0000 }, /* R946 */
951 { 0x0000, 0x0000 }, /* R947 */
952 { 0x0000, 0x0000 }, /* R948 */
953 { 0x0000, 0x0000 }, /* R949 */
954 { 0x0000, 0x0000 }, /* R950 */
955 { 0x0000, 0x0000 }, /* R951 */
956 { 0x0000, 0x0000 }, /* R952 */
957 { 0x0000, 0x0000 }, /* R953 */
958 { 0x0000, 0x0000 }, /* R954 */
959 { 0x0000, 0x0000 }, /* R955 */
960 { 0x0000, 0x0000 }, /* R956 */
961 { 0x0000, 0x0000 }, /* R957 */
962 { 0x0000, 0x0000 }, /* R958 */
963 { 0x0000, 0x0000 }, /* R959 */
964 { 0x0000, 0x0000 }, /* R960 */
965 { 0x0000, 0x0000 }, /* R961 */
966 { 0x0000, 0x0000 }, /* R962 */
967 { 0x0000, 0x0000 }, /* R963 */
968 { 0x0000, 0x0000 }, /* R964 */
969 { 0x0000, 0x0000 }, /* R965 */
970 { 0x0000, 0x0000 }, /* R966 */
971 { 0x0000, 0x0000 }, /* R967 */
972 { 0x0000, 0x0000 }, /* R968 */
973 { 0x0000, 0x0000 }, /* R969 */
974 { 0x0000, 0x0000 }, /* R970 */
975 { 0x0000, 0x0000 }, /* R971 */
976 { 0x0000, 0x0000 }, /* R972 */
977 { 0x0000, 0x0000 }, /* R973 */
978 { 0x0000, 0x0000 }, /* R974 */
979 { 0x0000, 0x0000 }, /* R975 */
980 { 0x0000, 0x0000 }, /* R976 */
981 { 0x0000, 0x0000 }, /* R977 */
982 { 0x0000, 0x0000 }, /* R978 */
983 { 0x0000, 0x0000 }, /* R979 */
984 { 0x0000, 0x0000 }, /* R980 */
985 { 0x0000, 0x0000 }, /* R981 */
986 { 0x0000, 0x0000 }, /* R982 */
987 { 0x0000, 0x0000 }, /* R983 */
988 { 0x0000, 0x0000 }, /* R984 */
989 { 0x0000, 0x0000 }, /* R985 */
990 { 0x0000, 0x0000 }, /* R986 */
991 { 0x0000, 0x0000 }, /* R987 */
992 { 0x0000, 0x0000 }, /* R988 */
993 { 0x0000, 0x0000 }, /* R989 */
994 { 0x0000, 0x0000 }, /* R990 */
995 { 0x0000, 0x0000 }, /* R991 */
996 { 0x0000, 0x0000 }, /* R992 */
997 { 0x0000, 0x0000 }, /* R993 */
998 { 0x0000, 0x0000 }, /* R994 */
999 { 0x0000, 0x0000 }, /* R995 */
1000 { 0x0000, 0x0000 }, /* R996 */
1001 { 0x0000, 0x0000 }, /* R997 */
1002 { 0x0000, 0x0000 }, /* R998 */
1003 { 0x0000, 0x0000 }, /* R999 */
1004 { 0x0000, 0x0000 }, /* R1000 */
1005 { 0x0000, 0x0000 }, /* R1001 */
1006 { 0x0000, 0x0000 }, /* R1002 */
1007 { 0x0000, 0x0000 }, /* R1003 */
1008 { 0x0000, 0x0000 }, /* R1004 */
1009 { 0x0000, 0x0000 }, /* R1005 */
1010 { 0x0000, 0x0000 }, /* R1006 */
1011 { 0x0000, 0x0000 }, /* R1007 */
1012 { 0x0000, 0x0000 }, /* R1008 */
1013 { 0x0000, 0x0000 }, /* R1009 */
1014 { 0x0000, 0x0000 }, /* R1010 */
1015 { 0x0000, 0x0000 }, /* R1011 */
1016 { 0x0000, 0x0000 }, /* R1012 */
1017 { 0x0000, 0x0000 }, /* R1013 */
1018 { 0x0000, 0x0000 }, /* R1014 */
1019 { 0x0000, 0x0000 }, /* R1015 */
1020 { 0x0000, 0x0000 }, /* R1016 */
1021 { 0x0000, 0x0000 }, /* R1017 */
1022 { 0x0000, 0x0000 }, /* R1018 */
1023 { 0x0000, 0x0000 }, /* R1019 */
1024 { 0x0000, 0x0000 }, /* R1020 */
1025 { 0x0000, 0x0000 }, /* R1021 */
1026 { 0x0000, 0x0000 }, /* R1022 */
1027 { 0x0000, 0x0000 }, /* R1023 */
1028 { 0x00FF, 0x01FF }, /* R1024 - AIF1 ADC1 Left Volume */
1029 { 0x00FF, 0x01FF }, /* R1025 - AIF1 ADC1 Right Volume */
1030 { 0x00FF, 0x01FF }, /* R1026 - AIF1 DAC1 Left Volume */
1031 { 0x00FF, 0x01FF }, /* R1027 - AIF1 DAC1 Right Volume */
1032 { 0x00FF, 0x01FF }, /* R1028 - AIF1 ADC2 Left Volume */
1033 { 0x00FF, 0x01FF }, /* R1029 - AIF1 ADC2 Right Volume */
1034 { 0x00FF, 0x01FF }, /* R1030 - AIF1 DAC2 Left Volume */
1035 { 0x00FF, 0x01FF }, /* R1031 - AIF1 DAC2 Right Volume */
1036 { 0x0000, 0x0000 }, /* R1032 */
1037 { 0x0000, 0x0000 }, /* R1033 */
1038 { 0x0000, 0x0000 }, /* R1034 */
1039 { 0x0000, 0x0000 }, /* R1035 */
1040 { 0x0000, 0x0000 }, /* R1036 */
1041 { 0x0000, 0x0000 }, /* R1037 */
1042 { 0x0000, 0x0000 }, /* R1038 */
1043 { 0x0000, 0x0000 }, /* R1039 */
1044 { 0xF800, 0xF800 }, /* R1040 - AIF1 ADC1 Filters */
1045 { 0x7800, 0x7800 }, /* R1041 - AIF1 ADC2 Filters */
1046 { 0x0000, 0x0000 }, /* R1042 */
1047 { 0x0000, 0x0000 }, /* R1043 */
1048 { 0x0000, 0x0000 }, /* R1044 */
1049 { 0x0000, 0x0000 }, /* R1045 */
1050 { 0x0000, 0x0000 }, /* R1046 */
1051 { 0x0000, 0x0000 }, /* R1047 */
1052 { 0x0000, 0x0000 }, /* R1048 */
1053 { 0x0000, 0x0000 }, /* R1049 */
1054 { 0x0000, 0x0000 }, /* R1050 */
1055 { 0x0000, 0x0000 }, /* R1051 */
1056 { 0x0000, 0x0000 }, /* R1052 */
1057 { 0x0000, 0x0000 }, /* R1053 */
1058 { 0x0000, 0x0000 }, /* R1054 */
1059 { 0x0000, 0x0000 }, /* R1055 */
1060 { 0x02B6, 0x02B6 }, /* R1056 - AIF1 DAC1 Filters (1) */
1061 { 0x3F00, 0x3F00 }, /* R1057 - AIF1 DAC1 Filters (2) */
1062 { 0x02B6, 0x02B6 }, /* R1058 - AIF1 DAC2 Filters (1) */
1063 { 0x3F00, 0x3F00 }, /* R1059 - AIF1 DAC2 Filters (2) */
1064 { 0x0000, 0x0000 }, /* R1060 */
1065 { 0x0000, 0x0000 }, /* R1061 */
1066 { 0x0000, 0x0000 }, /* R1062 */
1067 { 0x0000, 0x0000 }, /* R1063 */
1068 { 0x0000, 0x0000 }, /* R1064 */
1069 { 0x0000, 0x0000 }, /* R1065 */
1070 { 0x0000, 0x0000 }, /* R1066 */
1071 { 0x0000, 0x0000 }, /* R1067 */
1072 { 0x0000, 0x0000 }, /* R1068 */
1073 { 0x0000, 0x0000 }, /* R1069 */
1074 { 0x0000, 0x0000 }, /* R1070 */
1075 { 0x0000, 0x0000 }, /* R1071 */
1076 { 0x0000, 0x0000 }, /* R1072 */
1077 { 0x0000, 0x0000 }, /* R1073 */
1078 { 0x0000, 0x0000 }, /* R1074 */
1079 { 0x0000, 0x0000 }, /* R1075 */
1080 { 0x0000, 0x0000 }, /* R1076 */
1081 { 0x0000, 0x0000 }, /* R1077 */
1082 { 0x0000, 0x0000 }, /* R1078 */
1083 { 0x0000, 0x0000 }, /* R1079 */
1084 { 0x0000, 0x0000 }, /* R1080 */
1085 { 0x0000, 0x0000 }, /* R1081 */
1086 { 0x0000, 0x0000 }, /* R1082 */
1087 { 0x0000, 0x0000 }, /* R1083 */
1088 { 0x0000, 0x0000 }, /* R1084 */
1089 { 0x0000, 0x0000 }, /* R1085 */
1090 { 0x0000, 0x0000 }, /* R1086 */
1091 { 0x0000, 0x0000 }, /* R1087 */
1092 { 0xFFFF, 0xFFFF }, /* R1088 - AIF1 DRC1 (1) */
1093 { 0x1FFF, 0x1FFF }, /* R1089 - AIF1 DRC1 (2) */
1094 { 0xFFFF, 0xFFFF }, /* R1090 - AIF1 DRC1 (3) */
1095 { 0x07FF, 0x07FF }, /* R1091 - AIF1 DRC1 (4) */
1096 { 0x03FF, 0x03FF }, /* R1092 - AIF1 DRC1 (5) */
1097 { 0x0000, 0x0000 }, /* R1093 */
1098 { 0x0000, 0x0000 }, /* R1094 */
1099 { 0x0000, 0x0000 }, /* R1095 */
1100 { 0x0000, 0x0000 }, /* R1096 */
1101 { 0x0000, 0x0000 }, /* R1097 */
1102 { 0x0000, 0x0000 }, /* R1098 */
1103 { 0x0000, 0x0000 }, /* R1099 */
1104 { 0x0000, 0x0000 }, /* R1100 */
1105 { 0x0000, 0x0000 }, /* R1101 */
1106 { 0x0000, 0x0000 }, /* R1102 */
1107 { 0x0000, 0x0000 }, /* R1103 */
1108 { 0xFFFF, 0xFFFF }, /* R1104 - AIF1 DRC2 (1) */
1109 { 0x1FFF, 0x1FFF }, /* R1105 - AIF1 DRC2 (2) */
1110 { 0xFFFF, 0xFFFF }, /* R1106 - AIF1 DRC2 (3) */
1111 { 0x07FF, 0x07FF }, /* R1107 - AIF1 DRC2 (4) */
1112 { 0x03FF, 0x03FF }, /* R1108 - AIF1 DRC2 (5) */
1113 { 0x0000, 0x0000 }, /* R1109 */
1114 { 0x0000, 0x0000 }, /* R1110 */
1115 { 0x0000, 0x0000 }, /* R1111 */
1116 { 0x0000, 0x0000 }, /* R1112 */
1117 { 0x0000, 0x0000 }, /* R1113 */
1118 { 0x0000, 0x0000 }, /* R1114 */
1119 { 0x0000, 0x0000 }, /* R1115 */
1120 { 0x0000, 0x0000 }, /* R1116 */
1121 { 0x0000, 0x0000 }, /* R1117 */
1122 { 0x0000, 0x0000 }, /* R1118 */
1123 { 0x0000, 0x0000 }, /* R1119 */
1124 { 0x0000, 0x0000 }, /* R1120 */
1125 { 0x0000, 0x0000 }, /* R1121 */
1126 { 0x0000, 0x0000 }, /* R1122 */
1127 { 0x0000, 0x0000 }, /* R1123 */
1128 { 0x0000, 0x0000 }, /* R1124 */
1129 { 0x0000, 0x0000 }, /* R1125 */
1130 { 0x0000, 0x0000 }, /* R1126 */
1131 { 0x0000, 0x0000 }, /* R1127 */
1132 { 0x0000, 0x0000 }, /* R1128 */
1133 { 0x0000, 0x0000 }, /* R1129 */
1134 { 0x0000, 0x0000 }, /* R1130 */
1135 { 0x0000, 0x0000 }, /* R1131 */
1136 { 0x0000, 0x0000 }, /* R1132 */
1137 { 0x0000, 0x0000 }, /* R1133 */
1138 { 0x0000, 0x0000 }, /* R1134 */
1139 { 0x0000, 0x0000 }, /* R1135 */
1140 { 0x0000, 0x0000 }, /* R1136 */
1141 { 0x0000, 0x0000 }, /* R1137 */
1142 { 0x0000, 0x0000 }, /* R1138 */
1143 { 0x0000, 0x0000 }, /* R1139 */
1144 { 0x0000, 0x0000 }, /* R1140 */
1145 { 0x0000, 0x0000 }, /* R1141 */
1146 { 0x0000, 0x0000 }, /* R1142 */
1147 { 0x0000, 0x0000 }, /* R1143 */
1148 { 0x0000, 0x0000 }, /* R1144 */
1149 { 0x0000, 0x0000 }, /* R1145 */
1150 { 0x0000, 0x0000 }, /* R1146 */
1151 { 0x0000, 0x0000 }, /* R1147 */
1152 { 0x0000, 0x0000 }, /* R1148 */
1153 { 0x0000, 0x0000 }, /* R1149 */
1154 { 0x0000, 0x0000 }, /* R1150 */
1155 { 0x0000, 0x0000 }, /* R1151 */
1156 { 0xFFFF, 0xFFFF }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
1157 { 0xFFC0, 0xFFC0 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
1158 { 0xFFFF, 0xFFFF }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
1159 { 0xFFFF, 0xFFFF }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
1160 { 0xFFFF, 0xFFFF }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
1161 { 0xFFFF, 0xFFFF }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
1162 { 0xFFFF, 0xFFFF }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
1163 { 0xFFFF, 0xFFFF }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
1164 { 0xFFFF, 0xFFFF }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
1165 { 0xFFFF, 0xFFFF }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
1166 { 0xFFFF, 0xFFFF }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
1167 { 0xFFFF, 0xFFFF }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
1168 { 0xFFFF, 0xFFFF }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
1169 { 0xFFFF, 0xFFFF }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
1170 { 0xFFFF, 0xFFFF }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
1171 { 0xFFFF, 0xFFFF }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
1172 { 0xFFFF, 0xFFFF }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
1173 { 0xFFFF, 0xFFFF }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
1174 { 0xFFFF, 0xFFFF }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
1175 { 0xFFFF, 0xFFFF }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
1176 { 0x0000, 0x0000 }, /* R1172 */
1177 { 0x0000, 0x0000 }, /* R1173 */
1178 { 0x0000, 0x0000 }, /* R1174 */
1179 { 0x0000, 0x0000 }, /* R1175 */
1180 { 0x0000, 0x0000 }, /* R1176 */
1181 { 0x0000, 0x0000 }, /* R1177 */
1182 { 0x0000, 0x0000 }, /* R1178 */
1183 { 0x0000, 0x0000 }, /* R1179 */
1184 { 0x0000, 0x0000 }, /* R1180 */
1185 { 0x0000, 0x0000 }, /* R1181 */
1186 { 0x0000, 0x0000 }, /* R1182 */
1187 { 0x0000, 0x0000 }, /* R1183 */
1188 { 0xFFFF, 0xFFFF }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
1189 { 0xFFC0, 0xFFC0 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
1190 { 0xFFFF, 0xFFFF }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
1191 { 0xFFFF, 0xFFFF }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
1192 { 0xFFFF, 0xFFFF }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
1193 { 0xFFFF, 0xFFFF }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
1194 { 0xFFFF, 0xFFFF }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
1195 { 0xFFFF, 0xFFFF }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
1196 { 0xFFFF, 0xFFFF }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
1197 { 0xFFFF, 0xFFFF }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
1198 { 0xFFFF, 0xFFFF }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
1199 { 0xFFFF, 0xFFFF }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
1200 { 0xFFFF, 0xFFFF }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
1201 { 0xFFFF, 0xFFFF }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
1202 { 0xFFFF, 0xFFFF }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
1203 { 0xFFFF, 0xFFFF }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
1204 { 0xFFFF, 0xFFFF }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
1205 { 0xFFFF, 0xFFFF }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
1206 { 0xFFFF, 0xFFFF }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
1207 { 0xFFFF, 0xFFFF }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
1208 { 0x0000, 0x0000 }, /* R1204 */
1209 { 0x0000, 0x0000 }, /* R1205 */
1210 { 0x0000, 0x0000 }, /* R1206 */
1211 { 0x0000, 0x0000 }, /* R1207 */
1212 { 0x0000, 0x0000 }, /* R1208 */
1213 { 0x0000, 0x0000 }, /* R1209 */
1214 { 0x0000, 0x0000 }, /* R1210 */
1215 { 0x0000, 0x0000 }, /* R1211 */
1216 { 0x0000, 0x0000 }, /* R1212 */
1217 { 0x0000, 0x0000 }, /* R1213 */
1218 { 0x0000, 0x0000 }, /* R1214 */
1219 { 0x0000, 0x0000 }, /* R1215 */
1220 { 0x0000, 0x0000 }, /* R1216 */
1221 { 0x0000, 0x0000 }, /* R1217 */
1222 { 0x0000, 0x0000 }, /* R1218 */
1223 { 0x0000, 0x0000 }, /* R1219 */
1224 { 0x0000, 0x0000 }, /* R1220 */
1225 { 0x0000, 0x0000 }, /* R1221 */
1226 { 0x0000, 0x0000 }, /* R1222 */
1227 { 0x0000, 0x0000 }, /* R1223 */
1228 { 0x0000, 0x0000 }, /* R1224 */
1229 { 0x0000, 0x0000 }, /* R1225 */
1230 { 0x0000, 0x0000 }, /* R1226 */
1231 { 0x0000, 0x0000 }, /* R1227 */
1232 { 0x0000, 0x0000 }, /* R1228 */
1233 { 0x0000, 0x0000 }, /* R1229 */
1234 { 0x0000, 0x0000 }, /* R1230 */
1235 { 0x0000, 0x0000 }, /* R1231 */
1236 { 0x0000, 0x0000 }, /* R1232 */
1237 { 0x0000, 0x0000 }, /* R1233 */
1238 { 0x0000, 0x0000 }, /* R1234 */
1239 { 0x0000, 0x0000 }, /* R1235 */
1240 { 0x0000, 0x0000 }, /* R1236 */
1241 { 0x0000, 0x0000 }, /* R1237 */
1242 { 0x0000, 0x0000 }, /* R1238 */
1243 { 0x0000, 0x0000 }, /* R1239 */
1244 { 0x0000, 0x0000 }, /* R1240 */
1245 { 0x0000, 0x0000 }, /* R1241 */
1246 { 0x0000, 0x0000 }, /* R1242 */
1247 { 0x0000, 0x0000 }, /* R1243 */
1248 { 0x0000, 0x0000 }, /* R1244 */
1249 { 0x0000, 0x0000 }, /* R1245 */
1250 { 0x0000, 0x0000 }, /* R1246 */
1251 { 0x0000, 0x0000 }, /* R1247 */
1252 { 0x0000, 0x0000 }, /* R1248 */
1253 { 0x0000, 0x0000 }, /* R1249 */
1254 { 0x0000, 0x0000 }, /* R1250 */
1255 { 0x0000, 0x0000 }, /* R1251 */
1256 { 0x0000, 0x0000 }, /* R1252 */
1257 { 0x0000, 0x0000 }, /* R1253 */
1258 { 0x0000, 0x0000 }, /* R1254 */
1259 { 0x0000, 0x0000 }, /* R1255 */
1260 { 0x0000, 0x0000 }, /* R1256 */
1261 { 0x0000, 0x0000 }, /* R1257 */
1262 { 0x0000, 0x0000 }, /* R1258 */
1263 { 0x0000, 0x0000 }, /* R1259 */
1264 { 0x0000, 0x0000 }, /* R1260 */
1265 { 0x0000, 0x0000 }, /* R1261 */
1266 { 0x0000, 0x0000 }, /* R1262 */
1267 { 0x0000, 0x0000 }, /* R1263 */
1268 { 0x0000, 0x0000 }, /* R1264 */
1269 { 0x0000, 0x0000 }, /* R1265 */
1270 { 0x0000, 0x0000 }, /* R1266 */
1271 { 0x0000, 0x0000 }, /* R1267 */
1272 { 0x0000, 0x0000 }, /* R1268 */
1273 { 0x0000, 0x0000 }, /* R1269 */
1274 { 0x0000, 0x0000 }, /* R1270 */
1275 { 0x0000, 0x0000 }, /* R1271 */
1276 { 0x0000, 0x0000 }, /* R1272 */
1277 { 0x0000, 0x0000 }, /* R1273 */
1278 { 0x0000, 0x0000 }, /* R1274 */
1279 { 0x0000, 0x0000 }, /* R1275 */
1280 { 0x0000, 0x0000 }, /* R1276 */
1281 { 0x0000, 0x0000 }, /* R1277 */
1282 { 0x0000, 0x0000 }, /* R1278 */
1283 { 0x0000, 0x0000 }, /* R1279 */
1284 { 0x00FF, 0x01FF }, /* R1280 - AIF2 ADC Left Volume */
1285 { 0x00FF, 0x01FF }, /* R1281 - AIF2 ADC Right Volume */
1286 { 0x00FF, 0x01FF }, /* R1282 - AIF2 DAC Left Volume */
1287 { 0x00FF, 0x01FF }, /* R1283 - AIF2 DAC Right Volume */
1288 { 0x0000, 0x0000 }, /* R1284 */
1289 { 0x0000, 0x0000 }, /* R1285 */
1290 { 0x0000, 0x0000 }, /* R1286 */
1291 { 0x0000, 0x0000 }, /* R1287 */
1292 { 0x0000, 0x0000 }, /* R1288 */
1293 { 0x0000, 0x0000 }, /* R1289 */
1294 { 0x0000, 0x0000 }, /* R1290 */
1295 { 0x0000, 0x0000 }, /* R1291 */
1296 { 0x0000, 0x0000 }, /* R1292 */
1297 { 0x0000, 0x0000 }, /* R1293 */
1298 { 0x0000, 0x0000 }, /* R1294 */
1299 { 0x0000, 0x0000 }, /* R1295 */
1300 { 0xF800, 0xF800 }, /* R1296 - AIF2 ADC Filters */
1301 { 0x0000, 0x0000 }, /* R1297 */
1302 { 0x0000, 0x0000 }, /* R1298 */
1303 { 0x0000, 0x0000 }, /* R1299 */
1304 { 0x0000, 0x0000 }, /* R1300 */
1305 { 0x0000, 0x0000 }, /* R1301 */
1306 { 0x0000, 0x0000 }, /* R1302 */
1307 { 0x0000, 0x0000 }, /* R1303 */
1308 { 0x0000, 0x0000 }, /* R1304 */
1309 { 0x0000, 0x0000 }, /* R1305 */
1310 { 0x0000, 0x0000 }, /* R1306 */
1311 { 0x0000, 0x0000 }, /* R1307 */
1312 { 0x0000, 0x0000 }, /* R1308 */
1313 { 0x0000, 0x0000 }, /* R1309 */
1314 { 0x0000, 0x0000 }, /* R1310 */
1315 { 0x0000, 0x0000 }, /* R1311 */
1316 { 0x02B6, 0x02B6 }, /* R1312 - AIF2 DAC Filters (1) */
1317 { 0x3F00, 0x3F00 }, /* R1313 - AIF2 DAC Filters (2) */
1318 { 0x0000, 0x0000 }, /* R1314 */
1319 { 0x0000, 0x0000 }, /* R1315 */
1320 { 0x0000, 0x0000 }, /* R1316 */
1321 { 0x0000, 0x0000 }, /* R1317 */
1322 { 0x0000, 0x0000 }, /* R1318 */
1323 { 0x0000, 0x0000 }, /* R1319 */
1324 { 0x0000, 0x0000 }, /* R1320 */
1325 { 0x0000, 0x0000 }, /* R1321 */
1326 { 0x0000, 0x0000 }, /* R1322 */
1327 { 0x0000, 0x0000 }, /* R1323 */
1328 { 0x0000, 0x0000 }, /* R1324 */
1329 { 0x0000, 0x0000 }, /* R1325 */
1330 { 0x0000, 0x0000 }, /* R1326 */
1331 { 0x0000, 0x0000 }, /* R1327 */
1332 { 0x0000, 0x0000 }, /* R1328 */
1333 { 0x0000, 0x0000 }, /* R1329 */
1334 { 0x0000, 0x0000 }, /* R1330 */
1335 { 0x0000, 0x0000 }, /* R1331 */
1336 { 0x0000, 0x0000 }, /* R1332 */
1337 { 0x0000, 0x0000 }, /* R1333 */
1338 { 0x0000, 0x0000 }, /* R1334 */
1339 { 0x0000, 0x0000 }, /* R1335 */
1340 { 0x0000, 0x0000 }, /* R1336 */
1341 { 0x0000, 0x0000 }, /* R1337 */
1342 { 0x0000, 0x0000 }, /* R1338 */
1343 { 0x0000, 0x0000 }, /* R1339 */
1344 { 0x0000, 0x0000 }, /* R1340 */
1345 { 0x0000, 0x0000 }, /* R1341 */
1346 { 0x0000, 0x0000 }, /* R1342 */
1347 { 0x0000, 0x0000 }, /* R1343 */
1348 { 0xFFFF, 0xFFFF }, /* R1344 - AIF2 DRC (1) */
1349 { 0x1FFF, 0x1FFF }, /* R1345 - AIF2 DRC (2) */
1350 { 0xFFFF, 0xFFFF }, /* R1346 - AIF2 DRC (3) */
1351 { 0x07FF, 0x07FF }, /* R1347 - AIF2 DRC (4) */
1352 { 0x03FF, 0x03FF }, /* R1348 - AIF2 DRC (5) */
1353 { 0x0000, 0x0000 }, /* R1349 */
1354 { 0x0000, 0x0000 }, /* R1350 */
1355 { 0x0000, 0x0000 }, /* R1351 */
1356 { 0x0000, 0x0000 }, /* R1352 */
1357 { 0x0000, 0x0000 }, /* R1353 */
1358 { 0x0000, 0x0000 }, /* R1354 */
1359 { 0x0000, 0x0000 }, /* R1355 */
1360 { 0x0000, 0x0000 }, /* R1356 */
1361 { 0x0000, 0x0000 }, /* R1357 */
1362 { 0x0000, 0x0000 }, /* R1358 */
1363 { 0x0000, 0x0000 }, /* R1359 */
1364 { 0x0000, 0x0000 }, /* R1360 */
1365 { 0x0000, 0x0000 }, /* R1361 */
1366 { 0x0000, 0x0000 }, /* R1362 */
1367 { 0x0000, 0x0000 }, /* R1363 */
1368 { 0x0000, 0x0000 }, /* R1364 */
1369 { 0x0000, 0x0000 }, /* R1365 */
1370 { 0x0000, 0x0000 }, /* R1366 */
1371 { 0x0000, 0x0000 }, /* R1367 */
1372 { 0x0000, 0x0000 }, /* R1368 */
1373 { 0x0000, 0x0000 }, /* R1369 */
1374 { 0x0000, 0x0000 }, /* R1370 */
1375 { 0x0000, 0x0000 }, /* R1371 */
1376 { 0x0000, 0x0000 }, /* R1372 */
1377 { 0x0000, 0x0000 }, /* R1373 */
1378 { 0x0000, 0x0000 }, /* R1374 */
1379 { 0x0000, 0x0000 }, /* R1375 */
1380 { 0x0000, 0x0000 }, /* R1376 */
1381 { 0x0000, 0x0000 }, /* R1377 */
1382 { 0x0000, 0x0000 }, /* R1378 */
1383 { 0x0000, 0x0000 }, /* R1379 */
1384 { 0x0000, 0x0000 }, /* R1380 */
1385 { 0x0000, 0x0000 }, /* R1381 */
1386 { 0x0000, 0x0000 }, /* R1382 */
1387 { 0x0000, 0x0000 }, /* R1383 */
1388 { 0x0000, 0x0000 }, /* R1384 */
1389 { 0x0000, 0x0000 }, /* R1385 */
1390 { 0x0000, 0x0000 }, /* R1386 */
1391 { 0x0000, 0x0000 }, /* R1387 */
1392 { 0x0000, 0x0000 }, /* R1388 */
1393 { 0x0000, 0x0000 }, /* R1389 */
1394 { 0x0000, 0x0000 }, /* R1390 */
1395 { 0x0000, 0x0000 }, /* R1391 */
1396 { 0x0000, 0x0000 }, /* R1392 */
1397 { 0x0000, 0x0000 }, /* R1393 */
1398 { 0x0000, 0x0000 }, /* R1394 */
1399 { 0x0000, 0x0000 }, /* R1395 */
1400 { 0x0000, 0x0000 }, /* R1396 */
1401 { 0x0000, 0x0000 }, /* R1397 */
1402 { 0x0000, 0x0000 }, /* R1398 */
1403 { 0x0000, 0x0000 }, /* R1399 */
1404 { 0x0000, 0x0000 }, /* R1400 */
1405 { 0x0000, 0x0000 }, /* R1401 */
1406 { 0x0000, 0x0000 }, /* R1402 */
1407 { 0x0000, 0x0000 }, /* R1403 */
1408 { 0x0000, 0x0000 }, /* R1404 */
1409 { 0x0000, 0x0000 }, /* R1405 */
1410 { 0x0000, 0x0000 }, /* R1406 */
1411 { 0x0000, 0x0000 }, /* R1407 */
1412 { 0xFFFF, 0xFFFF }, /* R1408 - AIF2 EQ Gains (1) */
1413 { 0xFFC0, 0xFFC0 }, /* R1409 - AIF2 EQ Gains (2) */
1414 { 0xFFFF, 0xFFFF }, /* R1410 - AIF2 EQ Band 1 A */
1415 { 0xFFFF, 0xFFFF }, /* R1411 - AIF2 EQ Band 1 B */
1416 { 0xFFFF, 0xFFFF }, /* R1412 - AIF2 EQ Band 1 PG */
1417 { 0xFFFF, 0xFFFF }, /* R1413 - AIF2 EQ Band 2 A */
1418 { 0xFFFF, 0xFFFF }, /* R1414 - AIF2 EQ Band 2 B */
1419 { 0xFFFF, 0xFFFF }, /* R1415 - AIF2 EQ Band 2 C */
1420 { 0xFFFF, 0xFFFF }, /* R1416 - AIF2 EQ Band 2 PG */
1421 { 0xFFFF, 0xFFFF }, /* R1417 - AIF2 EQ Band 3 A */
1422 { 0xFFFF, 0xFFFF }, /* R1418 - AIF2 EQ Band 3 B */
1423 { 0xFFFF, 0xFFFF }, /* R1419 - AIF2 EQ Band 3 C */
1424 { 0xFFFF, 0xFFFF }, /* R1420 - AIF2 EQ Band 3 PG */
1425 { 0xFFFF, 0xFFFF }, /* R1421 - AIF2 EQ Band 4 A */
1426 { 0xFFFF, 0xFFFF }, /* R1422 - AIF2 EQ Band 4 B */
1427 { 0xFFFF, 0xFFFF }, /* R1423 - AIF2 EQ Band 4 C */
1428 { 0xFFFF, 0xFFFF }, /* R1424 - AIF2 EQ Band 4 PG */
1429 { 0xFFFF, 0xFFFF }, /* R1425 - AIF2 EQ Band 5 A */
1430 { 0xFFFF, 0xFFFF }, /* R1426 - AIF2 EQ Band 5 B */
1431 { 0xFFFF, 0xFFFF }, /* R1427 - AIF2 EQ Band 5 PG */
1432 { 0x0000, 0x0000 }, /* R1428 */
1433 { 0x0000, 0x0000 }, /* R1429 */
1434 { 0x0000, 0x0000 }, /* R1430 */
1435 { 0x0000, 0x0000 }, /* R1431 */
1436 { 0x0000, 0x0000 }, /* R1432 */
1437 { 0x0000, 0x0000 }, /* R1433 */
1438 { 0x0000, 0x0000 }, /* R1434 */
1439 { 0x0000, 0x0000 }, /* R1435 */
1440 { 0x0000, 0x0000 }, /* R1436 */
1441 { 0x0000, 0x0000 }, /* R1437 */
1442 { 0x0000, 0x0000 }, /* R1438 */
1443 { 0x0000, 0x0000 }, /* R1439 */
1444 { 0x0000, 0x0000 }, /* R1440 */
1445 { 0x0000, 0x0000 }, /* R1441 */
1446 { 0x0000, 0x0000 }, /* R1442 */
1447 { 0x0000, 0x0000 }, /* R1443 */
1448 { 0x0000, 0x0000 }, /* R1444 */
1449 { 0x0000, 0x0000 }, /* R1445 */
1450 { 0x0000, 0x0000 }, /* R1446 */
1451 { 0x0000, 0x0000 }, /* R1447 */
1452 { 0x0000, 0x0000 }, /* R1448 */
1453 { 0x0000, 0x0000 }, /* R1449 */
1454 { 0x0000, 0x0000 }, /* R1450 */
1455 { 0x0000, 0x0000 }, /* R1451 */
1456 { 0x0000, 0x0000 }, /* R1452 */
1457 { 0x0000, 0x0000 }, /* R1453 */
1458 { 0x0000, 0x0000 }, /* R1454 */
1459 { 0x0000, 0x0000 }, /* R1455 */
1460 { 0x0000, 0x0000 }, /* R1456 */
1461 { 0x0000, 0x0000 }, /* R1457 */
1462 { 0x0000, 0x0000 }, /* R1458 */
1463 { 0x0000, 0x0000 }, /* R1459 */
1464 { 0x0000, 0x0000 }, /* R1460 */
1465 { 0x0000, 0x0000 }, /* R1461 */
1466 { 0x0000, 0x0000 }, /* R1462 */
1467 { 0x0000, 0x0000 }, /* R1463 */
1468 { 0x0000, 0x0000 }, /* R1464 */
1469 { 0x0000, 0x0000 }, /* R1465 */
1470 { 0x0000, 0x0000 }, /* R1466 */
1471 { 0x0000, 0x0000 }, /* R1467 */
1472 { 0x0000, 0x0000 }, /* R1468 */
1473 { 0x0000, 0x0000 }, /* R1469 */
1474 { 0x0000, 0x0000 }, /* R1470 */
1475 { 0x0000, 0x0000 }, /* R1471 */
1476 { 0x0000, 0x0000 }, /* R1472 */
1477 { 0x0000, 0x0000 }, /* R1473 */
1478 { 0x0000, 0x0000 }, /* R1474 */
1479 { 0x0000, 0x0000 }, /* R1475 */
1480 { 0x0000, 0x0000 }, /* R1476 */
1481 { 0x0000, 0x0000 }, /* R1477 */
1482 { 0x0000, 0x0000 }, /* R1478 */
1483 { 0x0000, 0x0000 }, /* R1479 */
1484 { 0x0000, 0x0000 }, /* R1480 */
1485 { 0x0000, 0x0000 }, /* R1481 */
1486 { 0x0000, 0x0000 }, /* R1482 */
1487 { 0x0000, 0x0000 }, /* R1483 */
1488 { 0x0000, 0x0000 }, /* R1484 */
1489 { 0x0000, 0x0000 }, /* R1485 */
1490 { 0x0000, 0x0000 }, /* R1486 */
1491 { 0x0000, 0x0000 }, /* R1487 */
1492 { 0x0000, 0x0000 }, /* R1488 */
1493 { 0x0000, 0x0000 }, /* R1489 */
1494 { 0x0000, 0x0000 }, /* R1490 */
1495 { 0x0000, 0x0000 }, /* R1491 */
1496 { 0x0000, 0x0000 }, /* R1492 */
1497 { 0x0000, 0x0000 }, /* R1493 */
1498 { 0x0000, 0x0000 }, /* R1494 */
1499 { 0x0000, 0x0000 }, /* R1495 */
1500 { 0x0000, 0x0000 }, /* R1496 */
1501 { 0x0000, 0x0000 }, /* R1497 */
1502 { 0x0000, 0x0000 }, /* R1498 */
1503 { 0x0000, 0x0000 }, /* R1499 */
1504 { 0x0000, 0x0000 }, /* R1500 */
1505 { 0x0000, 0x0000 }, /* R1501 */
1506 { 0x0000, 0x0000 }, /* R1502 */
1507 { 0x0000, 0x0000 }, /* R1503 */
1508 { 0x0000, 0x0000 }, /* R1504 */
1509 { 0x0000, 0x0000 }, /* R1505 */
1510 { 0x0000, 0x0000 }, /* R1506 */
1511 { 0x0000, 0x0000 }, /* R1507 */
1512 { 0x0000, 0x0000 }, /* R1508 */
1513 { 0x0000, 0x0000 }, /* R1509 */
1514 { 0x0000, 0x0000 }, /* R1510 */
1515 { 0x0000, 0x0000 }, /* R1511 */
1516 { 0x0000, 0x0000 }, /* R1512 */
1517 { 0x0000, 0x0000 }, /* R1513 */
1518 { 0x0000, 0x0000 }, /* R1514 */
1519 { 0x0000, 0x0000 }, /* R1515 */
1520 { 0x0000, 0x0000 }, /* R1516 */
1521 { 0x0000, 0x0000 }, /* R1517 */
1522 { 0x0000, 0x0000 }, /* R1518 */
1523 { 0x0000, 0x0000 }, /* R1519 */
1524 { 0x0000, 0x0000 }, /* R1520 */
1525 { 0x0000, 0x0000 }, /* R1521 */
1526 { 0x0000, 0x0000 }, /* R1522 */
1527 { 0x0000, 0x0000 }, /* R1523 */
1528 { 0x0000, 0x0000 }, /* R1524 */
1529 { 0x0000, 0x0000 }, /* R1525 */
1530 { 0x0000, 0x0000 }, /* R1526 */
1531 { 0x0000, 0x0000 }, /* R1527 */
1532 { 0x0000, 0x0000 }, /* R1528 */
1533 { 0x0000, 0x0000 }, /* R1529 */
1534 { 0x0000, 0x0000 }, /* R1530 */
1535 { 0x0000, 0x0000 }, /* R1531 */
1536 { 0x0000, 0x0000 }, /* R1532 */
1537 { 0x0000, 0x0000 }, /* R1533 */
1538 { 0x0000, 0x0000 }, /* R1534 */
1539 { 0x0000, 0x0000 }, /* R1535 */
1540 { 0x01EF, 0x01EF }, /* R1536 - DAC1 Mixer Volumes */
1541 { 0x0037, 0x0037 }, /* R1537 - DAC1 Left Mixer Routing */
1542 { 0x0037, 0x0037 }, /* R1538 - DAC1 Right Mixer Routing */
1543 { 0x01EF, 0x01EF }, /* R1539 - DAC2 Mixer Volumes */
1544 { 0x0037, 0x0037 }, /* R1540 - DAC2 Left Mixer Routing */
1545 { 0x0037, 0x0037 }, /* R1541 - DAC2 Right Mixer Routing */
1546 { 0x0003, 0x0003 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
1547 { 0x0003, 0x0003 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
1548 { 0x0003, 0x0003 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
1549 { 0x0003, 0x0003 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
1550 { 0x0000, 0x0000 }, /* R1546 */
1551 { 0x0000, 0x0000 }, /* R1547 */
1552 { 0x0000, 0x0000 }, /* R1548 */
1553 { 0x0000, 0x0000 }, /* R1549 */
1554 { 0x0000, 0x0000 }, /* R1550 */
1555 { 0x0000, 0x0000 }, /* R1551 */
1556 { 0x02FF, 0x03FF }, /* R1552 - DAC1 Left Volume */
1557 { 0x02FF, 0x03FF }, /* R1553 - DAC1 Right Volume */
1558 { 0x02FF, 0x03FF }, /* R1554 - DAC2 Left Volume */
1559 { 0x02FF, 0x03FF }, /* R1555 - DAC2 Right Volume */
1560 { 0x0003, 0x0003 }, /* R1556 - DAC Softmute */
1561 { 0x0000, 0x0000 }, /* R1557 */
1562 { 0x0000, 0x0000 }, /* R1558 */
1563 { 0x0000, 0x0000 }, /* R1559 */
1564 { 0x0000, 0x0000 }, /* R1560 */
1565 { 0x0000, 0x0000 }, /* R1561 */
1566 { 0x0000, 0x0000 }, /* R1562 */
1567 { 0x0000, 0x0000 }, /* R1563 */
1568 { 0x0000, 0x0000 }, /* R1564 */
1569 { 0x0000, 0x0000 }, /* R1565 */
1570 { 0x0000, 0x0000 }, /* R1566 */
1571 { 0x0000, 0x0000 }, /* R1567 */
1572 { 0x0003, 0x0003 }, /* R1568 - Oversampling */
1573 { 0x03C3, 0x03C3 }, /* R1569 - Sidetone */
1574};
1575
1576const __devinitdata u16 wm8994_reg_defaults[WM8994_CACHE_SIZE] = {
1577 0x8994, /* R0 - Software Reset */
1578 0x0000, /* R1 - Power Management (1) */
1579 0x6000, /* R2 - Power Management (2) */
1580 0x0000, /* R3 - Power Management (3) */
1581 0x0000, /* R4 - Power Management (4) */
1582 0x0000, /* R5 - Power Management (5) */
1583 0x0000, /* R6 - Power Management (6) */
1584 0x0000, /* R7 */
1585 0x0000, /* R8 */
1586 0x0000, /* R9 */
1587 0x0000, /* R10 */
1588 0x0000, /* R11 */
1589 0x0000, /* R12 */
1590 0x0000, /* R13 */
1591 0x0000, /* R14 */
1592 0x0000, /* R15 */
1593 0x0000, /* R16 */
1594 0x0000, /* R17 */
1595 0x0000, /* R18 */
1596 0x0000, /* R19 */
1597 0x0000, /* R20 */
1598 0x0000, /* R21 - Input Mixer (1) */
1599 0x0000, /* R22 */
1600 0x0000, /* R23 */
1601 0x008B, /* R24 - Left Line Input 1&2 Volume */
1602 0x008B, /* R25 - Left Line Input 3&4 Volume */
1603 0x008B, /* R26 - Right Line Input 1&2 Volume */
1604 0x008B, /* R27 - Right Line Input 3&4 Volume */
1605 0x006D, /* R28 - Left Output Volume */
1606 0x006D, /* R29 - Right Output Volume */
1607 0x0066, /* R30 - Line Outputs Volume */
1608 0x0020, /* R31 - HPOUT2 Volume */
1609 0x0079, /* R32 - Left OPGA Volume */
1610 0x0079, /* R33 - Right OPGA Volume */
1611 0x0003, /* R34 - SPKMIXL Attenuation */
1612 0x0003, /* R35 - SPKMIXR Attenuation */
1613 0x0011, /* R36 - SPKOUT Mixers */
1614 0x0140, /* R37 - ClassD */
1615 0x0079, /* R38 - Speaker Volume Left */
1616 0x0079, /* R39 - Speaker Volume Right */
1617 0x0000, /* R40 - Input Mixer (2) */
1618 0x0000, /* R41 - Input Mixer (3) */
1619 0x0000, /* R42 - Input Mixer (4) */
1620 0x0000, /* R43 - Input Mixer (5) */
1621 0x0000, /* R44 - Input Mixer (6) */
1622 0x0000, /* R45 - Output Mixer (1) */
1623 0x0000, /* R46 - Output Mixer (2) */
1624 0x0000, /* R47 - Output Mixer (3) */
1625 0x0000, /* R48 - Output Mixer (4) */
1626 0x0000, /* R49 - Output Mixer (5) */
1627 0x0000, /* R50 - Output Mixer (6) */
1628 0x0000, /* R51 - HPOUT2 Mixer */
1629 0x0000, /* R52 - Line Mixer (1) */
1630 0x0000, /* R53 - Line Mixer (2) */
1631 0x0000, /* R54 - Speaker Mixer */
1632 0x0000, /* R55 - Additional Control */
1633 0x0000, /* R56 - AntiPOP (1) */
1634 0x0000, /* R57 - AntiPOP (2) */
1635 0x0000, /* R58 - MICBIAS */
1636 0x000D, /* R59 - LDO 1 */
1637 0x0003, /* R60 - LDO 2 */
1638 0x0000, /* R61 */
1639 0x0000, /* R62 */
1640 0x0000, /* R63 */
1641 0x0000, /* R64 */
1642 0x0000, /* R65 */
1643 0x0000, /* R66 */
1644 0x0000, /* R67 */
1645 0x0000, /* R68 */
1646 0x0000, /* R69 */
1647 0x0000, /* R70 */
1648 0x0000, /* R71 */
1649 0x0000, /* R72 */
1650 0x0000, /* R73 */
1651 0x0000, /* R74 */
1652 0x0000, /* R75 */
1653 0x1F25, /* R76 - Charge Pump (1) */
1654 0x0000, /* R77 */
1655 0x0000, /* R78 */
1656 0x0000, /* R79 */
1657 0x0000, /* R80 */
1658 0x0004, /* R81 - Class W (1) */
1659 0x0000, /* R82 */
1660 0x0000, /* R83 */
1661 0x0000, /* R84 - DC Servo (1) */
1662 0x054A, /* R85 - DC Servo (2) */
1663 0x0000, /* R86 */
1664 0x0000, /* R87 - DC Servo (4) */
1665 0x0000, /* R88 - DC Servo Readback */
1666 0x0000, /* R89 */
1667 0x0000, /* R90 */
1668 0x0000, /* R91 */
1669 0x0000, /* R92 */
1670 0x0000, /* R93 */
1671 0x0000, /* R94 */
1672 0x0000, /* R95 */
1673 0x0000, /* R96 - Analogue HP (1) */
1674 0x0000, /* R97 */
1675 0x0000, /* R98 */
1676 0x0000, /* R99 */
1677 0x0000, /* R100 */
1678 0x0000, /* R101 */
1679 0x0000, /* R102 */
1680 0x0000, /* R103 */
1681 0x0000, /* R104 */
1682 0x0000, /* R105 */
1683 0x0000, /* R106 */
1684 0x0000, /* R107 */
1685 0x0000, /* R108 */
1686 0x0000, /* R109 */
1687 0x0000, /* R110 */
1688 0x0000, /* R111 */
1689 0x0000, /* R112 */
1690 0x0000, /* R113 */
1691 0x0000, /* R114 */
1692 0x0000, /* R115 */
1693 0x0000, /* R116 */
1694 0x0000, /* R117 */
1695 0x0000, /* R118 */
1696 0x0000, /* R119 */
1697 0x0000, /* R120 */
1698 0x0000, /* R121 */
1699 0x0000, /* R122 */
1700 0x0000, /* R123 */
1701 0x0000, /* R124 */
1702 0x0000, /* R125 */
1703 0x0000, /* R126 */
1704 0x0000, /* R127 */
1705 0x0000, /* R128 */
1706 0x0000, /* R129 */
1707 0x0000, /* R130 */
1708 0x0000, /* R131 */
1709 0x0000, /* R132 */
1710 0x0000, /* R133 */
1711 0x0000, /* R134 */
1712 0x0000, /* R135 */
1713 0x0000, /* R136 */
1714 0x0000, /* R137 */
1715 0x0000, /* R138 */
1716 0x0000, /* R139 */
1717 0x0000, /* R140 */
1718 0x0000, /* R141 */
1719 0x0000, /* R142 */
1720 0x0000, /* R143 */
1721 0x0000, /* R144 */
1722 0x0000, /* R145 */
1723 0x0000, /* R146 */
1724 0x0000, /* R147 */
1725 0x0000, /* R148 */
1726 0x0000, /* R149 */
1727 0x0000, /* R150 */
1728 0x0000, /* R151 */
1729 0x0000, /* R152 */
1730 0x0000, /* R153 */
1731 0x0000, /* R154 */
1732 0x0000, /* R155 */
1733 0x0000, /* R156 */
1734 0x0000, /* R157 */
1735 0x0000, /* R158 */
1736 0x0000, /* R159 */
1737 0x0000, /* R160 */
1738 0x0000, /* R161 */
1739 0x0000, /* R162 */
1740 0x0000, /* R163 */
1741 0x0000, /* R164 */
1742 0x0000, /* R165 */
1743 0x0000, /* R166 */
1744 0x0000, /* R167 */
1745 0x0000, /* R168 */
1746 0x0000, /* R169 */
1747 0x0000, /* R170 */
1748 0x0000, /* R171 */
1749 0x0000, /* R172 */
1750 0x0000, /* R173 */
1751 0x0000, /* R174 */
1752 0x0000, /* R175 */
1753 0x0000, /* R176 */
1754 0x0000, /* R177 */
1755 0x0000, /* R178 */
1756 0x0000, /* R179 */
1757 0x0000, /* R180 */
1758 0x0000, /* R181 */
1759 0x0000, /* R182 */
1760 0x0000, /* R183 */
1761 0x0000, /* R184 */
1762 0x0000, /* R185 */
1763 0x0000, /* R186 */
1764 0x0000, /* R187 */
1765 0x0000, /* R188 */
1766 0x0000, /* R189 */
1767 0x0000, /* R190 */
1768 0x0000, /* R191 */
1769 0x0000, /* R192 */
1770 0x0000, /* R193 */
1771 0x0000, /* R194 */
1772 0x0000, /* R195 */
1773 0x0000, /* R196 */
1774 0x0000, /* R197 */
1775 0x0000, /* R198 */
1776 0x0000, /* R199 */
1777 0x0000, /* R200 */
1778 0x0000, /* R201 */
1779 0x0000, /* R202 */
1780 0x0000, /* R203 */
1781 0x0000, /* R204 */
1782 0x0000, /* R205 */
1783 0x0000, /* R206 */
1784 0x0000, /* R207 */
1785 0x0000, /* R208 */
1786 0x0000, /* R209 */
1787 0x0000, /* R210 */
1788 0x0000, /* R211 */
1789 0x0000, /* R212 */
1790 0x0000, /* R213 */
1791 0x0000, /* R214 */
1792 0x0000, /* R215 */
1793 0x0000, /* R216 */
1794 0x0000, /* R217 */
1795 0x0000, /* R218 */
1796 0x0000, /* R219 */
1797 0x0000, /* R220 */
1798 0x0000, /* R221 */
1799 0x0000, /* R222 */
1800 0x0000, /* R223 */
1801 0x0000, /* R224 */
1802 0x0000, /* R225 */
1803 0x0000, /* R226 */
1804 0x0000, /* R227 */
1805 0x0000, /* R228 */
1806 0x0000, /* R229 */
1807 0x0000, /* R230 */
1808 0x0000, /* R231 */
1809 0x0000, /* R232 */
1810 0x0000, /* R233 */
1811 0x0000, /* R234 */
1812 0x0000, /* R235 */
1813 0x0000, /* R236 */
1814 0x0000, /* R237 */
1815 0x0000, /* R238 */
1816 0x0000, /* R239 */
1817 0x0000, /* R240 */
1818 0x0000, /* R241 */
1819 0x0000, /* R242 */
1820 0x0000, /* R243 */
1821 0x0000, /* R244 */
1822 0x0000, /* R245 */
1823 0x0000, /* R246 */
1824 0x0000, /* R247 */
1825 0x0000, /* R248 */
1826 0x0000, /* R249 */
1827 0x0000, /* R250 */
1828 0x0000, /* R251 */
1829 0x0000, /* R252 */
1830 0x0000, /* R253 */
1831 0x0000, /* R254 */
1832 0x0000, /* R255 */
1833 0x0003, /* R256 - Chip Revision */
1834 0x8004, /* R257 - Control Interface */
1835 0x0000, /* R258 */
1836 0x0000, /* R259 */
1837 0x0000, /* R260 */
1838 0x0000, /* R261 */
1839 0x0000, /* R262 */
1840 0x0000, /* R263 */
1841 0x0000, /* R264 */
1842 0x0000, /* R265 */
1843 0x0000, /* R266 */
1844 0x0000, /* R267 */
1845 0x0000, /* R268 */
1846 0x0000, /* R269 */
1847 0x0000, /* R270 */
1848 0x0000, /* R271 */
1849 0x0000, /* R272 - Write Sequencer Ctrl (1) */
1850 0x0000, /* R273 - Write Sequencer Ctrl (2) */
1851 0x0000, /* R274 */
1852 0x0000, /* R275 */
1853 0x0000, /* R276 */
1854 0x0000, /* R277 */
1855 0x0000, /* R278 */
1856 0x0000, /* R279 */
1857 0x0000, /* R280 */
1858 0x0000, /* R281 */
1859 0x0000, /* R282 */
1860 0x0000, /* R283 */
1861 0x0000, /* R284 */
1862 0x0000, /* R285 */
1863 0x0000, /* R286 */
1864 0x0000, /* R287 */
1865 0x0000, /* R288 */
1866 0x0000, /* R289 */
1867 0x0000, /* R290 */
1868 0x0000, /* R291 */
1869 0x0000, /* R292 */
1870 0x0000, /* R293 */
1871 0x0000, /* R294 */
1872 0x0000, /* R295 */
1873 0x0000, /* R296 */
1874 0x0000, /* R297 */
1875 0x0000, /* R298 */
1876 0x0000, /* R299 */
1877 0x0000, /* R300 */
1878 0x0000, /* R301 */
1879 0x0000, /* R302 */
1880 0x0000, /* R303 */
1881 0x0000, /* R304 */
1882 0x0000, /* R305 */
1883 0x0000, /* R306 */
1884 0x0000, /* R307 */
1885 0x0000, /* R308 */
1886 0x0000, /* R309 */
1887 0x0000, /* R310 */
1888 0x0000, /* R311 */
1889 0x0000, /* R312 */
1890 0x0000, /* R313 */
1891 0x0000, /* R314 */
1892 0x0000, /* R315 */
1893 0x0000, /* R316 */
1894 0x0000, /* R317 */
1895 0x0000, /* R318 */
1896 0x0000, /* R319 */
1897 0x0000, /* R320 */
1898 0x0000, /* R321 */
1899 0x0000, /* R322 */
1900 0x0000, /* R323 */
1901 0x0000, /* R324 */
1902 0x0000, /* R325 */
1903 0x0000, /* R326 */
1904 0x0000, /* R327 */
1905 0x0000, /* R328 */
1906 0x0000, /* R329 */
1907 0x0000, /* R330 */
1908 0x0000, /* R331 */
1909 0x0000, /* R332 */
1910 0x0000, /* R333 */
1911 0x0000, /* R334 */
1912 0x0000, /* R335 */
1913 0x0000, /* R336 */
1914 0x0000, /* R337 */
1915 0x0000, /* R338 */
1916 0x0000, /* R339 */
1917 0x0000, /* R340 */
1918 0x0000, /* R341 */
1919 0x0000, /* R342 */
1920 0x0000, /* R343 */
1921 0x0000, /* R344 */
1922 0x0000, /* R345 */
1923 0x0000, /* R346 */
1924 0x0000, /* R347 */
1925 0x0000, /* R348 */
1926 0x0000, /* R349 */
1927 0x0000, /* R350 */
1928 0x0000, /* R351 */
1929 0x0000, /* R352 */
1930 0x0000, /* R353 */
1931 0x0000, /* R354 */
1932 0x0000, /* R355 */
1933 0x0000, /* R356 */
1934 0x0000, /* R357 */
1935 0x0000, /* R358 */
1936 0x0000, /* R359 */
1937 0x0000, /* R360 */
1938 0x0000, /* R361 */
1939 0x0000, /* R362 */
1940 0x0000, /* R363 */
1941 0x0000, /* R364 */
1942 0x0000, /* R365 */
1943 0x0000, /* R366 */
1944 0x0000, /* R367 */
1945 0x0000, /* R368 */
1946 0x0000, /* R369 */
1947 0x0000, /* R370 */
1948 0x0000, /* R371 */
1949 0x0000, /* R372 */
1950 0x0000, /* R373 */
1951 0x0000, /* R374 */
1952 0x0000, /* R375 */
1953 0x0000, /* R376 */
1954 0x0000, /* R377 */
1955 0x0000, /* R378 */
1956 0x0000, /* R379 */
1957 0x0000, /* R380 */
1958 0x0000, /* R381 */
1959 0x0000, /* R382 */
1960 0x0000, /* R383 */
1961 0x0000, /* R384 */
1962 0x0000, /* R385 */
1963 0x0000, /* R386 */
1964 0x0000, /* R387 */
1965 0x0000, /* R388 */
1966 0x0000, /* R389 */
1967 0x0000, /* R390 */
1968 0x0000, /* R391 */
1969 0x0000, /* R392 */
1970 0x0000, /* R393 */
1971 0x0000, /* R394 */
1972 0x0000, /* R395 */
1973 0x0000, /* R396 */
1974 0x0000, /* R397 */
1975 0x0000, /* R398 */
1976 0x0000, /* R399 */
1977 0x0000, /* R400 */
1978 0x0000, /* R401 */
1979 0x0000, /* R402 */
1980 0x0000, /* R403 */
1981 0x0000, /* R404 */
1982 0x0000, /* R405 */
1983 0x0000, /* R406 */
1984 0x0000, /* R407 */
1985 0x0000, /* R408 */
1986 0x0000, /* R409 */
1987 0x0000, /* R410 */
1988 0x0000, /* R411 */
1989 0x0000, /* R412 */
1990 0x0000, /* R413 */
1991 0x0000, /* R414 */
1992 0x0000, /* R415 */
1993 0x0000, /* R416 */
1994 0x0000, /* R417 */
1995 0x0000, /* R418 */
1996 0x0000, /* R419 */
1997 0x0000, /* R420 */
1998 0x0000, /* R421 */
1999 0x0000, /* R422 */
2000 0x0000, /* R423 */
2001 0x0000, /* R424 */
2002 0x0000, /* R425 */
2003 0x0000, /* R426 */
2004 0x0000, /* R427 */
2005 0x0000, /* R428 */
2006 0x0000, /* R429 */
2007 0x0000, /* R430 */
2008 0x0000, /* R431 */
2009 0x0000, /* R432 */
2010 0x0000, /* R433 */
2011 0x0000, /* R434 */
2012 0x0000, /* R435 */
2013 0x0000, /* R436 */
2014 0x0000, /* R437 */
2015 0x0000, /* R438 */
2016 0x0000, /* R439 */
2017 0x0000, /* R440 */
2018 0x0000, /* R441 */
2019 0x0000, /* R442 */
2020 0x0000, /* R443 */
2021 0x0000, /* R444 */
2022 0x0000, /* R445 */
2023 0x0000, /* R446 */
2024 0x0000, /* R447 */
2025 0x0000, /* R448 */
2026 0x0000, /* R449 */
2027 0x0000, /* R450 */
2028 0x0000, /* R451 */
2029 0x0000, /* R452 */
2030 0x0000, /* R453 */
2031 0x0000, /* R454 */
2032 0x0000, /* R455 */
2033 0x0000, /* R456 */
2034 0x0000, /* R457 */
2035 0x0000, /* R458 */
2036 0x0000, /* R459 */
2037 0x0000, /* R460 */
2038 0x0000, /* R461 */
2039 0x0000, /* R462 */
2040 0x0000, /* R463 */
2041 0x0000, /* R464 */
2042 0x0000, /* R465 */
2043 0x0000, /* R466 */
2044 0x0000, /* R467 */
2045 0x0000, /* R468 */
2046 0x0000, /* R469 */
2047 0x0000, /* R470 */
2048 0x0000, /* R471 */
2049 0x0000, /* R472 */
2050 0x0000, /* R473 */
2051 0x0000, /* R474 */
2052 0x0000, /* R475 */
2053 0x0000, /* R476 */
2054 0x0000, /* R477 */
2055 0x0000, /* R478 */
2056 0x0000, /* R479 */
2057 0x0000, /* R480 */
2058 0x0000, /* R481 */
2059 0x0000, /* R482 */
2060 0x0000, /* R483 */
2061 0x0000, /* R484 */
2062 0x0000, /* R485 */
2063 0x0000, /* R486 */
2064 0x0000, /* R487 */
2065 0x0000, /* R488 */
2066 0x0000, /* R489 */
2067 0x0000, /* R490 */
2068 0x0000, /* R491 */
2069 0x0000, /* R492 */
2070 0x0000, /* R493 */
2071 0x0000, /* R494 */
2072 0x0000, /* R495 */
2073 0x0000, /* R496 */
2074 0x0000, /* R497 */
2075 0x0000, /* R498 */
2076 0x0000, /* R499 */
2077 0x0000, /* R500 */
2078 0x0000, /* R501 */
2079 0x0000, /* R502 */
2080 0x0000, /* R503 */
2081 0x0000, /* R504 */
2082 0x0000, /* R505 */
2083 0x0000, /* R506 */
2084 0x0000, /* R507 */
2085 0x0000, /* R508 */
2086 0x0000, /* R509 */
2087 0x0000, /* R510 */
2088 0x0000, /* R511 */
2089 0x0000, /* R512 - AIF1 Clocking (1) */
2090 0x0000, /* R513 - AIF1 Clocking (2) */
2091 0x0000, /* R514 */
2092 0x0000, /* R515 */
2093 0x0000, /* R516 - AIF2 Clocking (1) */
2094 0x0000, /* R517 - AIF2 Clocking (2) */
2095 0x0000, /* R518 */
2096 0x0000, /* R519 */
2097 0x0000, /* R520 - Clocking (1) */
2098 0x0000, /* R521 - Clocking (2) */
2099 0x0000, /* R522 */
2100 0x0000, /* R523 */
2101 0x0000, /* R524 */
2102 0x0000, /* R525 */
2103 0x0000, /* R526 */
2104 0x0000, /* R527 */
2105 0x0083, /* R528 - AIF1 Rate */
2106 0x0083, /* R529 - AIF2 Rate */
2107 0x0000, /* R530 - Rate Status */
2108 0x0000, /* R531 */
2109 0x0000, /* R532 */
2110 0x0000, /* R533 */
2111 0x0000, /* R534 */
2112 0x0000, /* R535 */
2113 0x0000, /* R536 */
2114 0x0000, /* R537 */
2115 0x0000, /* R538 */
2116 0x0000, /* R539 */
2117 0x0000, /* R540 */
2118 0x0000, /* R541 */
2119 0x0000, /* R542 */
2120 0x0000, /* R543 */
2121 0x0000, /* R544 - FLL1 Control (1) */
2122 0x0000, /* R545 - FLL1 Control (2) */
2123 0x0000, /* R546 - FLL1 Control (3) */
2124 0x0000, /* R547 - FLL1 Control (4) */
2125 0x0C80, /* R548 - FLL1 Control (5) */
2126 0x0000, /* R549 */
2127 0x0000, /* R550 */
2128 0x0000, /* R551 */
2129 0x0000, /* R552 */
2130 0x0000, /* R553 */
2131 0x0000, /* R554 */
2132 0x0000, /* R555 */
2133 0x0000, /* R556 */
2134 0x0000, /* R557 */
2135 0x0000, /* R558 */
2136 0x0000, /* R559 */
2137 0x0000, /* R560 */
2138 0x0000, /* R561 */
2139 0x0000, /* R562 */
2140 0x0000, /* R563 */
2141 0x0000, /* R564 */
2142 0x0000, /* R565 */
2143 0x0000, /* R566 */
2144 0x0000, /* R567 */
2145 0x0000, /* R568 */
2146 0x0000, /* R569 */
2147 0x0000, /* R570 */
2148 0x0000, /* R571 */
2149 0x0000, /* R572 */
2150 0x0000, /* R573 */
2151 0x0000, /* R574 */
2152 0x0000, /* R575 */
2153 0x0000, /* R576 - FLL2 Control (1) */
2154 0x0000, /* R577 - FLL2 Control (2) */
2155 0x0000, /* R578 - FLL2 Control (3) */
2156 0x0000, /* R579 - FLL2 Control (4) */
2157 0x0C80, /* R580 - FLL2 Control (5) */
2158 0x0000, /* R581 */
2159 0x0000, /* R582 */
2160 0x0000, /* R583 */
2161 0x0000, /* R584 */
2162 0x0000, /* R585 */
2163 0x0000, /* R586 */
2164 0x0000, /* R587 */
2165 0x0000, /* R588 */
2166 0x0000, /* R589 */
2167 0x0000, /* R590 */
2168 0x0000, /* R591 */
2169 0x0000, /* R592 */
2170 0x0000, /* R593 */
2171 0x0000, /* R594 */
2172 0x0000, /* R595 */
2173 0x0000, /* R596 */
2174 0x0000, /* R597 */
2175 0x0000, /* R598 */
2176 0x0000, /* R599 */
2177 0x0000, /* R600 */
2178 0x0000, /* R601 */
2179 0x0000, /* R602 */
2180 0x0000, /* R603 */
2181 0x0000, /* R604 */
2182 0x0000, /* R605 */
2183 0x0000, /* R606 */
2184 0x0000, /* R607 */
2185 0x0000, /* R608 */
2186 0x0000, /* R609 */
2187 0x0000, /* R610 */
2188 0x0000, /* R611 */
2189 0x0000, /* R612 */
2190 0x0000, /* R613 */
2191 0x0000, /* R614 */
2192 0x0000, /* R615 */
2193 0x0000, /* R616 */
2194 0x0000, /* R617 */
2195 0x0000, /* R618 */
2196 0x0000, /* R619 */
2197 0x0000, /* R620 */
2198 0x0000, /* R621 */
2199 0x0000, /* R622 */
2200 0x0000, /* R623 */
2201 0x0000, /* R624 */
2202 0x0000, /* R625 */
2203 0x0000, /* R626 */
2204 0x0000, /* R627 */
2205 0x0000, /* R628 */
2206 0x0000, /* R629 */
2207 0x0000, /* R630 */
2208 0x0000, /* R631 */
2209 0x0000, /* R632 */
2210 0x0000, /* R633 */
2211 0x0000, /* R634 */
2212 0x0000, /* R635 */
2213 0x0000, /* R636 */
2214 0x0000, /* R637 */
2215 0x0000, /* R638 */
2216 0x0000, /* R639 */
2217 0x0000, /* R640 */
2218 0x0000, /* R641 */
2219 0x0000, /* R642 */
2220 0x0000, /* R643 */
2221 0x0000, /* R644 */
2222 0x0000, /* R645 */
2223 0x0000, /* R646 */
2224 0x0000, /* R647 */
2225 0x0000, /* R648 */
2226 0x0000, /* R649 */
2227 0x0000, /* R650 */
2228 0x0000, /* R651 */
2229 0x0000, /* R652 */
2230 0x0000, /* R653 */
2231 0x0000, /* R654 */
2232 0x0000, /* R655 */
2233 0x0000, /* R656 */
2234 0x0000, /* R657 */
2235 0x0000, /* R658 */
2236 0x0000, /* R659 */
2237 0x0000, /* R660 */
2238 0x0000, /* R661 */
2239 0x0000, /* R662 */
2240 0x0000, /* R663 */
2241 0x0000, /* R664 */
2242 0x0000, /* R665 */
2243 0x0000, /* R666 */
2244 0x0000, /* R667 */
2245 0x0000, /* R668 */
2246 0x0000, /* R669 */
2247 0x0000, /* R670 */
2248 0x0000, /* R671 */
2249 0x0000, /* R672 */
2250 0x0000, /* R673 */
2251 0x0000, /* R674 */
2252 0x0000, /* R675 */
2253 0x0000, /* R676 */
2254 0x0000, /* R677 */
2255 0x0000, /* R678 */
2256 0x0000, /* R679 */
2257 0x0000, /* R680 */
2258 0x0000, /* R681 */
2259 0x0000, /* R682 */
2260 0x0000, /* R683 */
2261 0x0000, /* R684 */
2262 0x0000, /* R685 */
2263 0x0000, /* R686 */
2264 0x0000, /* R687 */
2265 0x0000, /* R688 */
2266 0x0000, /* R689 */
2267 0x0000, /* R690 */
2268 0x0000, /* R691 */
2269 0x0000, /* R692 */
2270 0x0000, /* R693 */
2271 0x0000, /* R694 */
2272 0x0000, /* R695 */
2273 0x0000, /* R696 */
2274 0x0000, /* R697 */
2275 0x0000, /* R698 */
2276 0x0000, /* R699 */
2277 0x0000, /* R700 */
2278 0x0000, /* R701 */
2279 0x0000, /* R702 */
2280 0x0000, /* R703 */
2281 0x0000, /* R704 */
2282 0x0000, /* R705 */
2283 0x0000, /* R706 */
2284 0x0000, /* R707 */
2285 0x0000, /* R708 */
2286 0x0000, /* R709 */
2287 0x0000, /* R710 */
2288 0x0000, /* R711 */
2289 0x0000, /* R712 */
2290 0x0000, /* R713 */
2291 0x0000, /* R714 */
2292 0x0000, /* R715 */
2293 0x0000, /* R716 */
2294 0x0000, /* R717 */
2295 0x0000, /* R718 */
2296 0x0000, /* R719 */
2297 0x0000, /* R720 */
2298 0x0000, /* R721 */
2299 0x0000, /* R722 */
2300 0x0000, /* R723 */
2301 0x0000, /* R724 */
2302 0x0000, /* R725 */
2303 0x0000, /* R726 */
2304 0x0000, /* R727 */
2305 0x0000, /* R728 */
2306 0x0000, /* R729 */
2307 0x0000, /* R730 */
2308 0x0000, /* R731 */
2309 0x0000, /* R732 */
2310 0x0000, /* R733 */
2311 0x0000, /* R734 */
2312 0x0000, /* R735 */
2313 0x0000, /* R736 */
2314 0x0000, /* R737 */
2315 0x0000, /* R738 */
2316 0x0000, /* R739 */
2317 0x0000, /* R740 */
2318 0x0000, /* R741 */
2319 0x0000, /* R742 */
2320 0x0000, /* R743 */
2321 0x0000, /* R744 */
2322 0x0000, /* R745 */
2323 0x0000, /* R746 */
2324 0x0000, /* R747 */
2325 0x0000, /* R748 */
2326 0x0000, /* R749 */
2327 0x0000, /* R750 */
2328 0x0000, /* R751 */
2329 0x0000, /* R752 */
2330 0x0000, /* R753 */
2331 0x0000, /* R754 */
2332 0x0000, /* R755 */
2333 0x0000, /* R756 */
2334 0x0000, /* R757 */
2335 0x0000, /* R758 */
2336 0x0000, /* R759 */
2337 0x0000, /* R760 */
2338 0x0000, /* R761 */
2339 0x0000, /* R762 */
2340 0x0000, /* R763 */
2341 0x0000, /* R764 */
2342 0x0000, /* R765 */
2343 0x0000, /* R766 */
2344 0x0000, /* R767 */
2345 0x4050, /* R768 - AIF1 Control (1) */
2346 0x4000, /* R769 - AIF1 Control (2) */
2347 0x0000, /* R770 - AIF1 Master/Slave */
2348 0x0040, /* R771 - AIF1 BCLK */
2349 0x0040, /* R772 - AIF1ADC LRCLK */
2350 0x0040, /* R773 - AIF1DAC LRCLK */
2351 0x0004, /* R774 - AIF1DAC Data */
2352 0x0100, /* R775 - AIF1ADC Data */
2353 0x0000, /* R776 */
2354 0x0000, /* R777 */
2355 0x0000, /* R778 */
2356 0x0000, /* R779 */
2357 0x0000, /* R780 */
2358 0x0000, /* R781 */
2359 0x0000, /* R782 */
2360 0x0000, /* R783 */
2361 0x4050, /* R784 - AIF2 Control (1) */
2362 0x4000, /* R785 - AIF2 Control (2) */
2363 0x0000, /* R786 - AIF2 Master/Slave */
2364 0x0040, /* R787 - AIF2 BCLK */
2365 0x0040, /* R788 - AIF2ADC LRCLK */
2366 0x0040, /* R789 - AIF2DAC LRCLK */
2367 0x0000, /* R790 - AIF2DAC Data */
2368 0x0000, /* R791 - AIF2ADC Data */
2369 0x0000, /* R792 */
2370 0x0000, /* R793 */
2371 0x0000, /* R794 */
2372 0x0000, /* R795 */
2373 0x0000, /* R796 */
2374 0x0000, /* R797 */
2375 0x0000, /* R798 */
2376 0x0000, /* R799 */
2377 0x0000, /* R800 */
2378 0x0000, /* R801 */
2379 0x0000, /* R802 */
2380 0x0000, /* R803 */
2381 0x0000, /* R804 */
2382 0x0000, /* R805 */
2383 0x0000, /* R806 */
2384 0x0000, /* R807 */
2385 0x0000, /* R808 */
2386 0x0000, /* R809 */
2387 0x0000, /* R810 */
2388 0x0000, /* R811 */
2389 0x0000, /* R812 */
2390 0x0000, /* R813 */
2391 0x0000, /* R814 */
2392 0x0000, /* R815 */
2393 0x0000, /* R816 */
2394 0x0000, /* R817 */
2395 0x0000, /* R818 */
2396 0x0000, /* R819 */
2397 0x0000, /* R820 */
2398 0x0000, /* R821 */
2399 0x0000, /* R822 */
2400 0x0000, /* R823 */
2401 0x0000, /* R824 */
2402 0x0000, /* R825 */
2403 0x0000, /* R826 */
2404 0x0000, /* R827 */
2405 0x0000, /* R828 */
2406 0x0000, /* R829 */
2407 0x0000, /* R830 */
2408 0x0000, /* R831 */
2409 0x0000, /* R832 */
2410 0x0000, /* R833 */
2411 0x0000, /* R834 */
2412 0x0000, /* R835 */
2413 0x0000, /* R836 */
2414 0x0000, /* R837 */
2415 0x0000, /* R838 */
2416 0x0000, /* R839 */
2417 0x0000, /* R840 */
2418 0x0000, /* R841 */
2419 0x0000, /* R842 */
2420 0x0000, /* R843 */
2421 0x0000, /* R844 */
2422 0x0000, /* R845 */
2423 0x0000, /* R846 */
2424 0x0000, /* R847 */
2425 0x0000, /* R848 */
2426 0x0000, /* R849 */
2427 0x0000, /* R850 */
2428 0x0000, /* R851 */
2429 0x0000, /* R852 */
2430 0x0000, /* R853 */
2431 0x0000, /* R854 */
2432 0x0000, /* R855 */
2433 0x0000, /* R856 */
2434 0x0000, /* R857 */
2435 0x0000, /* R858 */
2436 0x0000, /* R859 */
2437 0x0000, /* R860 */
2438 0x0000, /* R861 */
2439 0x0000, /* R862 */
2440 0x0000, /* R863 */
2441 0x0000, /* R864 */
2442 0x0000, /* R865 */
2443 0x0000, /* R866 */
2444 0x0000, /* R867 */
2445 0x0000, /* R868 */
2446 0x0000, /* R869 */
2447 0x0000, /* R870 */
2448 0x0000, /* R871 */
2449 0x0000, /* R872 */
2450 0x0000, /* R873 */
2451 0x0000, /* R874 */
2452 0x0000, /* R875 */
2453 0x0000, /* R876 */
2454 0x0000, /* R877 */
2455 0x0000, /* R878 */
2456 0x0000, /* R879 */
2457 0x0000, /* R880 */
2458 0x0000, /* R881 */
2459 0x0000, /* R882 */
2460 0x0000, /* R883 */
2461 0x0000, /* R884 */
2462 0x0000, /* R885 */
2463 0x0000, /* R886 */
2464 0x0000, /* R887 */
2465 0x0000, /* R888 */
2466 0x0000, /* R889 */
2467 0x0000, /* R890 */
2468 0x0000, /* R891 */
2469 0x0000, /* R892 */
2470 0x0000, /* R893 */
2471 0x0000, /* R894 */
2472 0x0000, /* R895 */
2473 0x0000, /* R896 */
2474 0x0000, /* R897 */
2475 0x0000, /* R898 */
2476 0x0000, /* R899 */
2477 0x0000, /* R900 */
2478 0x0000, /* R901 */
2479 0x0000, /* R902 */
2480 0x0000, /* R903 */
2481 0x0000, /* R904 */
2482 0x0000, /* R905 */
2483 0x0000, /* R906 */
2484 0x0000, /* R907 */
2485 0x0000, /* R908 */
2486 0x0000, /* R909 */
2487 0x0000, /* R910 */
2488 0x0000, /* R911 */
2489 0x0000, /* R912 */
2490 0x0000, /* R913 */
2491 0x0000, /* R914 */
2492 0x0000, /* R915 */
2493 0x0000, /* R916 */
2494 0x0000, /* R917 */
2495 0x0000, /* R918 */
2496 0x0000, /* R919 */
2497 0x0000, /* R920 */
2498 0x0000, /* R921 */
2499 0x0000, /* R922 */
2500 0x0000, /* R923 */
2501 0x0000, /* R924 */
2502 0x0000, /* R925 */
2503 0x0000, /* R926 */
2504 0x0000, /* R927 */
2505 0x0000, /* R928 */
2506 0x0000, /* R929 */
2507 0x0000, /* R930 */
2508 0x0000, /* R931 */
2509 0x0000, /* R932 */
2510 0x0000, /* R933 */
2511 0x0000, /* R934 */
2512 0x0000, /* R935 */
2513 0x0000, /* R936 */
2514 0x0000, /* R937 */
2515 0x0000, /* R938 */
2516 0x0000, /* R939 */
2517 0x0000, /* R940 */
2518 0x0000, /* R941 */
2519 0x0000, /* R942 */
2520 0x0000, /* R943 */
2521 0x0000, /* R944 */
2522 0x0000, /* R945 */
2523 0x0000, /* R946 */
2524 0x0000, /* R947 */
2525 0x0000, /* R948 */
2526 0x0000, /* R949 */
2527 0x0000, /* R950 */
2528 0x0000, /* R951 */
2529 0x0000, /* R952 */
2530 0x0000, /* R953 */
2531 0x0000, /* R954 */
2532 0x0000, /* R955 */
2533 0x0000, /* R956 */
2534 0x0000, /* R957 */
2535 0x0000, /* R958 */
2536 0x0000, /* R959 */
2537 0x0000, /* R960 */
2538 0x0000, /* R961 */
2539 0x0000, /* R962 */
2540 0x0000, /* R963 */
2541 0x0000, /* R964 */
2542 0x0000, /* R965 */
2543 0x0000, /* R966 */
2544 0x0000, /* R967 */
2545 0x0000, /* R968 */
2546 0x0000, /* R969 */
2547 0x0000, /* R970 */
2548 0x0000, /* R971 */
2549 0x0000, /* R972 */
2550 0x0000, /* R973 */
2551 0x0000, /* R974 */
2552 0x0000, /* R975 */
2553 0x0000, /* R976 */
2554 0x0000, /* R977 */
2555 0x0000, /* R978 */
2556 0x0000, /* R979 */
2557 0x0000, /* R980 */
2558 0x0000, /* R981 */
2559 0x0000, /* R982 */
2560 0x0000, /* R983 */
2561 0x0000, /* R984 */
2562 0x0000, /* R985 */
2563 0x0000, /* R986 */
2564 0x0000, /* R987 */
2565 0x0000, /* R988 */
2566 0x0000, /* R989 */
2567 0x0000, /* R990 */
2568 0x0000, /* R991 */
2569 0x0000, /* R992 */
2570 0x0000, /* R993 */
2571 0x0000, /* R994 */
2572 0x0000, /* R995 */
2573 0x0000, /* R996 */
2574 0x0000, /* R997 */
2575 0x0000, /* R998 */
2576 0x0000, /* R999 */
2577 0x0000, /* R1000 */
2578 0x0000, /* R1001 */
2579 0x0000, /* R1002 */
2580 0x0000, /* R1003 */
2581 0x0000, /* R1004 */
2582 0x0000, /* R1005 */
2583 0x0000, /* R1006 */
2584 0x0000, /* R1007 */
2585 0x0000, /* R1008 */
2586 0x0000, /* R1009 */
2587 0x0000, /* R1010 */
2588 0x0000, /* R1011 */
2589 0x0000, /* R1012 */
2590 0x0000, /* R1013 */
2591 0x0000, /* R1014 */
2592 0x0000, /* R1015 */
2593 0x0000, /* R1016 */
2594 0x0000, /* R1017 */
2595 0x0000, /* R1018 */
2596 0x0000, /* R1019 */
2597 0x0000, /* R1020 */
2598 0x0000, /* R1021 */
2599 0x0000, /* R1022 */
2600 0x0000, /* R1023 */
2601 0x00C0, /* R1024 - AIF1 ADC1 Left Volume */
2602 0x00C0, /* R1025 - AIF1 ADC1 Right Volume */
2603 0x00C0, /* R1026 - AIF1 DAC1 Left Volume */
2604 0x00C0, /* R1027 - AIF1 DAC1 Right Volume */
2605 0x00C0, /* R1028 - AIF1 ADC2 Left Volume */
2606 0x00C0, /* R1029 - AIF1 ADC2 Right Volume */
2607 0x00C0, /* R1030 - AIF1 DAC2 Left Volume */
2608 0x00C0, /* R1031 - AIF1 DAC2 Right Volume */
2609 0x0000, /* R1032 */
2610 0x0000, /* R1033 */
2611 0x0000, /* R1034 */
2612 0x0000, /* R1035 */
2613 0x0000, /* R1036 */
2614 0x0000, /* R1037 */
2615 0x0000, /* R1038 */
2616 0x0000, /* R1039 */
2617 0x0000, /* R1040 - AIF1 ADC1 Filters */
2618 0x0000, /* R1041 - AIF1 ADC2 Filters */
2619 0x0000, /* R1042 */
2620 0x0000, /* R1043 */
2621 0x0000, /* R1044 */
2622 0x0000, /* R1045 */
2623 0x0000, /* R1046 */
2624 0x0000, /* R1047 */
2625 0x0000, /* R1048 */
2626 0x0000, /* R1049 */
2627 0x0000, /* R1050 */
2628 0x0000, /* R1051 */
2629 0x0000, /* R1052 */
2630 0x0000, /* R1053 */
2631 0x0000, /* R1054 */
2632 0x0000, /* R1055 */
2633 0x0200, /* R1056 - AIF1 DAC1 Filters (1) */
2634 0x0010, /* R1057 - AIF1 DAC1 Filters (2) */
2635 0x0200, /* R1058 - AIF1 DAC2 Filters (1) */
2636 0x0010, /* R1059 - AIF1 DAC2 Filters (2) */
2637 0x0000, /* R1060 */
2638 0x0000, /* R1061 */
2639 0x0000, /* R1062 */
2640 0x0000, /* R1063 */
2641 0x0000, /* R1064 */
2642 0x0000, /* R1065 */
2643 0x0000, /* R1066 */
2644 0x0000, /* R1067 */
2645 0x0000, /* R1068 */
2646 0x0000, /* R1069 */
2647 0x0000, /* R1070 */
2648 0x0000, /* R1071 */
2649 0x0000, /* R1072 */
2650 0x0000, /* R1073 */
2651 0x0000, /* R1074 */
2652 0x0000, /* R1075 */
2653 0x0000, /* R1076 */
2654 0x0000, /* R1077 */
2655 0x0000, /* R1078 */
2656 0x0000, /* R1079 */
2657 0x0000, /* R1080 */
2658 0x0000, /* R1081 */
2659 0x0000, /* R1082 */
2660 0x0000, /* R1083 */
2661 0x0000, /* R1084 */
2662 0x0000, /* R1085 */
2663 0x0000, /* R1086 */
2664 0x0000, /* R1087 */
2665 0x0098, /* R1088 - AIF1 DRC1 (1) */
2666 0x0845, /* R1089 - AIF1 DRC1 (2) */
2667 0x0000, /* R1090 - AIF1 DRC1 (3) */
2668 0x0000, /* R1091 - AIF1 DRC1 (4) */
2669 0x0000, /* R1092 - AIF1 DRC1 (5) */
2670 0x0000, /* R1093 */
2671 0x0000, /* R1094 */
2672 0x0000, /* R1095 */
2673 0x0000, /* R1096 */
2674 0x0000, /* R1097 */
2675 0x0000, /* R1098 */
2676 0x0000, /* R1099 */
2677 0x0000, /* R1100 */
2678 0x0000, /* R1101 */
2679 0x0000, /* R1102 */
2680 0x0000, /* R1103 */
2681 0x0098, /* R1104 - AIF1 DRC2 (1) */
2682 0x0845, /* R1105 - AIF1 DRC2 (2) */
2683 0x0000, /* R1106 - AIF1 DRC2 (3) */
2684 0x0000, /* R1107 - AIF1 DRC2 (4) */
2685 0x0000, /* R1108 - AIF1 DRC2 (5) */
2686 0x0000, /* R1109 */
2687 0x0000, /* R1110 */
2688 0x0000, /* R1111 */
2689 0x0000, /* R1112 */
2690 0x0000, /* R1113 */
2691 0x0000, /* R1114 */
2692 0x0000, /* R1115 */
2693 0x0000, /* R1116 */
2694 0x0000, /* R1117 */
2695 0x0000, /* R1118 */
2696 0x0000, /* R1119 */
2697 0x0000, /* R1120 */
2698 0x0000, /* R1121 */
2699 0x0000, /* R1122 */
2700 0x0000, /* R1123 */
2701 0x0000, /* R1124 */
2702 0x0000, /* R1125 */
2703 0x0000, /* R1126 */
2704 0x0000, /* R1127 */
2705 0x0000, /* R1128 */
2706 0x0000, /* R1129 */
2707 0x0000, /* R1130 */
2708 0x0000, /* R1131 */
2709 0x0000, /* R1132 */
2710 0x0000, /* R1133 */
2711 0x0000, /* R1134 */
2712 0x0000, /* R1135 */
2713 0x0000, /* R1136 */
2714 0x0000, /* R1137 */
2715 0x0000, /* R1138 */
2716 0x0000, /* R1139 */
2717 0x0000, /* R1140 */
2718 0x0000, /* R1141 */
2719 0x0000, /* R1142 */
2720 0x0000, /* R1143 */
2721 0x0000, /* R1144 */
2722 0x0000, /* R1145 */
2723 0x0000, /* R1146 */
2724 0x0000, /* R1147 */
2725 0x0000, /* R1148 */
2726 0x0000, /* R1149 */
2727 0x0000, /* R1150 */
2728 0x0000, /* R1151 */
2729 0x6318, /* R1152 - AIF1 DAC1 EQ Gains (1) */
2730 0x6300, /* R1153 - AIF1 DAC1 EQ Gains (2) */
2731 0x0FCA, /* R1154 - AIF1 DAC1 EQ Band 1 A */
2732 0x0400, /* R1155 - AIF1 DAC1 EQ Band 1 B */
2733 0x00D8, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
2734 0x1EB5, /* R1157 - AIF1 DAC1 EQ Band 2 A */
2735 0xF145, /* R1158 - AIF1 DAC1 EQ Band 2 B */
2736 0x0B75, /* R1159 - AIF1 DAC1 EQ Band 2 C */
2737 0x01C5, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
2738 0x1C58, /* R1161 - AIF1 DAC1 EQ Band 3 A */
2739 0xF373, /* R1162 - AIF1 DAC1 EQ Band 3 B */
2740 0x0A54, /* R1163 - AIF1 DAC1 EQ Band 3 C */
2741 0x0558, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
2742 0x168E, /* R1165 - AIF1 DAC1 EQ Band 4 A */
2743 0xF829, /* R1166 - AIF1 DAC1 EQ Band 4 B */
2744 0x07AD, /* R1167 - AIF1 DAC1 EQ Band 4 C */
2745 0x1103, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
2746 0x0564, /* R1169 - AIF1 DAC1 EQ Band 5 A */
2747 0x0559, /* R1170 - AIF1 DAC1 EQ Band 5 B */
2748 0x4000, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
2749 0x0000, /* R1172 */
2750 0x0000, /* R1173 */
2751 0x0000, /* R1174 */
2752 0x0000, /* R1175 */
2753 0x0000, /* R1176 */
2754 0x0000, /* R1177 */
2755 0x0000, /* R1178 */
2756 0x0000, /* R1179 */
2757 0x0000, /* R1180 */
2758 0x0000, /* R1181 */
2759 0x0000, /* R1182 */
2760 0x0000, /* R1183 */
2761 0x6318, /* R1184 - AIF1 DAC2 EQ Gains (1) */
2762 0x6300, /* R1185 - AIF1 DAC2 EQ Gains (2) */
2763 0x0FCA, /* R1186 - AIF1 DAC2 EQ Band 1 A */
2764 0x0400, /* R1187 - AIF1 DAC2 EQ Band 1 B */
2765 0x00D8, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
2766 0x1EB5, /* R1189 - AIF1 DAC2 EQ Band 2 A */
2767 0xF145, /* R1190 - AIF1 DAC2 EQ Band 2 B */
2768 0x0B75, /* R1191 - AIF1 DAC2 EQ Band 2 C */
2769 0x01C5, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
2770 0x1C58, /* R1193 - AIF1 DAC2 EQ Band 3 A */
2771 0xF373, /* R1194 - AIF1 DAC2 EQ Band 3 B */
2772 0x0A54, /* R1195 - AIF1 DAC2 EQ Band 3 C */
2773 0x0558, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
2774 0x168E, /* R1197 - AIF1 DAC2 EQ Band 4 A */
2775 0xF829, /* R1198 - AIF1 DAC2 EQ Band 4 B */
2776 0x07AD, /* R1199 - AIF1 DAC2 EQ Band 4 C */
2777 0x1103, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
2778 0x0564, /* R1201 - AIF1 DAC2 EQ Band 5 A */
2779 0x0559, /* R1202 - AIF1 DAC2 EQ Band 5 B */
2780 0x4000, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
2781 0x0000, /* R1204 */
2782 0x0000, /* R1205 */
2783 0x0000, /* R1206 */
2784 0x0000, /* R1207 */
2785 0x0000, /* R1208 */
2786 0x0000, /* R1209 */
2787 0x0000, /* R1210 */
2788 0x0000, /* R1211 */
2789 0x0000, /* R1212 */
2790 0x0000, /* R1213 */
2791 0x0000, /* R1214 */
2792 0x0000, /* R1215 */
2793 0x0000, /* R1216 */
2794 0x0000, /* R1217 */
2795 0x0000, /* R1218 */
2796 0x0000, /* R1219 */
2797 0x0000, /* R1220 */
2798 0x0000, /* R1221 */
2799 0x0000, /* R1222 */
2800 0x0000, /* R1223 */
2801 0x0000, /* R1224 */
2802 0x0000, /* R1225 */
2803 0x0000, /* R1226 */
2804 0x0000, /* R1227 */
2805 0x0000, /* R1228 */
2806 0x0000, /* R1229 */
2807 0x0000, /* R1230 */
2808 0x0000, /* R1231 */
2809 0x0000, /* R1232 */
2810 0x0000, /* R1233 */
2811 0x0000, /* R1234 */
2812 0x0000, /* R1235 */
2813 0x0000, /* R1236 */
2814 0x0000, /* R1237 */
2815 0x0000, /* R1238 */
2816 0x0000, /* R1239 */
2817 0x0000, /* R1240 */
2818 0x0000, /* R1241 */
2819 0x0000, /* R1242 */
2820 0x0000, /* R1243 */
2821 0x0000, /* R1244 */
2822 0x0000, /* R1245 */
2823 0x0000, /* R1246 */
2824 0x0000, /* R1247 */
2825 0x0000, /* R1248 */
2826 0x0000, /* R1249 */
2827 0x0000, /* R1250 */
2828 0x0000, /* R1251 */
2829 0x0000, /* R1252 */
2830 0x0000, /* R1253 */
2831 0x0000, /* R1254 */
2832 0x0000, /* R1255 */
2833 0x0000, /* R1256 */
2834 0x0000, /* R1257 */
2835 0x0000, /* R1258 */
2836 0x0000, /* R1259 */
2837 0x0000, /* R1260 */
2838 0x0000, /* R1261 */
2839 0x0000, /* R1262 */
2840 0x0000, /* R1263 */
2841 0x0000, /* R1264 */
2842 0x0000, /* R1265 */
2843 0x0000, /* R1266 */
2844 0x0000, /* R1267 */
2845 0x0000, /* R1268 */
2846 0x0000, /* R1269 */
2847 0x0000, /* R1270 */
2848 0x0000, /* R1271 */
2849 0x0000, /* R1272 */
2850 0x0000, /* R1273 */
2851 0x0000, /* R1274 */
2852 0x0000, /* R1275 */
2853 0x0000, /* R1276 */
2854 0x0000, /* R1277 */
2855 0x0000, /* R1278 */
2856 0x0000, /* R1279 */
2857 0x00C0, /* R1280 - AIF2 ADC Left Volume */
2858 0x00C0, /* R1281 - AIF2 ADC Right Volume */
2859 0x00C0, /* R1282 - AIF2 DAC Left Volume */
2860 0x00C0, /* R1283 - AIF2 DAC Right Volume */
2861 0x0000, /* R1284 */
2862 0x0000, /* R1285 */
2863 0x0000, /* R1286 */
2864 0x0000, /* R1287 */
2865 0x0000, /* R1288 */
2866 0x0000, /* R1289 */
2867 0x0000, /* R1290 */
2868 0x0000, /* R1291 */
2869 0x0000, /* R1292 */
2870 0x0000, /* R1293 */
2871 0x0000, /* R1294 */
2872 0x0000, /* R1295 */
2873 0x0000, /* R1296 - AIF2 ADC Filters */
2874 0x0000, /* R1297 */
2875 0x0000, /* R1298 */
2876 0x0000, /* R1299 */
2877 0x0000, /* R1300 */
2878 0x0000, /* R1301 */
2879 0x0000, /* R1302 */
2880 0x0000, /* R1303 */
2881 0x0000, /* R1304 */
2882 0x0000, /* R1305 */
2883 0x0000, /* R1306 */
2884 0x0000, /* R1307 */
2885 0x0000, /* R1308 */
2886 0x0000, /* R1309 */
2887 0x0000, /* R1310 */
2888 0x0000, /* R1311 */
2889 0x0200, /* R1312 - AIF2 DAC Filters (1) */
2890 0x0010, /* R1313 - AIF2 DAC Filters (2) */
2891 0x0000, /* R1314 */
2892 0x0000, /* R1315 */
2893 0x0000, /* R1316 */
2894 0x0000, /* R1317 */
2895 0x0000, /* R1318 */
2896 0x0000, /* R1319 */
2897 0x0000, /* R1320 */
2898 0x0000, /* R1321 */
2899 0x0000, /* R1322 */
2900 0x0000, /* R1323 */
2901 0x0000, /* R1324 */
2902 0x0000, /* R1325 */
2903 0x0000, /* R1326 */
2904 0x0000, /* R1327 */
2905 0x0000, /* R1328 */
2906 0x0000, /* R1329 */
2907 0x0000, /* R1330 */
2908 0x0000, /* R1331 */
2909 0x0000, /* R1332 */
2910 0x0000, /* R1333 */
2911 0x0000, /* R1334 */
2912 0x0000, /* R1335 */
2913 0x0000, /* R1336 */
2914 0x0000, /* R1337 */
2915 0x0000, /* R1338 */
2916 0x0000, /* R1339 */
2917 0x0000, /* R1340 */
2918 0x0000, /* R1341 */
2919 0x0000, /* R1342 */
2920 0x0000, /* R1343 */
2921 0x0098, /* R1344 - AIF2 DRC (1) */
2922 0x0845, /* R1345 - AIF2 DRC (2) */
2923 0x0000, /* R1346 - AIF2 DRC (3) */
2924 0x0000, /* R1347 - AIF2 DRC (4) */
2925 0x0000, /* R1348 - AIF2 DRC (5) */
2926 0x0000, /* R1349 */
2927 0x0000, /* R1350 */
2928 0x0000, /* R1351 */
2929 0x0000, /* R1352 */
2930 0x0000, /* R1353 */
2931 0x0000, /* R1354 */
2932 0x0000, /* R1355 */
2933 0x0000, /* R1356 */
2934 0x0000, /* R1357 */
2935 0x0000, /* R1358 */
2936 0x0000, /* R1359 */
2937 0x0000, /* R1360 */
2938 0x0000, /* R1361 */
2939 0x0000, /* R1362 */
2940 0x0000, /* R1363 */
2941 0x0000, /* R1364 */
2942 0x0000, /* R1365 */
2943 0x0000, /* R1366 */
2944 0x0000, /* R1367 */
2945 0x0000, /* R1368 */
2946 0x0000, /* R1369 */
2947 0x0000, /* R1370 */
2948 0x0000, /* R1371 */
2949 0x0000, /* R1372 */
2950 0x0000, /* R1373 */
2951 0x0000, /* R1374 */
2952 0x0000, /* R1375 */
2953 0x0000, /* R1376 */
2954 0x0000, /* R1377 */
2955 0x0000, /* R1378 */
2956 0x0000, /* R1379 */
2957 0x0000, /* R1380 */
2958 0x0000, /* R1381 */
2959 0x0000, /* R1382 */
2960 0x0000, /* R1383 */
2961 0x0000, /* R1384 */
2962 0x0000, /* R1385 */
2963 0x0000, /* R1386 */
2964 0x0000, /* R1387 */
2965 0x0000, /* R1388 */
2966 0x0000, /* R1389 */
2967 0x0000, /* R1390 */
2968 0x0000, /* R1391 */
2969 0x0000, /* R1392 */
2970 0x0000, /* R1393 */
2971 0x0000, /* R1394 */
2972 0x0000, /* R1395 */
2973 0x0000, /* R1396 */
2974 0x0000, /* R1397 */
2975 0x0000, /* R1398 */
2976 0x0000, /* R1399 */
2977 0x0000, /* R1400 */
2978 0x0000, /* R1401 */
2979 0x0000, /* R1402 */
2980 0x0000, /* R1403 */
2981 0x0000, /* R1404 */
2982 0x0000, /* R1405 */
2983 0x0000, /* R1406 */
2984 0x0000, /* R1407 */
2985 0x6318, /* R1408 - AIF2 EQ Gains (1) */
2986 0x6300, /* R1409 - AIF2 EQ Gains (2) */
2987 0x0FCA, /* R1410 - AIF2 EQ Band 1 A */
2988 0x0400, /* R1411 - AIF2 EQ Band 1 B */
2989 0x00D8, /* R1412 - AIF2 EQ Band 1 PG */
2990 0x1EB5, /* R1413 - AIF2 EQ Band 2 A */
2991 0xF145, /* R1414 - AIF2 EQ Band 2 B */
2992 0x0B75, /* R1415 - AIF2 EQ Band 2 C */
2993 0x01C5, /* R1416 - AIF2 EQ Band 2 PG */
2994 0x1C58, /* R1417 - AIF2 EQ Band 3 A */
2995 0xF373, /* R1418 - AIF2 EQ Band 3 B */
2996 0x0A54, /* R1419 - AIF2 EQ Band 3 C */
2997 0x0558, /* R1420 - AIF2 EQ Band 3 PG */
2998 0x168E, /* R1421 - AIF2 EQ Band 4 A */
2999 0xF829, /* R1422 - AIF2 EQ Band 4 B */
3000 0x07AD, /* R1423 - AIF2 EQ Band 4 C */
3001 0x1103, /* R1424 - AIF2 EQ Band 4 PG */
3002 0x0564, /* R1425 - AIF2 EQ Band 5 A */
3003 0x0559, /* R1426 - AIF2 EQ Band 5 B */
3004 0x4000, /* R1427 - AIF2 EQ Band 5 PG */
3005 0x0000, /* R1428 */
3006 0x0000, /* R1429 */
3007 0x0000, /* R1430 */
3008 0x0000, /* R1431 */
3009 0x0000, /* R1432 */
3010 0x0000, /* R1433 */
3011 0x0000, /* R1434 */
3012 0x0000, /* R1435 */
3013 0x0000, /* R1436 */
3014 0x0000, /* R1437 */
3015 0x0000, /* R1438 */
3016 0x0000, /* R1439 */
3017 0x0000, /* R1440 */
3018 0x0000, /* R1441 */
3019 0x0000, /* R1442 */
3020 0x0000, /* R1443 */
3021 0x0000, /* R1444 */
3022 0x0000, /* R1445 */
3023 0x0000, /* R1446 */
3024 0x0000, /* R1447 */
3025 0x0000, /* R1448 */
3026 0x0000, /* R1449 */
3027 0x0000, /* R1450 */
3028 0x0000, /* R1451 */
3029 0x0000, /* R1452 */
3030 0x0000, /* R1453 */
3031 0x0000, /* R1454 */
3032 0x0000, /* R1455 */
3033 0x0000, /* R1456 */
3034 0x0000, /* R1457 */
3035 0x0000, /* R1458 */
3036 0x0000, /* R1459 */
3037 0x0000, /* R1460 */
3038 0x0000, /* R1461 */
3039 0x0000, /* R1462 */
3040 0x0000, /* R1463 */
3041 0x0000, /* R1464 */
3042 0x0000, /* R1465 */
3043 0x0000, /* R1466 */
3044 0x0000, /* R1467 */
3045 0x0000, /* R1468 */
3046 0x0000, /* R1469 */
3047 0x0000, /* R1470 */
3048 0x0000, /* R1471 */
3049 0x0000, /* R1472 */
3050 0x0000, /* R1473 */
3051 0x0000, /* R1474 */
3052 0x0000, /* R1475 */
3053 0x0000, /* R1476 */
3054 0x0000, /* R1477 */
3055 0x0000, /* R1478 */
3056 0x0000, /* R1479 */
3057 0x0000, /* R1480 */
3058 0x0000, /* R1481 */
3059 0x0000, /* R1482 */
3060 0x0000, /* R1483 */
3061 0x0000, /* R1484 */
3062 0x0000, /* R1485 */
3063 0x0000, /* R1486 */
3064 0x0000, /* R1487 */
3065 0x0000, /* R1488 */
3066 0x0000, /* R1489 */
3067 0x0000, /* R1490 */
3068 0x0000, /* R1491 */
3069 0x0000, /* R1492 */
3070 0x0000, /* R1493 */
3071 0x0000, /* R1494 */
3072 0x0000, /* R1495 */
3073 0x0000, /* R1496 */
3074 0x0000, /* R1497 */
3075 0x0000, /* R1498 */
3076 0x0000, /* R1499 */
3077 0x0000, /* R1500 */
3078 0x0000, /* R1501 */
3079 0x0000, /* R1502 */
3080 0x0000, /* R1503 */
3081 0x0000, /* R1504 */
3082 0x0000, /* R1505 */
3083 0x0000, /* R1506 */
3084 0x0000, /* R1507 */
3085 0x0000, /* R1508 */
3086 0x0000, /* R1509 */
3087 0x0000, /* R1510 */
3088 0x0000, /* R1511 */
3089 0x0000, /* R1512 */
3090 0x0000, /* R1513 */
3091 0x0000, /* R1514 */
3092 0x0000, /* R1515 */
3093 0x0000, /* R1516 */
3094 0x0000, /* R1517 */
3095 0x0000, /* R1518 */
3096 0x0000, /* R1519 */
3097 0x0000, /* R1520 */
3098 0x0000, /* R1521 */
3099 0x0000, /* R1522 */
3100 0x0000, /* R1523 */
3101 0x0000, /* R1524 */
3102 0x0000, /* R1525 */
3103 0x0000, /* R1526 */
3104 0x0000, /* R1527 */
3105 0x0000, /* R1528 */
3106 0x0000, /* R1529 */
3107 0x0000, /* R1530 */
3108 0x0000, /* R1531 */
3109 0x0000, /* R1532 */
3110 0x0000, /* R1533 */
3111 0x0000, /* R1534 */
3112 0x0000, /* R1535 */
3113 0x0000, /* R1536 - DAC1 Mixer Volumes */
3114 0x0000, /* R1537 - DAC1 Left Mixer Routing */
3115 0x0000, /* R1538 - DAC1 Right Mixer Routing */
3116 0x0000, /* R1539 - DAC2 Mixer Volumes */
3117 0x0000, /* R1540 - DAC2 Left Mixer Routing */
3118 0x0000, /* R1541 - DAC2 Right Mixer Routing */
3119 0x0000, /* R1542 - AIF1 ADC1 Left Mixer Routing */
3120 0x0000, /* R1543 - AIF1 ADC1 Right Mixer Routing */
3121 0x0000, /* R1544 - AIF1 ADC2 Left Mixer Routing */
3122 0x0000, /* R1545 - AIF1 ADC2 Right mixer Routing */
3123 0x0000, /* R1546 */
3124 0x0000, /* R1547 */
3125 0x0000, /* R1548 */
3126 0x0000, /* R1549 */
3127 0x0000, /* R1550 */
3128 0x0000, /* R1551 */
3129 0x02C0, /* R1552 - DAC1 Left Volume */
3130 0x02C0, /* R1553 - DAC1 Right Volume */
3131 0x02C0, /* R1554 - DAC2 Left Volume */
3132 0x02C0, /* R1555 - DAC2 Right Volume */
3133 0x0000, /* R1556 - DAC Softmute */
3134 0x0000, /* R1557 */
3135 0x0000, /* R1558 */
3136 0x0000, /* R1559 */
3137 0x0000, /* R1560 */
3138 0x0000, /* R1561 */
3139 0x0000, /* R1562 */
3140 0x0000, /* R1563 */
3141 0x0000, /* R1564 */
3142 0x0000, /* R1565 */
3143 0x0000, /* R1566 */
3144 0x0000, /* R1567 */
3145 0x0002, /* R1568 - Oversampling */
3146 0x0000, /* R1569 - Sidetone */
3147};
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index 4d3e6f1ac584..247a6a99feb8 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -18,15 +18,17 @@
18#include <linux/pm.h> 18#include <linux/pm.h>
19#include <linux/i2c.h> 19#include <linux/i2c.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
21#include <linux/regulator/consumer.h> 22#include <linux/regulator/consumer.h>
22#include <linux/slab.h> 23#include <linux/slab.h>
23#include <sound/core.h> 24#include <sound/core.h>
25#include <sound/jack.h>
24#include <sound/pcm.h> 26#include <sound/pcm.h>
25#include <sound/pcm_params.h> 27#include <sound/pcm_params.h>
26#include <sound/soc.h> 28#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h> 29#include <sound/initval.h>
29#include <sound/tlv.h> 30#include <sound/tlv.h>
31#include <trace/events/asoc.h>
30 32
31#include <linux/mfd/wm8994/core.h> 33#include <linux/mfd/wm8994/core.h>
32#include <linux/mfd/wm8994/registers.h> 34#include <linux/mfd/wm8994/registers.h>
@@ -57,8 +59,6 @@ static int wm8994_retune_mobile_base[] = {
57 WM8994_AIF2_EQ_GAINS_1, 59 WM8994_AIF2_EQ_GAINS_1,
58}; 60};
59 61
60#define WM8994_REG_CACHE_SIZE 0x621
61
62struct wm8994_micdet { 62struct wm8994_micdet {
63 struct snd_soc_jack *jack; 63 struct snd_soc_jack *jack;
64 int det; 64 int det;
@@ -71,7 +71,6 @@ struct wm8994_priv {
71 enum snd_soc_control_type control_type; 71 enum snd_soc_control_type control_type;
72 void *control_data; 72 void *control_data;
73 struct snd_soc_codec *codec; 73 struct snd_soc_codec *codec;
74 u16 reg_cache[WM8994_REG_CACHE_SIZE + 1];
75 int sysclk[2]; 74 int sysclk[2];
76 int sysclk_rate[2]; 75 int sysclk_rate[2];
77 int mclk[2]; 76 int mclk[2];
@@ -81,6 +80,8 @@ struct wm8994_priv {
81 int dac_rates[2]; 80 int dac_rates[2];
82 int lrclk_shared[2]; 81 int lrclk_shared[2];
83 82
83 int mbc_ena[3];
84
84 /* Platform dependant DRC configuration */ 85 /* Platform dependant DRC configuration */
85 const char **drc_texts; 86 const char **drc_texts;
86 int drc_cfg[WM8994_NUM_DRC]; 87 int drc_cfg[WM8994_NUM_DRC];
@@ -92,1588 +93,22 @@ struct wm8994_priv {
92 int retune_mobile_cfg[WM8994_NUM_EQ]; 93 int retune_mobile_cfg[WM8994_NUM_EQ];
93 struct soc_enum retune_mobile_enum; 94 struct soc_enum retune_mobile_enum;
94 95
96 /* Platform dependant MBC configuration */
97 int mbc_cfg;
98 const char **mbc_texts;
99 struct soc_enum mbc_enum;
100
95 struct wm8994_micdet micdet[2]; 101 struct wm8994_micdet micdet[2];
96 102
103 wm8958_micdet_cb jack_cb;
104 void *jack_cb_data;
105 bool jack_is_mic;
106 bool jack_is_video;
107
97 int revision; 108 int revision;
98 struct wm8994_pdata *pdata; 109 struct wm8994_pdata *pdata;
99}; 110};
100 111
101static const struct {
102 unsigned short readable; /* Mask of readable bits */
103 unsigned short writable; /* Mask of writable bits */
104} access_masks[] = {
105 { 0xFFFF, 0xFFFF }, /* R0 - Software Reset */
106 { 0x3B37, 0x3B37 }, /* R1 - Power Management (1) */
107 { 0x6BF0, 0x6BF0 }, /* R2 - Power Management (2) */
108 { 0x3FF0, 0x3FF0 }, /* R3 - Power Management (3) */
109 { 0x3F3F, 0x3F3F }, /* R4 - Power Management (4) */
110 { 0x3F0F, 0x3F0F }, /* R5 - Power Management (5) */
111 { 0x003F, 0x003F }, /* R6 - Power Management (6) */
112 { 0x0000, 0x0000 }, /* R7 */
113 { 0x0000, 0x0000 }, /* R8 */
114 { 0x0000, 0x0000 }, /* R9 */
115 { 0x0000, 0x0000 }, /* R10 */
116 { 0x0000, 0x0000 }, /* R11 */
117 { 0x0000, 0x0000 }, /* R12 */
118 { 0x0000, 0x0000 }, /* R13 */
119 { 0x0000, 0x0000 }, /* R14 */
120 { 0x0000, 0x0000 }, /* R15 */
121 { 0x0000, 0x0000 }, /* R16 */
122 { 0x0000, 0x0000 }, /* R17 */
123 { 0x0000, 0x0000 }, /* R18 */
124 { 0x0000, 0x0000 }, /* R19 */
125 { 0x0000, 0x0000 }, /* R20 */
126 { 0x01C0, 0x01C0 }, /* R21 - Input Mixer (1) */
127 { 0x0000, 0x0000 }, /* R22 */
128 { 0x0000, 0x0000 }, /* R23 */
129 { 0x00DF, 0x01DF }, /* R24 - Left Line Input 1&2 Volume */
130 { 0x00DF, 0x01DF }, /* R25 - Left Line Input 3&4 Volume */
131 { 0x00DF, 0x01DF }, /* R26 - Right Line Input 1&2 Volume */
132 { 0x00DF, 0x01DF }, /* R27 - Right Line Input 3&4 Volume */
133 { 0x00FF, 0x01FF }, /* R28 - Left Output Volume */
134 { 0x00FF, 0x01FF }, /* R29 - Right Output Volume */
135 { 0x0077, 0x0077 }, /* R30 - Line Outputs Volume */
136 { 0x0030, 0x0030 }, /* R31 - HPOUT2 Volume */
137 { 0x00FF, 0x01FF }, /* R32 - Left OPGA Volume */
138 { 0x00FF, 0x01FF }, /* R33 - Right OPGA Volume */
139 { 0x007F, 0x007F }, /* R34 - SPKMIXL Attenuation */
140 { 0x017F, 0x017F }, /* R35 - SPKMIXR Attenuation */
141 { 0x003F, 0x003F }, /* R36 - SPKOUT Mixers */
142 { 0x003F, 0x003F }, /* R37 - ClassD */
143 { 0x00FF, 0x01FF }, /* R38 - Speaker Volume Left */
144 { 0x00FF, 0x01FF }, /* R39 - Speaker Volume Right */
145 { 0x00FF, 0x00FF }, /* R40 - Input Mixer (2) */
146 { 0x01B7, 0x01B7 }, /* R41 - Input Mixer (3) */
147 { 0x01B7, 0x01B7 }, /* R42 - Input Mixer (4) */
148 { 0x01C7, 0x01C7 }, /* R43 - Input Mixer (5) */
149 { 0x01C7, 0x01C7 }, /* R44 - Input Mixer (6) */
150 { 0x01FF, 0x01FF }, /* R45 - Output Mixer (1) */
151 { 0x01FF, 0x01FF }, /* R46 - Output Mixer (2) */
152 { 0x0FFF, 0x0FFF }, /* R47 - Output Mixer (3) */
153 { 0x0FFF, 0x0FFF }, /* R48 - Output Mixer (4) */
154 { 0x0FFF, 0x0FFF }, /* R49 - Output Mixer (5) */
155 { 0x0FFF, 0x0FFF }, /* R50 - Output Mixer (6) */
156 { 0x0038, 0x0038 }, /* R51 - HPOUT2 Mixer */
157 { 0x0077, 0x0077 }, /* R52 - Line Mixer (1) */
158 { 0x0077, 0x0077 }, /* R53 - Line Mixer (2) */
159 { 0x03FF, 0x03FF }, /* R54 - Speaker Mixer */
160 { 0x00C1, 0x00C1 }, /* R55 - Additional Control */
161 { 0x00F0, 0x00F0 }, /* R56 - AntiPOP (1) */
162 { 0x01EF, 0x01EF }, /* R57 - AntiPOP (2) */
163 { 0x00FF, 0x00FF }, /* R58 - MICBIAS */
164 { 0x000F, 0x000F }, /* R59 - LDO 1 */
165 { 0x0007, 0x0007 }, /* R60 - LDO 2 */
166 { 0x0000, 0x0000 }, /* R61 */
167 { 0x0000, 0x0000 }, /* R62 */
168 { 0x0000, 0x0000 }, /* R63 */
169 { 0x0000, 0x0000 }, /* R64 */
170 { 0x0000, 0x0000 }, /* R65 */
171 { 0x0000, 0x0000 }, /* R66 */
172 { 0x0000, 0x0000 }, /* R67 */
173 { 0x0000, 0x0000 }, /* R68 */
174 { 0x0000, 0x0000 }, /* R69 */
175 { 0x0000, 0x0000 }, /* R70 */
176 { 0x0000, 0x0000 }, /* R71 */
177 { 0x0000, 0x0000 }, /* R72 */
178 { 0x0000, 0x0000 }, /* R73 */
179 { 0x0000, 0x0000 }, /* R74 */
180 { 0x0000, 0x0000 }, /* R75 */
181 { 0x8000, 0x8000 }, /* R76 - Charge Pump (1) */
182 { 0x0000, 0x0000 }, /* R77 */
183 { 0x0000, 0x0000 }, /* R78 */
184 { 0x0000, 0x0000 }, /* R79 */
185 { 0x0000, 0x0000 }, /* R80 */
186 { 0x0301, 0x0301 }, /* R81 - Class W (1) */
187 { 0x0000, 0x0000 }, /* R82 */
188 { 0x0000, 0x0000 }, /* R83 */
189 { 0x333F, 0x333F }, /* R84 - DC Servo (1) */
190 { 0x0FEF, 0x0FEF }, /* R85 - DC Servo (2) */
191 { 0x0000, 0x0000 }, /* R86 */
192 { 0xFFFF, 0xFFFF }, /* R87 - DC Servo (4) */
193 { 0x0333, 0x0000 }, /* R88 - DC Servo Readback */
194 { 0x0000, 0x0000 }, /* R89 */
195 { 0x0000, 0x0000 }, /* R90 */
196 { 0x0000, 0x0000 }, /* R91 */
197 { 0x0000, 0x0000 }, /* R92 */
198 { 0x0000, 0x0000 }, /* R93 */
199 { 0x0000, 0x0000 }, /* R94 */
200 { 0x0000, 0x0000 }, /* R95 */
201 { 0x00EE, 0x00EE }, /* R96 - Analogue HP (1) */
202 { 0x0000, 0x0000 }, /* R97 */
203 { 0x0000, 0x0000 }, /* R98 */
204 { 0x0000, 0x0000 }, /* R99 */
205 { 0x0000, 0x0000 }, /* R100 */
206 { 0x0000, 0x0000 }, /* R101 */
207 { 0x0000, 0x0000 }, /* R102 */
208 { 0x0000, 0x0000 }, /* R103 */
209 { 0x0000, 0x0000 }, /* R104 */
210 { 0x0000, 0x0000 }, /* R105 */
211 { 0x0000, 0x0000 }, /* R106 */
212 { 0x0000, 0x0000 }, /* R107 */
213 { 0x0000, 0x0000 }, /* R108 */
214 { 0x0000, 0x0000 }, /* R109 */
215 { 0x0000, 0x0000 }, /* R110 */
216 { 0x0000, 0x0000 }, /* R111 */
217 { 0x0000, 0x0000 }, /* R112 */
218 { 0x0000, 0x0000 }, /* R113 */
219 { 0x0000, 0x0000 }, /* R114 */
220 { 0x0000, 0x0000 }, /* R115 */
221 { 0x0000, 0x0000 }, /* R116 */
222 { 0x0000, 0x0000 }, /* R117 */
223 { 0x0000, 0x0000 }, /* R118 */
224 { 0x0000, 0x0000 }, /* R119 */
225 { 0x0000, 0x0000 }, /* R120 */
226 { 0x0000, 0x0000 }, /* R121 */
227 { 0x0000, 0x0000 }, /* R122 */
228 { 0x0000, 0x0000 }, /* R123 */
229 { 0x0000, 0x0000 }, /* R124 */
230 { 0x0000, 0x0000 }, /* R125 */
231 { 0x0000, 0x0000 }, /* R126 */
232 { 0x0000, 0x0000 }, /* R127 */
233 { 0x0000, 0x0000 }, /* R128 */
234 { 0x0000, 0x0000 }, /* R129 */
235 { 0x0000, 0x0000 }, /* R130 */
236 { 0x0000, 0x0000 }, /* R131 */
237 { 0x0000, 0x0000 }, /* R132 */
238 { 0x0000, 0x0000 }, /* R133 */
239 { 0x0000, 0x0000 }, /* R134 */
240 { 0x0000, 0x0000 }, /* R135 */
241 { 0x0000, 0x0000 }, /* R136 */
242 { 0x0000, 0x0000 }, /* R137 */
243 { 0x0000, 0x0000 }, /* R138 */
244 { 0x0000, 0x0000 }, /* R139 */
245 { 0x0000, 0x0000 }, /* R140 */
246 { 0x0000, 0x0000 }, /* R141 */
247 { 0x0000, 0x0000 }, /* R142 */
248 { 0x0000, 0x0000 }, /* R143 */
249 { 0x0000, 0x0000 }, /* R144 */
250 { 0x0000, 0x0000 }, /* R145 */
251 { 0x0000, 0x0000 }, /* R146 */
252 { 0x0000, 0x0000 }, /* R147 */
253 { 0x0000, 0x0000 }, /* R148 */
254 { 0x0000, 0x0000 }, /* R149 */
255 { 0x0000, 0x0000 }, /* R150 */
256 { 0x0000, 0x0000 }, /* R151 */
257 { 0x0000, 0x0000 }, /* R152 */
258 { 0x0000, 0x0000 }, /* R153 */
259 { 0x0000, 0x0000 }, /* R154 */
260 { 0x0000, 0x0000 }, /* R155 */
261 { 0x0000, 0x0000 }, /* R156 */
262 { 0x0000, 0x0000 }, /* R157 */
263 { 0x0000, 0x0000 }, /* R158 */
264 { 0x0000, 0x0000 }, /* R159 */
265 { 0x0000, 0x0000 }, /* R160 */
266 { 0x0000, 0x0000 }, /* R161 */
267 { 0x0000, 0x0000 }, /* R162 */
268 { 0x0000, 0x0000 }, /* R163 */
269 { 0x0000, 0x0000 }, /* R164 */
270 { 0x0000, 0x0000 }, /* R165 */
271 { 0x0000, 0x0000 }, /* R166 */
272 { 0x0000, 0x0000 }, /* R167 */
273 { 0x0000, 0x0000 }, /* R168 */
274 { 0x0000, 0x0000 }, /* R169 */
275 { 0x0000, 0x0000 }, /* R170 */
276 { 0x0000, 0x0000 }, /* R171 */
277 { 0x0000, 0x0000 }, /* R172 */
278 { 0x0000, 0x0000 }, /* R173 */
279 { 0x0000, 0x0000 }, /* R174 */
280 { 0x0000, 0x0000 }, /* R175 */
281 { 0x0000, 0x0000 }, /* R176 */
282 { 0x0000, 0x0000 }, /* R177 */
283 { 0x0000, 0x0000 }, /* R178 */
284 { 0x0000, 0x0000 }, /* R179 */
285 { 0x0000, 0x0000 }, /* R180 */
286 { 0x0000, 0x0000 }, /* R181 */
287 { 0x0000, 0x0000 }, /* R182 */
288 { 0x0000, 0x0000 }, /* R183 */
289 { 0x0000, 0x0000 }, /* R184 */
290 { 0x0000, 0x0000 }, /* R185 */
291 { 0x0000, 0x0000 }, /* R186 */
292 { 0x0000, 0x0000 }, /* R187 */
293 { 0x0000, 0x0000 }, /* R188 */
294 { 0x0000, 0x0000 }, /* R189 */
295 { 0x0000, 0x0000 }, /* R190 */
296 { 0x0000, 0x0000 }, /* R191 */
297 { 0x0000, 0x0000 }, /* R192 */
298 { 0x0000, 0x0000 }, /* R193 */
299 { 0x0000, 0x0000 }, /* R194 */
300 { 0x0000, 0x0000 }, /* R195 */
301 { 0x0000, 0x0000 }, /* R196 */
302 { 0x0000, 0x0000 }, /* R197 */
303 { 0x0000, 0x0000 }, /* R198 */
304 { 0x0000, 0x0000 }, /* R199 */
305 { 0x0000, 0x0000 }, /* R200 */
306 { 0x0000, 0x0000 }, /* R201 */
307 { 0x0000, 0x0000 }, /* R202 */
308 { 0x0000, 0x0000 }, /* R203 */
309 { 0x0000, 0x0000 }, /* R204 */
310 { 0x0000, 0x0000 }, /* R205 */
311 { 0x0000, 0x0000 }, /* R206 */
312 { 0x0000, 0x0000 }, /* R207 */
313 { 0x0000, 0x0000 }, /* R208 */
314 { 0x0000, 0x0000 }, /* R209 */
315 { 0x0000, 0x0000 }, /* R210 */
316 { 0x0000, 0x0000 }, /* R211 */
317 { 0x0000, 0x0000 }, /* R212 */
318 { 0x0000, 0x0000 }, /* R213 */
319 { 0x0000, 0x0000 }, /* R214 */
320 { 0x0000, 0x0000 }, /* R215 */
321 { 0x0000, 0x0000 }, /* R216 */
322 { 0x0000, 0x0000 }, /* R217 */
323 { 0x0000, 0x0000 }, /* R218 */
324 { 0x0000, 0x0000 }, /* R219 */
325 { 0x0000, 0x0000 }, /* R220 */
326 { 0x0000, 0x0000 }, /* R221 */
327 { 0x0000, 0x0000 }, /* R222 */
328 { 0x0000, 0x0000 }, /* R223 */
329 { 0x0000, 0x0000 }, /* R224 */
330 { 0x0000, 0x0000 }, /* R225 */
331 { 0x0000, 0x0000 }, /* R226 */
332 { 0x0000, 0x0000 }, /* R227 */
333 { 0x0000, 0x0000 }, /* R228 */
334 { 0x0000, 0x0000 }, /* R229 */
335 { 0x0000, 0x0000 }, /* R230 */
336 { 0x0000, 0x0000 }, /* R231 */
337 { 0x0000, 0x0000 }, /* R232 */
338 { 0x0000, 0x0000 }, /* R233 */
339 { 0x0000, 0x0000 }, /* R234 */
340 { 0x0000, 0x0000 }, /* R235 */
341 { 0x0000, 0x0000 }, /* R236 */
342 { 0x0000, 0x0000 }, /* R237 */
343 { 0x0000, 0x0000 }, /* R238 */
344 { 0x0000, 0x0000 }, /* R239 */
345 { 0x0000, 0x0000 }, /* R240 */
346 { 0x0000, 0x0000 }, /* R241 */
347 { 0x0000, 0x0000 }, /* R242 */
348 { 0x0000, 0x0000 }, /* R243 */
349 { 0x0000, 0x0000 }, /* R244 */
350 { 0x0000, 0x0000 }, /* R245 */
351 { 0x0000, 0x0000 }, /* R246 */
352 { 0x0000, 0x0000 }, /* R247 */
353 { 0x0000, 0x0000 }, /* R248 */
354 { 0x0000, 0x0000 }, /* R249 */
355 { 0x0000, 0x0000 }, /* R250 */
356 { 0x0000, 0x0000 }, /* R251 */
357 { 0x0000, 0x0000 }, /* R252 */
358 { 0x0000, 0x0000 }, /* R253 */
359 { 0x0000, 0x0000 }, /* R254 */
360 { 0x0000, 0x0000 }, /* R255 */
361 { 0x000F, 0x0000 }, /* R256 - Chip Revision */
362 { 0x0074, 0x0074 }, /* R257 - Control Interface */
363 { 0x0000, 0x0000 }, /* R258 */
364 { 0x0000, 0x0000 }, /* R259 */
365 { 0x0000, 0x0000 }, /* R260 */
366 { 0x0000, 0x0000 }, /* R261 */
367 { 0x0000, 0x0000 }, /* R262 */
368 { 0x0000, 0x0000 }, /* R263 */
369 { 0x0000, 0x0000 }, /* R264 */
370 { 0x0000, 0x0000 }, /* R265 */
371 { 0x0000, 0x0000 }, /* R266 */
372 { 0x0000, 0x0000 }, /* R267 */
373 { 0x0000, 0x0000 }, /* R268 */
374 { 0x0000, 0x0000 }, /* R269 */
375 { 0x0000, 0x0000 }, /* R270 */
376 { 0x0000, 0x0000 }, /* R271 */
377 { 0x807F, 0x837F }, /* R272 - Write Sequencer Ctrl (1) */
378 { 0x017F, 0x0000 }, /* R273 - Write Sequencer Ctrl (2) */
379 { 0x0000, 0x0000 }, /* R274 */
380 { 0x0000, 0x0000 }, /* R275 */
381 { 0x0000, 0x0000 }, /* R276 */
382 { 0x0000, 0x0000 }, /* R277 */
383 { 0x0000, 0x0000 }, /* R278 */
384 { 0x0000, 0x0000 }, /* R279 */
385 { 0x0000, 0x0000 }, /* R280 */
386 { 0x0000, 0x0000 }, /* R281 */
387 { 0x0000, 0x0000 }, /* R282 */
388 { 0x0000, 0x0000 }, /* R283 */
389 { 0x0000, 0x0000 }, /* R284 */
390 { 0x0000, 0x0000 }, /* R285 */
391 { 0x0000, 0x0000 }, /* R286 */
392 { 0x0000, 0x0000 }, /* R287 */
393 { 0x0000, 0x0000 }, /* R288 */
394 { 0x0000, 0x0000 }, /* R289 */
395 { 0x0000, 0x0000 }, /* R290 */
396 { 0x0000, 0x0000 }, /* R291 */
397 { 0x0000, 0x0000 }, /* R292 */
398 { 0x0000, 0x0000 }, /* R293 */
399 { 0x0000, 0x0000 }, /* R294 */
400 { 0x0000, 0x0000 }, /* R295 */
401 { 0x0000, 0x0000 }, /* R296 */
402 { 0x0000, 0x0000 }, /* R297 */
403 { 0x0000, 0x0000 }, /* R298 */
404 { 0x0000, 0x0000 }, /* R299 */
405 { 0x0000, 0x0000 }, /* R300 */
406 { 0x0000, 0x0000 }, /* R301 */
407 { 0x0000, 0x0000 }, /* R302 */
408 { 0x0000, 0x0000 }, /* R303 */
409 { 0x0000, 0x0000 }, /* R304 */
410 { 0x0000, 0x0000 }, /* R305 */
411 { 0x0000, 0x0000 }, /* R306 */
412 { 0x0000, 0x0000 }, /* R307 */
413 { 0x0000, 0x0000 }, /* R308 */
414 { 0x0000, 0x0000 }, /* R309 */
415 { 0x0000, 0x0000 }, /* R310 */
416 { 0x0000, 0x0000 }, /* R311 */
417 { 0x0000, 0x0000 }, /* R312 */
418 { 0x0000, 0x0000 }, /* R313 */
419 { 0x0000, 0x0000 }, /* R314 */
420 { 0x0000, 0x0000 }, /* R315 */
421 { 0x0000, 0x0000 }, /* R316 */
422 { 0x0000, 0x0000 }, /* R317 */
423 { 0x0000, 0x0000 }, /* R318 */
424 { 0x0000, 0x0000 }, /* R319 */
425 { 0x0000, 0x0000 }, /* R320 */
426 { 0x0000, 0x0000 }, /* R321 */
427 { 0x0000, 0x0000 }, /* R322 */
428 { 0x0000, 0x0000 }, /* R323 */
429 { 0x0000, 0x0000 }, /* R324 */
430 { 0x0000, 0x0000 }, /* R325 */
431 { 0x0000, 0x0000 }, /* R326 */
432 { 0x0000, 0x0000 }, /* R327 */
433 { 0x0000, 0x0000 }, /* R328 */
434 { 0x0000, 0x0000 }, /* R329 */
435 { 0x0000, 0x0000 }, /* R330 */
436 { 0x0000, 0x0000 }, /* R331 */
437 { 0x0000, 0x0000 }, /* R332 */
438 { 0x0000, 0x0000 }, /* R333 */
439 { 0x0000, 0x0000 }, /* R334 */
440 { 0x0000, 0x0000 }, /* R335 */
441 { 0x0000, 0x0000 }, /* R336 */
442 { 0x0000, 0x0000 }, /* R337 */
443 { 0x0000, 0x0000 }, /* R338 */
444 { 0x0000, 0x0000 }, /* R339 */
445 { 0x0000, 0x0000 }, /* R340 */
446 { 0x0000, 0x0000 }, /* R341 */
447 { 0x0000, 0x0000 }, /* R342 */
448 { 0x0000, 0x0000 }, /* R343 */
449 { 0x0000, 0x0000 }, /* R344 */
450 { 0x0000, 0x0000 }, /* R345 */
451 { 0x0000, 0x0000 }, /* R346 */
452 { 0x0000, 0x0000 }, /* R347 */
453 { 0x0000, 0x0000 }, /* R348 */
454 { 0x0000, 0x0000 }, /* R349 */
455 { 0x0000, 0x0000 }, /* R350 */
456 { 0x0000, 0x0000 }, /* R351 */
457 { 0x0000, 0x0000 }, /* R352 */
458 { 0x0000, 0x0000 }, /* R353 */
459 { 0x0000, 0x0000 }, /* R354 */
460 { 0x0000, 0x0000 }, /* R355 */
461 { 0x0000, 0x0000 }, /* R356 */
462 { 0x0000, 0x0000 }, /* R357 */
463 { 0x0000, 0x0000 }, /* R358 */
464 { 0x0000, 0x0000 }, /* R359 */
465 { 0x0000, 0x0000 }, /* R360 */
466 { 0x0000, 0x0000 }, /* R361 */
467 { 0x0000, 0x0000 }, /* R362 */
468 { 0x0000, 0x0000 }, /* R363 */
469 { 0x0000, 0x0000 }, /* R364 */
470 { 0x0000, 0x0000 }, /* R365 */
471 { 0x0000, 0x0000 }, /* R366 */
472 { 0x0000, 0x0000 }, /* R367 */
473 { 0x0000, 0x0000 }, /* R368 */
474 { 0x0000, 0x0000 }, /* R369 */
475 { 0x0000, 0x0000 }, /* R370 */
476 { 0x0000, 0x0000 }, /* R371 */
477 { 0x0000, 0x0000 }, /* R372 */
478 { 0x0000, 0x0000 }, /* R373 */
479 { 0x0000, 0x0000 }, /* R374 */
480 { 0x0000, 0x0000 }, /* R375 */
481 { 0x0000, 0x0000 }, /* R376 */
482 { 0x0000, 0x0000 }, /* R377 */
483 { 0x0000, 0x0000 }, /* R378 */
484 { 0x0000, 0x0000 }, /* R379 */
485 { 0x0000, 0x0000 }, /* R380 */
486 { 0x0000, 0x0000 }, /* R381 */
487 { 0x0000, 0x0000 }, /* R382 */
488 { 0x0000, 0x0000 }, /* R383 */
489 { 0x0000, 0x0000 }, /* R384 */
490 { 0x0000, 0x0000 }, /* R385 */
491 { 0x0000, 0x0000 }, /* R386 */
492 { 0x0000, 0x0000 }, /* R387 */
493 { 0x0000, 0x0000 }, /* R388 */
494 { 0x0000, 0x0000 }, /* R389 */
495 { 0x0000, 0x0000 }, /* R390 */
496 { 0x0000, 0x0000 }, /* R391 */
497 { 0x0000, 0x0000 }, /* R392 */
498 { 0x0000, 0x0000 }, /* R393 */
499 { 0x0000, 0x0000 }, /* R394 */
500 { 0x0000, 0x0000 }, /* R395 */
501 { 0x0000, 0x0000 }, /* R396 */
502 { 0x0000, 0x0000 }, /* R397 */
503 { 0x0000, 0x0000 }, /* R398 */
504 { 0x0000, 0x0000 }, /* R399 */
505 { 0x0000, 0x0000 }, /* R400 */
506 { 0x0000, 0x0000 }, /* R401 */
507 { 0x0000, 0x0000 }, /* R402 */
508 { 0x0000, 0x0000 }, /* R403 */
509 { 0x0000, 0x0000 }, /* R404 */
510 { 0x0000, 0x0000 }, /* R405 */
511 { 0x0000, 0x0000 }, /* R406 */
512 { 0x0000, 0x0000 }, /* R407 */
513 { 0x0000, 0x0000 }, /* R408 */
514 { 0x0000, 0x0000 }, /* R409 */
515 { 0x0000, 0x0000 }, /* R410 */
516 { 0x0000, 0x0000 }, /* R411 */
517 { 0x0000, 0x0000 }, /* R412 */
518 { 0x0000, 0x0000 }, /* R413 */
519 { 0x0000, 0x0000 }, /* R414 */
520 { 0x0000, 0x0000 }, /* R415 */
521 { 0x0000, 0x0000 }, /* R416 */
522 { 0x0000, 0x0000 }, /* R417 */
523 { 0x0000, 0x0000 }, /* R418 */
524 { 0x0000, 0x0000 }, /* R419 */
525 { 0x0000, 0x0000 }, /* R420 */
526 { 0x0000, 0x0000 }, /* R421 */
527 { 0x0000, 0x0000 }, /* R422 */
528 { 0x0000, 0x0000 }, /* R423 */
529 { 0x0000, 0x0000 }, /* R424 */
530 { 0x0000, 0x0000 }, /* R425 */
531 { 0x0000, 0x0000 }, /* R426 */
532 { 0x0000, 0x0000 }, /* R427 */
533 { 0x0000, 0x0000 }, /* R428 */
534 { 0x0000, 0x0000 }, /* R429 */
535 { 0x0000, 0x0000 }, /* R430 */
536 { 0x0000, 0x0000 }, /* R431 */
537 { 0x0000, 0x0000 }, /* R432 */
538 { 0x0000, 0x0000 }, /* R433 */
539 { 0x0000, 0x0000 }, /* R434 */
540 { 0x0000, 0x0000 }, /* R435 */
541 { 0x0000, 0x0000 }, /* R436 */
542 { 0x0000, 0x0000 }, /* R437 */
543 { 0x0000, 0x0000 }, /* R438 */
544 { 0x0000, 0x0000 }, /* R439 */
545 { 0x0000, 0x0000 }, /* R440 */
546 { 0x0000, 0x0000 }, /* R441 */
547 { 0x0000, 0x0000 }, /* R442 */
548 { 0x0000, 0x0000 }, /* R443 */
549 { 0x0000, 0x0000 }, /* R444 */
550 { 0x0000, 0x0000 }, /* R445 */
551 { 0x0000, 0x0000 }, /* R446 */
552 { 0x0000, 0x0000 }, /* R447 */
553 { 0x0000, 0x0000 }, /* R448 */
554 { 0x0000, 0x0000 }, /* R449 */
555 { 0x0000, 0x0000 }, /* R450 */
556 { 0x0000, 0x0000 }, /* R451 */
557 { 0x0000, 0x0000 }, /* R452 */
558 { 0x0000, 0x0000 }, /* R453 */
559 { 0x0000, 0x0000 }, /* R454 */
560 { 0x0000, 0x0000 }, /* R455 */
561 { 0x0000, 0x0000 }, /* R456 */
562 { 0x0000, 0x0000 }, /* R457 */
563 { 0x0000, 0x0000 }, /* R458 */
564 { 0x0000, 0x0000 }, /* R459 */
565 { 0x0000, 0x0000 }, /* R460 */
566 { 0x0000, 0x0000 }, /* R461 */
567 { 0x0000, 0x0000 }, /* R462 */
568 { 0x0000, 0x0000 }, /* R463 */
569 { 0x0000, 0x0000 }, /* R464 */
570 { 0x0000, 0x0000 }, /* R465 */
571 { 0x0000, 0x0000 }, /* R466 */
572 { 0x0000, 0x0000 }, /* R467 */
573 { 0x0000, 0x0000 }, /* R468 */
574 { 0x0000, 0x0000 }, /* R469 */
575 { 0x0000, 0x0000 }, /* R470 */
576 { 0x0000, 0x0000 }, /* R471 */
577 { 0x0000, 0x0000 }, /* R472 */
578 { 0x0000, 0x0000 }, /* R473 */
579 { 0x0000, 0x0000 }, /* R474 */
580 { 0x0000, 0x0000 }, /* R475 */
581 { 0x0000, 0x0000 }, /* R476 */
582 { 0x0000, 0x0000 }, /* R477 */
583 { 0x0000, 0x0000 }, /* R478 */
584 { 0x0000, 0x0000 }, /* R479 */
585 { 0x0000, 0x0000 }, /* R480 */
586 { 0x0000, 0x0000 }, /* R481 */
587 { 0x0000, 0x0000 }, /* R482 */
588 { 0x0000, 0x0000 }, /* R483 */
589 { 0x0000, 0x0000 }, /* R484 */
590 { 0x0000, 0x0000 }, /* R485 */
591 { 0x0000, 0x0000 }, /* R486 */
592 { 0x0000, 0x0000 }, /* R487 */
593 { 0x0000, 0x0000 }, /* R488 */
594 { 0x0000, 0x0000 }, /* R489 */
595 { 0x0000, 0x0000 }, /* R490 */
596 { 0x0000, 0x0000 }, /* R491 */
597 { 0x0000, 0x0000 }, /* R492 */
598 { 0x0000, 0x0000 }, /* R493 */
599 { 0x0000, 0x0000 }, /* R494 */
600 { 0x0000, 0x0000 }, /* R495 */
601 { 0x0000, 0x0000 }, /* R496 */
602 { 0x0000, 0x0000 }, /* R497 */
603 { 0x0000, 0x0000 }, /* R498 */
604 { 0x0000, 0x0000 }, /* R499 */
605 { 0x0000, 0x0000 }, /* R500 */
606 { 0x0000, 0x0000 }, /* R501 */
607 { 0x0000, 0x0000 }, /* R502 */
608 { 0x0000, 0x0000 }, /* R503 */
609 { 0x0000, 0x0000 }, /* R504 */
610 { 0x0000, 0x0000 }, /* R505 */
611 { 0x0000, 0x0000 }, /* R506 */
612 { 0x0000, 0x0000 }, /* R507 */
613 { 0x0000, 0x0000 }, /* R508 */
614 { 0x0000, 0x0000 }, /* R509 */
615 { 0x0000, 0x0000 }, /* R510 */
616 { 0x0000, 0x0000 }, /* R511 */
617 { 0x001F, 0x001F }, /* R512 - AIF1 Clocking (1) */
618 { 0x003F, 0x003F }, /* R513 - AIF1 Clocking (2) */
619 { 0x0000, 0x0000 }, /* R514 */
620 { 0x0000, 0x0000 }, /* R515 */
621 { 0x001F, 0x001F }, /* R516 - AIF2 Clocking (1) */
622 { 0x003F, 0x003F }, /* R517 - AIF2 Clocking (2) */
623 { 0x0000, 0x0000 }, /* R518 */
624 { 0x0000, 0x0000 }, /* R519 */
625 { 0x001F, 0x001F }, /* R520 - Clocking (1) */
626 { 0x0777, 0x0777 }, /* R521 - Clocking (2) */
627 { 0x0000, 0x0000 }, /* R522 */
628 { 0x0000, 0x0000 }, /* R523 */
629 { 0x0000, 0x0000 }, /* R524 */
630 { 0x0000, 0x0000 }, /* R525 */
631 { 0x0000, 0x0000 }, /* R526 */
632 { 0x0000, 0x0000 }, /* R527 */
633 { 0x00FF, 0x00FF }, /* R528 - AIF1 Rate */
634 { 0x00FF, 0x00FF }, /* R529 - AIF2 Rate */
635 { 0x000F, 0x0000 }, /* R530 - Rate Status */
636 { 0x0000, 0x0000 }, /* R531 */
637 { 0x0000, 0x0000 }, /* R532 */
638 { 0x0000, 0x0000 }, /* R533 */
639 { 0x0000, 0x0000 }, /* R534 */
640 { 0x0000, 0x0000 }, /* R535 */
641 { 0x0000, 0x0000 }, /* R536 */
642 { 0x0000, 0x0000 }, /* R537 */
643 { 0x0000, 0x0000 }, /* R538 */
644 { 0x0000, 0x0000 }, /* R539 */
645 { 0x0000, 0x0000 }, /* R540 */
646 { 0x0000, 0x0000 }, /* R541 */
647 { 0x0000, 0x0000 }, /* R542 */
648 { 0x0000, 0x0000 }, /* R543 */
649 { 0x0007, 0x0007 }, /* R544 - FLL1 Control (1) */
650 { 0x3F77, 0x3F77 }, /* R545 - FLL1 Control (2) */
651 { 0xFFFF, 0xFFFF }, /* R546 - FLL1 Control (3) */
652 { 0x7FEF, 0x7FEF }, /* R547 - FLL1 Control (4) */
653 { 0x1FDB, 0x1FDB }, /* R548 - FLL1 Control (5) */
654 { 0x0000, 0x0000 }, /* R549 */
655 { 0x0000, 0x0000 }, /* R550 */
656 { 0x0000, 0x0000 }, /* R551 */
657 { 0x0000, 0x0000 }, /* R552 */
658 { 0x0000, 0x0000 }, /* R553 */
659 { 0x0000, 0x0000 }, /* R554 */
660 { 0x0000, 0x0000 }, /* R555 */
661 { 0x0000, 0x0000 }, /* R556 */
662 { 0x0000, 0x0000 }, /* R557 */
663 { 0x0000, 0x0000 }, /* R558 */
664 { 0x0000, 0x0000 }, /* R559 */
665 { 0x0000, 0x0000 }, /* R560 */
666 { 0x0000, 0x0000 }, /* R561 */
667 { 0x0000, 0x0000 }, /* R562 */
668 { 0x0000, 0x0000 }, /* R563 */
669 { 0x0000, 0x0000 }, /* R564 */
670 { 0x0000, 0x0000 }, /* R565 */
671 { 0x0000, 0x0000 }, /* R566 */
672 { 0x0000, 0x0000 }, /* R567 */
673 { 0x0000, 0x0000 }, /* R568 */
674 { 0x0000, 0x0000 }, /* R569 */
675 { 0x0000, 0x0000 }, /* R570 */
676 { 0x0000, 0x0000 }, /* R571 */
677 { 0x0000, 0x0000 }, /* R572 */
678 { 0x0000, 0x0000 }, /* R573 */
679 { 0x0000, 0x0000 }, /* R574 */
680 { 0x0000, 0x0000 }, /* R575 */
681 { 0x0007, 0x0007 }, /* R576 - FLL2 Control (1) */
682 { 0x3F77, 0x3F77 }, /* R577 - FLL2 Control (2) */
683 { 0xFFFF, 0xFFFF }, /* R578 - FLL2 Control (3) */
684 { 0x7FEF, 0x7FEF }, /* R579 - FLL2 Control (4) */
685 { 0x1FDB, 0x1FDB }, /* R580 - FLL2 Control (5) */
686 { 0x0000, 0x0000 }, /* R581 */
687 { 0x0000, 0x0000 }, /* R582 */
688 { 0x0000, 0x0000 }, /* R583 */
689 { 0x0000, 0x0000 }, /* R584 */
690 { 0x0000, 0x0000 }, /* R585 */
691 { 0x0000, 0x0000 }, /* R586 */
692 { 0x0000, 0x0000 }, /* R587 */
693 { 0x0000, 0x0000 }, /* R588 */
694 { 0x0000, 0x0000 }, /* R589 */
695 { 0x0000, 0x0000 }, /* R590 */
696 { 0x0000, 0x0000 }, /* R591 */
697 { 0x0000, 0x0000 }, /* R592 */
698 { 0x0000, 0x0000 }, /* R593 */
699 { 0x0000, 0x0000 }, /* R594 */
700 { 0x0000, 0x0000 }, /* R595 */
701 { 0x0000, 0x0000 }, /* R596 */
702 { 0x0000, 0x0000 }, /* R597 */
703 { 0x0000, 0x0000 }, /* R598 */
704 { 0x0000, 0x0000 }, /* R599 */
705 { 0x0000, 0x0000 }, /* R600 */
706 { 0x0000, 0x0000 }, /* R601 */
707 { 0x0000, 0x0000 }, /* R602 */
708 { 0x0000, 0x0000 }, /* R603 */
709 { 0x0000, 0x0000 }, /* R604 */
710 { 0x0000, 0x0000 }, /* R605 */
711 { 0x0000, 0x0000 }, /* R606 */
712 { 0x0000, 0x0000 }, /* R607 */
713 { 0x0000, 0x0000 }, /* R608 */
714 { 0x0000, 0x0000 }, /* R609 */
715 { 0x0000, 0x0000 }, /* R610 */
716 { 0x0000, 0x0000 }, /* R611 */
717 { 0x0000, 0x0000 }, /* R612 */
718 { 0x0000, 0x0000 }, /* R613 */
719 { 0x0000, 0x0000 }, /* R614 */
720 { 0x0000, 0x0000 }, /* R615 */
721 { 0x0000, 0x0000 }, /* R616 */
722 { 0x0000, 0x0000 }, /* R617 */
723 { 0x0000, 0x0000 }, /* R618 */
724 { 0x0000, 0x0000 }, /* R619 */
725 { 0x0000, 0x0000 }, /* R620 */
726 { 0x0000, 0x0000 }, /* R621 */
727 { 0x0000, 0x0000 }, /* R622 */
728 { 0x0000, 0x0000 }, /* R623 */
729 { 0x0000, 0x0000 }, /* R624 */
730 { 0x0000, 0x0000 }, /* R625 */
731 { 0x0000, 0x0000 }, /* R626 */
732 { 0x0000, 0x0000 }, /* R627 */
733 { 0x0000, 0x0000 }, /* R628 */
734 { 0x0000, 0x0000 }, /* R629 */
735 { 0x0000, 0x0000 }, /* R630 */
736 { 0x0000, 0x0000 }, /* R631 */
737 { 0x0000, 0x0000 }, /* R632 */
738 { 0x0000, 0x0000 }, /* R633 */
739 { 0x0000, 0x0000 }, /* R634 */
740 { 0x0000, 0x0000 }, /* R635 */
741 { 0x0000, 0x0000 }, /* R636 */
742 { 0x0000, 0x0000 }, /* R637 */
743 { 0x0000, 0x0000 }, /* R638 */
744 { 0x0000, 0x0000 }, /* R639 */
745 { 0x0000, 0x0000 }, /* R640 */
746 { 0x0000, 0x0000 }, /* R641 */
747 { 0x0000, 0x0000 }, /* R642 */
748 { 0x0000, 0x0000 }, /* R643 */
749 { 0x0000, 0x0000 }, /* R644 */
750 { 0x0000, 0x0000 }, /* R645 */
751 { 0x0000, 0x0000 }, /* R646 */
752 { 0x0000, 0x0000 }, /* R647 */
753 { 0x0000, 0x0000 }, /* R648 */
754 { 0x0000, 0x0000 }, /* R649 */
755 { 0x0000, 0x0000 }, /* R650 */
756 { 0x0000, 0x0000 }, /* R651 */
757 { 0x0000, 0x0000 }, /* R652 */
758 { 0x0000, 0x0000 }, /* R653 */
759 { 0x0000, 0x0000 }, /* R654 */
760 { 0x0000, 0x0000 }, /* R655 */
761 { 0x0000, 0x0000 }, /* R656 */
762 { 0x0000, 0x0000 }, /* R657 */
763 { 0x0000, 0x0000 }, /* R658 */
764 { 0x0000, 0x0000 }, /* R659 */
765 { 0x0000, 0x0000 }, /* R660 */
766 { 0x0000, 0x0000 }, /* R661 */
767 { 0x0000, 0x0000 }, /* R662 */
768 { 0x0000, 0x0000 }, /* R663 */
769 { 0x0000, 0x0000 }, /* R664 */
770 { 0x0000, 0x0000 }, /* R665 */
771 { 0x0000, 0x0000 }, /* R666 */
772 { 0x0000, 0x0000 }, /* R667 */
773 { 0x0000, 0x0000 }, /* R668 */
774 { 0x0000, 0x0000 }, /* R669 */
775 { 0x0000, 0x0000 }, /* R670 */
776 { 0x0000, 0x0000 }, /* R671 */
777 { 0x0000, 0x0000 }, /* R672 */
778 { 0x0000, 0x0000 }, /* R673 */
779 { 0x0000, 0x0000 }, /* R674 */
780 { 0x0000, 0x0000 }, /* R675 */
781 { 0x0000, 0x0000 }, /* R676 */
782 { 0x0000, 0x0000 }, /* R677 */
783 { 0x0000, 0x0000 }, /* R678 */
784 { 0x0000, 0x0000 }, /* R679 */
785 { 0x0000, 0x0000 }, /* R680 */
786 { 0x0000, 0x0000 }, /* R681 */
787 { 0x0000, 0x0000 }, /* R682 */
788 { 0x0000, 0x0000 }, /* R683 */
789 { 0x0000, 0x0000 }, /* R684 */
790 { 0x0000, 0x0000 }, /* R685 */
791 { 0x0000, 0x0000 }, /* R686 */
792 { 0x0000, 0x0000 }, /* R687 */
793 { 0x0000, 0x0000 }, /* R688 */
794 { 0x0000, 0x0000 }, /* R689 */
795 { 0x0000, 0x0000 }, /* R690 */
796 { 0x0000, 0x0000 }, /* R691 */
797 { 0x0000, 0x0000 }, /* R692 */
798 { 0x0000, 0x0000 }, /* R693 */
799 { 0x0000, 0x0000 }, /* R694 */
800 { 0x0000, 0x0000 }, /* R695 */
801 { 0x0000, 0x0000 }, /* R696 */
802 { 0x0000, 0x0000 }, /* R697 */
803 { 0x0000, 0x0000 }, /* R698 */
804 { 0x0000, 0x0000 }, /* R699 */
805 { 0x0000, 0x0000 }, /* R700 */
806 { 0x0000, 0x0000 }, /* R701 */
807 { 0x0000, 0x0000 }, /* R702 */
808 { 0x0000, 0x0000 }, /* R703 */
809 { 0x0000, 0x0000 }, /* R704 */
810 { 0x0000, 0x0000 }, /* R705 */
811 { 0x0000, 0x0000 }, /* R706 */
812 { 0x0000, 0x0000 }, /* R707 */
813 { 0x0000, 0x0000 }, /* R708 */
814 { 0x0000, 0x0000 }, /* R709 */
815 { 0x0000, 0x0000 }, /* R710 */
816 { 0x0000, 0x0000 }, /* R711 */
817 { 0x0000, 0x0000 }, /* R712 */
818 { 0x0000, 0x0000 }, /* R713 */
819 { 0x0000, 0x0000 }, /* R714 */
820 { 0x0000, 0x0000 }, /* R715 */
821 { 0x0000, 0x0000 }, /* R716 */
822 { 0x0000, 0x0000 }, /* R717 */
823 { 0x0000, 0x0000 }, /* R718 */
824 { 0x0000, 0x0000 }, /* R719 */
825 { 0x0000, 0x0000 }, /* R720 */
826 { 0x0000, 0x0000 }, /* R721 */
827 { 0x0000, 0x0000 }, /* R722 */
828 { 0x0000, 0x0000 }, /* R723 */
829 { 0x0000, 0x0000 }, /* R724 */
830 { 0x0000, 0x0000 }, /* R725 */
831 { 0x0000, 0x0000 }, /* R726 */
832 { 0x0000, 0x0000 }, /* R727 */
833 { 0x0000, 0x0000 }, /* R728 */
834 { 0x0000, 0x0000 }, /* R729 */
835 { 0x0000, 0x0000 }, /* R730 */
836 { 0x0000, 0x0000 }, /* R731 */
837 { 0x0000, 0x0000 }, /* R732 */
838 { 0x0000, 0x0000 }, /* R733 */
839 { 0x0000, 0x0000 }, /* R734 */
840 { 0x0000, 0x0000 }, /* R735 */
841 { 0x0000, 0x0000 }, /* R736 */
842 { 0x0000, 0x0000 }, /* R737 */
843 { 0x0000, 0x0000 }, /* R738 */
844 { 0x0000, 0x0000 }, /* R739 */
845 { 0x0000, 0x0000 }, /* R740 */
846 { 0x0000, 0x0000 }, /* R741 */
847 { 0x0000, 0x0000 }, /* R742 */
848 { 0x0000, 0x0000 }, /* R743 */
849 { 0x0000, 0x0000 }, /* R744 */
850 { 0x0000, 0x0000 }, /* R745 */
851 { 0x0000, 0x0000 }, /* R746 */
852 { 0x0000, 0x0000 }, /* R747 */
853 { 0x0000, 0x0000 }, /* R748 */
854 { 0x0000, 0x0000 }, /* R749 */
855 { 0x0000, 0x0000 }, /* R750 */
856 { 0x0000, 0x0000 }, /* R751 */
857 { 0x0000, 0x0000 }, /* R752 */
858 { 0x0000, 0x0000 }, /* R753 */
859 { 0x0000, 0x0000 }, /* R754 */
860 { 0x0000, 0x0000 }, /* R755 */
861 { 0x0000, 0x0000 }, /* R756 */
862 { 0x0000, 0x0000 }, /* R757 */
863 { 0x0000, 0x0000 }, /* R758 */
864 { 0x0000, 0x0000 }, /* R759 */
865 { 0x0000, 0x0000 }, /* R760 */
866 { 0x0000, 0x0000 }, /* R761 */
867 { 0x0000, 0x0000 }, /* R762 */
868 { 0x0000, 0x0000 }, /* R763 */
869 { 0x0000, 0x0000 }, /* R764 */
870 { 0x0000, 0x0000 }, /* R765 */
871 { 0x0000, 0x0000 }, /* R766 */
872 { 0x0000, 0x0000 }, /* R767 */
873 { 0xE1F8, 0xE1F8 }, /* R768 - AIF1 Control (1) */
874 { 0xCD1F, 0xCD1F }, /* R769 - AIF1 Control (2) */
875 { 0xF000, 0xF000 }, /* R770 - AIF1 Master/Slave */
876 { 0x01F0, 0x01F0 }, /* R771 - AIF1 BCLK */
877 { 0x0FFF, 0x0FFF }, /* R772 - AIF1ADC LRCLK */
878 { 0x0FFF, 0x0FFF }, /* R773 - AIF1DAC LRCLK */
879 { 0x0003, 0x0003 }, /* R774 - AIF1DAC Data */
880 { 0x0003, 0x0003 }, /* R775 - AIF1ADC Data */
881 { 0x0000, 0x0000 }, /* R776 */
882 { 0x0000, 0x0000 }, /* R777 */
883 { 0x0000, 0x0000 }, /* R778 */
884 { 0x0000, 0x0000 }, /* R779 */
885 { 0x0000, 0x0000 }, /* R780 */
886 { 0x0000, 0x0000 }, /* R781 */
887 { 0x0000, 0x0000 }, /* R782 */
888 { 0x0000, 0x0000 }, /* R783 */
889 { 0xF1F8, 0xF1F8 }, /* R784 - AIF2 Control (1) */
890 { 0xFD1F, 0xFD1F }, /* R785 - AIF2 Control (2) */
891 { 0xF000, 0xF000 }, /* R786 - AIF2 Master/Slave */
892 { 0x01F0, 0x01F0 }, /* R787 - AIF2 BCLK */
893 { 0x0FFF, 0x0FFF }, /* R788 - AIF2ADC LRCLK */
894 { 0x0FFF, 0x0FFF }, /* R789 - AIF2DAC LRCLK */
895 { 0x0003, 0x0003 }, /* R790 - AIF2DAC Data */
896 { 0x0003, 0x0003 }, /* R791 - AIF2ADC Data */
897 { 0x0000, 0x0000 }, /* R792 */
898 { 0x0000, 0x0000 }, /* R793 */
899 { 0x0000, 0x0000 }, /* R794 */
900 { 0x0000, 0x0000 }, /* R795 */
901 { 0x0000, 0x0000 }, /* R796 */
902 { 0x0000, 0x0000 }, /* R797 */
903 { 0x0000, 0x0000 }, /* R798 */
904 { 0x0000, 0x0000 }, /* R799 */
905 { 0x0000, 0x0000 }, /* R800 */
906 { 0x0000, 0x0000 }, /* R801 */
907 { 0x0000, 0x0000 }, /* R802 */
908 { 0x0000, 0x0000 }, /* R803 */
909 { 0x0000, 0x0000 }, /* R804 */
910 { 0x0000, 0x0000 }, /* R805 */
911 { 0x0000, 0x0000 }, /* R806 */
912 { 0x0000, 0x0000 }, /* R807 */
913 { 0x0000, 0x0000 }, /* R808 */
914 { 0x0000, 0x0000 }, /* R809 */
915 { 0x0000, 0x0000 }, /* R810 */
916 { 0x0000, 0x0000 }, /* R811 */
917 { 0x0000, 0x0000 }, /* R812 */
918 { 0x0000, 0x0000 }, /* R813 */
919 { 0x0000, 0x0000 }, /* R814 */
920 { 0x0000, 0x0000 }, /* R815 */
921 { 0x0000, 0x0000 }, /* R816 */
922 { 0x0000, 0x0000 }, /* R817 */
923 { 0x0000, 0x0000 }, /* R818 */
924 { 0x0000, 0x0000 }, /* R819 */
925 { 0x0000, 0x0000 }, /* R820 */
926 { 0x0000, 0x0000 }, /* R821 */
927 { 0x0000, 0x0000 }, /* R822 */
928 { 0x0000, 0x0000 }, /* R823 */
929 { 0x0000, 0x0000 }, /* R824 */
930 { 0x0000, 0x0000 }, /* R825 */
931 { 0x0000, 0x0000 }, /* R826 */
932 { 0x0000, 0x0000 }, /* R827 */
933 { 0x0000, 0x0000 }, /* R828 */
934 { 0x0000, 0x0000 }, /* R829 */
935 { 0x0000, 0x0000 }, /* R830 */
936 { 0x0000, 0x0000 }, /* R831 */
937 { 0x0000, 0x0000 }, /* R832 */
938 { 0x0000, 0x0000 }, /* R833 */
939 { 0x0000, 0x0000 }, /* R834 */
940 { 0x0000, 0x0000 }, /* R835 */
941 { 0x0000, 0x0000 }, /* R836 */
942 { 0x0000, 0x0000 }, /* R837 */
943 { 0x0000, 0x0000 }, /* R838 */
944 { 0x0000, 0x0000 }, /* R839 */
945 { 0x0000, 0x0000 }, /* R840 */
946 { 0x0000, 0x0000 }, /* R841 */
947 { 0x0000, 0x0000 }, /* R842 */
948 { 0x0000, 0x0000 }, /* R843 */
949 { 0x0000, 0x0000 }, /* R844 */
950 { 0x0000, 0x0000 }, /* R845 */
951 { 0x0000, 0x0000 }, /* R846 */
952 { 0x0000, 0x0000 }, /* R847 */
953 { 0x0000, 0x0000 }, /* R848 */
954 { 0x0000, 0x0000 }, /* R849 */
955 { 0x0000, 0x0000 }, /* R850 */
956 { 0x0000, 0x0000 }, /* R851 */
957 { 0x0000, 0x0000 }, /* R852 */
958 { 0x0000, 0x0000 }, /* R853 */
959 { 0x0000, 0x0000 }, /* R854 */
960 { 0x0000, 0x0000 }, /* R855 */
961 { 0x0000, 0x0000 }, /* R856 */
962 { 0x0000, 0x0000 }, /* R857 */
963 { 0x0000, 0x0000 }, /* R858 */
964 { 0x0000, 0x0000 }, /* R859 */
965 { 0x0000, 0x0000 }, /* R860 */
966 { 0x0000, 0x0000 }, /* R861 */
967 { 0x0000, 0x0000 }, /* R862 */
968 { 0x0000, 0x0000 }, /* R863 */
969 { 0x0000, 0x0000 }, /* R864 */
970 { 0x0000, 0x0000 }, /* R865 */
971 { 0x0000, 0x0000 }, /* R866 */
972 { 0x0000, 0x0000 }, /* R867 */
973 { 0x0000, 0x0000 }, /* R868 */
974 { 0x0000, 0x0000 }, /* R869 */
975 { 0x0000, 0x0000 }, /* R870 */
976 { 0x0000, 0x0000 }, /* R871 */
977 { 0x0000, 0x0000 }, /* R872 */
978 { 0x0000, 0x0000 }, /* R873 */
979 { 0x0000, 0x0000 }, /* R874 */
980 { 0x0000, 0x0000 }, /* R875 */
981 { 0x0000, 0x0000 }, /* R876 */
982 { 0x0000, 0x0000 }, /* R877 */
983 { 0x0000, 0x0000 }, /* R878 */
984 { 0x0000, 0x0000 }, /* R879 */
985 { 0x0000, 0x0000 }, /* R880 */
986 { 0x0000, 0x0000 }, /* R881 */
987 { 0x0000, 0x0000 }, /* R882 */
988 { 0x0000, 0x0000 }, /* R883 */
989 { 0x0000, 0x0000 }, /* R884 */
990 { 0x0000, 0x0000 }, /* R885 */
991 { 0x0000, 0x0000 }, /* R886 */
992 { 0x0000, 0x0000 }, /* R887 */
993 { 0x0000, 0x0000 }, /* R888 */
994 { 0x0000, 0x0000 }, /* R889 */
995 { 0x0000, 0x0000 }, /* R890 */
996 { 0x0000, 0x0000 }, /* R891 */
997 { 0x0000, 0x0000 }, /* R892 */
998 { 0x0000, 0x0000 }, /* R893 */
999 { 0x0000, 0x0000 }, /* R894 */
1000 { 0x0000, 0x0000 }, /* R895 */
1001 { 0x0000, 0x0000 }, /* R896 */
1002 { 0x0000, 0x0000 }, /* R897 */
1003 { 0x0000, 0x0000 }, /* R898 */
1004 { 0x0000, 0x0000 }, /* R899 */
1005 { 0x0000, 0x0000 }, /* R900 */
1006 { 0x0000, 0x0000 }, /* R901 */
1007 { 0x0000, 0x0000 }, /* R902 */
1008 { 0x0000, 0x0000 }, /* R903 */
1009 { 0x0000, 0x0000 }, /* R904 */
1010 { 0x0000, 0x0000 }, /* R905 */
1011 { 0x0000, 0x0000 }, /* R906 */
1012 { 0x0000, 0x0000 }, /* R907 */
1013 { 0x0000, 0x0000 }, /* R908 */
1014 { 0x0000, 0x0000 }, /* R909 */
1015 { 0x0000, 0x0000 }, /* R910 */
1016 { 0x0000, 0x0000 }, /* R911 */
1017 { 0x0000, 0x0000 }, /* R912 */
1018 { 0x0000, 0x0000 }, /* R913 */
1019 { 0x0000, 0x0000 }, /* R914 */
1020 { 0x0000, 0x0000 }, /* R915 */
1021 { 0x0000, 0x0000 }, /* R916 */
1022 { 0x0000, 0x0000 }, /* R917 */
1023 { 0x0000, 0x0000 }, /* R918 */
1024 { 0x0000, 0x0000 }, /* R919 */
1025 { 0x0000, 0x0000 }, /* R920 */
1026 { 0x0000, 0x0000 }, /* R921 */
1027 { 0x0000, 0x0000 }, /* R922 */
1028 { 0x0000, 0x0000 }, /* R923 */
1029 { 0x0000, 0x0000 }, /* R924 */
1030 { 0x0000, 0x0000 }, /* R925 */
1031 { 0x0000, 0x0000 }, /* R926 */
1032 { 0x0000, 0x0000 }, /* R927 */
1033 { 0x0000, 0x0000 }, /* R928 */
1034 { 0x0000, 0x0000 }, /* R929 */
1035 { 0x0000, 0x0000 }, /* R930 */
1036 { 0x0000, 0x0000 }, /* R931 */
1037 { 0x0000, 0x0000 }, /* R932 */
1038 { 0x0000, 0x0000 }, /* R933 */
1039 { 0x0000, 0x0000 }, /* R934 */
1040 { 0x0000, 0x0000 }, /* R935 */
1041 { 0x0000, 0x0000 }, /* R936 */
1042 { 0x0000, 0x0000 }, /* R937 */
1043 { 0x0000, 0x0000 }, /* R938 */
1044 { 0x0000, 0x0000 }, /* R939 */
1045 { 0x0000, 0x0000 }, /* R940 */
1046 { 0x0000, 0x0000 }, /* R941 */
1047 { 0x0000, 0x0000 }, /* R942 */
1048 { 0x0000, 0x0000 }, /* R943 */
1049 { 0x0000, 0x0000 }, /* R944 */
1050 { 0x0000, 0x0000 }, /* R945 */
1051 { 0x0000, 0x0000 }, /* R946 */
1052 { 0x0000, 0x0000 }, /* R947 */
1053 { 0x0000, 0x0000 }, /* R948 */
1054 { 0x0000, 0x0000 }, /* R949 */
1055 { 0x0000, 0x0000 }, /* R950 */
1056 { 0x0000, 0x0000 }, /* R951 */
1057 { 0x0000, 0x0000 }, /* R952 */
1058 { 0x0000, 0x0000 }, /* R953 */
1059 { 0x0000, 0x0000 }, /* R954 */
1060 { 0x0000, 0x0000 }, /* R955 */
1061 { 0x0000, 0x0000 }, /* R956 */
1062 { 0x0000, 0x0000 }, /* R957 */
1063 { 0x0000, 0x0000 }, /* R958 */
1064 { 0x0000, 0x0000 }, /* R959 */
1065 { 0x0000, 0x0000 }, /* R960 */
1066 { 0x0000, 0x0000 }, /* R961 */
1067 { 0x0000, 0x0000 }, /* R962 */
1068 { 0x0000, 0x0000 }, /* R963 */
1069 { 0x0000, 0x0000 }, /* R964 */
1070 { 0x0000, 0x0000 }, /* R965 */
1071 { 0x0000, 0x0000 }, /* R966 */
1072 { 0x0000, 0x0000 }, /* R967 */
1073 { 0x0000, 0x0000 }, /* R968 */
1074 { 0x0000, 0x0000 }, /* R969 */
1075 { 0x0000, 0x0000 }, /* R970 */
1076 { 0x0000, 0x0000 }, /* R971 */
1077 { 0x0000, 0x0000 }, /* R972 */
1078 { 0x0000, 0x0000 }, /* R973 */
1079 { 0x0000, 0x0000 }, /* R974 */
1080 { 0x0000, 0x0000 }, /* R975 */
1081 { 0x0000, 0x0000 }, /* R976 */
1082 { 0x0000, 0x0000 }, /* R977 */
1083 { 0x0000, 0x0000 }, /* R978 */
1084 { 0x0000, 0x0000 }, /* R979 */
1085 { 0x0000, 0x0000 }, /* R980 */
1086 { 0x0000, 0x0000 }, /* R981 */
1087 { 0x0000, 0x0000 }, /* R982 */
1088 { 0x0000, 0x0000 }, /* R983 */
1089 { 0x0000, 0x0000 }, /* R984 */
1090 { 0x0000, 0x0000 }, /* R985 */
1091 { 0x0000, 0x0000 }, /* R986 */
1092 { 0x0000, 0x0000 }, /* R987 */
1093 { 0x0000, 0x0000 }, /* R988 */
1094 { 0x0000, 0x0000 }, /* R989 */
1095 { 0x0000, 0x0000 }, /* R990 */
1096 { 0x0000, 0x0000 }, /* R991 */
1097 { 0x0000, 0x0000 }, /* R992 */
1098 { 0x0000, 0x0000 }, /* R993 */
1099 { 0x0000, 0x0000 }, /* R994 */
1100 { 0x0000, 0x0000 }, /* R995 */
1101 { 0x0000, 0x0000 }, /* R996 */
1102 { 0x0000, 0x0000 }, /* R997 */
1103 { 0x0000, 0x0000 }, /* R998 */
1104 { 0x0000, 0x0000 }, /* R999 */
1105 { 0x0000, 0x0000 }, /* R1000 */
1106 { 0x0000, 0x0000 }, /* R1001 */
1107 { 0x0000, 0x0000 }, /* R1002 */
1108 { 0x0000, 0x0000 }, /* R1003 */
1109 { 0x0000, 0x0000 }, /* R1004 */
1110 { 0x0000, 0x0000 }, /* R1005 */
1111 { 0x0000, 0x0000 }, /* R1006 */
1112 { 0x0000, 0x0000 }, /* R1007 */
1113 { 0x0000, 0x0000 }, /* R1008 */
1114 { 0x0000, 0x0000 }, /* R1009 */
1115 { 0x0000, 0x0000 }, /* R1010 */
1116 { 0x0000, 0x0000 }, /* R1011 */
1117 { 0x0000, 0x0000 }, /* R1012 */
1118 { 0x0000, 0x0000 }, /* R1013 */
1119 { 0x0000, 0x0000 }, /* R1014 */
1120 { 0x0000, 0x0000 }, /* R1015 */
1121 { 0x0000, 0x0000 }, /* R1016 */
1122 { 0x0000, 0x0000 }, /* R1017 */
1123 { 0x0000, 0x0000 }, /* R1018 */
1124 { 0x0000, 0x0000 }, /* R1019 */
1125 { 0x0000, 0x0000 }, /* R1020 */
1126 { 0x0000, 0x0000 }, /* R1021 */
1127 { 0x0000, 0x0000 }, /* R1022 */
1128 { 0x0000, 0x0000 }, /* R1023 */
1129 { 0x00FF, 0x01FF }, /* R1024 - AIF1 ADC1 Left Volume */
1130 { 0x00FF, 0x01FF }, /* R1025 - AIF1 ADC1 Right Volume */
1131 { 0x00FF, 0x01FF }, /* R1026 - AIF1 DAC1 Left Volume */
1132 { 0x00FF, 0x01FF }, /* R1027 - AIF1 DAC1 Right Volume */
1133 { 0x00FF, 0x01FF }, /* R1028 - AIF1 ADC2 Left Volume */
1134 { 0x00FF, 0x01FF }, /* R1029 - AIF1 ADC2 Right Volume */
1135 { 0x00FF, 0x01FF }, /* R1030 - AIF1 DAC2 Left Volume */
1136 { 0x00FF, 0x01FF }, /* R1031 - AIF1 DAC2 Right Volume */
1137 { 0x0000, 0x0000 }, /* R1032 */
1138 { 0x0000, 0x0000 }, /* R1033 */
1139 { 0x0000, 0x0000 }, /* R1034 */
1140 { 0x0000, 0x0000 }, /* R1035 */
1141 { 0x0000, 0x0000 }, /* R1036 */
1142 { 0x0000, 0x0000 }, /* R1037 */
1143 { 0x0000, 0x0000 }, /* R1038 */
1144 { 0x0000, 0x0000 }, /* R1039 */
1145 { 0xF800, 0xF800 }, /* R1040 - AIF1 ADC1 Filters */
1146 { 0x7800, 0x7800 }, /* R1041 - AIF1 ADC2 Filters */
1147 { 0x0000, 0x0000 }, /* R1042 */
1148 { 0x0000, 0x0000 }, /* R1043 */
1149 { 0x0000, 0x0000 }, /* R1044 */
1150 { 0x0000, 0x0000 }, /* R1045 */
1151 { 0x0000, 0x0000 }, /* R1046 */
1152 { 0x0000, 0x0000 }, /* R1047 */
1153 { 0x0000, 0x0000 }, /* R1048 */
1154 { 0x0000, 0x0000 }, /* R1049 */
1155 { 0x0000, 0x0000 }, /* R1050 */
1156 { 0x0000, 0x0000 }, /* R1051 */
1157 { 0x0000, 0x0000 }, /* R1052 */
1158 { 0x0000, 0x0000 }, /* R1053 */
1159 { 0x0000, 0x0000 }, /* R1054 */
1160 { 0x0000, 0x0000 }, /* R1055 */
1161 { 0x02B6, 0x02B6 }, /* R1056 - AIF1 DAC1 Filters (1) */
1162 { 0x3F00, 0x3F00 }, /* R1057 - AIF1 DAC1 Filters (2) */
1163 { 0x02B6, 0x02B6 }, /* R1058 - AIF1 DAC2 Filters (1) */
1164 { 0x3F00, 0x3F00 }, /* R1059 - AIF1 DAC2 Filters (2) */
1165 { 0x0000, 0x0000 }, /* R1060 */
1166 { 0x0000, 0x0000 }, /* R1061 */
1167 { 0x0000, 0x0000 }, /* R1062 */
1168 { 0x0000, 0x0000 }, /* R1063 */
1169 { 0x0000, 0x0000 }, /* R1064 */
1170 { 0x0000, 0x0000 }, /* R1065 */
1171 { 0x0000, 0x0000 }, /* R1066 */
1172 { 0x0000, 0x0000 }, /* R1067 */
1173 { 0x0000, 0x0000 }, /* R1068 */
1174 { 0x0000, 0x0000 }, /* R1069 */
1175 { 0x0000, 0x0000 }, /* R1070 */
1176 { 0x0000, 0x0000 }, /* R1071 */
1177 { 0x0000, 0x0000 }, /* R1072 */
1178 { 0x0000, 0x0000 }, /* R1073 */
1179 { 0x0000, 0x0000 }, /* R1074 */
1180 { 0x0000, 0x0000 }, /* R1075 */
1181 { 0x0000, 0x0000 }, /* R1076 */
1182 { 0x0000, 0x0000 }, /* R1077 */
1183 { 0x0000, 0x0000 }, /* R1078 */
1184 { 0x0000, 0x0000 }, /* R1079 */
1185 { 0x0000, 0x0000 }, /* R1080 */
1186 { 0x0000, 0x0000 }, /* R1081 */
1187 { 0x0000, 0x0000 }, /* R1082 */
1188 { 0x0000, 0x0000 }, /* R1083 */
1189 { 0x0000, 0x0000 }, /* R1084 */
1190 { 0x0000, 0x0000 }, /* R1085 */
1191 { 0x0000, 0x0000 }, /* R1086 */
1192 { 0x0000, 0x0000 }, /* R1087 */
1193 { 0xFFFF, 0xFFFF }, /* R1088 - AIF1 DRC1 (1) */
1194 { 0x1FFF, 0x1FFF }, /* R1089 - AIF1 DRC1 (2) */
1195 { 0xFFFF, 0xFFFF }, /* R1090 - AIF1 DRC1 (3) */
1196 { 0x07FF, 0x07FF }, /* R1091 - AIF1 DRC1 (4) */
1197 { 0x03FF, 0x03FF }, /* R1092 - AIF1 DRC1 (5) */
1198 { 0x0000, 0x0000 }, /* R1093 */
1199 { 0x0000, 0x0000 }, /* R1094 */
1200 { 0x0000, 0x0000 }, /* R1095 */
1201 { 0x0000, 0x0000 }, /* R1096 */
1202 { 0x0000, 0x0000 }, /* R1097 */
1203 { 0x0000, 0x0000 }, /* R1098 */
1204 { 0x0000, 0x0000 }, /* R1099 */
1205 { 0x0000, 0x0000 }, /* R1100 */
1206 { 0x0000, 0x0000 }, /* R1101 */
1207 { 0x0000, 0x0000 }, /* R1102 */
1208 { 0x0000, 0x0000 }, /* R1103 */
1209 { 0xFFFF, 0xFFFF }, /* R1104 - AIF1 DRC2 (1) */
1210 { 0x1FFF, 0x1FFF }, /* R1105 - AIF1 DRC2 (2) */
1211 { 0xFFFF, 0xFFFF }, /* R1106 - AIF1 DRC2 (3) */
1212 { 0x07FF, 0x07FF }, /* R1107 - AIF1 DRC2 (4) */
1213 { 0x03FF, 0x03FF }, /* R1108 - AIF1 DRC2 (5) */
1214 { 0x0000, 0x0000 }, /* R1109 */
1215 { 0x0000, 0x0000 }, /* R1110 */
1216 { 0x0000, 0x0000 }, /* R1111 */
1217 { 0x0000, 0x0000 }, /* R1112 */
1218 { 0x0000, 0x0000 }, /* R1113 */
1219 { 0x0000, 0x0000 }, /* R1114 */
1220 { 0x0000, 0x0000 }, /* R1115 */
1221 { 0x0000, 0x0000 }, /* R1116 */
1222 { 0x0000, 0x0000 }, /* R1117 */
1223 { 0x0000, 0x0000 }, /* R1118 */
1224 { 0x0000, 0x0000 }, /* R1119 */
1225 { 0x0000, 0x0000 }, /* R1120 */
1226 { 0x0000, 0x0000 }, /* R1121 */
1227 { 0x0000, 0x0000 }, /* R1122 */
1228 { 0x0000, 0x0000 }, /* R1123 */
1229 { 0x0000, 0x0000 }, /* R1124 */
1230 { 0x0000, 0x0000 }, /* R1125 */
1231 { 0x0000, 0x0000 }, /* R1126 */
1232 { 0x0000, 0x0000 }, /* R1127 */
1233 { 0x0000, 0x0000 }, /* R1128 */
1234 { 0x0000, 0x0000 }, /* R1129 */
1235 { 0x0000, 0x0000 }, /* R1130 */
1236 { 0x0000, 0x0000 }, /* R1131 */
1237 { 0x0000, 0x0000 }, /* R1132 */
1238 { 0x0000, 0x0000 }, /* R1133 */
1239 { 0x0000, 0x0000 }, /* R1134 */
1240 { 0x0000, 0x0000 }, /* R1135 */
1241 { 0x0000, 0x0000 }, /* R1136 */
1242 { 0x0000, 0x0000 }, /* R1137 */
1243 { 0x0000, 0x0000 }, /* R1138 */
1244 { 0x0000, 0x0000 }, /* R1139 */
1245 { 0x0000, 0x0000 }, /* R1140 */
1246 { 0x0000, 0x0000 }, /* R1141 */
1247 { 0x0000, 0x0000 }, /* R1142 */
1248 { 0x0000, 0x0000 }, /* R1143 */
1249 { 0x0000, 0x0000 }, /* R1144 */
1250 { 0x0000, 0x0000 }, /* R1145 */
1251 { 0x0000, 0x0000 }, /* R1146 */
1252 { 0x0000, 0x0000 }, /* R1147 */
1253 { 0x0000, 0x0000 }, /* R1148 */
1254 { 0x0000, 0x0000 }, /* R1149 */
1255 { 0x0000, 0x0000 }, /* R1150 */
1256 { 0x0000, 0x0000 }, /* R1151 */
1257 { 0xFFFF, 0xFFFF }, /* R1152 - AIF1 DAC1 EQ Gains (1) */
1258 { 0xFFC0, 0xFFC0 }, /* R1153 - AIF1 DAC1 EQ Gains (2) */
1259 { 0xFFFF, 0xFFFF }, /* R1154 - AIF1 DAC1 EQ Band 1 A */
1260 { 0xFFFF, 0xFFFF }, /* R1155 - AIF1 DAC1 EQ Band 1 B */
1261 { 0xFFFF, 0xFFFF }, /* R1156 - AIF1 DAC1 EQ Band 1 PG */
1262 { 0xFFFF, 0xFFFF }, /* R1157 - AIF1 DAC1 EQ Band 2 A */
1263 { 0xFFFF, 0xFFFF }, /* R1158 - AIF1 DAC1 EQ Band 2 B */
1264 { 0xFFFF, 0xFFFF }, /* R1159 - AIF1 DAC1 EQ Band 2 C */
1265 { 0xFFFF, 0xFFFF }, /* R1160 - AIF1 DAC1 EQ Band 2 PG */
1266 { 0xFFFF, 0xFFFF }, /* R1161 - AIF1 DAC1 EQ Band 3 A */
1267 { 0xFFFF, 0xFFFF }, /* R1162 - AIF1 DAC1 EQ Band 3 B */
1268 { 0xFFFF, 0xFFFF }, /* R1163 - AIF1 DAC1 EQ Band 3 C */
1269 { 0xFFFF, 0xFFFF }, /* R1164 - AIF1 DAC1 EQ Band 3 PG */
1270 { 0xFFFF, 0xFFFF }, /* R1165 - AIF1 DAC1 EQ Band 4 A */
1271 { 0xFFFF, 0xFFFF }, /* R1166 - AIF1 DAC1 EQ Band 4 B */
1272 { 0xFFFF, 0xFFFF }, /* R1167 - AIF1 DAC1 EQ Band 4 C */
1273 { 0xFFFF, 0xFFFF }, /* R1168 - AIF1 DAC1 EQ Band 4 PG */
1274 { 0xFFFF, 0xFFFF }, /* R1169 - AIF1 DAC1 EQ Band 5 A */
1275 { 0xFFFF, 0xFFFF }, /* R1170 - AIF1 DAC1 EQ Band 5 B */
1276 { 0xFFFF, 0xFFFF }, /* R1171 - AIF1 DAC1 EQ Band 5 PG */
1277 { 0x0000, 0x0000 }, /* R1172 */
1278 { 0x0000, 0x0000 }, /* R1173 */
1279 { 0x0000, 0x0000 }, /* R1174 */
1280 { 0x0000, 0x0000 }, /* R1175 */
1281 { 0x0000, 0x0000 }, /* R1176 */
1282 { 0x0000, 0x0000 }, /* R1177 */
1283 { 0x0000, 0x0000 }, /* R1178 */
1284 { 0x0000, 0x0000 }, /* R1179 */
1285 { 0x0000, 0x0000 }, /* R1180 */
1286 { 0x0000, 0x0000 }, /* R1181 */
1287 { 0x0000, 0x0000 }, /* R1182 */
1288 { 0x0000, 0x0000 }, /* R1183 */
1289 { 0xFFFF, 0xFFFF }, /* R1184 - AIF1 DAC2 EQ Gains (1) */
1290 { 0xFFC0, 0xFFC0 }, /* R1185 - AIF1 DAC2 EQ Gains (2) */
1291 { 0xFFFF, 0xFFFF }, /* R1186 - AIF1 DAC2 EQ Band 1 A */
1292 { 0xFFFF, 0xFFFF }, /* R1187 - AIF1 DAC2 EQ Band 1 B */
1293 { 0xFFFF, 0xFFFF }, /* R1188 - AIF1 DAC2 EQ Band 1 PG */
1294 { 0xFFFF, 0xFFFF }, /* R1189 - AIF1 DAC2 EQ Band 2 A */
1295 { 0xFFFF, 0xFFFF }, /* R1190 - AIF1 DAC2 EQ Band 2 B */
1296 { 0xFFFF, 0xFFFF }, /* R1191 - AIF1 DAC2 EQ Band 2 C */
1297 { 0xFFFF, 0xFFFF }, /* R1192 - AIF1 DAC2 EQ Band 2 PG */
1298 { 0xFFFF, 0xFFFF }, /* R1193 - AIF1 DAC2 EQ Band 3 A */
1299 { 0xFFFF, 0xFFFF }, /* R1194 - AIF1 DAC2 EQ Band 3 B */
1300 { 0xFFFF, 0xFFFF }, /* R1195 - AIF1 DAC2 EQ Band 3 C */
1301 { 0xFFFF, 0xFFFF }, /* R1196 - AIF1 DAC2 EQ Band 3 PG */
1302 { 0xFFFF, 0xFFFF }, /* R1197 - AIF1 DAC2 EQ Band 4 A */
1303 { 0xFFFF, 0xFFFF }, /* R1198 - AIF1 DAC2 EQ Band 4 B */
1304 { 0xFFFF, 0xFFFF }, /* R1199 - AIF1 DAC2 EQ Band 4 C */
1305 { 0xFFFF, 0xFFFF }, /* R1200 - AIF1 DAC2 EQ Band 4 PG */
1306 { 0xFFFF, 0xFFFF }, /* R1201 - AIF1 DAC2 EQ Band 5 A */
1307 { 0xFFFF, 0xFFFF }, /* R1202 - AIF1 DAC2 EQ Band 5 B */
1308 { 0xFFFF, 0xFFFF }, /* R1203 - AIF1 DAC2 EQ Band 5 PG */
1309 { 0x0000, 0x0000 }, /* R1204 */
1310 { 0x0000, 0x0000 }, /* R1205 */
1311 { 0x0000, 0x0000 }, /* R1206 */
1312 { 0x0000, 0x0000 }, /* R1207 */
1313 { 0x0000, 0x0000 }, /* R1208 */
1314 { 0x0000, 0x0000 }, /* R1209 */
1315 { 0x0000, 0x0000 }, /* R1210 */
1316 { 0x0000, 0x0000 }, /* R1211 */
1317 { 0x0000, 0x0000 }, /* R1212 */
1318 { 0x0000, 0x0000 }, /* R1213 */
1319 { 0x0000, 0x0000 }, /* R1214 */
1320 { 0x0000, 0x0000 }, /* R1215 */
1321 { 0x0000, 0x0000 }, /* R1216 */
1322 { 0x0000, 0x0000 }, /* R1217 */
1323 { 0x0000, 0x0000 }, /* R1218 */
1324 { 0x0000, 0x0000 }, /* R1219 */
1325 { 0x0000, 0x0000 }, /* R1220 */
1326 { 0x0000, 0x0000 }, /* R1221 */
1327 { 0x0000, 0x0000 }, /* R1222 */
1328 { 0x0000, 0x0000 }, /* R1223 */
1329 { 0x0000, 0x0000 }, /* R1224 */
1330 { 0x0000, 0x0000 }, /* R1225 */
1331 { 0x0000, 0x0000 }, /* R1226 */
1332 { 0x0000, 0x0000 }, /* R1227 */
1333 { 0x0000, 0x0000 }, /* R1228 */
1334 { 0x0000, 0x0000 }, /* R1229 */
1335 { 0x0000, 0x0000 }, /* R1230 */
1336 { 0x0000, 0x0000 }, /* R1231 */
1337 { 0x0000, 0x0000 }, /* R1232 */
1338 { 0x0000, 0x0000 }, /* R1233 */
1339 { 0x0000, 0x0000 }, /* R1234 */
1340 { 0x0000, 0x0000 }, /* R1235 */
1341 { 0x0000, 0x0000 }, /* R1236 */
1342 { 0x0000, 0x0000 }, /* R1237 */
1343 { 0x0000, 0x0000 }, /* R1238 */
1344 { 0x0000, 0x0000 }, /* R1239 */
1345 { 0x0000, 0x0000 }, /* R1240 */
1346 { 0x0000, 0x0000 }, /* R1241 */
1347 { 0x0000, 0x0000 }, /* R1242 */
1348 { 0x0000, 0x0000 }, /* R1243 */
1349 { 0x0000, 0x0000 }, /* R1244 */
1350 { 0x0000, 0x0000 }, /* R1245 */
1351 { 0x0000, 0x0000 }, /* R1246 */
1352 { 0x0000, 0x0000 }, /* R1247 */
1353 { 0x0000, 0x0000 }, /* R1248 */
1354 { 0x0000, 0x0000 }, /* R1249 */
1355 { 0x0000, 0x0000 }, /* R1250 */
1356 { 0x0000, 0x0000 }, /* R1251 */
1357 { 0x0000, 0x0000 }, /* R1252 */
1358 { 0x0000, 0x0000 }, /* R1253 */
1359 { 0x0000, 0x0000 }, /* R1254 */
1360 { 0x0000, 0x0000 }, /* R1255 */
1361 { 0x0000, 0x0000 }, /* R1256 */
1362 { 0x0000, 0x0000 }, /* R1257 */
1363 { 0x0000, 0x0000 }, /* R1258 */
1364 { 0x0000, 0x0000 }, /* R1259 */
1365 { 0x0000, 0x0000 }, /* R1260 */
1366 { 0x0000, 0x0000 }, /* R1261 */
1367 { 0x0000, 0x0000 }, /* R1262 */
1368 { 0x0000, 0x0000 }, /* R1263 */
1369 { 0x0000, 0x0000 }, /* R1264 */
1370 { 0x0000, 0x0000 }, /* R1265 */
1371 { 0x0000, 0x0000 }, /* R1266 */
1372 { 0x0000, 0x0000 }, /* R1267 */
1373 { 0x0000, 0x0000 }, /* R1268 */
1374 { 0x0000, 0x0000 }, /* R1269 */
1375 { 0x0000, 0x0000 }, /* R1270 */
1376 { 0x0000, 0x0000 }, /* R1271 */
1377 { 0x0000, 0x0000 }, /* R1272 */
1378 { 0x0000, 0x0000 }, /* R1273 */
1379 { 0x0000, 0x0000 }, /* R1274 */
1380 { 0x0000, 0x0000 }, /* R1275 */
1381 { 0x0000, 0x0000 }, /* R1276 */
1382 { 0x0000, 0x0000 }, /* R1277 */
1383 { 0x0000, 0x0000 }, /* R1278 */
1384 { 0x0000, 0x0000 }, /* R1279 */
1385 { 0x00FF, 0x01FF }, /* R1280 - AIF2 ADC Left Volume */
1386 { 0x00FF, 0x01FF }, /* R1281 - AIF2 ADC Right Volume */
1387 { 0x00FF, 0x01FF }, /* R1282 - AIF2 DAC Left Volume */
1388 { 0x00FF, 0x01FF }, /* R1283 - AIF2 DAC Right Volume */
1389 { 0x0000, 0x0000 }, /* R1284 */
1390 { 0x0000, 0x0000 }, /* R1285 */
1391 { 0x0000, 0x0000 }, /* R1286 */
1392 { 0x0000, 0x0000 }, /* R1287 */
1393 { 0x0000, 0x0000 }, /* R1288 */
1394 { 0x0000, 0x0000 }, /* R1289 */
1395 { 0x0000, 0x0000 }, /* R1290 */
1396 { 0x0000, 0x0000 }, /* R1291 */
1397 { 0x0000, 0x0000 }, /* R1292 */
1398 { 0x0000, 0x0000 }, /* R1293 */
1399 { 0x0000, 0x0000 }, /* R1294 */
1400 { 0x0000, 0x0000 }, /* R1295 */
1401 { 0xF800, 0xF800 }, /* R1296 - AIF2 ADC Filters */
1402 { 0x0000, 0x0000 }, /* R1297 */
1403 { 0x0000, 0x0000 }, /* R1298 */
1404 { 0x0000, 0x0000 }, /* R1299 */
1405 { 0x0000, 0x0000 }, /* R1300 */
1406 { 0x0000, 0x0000 }, /* R1301 */
1407 { 0x0000, 0x0000 }, /* R1302 */
1408 { 0x0000, 0x0000 }, /* R1303 */
1409 { 0x0000, 0x0000 }, /* R1304 */
1410 { 0x0000, 0x0000 }, /* R1305 */
1411 { 0x0000, 0x0000 }, /* R1306 */
1412 { 0x0000, 0x0000 }, /* R1307 */
1413 { 0x0000, 0x0000 }, /* R1308 */
1414 { 0x0000, 0x0000 }, /* R1309 */
1415 { 0x0000, 0x0000 }, /* R1310 */
1416 { 0x0000, 0x0000 }, /* R1311 */
1417 { 0x02B6, 0x02B6 }, /* R1312 - AIF2 DAC Filters (1) */
1418 { 0x3F00, 0x3F00 }, /* R1313 - AIF2 DAC Filters (2) */
1419 { 0x0000, 0x0000 }, /* R1314 */
1420 { 0x0000, 0x0000 }, /* R1315 */
1421 { 0x0000, 0x0000 }, /* R1316 */
1422 { 0x0000, 0x0000 }, /* R1317 */
1423 { 0x0000, 0x0000 }, /* R1318 */
1424 { 0x0000, 0x0000 }, /* R1319 */
1425 { 0x0000, 0x0000 }, /* R1320 */
1426 { 0x0000, 0x0000 }, /* R1321 */
1427 { 0x0000, 0x0000 }, /* R1322 */
1428 { 0x0000, 0x0000 }, /* R1323 */
1429 { 0x0000, 0x0000 }, /* R1324 */
1430 { 0x0000, 0x0000 }, /* R1325 */
1431 { 0x0000, 0x0000 }, /* R1326 */
1432 { 0x0000, 0x0000 }, /* R1327 */
1433 { 0x0000, 0x0000 }, /* R1328 */
1434 { 0x0000, 0x0000 }, /* R1329 */
1435 { 0x0000, 0x0000 }, /* R1330 */
1436 { 0x0000, 0x0000 }, /* R1331 */
1437 { 0x0000, 0x0000 }, /* R1332 */
1438 { 0x0000, 0x0000 }, /* R1333 */
1439 { 0x0000, 0x0000 }, /* R1334 */
1440 { 0x0000, 0x0000 }, /* R1335 */
1441 { 0x0000, 0x0000 }, /* R1336 */
1442 { 0x0000, 0x0000 }, /* R1337 */
1443 { 0x0000, 0x0000 }, /* R1338 */
1444 { 0x0000, 0x0000 }, /* R1339 */
1445 { 0x0000, 0x0000 }, /* R1340 */
1446 { 0x0000, 0x0000 }, /* R1341 */
1447 { 0x0000, 0x0000 }, /* R1342 */
1448 { 0x0000, 0x0000 }, /* R1343 */
1449 { 0xFFFF, 0xFFFF }, /* R1344 - AIF2 DRC (1) */
1450 { 0x1FFF, 0x1FFF }, /* R1345 - AIF2 DRC (2) */
1451 { 0xFFFF, 0xFFFF }, /* R1346 - AIF2 DRC (3) */
1452 { 0x07FF, 0x07FF }, /* R1347 - AIF2 DRC (4) */
1453 { 0x03FF, 0x03FF }, /* R1348 - AIF2 DRC (5) */
1454 { 0x0000, 0x0000 }, /* R1349 */
1455 { 0x0000, 0x0000 }, /* R1350 */
1456 { 0x0000, 0x0000 }, /* R1351 */
1457 { 0x0000, 0x0000 }, /* R1352 */
1458 { 0x0000, 0x0000 }, /* R1353 */
1459 { 0x0000, 0x0000 }, /* R1354 */
1460 { 0x0000, 0x0000 }, /* R1355 */
1461 { 0x0000, 0x0000 }, /* R1356 */
1462 { 0x0000, 0x0000 }, /* R1357 */
1463 { 0x0000, 0x0000 }, /* R1358 */
1464 { 0x0000, 0x0000 }, /* R1359 */
1465 { 0x0000, 0x0000 }, /* R1360 */
1466 { 0x0000, 0x0000 }, /* R1361 */
1467 { 0x0000, 0x0000 }, /* R1362 */
1468 { 0x0000, 0x0000 }, /* R1363 */
1469 { 0x0000, 0x0000 }, /* R1364 */
1470 { 0x0000, 0x0000 }, /* R1365 */
1471 { 0x0000, 0x0000 }, /* R1366 */
1472 { 0x0000, 0x0000 }, /* R1367 */
1473 { 0x0000, 0x0000 }, /* R1368 */
1474 { 0x0000, 0x0000 }, /* R1369 */
1475 { 0x0000, 0x0000 }, /* R1370 */
1476 { 0x0000, 0x0000 }, /* R1371 */
1477 { 0x0000, 0x0000 }, /* R1372 */
1478 { 0x0000, 0x0000 }, /* R1373 */
1479 { 0x0000, 0x0000 }, /* R1374 */
1480 { 0x0000, 0x0000 }, /* R1375 */
1481 { 0x0000, 0x0000 }, /* R1376 */
1482 { 0x0000, 0x0000 }, /* R1377 */
1483 { 0x0000, 0x0000 }, /* R1378 */
1484 { 0x0000, 0x0000 }, /* R1379 */
1485 { 0x0000, 0x0000 }, /* R1380 */
1486 { 0x0000, 0x0000 }, /* R1381 */
1487 { 0x0000, 0x0000 }, /* R1382 */
1488 { 0x0000, 0x0000 }, /* R1383 */
1489 { 0x0000, 0x0000 }, /* R1384 */
1490 { 0x0000, 0x0000 }, /* R1385 */
1491 { 0x0000, 0x0000 }, /* R1386 */
1492 { 0x0000, 0x0000 }, /* R1387 */
1493 { 0x0000, 0x0000 }, /* R1388 */
1494 { 0x0000, 0x0000 }, /* R1389 */
1495 { 0x0000, 0x0000 }, /* R1390 */
1496 { 0x0000, 0x0000 }, /* R1391 */
1497 { 0x0000, 0x0000 }, /* R1392 */
1498 { 0x0000, 0x0000 }, /* R1393 */
1499 { 0x0000, 0x0000 }, /* R1394 */
1500 { 0x0000, 0x0000 }, /* R1395 */
1501 { 0x0000, 0x0000 }, /* R1396 */
1502 { 0x0000, 0x0000 }, /* R1397 */
1503 { 0x0000, 0x0000 }, /* R1398 */
1504 { 0x0000, 0x0000 }, /* R1399 */
1505 { 0x0000, 0x0000 }, /* R1400 */
1506 { 0x0000, 0x0000 }, /* R1401 */
1507 { 0x0000, 0x0000 }, /* R1402 */
1508 { 0x0000, 0x0000 }, /* R1403 */
1509 { 0x0000, 0x0000 }, /* R1404 */
1510 { 0x0000, 0x0000 }, /* R1405 */
1511 { 0x0000, 0x0000 }, /* R1406 */
1512 { 0x0000, 0x0000 }, /* R1407 */
1513 { 0xFFFF, 0xFFFF }, /* R1408 - AIF2 EQ Gains (1) */
1514 { 0xFFC0, 0xFFC0 }, /* R1409 - AIF2 EQ Gains (2) */
1515 { 0xFFFF, 0xFFFF }, /* R1410 - AIF2 EQ Band 1 A */
1516 { 0xFFFF, 0xFFFF }, /* R1411 - AIF2 EQ Band 1 B */
1517 { 0xFFFF, 0xFFFF }, /* R1412 - AIF2 EQ Band 1 PG */
1518 { 0xFFFF, 0xFFFF }, /* R1413 - AIF2 EQ Band 2 A */
1519 { 0xFFFF, 0xFFFF }, /* R1414 - AIF2 EQ Band 2 B */
1520 { 0xFFFF, 0xFFFF }, /* R1415 - AIF2 EQ Band 2 C */
1521 { 0xFFFF, 0xFFFF }, /* R1416 - AIF2 EQ Band 2 PG */
1522 { 0xFFFF, 0xFFFF }, /* R1417 - AIF2 EQ Band 3 A */
1523 { 0xFFFF, 0xFFFF }, /* R1418 - AIF2 EQ Band 3 B */
1524 { 0xFFFF, 0xFFFF }, /* R1419 - AIF2 EQ Band 3 C */
1525 { 0xFFFF, 0xFFFF }, /* R1420 - AIF2 EQ Band 3 PG */
1526 { 0xFFFF, 0xFFFF }, /* R1421 - AIF2 EQ Band 4 A */
1527 { 0xFFFF, 0xFFFF }, /* R1422 - AIF2 EQ Band 4 B */
1528 { 0xFFFF, 0xFFFF }, /* R1423 - AIF2 EQ Band 4 C */
1529 { 0xFFFF, 0xFFFF }, /* R1424 - AIF2 EQ Band 4 PG */
1530 { 0xFFFF, 0xFFFF }, /* R1425 - AIF2 EQ Band 5 A */
1531 { 0xFFFF, 0xFFFF }, /* R1426 - AIF2 EQ Band 5 B */
1532 { 0xFFFF, 0xFFFF }, /* R1427 - AIF2 EQ Band 5 PG */
1533 { 0x0000, 0x0000 }, /* R1428 */
1534 { 0x0000, 0x0000 }, /* R1429 */
1535 { 0x0000, 0x0000 }, /* R1430 */
1536 { 0x0000, 0x0000 }, /* R1431 */
1537 { 0x0000, 0x0000 }, /* R1432 */
1538 { 0x0000, 0x0000 }, /* R1433 */
1539 { 0x0000, 0x0000 }, /* R1434 */
1540 { 0x0000, 0x0000 }, /* R1435 */
1541 { 0x0000, 0x0000 }, /* R1436 */
1542 { 0x0000, 0x0000 }, /* R1437 */
1543 { 0x0000, 0x0000 }, /* R1438 */
1544 { 0x0000, 0x0000 }, /* R1439 */
1545 { 0x0000, 0x0000 }, /* R1440 */
1546 { 0x0000, 0x0000 }, /* R1441 */
1547 { 0x0000, 0x0000 }, /* R1442 */
1548 { 0x0000, 0x0000 }, /* R1443 */
1549 { 0x0000, 0x0000 }, /* R1444 */
1550 { 0x0000, 0x0000 }, /* R1445 */
1551 { 0x0000, 0x0000 }, /* R1446 */
1552 { 0x0000, 0x0000 }, /* R1447 */
1553 { 0x0000, 0x0000 }, /* R1448 */
1554 { 0x0000, 0x0000 }, /* R1449 */
1555 { 0x0000, 0x0000 }, /* R1450 */
1556 { 0x0000, 0x0000 }, /* R1451 */
1557 { 0x0000, 0x0000 }, /* R1452 */
1558 { 0x0000, 0x0000 }, /* R1453 */
1559 { 0x0000, 0x0000 }, /* R1454 */
1560 { 0x0000, 0x0000 }, /* R1455 */
1561 { 0x0000, 0x0000 }, /* R1456 */
1562 { 0x0000, 0x0000 }, /* R1457 */
1563 { 0x0000, 0x0000 }, /* R1458 */
1564 { 0x0000, 0x0000 }, /* R1459 */
1565 { 0x0000, 0x0000 }, /* R1460 */
1566 { 0x0000, 0x0000 }, /* R1461 */
1567 { 0x0000, 0x0000 }, /* R1462 */
1568 { 0x0000, 0x0000 }, /* R1463 */
1569 { 0x0000, 0x0000 }, /* R1464 */
1570 { 0x0000, 0x0000 }, /* R1465 */
1571 { 0x0000, 0x0000 }, /* R1466 */
1572 { 0x0000, 0x0000 }, /* R1467 */
1573 { 0x0000, 0x0000 }, /* R1468 */
1574 { 0x0000, 0x0000 }, /* R1469 */
1575 { 0x0000, 0x0000 }, /* R1470 */
1576 { 0x0000, 0x0000 }, /* R1471 */
1577 { 0x0000, 0x0000 }, /* R1472 */
1578 { 0x0000, 0x0000 }, /* R1473 */
1579 { 0x0000, 0x0000 }, /* R1474 */
1580 { 0x0000, 0x0000 }, /* R1475 */
1581 { 0x0000, 0x0000 }, /* R1476 */
1582 { 0x0000, 0x0000 }, /* R1477 */
1583 { 0x0000, 0x0000 }, /* R1478 */
1584 { 0x0000, 0x0000 }, /* R1479 */
1585 { 0x0000, 0x0000 }, /* R1480 */
1586 { 0x0000, 0x0000 }, /* R1481 */
1587 { 0x0000, 0x0000 }, /* R1482 */
1588 { 0x0000, 0x0000 }, /* R1483 */
1589 { 0x0000, 0x0000 }, /* R1484 */
1590 { 0x0000, 0x0000 }, /* R1485 */
1591 { 0x0000, 0x0000 }, /* R1486 */
1592 { 0x0000, 0x0000 }, /* R1487 */
1593 { 0x0000, 0x0000 }, /* R1488 */
1594 { 0x0000, 0x0000 }, /* R1489 */
1595 { 0x0000, 0x0000 }, /* R1490 */
1596 { 0x0000, 0x0000 }, /* R1491 */
1597 { 0x0000, 0x0000 }, /* R1492 */
1598 { 0x0000, 0x0000 }, /* R1493 */
1599 { 0x0000, 0x0000 }, /* R1494 */
1600 { 0x0000, 0x0000 }, /* R1495 */
1601 { 0x0000, 0x0000 }, /* R1496 */
1602 { 0x0000, 0x0000 }, /* R1497 */
1603 { 0x0000, 0x0000 }, /* R1498 */
1604 { 0x0000, 0x0000 }, /* R1499 */
1605 { 0x0000, 0x0000 }, /* R1500 */
1606 { 0x0000, 0x0000 }, /* R1501 */
1607 { 0x0000, 0x0000 }, /* R1502 */
1608 { 0x0000, 0x0000 }, /* R1503 */
1609 { 0x0000, 0x0000 }, /* R1504 */
1610 { 0x0000, 0x0000 }, /* R1505 */
1611 { 0x0000, 0x0000 }, /* R1506 */
1612 { 0x0000, 0x0000 }, /* R1507 */
1613 { 0x0000, 0x0000 }, /* R1508 */
1614 { 0x0000, 0x0000 }, /* R1509 */
1615 { 0x0000, 0x0000 }, /* R1510 */
1616 { 0x0000, 0x0000 }, /* R1511 */
1617 { 0x0000, 0x0000 }, /* R1512 */
1618 { 0x0000, 0x0000 }, /* R1513 */
1619 { 0x0000, 0x0000 }, /* R1514 */
1620 { 0x0000, 0x0000 }, /* R1515 */
1621 { 0x0000, 0x0000 }, /* R1516 */
1622 { 0x0000, 0x0000 }, /* R1517 */
1623 { 0x0000, 0x0000 }, /* R1518 */
1624 { 0x0000, 0x0000 }, /* R1519 */
1625 { 0x0000, 0x0000 }, /* R1520 */
1626 { 0x0000, 0x0000 }, /* R1521 */
1627 { 0x0000, 0x0000 }, /* R1522 */
1628 { 0x0000, 0x0000 }, /* R1523 */
1629 { 0x0000, 0x0000 }, /* R1524 */
1630 { 0x0000, 0x0000 }, /* R1525 */
1631 { 0x0000, 0x0000 }, /* R1526 */
1632 { 0x0000, 0x0000 }, /* R1527 */
1633 { 0x0000, 0x0000 }, /* R1528 */
1634 { 0x0000, 0x0000 }, /* R1529 */
1635 { 0x0000, 0x0000 }, /* R1530 */
1636 { 0x0000, 0x0000 }, /* R1531 */
1637 { 0x0000, 0x0000 }, /* R1532 */
1638 { 0x0000, 0x0000 }, /* R1533 */
1639 { 0x0000, 0x0000 }, /* R1534 */
1640 { 0x0000, 0x0000 }, /* R1535 */
1641 { 0x01EF, 0x01EF }, /* R1536 - DAC1 Mixer Volumes */
1642 { 0x0037, 0x0037 }, /* R1537 - DAC1 Left Mixer Routing */
1643 { 0x0037, 0x0037 }, /* R1538 - DAC1 Right Mixer Routing */
1644 { 0x01EF, 0x01EF }, /* R1539 - DAC2 Mixer Volumes */
1645 { 0x0037, 0x0037 }, /* R1540 - DAC2 Left Mixer Routing */
1646 { 0x0037, 0x0037 }, /* R1541 - DAC2 Right Mixer Routing */
1647 { 0x0003, 0x0003 }, /* R1542 - AIF1 ADC1 Left Mixer Routing */
1648 { 0x0003, 0x0003 }, /* R1543 - AIF1 ADC1 Right Mixer Routing */
1649 { 0x0003, 0x0003 }, /* R1544 - AIF1 ADC2 Left Mixer Routing */
1650 { 0x0003, 0x0003 }, /* R1545 - AIF1 ADC2 Right mixer Routing */
1651 { 0x0000, 0x0000 }, /* R1546 */
1652 { 0x0000, 0x0000 }, /* R1547 */
1653 { 0x0000, 0x0000 }, /* R1548 */
1654 { 0x0000, 0x0000 }, /* R1549 */
1655 { 0x0000, 0x0000 }, /* R1550 */
1656 { 0x0000, 0x0000 }, /* R1551 */
1657 { 0x02FF, 0x03FF }, /* R1552 - DAC1 Left Volume */
1658 { 0x02FF, 0x03FF }, /* R1553 - DAC1 Right Volume */
1659 { 0x02FF, 0x03FF }, /* R1554 - DAC2 Left Volume */
1660 { 0x02FF, 0x03FF }, /* R1555 - DAC2 Right Volume */
1661 { 0x0003, 0x0003 }, /* R1556 - DAC Softmute */
1662 { 0x0000, 0x0000 }, /* R1557 */
1663 { 0x0000, 0x0000 }, /* R1558 */
1664 { 0x0000, 0x0000 }, /* R1559 */
1665 { 0x0000, 0x0000 }, /* R1560 */
1666 { 0x0000, 0x0000 }, /* R1561 */
1667 { 0x0000, 0x0000 }, /* R1562 */
1668 { 0x0000, 0x0000 }, /* R1563 */
1669 { 0x0000, 0x0000 }, /* R1564 */
1670 { 0x0000, 0x0000 }, /* R1565 */
1671 { 0x0000, 0x0000 }, /* R1566 */
1672 { 0x0000, 0x0000 }, /* R1567 */
1673 { 0x0003, 0x0003 }, /* R1568 - Oversampling */
1674 { 0x03C3, 0x03C3 }, /* R1569 - Sidetone */
1675};
1676
1677static int wm8994_readable(unsigned int reg) 112static int wm8994_readable(unsigned int reg)
1678{ 113{
1679 switch (reg) { 114 switch (reg) {
@@ -1696,14 +131,14 @@ static int wm8994_readable(unsigned int reg)
1696 break; 131 break;
1697 } 132 }
1698 133
1699 if (reg >= ARRAY_SIZE(access_masks)) 134 if (reg >= WM8994_CACHE_SIZE)
1700 return 0; 135 return 0;
1701 return access_masks[reg].readable != 0; 136 return wm8994_access_masks[reg].readable != 0;
1702} 137}
1703 138
1704static int wm8994_volatile(unsigned int reg) 139static int wm8994_volatile(unsigned int reg)
1705{ 140{
1706 if (reg >= WM8994_REG_CACHE_SIZE) 141 if (reg >= WM8994_CACHE_SIZE)
1707 return 1; 142 return 1;
1708 143
1709 switch (reg) { 144 switch (reg) {
@@ -1714,6 +149,8 @@ static int wm8994_volatile(unsigned int reg)
1714 case WM8994_RATE_STATUS: 149 case WM8994_RATE_STATUS:
1715 case WM8994_LDO_1: 150 case WM8994_LDO_1:
1716 case WM8994_LDO_2: 151 case WM8994_LDO_2:
152 case WM8958_DSP2_EXECCONTROL:
153 case WM8958_MIC_DETECT_3:
1717 return 1; 154 return 1;
1718 default: 155 default:
1719 return 0; 156 return 0;
@@ -1723,14 +160,16 @@ static int wm8994_volatile(unsigned int reg)
1723static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg, 160static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
1724 unsigned int value) 161 unsigned int value)
1725{ 162{
1726 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 163 int ret;
1727 164
1728 BUG_ON(reg > WM8994_MAX_REGISTER); 165 BUG_ON(reg > WM8994_MAX_REGISTER);
1729 166
1730 if (!wm8994_volatile(reg)) 167 if (!wm8994_volatile(reg)) {
1731 wm8994->reg_cache[reg] = value; 168 ret = snd_soc_cache_write(codec, reg, value);
1732 169 if (ret != 0)
1733 dev_dbg(codec->dev, "0x%x = 0x%x\n", reg, value); 170 dev_err(codec->dev, "Cache write to %x failed: %d\n",
171 reg, ret);
172 }
1734 173
1735 return wm8994_reg_write(codec->control_data, reg, value); 174 return wm8994_reg_write(codec->control_data, reg, value);
1736} 175}
@@ -1738,14 +177,22 @@ static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
1738static unsigned int wm8994_read(struct snd_soc_codec *codec, 177static unsigned int wm8994_read(struct snd_soc_codec *codec,
1739 unsigned int reg) 178 unsigned int reg)
1740{ 179{
1741 u16 *reg_cache = codec->reg_cache; 180 unsigned int val;
181 int ret;
1742 182
1743 BUG_ON(reg > WM8994_MAX_REGISTER); 183 BUG_ON(reg > WM8994_MAX_REGISTER);
1744 184
1745 if (wm8994_volatile(reg)) 185 if (!wm8994_volatile(reg) && wm8994_readable(reg) &&
1746 return wm8994_reg_read(codec->control_data, reg); 186 reg < codec->driver->reg_cache_size) {
1747 else 187 ret = snd_soc_cache_read(codec, reg, &val);
1748 return reg_cache[reg]; 188 if (ret >= 0)
189 return val;
190 else
191 dev_err(codec->dev, "Cache read from %x failed: %d\n",
192 reg, ret);
193 }
194
195 return wm8994_reg_read(codec->control_data, reg);
1749} 196}
1750 197
1751static int configure_aif_clock(struct snd_soc_codec *codec, int aif) 198static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
@@ -1837,7 +284,7 @@ static int configure_clock(struct snd_soc_codec *codec)
1837 284
1838 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new); 285 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
1839 286
1840 snd_soc_dapm_sync(codec); 287 snd_soc_dapm_sync(&codec->dapm);
1841 288
1842 return 0; 289 return 0;
1843} 290}
@@ -1864,6 +311,19 @@ static const char *sidetone_hpf_text[] = {
1864static const struct soc_enum sidetone_hpf = 311static const struct soc_enum sidetone_hpf =
1865 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text); 312 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
1866 313
314static const char *adc_hpf_text[] = {
315 "HiFi", "Voice 1", "Voice 2", "Voice 3"
316};
317
318static const struct soc_enum aif1adc1_hpf =
319 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
320
321static const struct soc_enum aif1adc2_hpf =
322 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
323
324static const struct soc_enum aif2adc_hpf =
325 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
326
1867static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); 327static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
1868static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 328static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1869static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 329static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
@@ -2071,21 +531,252 @@ static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
2071 return 0; 531 return 0;
2072} 532}
2073 533
2074static const char *aifdac_src_text[] = { 534static const char *aif_chan_src_text[] = {
2075 "Left", "Right" 535 "Left", "Right"
2076}; 536};
2077 537
538static const struct soc_enum aif1adcl_src =
539 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
540
541static const struct soc_enum aif1adcr_src =
542 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
543
544static const struct soc_enum aif2adcl_src =
545 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
546
547static const struct soc_enum aif2adcr_src =
548 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
549
2078static const struct soc_enum aif1dacl_src = 550static const struct soc_enum aif1dacl_src =
2079 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aifdac_src_text); 551 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
2080 552
2081static const struct soc_enum aif1dacr_src = 553static const struct soc_enum aif1dacr_src =
2082 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aifdac_src_text); 554 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
2083 555
2084static const struct soc_enum aif2dacl_src = 556static const struct soc_enum aif2dacl_src =
2085 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aifdac_src_text); 557 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
2086 558
2087static const struct soc_enum aif2dacr_src = 559static const struct soc_enum aif2dacr_src =
2088 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aifdac_src_text); 560 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
561
562static const char *osr_text[] = {
563 "Low Power", "High Performance",
564};
565
566static const struct soc_enum dac_osr =
567 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
568
569static const struct soc_enum adc_osr =
570 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
571
572static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start)
573{
574 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
575 struct wm8994_pdata *pdata = wm8994->pdata;
576 int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
577 int ena, reg, aif, i;
578
579 switch (mbc) {
580 case 0:
581 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
582 aif = 0;
583 break;
584 case 1:
585 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
586 aif = 0;
587 break;
588 case 2:
589 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
590 aif = 1;
591 break;
592 default:
593 BUG();
594 return;
595 }
596
597 /* We can only enable the MBC if the AIF is enabled and we
598 * want it to be enabled. */
599 ena = pwr_reg && wm8994->mbc_ena[mbc];
600
601 reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
602
603 dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n",
604 mbc, start, pwr_reg, reg);
605
606 if (start && ena) {
607 /* If the DSP is already running then noop */
608 if (reg & WM8958_DSP2_ENA)
609 return;
610
611 /* Switch the clock over to the appropriate AIF */
612 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
613 WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
614 aif << WM8958_DSP2CLK_SRC_SHIFT |
615 WM8958_DSP2CLK_ENA);
616
617 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
618 WM8958_DSP2_ENA, WM8958_DSP2_ENA);
619
620 /* If we've got user supplied MBC settings use them */
621 if (pdata && pdata->num_mbc_cfgs) {
622 struct wm8958_mbc_cfg *cfg
623 = &pdata->mbc_cfgs[wm8994->mbc_cfg];
624
625 for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
626 snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
627 cfg->coeff_regs[i]);
628
629 for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
630 snd_soc_write(codec,
631 i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
632 cfg->cutoff_regs[i]);
633 }
634
635 /* Run the DSP */
636 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
637 WM8958_DSP2_RUNR);
638
639 /* And we're off! */
640 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
641 WM8958_MBC_ENA | WM8958_MBC_SEL_MASK,
642 mbc << WM8958_MBC_SEL_SHIFT |
643 WM8958_MBC_ENA);
644 } else {
645 /* If the DSP is already stopped then noop */
646 if (!(reg & WM8958_DSP2_ENA))
647 return;
648
649 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
650 WM8958_MBC_ENA, 0);
651 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
652 WM8958_DSP2_ENA, 0);
653 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
654 WM8958_DSP2CLK_ENA, 0);
655 }
656}
657
658static int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
659 struct snd_kcontrol *kcontrol, int event)
660{
661 struct snd_soc_codec *codec = w->codec;
662 int mbc;
663
664 switch (w->shift) {
665 case 13:
666 case 12:
667 mbc = 2;
668 break;
669 case 11:
670 case 10:
671 mbc = 1;
672 break;
673 case 9:
674 case 8:
675 mbc = 0;
676 break;
677 default:
678 BUG();
679 return -EINVAL;
680 }
681
682 switch (event) {
683 case SND_SOC_DAPM_POST_PMU:
684 wm8958_mbc_apply(codec, mbc, 1);
685 break;
686 case SND_SOC_DAPM_POST_PMD:
687 wm8958_mbc_apply(codec, mbc, 0);
688 break;
689 }
690
691 return 0;
692}
693
694static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
695 struct snd_ctl_elem_value *ucontrol)
696{
697 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
698 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
699 struct wm8994_pdata *pdata = wm8994->pdata;
700 int value = ucontrol->value.integer.value[0];
701 int reg;
702
703 /* Don't allow on the fly reconfiguration */
704 reg = snd_soc_read(codec, WM8994_CLOCKING_1);
705 if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
706 return -EBUSY;
707
708 if (value >= pdata->num_mbc_cfgs)
709 return -EINVAL;
710
711 wm8994->mbc_cfg = value;
712
713 return 0;
714}
715
716static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
717 struct snd_ctl_elem_value *ucontrol)
718{
719 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
720 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
721
722 ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
723
724 return 0;
725}
726
727static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
728 struct snd_ctl_elem_info *uinfo)
729{
730 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
731 uinfo->count = 1;
732 uinfo->value.integer.min = 0;
733 uinfo->value.integer.max = 1;
734 return 0;
735}
736
737static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
738 struct snd_ctl_elem_value *ucontrol)
739{
740 int mbc = kcontrol->private_value;
741 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
742 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
743
744 ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
745
746 return 0;
747}
748
749static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
750 struct snd_ctl_elem_value *ucontrol)
751{
752 int mbc = kcontrol->private_value;
753 int i;
754 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
755 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
756
757 if (ucontrol->value.integer.value[0] > 1)
758 return -EINVAL;
759
760 for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
761 if (mbc != i && wm8994->mbc_ena[i]) {
762 dev_dbg(codec->dev, "MBC %d active already\n", mbc);
763 return -EBUSY;
764 }
765 }
766
767 wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
768
769 wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]);
770
771 return 0;
772}
773
774#define WM8958_MBC_SWITCH(xname, xval) {\
775 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
776 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
777 .info = wm8958_mbc_info, \
778 .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
779 .private_value = xval }
2089 780
2090static const struct snd_kcontrol_new wm8994_snd_controls[] = { 781static const struct snd_kcontrol_new wm8994_snd_controls[] = {
2091SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, 782SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
@@ -2098,10 +789,15 @@ SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
2098 WM8994_AIF2_ADC_RIGHT_VOLUME, 789 WM8994_AIF2_ADC_RIGHT_VOLUME,
2099 1, 119, 0, digital_tlv), 790 1, 119, 0, digital_tlv),
2100 791
792SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
793SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
794SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
795SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
796
2101SOC_ENUM("AIF1DACL Source", aif1dacl_src), 797SOC_ENUM("AIF1DACL Source", aif1dacl_src),
2102SOC_ENUM("AIF1DACR Source", aif1dacr_src), 798SOC_ENUM("AIF1DACR Source", aif1dacr_src),
2103SOC_ENUM("AIF2DACL Source", aif1dacl_src), 799SOC_ENUM("AIF2DACL Source", aif2dacl_src),
2104SOC_ENUM("AIF2DACR Source", aif1dacr_src), 800SOC_ENUM("AIF2DACR Source", aif2dacr_src),
2105 801
2106SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, 802SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
2107 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 803 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
@@ -2140,6 +836,18 @@ SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
2140SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), 836SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
2141SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), 837SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
2142 838
839SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
840SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
841
842SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
843SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
844
845SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
846SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
847
848SOC_ENUM("ADC OSR", adc_osr),
849SOC_ENUM("DAC OSR", dac_osr),
850
2143SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, 851SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
2144 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 852 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
2145SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, 853SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
@@ -2162,15 +870,15 @@ SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
2162 870
2163SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 871SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
2164 10, 15, 0, wm8994_3d_tlv), 872 10, 15, 0, wm8994_3d_tlv),
2165SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 873SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
2166 8, 1, 0), 874 8, 1, 0),
2167SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, 875SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
2168 10, 15, 0, wm8994_3d_tlv), 876 10, 15, 0, wm8994_3d_tlv),
2169SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 877SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
2170 8, 1, 0), 878 8, 1, 0),
2171SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, 879SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
2172 10, 15, 0, wm8994_3d_tlv), 880 10, 15, 0, wm8994_3d_tlv),
2173SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, 881SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
2174 8, 1, 0), 882 8, 1, 0),
2175}; 883};
2176 884
@@ -2209,6 +917,13 @@ SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
2209 eq_tlv), 917 eq_tlv),
2210}; 918};
2211 919
920static const struct snd_kcontrol_new wm8958_snd_controls[] = {
921SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
922WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
923WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
924WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
925};
926
2212static int clk_sys_event(struct snd_soc_dapm_widget *w, 927static int clk_sys_event(struct snd_soc_dapm_widget *w,
2213 struct snd_kcontrol *kcontrol, int event) 928 struct snd_kcontrol *kcontrol, int event)
2214{ 929{
@@ -2228,6 +943,7 @@ static int clk_sys_event(struct snd_soc_dapm_widget *w,
2228 943
2229static void wm8994_update_class_w(struct snd_soc_codec *codec) 944static void wm8994_update_class_w(struct snd_soc_codec *codec)
2230{ 945{
946 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2231 int enable = 1; 947 int enable = 1;
2232 int source = 0; /* GCC flow analysis can't track enable */ 948 int source = 0; /* GCC flow analysis can't track enable */
2233 int reg, reg_r; 949 int reg, reg_r;
@@ -2278,11 +994,13 @@ static void wm8994_update_class_w(struct snd_soc_codec *codec)
2278 WM8994_CP_DYN_PWR | 994 WM8994_CP_DYN_PWR |
2279 WM8994_CP_DYN_SRC_SEL_MASK, 995 WM8994_CP_DYN_SRC_SEL_MASK,
2280 source | WM8994_CP_DYN_PWR); 996 source | WM8994_CP_DYN_PWR);
997 wm8994->hubs.class_w = true;
2281 998
2282 } else { 999 } else {
2283 dev_dbg(codec->dev, "Class W disabled\n"); 1000 dev_dbg(codec->dev, "Class W disabled\n");
2284 snd_soc_update_bits(codec, WM8994_CLASS_W_1, 1001 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
2285 WM8994_CP_DYN_PWR, 0); 1002 WM8994_CP_DYN_PWR, 0);
1003 wm8994->hubs.class_w = false;
2286 } 1004 }
2287} 1005}
2288 1006
@@ -2512,14 +1230,47 @@ static const struct snd_kcontrol_new aif2adc_mux =
2512 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); 1230 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
2513 1231
2514static const char *aif3adc_text[] = { 1232static const char *aif3adc_text[] = {
2515 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", 1233 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
2516}; 1234};
2517 1235
2518static const struct soc_enum aif3adc_enum = 1236static const struct soc_enum wm8994_aif3adc_enum =
2519 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text); 1237 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
2520 1238
2521static const struct snd_kcontrol_new aif3adc_mux = 1239static const struct snd_kcontrol_new wm8994_aif3adc_mux =
2522 SOC_DAPM_ENUM("AIF3ADC Mux", aif3adc_enum); 1240 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1241
1242static const struct soc_enum wm8958_aif3adc_enum =
1243 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1244
1245static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1246 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1247
1248static const char *mono_pcm_out_text[] = {
1249 "None", "AIF2ADCL", "AIF2ADCR",
1250};
1251
1252static const struct soc_enum mono_pcm_out_enum =
1253 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1254
1255static const struct snd_kcontrol_new mono_pcm_out_mux =
1256 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1257
1258static const char *aif2dac_src_text[] = {
1259 "AIF2", "AIF3",
1260};
1261
1262/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1263static const struct soc_enum aif2dacl_src_enum =
1264 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1265
1266static const struct snd_kcontrol_new aif2dacl_src_mux =
1267 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1268
1269static const struct soc_enum aif2dacr_src_enum =
1270 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1271
1272static const struct snd_kcontrol_new aif2dacr_src_mux =
1273 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
2523 1274
2524static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { 1275static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
2525SND_SOC_DAPM_INPUT("DMIC1DAT"), 1276SND_SOC_DAPM_INPUT("DMIC1DAT"),
@@ -2540,19 +1291,23 @@ SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
2540 0, WM8994_POWER_MANAGEMENT_4, 9, 0), 1291 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
2541SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 1292SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
2542 0, WM8994_POWER_MANAGEMENT_4, 8, 0), 1293 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
2543SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, 1294SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
2544 WM8994_POWER_MANAGEMENT_5, 9, 0), 1295 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
2545SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, 1296 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2546 WM8994_POWER_MANAGEMENT_5, 8, 0), 1297SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1298 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1299 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2547 1300
2548SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", 1301SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
2549 0, WM8994_POWER_MANAGEMENT_4, 11, 0), 1302 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
2550SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", 1303SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
2551 0, WM8994_POWER_MANAGEMENT_4, 10, 0), 1304 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
2552SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, 1305SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
2553 WM8994_POWER_MANAGEMENT_5, 11, 0), 1306 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
2554SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, 1307 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2555 WM8994_POWER_MANAGEMENT_5, 10, 0), 1308SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1309 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1310 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2556 1311
2557SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 1312SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
2558 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 1313 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
@@ -2581,10 +1336,12 @@ SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
2581 WM8994_POWER_MANAGEMENT_4, 13, 0), 1336 WM8994_POWER_MANAGEMENT_4, 13, 0),
2582SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, 1337SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
2583 WM8994_POWER_MANAGEMENT_4, 12, 0), 1338 WM8994_POWER_MANAGEMENT_4, 12, 0),
2584SND_SOC_DAPM_AIF_IN("AIF2DACL", NULL, 0, 1339SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
2585 WM8994_POWER_MANAGEMENT_5, 13, 0), 1340 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
2586SND_SOC_DAPM_AIF_IN("AIF2DACR", NULL, 0, 1341 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2587 WM8994_POWER_MANAGEMENT_5, 12, 0), 1342SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1343 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1344 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2588 1345
2589SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), 1346SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2590SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), 1347SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
@@ -2593,7 +1350,6 @@ SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2593SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), 1350SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
2594SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), 1351SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
2595SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), 1352SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
2596SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &aif3adc_mux),
2597 1353
2598SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), 1354SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2599SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), 1355SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
@@ -2631,8 +1387,18 @@ SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
2631SND_SOC_DAPM_POST("Debug log", post_ev), 1387SND_SOC_DAPM_POST("Debug log", post_ev),
2632}; 1388};
2633 1389
2634static const struct snd_soc_dapm_route intercon[] = { 1390static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1391SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1392};
1393
1394static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1395SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1396SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1397SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1398SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1399};
2635 1400
1401static const struct snd_soc_dapm_route intercon[] = {
2636 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1402 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
2637 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1403 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
2638 1404
@@ -2740,9 +1506,6 @@ static const struct snd_soc_dapm_route intercon[] = {
2740 { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, 1506 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
2741 { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, 1507 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
2742 1508
2743 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2744 { "AIF2DACR", NULL, "AIF2DAC Mux" },
2745
2746 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" }, 1509 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
2747 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, 1510 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
2748 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" }, 1511 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
@@ -2815,6 +1578,26 @@ static const struct snd_soc_dapm_route intercon[] = {
2815 { "Right Headphone Mux", "DAC", "DAC1R" }, 1578 { "Right Headphone Mux", "DAC", "DAC1R" },
2816}; 1579};
2817 1580
1581static const struct snd_soc_dapm_route wm8994_intercon[] = {
1582 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1583 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1584};
1585
1586static const struct snd_soc_dapm_route wm8958_intercon[] = {
1587 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1588 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1589
1590 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1591 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1592 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1593 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1594
1595 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1596 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1597
1598 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1599};
1600
2818/* The size in bits of the FLL divide multiplied by 10 1601/* The size in bits of the FLL divide multiplied by 10
2819 * to allow rounding later */ 1602 * to allow rounding later */
2820#define FIXED_FLL_SIZE ((1 << 16) * 10) 1603#define FIXED_FLL_SIZE ((1 << 16) * 10)
@@ -2930,6 +1713,7 @@ static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2930 /* Allow no source specification when stopping */ 1713 /* Allow no source specification when stopping */
2931 if (freq_out) 1714 if (freq_out)
2932 return -EINVAL; 1715 return -EINVAL;
1716 src = wm8994->fll[id].src;
2933 break; 1717 break;
2934 case WM8994_FLL_SRC_MCLK1: 1718 case WM8994_FLL_SRC_MCLK1:
2935 case WM8994_FLL_SRC_MCLK2: 1719 case WM8994_FLL_SRC_MCLK2:
@@ -3094,6 +1878,7 @@ static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
3094static int wm8994_set_bias_level(struct snd_soc_codec *codec, 1878static int wm8994_set_bias_level(struct snd_soc_codec *codec,
3095 enum snd_soc_bias_level level) 1879 enum snd_soc_bias_level level)
3096{ 1880{
1881 struct wm8994 *control = codec->control_data;
3097 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 1882 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3098 1883
3099 switch (level) { 1884 switch (level) {
@@ -3107,16 +1892,36 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec,
3107 break; 1892 break;
3108 1893
3109 case SND_SOC_BIAS_STANDBY: 1894 case SND_SOC_BIAS_STANDBY:
3110 if (codec->bias_level == SND_SOC_BIAS_OFF) { 1895 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
3111 /* Tweak DC servo and DSP configuration for 1896 pm_runtime_get_sync(codec->dev);
3112 * improved performance. */ 1897
3113 if (wm8994->revision < 4) { 1898 switch (control->type) {
3114 /* Tweak DC servo and DSP configuration for 1899 case WM8994:
3115 * improved performance. */ 1900 if (wm8994->revision < 4) {
3116 snd_soc_write(codec, 0x102, 0x3); 1901 /* Tweak DC servo and DSP
3117 snd_soc_write(codec, 0x56, 0x3); 1902 * configuration for improved
3118 snd_soc_write(codec, 0x817, 0); 1903 * performance. */
3119 snd_soc_write(codec, 0x102, 0); 1904 snd_soc_write(codec, 0x102, 0x3);
1905 snd_soc_write(codec, 0x56, 0x3);
1906 snd_soc_write(codec, 0x817, 0);
1907 snd_soc_write(codec, 0x102, 0);
1908 }
1909 break;
1910
1911 case WM8958:
1912 if (wm8994->revision == 0) {
1913 /* Optimise performance for rev A */
1914 snd_soc_write(codec, 0x102, 0x3);
1915 snd_soc_write(codec, 0xcb, 0x81);
1916 snd_soc_write(codec, 0x817, 0);
1917 snd_soc_write(codec, 0x102, 0);
1918
1919 snd_soc_update_bits(codec,
1920 WM8958_CHARGE_PUMP_2,
1921 WM8958_CP_DISCH,
1922 WM8958_CP_DISCH);
1923 }
1924 break;
3120 } 1925 }
3121 1926
3122 /* Discharge LINEOUT1 & 2 */ 1927 /* Discharge LINEOUT1 & 2 */
@@ -3151,7 +1956,7 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec,
3151 break; 1956 break;
3152 1957
3153 case SND_SOC_BIAS_OFF: 1958 case SND_SOC_BIAS_OFF:
3154 if (codec->bias_level == SND_SOC_BIAS_STANDBY) { 1959 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
3155 /* Switch over to startup biases */ 1960 /* Switch over to startup biases */
3156 snd_soc_update_bits(codec, WM8994_ANTIPOP_2, 1961 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
3157 WM8994_BIAS_SRC | 1962 WM8994_BIAS_SRC |
@@ -3183,16 +1988,19 @@ static int wm8994_set_bias_level(struct snd_soc_codec *codec,
3183 WM8994_STARTUP_BIAS_ENA | 1988 WM8994_STARTUP_BIAS_ENA |
3184 WM8994_VMID_BUF_ENA | 1989 WM8994_VMID_BUF_ENA |
3185 WM8994_VMID_RAMP_MASK, 0); 1990 WM8994_VMID_RAMP_MASK, 0);
1991
1992 pm_runtime_put(codec->dev);
3186 } 1993 }
3187 break; 1994 break;
3188 } 1995 }
3189 codec->bias_level = level; 1996 codec->dapm.bias_level = level;
3190 return 0; 1997 return 0;
3191} 1998}
3192 1999
3193static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2000static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3194{ 2001{
3195 struct snd_soc_codec *codec = dai->codec; 2002 struct snd_soc_codec *codec = dai->codec;
2003 struct wm8994 *control = codec->control_data;
3196 int ms_reg; 2004 int ms_reg;
3197 int aif1_reg; 2005 int aif1_reg;
3198 int ms = 0; 2006 int ms = 0;
@@ -3277,6 +2085,13 @@ static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3277 return -EINVAL; 2085 return -EINVAL;
3278 } 2086 }
3279 2087
2088 /* The AIF2 format configuration needs to be mirrored to AIF3
2089 * on WM8958 if it's in use so just do it all the time. */
2090 if (control->type == WM8958 && dai->id == 2)
2091 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2092 WM8994_AIF1_LRCLK_INV |
2093 WM8958_AIF3_FMT_MASK, aif1);
2094
3280 snd_soc_update_bits(codec, aif1_reg, 2095 snd_soc_update_bits(codec, aif1_reg,
3281 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | 2096 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
3282 WM8994_AIF1_FMT_MASK, 2097 WM8994_AIF1_FMT_MASK,
@@ -3317,12 +2132,15 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3317 struct snd_soc_dai *dai) 2132 struct snd_soc_dai *dai)
3318{ 2133{
3319 struct snd_soc_codec *codec = dai->codec; 2134 struct snd_soc_codec *codec = dai->codec;
2135 struct wm8994 *control = codec->control_data;
3320 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2136 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3321 int aif1_reg; 2137 int aif1_reg;
2138 int aif2_reg;
3322 int bclk_reg; 2139 int bclk_reg;
3323 int lrclk_reg; 2140 int lrclk_reg;
3324 int rate_reg; 2141 int rate_reg;
3325 int aif1 = 0; 2142 int aif1 = 0;
2143 int aif2 = 0;
3326 int bclk = 0; 2144 int bclk = 0;
3327 int lrclk = 0; 2145 int lrclk = 0;
3328 int rate_val = 0; 2146 int rate_val = 0;
@@ -3333,6 +2151,7 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3333 switch (dai->id) { 2151 switch (dai->id) {
3334 case 1: 2152 case 1:
3335 aif1_reg = WM8994_AIF1_CONTROL_1; 2153 aif1_reg = WM8994_AIF1_CONTROL_1;
2154 aif2_reg = WM8994_AIF1_CONTROL_2;
3336 bclk_reg = WM8994_AIF1_BCLK; 2155 bclk_reg = WM8994_AIF1_BCLK;
3337 rate_reg = WM8994_AIF1_RATE; 2156 rate_reg = WM8994_AIF1_RATE;
3338 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2157 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
@@ -3345,6 +2164,7 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3345 break; 2164 break;
3346 case 2: 2165 case 2:
3347 aif1_reg = WM8994_AIF2_CONTROL_1; 2166 aif1_reg = WM8994_AIF2_CONTROL_1;
2167 aif2_reg = WM8994_AIF2_CONTROL_2;
3348 bclk_reg = WM8994_AIF2_BCLK; 2168 bclk_reg = WM8994_AIF2_BCLK;
3349 rate_reg = WM8994_AIF2_RATE; 2169 rate_reg = WM8994_AIF2_RATE;
3350 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 2170 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
@@ -3355,6 +2175,14 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3355 dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); 2175 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
3356 } 2176 }
3357 break; 2177 break;
2178 case 3:
2179 switch (control->type) {
2180 case WM8958:
2181 aif1_reg = WM8958_AIF3_CONTROL_1;
2182 break;
2183 default:
2184 return 0;
2185 }
3358 default: 2186 default:
3359 return -EINVAL; 2187 return -EINVAL;
3360 } 2188 }
@@ -3392,6 +2220,10 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3392 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 2220 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
3393 dai->id, wm8994->aifclk[id], bclk_rate); 2221 dai->id, wm8994->aifclk[id], bclk_rate);
3394 2222
2223 if (params_channels(params) == 1 &&
2224 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2225 aif2 |= WM8994_AIF1_MONO;
2226
3395 if (wm8994->aifclk[id] == 0) { 2227 if (wm8994->aifclk[id] == 0) {
3396 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); 2228 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
3397 return -EINVAL; 2229 return -EINVAL;
@@ -3435,6 +2267,7 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3435 lrclk, bclk_rate / lrclk); 2267 lrclk, bclk_rate / lrclk);
3436 2268
3437 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); 2269 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2270 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
3438 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); 2271 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
3439 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, 2272 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
3440 lrclk); 2273 lrclk);
@@ -3458,6 +2291,47 @@ static int wm8994_hw_params(struct snd_pcm_substream *substream,
3458 return 0; 2291 return 0;
3459} 2292}
3460 2293
2294static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2295 struct snd_pcm_hw_params *params,
2296 struct snd_soc_dai *dai)
2297{
2298 struct snd_soc_codec *codec = dai->codec;
2299 struct wm8994 *control = codec->control_data;
2300 int aif1_reg;
2301 int aif1 = 0;
2302
2303 switch (dai->id) {
2304 case 3:
2305 switch (control->type) {
2306 case WM8958:
2307 aif1_reg = WM8958_AIF3_CONTROL_1;
2308 break;
2309 default:
2310 return 0;
2311 }
2312 default:
2313 return 0;
2314 }
2315
2316 switch (params_format(params)) {
2317 case SNDRV_PCM_FORMAT_S16_LE:
2318 break;
2319 case SNDRV_PCM_FORMAT_S20_3LE:
2320 aif1 |= 0x20;
2321 break;
2322 case SNDRV_PCM_FORMAT_S24_LE:
2323 aif1 |= 0x40;
2324 break;
2325 case SNDRV_PCM_FORMAT_S32_LE:
2326 aif1 |= 0x60;
2327 break;
2328 default:
2329 return -EINVAL;
2330 }
2331
2332 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2333}
2334
3461static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) 2335static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
3462{ 2336{
3463 struct snd_soc_codec *codec = codec_dai->codec; 2337 struct snd_soc_codec *codec = codec_dai->codec;
@@ -3539,6 +2413,7 @@ static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3539}; 2413};
3540 2414
3541static struct snd_soc_dai_ops wm8994_aif3_dai_ops = { 2415static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2416 .hw_params = wm8994_aif3_hw_params,
3542 .set_tristate = wm8994_set_tristate, 2417 .set_tristate = wm8994_set_tristate,
3543}; 2418};
3544 2419
@@ -3548,14 +2423,14 @@ static struct snd_soc_dai_driver wm8994_dai[] = {
3548 .id = 1, 2423 .id = 1,
3549 .playback = { 2424 .playback = {
3550 .stream_name = "AIF1 Playback", 2425 .stream_name = "AIF1 Playback",
3551 .channels_min = 2, 2426 .channels_min = 1,
3552 .channels_max = 2, 2427 .channels_max = 2,
3553 .rates = WM8994_RATES, 2428 .rates = WM8994_RATES,
3554 .formats = WM8994_FORMATS, 2429 .formats = WM8994_FORMATS,
3555 }, 2430 },
3556 .capture = { 2431 .capture = {
3557 .stream_name = "AIF1 Capture", 2432 .stream_name = "AIF1 Capture",
3558 .channels_min = 2, 2433 .channels_min = 1,
3559 .channels_max = 2, 2434 .channels_max = 2,
3560 .rates = WM8994_RATES, 2435 .rates = WM8994_RATES,
3561 .formats = WM8994_FORMATS, 2436 .formats = WM8994_FORMATS,
@@ -3567,14 +2442,14 @@ static struct snd_soc_dai_driver wm8994_dai[] = {
3567 .id = 2, 2442 .id = 2,
3568 .playback = { 2443 .playback = {
3569 .stream_name = "AIF2 Playback", 2444 .stream_name = "AIF2 Playback",
3570 .channels_min = 2, 2445 .channels_min = 1,
3571 .channels_max = 2, 2446 .channels_max = 2,
3572 .rates = WM8994_RATES, 2447 .rates = WM8994_RATES,
3573 .formats = WM8994_FORMATS, 2448 .formats = WM8994_FORMATS,
3574 }, 2449 },
3575 .capture = { 2450 .capture = {
3576 .stream_name = "AIF2 Capture", 2451 .stream_name = "AIF2 Capture",
3577 .channels_min = 2, 2452 .channels_min = 1,
3578 .channels_max = 2, 2453 .channels_max = 2,
3579 .rates = WM8994_RATES, 2454 .rates = WM8994_RATES,
3580 .formats = WM8994_FORMATS, 2455 .formats = WM8994_FORMATS,
@@ -3586,14 +2461,14 @@ static struct snd_soc_dai_driver wm8994_dai[] = {
3586 .id = 3, 2461 .id = 3,
3587 .playback = { 2462 .playback = {
3588 .stream_name = "AIF3 Playback", 2463 .stream_name = "AIF3 Playback",
3589 .channels_min = 2, 2464 .channels_min = 1,
3590 .channels_max = 2, 2465 .channels_max = 2,
3591 .rates = WM8994_RATES, 2466 .rates = WM8994_RATES,
3592 .formats = WM8994_FORMATS, 2467 .formats = WM8994_FORMATS,
3593 }, 2468 },
3594 .capture = { 2469 .capture = {
3595 .stream_name = "AIF3 Capture", 2470 .stream_name = "AIF3 Capture",
3596 .channels_min = 2, 2471 .channels_min = 1,
3597 .channels_max = 2, 2472 .channels_max = 2,
3598 .rates = WM8994_RATES, 2473 .rates = WM8994_RATES,
3599 .formats = WM8994_FORMATS, 2474 .formats = WM8994_FORMATS,
@@ -3625,26 +2500,12 @@ static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
3625static int wm8994_resume(struct snd_soc_codec *codec) 2500static int wm8994_resume(struct snd_soc_codec *codec)
3626{ 2501{
3627 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2502 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3628 u16 *reg_cache = codec->reg_cache;
3629 int i, ret; 2503 int i, ret;
3630 2504
3631 /* Restore the registers */ 2505 /* Restore the registers */
3632 for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) { 2506 ret = snd_soc_cache_sync(codec);
3633 switch (i) { 2507 if (ret != 0)
3634 case WM8994_LDO_1: 2508 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
3635 case WM8994_LDO_2:
3636 case WM8994_SOFTWARE_RESET:
3637 /* Handled by other MFD drivers */
3638 continue;
3639 default:
3640 break;
3641 }
3642
3643 if (!access_masks[i].writable)
3644 continue;
3645
3646 wm8994_reg_write(codec->control_data, i, reg_cache[i]);
3647 }
3648 2509
3649 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2510 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3650 2511
@@ -3794,6 +2655,34 @@ static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3794 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", 2655 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3795 pdata->num_retune_mobile_cfgs); 2656 pdata->num_retune_mobile_cfgs);
3796 2657
2658 if (pdata->num_mbc_cfgs) {
2659 struct snd_kcontrol_new control[] = {
2660 SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
2661 wm8958_get_mbc_enum, wm8958_put_mbc_enum),
2662 };
2663
2664 /* We need an array of texts for the enum API */
2665 wm8994->mbc_texts = kmalloc(sizeof(char *)
2666 * pdata->num_mbc_cfgs, GFP_KERNEL);
2667 if (!wm8994->mbc_texts) {
2668 dev_err(wm8994->codec->dev,
2669 "Failed to allocate %d MBC config texts\n",
2670 pdata->num_mbc_cfgs);
2671 return;
2672 }
2673
2674 for (i = 0; i < pdata->num_mbc_cfgs; i++)
2675 wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
2676
2677 wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
2678 wm8994->mbc_enum.texts = wm8994->mbc_texts;
2679
2680 ret = snd_soc_add_controls(wm8994->codec, control, 1);
2681 if (ret != 0)
2682 dev_err(wm8994->codec->dev,
2683 "Failed to add MBC mode controls: %d\n", ret);
2684 }
2685
3797 if (pdata->num_retune_mobile_cfgs) 2686 if (pdata->num_retune_mobile_cfgs)
3798 wm8994_handle_retune_mobile_pdata(wm8994); 2687 wm8994_handle_retune_mobile_pdata(wm8994);
3799 else 2688 else
@@ -3823,8 +2712,12 @@ int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3823{ 2712{
3824 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 2713 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3825 struct wm8994_micdet *micdet; 2714 struct wm8994_micdet *micdet;
2715 struct wm8994 *control = codec->control_data;
3826 int reg; 2716 int reg;
3827 2717
2718 if (control->type != WM8994)
2719 return -EINVAL;
2720
3828 switch (micbias) { 2721 switch (micbias) {
3829 case 1: 2722 case 1:
3830 micdet = &wm8994->micdet[0]; 2723 micdet = &wm8994->micdet[0];
@@ -3863,6 +2756,10 @@ static irqreturn_t wm8994_mic_irq(int irq, void *data)
3863 int reg; 2756 int reg;
3864 int report; 2757 int report;
3865 2758
2759#ifndef CONFIG_SND_SOC_WM8994_MODULE
2760 trace_snd_soc_jack_irq(dev_name(codec->dev));
2761#endif
2762
3866 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2); 2763 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3867 if (reg < 0) { 2764 if (reg < 0) {
3868 dev_err(codec->dev, "Failed to read microphone status: %d\n", 2765 dev_err(codec->dev, "Failed to read microphone status: %d\n",
@@ -3891,77 +2788,251 @@ static irqreturn_t wm8994_mic_irq(int irq, void *data)
3891 return IRQ_HANDLED; 2788 return IRQ_HANDLED;
3892} 2789}
3893 2790
2791/* Default microphone detection handler for WM8958 - the user can
2792 * override this if they wish.
2793 */
2794static void wm8958_default_micdet(u16 status, void *data)
2795{
2796 struct snd_soc_codec *codec = data;
2797 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2798 int report = 0;
2799
2800 /* If nothing present then clear our statuses */
2801 if (!(status & WM8958_MICD_STS)) {
2802 wm8994->jack_is_video = false;
2803 wm8994->jack_is_mic = false;
2804 goto done;
2805 }
2806
2807 /* Assume anything over 475 ohms is a microphone and remember
2808 * that we've seen one (since buttons override it) */
2809 if (status & 0x600)
2810 wm8994->jack_is_mic = true;
2811 if (wm8994->jack_is_mic)
2812 report |= SND_JACK_MICROPHONE;
2813
2814 /* Video has an impedence of approximately 75 ohms; assume
2815 * this isn't used as a button and remember it since buttons
2816 * override it. */
2817 if (status & 0x40)
2818 wm8994->jack_is_video = true;
2819 if (wm8994->jack_is_video)
2820 report |= SND_JACK_VIDEOOUT;
2821
2822 /* Everything else is buttons; just assign slots */
2823 if (status & 0x4)
2824 report |= SND_JACK_BTN_0;
2825 if (status & 0x8)
2826 report |= SND_JACK_BTN_1;
2827 if (status & 0x10)
2828 report |= SND_JACK_BTN_2;
2829 if (status & 0x20)
2830 report |= SND_JACK_BTN_3;
2831 if (status & 0x80)
2832 report |= SND_JACK_BTN_4;
2833 if (status & 0x100)
2834 report |= SND_JACK_BTN_5;
2835
2836done:
2837 snd_soc_jack_report(wm8994->micdet[0].jack,
2838 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 |
2839 SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5 |
2840 SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT,
2841 report);
2842}
2843
2844/**
2845 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2846 *
2847 * @codec: WM8958 codec
2848 * @jack: jack to report detection events on
2849 *
2850 * Enable microphone detection functionality for the WM8958. By
2851 * default simple detection which supports the detection of up to 6
2852 * buttons plus video and microphone functionality is supported.
2853 *
2854 * The WM8958 has an advanced jack detection facility which is able to
2855 * support complex accessory detection, especially when used in
2856 * conjunction with external circuitry. In order to provide maximum
2857 * flexiblity a callback is provided which allows a completely custom
2858 * detection algorithm.
2859 */
2860int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2861 wm8958_micdet_cb cb, void *cb_data)
2862{
2863 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2864 struct wm8994 *control = codec->control_data;
2865
2866 if (control->type != WM8958)
2867 return -EINVAL;
2868
2869 if (jack) {
2870 if (!cb) {
2871 dev_dbg(codec->dev, "Using default micdet callback\n");
2872 cb = wm8958_default_micdet;
2873 cb_data = codec;
2874 }
2875
2876 wm8994->micdet[0].jack = jack;
2877 wm8994->jack_cb = cb;
2878 wm8994->jack_cb_data = cb_data;
2879
2880 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2881 WM8958_MICD_ENA, WM8958_MICD_ENA);
2882 } else {
2883 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2884 WM8958_MICD_ENA, 0);
2885 }
2886
2887 return 0;
2888}
2889EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2890
2891static irqreturn_t wm8958_mic_irq(int irq, void *data)
2892{
2893 struct wm8994_priv *wm8994 = data;
2894 struct snd_soc_codec *codec = wm8994->codec;
2895 int reg;
2896
2897 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2898 if (reg < 0) {
2899 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2900 reg);
2901 return IRQ_NONE;
2902 }
2903
2904 if (!(reg & WM8958_MICD_VALID)) {
2905 dev_dbg(codec->dev, "Mic detect data not valid\n");
2906 goto out;
2907 }
2908
2909#ifndef CONFIG_SND_SOC_WM8994_MODULE
2910 trace_snd_soc_jack_irq(dev_name(codec->dev));
2911#endif
2912
2913 if (wm8994->jack_cb)
2914 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2915 else
2916 dev_warn(codec->dev, "Accessory detection with no callback\n");
2917
2918out:
2919 return IRQ_HANDLED;
2920}
2921
3894static int wm8994_codec_probe(struct snd_soc_codec *codec) 2922static int wm8994_codec_probe(struct snd_soc_codec *codec)
3895{ 2923{
2924 struct wm8994 *control;
3896 struct wm8994_priv *wm8994; 2925 struct wm8994_priv *wm8994;
2926 struct snd_soc_dapm_context *dapm = &codec->dapm;
3897 int ret, i; 2927 int ret, i;
3898 2928
3899 codec->control_data = dev_get_drvdata(codec->dev->parent); 2929 codec->control_data = dev_get_drvdata(codec->dev->parent);
2930 control = codec->control_data;
3900 2931
3901 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL); 2932 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3902 if (wm8994 == NULL) 2933 if (wm8994 == NULL)
3903 return -ENOMEM; 2934 return -ENOMEM;
3904 snd_soc_codec_set_drvdata(codec, wm8994); 2935 snd_soc_codec_set_drvdata(codec, wm8994);
3905 2936
3906 codec->reg_cache = &wm8994->reg_cache;
3907
3908 wm8994->pdata = dev_get_platdata(codec->dev->parent); 2937 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3909 wm8994->codec = codec; 2938 wm8994->codec = codec;
3910 2939
3911 /* Fill the cache with physical values we inherited; don't reset */ 2940 pm_runtime_enable(codec->dev);
3912 ret = wm8994_bulk_read(codec->control_data, 0, 2941 pm_runtime_resume(codec->dev);
3913 ARRAY_SIZE(wm8994->reg_cache) - 1,
3914 codec->reg_cache);
3915 if (ret < 0) {
3916 dev_err(codec->dev, "Failed to fill register cache: %d\n",
3917 ret);
3918 goto err;
3919 }
3920 2942
3921 /* Clear the cached values for unreadable/volatile registers to 2943 /* Read our current status back from the chip - we don't want to
3922 * avoid potential confusion. 2944 * reset as this may interfere with the GPIO or LDO operation. */
3923 */ 2945 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
3924 for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++) 2946 if (!wm8994_readable(i) || wm8994_volatile(i))
3925 if (wm8994_volatile(i) || !wm8994_readable(i)) 2947 continue;
3926 wm8994->reg_cache[i] = 0; 2948
2949 ret = wm8994_reg_read(codec->control_data, i);
2950 if (ret <= 0)
2951 continue;
2952
2953 ret = snd_soc_cache_write(codec, i, ret);
2954 if (ret != 0) {
2955 dev_err(codec->dev,
2956 "Failed to initialise cache for 0x%x: %d\n",
2957 i, ret);
2958 goto err;
2959 }
2960 }
3927 2961
3928 /* Set revision-specific configuration */ 2962 /* Set revision-specific configuration */
3929 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION); 2963 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3930 switch (wm8994->revision) { 2964 switch (control->type) {
3931 case 2: 2965 case WM8994:
3932 case 3: 2966 switch (wm8994->revision) {
3933 wm8994->hubs.dcs_codes = -5; 2967 case 2:
3934 wm8994->hubs.hp_startup_mode = 1; 2968 case 3:
2969 wm8994->hubs.dcs_codes = -5;
2970 wm8994->hubs.hp_startup_mode = 1;
2971 wm8994->hubs.dcs_readback_mode = 1;
2972 break;
2973 default:
2974 wm8994->hubs.dcs_readback_mode = 1;
2975 break;
2976 }
2977
2978 case WM8958:
3935 wm8994->hubs.dcs_readback_mode = 1; 2979 wm8994->hubs.dcs_readback_mode = 1;
3936 break; 2980 break;
2981
3937 default: 2982 default:
3938 wm8994->hubs.dcs_readback_mode = 1;
3939 break; 2983 break;
3940 } 2984 }
3941 2985
3942 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_DET, 2986 switch (control->type) {
3943 wm8994_mic_irq, "Mic 1 detect", wm8994); 2987 case WM8994:
3944 if (ret != 0) 2988 ret = wm8994_request_irq(codec->control_data,
3945 dev_warn(codec->dev, 2989 WM8994_IRQ_MIC1_DET,
3946 "Failed to request Mic1 detect IRQ: %d\n", ret); 2990 wm8994_mic_irq, "Mic 1 detect",
3947 2991 wm8994);
3948 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, 2992 if (ret != 0)
3949 wm8994_mic_irq, "Mic 1 short", wm8994); 2993 dev_warn(codec->dev,
3950 if (ret != 0) 2994 "Failed to request Mic1 detect IRQ: %d\n",
3951 dev_warn(codec->dev, 2995 ret);
3952 "Failed to request Mic1 short IRQ: %d\n", ret); 2996
3953 2997 ret = wm8994_request_irq(codec->control_data,
3954 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_DET, 2998 WM8994_IRQ_MIC1_SHRT,
3955 wm8994_mic_irq, "Mic 2 detect", wm8994); 2999 wm8994_mic_irq, "Mic 1 short",
3956 if (ret != 0) 3000 wm8994);
3957 dev_warn(codec->dev, 3001 if (ret != 0)
3958 "Failed to request Mic2 detect IRQ: %d\n", ret); 3002 dev_warn(codec->dev,
3003 "Failed to request Mic1 short IRQ: %d\n",
3004 ret);
3005
3006 ret = wm8994_request_irq(codec->control_data,
3007 WM8994_IRQ_MIC2_DET,
3008 wm8994_mic_irq, "Mic 2 detect",
3009 wm8994);
3010 if (ret != 0)
3011 dev_warn(codec->dev,
3012 "Failed to request Mic2 detect IRQ: %d\n",
3013 ret);
3014
3015 ret = wm8994_request_irq(codec->control_data,
3016 WM8994_IRQ_MIC2_SHRT,
3017 wm8994_mic_irq, "Mic 2 short",
3018 wm8994);
3019 if (ret != 0)
3020 dev_warn(codec->dev,
3021 "Failed to request Mic2 short IRQ: %d\n",
3022 ret);
3023 break;
3959 3024
3960 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, 3025 case WM8958:
3961 wm8994_mic_irq, "Mic 2 short", wm8994); 3026 ret = wm8994_request_irq(codec->control_data,
3962 if (ret != 0) 3027 WM8994_IRQ_MIC1_DET,
3963 dev_warn(codec->dev, 3028 wm8958_mic_irq, "Mic detect",
3964 "Failed to request Mic2 short IRQ: %d\n", ret); 3029 wm8994);
3030 if (ret != 0)
3031 dev_warn(codec->dev,
3032 "Failed to request Mic detect IRQ: %d\n",
3033 ret);
3034 break;
3035 }
3965 3036
3966 /* Remember if AIFnLRCLK is configured as a GPIO. This should be 3037 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3967 * configured on init - if a system wants to do this dynamically 3038 * configured on init - if a system wants to do this dynamically
@@ -4034,10 +3105,36 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec)
4034 wm_hubs_add_analogue_controls(codec); 3105 wm_hubs_add_analogue_controls(codec);
4035 snd_soc_add_controls(codec, wm8994_snd_controls, 3106 snd_soc_add_controls(codec, wm8994_snd_controls,
4036 ARRAY_SIZE(wm8994_snd_controls)); 3107 ARRAY_SIZE(wm8994_snd_controls));
4037 snd_soc_dapm_new_controls(codec, wm8994_dapm_widgets, 3108 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4038 ARRAY_SIZE(wm8994_dapm_widgets)); 3109 ARRAY_SIZE(wm8994_dapm_widgets));
3110
3111 switch (control->type) {
3112 case WM8994:
3113 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3114 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3115 break;
3116 case WM8958:
3117 snd_soc_add_controls(codec, wm8958_snd_controls,
3118 ARRAY_SIZE(wm8958_snd_controls));
3119 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3120 ARRAY_SIZE(wm8958_dapm_widgets));
3121 break;
3122 }
3123
3124
4039 wm_hubs_add_analogue_routes(codec, 0, 0); 3125 wm_hubs_add_analogue_routes(codec, 0, 0);
4040 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 3126 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3127
3128 switch (control->type) {
3129 case WM8994:
3130 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3131 ARRAY_SIZE(wm8994_intercon));
3132 break;
3133 case WM8958:
3134 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3135 ARRAY_SIZE(wm8958_intercon));
3136 break;
3137 }
4041 3138
4042 return 0; 3139 return 0;
4043 3140
@@ -4054,13 +3151,29 @@ err:
4054static int wm8994_codec_remove(struct snd_soc_codec *codec) 3151static int wm8994_codec_remove(struct snd_soc_codec *codec)
4055{ 3152{
4056 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); 3153 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3154 struct wm8994 *control = codec->control_data;
4057 3155
4058 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); 3156 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4059 3157
4060 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994); 3158 pm_runtime_disable(codec->dev);
4061 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994); 3159
4062 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994); 3160 switch (control->type) {
4063 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994); 3161 case WM8994:
3162 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
3163 wm8994);
3164 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3165 wm8994);
3166 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3167 wm8994);
3168 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3169 wm8994);
3170 break;
3171
3172 case WM8958:
3173 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3174 wm8994);
3175 break;
3176 }
4064 kfree(wm8994->retune_mobile_texts); 3177 kfree(wm8994->retune_mobile_texts);
4065 kfree(wm8994->drc_texts); 3178 kfree(wm8994->drc_texts);
4066 kfree(wm8994); 3179 kfree(wm8994);
@@ -4073,11 +3186,16 @@ static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4073 .remove = wm8994_codec_remove, 3186 .remove = wm8994_codec_remove,
4074 .suspend = wm8994_suspend, 3187 .suspend = wm8994_suspend,
4075 .resume = wm8994_resume, 3188 .resume = wm8994_resume,
4076 .read = wm8994_read, 3189 .read = wm8994_read,
4077 .write = wm8994_write, 3190 .write = wm8994_write,
4078 .readable_register = wm8994_readable, 3191 .readable_register = wm8994_readable,
4079 .volatile_register = wm8994_volatile, 3192 .volatile_register = wm8994_volatile,
4080 .set_bias_level = wm8994_set_bias_level, 3193 .set_bias_level = wm8994_set_bias_level,
3194
3195 .reg_cache_size = WM8994_CACHE_SIZE,
3196 .reg_cache_default = wm8994_reg_defaults,
3197 .reg_word_size = 2,
3198 .compress_type = SND_SOC_RBTREE_COMPRESSION,
4081}; 3199};
4082 3200
4083static int __devinit wm8994_probe(struct platform_device *pdev) 3201static int __devinit wm8994_probe(struct platform_device *pdev)
diff --git a/sound/soc/codecs/wm8994.h b/sound/soc/codecs/wm8994.h
index d8dce260c430..0c355bfc88f1 100644
--- a/sound/soc/codecs/wm8994.h
+++ b/sound/soc/codecs/wm8994.h
@@ -28,7 +28,21 @@
28#define WM8994_FLL_SRC_LRCLK 3 28#define WM8994_FLL_SRC_LRCLK 3
29#define WM8994_FLL_SRC_BCLK 4 29#define WM8994_FLL_SRC_BCLK 4
30 30
31typedef void (*wm8958_micdet_cb)(u16 status, void *data);
32
31int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 33int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
32 int micbias, int det, int shrt); 34 int micbias, int det, int shrt);
35int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
36 wm8958_micdet_cb cb, void *cb_data);
37
38#define WM8994_CACHE_SIZE 1570
39
40struct wm8994_access_mask {
41 unsigned short readable; /* Mask of readable bits */
42 unsigned short writable; /* Mask of writable bits */
43};
44
45extern const struct wm8994_access_mask wm8994_access_masks[WM8994_CACHE_SIZE];
46extern const __devinitdata u16 wm8994_reg_defaults[WM8994_CACHE_SIZE];
33 47
34#endif 48#endif
diff --git a/sound/soc/codecs/wm8995.c b/sound/soc/codecs/wm8995.c
new file mode 100644
index 000000000000..6045cbde492b
--- /dev/null
+++ b/sound/soc/codecs/wm8995.c
@@ -0,0 +1,1818 @@
1/*
2 * wm8995.c -- WM8995 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * Based on wm8994.c and wm_hubs.c by Mark Brown
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/spi/spi.h>
22#include <linux/slab.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30
31#include "wm8995.h"
32
33static const u16 wm8995_reg_defs[WM8995_MAX_REGISTER + 1] = {
34 [0] = 0x8995, [5] = 0x0100, [16] = 0x000b, [17] = 0x000b,
35 [24] = 0x02c0, [25] = 0x02c0, [26] = 0x02c0, [27] = 0x02c0,
36 [28] = 0x000f, [32] = 0x0005, [33] = 0x0005, [40] = 0x0003,
37 [41] = 0x0013, [48] = 0x0004, [56] = 0x09f8, [64] = 0x1f25,
38 [69] = 0x0004, [82] = 0xaaaa, [84] = 0x2a2a, [146] = 0x0060,
39 [256] = 0x0002, [257] = 0x8004, [520] = 0x0010, [528] = 0x0083,
40 [529] = 0x0083, [548] = 0x0c80, [580] = 0x0c80, [768] = 0x4050,
41 [769] = 0x4000, [771] = 0x0040, [772] = 0x0040, [773] = 0x0040,
42 [774] = 0x0004, [775] = 0x0100, [784] = 0x4050, [785] = 0x4000,
43 [787] = 0x0040, [788] = 0x0040, [789] = 0x0040, [1024] = 0x00c0,
44 [1025] = 0x00c0, [1026] = 0x00c0, [1027] = 0x00c0, [1028] = 0x00c0,
45 [1029] = 0x00c0, [1030] = 0x00c0, [1031] = 0x00c0, [1056] = 0x0200,
46 [1057] = 0x0010, [1058] = 0x0200, [1059] = 0x0010, [1088] = 0x0098,
47 [1089] = 0x0845, [1104] = 0x0098, [1105] = 0x0845, [1152] = 0x6318,
48 [1153] = 0x6300, [1154] = 0x0fca, [1155] = 0x0400, [1156] = 0x00d8,
49 [1157] = 0x1eb5, [1158] = 0xf145, [1159] = 0x0b75, [1160] = 0x01c5,
50 [1161] = 0x1c58, [1162] = 0xf373, [1163] = 0x0a54, [1164] = 0x0558,
51 [1165] = 0x168e, [1166] = 0xf829, [1167] = 0x07ad, [1168] = 0x1103,
52 [1169] = 0x0564, [1170] = 0x0559, [1171] = 0x4000, [1184] = 0x6318,
53 [1185] = 0x6300, [1186] = 0x0fca, [1187] = 0x0400, [1188] = 0x00d8,
54 [1189] = 0x1eb5, [1190] = 0xf145, [1191] = 0x0b75, [1192] = 0x01c5,
55 [1193] = 0x1c58, [1194] = 0xf373, [1195] = 0x0a54, [1196] = 0x0558,
56 [1197] = 0x168e, [1198] = 0xf829, [1199] = 0x07ad, [1200] = 0x1103,
57 [1201] = 0x0564, [1202] = 0x0559, [1203] = 0x4000, [1280] = 0x00c0,
58 [1281] = 0x00c0, [1282] = 0x00c0, [1283] = 0x00c0, [1312] = 0x0200,
59 [1313] = 0x0010, [1344] = 0x0098, [1345] = 0x0845, [1408] = 0x6318,
60 [1409] = 0x6300, [1410] = 0x0fca, [1411] = 0x0400, [1412] = 0x00d8,
61 [1413] = 0x1eb5, [1414] = 0xf145, [1415] = 0x0b75, [1416] = 0x01c5,
62 [1417] = 0x1c58, [1418] = 0xf373, [1419] = 0x0a54, [1420] = 0x0558,
63 [1421] = 0x168e, [1422] = 0xf829, [1423] = 0x07ad, [1424] = 0x1103,
64 [1425] = 0x0564, [1426] = 0x0559, [1427] = 0x4000, [1568] = 0x0002,
65 [1792] = 0xa100, [1793] = 0xa101, [1794] = 0xa101, [1795] = 0xa101,
66 [1796] = 0xa101, [1797] = 0xa101, [1798] = 0xa101, [1799] = 0xa101,
67 [1800] = 0xa101, [1801] = 0xa101, [1802] = 0xa101, [1803] = 0xa101,
68 [1804] = 0xa101, [1805] = 0xa101, [1825] = 0x0055, [1848] = 0x3fff,
69 [1849] = 0x1fff, [2049] = 0x0001, [2050] = 0x0069, [2056] = 0x0002,
70 [2057] = 0x0003, [2058] = 0x0069, [12288] = 0x0001, [12289] = 0x0001,
71 [12291] = 0x0006, [12292] = 0x0040, [12293] = 0x0001, [12294] = 0x000f,
72 [12295] = 0x0006, [12296] = 0x0001, [12297] = 0x0003, [12298] = 0x0104,
73 [12300] = 0x0060, [12301] = 0x0011, [12302] = 0x0401, [12304] = 0x0050,
74 [12305] = 0x0003, [12306] = 0x0100, [12308] = 0x0051, [12309] = 0x0003,
75 [12310] = 0x0104, [12311] = 0x000a, [12312] = 0x0060, [12313] = 0x003b,
76 [12314] = 0x0502, [12315] = 0x0100, [12316] = 0x2fff, [12320] = 0x2fff,
77 [12324] = 0x2fff, [12328] = 0x2fff, [12332] = 0x2fff, [12336] = 0x2fff,
78 [12340] = 0x2fff, [12344] = 0x2fff, [12348] = 0x2fff, [12352] = 0x0001,
79 [12353] = 0x0001, [12355] = 0x0006, [12356] = 0x0040, [12357] = 0x0001,
80 [12358] = 0x000f, [12359] = 0x0006, [12360] = 0x0001, [12361] = 0x0003,
81 [12362] = 0x0104, [12364] = 0x0060, [12365] = 0x0011, [12366] = 0x0401,
82 [12368] = 0x0050, [12369] = 0x0003, [12370] = 0x0100, [12372] = 0x0060,
83 [12373] = 0x003b, [12374] = 0x0502, [12375] = 0x0100, [12376] = 0x2fff,
84 [12380] = 0x2fff, [12384] = 0x2fff, [12388] = 0x2fff, [12392] = 0x2fff,
85 [12396] = 0x2fff, [12400] = 0x2fff, [12404] = 0x2fff, [12408] = 0x2fff,
86 [12412] = 0x2fff, [12416] = 0x0001, [12417] = 0x0001, [12419] = 0x0006,
87 [12420] = 0x0040, [12421] = 0x0001, [12422] = 0x000f, [12423] = 0x0006,
88 [12424] = 0x0001, [12425] = 0x0003, [12426] = 0x0106, [12428] = 0x0061,
89 [12429] = 0x0011, [12430] = 0x0401, [12432] = 0x0050, [12433] = 0x0003,
90 [12434] = 0x0102, [12436] = 0x0051, [12437] = 0x0003, [12438] = 0x0106,
91 [12439] = 0x000a, [12440] = 0x0061, [12441] = 0x003b, [12442] = 0x0502,
92 [12443] = 0x0100, [12444] = 0x2fff, [12448] = 0x2fff, [12452] = 0x2fff,
93 [12456] = 0x2fff, [12460] = 0x2fff, [12464] = 0x2fff, [12468] = 0x2fff,
94 [12472] = 0x2fff, [12476] = 0x2fff, [12480] = 0x0001, [12481] = 0x0001,
95 [12483] = 0x0006, [12484] = 0x0040, [12485] = 0x0001, [12486] = 0x000f,
96 [12487] = 0x0006, [12488] = 0x0001, [12489] = 0x0003, [12490] = 0x0106,
97 [12492] = 0x0061, [12493] = 0x0011, [12494] = 0x0401, [12496] = 0x0050,
98 [12497] = 0x0003, [12498] = 0x0102, [12500] = 0x0061, [12501] = 0x003b,
99 [12502] = 0x0502, [12503] = 0x0100, [12504] = 0x2fff, [12508] = 0x2fff,
100 [12512] = 0x2fff, [12516] = 0x2fff, [12520] = 0x2fff, [12524] = 0x2fff,
101 [12528] = 0x2fff, [12532] = 0x2fff, [12536] = 0x2fff, [12540] = 0x2fff,
102 [12544] = 0x0060, [12546] = 0x0601, [12548] = 0x0050, [12550] = 0x0100,
103 [12552] = 0x0001, [12554] = 0x0104, [12555] = 0x0100, [12556] = 0x2fff,
104 [12560] = 0x2fff, [12564] = 0x2fff, [12568] = 0x2fff, [12572] = 0x2fff,
105 [12576] = 0x2fff, [12580] = 0x2fff, [12584] = 0x2fff, [12588] = 0x2fff,
106 [12592] = 0x2fff, [12596] = 0x2fff, [12600] = 0x2fff, [12604] = 0x2fff,
107 [12608] = 0x0061, [12610] = 0x0601, [12612] = 0x0050, [12614] = 0x0102,
108 [12616] = 0x0001, [12618] = 0x0106, [12619] = 0x0100, [12620] = 0x2fff,
109 [12624] = 0x2fff, [12628] = 0x2fff, [12632] = 0x2fff, [12636] = 0x2fff,
110 [12640] = 0x2fff, [12644] = 0x2fff, [12648] = 0x2fff, [12652] = 0x2fff,
111 [12656] = 0x2fff, [12660] = 0x2fff, [12664] = 0x2fff, [12668] = 0x2fff,
112 [12672] = 0x0060, [12674] = 0x0601, [12676] = 0x0061, [12678] = 0x0601,
113 [12680] = 0x0050, [12682] = 0x0300, [12684] = 0x0001, [12686] = 0x0304,
114 [12688] = 0x0040, [12690] = 0x000f, [12692] = 0x0001, [12695] = 0x0100
115};
116
117struct fll_config {
118 int src;
119 int in;
120 int out;
121};
122
123struct wm8995_priv {
124 enum snd_soc_control_type control_type;
125 int sysclk[2];
126 int mclk[2];
127 int aifclk[2];
128 struct fll_config fll[2], fll_suspend[2];
129};
130
131static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
132static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0);
133static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0);
134static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
135
136static const char *in1l_text[] = {
137 "Differential", "Single-ended IN1LN", "Single-ended IN1LP"
138};
139
140static const SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
141 2, in1l_text);
142
143static const char *in1r_text[] = {
144 "Differential", "Single-ended IN1RN", "Single-ended IN1RP"
145};
146
147static const SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL,
148 0, in1r_text);
149
150static const char *dmic_src_text[] = {
151 "DMICDAT1", "DMICDAT2", "DMICDAT3"
152};
153
154static const SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5,
155 8, dmic_src_text);
156static const SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5,
157 6, dmic_src_text);
158
159static const struct snd_kcontrol_new wm8995_snd_controls[] = {
160 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME,
161 WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
162 SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME,
163 WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1),
164
165 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME,
166 WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
167 SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME,
168 WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1),
169
170 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME,
171 WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
172 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME,
173 WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
174 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME,
175 WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
176
177 SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME,
178 WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv),
179
180 SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL,
181 4, 3, 0, in1l_boost_tlv),
182
183 SOC_ENUM("IN1L Mode", in1l_enum),
184 SOC_ENUM("IN1R Mode", in1r_enum),
185
186 SOC_ENUM("DMIC1 SRC", dmic_src1_enum),
187 SOC_ENUM("DMIC2 SRC", dmic_src2_enum),
188
189 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5,
190 24, 0, sidetone_tlv),
191 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5,
192 24, 0, sidetone_tlv),
193
194 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME,
195 WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
196 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME,
197 WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv),
198 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME,
199 WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv)
200};
201
202static void wm8995_update_class_w(struct snd_soc_codec *codec)
203{
204 int enable = 1;
205 int source = 0; /* GCC flow analysis can't track enable */
206 int reg, reg_r;
207
208 /* We also need the same setting for L/R and only one path */
209 reg = snd_soc_read(codec, WM8995_DAC1_LEFT_MIXER_ROUTING);
210 switch (reg) {
211 case WM8995_AIF2DACL_TO_DAC1L:
212 dev_dbg(codec->dev, "Class W source AIF2DAC\n");
213 source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT;
214 break;
215 case WM8995_AIF1DAC2L_TO_DAC1L:
216 dev_dbg(codec->dev, "Class W source AIF1DAC2\n");
217 source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT;
218 break;
219 case WM8995_AIF1DAC1L_TO_DAC1L:
220 dev_dbg(codec->dev, "Class W source AIF1DAC1\n");
221 source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT;
222 break;
223 default:
224 dev_dbg(codec->dev, "DAC mixer setting: %x\n", reg);
225 enable = 0;
226 break;
227 }
228
229 reg_r = snd_soc_read(codec, WM8995_DAC1_RIGHT_MIXER_ROUTING);
230 if (reg_r != reg) {
231 dev_dbg(codec->dev, "Left and right DAC mixers different\n");
232 enable = 0;
233 }
234
235 if (enable) {
236 dev_dbg(codec->dev, "Class W enabled\n");
237 snd_soc_update_bits(codec, WM8995_CLASS_W_1,
238 WM8995_CP_DYN_PWR_MASK |
239 WM8995_CP_DYN_SRC_SEL_MASK,
240 source | WM8995_CP_DYN_PWR);
241 } else {
242 dev_dbg(codec->dev, "Class W disabled\n");
243 snd_soc_update_bits(codec, WM8995_CLASS_W_1,
244 WM8995_CP_DYN_PWR_MASK, 0);
245 }
246}
247
248static int check_clk_sys(struct snd_soc_dapm_widget *source,
249 struct snd_soc_dapm_widget *sink)
250{
251 unsigned int reg;
252 const char *clk;
253
254 reg = snd_soc_read(source->codec, WM8995_CLOCKING_1);
255 /* Check what we're currently using for CLK_SYS */
256 if (reg & WM8995_SYSCLK_SRC)
257 clk = "AIF2CLK";
258 else
259 clk = "AIF1CLK";
260 return !strcmp(source->name, clk);
261}
262
263static int wm8995_put_class_w(struct snd_kcontrol *kcontrol,
264 struct snd_ctl_elem_value *ucontrol)
265{
266 struct snd_soc_dapm_widget *w;
267 struct snd_soc_codec *codec;
268 int ret;
269
270 w = snd_kcontrol_chip(kcontrol);
271 codec = w->codec;
272 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
273 wm8995_update_class_w(codec);
274 return ret;
275}
276
277static int hp_supply_event(struct snd_soc_dapm_widget *w,
278 struct snd_kcontrol *kcontrol, int event)
279{
280 struct snd_soc_codec *codec;
281 struct wm8995_priv *wm8995;
282
283 codec = w->codec;
284 wm8995 = snd_soc_codec_get_drvdata(codec);
285
286 switch (event) {
287 case SND_SOC_DAPM_PRE_PMU:
288 /* Enable the headphone amp */
289 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
290 WM8995_HPOUT1L_ENA_MASK |
291 WM8995_HPOUT1R_ENA_MASK,
292 WM8995_HPOUT1L_ENA |
293 WM8995_HPOUT1R_ENA);
294
295 /* Enable the second stage */
296 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
297 WM8995_HPOUT1L_DLY_MASK |
298 WM8995_HPOUT1R_DLY_MASK,
299 WM8995_HPOUT1L_DLY |
300 WM8995_HPOUT1R_DLY);
301 break;
302 case SND_SOC_DAPM_PRE_PMD:
303 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1,
304 WM8995_CP_ENA_MASK, 0);
305 break;
306 }
307
308 return 0;
309}
310
311static void dc_servo_cmd(struct snd_soc_codec *codec,
312 unsigned int reg, unsigned int val, unsigned int mask)
313{
314 int timeout = 10;
315
316 dev_dbg(codec->dev, "%s: reg = %#x, val = %#x, mask = %#x\n",
317 __func__, reg, val, mask);
318
319 snd_soc_write(codec, reg, val);
320 while (timeout--) {
321 msleep(10);
322 val = snd_soc_read(codec, WM8995_DC_SERVO_READBACK_0);
323 if ((val & mask) == mask)
324 return;
325 }
326
327 dev_err(codec->dev, "Timed out waiting for DC Servo\n");
328}
329
330static int hp_event(struct snd_soc_dapm_widget *w,
331 struct snd_kcontrol *kcontrol, int event)
332{
333 struct snd_soc_codec *codec;
334 unsigned int reg;
335
336 codec = w->codec;
337 reg = snd_soc_read(codec, WM8995_ANALOGUE_HP_1);
338
339 switch (event) {
340 case SND_SOC_DAPM_POST_PMU:
341 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1,
342 WM8995_CP_ENA_MASK, WM8995_CP_ENA);
343
344 msleep(5);
345
346 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
347 WM8995_HPOUT1L_ENA_MASK |
348 WM8995_HPOUT1R_ENA_MASK,
349 WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA);
350
351 udelay(20);
352
353 reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY;
354 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg);
355
356 snd_soc_write(codec, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 |
357 WM8995_DCS_ENA_CHAN_1);
358
359 dc_servo_cmd(codec, WM8995_DC_SERVO_2,
360 WM8995_DCS_TRIG_STARTUP_0 |
361 WM8995_DCS_TRIG_STARTUP_1,
362 WM8995_DCS_TRIG_DAC_WR_0 |
363 WM8995_DCS_TRIG_DAC_WR_1);
364
365 reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT |
366 WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT;
367 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg);
368
369 break;
370 case SND_SOC_DAPM_PRE_PMD:
371 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
372 WM8995_HPOUT1L_OUTP_MASK |
373 WM8995_HPOUT1R_OUTP_MASK |
374 WM8995_HPOUT1L_RMV_SHORT_MASK |
375 WM8995_HPOUT1R_RMV_SHORT_MASK, 0);
376
377 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1,
378 WM8995_HPOUT1L_DLY_MASK |
379 WM8995_HPOUT1R_DLY_MASK, 0);
380
381 snd_soc_write(codec, WM8995_DC_SERVO_1, 0);
382
383 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
384 WM8995_HPOUT1L_ENA_MASK |
385 WM8995_HPOUT1R_ENA_MASK,
386 0);
387 break;
388 }
389
390 return 0;
391}
392
393static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
394{
395 struct wm8995_priv *wm8995;
396 int rate;
397 int reg1 = 0;
398 int offset;
399
400 wm8995 = snd_soc_codec_get_drvdata(codec);
401
402 if (aif)
403 offset = 4;
404 else
405 offset = 0;
406
407 switch (wm8995->sysclk[aif]) {
408 case WM8995_SYSCLK_MCLK1:
409 rate = wm8995->mclk[0];
410 break;
411 case WM8995_SYSCLK_MCLK2:
412 reg1 |= 0x8;
413 rate = wm8995->mclk[1];
414 break;
415 case WM8995_SYSCLK_FLL1:
416 reg1 |= 0x10;
417 rate = wm8995->fll[0].out;
418 break;
419 case WM8995_SYSCLK_FLL2:
420 reg1 |= 0x18;
421 rate = wm8995->fll[1].out;
422 break;
423 default:
424 return -EINVAL;
425 }
426
427 if (rate >= 13500000) {
428 rate /= 2;
429 reg1 |= WM8995_AIF1CLK_DIV;
430
431 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
432 aif + 1, rate);
433 }
434
435 wm8995->aifclk[aif] = rate;
436
437 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1 + offset,
438 WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK,
439 reg1);
440 return 0;
441}
442
443static int configure_clock(struct snd_soc_codec *codec)
444{
445 struct wm8995_priv *wm8995;
446 int old, new;
447
448 wm8995 = snd_soc_codec_get_drvdata(codec);
449
450 /* Bring up the AIF clocks first */
451 configure_aif_clock(codec, 0);
452 configure_aif_clock(codec, 1);
453
454 /*
455 * Then switch CLK_SYS over to the higher of them; a change
456 * can only happen as a result of a clocking change which can
457 * only be made outside of DAPM so we can safely redo the
458 * clocking.
459 */
460
461 /* If they're equal it doesn't matter which is used */
462 if (wm8995->aifclk[0] == wm8995->aifclk[1])
463 return 0;
464
465 if (wm8995->aifclk[0] < wm8995->aifclk[1])
466 new = WM8995_SYSCLK_SRC;
467 else
468 new = 0;
469
470 old = snd_soc_read(codec, WM8995_CLOCKING_1) & WM8995_SYSCLK_SRC;
471
472 /* If there's no change then we're done. */
473 if (old == new)
474 return 0;
475
476 snd_soc_update_bits(codec, WM8995_CLOCKING_1,
477 WM8995_SYSCLK_SRC_MASK, new);
478
479 snd_soc_dapm_sync(&codec->dapm);
480
481 return 0;
482}
483
484static int clk_sys_event(struct snd_soc_dapm_widget *w,
485 struct snd_kcontrol *kcontrol, int event)
486{
487 struct snd_soc_codec *codec;
488
489 codec = w->codec;
490
491 switch (event) {
492 case SND_SOC_DAPM_PRE_PMU:
493 return configure_clock(codec);
494
495 case SND_SOC_DAPM_POST_PMD:
496 configure_clock(codec);
497 break;
498 }
499
500 return 0;
501}
502
503static const char *sidetone_text[] = {
504 "ADC/DMIC1", "DMIC2",
505};
506
507static const struct soc_enum sidetone1_enum =
508 SOC_ENUM_SINGLE(WM8995_SIDETONE, 0, 2, sidetone_text);
509
510static const struct snd_kcontrol_new sidetone1_mux =
511 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
512
513static const struct soc_enum sidetone2_enum =
514 SOC_ENUM_SINGLE(WM8995_SIDETONE, 1, 2, sidetone_text);
515
516static const struct snd_kcontrol_new sidetone2_mux =
517 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
518
519static const struct snd_kcontrol_new aif1adc1l_mix[] = {
520 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
521 1, 1, 0),
522 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING,
523 0, 1, 0),
524};
525
526static const struct snd_kcontrol_new aif1adc1r_mix[] = {
527 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
528 1, 1, 0),
529 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING,
530 0, 1, 0),
531};
532
533static const struct snd_kcontrol_new aif1adc2l_mix[] = {
534 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
535 1, 1, 0),
536 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING,
537 0, 1, 0),
538};
539
540static const struct snd_kcontrol_new aif1adc2r_mix[] = {
541 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
542 1, 1, 0),
543 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING,
544 0, 1, 0),
545};
546
547static const struct snd_kcontrol_new dac1l_mix[] = {
548 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
549 5, 1, 0),
550 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
551 4, 1, 0),
552 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
553 2, 1, 0),
554 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
555 1, 1, 0),
556 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING,
557 0, 1, 0),
558};
559
560static const struct snd_kcontrol_new dac1r_mix[] = {
561 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
562 5, 1, 0),
563 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
564 4, 1, 0),
565 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
566 2, 1, 0),
567 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
568 1, 1, 0),
569 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING,
570 0, 1, 0),
571};
572
573static const struct snd_kcontrol_new aif2dac2l_mix[] = {
574 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
575 5, 1, 0),
576 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
577 4, 1, 0),
578 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
579 2, 1, 0),
580 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
581 1, 1, 0),
582 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING,
583 0, 1, 0),
584};
585
586static const struct snd_kcontrol_new aif2dac2r_mix[] = {
587 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
588 5, 1, 0),
589 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
590 4, 1, 0),
591 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
592 2, 1, 0),
593 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
594 1, 1, 0),
595 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING,
596 0, 1, 0),
597};
598
599static const struct snd_kcontrol_new in1l_pga =
600 SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0);
601
602static const struct snd_kcontrol_new in1r_pga =
603 SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0);
604
605static const char *adc_mux_text[] = {
606 "ADC",
607 "DMIC",
608};
609
610static const struct soc_enum adc_enum =
611 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
612
613static const struct snd_kcontrol_new adcl_mux =
614 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
615
616static const struct snd_kcontrol_new adcr_mux =
617 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
618
619static const char *spk_src_text[] = {
620 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
621};
622
623static const SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1,
624 0, spk_src_text);
625static const SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1,
626 0, spk_src_text);
627static const SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2,
628 0, spk_src_text);
629static const SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2,
630 0, spk_src_text);
631
632static const struct snd_kcontrol_new spk1l_mux =
633 SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum);
634static const struct snd_kcontrol_new spk1r_mux =
635 SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum);
636static const struct snd_kcontrol_new spk2l_mux =
637 SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum);
638static const struct snd_kcontrol_new spk2r_mux =
639 SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum);
640
641static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = {
642 SND_SOC_DAPM_INPUT("DMIC1DAT"),
643 SND_SOC_DAPM_INPUT("DMIC2DAT"),
644
645 SND_SOC_DAPM_INPUT("IN1L"),
646 SND_SOC_DAPM_INPUT("IN1R"),
647
648 SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0,
649 &in1l_pga, 1),
650 SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0,
651 &in1r_pga, 1),
652
653 SND_SOC_DAPM_MICBIAS("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0),
654 SND_SOC_DAPM_MICBIAS("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0),
655
656 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0),
657 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0),
658 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0),
659 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0),
660 SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0),
661 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
662 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
663
664 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0,
665 WM8995_POWER_MANAGEMENT_3, 9, 0),
666 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0,
667 WM8995_POWER_MANAGEMENT_3, 8, 0),
668 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0,
669 SND_SOC_NOPM, 0, 0),
670 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
671 0, WM8995_POWER_MANAGEMENT_3, 11, 0),
672 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
673 0, WM8995_POWER_MANAGEMENT_3, 10, 0),
674
675 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0,
676 &adcl_mux),
677 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
678 &adcr_mux),
679
680 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0),
681 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0),
682 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0),
683 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0),
684
685 SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0),
686 SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0),
687
688 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
689 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
690 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
691 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
692 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
693 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
694 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
695 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
696
697 SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
698 9, 0),
699 SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
700 8, 0),
701 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM,
702 0, 0),
703
704 SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4,
705 11, 0),
706 SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4,
707 10, 0),
708
709 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
710 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
711 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
712 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
713
714 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0),
715 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0),
716 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0),
717 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0),
718
719 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix,
720 ARRAY_SIZE(dac1l_mix)),
721 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix,
722 ARRAY_SIZE(dac1r_mix)),
723
724 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
725 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
726
727 SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
728 hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
729
730 SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0,
731 hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
732
733 SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1,
734 4, 0, &spk1l_mux),
735 SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1,
736 4, 0, &spk1r_mux),
737 SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2,
738 4, 0, &spk2l_mux),
739 SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2,
740 4, 0, &spk2r_mux),
741
742 SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
743
744 SND_SOC_DAPM_OUTPUT("HP1L"),
745 SND_SOC_DAPM_OUTPUT("HP1R"),
746 SND_SOC_DAPM_OUTPUT("SPK1L"),
747 SND_SOC_DAPM_OUTPUT("SPK1R"),
748 SND_SOC_DAPM_OUTPUT("SPK2L"),
749 SND_SOC_DAPM_OUTPUT("SPK2R")
750};
751
752static const struct snd_soc_dapm_route wm8995_intercon[] = {
753 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
754 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
755
756 { "DSP1CLK", NULL, "CLK_SYS" },
757 { "DSP2CLK", NULL, "CLK_SYS" },
758 { "SYSDSPCLK", NULL, "CLK_SYS" },
759
760 { "AIF1ADC1L", NULL, "AIF1CLK" },
761 { "AIF1ADC1L", NULL, "DSP1CLK" },
762 { "AIF1ADC1R", NULL, "AIF1CLK" },
763 { "AIF1ADC1R", NULL, "DSP1CLK" },
764 { "AIF1ADC1R", NULL, "SYSDSPCLK" },
765
766 { "AIF1ADC2L", NULL, "AIF1CLK" },
767 { "AIF1ADC2L", NULL, "DSP1CLK" },
768 { "AIF1ADC2R", NULL, "AIF1CLK" },
769 { "AIF1ADC2R", NULL, "DSP1CLK" },
770 { "AIF1ADC2R", NULL, "SYSDSPCLK" },
771
772 { "DMIC1L", NULL, "DMIC1DAT" },
773 { "DMIC1L", NULL, "CLK_SYS" },
774 { "DMIC1R", NULL, "DMIC1DAT" },
775 { "DMIC1R", NULL, "CLK_SYS" },
776 { "DMIC2L", NULL, "DMIC2DAT" },
777 { "DMIC2L", NULL, "CLK_SYS" },
778 { "DMIC2R", NULL, "DMIC2DAT" },
779 { "DMIC2R", NULL, "CLK_SYS" },
780
781 { "ADCL", NULL, "AIF1CLK" },
782 { "ADCL", NULL, "DSP1CLK" },
783 { "ADCL", NULL, "SYSDSPCLK" },
784
785 { "ADCR", NULL, "AIF1CLK" },
786 { "ADCR", NULL, "DSP1CLK" },
787 { "ADCR", NULL, "SYSDSPCLK" },
788
789 { "IN1L PGA", "IN1L Switch", "IN1L" },
790 { "IN1R PGA", "IN1R Switch", "IN1R" },
791 { "IN1L PGA", NULL, "LDO2" },
792 { "IN1R PGA", NULL, "LDO2" },
793
794 { "ADCL", NULL, "IN1L PGA" },
795 { "ADCR", NULL, "IN1R PGA" },
796
797 { "ADCL Mux", "ADC", "ADCL" },
798 { "ADCL Mux", "DMIC", "DMIC1L" },
799 { "ADCR Mux", "ADC", "ADCR" },
800 { "ADCR Mux", "DMIC", "DMIC1R" },
801
802 /* AIF1 outputs */
803 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
804 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
805
806 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
807 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
808
809 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
810 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
811
812 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
813 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
814
815 /* Sidetone */
816 { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" },
817 { "Left Sidetone", "DMIC2", "AIF1ADC2L" },
818 { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" },
819 { "Right Sidetone", "DMIC2", "AIF1ADC2R" },
820
821 { "AIF1DAC1L", NULL, "AIF1CLK" },
822 { "AIF1DAC1L", NULL, "DSP1CLK" },
823 { "AIF1DAC1R", NULL, "AIF1CLK" },
824 { "AIF1DAC1R", NULL, "DSP1CLK" },
825 { "AIF1DAC1R", NULL, "SYSDSPCLK" },
826
827 { "AIF1DAC2L", NULL, "AIF1CLK" },
828 { "AIF1DAC2L", NULL, "DSP1CLK" },
829 { "AIF1DAC2R", NULL, "AIF1CLK" },
830 { "AIF1DAC2R", NULL, "DSP1CLK" },
831 { "AIF1DAC2R", NULL, "SYSDSPCLK" },
832
833 { "DAC1L", NULL, "AIF1CLK" },
834 { "DAC1L", NULL, "DSP1CLK" },
835 { "DAC1L", NULL, "SYSDSPCLK" },
836
837 { "DAC1R", NULL, "AIF1CLK" },
838 { "DAC1R", NULL, "DSP1CLK" },
839 { "DAC1R", NULL, "SYSDSPCLK" },
840
841 { "AIF1DAC1L", NULL, "AIF1DACDAT" },
842 { "AIF1DAC1R", NULL, "AIF1DACDAT" },
843 { "AIF1DAC2L", NULL, "AIF1DACDAT" },
844 { "AIF1DAC2R", NULL, "AIF1DACDAT" },
845
846 /* DAC1 inputs */
847 { "DAC1L", NULL, "DAC1L Mixer" },
848 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
849 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
850 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
851 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
852
853 { "DAC1R", NULL, "DAC1R Mixer" },
854 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
855 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
856 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
857 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
858
859 /* DAC2/AIF2 outputs */
860 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
861 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
862 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
863
864 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
865 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
866 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
867
868 /* Output stages */
869 { "Headphone PGA", NULL, "DAC1L" },
870 { "Headphone PGA", NULL, "DAC1R" },
871
872 { "Headphone PGA", NULL, "DAC2L" },
873 { "Headphone PGA", NULL, "DAC2R" },
874
875 { "Headphone PGA", NULL, "Headphone Supply" },
876 { "Headphone PGA", NULL, "CLK_SYS" },
877 { "Headphone PGA", NULL, "LDO2" },
878
879 { "HP1L", NULL, "Headphone PGA" },
880 { "HP1R", NULL, "Headphone PGA" },
881
882 { "SPK1L Driver", "DAC1L", "DAC1L" },
883 { "SPK1L Driver", "DAC1R", "DAC1R" },
884 { "SPK1L Driver", "DAC2L", "DAC2L" },
885 { "SPK1L Driver", "DAC2R", "DAC2R" },
886 { "SPK1L Driver", NULL, "CLK_SYS" },
887
888 { "SPK1R Driver", "DAC1L", "DAC1L" },
889 { "SPK1R Driver", "DAC1R", "DAC1R" },
890 { "SPK1R Driver", "DAC2L", "DAC2L" },
891 { "SPK1R Driver", "DAC2R", "DAC2R" },
892 { "SPK1R Driver", NULL, "CLK_SYS" },
893
894 { "SPK2L Driver", "DAC1L", "DAC1L" },
895 { "SPK2L Driver", "DAC1R", "DAC1R" },
896 { "SPK2L Driver", "DAC2L", "DAC2L" },
897 { "SPK2L Driver", "DAC2R", "DAC2R" },
898 { "SPK2L Driver", NULL, "CLK_SYS" },
899
900 { "SPK2R Driver", "DAC1L", "DAC1L" },
901 { "SPK2R Driver", "DAC1R", "DAC1R" },
902 { "SPK2R Driver", "DAC2L", "DAC2L" },
903 { "SPK2R Driver", "DAC2R", "DAC2R" },
904 { "SPK2R Driver", NULL, "CLK_SYS" },
905
906 { "SPK1L", NULL, "SPK1L Driver" },
907 { "SPK1R", NULL, "SPK1R Driver" },
908 { "SPK2L", NULL, "SPK2L Driver" },
909 { "SPK2R", NULL, "SPK2R Driver" }
910};
911
912static int wm8995_volatile(unsigned int reg)
913{
914 /* out of bounds registers are generally considered
915 * volatile to support register banks that are partially
916 * owned by something else for e.g. a DSP
917 */
918 if (reg > WM8995_MAX_CACHED_REGISTER)
919 return 1;
920
921 switch (reg) {
922 case WM8995_SOFTWARE_RESET:
923 case WM8995_DC_SERVO_READBACK_0:
924 case WM8995_INTERRUPT_STATUS_1:
925 case WM8995_INTERRUPT_STATUS_2:
926 case WM8995_INTERRUPT_STATUS_1_MASK:
927 case WM8995_INTERRUPT_STATUS_2_MASK:
928 case WM8995_INTERRUPT_CONTROL:
929 case WM8995_ACCESSORY_DETECT_MODE1:
930 case WM8995_ACCESSORY_DETECT_MODE2:
931 case WM8995_HEADPHONE_DETECT1:
932 case WM8995_HEADPHONE_DETECT2:
933 return 1;
934 }
935
936 return 0;
937}
938
939static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute)
940{
941 struct snd_soc_codec *codec = dai->codec;
942 int mute_reg;
943
944 switch (dai->id) {
945 case 0:
946 mute_reg = WM8995_AIF1_DAC1_FILTERS_1;
947 break;
948 case 1:
949 mute_reg = WM8995_AIF2_DAC_FILTERS_1;
950 break;
951 default:
952 return -EINVAL;
953 }
954
955 snd_soc_update_bits(codec, mute_reg, WM8995_AIF1DAC1_MUTE_MASK,
956 !!mute << WM8995_AIF1DAC1_MUTE_SHIFT);
957 return 0;
958}
959
960static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
961{
962 struct snd_soc_codec *codec;
963 int master;
964 int aif;
965
966 codec = dai->codec;
967
968 master = 0;
969 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
970 case SND_SOC_DAIFMT_CBS_CFS:
971 break;
972 case SND_SOC_DAIFMT_CBM_CFM:
973 master = WM8995_AIF1_MSTR;
974 break;
975 default:
976 dev_err(dai->dev, "Unknown master/slave configuration\n");
977 return -EINVAL;
978 }
979
980 aif = 0;
981 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
982 case SND_SOC_DAIFMT_DSP_B:
983 aif |= WM8995_AIF1_LRCLK_INV;
984 case SND_SOC_DAIFMT_DSP_A:
985 aif |= (0x3 << WM8995_AIF1_FMT_SHIFT);
986 break;
987 case SND_SOC_DAIFMT_I2S:
988 aif |= (0x2 << WM8995_AIF1_FMT_SHIFT);
989 break;
990 case SND_SOC_DAIFMT_RIGHT_J:
991 break;
992 case SND_SOC_DAIFMT_LEFT_J:
993 aif |= (0x1 << WM8995_AIF1_FMT_SHIFT);
994 break;
995 default:
996 dev_err(dai->dev, "Unknown dai format\n");
997 return -EINVAL;
998 }
999
1000 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1001 case SND_SOC_DAIFMT_DSP_A:
1002 case SND_SOC_DAIFMT_DSP_B:
1003 /* frame inversion not valid for DSP modes */
1004 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1005 case SND_SOC_DAIFMT_NB_NF:
1006 break;
1007 case SND_SOC_DAIFMT_IB_NF:
1008 aif |= WM8995_AIF1_BCLK_INV;
1009 break;
1010 default:
1011 return -EINVAL;
1012 }
1013 break;
1014
1015 case SND_SOC_DAIFMT_I2S:
1016 case SND_SOC_DAIFMT_RIGHT_J:
1017 case SND_SOC_DAIFMT_LEFT_J:
1018 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1019 case SND_SOC_DAIFMT_NB_NF:
1020 break;
1021 case SND_SOC_DAIFMT_IB_IF:
1022 aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV;
1023 break;
1024 case SND_SOC_DAIFMT_IB_NF:
1025 aif |= WM8995_AIF1_BCLK_INV;
1026 break;
1027 case SND_SOC_DAIFMT_NB_IF:
1028 aif |= WM8995_AIF1_LRCLK_INV;
1029 break;
1030 default:
1031 return -EINVAL;
1032 }
1033 break;
1034 default:
1035 return -EINVAL;
1036 }
1037
1038 snd_soc_update_bits(codec, WM8995_AIF1_CONTROL_1,
1039 WM8995_AIF1_BCLK_INV_MASK |
1040 WM8995_AIF1_LRCLK_INV_MASK |
1041 WM8995_AIF1_FMT_MASK, aif);
1042 snd_soc_update_bits(codec, WM8995_AIF1_MASTER_SLAVE,
1043 WM8995_AIF1_MSTR_MASK, master);
1044 return 0;
1045}
1046
1047static const int srs[] = {
1048 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100,
1049 48000, 88200, 96000
1050};
1051
1052static const int fs_ratios[] = {
1053 -1 /* reserved */,
1054 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
1055};
1056
1057static const int bclk_divs[] = {
1058 10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480
1059};
1060
1061static int wm8995_hw_params(struct snd_pcm_substream *substream,
1062 struct snd_pcm_hw_params *params,
1063 struct snd_soc_dai *dai)
1064{
1065 struct snd_soc_codec *codec;
1066 struct wm8995_priv *wm8995;
1067 int aif1_reg;
1068 int bclk_reg;
1069 int lrclk_reg;
1070 int rate_reg;
1071 int bclk_rate;
1072 int aif1;
1073 int lrclk, bclk;
1074 int i, rate_val, best, best_val, cur_val;
1075
1076 codec = dai->codec;
1077 wm8995 = snd_soc_codec_get_drvdata(codec);
1078
1079 switch (dai->id) {
1080 case 0:
1081 aif1_reg = WM8995_AIF1_CONTROL_1;
1082 bclk_reg = WM8995_AIF1_BCLK;
1083 rate_reg = WM8995_AIF1_RATE;
1084 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
1085 wm8995->lrclk_shared[0] */) {
1086 lrclk_reg = WM8995_AIF1DAC_LRCLK;
1087 } else {
1088 lrclk_reg = WM8995_AIF1ADC_LRCLK;
1089 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
1090 }
1091 break;
1092 case 1:
1093 aif1_reg = WM8995_AIF2_CONTROL_1;
1094 bclk_reg = WM8995_AIF2_BCLK;
1095 rate_reg = WM8995_AIF2_RATE;
1096 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* ||
1097 wm8995->lrclk_shared[1] */) {
1098 lrclk_reg = WM8995_AIF2DAC_LRCLK;
1099 } else {
1100 lrclk_reg = WM8995_AIF2ADC_LRCLK;
1101 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
1102 }
1103 break;
1104 default:
1105 return -EINVAL;
1106 }
1107
1108 bclk_rate = snd_soc_params_to_bclk(params);
1109 if (bclk_rate < 0)
1110 return bclk_rate;
1111
1112 aif1 = 0;
1113 switch (params_format(params)) {
1114 case SNDRV_PCM_FORMAT_S16_LE:
1115 break;
1116 case SNDRV_PCM_FORMAT_S20_3LE:
1117 aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT);
1118 break;
1119 case SNDRV_PCM_FORMAT_S24_LE:
1120 aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT);
1121 break;
1122 case SNDRV_PCM_FORMAT_S32_LE:
1123 aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT);
1124 break;
1125 default:
1126 dev_err(dai->dev, "Unsupported word length %u\n",
1127 params_format(params));
1128 return -EINVAL;
1129 }
1130
1131 /* try to find a suitable sample rate */
1132 for (i = 0; i < ARRAY_SIZE(srs); ++i)
1133 if (srs[i] == params_rate(params))
1134 break;
1135 if (i == ARRAY_SIZE(srs)) {
1136 dev_err(dai->dev, "Sample rate %d is not supported\n",
1137 params_rate(params));
1138 return -EINVAL;
1139 }
1140 rate_val = i << WM8995_AIF1_SR_SHIFT;
1141
1142 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]);
1143 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
1144 dai->id + 1, wm8995->aifclk[dai->id], bclk_rate);
1145
1146 /* AIFCLK/fs ratio; look for a close match in either direction */
1147 best = 1;
1148 best_val = abs((fs_ratios[1] * params_rate(params))
1149 - wm8995->aifclk[dai->id]);
1150 for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) {
1151 cur_val = abs((fs_ratios[i] * params_rate(params))
1152 - wm8995->aifclk[dai->id]);
1153 if (cur_val >= best_val)
1154 continue;
1155 best = i;
1156 best_val = cur_val;
1157 }
1158 rate_val |= best;
1159
1160 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
1161 dai->id + 1, fs_ratios[best]);
1162
1163 /*
1164 * We may not get quite the right frequency if using
1165 * approximate clocks so look for the closest match that is
1166 * higher than the target (we need to ensure that there enough
1167 * BCLKs to clock out the samples).
1168 */
1169 best = 0;
1170 bclk = 0;
1171 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1172 cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate;
1173 if (cur_val < 0) /* BCLK table is sorted */
1174 break;
1175 best = i;
1176 }
1177 bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT;
1178
1179 bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best];
1180 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1181 bclk_divs[best], bclk_rate);
1182
1183 lrclk = bclk_rate / params_rate(params);
1184 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1185 lrclk, bclk_rate / lrclk);
1186
1187 snd_soc_update_bits(codec, aif1_reg,
1188 WM8995_AIF1_WL_MASK, aif1);
1189 snd_soc_update_bits(codec, bclk_reg,
1190 WM8995_AIF1_BCLK_DIV_MASK, bclk);
1191 snd_soc_update_bits(codec, lrclk_reg,
1192 WM8995_AIF1DAC_RATE_MASK, lrclk);
1193 snd_soc_update_bits(codec, rate_reg,
1194 WM8995_AIF1_SR_MASK |
1195 WM8995_AIF1CLK_RATE_MASK, rate_val);
1196 return 0;
1197}
1198
1199static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
1200{
1201 struct snd_soc_codec *codec = codec_dai->codec;
1202 int reg, val, mask;
1203
1204 switch (codec_dai->id) {
1205 case 0:
1206 reg = WM8995_AIF1_MASTER_SLAVE;
1207 mask = WM8995_AIF1_TRI;
1208 break;
1209 case 1:
1210 reg = WM8995_AIF2_MASTER_SLAVE;
1211 mask = WM8995_AIF2_TRI;
1212 break;
1213 case 2:
1214 reg = WM8995_POWER_MANAGEMENT_5;
1215 mask = WM8995_AIF3_TRI;
1216 break;
1217 default:
1218 return -EINVAL;
1219 }
1220
1221 if (tristate)
1222 val = mask;
1223 else
1224 val = 0;
1225
1226 return snd_soc_update_bits(codec, reg, mask, reg);
1227}
1228
1229/* The size in bits of the FLL divide multiplied by 10
1230 * to allow rounding later */
1231#define FIXED_FLL_SIZE ((1 << 16) * 10)
1232
1233struct fll_div {
1234 u16 outdiv;
1235 u16 n;
1236 u16 k;
1237 u16 clk_ref_div;
1238 u16 fll_fratio;
1239};
1240
1241static int wm8995_get_fll_config(struct fll_div *fll,
1242 int freq_in, int freq_out)
1243{
1244 u64 Kpart;
1245 unsigned int K, Ndiv, Nmod;
1246
1247 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1248
1249 /* Scale the input frequency down to <= 13.5MHz */
1250 fll->clk_ref_div = 0;
1251 while (freq_in > 13500000) {
1252 fll->clk_ref_div++;
1253 freq_in /= 2;
1254
1255 if (fll->clk_ref_div > 3)
1256 return -EINVAL;
1257 }
1258 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1259
1260 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1261 fll->outdiv = 3;
1262 while (freq_out * (fll->outdiv + 1) < 90000000) {
1263 fll->outdiv++;
1264 if (fll->outdiv > 63)
1265 return -EINVAL;
1266 }
1267 freq_out *= fll->outdiv + 1;
1268 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1269
1270 if (freq_in > 1000000) {
1271 fll->fll_fratio = 0;
1272 } else if (freq_in > 256000) {
1273 fll->fll_fratio = 1;
1274 freq_in *= 2;
1275 } else if (freq_in > 128000) {
1276 fll->fll_fratio = 2;
1277 freq_in *= 4;
1278 } else if (freq_in > 64000) {
1279 fll->fll_fratio = 3;
1280 freq_in *= 8;
1281 } else {
1282 fll->fll_fratio = 4;
1283 freq_in *= 16;
1284 }
1285 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1286
1287 /* Now, calculate N.K */
1288 Ndiv = freq_out / freq_in;
1289
1290 fll->n = Ndiv;
1291 Nmod = freq_out % freq_in;
1292 pr_debug("Nmod=%d\n", Nmod);
1293
1294 /* Calculate fractional part - scale up so we can round. */
1295 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1296
1297 do_div(Kpart, freq_in);
1298
1299 K = Kpart & 0xFFFFFFFF;
1300
1301 if ((K % 10) >= 5)
1302 K += 5;
1303
1304 /* Move down to proper range now rounding is done */
1305 fll->k = K / 10;
1306
1307 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1308
1309 return 0;
1310}
1311
1312static int wm8995_set_fll(struct snd_soc_dai *dai, int id,
1313 int src, unsigned int freq_in,
1314 unsigned int freq_out)
1315{
1316 struct snd_soc_codec *codec;
1317 struct wm8995_priv *wm8995;
1318 int reg_offset, ret;
1319 struct fll_div fll;
1320 u16 reg, aif1, aif2;
1321
1322 codec = dai->codec;
1323 wm8995 = snd_soc_codec_get_drvdata(codec);
1324
1325 aif1 = snd_soc_read(codec, WM8995_AIF1_CLOCKING_1)
1326 & WM8995_AIF1CLK_ENA;
1327
1328 aif2 = snd_soc_read(codec, WM8995_AIF2_CLOCKING_1)
1329 & WM8995_AIF2CLK_ENA;
1330
1331 switch (id) {
1332 case WM8995_FLL1:
1333 reg_offset = 0;
1334 id = 0;
1335 break;
1336 case WM8995_FLL2:
1337 reg_offset = 0x20;
1338 id = 1;
1339 break;
1340 default:
1341 return -EINVAL;
1342 }
1343
1344 switch (src) {
1345 case 0:
1346 /* Allow no source specification when stopping */
1347 if (freq_out)
1348 return -EINVAL;
1349 break;
1350 case WM8995_FLL_SRC_MCLK1:
1351 case WM8995_FLL_SRC_MCLK2:
1352 case WM8995_FLL_SRC_LRCLK:
1353 case WM8995_FLL_SRC_BCLK:
1354 break;
1355 default:
1356 return -EINVAL;
1357 }
1358
1359 /* Are we changing anything? */
1360 if (wm8995->fll[id].src == src &&
1361 wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out)
1362 return 0;
1363
1364 /* If we're stopping the FLL redo the old config - no
1365 * registers will actually be written but we avoid GCC flow
1366 * analysis bugs spewing warnings.
1367 */
1368 if (freq_out)
1369 ret = wm8995_get_fll_config(&fll, freq_in, freq_out);
1370 else
1371 ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in,
1372 wm8995->fll[id].out);
1373 if (ret < 0)
1374 return ret;
1375
1376 /* Gate the AIF clocks while we reclock */
1377 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1,
1378 WM8995_AIF1CLK_ENA_MASK, 0);
1379 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1,
1380 WM8995_AIF2CLK_ENA_MASK, 0);
1381
1382 /* We always need to disable the FLL while reconfiguring */
1383 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset,
1384 WM8995_FLL1_ENA_MASK, 0);
1385
1386 reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) |
1387 (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT);
1388 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_2 + reg_offset,
1389 WM8995_FLL1_OUTDIV_MASK |
1390 WM8995_FLL1_FRATIO_MASK, reg);
1391
1392 snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k);
1393
1394 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_4 + reg_offset,
1395 WM8995_FLL1_N_MASK,
1396 fll.n << WM8995_FLL1_N_SHIFT);
1397
1398 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_5 + reg_offset,
1399 WM8995_FLL1_REFCLK_DIV_MASK |
1400 WM8995_FLL1_REFCLK_SRC_MASK,
1401 (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) |
1402 (src - 1));
1403
1404 if (freq_out)
1405 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset,
1406 WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA);
1407
1408 wm8995->fll[id].in = freq_in;
1409 wm8995->fll[id].out = freq_out;
1410 wm8995->fll[id].src = src;
1411
1412 /* Enable any gated AIF clocks */
1413 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1,
1414 WM8995_AIF1CLK_ENA_MASK, aif1);
1415 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1,
1416 WM8995_AIF2CLK_ENA_MASK, aif2);
1417
1418 configure_clock(codec);
1419
1420 return 0;
1421}
1422
1423static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai,
1424 int clk_id, unsigned int freq, int dir)
1425{
1426 struct snd_soc_codec *codec;
1427 struct wm8995_priv *wm8995;
1428
1429 codec = dai->codec;
1430 wm8995 = snd_soc_codec_get_drvdata(codec);
1431
1432 switch (dai->id) {
1433 case 0:
1434 case 1:
1435 break;
1436 default:
1437 /* AIF3 shares clocking with AIF1/2 */
1438 return -EINVAL;
1439 }
1440
1441 switch (clk_id) {
1442 case WM8995_SYSCLK_MCLK1:
1443 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1;
1444 wm8995->mclk[0] = freq;
1445 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1446 dai->id + 1, freq);
1447 break;
1448 case WM8995_SYSCLK_MCLK2:
1449 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1;
1450 wm8995->mclk[1] = freq;
1451 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1452 dai->id + 1, freq);
1453 break;
1454 case WM8995_SYSCLK_FLL1:
1455 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1;
1456 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1);
1457 break;
1458 case WM8995_SYSCLK_FLL2:
1459 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2;
1460 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1);
1461 break;
1462 case WM8995_SYSCLK_OPCLK:
1463 default:
1464 dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
1465 return -EINVAL;
1466 }
1467
1468 configure_clock(codec);
1469
1470 return 0;
1471}
1472
1473static int wm8995_set_bias_level(struct snd_soc_codec *codec,
1474 enum snd_soc_bias_level level)
1475{
1476 struct wm8995_priv *wm8995;
1477 int ret;
1478
1479 wm8995 = snd_soc_codec_get_drvdata(codec);
1480 switch (level) {
1481 case SND_SOC_BIAS_ON:
1482 case SND_SOC_BIAS_PREPARE:
1483 break;
1484 case SND_SOC_BIAS_STANDBY:
1485 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1486 ret = snd_soc_cache_sync(codec);
1487 if (ret) {
1488 dev_err(codec->dev,
1489 "Failed to sync cache: %d\n", ret);
1490 return ret;
1491 }
1492
1493 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
1494 WM8995_BG_ENA_MASK, WM8995_BG_ENA);
1495
1496 }
1497 break;
1498 case SND_SOC_BIAS_OFF:
1499 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1,
1500 WM8995_BG_ENA_MASK, 0);
1501 break;
1502 }
1503
1504 codec->dapm.bias_level = level;
1505 return 0;
1506}
1507
1508#ifdef CONFIG_PM
1509static int wm8995_suspend(struct snd_soc_codec *codec, pm_message_t state)
1510{
1511 wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF);
1512 return 0;
1513}
1514
1515static int wm8995_resume(struct snd_soc_codec *codec)
1516{
1517 wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1518 return 0;
1519}
1520#else
1521#define wm8995_suspend NULL
1522#define wm8995_resume NULL
1523#endif
1524
1525static int wm8995_remove(struct snd_soc_codec *codec)
1526{
1527 struct wm8995_priv *wm8995;
1528 struct i2c_client *i2c;
1529
1530 i2c = container_of(codec->dev, struct i2c_client, dev);
1531 wm8995 = snd_soc_codec_get_drvdata(codec);
1532 wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF);
1533 return 0;
1534}
1535
1536static int wm8995_probe(struct snd_soc_codec *codec)
1537{
1538 struct wm8995_priv *wm8995;
1539 int ret;
1540
1541 codec->dapm.idle_bias_off = 1;
1542 wm8995 = snd_soc_codec_get_drvdata(codec);
1543
1544 ret = snd_soc_codec_set_cache_io(codec, 16, 16, wm8995->control_type);
1545 if (ret < 0) {
1546 dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
1547 return ret;
1548 }
1549
1550 ret = snd_soc_read(codec, WM8995_SOFTWARE_RESET);
1551 if (ret < 0) {
1552 dev_err(codec->dev, "Failed to read device ID: %d\n", ret);
1553 return ret;
1554 }
1555
1556 if (ret != 0x8995) {
1557 dev_err(codec->dev, "Invalid device ID: %#x\n", ret);
1558 return -EINVAL;
1559 }
1560
1561 ret = snd_soc_write(codec, WM8995_SOFTWARE_RESET, 0);
1562 if (ret < 0) {
1563 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
1564 return ret;
1565 }
1566
1567 wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1568
1569 /* Latch volume updates (right only; we always do left then right). */
1570 snd_soc_update_bits(codec, WM8995_AIF1_DAC1_RIGHT_VOLUME,
1571 WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU);
1572 snd_soc_update_bits(codec, WM8995_AIF1_DAC2_RIGHT_VOLUME,
1573 WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU);
1574 snd_soc_update_bits(codec, WM8995_AIF2_DAC_RIGHT_VOLUME,
1575 WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU);
1576 snd_soc_update_bits(codec, WM8995_AIF1_ADC1_RIGHT_VOLUME,
1577 WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU);
1578 snd_soc_update_bits(codec, WM8995_AIF1_ADC2_RIGHT_VOLUME,
1579 WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU);
1580 snd_soc_update_bits(codec, WM8995_AIF2_ADC_RIGHT_VOLUME,
1581 WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU);
1582 snd_soc_update_bits(codec, WM8995_DAC1_RIGHT_VOLUME,
1583 WM8995_DAC1_VU_MASK, WM8995_DAC1_VU);
1584 snd_soc_update_bits(codec, WM8995_DAC2_RIGHT_VOLUME,
1585 WM8995_DAC2_VU_MASK, WM8995_DAC2_VU);
1586 snd_soc_update_bits(codec, WM8995_RIGHT_LINE_INPUT_1_VOLUME,
1587 WM8995_IN1_VU_MASK, WM8995_IN1_VU);
1588
1589 wm8995_update_class_w(codec);
1590
1591 snd_soc_add_controls(codec, wm8995_snd_controls,
1592 ARRAY_SIZE(wm8995_snd_controls));
1593 snd_soc_dapm_new_controls(&codec->dapm, wm8995_dapm_widgets,
1594 ARRAY_SIZE(wm8995_dapm_widgets));
1595 snd_soc_dapm_add_routes(&codec->dapm, wm8995_intercon,
1596 ARRAY_SIZE(wm8995_intercon));
1597
1598 return 0;
1599}
1600
1601#define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1602 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1603
1604static struct snd_soc_dai_ops wm8995_aif1_dai_ops = {
1605 .set_sysclk = wm8995_set_dai_sysclk,
1606 .set_fmt = wm8995_set_dai_fmt,
1607 .hw_params = wm8995_hw_params,
1608 .digital_mute = wm8995_aif_mute,
1609 .set_pll = wm8995_set_fll,
1610 .set_tristate = wm8995_set_tristate,
1611};
1612
1613static struct snd_soc_dai_ops wm8995_aif2_dai_ops = {
1614 .set_sysclk = wm8995_set_dai_sysclk,
1615 .set_fmt = wm8995_set_dai_fmt,
1616 .hw_params = wm8995_hw_params,
1617 .digital_mute = wm8995_aif_mute,
1618 .set_pll = wm8995_set_fll,
1619 .set_tristate = wm8995_set_tristate,
1620};
1621
1622static struct snd_soc_dai_ops wm8995_aif3_dai_ops = {
1623 .set_tristate = wm8995_set_tristate,
1624};
1625
1626static struct snd_soc_dai_driver wm8995_dai[] = {
1627 {
1628 .name = "wm8995-aif1",
1629 .playback = {
1630 .stream_name = "AIF1 Playback",
1631 .channels_min = 2,
1632 .channels_max = 2,
1633 .rates = SNDRV_PCM_RATE_8000_96000,
1634 .formats = WM8995_FORMATS
1635 },
1636 .capture = {
1637 .stream_name = "AIF1 Capture",
1638 .channels_min = 2,
1639 .channels_max = 2,
1640 .rates = SNDRV_PCM_RATE_8000_48000,
1641 .formats = WM8995_FORMATS
1642 },
1643 .ops = &wm8995_aif1_dai_ops
1644 },
1645 {
1646 .name = "wm8995-aif2",
1647 .playback = {
1648 .stream_name = "AIF2 Playback",
1649 .channels_min = 2,
1650 .channels_max = 2,
1651 .rates = SNDRV_PCM_RATE_8000_96000,
1652 .formats = WM8995_FORMATS
1653 },
1654 .capture = {
1655 .stream_name = "AIF2 Capture",
1656 .channels_min = 2,
1657 .channels_max = 2,
1658 .rates = SNDRV_PCM_RATE_8000_48000,
1659 .formats = WM8995_FORMATS
1660 },
1661 .ops = &wm8995_aif2_dai_ops
1662 },
1663 {
1664 .name = "wm8995-aif3",
1665 .playback = {
1666 .stream_name = "AIF3 Playback",
1667 .channels_min = 2,
1668 .channels_max = 2,
1669 .rates = SNDRV_PCM_RATE_8000_96000,
1670 .formats = WM8995_FORMATS
1671 },
1672 .capture = {
1673 .stream_name = "AIF3 Capture",
1674 .channels_min = 2,
1675 .channels_max = 2,
1676 .rates = SNDRV_PCM_RATE_8000_48000,
1677 .formats = WM8995_FORMATS
1678 },
1679 .ops = &wm8995_aif3_dai_ops
1680 }
1681};
1682
1683static struct snd_soc_codec_driver soc_codec_dev_wm8995 = {
1684 .probe = wm8995_probe,
1685 .remove = wm8995_remove,
1686 .suspend = wm8995_suspend,
1687 .resume = wm8995_resume,
1688 .set_bias_level = wm8995_set_bias_level,
1689 .reg_cache_size = ARRAY_SIZE(wm8995_reg_defs),
1690 .reg_word_size = sizeof(u16),
1691 .reg_cache_default = wm8995_reg_defs,
1692 .volatile_register = wm8995_volatile,
1693 .compress_type = SND_SOC_RBTREE_COMPRESSION
1694};
1695
1696#if defined(CONFIG_SPI_MASTER)
1697static int __devinit wm8995_spi_probe(struct spi_device *spi)
1698{
1699 struct wm8995_priv *wm8995;
1700 int ret;
1701
1702 wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL);
1703 if (!wm8995)
1704 return -ENOMEM;
1705
1706 wm8995->control_type = SND_SOC_SPI;
1707 spi_set_drvdata(spi, wm8995);
1708
1709 ret = snd_soc_register_codec(&spi->dev,
1710 &soc_codec_dev_wm8995, wm8995_dai,
1711 ARRAY_SIZE(wm8995_dai));
1712 if (ret < 0)
1713 kfree(wm8995);
1714 return ret;
1715}
1716
1717static int __devexit wm8995_spi_remove(struct spi_device *spi)
1718{
1719 snd_soc_unregister_codec(&spi->dev);
1720 kfree(spi_get_drvdata(spi));
1721 return 0;
1722}
1723
1724static struct spi_driver wm8995_spi_driver = {
1725 .driver = {
1726 .name = "wm8995",
1727 .owner = THIS_MODULE,
1728 },
1729 .probe = wm8995_spi_probe,
1730 .remove = __devexit_p(wm8995_spi_remove)
1731};
1732#endif
1733
1734#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1735static __devinit int wm8995_i2c_probe(struct i2c_client *i2c,
1736 const struct i2c_device_id *id)
1737{
1738 struct wm8995_priv *wm8995;
1739 int ret;
1740
1741 wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL);
1742 if (!wm8995)
1743 return -ENOMEM;
1744
1745 wm8995->control_type = SND_SOC_I2C;
1746 i2c_set_clientdata(i2c, wm8995);
1747
1748 ret = snd_soc_register_codec(&i2c->dev,
1749 &soc_codec_dev_wm8995, wm8995_dai,
1750 ARRAY_SIZE(wm8995_dai));
1751 if (ret < 0)
1752 kfree(wm8995);
1753 return ret;
1754}
1755
1756static __devexit int wm8995_i2c_remove(struct i2c_client *client)
1757{
1758 snd_soc_unregister_codec(&client->dev);
1759 kfree(i2c_get_clientdata(client));
1760 return 0;
1761}
1762
1763static const struct i2c_device_id wm8995_i2c_id[] = {
1764 {"wm8995", 0},
1765 {}
1766};
1767
1768MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id);
1769
1770static struct i2c_driver wm8995_i2c_driver = {
1771 .driver = {
1772 .name = "wm8995",
1773 .owner = THIS_MODULE,
1774 },
1775 .probe = wm8995_i2c_probe,
1776 .remove = __devexit_p(wm8995_i2c_remove),
1777 .id_table = wm8995_i2c_id
1778};
1779#endif
1780
1781static int __init wm8995_modinit(void)
1782{
1783 int ret = 0;
1784
1785#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1786 ret = i2c_add_driver(&wm8995_i2c_driver);
1787 if (ret) {
1788 printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n",
1789 ret);
1790 }
1791#endif
1792#if defined(CONFIG_SPI_MASTER)
1793 ret = spi_register_driver(&wm8995_spi_driver);
1794 if (ret) {
1795 printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n",
1796 ret);
1797 }
1798#endif
1799 return ret;
1800}
1801
1802module_init(wm8995_modinit);
1803
1804static void __exit wm8995_exit(void)
1805{
1806#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1807 i2c_del_driver(&wm8995_i2c_driver);
1808#endif
1809#if defined(CONFIG_SPI_MASTER)
1810 spi_unregister_driver(&wm8995_spi_driver);
1811#endif
1812}
1813
1814module_exit(wm8995_exit);
1815
1816MODULE_DESCRIPTION("ASoC WM8995 driver");
1817MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
1818MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8995.h b/sound/soc/codecs/wm8995.h
new file mode 100644
index 000000000000..5642121c4977
--- /dev/null
+++ b/sound/soc/codecs/wm8995.h
@@ -0,0 +1,4269 @@
1/*
2 * wm8995.h -- WM8995 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef _WM8995_H
14#define _WM8995_H
15
16#include <asm/types.h>
17
18/*
19 * Register values.
20 */
21#define WM8995_SOFTWARE_RESET 0x00
22#define WM8995_POWER_MANAGEMENT_1 0x01
23#define WM8995_POWER_MANAGEMENT_2 0x02
24#define WM8995_POWER_MANAGEMENT_3 0x03
25#define WM8995_POWER_MANAGEMENT_4 0x04
26#define WM8995_POWER_MANAGEMENT_5 0x05
27#define WM8995_LEFT_LINE_INPUT_1_VOLUME 0x10
28#define WM8995_RIGHT_LINE_INPUT_1_VOLUME 0x11
29#define WM8995_LEFT_LINE_INPUT_CONTROL 0x12
30#define WM8995_DAC1_LEFT_VOLUME 0x18
31#define WM8995_DAC1_RIGHT_VOLUME 0x19
32#define WM8995_DAC2_LEFT_VOLUME 0x1A
33#define WM8995_DAC2_RIGHT_VOLUME 0x1B
34#define WM8995_OUTPUT_VOLUME_ZC_1 0x1C
35#define WM8995_MICBIAS_1 0x20
36#define WM8995_MICBIAS_2 0x21
37#define WM8995_LDO_1 0x28
38#define WM8995_LDO_2 0x29
39#define WM8995_ACCESSORY_DETECT_MODE1 0x30
40#define WM8995_ACCESSORY_DETECT_MODE2 0x31
41#define WM8995_HEADPHONE_DETECT1 0x34
42#define WM8995_HEADPHONE_DETECT2 0x35
43#define WM8995_MIC_DETECT_1 0x38
44#define WM8995_MIC_DETECT_2 0x39
45#define WM8995_CHARGE_PUMP_1 0x40
46#define WM8995_CLASS_W_1 0x45
47#define WM8995_DC_SERVO_1 0x50
48#define WM8995_DC_SERVO_2 0x51
49#define WM8995_DC_SERVO_3 0x52
50#define WM8995_DC_SERVO_5 0x54
51#define WM8995_DC_SERVO_6 0x55
52#define WM8995_DC_SERVO_7 0x56
53#define WM8995_DC_SERVO_READBACK_0 0x57
54#define WM8995_ANALOGUE_HP_1 0x60
55#define WM8995_ANALOGUE_HP_2 0x61
56#define WM8995_CHIP_REVISION 0x100
57#define WM8995_CONTROL_INTERFACE_1 0x101
58#define WM8995_CONTROL_INTERFACE_2 0x102
59#define WM8995_WRITE_SEQUENCER_CTRL_1 0x110
60#define WM8995_WRITE_SEQUENCER_CTRL_2 0x111
61#define WM8995_AIF1_CLOCKING_1 0x200
62#define WM8995_AIF1_CLOCKING_2 0x201
63#define WM8995_AIF2_CLOCKING_1 0x204
64#define WM8995_AIF2_CLOCKING_2 0x205
65#define WM8995_CLOCKING_1 0x208
66#define WM8995_CLOCKING_2 0x209
67#define WM8995_AIF1_RATE 0x210
68#define WM8995_AIF2_RATE 0x211
69#define WM8995_RATE_STATUS 0x212
70#define WM8995_FLL1_CONTROL_1 0x220
71#define WM8995_FLL1_CONTROL_2 0x221
72#define WM8995_FLL1_CONTROL_3 0x222
73#define WM8995_FLL1_CONTROL_4 0x223
74#define WM8995_FLL1_CONTROL_5 0x224
75#define WM8995_FLL2_CONTROL_1 0x240
76#define WM8995_FLL2_CONTROL_2 0x241
77#define WM8995_FLL2_CONTROL_3 0x242
78#define WM8995_FLL2_CONTROL_4 0x243
79#define WM8995_FLL2_CONTROL_5 0x244
80#define WM8995_AIF1_CONTROL_1 0x300
81#define WM8995_AIF1_CONTROL_2 0x301
82#define WM8995_AIF1_MASTER_SLAVE 0x302
83#define WM8995_AIF1_BCLK 0x303
84#define WM8995_AIF1ADC_LRCLK 0x304
85#define WM8995_AIF1DAC_LRCLK 0x305
86#define WM8995_AIF1DAC_DATA 0x306
87#define WM8995_AIF1ADC_DATA 0x307
88#define WM8995_AIF2_CONTROL_1 0x310
89#define WM8995_AIF2_CONTROL_2 0x311
90#define WM8995_AIF2_MASTER_SLAVE 0x312
91#define WM8995_AIF2_BCLK 0x313
92#define WM8995_AIF2ADC_LRCLK 0x314
93#define WM8995_AIF2DAC_LRCLK 0x315
94#define WM8995_AIF2DAC_DATA 0x316
95#define WM8995_AIF2ADC_DATA 0x317
96#define WM8995_AIF1_ADC1_LEFT_VOLUME 0x400
97#define WM8995_AIF1_ADC1_RIGHT_VOLUME 0x401
98#define WM8995_AIF1_DAC1_LEFT_VOLUME 0x402
99#define WM8995_AIF1_DAC1_RIGHT_VOLUME 0x403
100#define WM8995_AIF1_ADC2_LEFT_VOLUME 0x404
101#define WM8995_AIF1_ADC2_RIGHT_VOLUME 0x405
102#define WM8995_AIF1_DAC2_LEFT_VOLUME 0x406
103#define WM8995_AIF1_DAC2_RIGHT_VOLUME 0x407
104#define WM8995_AIF1_ADC1_FILTERS 0x410
105#define WM8995_AIF1_ADC2_FILTERS 0x411
106#define WM8995_AIF1_DAC1_FILTERS_1 0x420
107#define WM8995_AIF1_DAC1_FILTERS_2 0x421
108#define WM8995_AIF1_DAC2_FILTERS_1 0x422
109#define WM8995_AIF1_DAC2_FILTERS_2 0x423
110#define WM8995_AIF1_DRC1_1 0x440
111#define WM8995_AIF1_DRC1_2 0x441
112#define WM8995_AIF1_DRC1_3 0x442
113#define WM8995_AIF1_DRC1_4 0x443
114#define WM8995_AIF1_DRC1_5 0x444
115#define WM8995_AIF1_DRC2_1 0x450
116#define WM8995_AIF1_DRC2_2 0x451
117#define WM8995_AIF1_DRC2_3 0x452
118#define WM8995_AIF1_DRC2_4 0x453
119#define WM8995_AIF1_DRC2_5 0x454
120#define WM8995_AIF1_DAC1_EQ_GAINS_1 0x480
121#define WM8995_AIF1_DAC1_EQ_GAINS_2 0x481
122#define WM8995_AIF1_DAC1_EQ_BAND_1_A 0x482
123#define WM8995_AIF1_DAC1_EQ_BAND_1_B 0x483
124#define WM8995_AIF1_DAC1_EQ_BAND_1_PG 0x484
125#define WM8995_AIF1_DAC1_EQ_BAND_2_A 0x485
126#define WM8995_AIF1_DAC1_EQ_BAND_2_B 0x486
127#define WM8995_AIF1_DAC1_EQ_BAND_2_C 0x487
128#define WM8995_AIF1_DAC1_EQ_BAND_2_PG 0x488
129#define WM8995_AIF1_DAC1_EQ_BAND_3_A 0x489
130#define WM8995_AIF1_DAC1_EQ_BAND_3_B 0x48A
131#define WM8995_AIF1_DAC1_EQ_BAND_3_C 0x48B
132#define WM8995_AIF1_DAC1_EQ_BAND_3_PG 0x48C
133#define WM8995_AIF1_DAC1_EQ_BAND_4_A 0x48D
134#define WM8995_AIF1_DAC1_EQ_BAND_4_B 0x48E
135#define WM8995_AIF1_DAC1_EQ_BAND_4_C 0x48F
136#define WM8995_AIF1_DAC1_EQ_BAND_4_PG 0x490
137#define WM8995_AIF1_DAC1_EQ_BAND_5_A 0x491
138#define WM8995_AIF1_DAC1_EQ_BAND_5_B 0x492
139#define WM8995_AIF1_DAC1_EQ_BAND_5_PG 0x493
140#define WM8995_AIF1_DAC2_EQ_GAINS_1 0x4A0
141#define WM8995_AIF1_DAC2_EQ_GAINS_2 0x4A1
142#define WM8995_AIF1_DAC2_EQ_BAND_1_A 0x4A2
143#define WM8995_AIF1_DAC2_EQ_BAND_1_B 0x4A3
144#define WM8995_AIF1_DAC2_EQ_BAND_1_PG 0x4A4
145#define WM8995_AIF1_DAC2_EQ_BAND_2_A 0x4A5
146#define WM8995_AIF1_DAC2_EQ_BAND_2_B 0x4A6
147#define WM8995_AIF1_DAC2_EQ_BAND_2_C 0x4A7
148#define WM8995_AIF1_DAC2_EQ_BAND_2_PG 0x4A8
149#define WM8995_AIF1_DAC2_EQ_BAND_3_A 0x4A9
150#define WM8995_AIF1_DAC2_EQ_BAND_3_B 0x4AA
151#define WM8995_AIF1_DAC2_EQ_BAND_3_C 0x4AB
152#define WM8995_AIF1_DAC2_EQ_BAND_3_PG 0x4AC
153#define WM8995_AIF1_DAC2_EQ_BAND_4_A 0x4AD
154#define WM8995_AIF1_DAC2_EQ_BAND_4_B 0x4AE
155#define WM8995_AIF1_DAC2_EQ_BAND_4_C 0x4AF
156#define WM8995_AIF1_DAC2_EQ_BAND_4_PG 0x4B0
157#define WM8995_AIF1_DAC2_EQ_BAND_5_A 0x4B1
158#define WM8995_AIF1_DAC2_EQ_BAND_5_B 0x4B2
159#define WM8995_AIF1_DAC2_EQ_BAND_5_PG 0x4B3
160#define WM8995_AIF2_ADC_LEFT_VOLUME 0x500
161#define WM8995_AIF2_ADC_RIGHT_VOLUME 0x501
162#define WM8995_AIF2_DAC_LEFT_VOLUME 0x502
163#define WM8995_AIF2_DAC_RIGHT_VOLUME 0x503
164#define WM8995_AIF2_ADC_FILTERS 0x510
165#define WM8995_AIF2_DAC_FILTERS_1 0x520
166#define WM8995_AIF2_DAC_FILTERS_2 0x521
167#define WM8995_AIF2_DRC_1 0x540
168#define WM8995_AIF2_DRC_2 0x541
169#define WM8995_AIF2_DRC_3 0x542
170#define WM8995_AIF2_DRC_4 0x543
171#define WM8995_AIF2_DRC_5 0x544
172#define WM8995_AIF2_EQ_GAINS_1 0x580
173#define WM8995_AIF2_EQ_GAINS_2 0x581
174#define WM8995_AIF2_EQ_BAND_1_A 0x582
175#define WM8995_AIF2_EQ_BAND_1_B 0x583
176#define WM8995_AIF2_EQ_BAND_1_PG 0x584
177#define WM8995_AIF2_EQ_BAND_2_A 0x585
178#define WM8995_AIF2_EQ_BAND_2_B 0x586
179#define WM8995_AIF2_EQ_BAND_2_C 0x587
180#define WM8995_AIF2_EQ_BAND_2_PG 0x588
181#define WM8995_AIF2_EQ_BAND_3_A 0x589
182#define WM8995_AIF2_EQ_BAND_3_B 0x58A
183#define WM8995_AIF2_EQ_BAND_3_C 0x58B
184#define WM8995_AIF2_EQ_BAND_3_PG 0x58C
185#define WM8995_AIF2_EQ_BAND_4_A 0x58D
186#define WM8995_AIF2_EQ_BAND_4_B 0x58E
187#define WM8995_AIF2_EQ_BAND_4_C 0x58F
188#define WM8995_AIF2_EQ_BAND_4_PG 0x590
189#define WM8995_AIF2_EQ_BAND_5_A 0x591
190#define WM8995_AIF2_EQ_BAND_5_B 0x592
191#define WM8995_AIF2_EQ_BAND_5_PG 0x593
192#define WM8995_DAC1_MIXER_VOLUMES 0x600
193#define WM8995_DAC1_LEFT_MIXER_ROUTING 0x601
194#define WM8995_DAC1_RIGHT_MIXER_ROUTING 0x602
195#define WM8995_DAC2_MIXER_VOLUMES 0x603
196#define WM8995_DAC2_LEFT_MIXER_ROUTING 0x604
197#define WM8995_DAC2_RIGHT_MIXER_ROUTING 0x605
198#define WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING 0x606
199#define WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING 0x607
200#define WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING 0x608
201#define WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING 0x609
202#define WM8995_DAC_SOFTMUTE 0x610
203#define WM8995_OVERSAMPLING 0x620
204#define WM8995_SIDETONE 0x621
205#define WM8995_GPIO_1 0x700
206#define WM8995_GPIO_2 0x701
207#define WM8995_GPIO_3 0x702
208#define WM8995_GPIO_4 0x703
209#define WM8995_GPIO_5 0x704
210#define WM8995_GPIO_6 0x705
211#define WM8995_GPIO_7 0x706
212#define WM8995_GPIO_8 0x707
213#define WM8995_GPIO_9 0x708
214#define WM8995_GPIO_10 0x709
215#define WM8995_GPIO_11 0x70A
216#define WM8995_GPIO_12 0x70B
217#define WM8995_GPIO_13 0x70C
218#define WM8995_GPIO_14 0x70D
219#define WM8995_PULL_CONTROL_1 0x720
220#define WM8995_PULL_CONTROL_2 0x721
221#define WM8995_INTERRUPT_STATUS_1 0x730
222#define WM8995_INTERRUPT_STATUS_2 0x731
223#define WM8995_INTERRUPT_RAW_STATUS_2 0x732
224#define WM8995_INTERRUPT_STATUS_1_MASK 0x738
225#define WM8995_INTERRUPT_STATUS_2_MASK 0x739
226#define WM8995_INTERRUPT_CONTROL 0x740
227#define WM8995_LEFT_PDM_SPEAKER_1 0x800
228#define WM8995_RIGHT_PDM_SPEAKER_1 0x801
229#define WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE 0x802
230#define WM8995_LEFT_PDM_SPEAKER_2 0x808
231#define WM8995_RIGHT_PDM_SPEAKER_2 0x809
232#define WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE 0x80A
233#define WM8995_WRITE_SEQUENCER_0 0x3000
234#define WM8995_WRITE_SEQUENCER_1 0x3001
235#define WM8995_WRITE_SEQUENCER_2 0x3002
236#define WM8995_WRITE_SEQUENCER_3 0x3003
237#define WM8995_WRITE_SEQUENCER_4 0x3004
238#define WM8995_WRITE_SEQUENCER_5 0x3005
239#define WM8995_WRITE_SEQUENCER_6 0x3006
240#define WM8995_WRITE_SEQUENCER_7 0x3007
241#define WM8995_WRITE_SEQUENCER_8 0x3008
242#define WM8995_WRITE_SEQUENCER_9 0x3009
243#define WM8995_WRITE_SEQUENCER_10 0x300A
244#define WM8995_WRITE_SEQUENCER_11 0x300B
245#define WM8995_WRITE_SEQUENCER_12 0x300C
246#define WM8995_WRITE_SEQUENCER_13 0x300D
247#define WM8995_WRITE_SEQUENCER_14 0x300E
248#define WM8995_WRITE_SEQUENCER_15 0x300F
249#define WM8995_WRITE_SEQUENCER_16 0x3010
250#define WM8995_WRITE_SEQUENCER_17 0x3011
251#define WM8995_WRITE_SEQUENCER_18 0x3012
252#define WM8995_WRITE_SEQUENCER_19 0x3013
253#define WM8995_WRITE_SEQUENCER_20 0x3014
254#define WM8995_WRITE_SEQUENCER_21 0x3015
255#define WM8995_WRITE_SEQUENCER_22 0x3016
256#define WM8995_WRITE_SEQUENCER_23 0x3017
257#define WM8995_WRITE_SEQUENCER_24 0x3018
258#define WM8995_WRITE_SEQUENCER_25 0x3019
259#define WM8995_WRITE_SEQUENCER_26 0x301A
260#define WM8995_WRITE_SEQUENCER_27 0x301B
261#define WM8995_WRITE_SEQUENCER_28 0x301C
262#define WM8995_WRITE_SEQUENCER_29 0x301D
263#define WM8995_WRITE_SEQUENCER_30 0x301E
264#define WM8995_WRITE_SEQUENCER_31 0x301F
265#define WM8995_WRITE_SEQUENCER_32 0x3020
266#define WM8995_WRITE_SEQUENCER_33 0x3021
267#define WM8995_WRITE_SEQUENCER_34 0x3022
268#define WM8995_WRITE_SEQUENCER_35 0x3023
269#define WM8995_WRITE_SEQUENCER_36 0x3024
270#define WM8995_WRITE_SEQUENCER_37 0x3025
271#define WM8995_WRITE_SEQUENCER_38 0x3026
272#define WM8995_WRITE_SEQUENCER_39 0x3027
273#define WM8995_WRITE_SEQUENCER_40 0x3028
274#define WM8995_WRITE_SEQUENCER_41 0x3029
275#define WM8995_WRITE_SEQUENCER_42 0x302A
276#define WM8995_WRITE_SEQUENCER_43 0x302B
277#define WM8995_WRITE_SEQUENCER_44 0x302C
278#define WM8995_WRITE_SEQUENCER_45 0x302D
279#define WM8995_WRITE_SEQUENCER_46 0x302E
280#define WM8995_WRITE_SEQUENCER_47 0x302F
281#define WM8995_WRITE_SEQUENCER_48 0x3030
282#define WM8995_WRITE_SEQUENCER_49 0x3031
283#define WM8995_WRITE_SEQUENCER_50 0x3032
284#define WM8995_WRITE_SEQUENCER_51 0x3033
285#define WM8995_WRITE_SEQUENCER_52 0x3034
286#define WM8995_WRITE_SEQUENCER_53 0x3035
287#define WM8995_WRITE_SEQUENCER_54 0x3036
288#define WM8995_WRITE_SEQUENCER_55 0x3037
289#define WM8995_WRITE_SEQUENCER_56 0x3038
290#define WM8995_WRITE_SEQUENCER_57 0x3039
291#define WM8995_WRITE_SEQUENCER_58 0x303A
292#define WM8995_WRITE_SEQUENCER_59 0x303B
293#define WM8995_WRITE_SEQUENCER_60 0x303C
294#define WM8995_WRITE_SEQUENCER_61 0x303D
295#define WM8995_WRITE_SEQUENCER_62 0x303E
296#define WM8995_WRITE_SEQUENCER_63 0x303F
297#define WM8995_WRITE_SEQUENCER_64 0x3040
298#define WM8995_WRITE_SEQUENCER_65 0x3041
299#define WM8995_WRITE_SEQUENCER_66 0x3042
300#define WM8995_WRITE_SEQUENCER_67 0x3043
301#define WM8995_WRITE_SEQUENCER_68 0x3044
302#define WM8995_WRITE_SEQUENCER_69 0x3045
303#define WM8995_WRITE_SEQUENCER_70 0x3046
304#define WM8995_WRITE_SEQUENCER_71 0x3047
305#define WM8995_WRITE_SEQUENCER_72 0x3048
306#define WM8995_WRITE_SEQUENCER_73 0x3049
307#define WM8995_WRITE_SEQUENCER_74 0x304A
308#define WM8995_WRITE_SEQUENCER_75 0x304B
309#define WM8995_WRITE_SEQUENCER_76 0x304C
310#define WM8995_WRITE_SEQUENCER_77 0x304D
311#define WM8995_WRITE_SEQUENCER_78 0x304E
312#define WM8995_WRITE_SEQUENCER_79 0x304F
313#define WM8995_WRITE_SEQUENCER_80 0x3050
314#define WM8995_WRITE_SEQUENCER_81 0x3051
315#define WM8995_WRITE_SEQUENCER_82 0x3052
316#define WM8995_WRITE_SEQUENCER_83 0x3053
317#define WM8995_WRITE_SEQUENCER_84 0x3054
318#define WM8995_WRITE_SEQUENCER_85 0x3055
319#define WM8995_WRITE_SEQUENCER_86 0x3056
320#define WM8995_WRITE_SEQUENCER_87 0x3057
321#define WM8995_WRITE_SEQUENCER_88 0x3058
322#define WM8995_WRITE_SEQUENCER_89 0x3059
323#define WM8995_WRITE_SEQUENCER_90 0x305A
324#define WM8995_WRITE_SEQUENCER_91 0x305B
325#define WM8995_WRITE_SEQUENCER_92 0x305C
326#define WM8995_WRITE_SEQUENCER_93 0x305D
327#define WM8995_WRITE_SEQUENCER_94 0x305E
328#define WM8995_WRITE_SEQUENCER_95 0x305F
329#define WM8995_WRITE_SEQUENCER_96 0x3060
330#define WM8995_WRITE_SEQUENCER_97 0x3061
331#define WM8995_WRITE_SEQUENCER_98 0x3062
332#define WM8995_WRITE_SEQUENCER_99 0x3063
333#define WM8995_WRITE_SEQUENCER_100 0x3064
334#define WM8995_WRITE_SEQUENCER_101 0x3065
335#define WM8995_WRITE_SEQUENCER_102 0x3066
336#define WM8995_WRITE_SEQUENCER_103 0x3067
337#define WM8995_WRITE_SEQUENCER_104 0x3068
338#define WM8995_WRITE_SEQUENCER_105 0x3069
339#define WM8995_WRITE_SEQUENCER_106 0x306A
340#define WM8995_WRITE_SEQUENCER_107 0x306B
341#define WM8995_WRITE_SEQUENCER_108 0x306C
342#define WM8995_WRITE_SEQUENCER_109 0x306D
343#define WM8995_WRITE_SEQUENCER_110 0x306E
344#define WM8995_WRITE_SEQUENCER_111 0x306F
345#define WM8995_WRITE_SEQUENCER_112 0x3070
346#define WM8995_WRITE_SEQUENCER_113 0x3071
347#define WM8995_WRITE_SEQUENCER_114 0x3072
348#define WM8995_WRITE_SEQUENCER_115 0x3073
349#define WM8995_WRITE_SEQUENCER_116 0x3074
350#define WM8995_WRITE_SEQUENCER_117 0x3075
351#define WM8995_WRITE_SEQUENCER_118 0x3076
352#define WM8995_WRITE_SEQUENCER_119 0x3077
353#define WM8995_WRITE_SEQUENCER_120 0x3078
354#define WM8995_WRITE_SEQUENCER_121 0x3079
355#define WM8995_WRITE_SEQUENCER_122 0x307A
356#define WM8995_WRITE_SEQUENCER_123 0x307B
357#define WM8995_WRITE_SEQUENCER_124 0x307C
358#define WM8995_WRITE_SEQUENCER_125 0x307D
359#define WM8995_WRITE_SEQUENCER_126 0x307E
360#define WM8995_WRITE_SEQUENCER_127 0x307F
361#define WM8995_WRITE_SEQUENCER_128 0x3080
362#define WM8995_WRITE_SEQUENCER_129 0x3081
363#define WM8995_WRITE_SEQUENCER_130 0x3082
364#define WM8995_WRITE_SEQUENCER_131 0x3083
365#define WM8995_WRITE_SEQUENCER_132 0x3084
366#define WM8995_WRITE_SEQUENCER_133 0x3085
367#define WM8995_WRITE_SEQUENCER_134 0x3086
368#define WM8995_WRITE_SEQUENCER_135 0x3087
369#define WM8995_WRITE_SEQUENCER_136 0x3088
370#define WM8995_WRITE_SEQUENCER_137 0x3089
371#define WM8995_WRITE_SEQUENCER_138 0x308A
372#define WM8995_WRITE_SEQUENCER_139 0x308B
373#define WM8995_WRITE_SEQUENCER_140 0x308C
374#define WM8995_WRITE_SEQUENCER_141 0x308D
375#define WM8995_WRITE_SEQUENCER_142 0x308E
376#define WM8995_WRITE_SEQUENCER_143 0x308F
377#define WM8995_WRITE_SEQUENCER_144 0x3090
378#define WM8995_WRITE_SEQUENCER_145 0x3091
379#define WM8995_WRITE_SEQUENCER_146 0x3092
380#define WM8995_WRITE_SEQUENCER_147 0x3093
381#define WM8995_WRITE_SEQUENCER_148 0x3094
382#define WM8995_WRITE_SEQUENCER_149 0x3095
383#define WM8995_WRITE_SEQUENCER_150 0x3096
384#define WM8995_WRITE_SEQUENCER_151 0x3097
385#define WM8995_WRITE_SEQUENCER_152 0x3098
386#define WM8995_WRITE_SEQUENCER_153 0x3099
387#define WM8995_WRITE_SEQUENCER_154 0x309A
388#define WM8995_WRITE_SEQUENCER_155 0x309B
389#define WM8995_WRITE_SEQUENCER_156 0x309C
390#define WM8995_WRITE_SEQUENCER_157 0x309D
391#define WM8995_WRITE_SEQUENCER_158 0x309E
392#define WM8995_WRITE_SEQUENCER_159 0x309F
393#define WM8995_WRITE_SEQUENCER_160 0x30A0
394#define WM8995_WRITE_SEQUENCER_161 0x30A1
395#define WM8995_WRITE_SEQUENCER_162 0x30A2
396#define WM8995_WRITE_SEQUENCER_163 0x30A3
397#define WM8995_WRITE_SEQUENCER_164 0x30A4
398#define WM8995_WRITE_SEQUENCER_165 0x30A5
399#define WM8995_WRITE_SEQUENCER_166 0x30A6
400#define WM8995_WRITE_SEQUENCER_167 0x30A7
401#define WM8995_WRITE_SEQUENCER_168 0x30A8
402#define WM8995_WRITE_SEQUENCER_169 0x30A9
403#define WM8995_WRITE_SEQUENCER_170 0x30AA
404#define WM8995_WRITE_SEQUENCER_171 0x30AB
405#define WM8995_WRITE_SEQUENCER_172 0x30AC
406#define WM8995_WRITE_SEQUENCER_173 0x30AD
407#define WM8995_WRITE_SEQUENCER_174 0x30AE
408#define WM8995_WRITE_SEQUENCER_175 0x30AF
409#define WM8995_WRITE_SEQUENCER_176 0x30B0
410#define WM8995_WRITE_SEQUENCER_177 0x30B1
411#define WM8995_WRITE_SEQUENCER_178 0x30B2
412#define WM8995_WRITE_SEQUENCER_179 0x30B3
413#define WM8995_WRITE_SEQUENCER_180 0x30B4
414#define WM8995_WRITE_SEQUENCER_181 0x30B5
415#define WM8995_WRITE_SEQUENCER_182 0x30B6
416#define WM8995_WRITE_SEQUENCER_183 0x30B7
417#define WM8995_WRITE_SEQUENCER_184 0x30B8
418#define WM8995_WRITE_SEQUENCER_185 0x30B9
419#define WM8995_WRITE_SEQUENCER_186 0x30BA
420#define WM8995_WRITE_SEQUENCER_187 0x30BB
421#define WM8995_WRITE_SEQUENCER_188 0x30BC
422#define WM8995_WRITE_SEQUENCER_189 0x30BD
423#define WM8995_WRITE_SEQUENCER_190 0x30BE
424#define WM8995_WRITE_SEQUENCER_191 0x30BF
425#define WM8995_WRITE_SEQUENCER_192 0x30C0
426#define WM8995_WRITE_SEQUENCER_193 0x30C1
427#define WM8995_WRITE_SEQUENCER_194 0x30C2
428#define WM8995_WRITE_SEQUENCER_195 0x30C3
429#define WM8995_WRITE_SEQUENCER_196 0x30C4
430#define WM8995_WRITE_SEQUENCER_197 0x30C5
431#define WM8995_WRITE_SEQUENCER_198 0x30C6
432#define WM8995_WRITE_SEQUENCER_199 0x30C7
433#define WM8995_WRITE_SEQUENCER_200 0x30C8
434#define WM8995_WRITE_SEQUENCER_201 0x30C9
435#define WM8995_WRITE_SEQUENCER_202 0x30CA
436#define WM8995_WRITE_SEQUENCER_203 0x30CB
437#define WM8995_WRITE_SEQUENCER_204 0x30CC
438#define WM8995_WRITE_SEQUENCER_205 0x30CD
439#define WM8995_WRITE_SEQUENCER_206 0x30CE
440#define WM8995_WRITE_SEQUENCER_207 0x30CF
441#define WM8995_WRITE_SEQUENCER_208 0x30D0
442#define WM8995_WRITE_SEQUENCER_209 0x30D1
443#define WM8995_WRITE_SEQUENCER_210 0x30D2
444#define WM8995_WRITE_SEQUENCER_211 0x30D3
445#define WM8995_WRITE_SEQUENCER_212 0x30D4
446#define WM8995_WRITE_SEQUENCER_213 0x30D5
447#define WM8995_WRITE_SEQUENCER_214 0x30D6
448#define WM8995_WRITE_SEQUENCER_215 0x30D7
449#define WM8995_WRITE_SEQUENCER_216 0x30D8
450#define WM8995_WRITE_SEQUENCER_217 0x30D9
451#define WM8995_WRITE_SEQUENCER_218 0x30DA
452#define WM8995_WRITE_SEQUENCER_219 0x30DB
453#define WM8995_WRITE_SEQUENCER_220 0x30DC
454#define WM8995_WRITE_SEQUENCER_221 0x30DD
455#define WM8995_WRITE_SEQUENCER_222 0x30DE
456#define WM8995_WRITE_SEQUENCER_223 0x30DF
457#define WM8995_WRITE_SEQUENCER_224 0x30E0
458#define WM8995_WRITE_SEQUENCER_225 0x30E1
459#define WM8995_WRITE_SEQUENCER_226 0x30E2
460#define WM8995_WRITE_SEQUENCER_227 0x30E3
461#define WM8995_WRITE_SEQUENCER_228 0x30E4
462#define WM8995_WRITE_SEQUENCER_229 0x30E5
463#define WM8995_WRITE_SEQUENCER_230 0x30E6
464#define WM8995_WRITE_SEQUENCER_231 0x30E7
465#define WM8995_WRITE_SEQUENCER_232 0x30E8
466#define WM8995_WRITE_SEQUENCER_233 0x30E9
467#define WM8995_WRITE_SEQUENCER_234 0x30EA
468#define WM8995_WRITE_SEQUENCER_235 0x30EB
469#define WM8995_WRITE_SEQUENCER_236 0x30EC
470#define WM8995_WRITE_SEQUENCER_237 0x30ED
471#define WM8995_WRITE_SEQUENCER_238 0x30EE
472#define WM8995_WRITE_SEQUENCER_239 0x30EF
473#define WM8995_WRITE_SEQUENCER_240 0x30F0
474#define WM8995_WRITE_SEQUENCER_241 0x30F1
475#define WM8995_WRITE_SEQUENCER_242 0x30F2
476#define WM8995_WRITE_SEQUENCER_243 0x30F3
477#define WM8995_WRITE_SEQUENCER_244 0x30F4
478#define WM8995_WRITE_SEQUENCER_245 0x30F5
479#define WM8995_WRITE_SEQUENCER_246 0x30F6
480#define WM8995_WRITE_SEQUENCER_247 0x30F7
481#define WM8995_WRITE_SEQUENCER_248 0x30F8
482#define WM8995_WRITE_SEQUENCER_249 0x30F9
483#define WM8995_WRITE_SEQUENCER_250 0x30FA
484#define WM8995_WRITE_SEQUENCER_251 0x30FB
485#define WM8995_WRITE_SEQUENCER_252 0x30FC
486#define WM8995_WRITE_SEQUENCER_253 0x30FD
487#define WM8995_WRITE_SEQUENCER_254 0x30FE
488#define WM8995_WRITE_SEQUENCER_255 0x30FF
489#define WM8995_WRITE_SEQUENCER_256 0x3100
490#define WM8995_WRITE_SEQUENCER_257 0x3101
491#define WM8995_WRITE_SEQUENCER_258 0x3102
492#define WM8995_WRITE_SEQUENCER_259 0x3103
493#define WM8995_WRITE_SEQUENCER_260 0x3104
494#define WM8995_WRITE_SEQUENCER_261 0x3105
495#define WM8995_WRITE_SEQUENCER_262 0x3106
496#define WM8995_WRITE_SEQUENCER_263 0x3107
497#define WM8995_WRITE_SEQUENCER_264 0x3108
498#define WM8995_WRITE_SEQUENCER_265 0x3109
499#define WM8995_WRITE_SEQUENCER_266 0x310A
500#define WM8995_WRITE_SEQUENCER_267 0x310B
501#define WM8995_WRITE_SEQUENCER_268 0x310C
502#define WM8995_WRITE_SEQUENCER_269 0x310D
503#define WM8995_WRITE_SEQUENCER_270 0x310E
504#define WM8995_WRITE_SEQUENCER_271 0x310F
505#define WM8995_WRITE_SEQUENCER_272 0x3110
506#define WM8995_WRITE_SEQUENCER_273 0x3111
507#define WM8995_WRITE_SEQUENCER_274 0x3112
508#define WM8995_WRITE_SEQUENCER_275 0x3113
509#define WM8995_WRITE_SEQUENCER_276 0x3114
510#define WM8995_WRITE_SEQUENCER_277 0x3115
511#define WM8995_WRITE_SEQUENCER_278 0x3116
512#define WM8995_WRITE_SEQUENCER_279 0x3117
513#define WM8995_WRITE_SEQUENCER_280 0x3118
514#define WM8995_WRITE_SEQUENCER_281 0x3119
515#define WM8995_WRITE_SEQUENCER_282 0x311A
516#define WM8995_WRITE_SEQUENCER_283 0x311B
517#define WM8995_WRITE_SEQUENCER_284 0x311C
518#define WM8995_WRITE_SEQUENCER_285 0x311D
519#define WM8995_WRITE_SEQUENCER_286 0x311E
520#define WM8995_WRITE_SEQUENCER_287 0x311F
521#define WM8995_WRITE_SEQUENCER_288 0x3120
522#define WM8995_WRITE_SEQUENCER_289 0x3121
523#define WM8995_WRITE_SEQUENCER_290 0x3122
524#define WM8995_WRITE_SEQUENCER_291 0x3123
525#define WM8995_WRITE_SEQUENCER_292 0x3124
526#define WM8995_WRITE_SEQUENCER_293 0x3125
527#define WM8995_WRITE_SEQUENCER_294 0x3126
528#define WM8995_WRITE_SEQUENCER_295 0x3127
529#define WM8995_WRITE_SEQUENCER_296 0x3128
530#define WM8995_WRITE_SEQUENCER_297 0x3129
531#define WM8995_WRITE_SEQUENCER_298 0x312A
532#define WM8995_WRITE_SEQUENCER_299 0x312B
533#define WM8995_WRITE_SEQUENCER_300 0x312C
534#define WM8995_WRITE_SEQUENCER_301 0x312D
535#define WM8995_WRITE_SEQUENCER_302 0x312E
536#define WM8995_WRITE_SEQUENCER_303 0x312F
537#define WM8995_WRITE_SEQUENCER_304 0x3130
538#define WM8995_WRITE_SEQUENCER_305 0x3131
539#define WM8995_WRITE_SEQUENCER_306 0x3132
540#define WM8995_WRITE_SEQUENCER_307 0x3133
541#define WM8995_WRITE_SEQUENCER_308 0x3134
542#define WM8995_WRITE_SEQUENCER_309 0x3135
543#define WM8995_WRITE_SEQUENCER_310 0x3136
544#define WM8995_WRITE_SEQUENCER_311 0x3137
545#define WM8995_WRITE_SEQUENCER_312 0x3138
546#define WM8995_WRITE_SEQUENCER_313 0x3139
547#define WM8995_WRITE_SEQUENCER_314 0x313A
548#define WM8995_WRITE_SEQUENCER_315 0x313B
549#define WM8995_WRITE_SEQUENCER_316 0x313C
550#define WM8995_WRITE_SEQUENCER_317 0x313D
551#define WM8995_WRITE_SEQUENCER_318 0x313E
552#define WM8995_WRITE_SEQUENCER_319 0x313F
553#define WM8995_WRITE_SEQUENCER_320 0x3140
554#define WM8995_WRITE_SEQUENCER_321 0x3141
555#define WM8995_WRITE_SEQUENCER_322 0x3142
556#define WM8995_WRITE_SEQUENCER_323 0x3143
557#define WM8995_WRITE_SEQUENCER_324 0x3144
558#define WM8995_WRITE_SEQUENCER_325 0x3145
559#define WM8995_WRITE_SEQUENCER_326 0x3146
560#define WM8995_WRITE_SEQUENCER_327 0x3147
561#define WM8995_WRITE_SEQUENCER_328 0x3148
562#define WM8995_WRITE_SEQUENCER_329 0x3149
563#define WM8995_WRITE_SEQUENCER_330 0x314A
564#define WM8995_WRITE_SEQUENCER_331 0x314B
565#define WM8995_WRITE_SEQUENCER_332 0x314C
566#define WM8995_WRITE_SEQUENCER_333 0x314D
567#define WM8995_WRITE_SEQUENCER_334 0x314E
568#define WM8995_WRITE_SEQUENCER_335 0x314F
569#define WM8995_WRITE_SEQUENCER_336 0x3150
570#define WM8995_WRITE_SEQUENCER_337 0x3151
571#define WM8995_WRITE_SEQUENCER_338 0x3152
572#define WM8995_WRITE_SEQUENCER_339 0x3153
573#define WM8995_WRITE_SEQUENCER_340 0x3154
574#define WM8995_WRITE_SEQUENCER_341 0x3155
575#define WM8995_WRITE_SEQUENCER_342 0x3156
576#define WM8995_WRITE_SEQUENCER_343 0x3157
577#define WM8995_WRITE_SEQUENCER_344 0x3158
578#define WM8995_WRITE_SEQUENCER_345 0x3159
579#define WM8995_WRITE_SEQUENCER_346 0x315A
580#define WM8995_WRITE_SEQUENCER_347 0x315B
581#define WM8995_WRITE_SEQUENCER_348 0x315C
582#define WM8995_WRITE_SEQUENCER_349 0x315D
583#define WM8995_WRITE_SEQUENCER_350 0x315E
584#define WM8995_WRITE_SEQUENCER_351 0x315F
585#define WM8995_WRITE_SEQUENCER_352 0x3160
586#define WM8995_WRITE_SEQUENCER_353 0x3161
587#define WM8995_WRITE_SEQUENCER_354 0x3162
588#define WM8995_WRITE_SEQUENCER_355 0x3163
589#define WM8995_WRITE_SEQUENCER_356 0x3164
590#define WM8995_WRITE_SEQUENCER_357 0x3165
591#define WM8995_WRITE_SEQUENCER_358 0x3166
592#define WM8995_WRITE_SEQUENCER_359 0x3167
593#define WM8995_WRITE_SEQUENCER_360 0x3168
594#define WM8995_WRITE_SEQUENCER_361 0x3169
595#define WM8995_WRITE_SEQUENCER_362 0x316A
596#define WM8995_WRITE_SEQUENCER_363 0x316B
597#define WM8995_WRITE_SEQUENCER_364 0x316C
598#define WM8995_WRITE_SEQUENCER_365 0x316D
599#define WM8995_WRITE_SEQUENCER_366 0x316E
600#define WM8995_WRITE_SEQUENCER_367 0x316F
601#define WM8995_WRITE_SEQUENCER_368 0x3170
602#define WM8995_WRITE_SEQUENCER_369 0x3171
603#define WM8995_WRITE_SEQUENCER_370 0x3172
604#define WM8995_WRITE_SEQUENCER_371 0x3173
605#define WM8995_WRITE_SEQUENCER_372 0x3174
606#define WM8995_WRITE_SEQUENCER_373 0x3175
607#define WM8995_WRITE_SEQUENCER_374 0x3176
608#define WM8995_WRITE_SEQUENCER_375 0x3177
609#define WM8995_WRITE_SEQUENCER_376 0x3178
610#define WM8995_WRITE_SEQUENCER_377 0x3179
611#define WM8995_WRITE_SEQUENCER_378 0x317A
612#define WM8995_WRITE_SEQUENCER_379 0x317B
613#define WM8995_WRITE_SEQUENCER_380 0x317C
614#define WM8995_WRITE_SEQUENCER_381 0x317D
615#define WM8995_WRITE_SEQUENCER_382 0x317E
616#define WM8995_WRITE_SEQUENCER_383 0x317F
617#define WM8995_WRITE_SEQUENCER_384 0x3180
618#define WM8995_WRITE_SEQUENCER_385 0x3181
619#define WM8995_WRITE_SEQUENCER_386 0x3182
620#define WM8995_WRITE_SEQUENCER_387 0x3183
621#define WM8995_WRITE_SEQUENCER_388 0x3184
622#define WM8995_WRITE_SEQUENCER_389 0x3185
623#define WM8995_WRITE_SEQUENCER_390 0x3186
624#define WM8995_WRITE_SEQUENCER_391 0x3187
625#define WM8995_WRITE_SEQUENCER_392 0x3188
626#define WM8995_WRITE_SEQUENCER_393 0x3189
627#define WM8995_WRITE_SEQUENCER_394 0x318A
628#define WM8995_WRITE_SEQUENCER_395 0x318B
629#define WM8995_WRITE_SEQUENCER_396 0x318C
630#define WM8995_WRITE_SEQUENCER_397 0x318D
631#define WM8995_WRITE_SEQUENCER_398 0x318E
632#define WM8995_WRITE_SEQUENCER_399 0x318F
633#define WM8995_WRITE_SEQUENCER_400 0x3190
634#define WM8995_WRITE_SEQUENCER_401 0x3191
635#define WM8995_WRITE_SEQUENCER_402 0x3192
636#define WM8995_WRITE_SEQUENCER_403 0x3193
637#define WM8995_WRITE_SEQUENCER_404 0x3194
638#define WM8995_WRITE_SEQUENCER_405 0x3195
639#define WM8995_WRITE_SEQUENCER_406 0x3196
640#define WM8995_WRITE_SEQUENCER_407 0x3197
641#define WM8995_WRITE_SEQUENCER_408 0x3198
642#define WM8995_WRITE_SEQUENCER_409 0x3199
643#define WM8995_WRITE_SEQUENCER_410 0x319A
644#define WM8995_WRITE_SEQUENCER_411 0x319B
645#define WM8995_WRITE_SEQUENCER_412 0x319C
646#define WM8995_WRITE_SEQUENCER_413 0x319D
647#define WM8995_WRITE_SEQUENCER_414 0x319E
648#define WM8995_WRITE_SEQUENCER_415 0x319F
649#define WM8995_WRITE_SEQUENCER_416 0x31A0
650#define WM8995_WRITE_SEQUENCER_417 0x31A1
651#define WM8995_WRITE_SEQUENCER_418 0x31A2
652#define WM8995_WRITE_SEQUENCER_419 0x31A3
653#define WM8995_WRITE_SEQUENCER_420 0x31A4
654#define WM8995_WRITE_SEQUENCER_421 0x31A5
655#define WM8995_WRITE_SEQUENCER_422 0x31A6
656#define WM8995_WRITE_SEQUENCER_423 0x31A7
657#define WM8995_WRITE_SEQUENCER_424 0x31A8
658#define WM8995_WRITE_SEQUENCER_425 0x31A9
659#define WM8995_WRITE_SEQUENCER_426 0x31AA
660#define WM8995_WRITE_SEQUENCER_427 0x31AB
661#define WM8995_WRITE_SEQUENCER_428 0x31AC
662#define WM8995_WRITE_SEQUENCER_429 0x31AD
663#define WM8995_WRITE_SEQUENCER_430 0x31AE
664#define WM8995_WRITE_SEQUENCER_431 0x31AF
665#define WM8995_WRITE_SEQUENCER_432 0x31B0
666#define WM8995_WRITE_SEQUENCER_433 0x31B1
667#define WM8995_WRITE_SEQUENCER_434 0x31B2
668#define WM8995_WRITE_SEQUENCER_435 0x31B3
669#define WM8995_WRITE_SEQUENCER_436 0x31B4
670#define WM8995_WRITE_SEQUENCER_437 0x31B5
671#define WM8995_WRITE_SEQUENCER_438 0x31B6
672#define WM8995_WRITE_SEQUENCER_439 0x31B7
673#define WM8995_WRITE_SEQUENCER_440 0x31B8
674#define WM8995_WRITE_SEQUENCER_441 0x31B9
675#define WM8995_WRITE_SEQUENCER_442 0x31BA
676#define WM8995_WRITE_SEQUENCER_443 0x31BB
677#define WM8995_WRITE_SEQUENCER_444 0x31BC
678#define WM8995_WRITE_SEQUENCER_445 0x31BD
679#define WM8995_WRITE_SEQUENCER_446 0x31BE
680#define WM8995_WRITE_SEQUENCER_447 0x31BF
681#define WM8995_WRITE_SEQUENCER_448 0x31C0
682#define WM8995_WRITE_SEQUENCER_449 0x31C1
683#define WM8995_WRITE_SEQUENCER_450 0x31C2
684#define WM8995_WRITE_SEQUENCER_451 0x31C3
685#define WM8995_WRITE_SEQUENCER_452 0x31C4
686#define WM8995_WRITE_SEQUENCER_453 0x31C5
687#define WM8995_WRITE_SEQUENCER_454 0x31C6
688#define WM8995_WRITE_SEQUENCER_455 0x31C7
689#define WM8995_WRITE_SEQUENCER_456 0x31C8
690#define WM8995_WRITE_SEQUENCER_457 0x31C9
691#define WM8995_WRITE_SEQUENCER_458 0x31CA
692#define WM8995_WRITE_SEQUENCER_459 0x31CB
693#define WM8995_WRITE_SEQUENCER_460 0x31CC
694#define WM8995_WRITE_SEQUENCER_461 0x31CD
695#define WM8995_WRITE_SEQUENCER_462 0x31CE
696#define WM8995_WRITE_SEQUENCER_463 0x31CF
697#define WM8995_WRITE_SEQUENCER_464 0x31D0
698#define WM8995_WRITE_SEQUENCER_465 0x31D1
699#define WM8995_WRITE_SEQUENCER_466 0x31D2
700#define WM8995_WRITE_SEQUENCER_467 0x31D3
701#define WM8995_WRITE_SEQUENCER_468 0x31D4
702#define WM8995_WRITE_SEQUENCER_469 0x31D5
703#define WM8995_WRITE_SEQUENCER_470 0x31D6
704#define WM8995_WRITE_SEQUENCER_471 0x31D7
705#define WM8995_WRITE_SEQUENCER_472 0x31D8
706#define WM8995_WRITE_SEQUENCER_473 0x31D9
707#define WM8995_WRITE_SEQUENCER_474 0x31DA
708#define WM8995_WRITE_SEQUENCER_475 0x31DB
709#define WM8995_WRITE_SEQUENCER_476 0x31DC
710#define WM8995_WRITE_SEQUENCER_477 0x31DD
711#define WM8995_WRITE_SEQUENCER_478 0x31DE
712#define WM8995_WRITE_SEQUENCER_479 0x31DF
713#define WM8995_WRITE_SEQUENCER_480 0x31E0
714#define WM8995_WRITE_SEQUENCER_481 0x31E1
715#define WM8995_WRITE_SEQUENCER_482 0x31E2
716#define WM8995_WRITE_SEQUENCER_483 0x31E3
717#define WM8995_WRITE_SEQUENCER_484 0x31E4
718#define WM8995_WRITE_SEQUENCER_485 0x31E5
719#define WM8995_WRITE_SEQUENCER_486 0x31E6
720#define WM8995_WRITE_SEQUENCER_487 0x31E7
721#define WM8995_WRITE_SEQUENCER_488 0x31E8
722#define WM8995_WRITE_SEQUENCER_489 0x31E9
723#define WM8995_WRITE_SEQUENCER_490 0x31EA
724#define WM8995_WRITE_SEQUENCER_491 0x31EB
725#define WM8995_WRITE_SEQUENCER_492 0x31EC
726#define WM8995_WRITE_SEQUENCER_493 0x31ED
727#define WM8995_WRITE_SEQUENCER_494 0x31EE
728#define WM8995_WRITE_SEQUENCER_495 0x31EF
729#define WM8995_WRITE_SEQUENCER_496 0x31F0
730#define WM8995_WRITE_SEQUENCER_497 0x31F1
731#define WM8995_WRITE_SEQUENCER_498 0x31F2
732#define WM8995_WRITE_SEQUENCER_499 0x31F3
733#define WM8995_WRITE_SEQUENCER_500 0x31F4
734#define WM8995_WRITE_SEQUENCER_501 0x31F5
735#define WM8995_WRITE_SEQUENCER_502 0x31F6
736#define WM8995_WRITE_SEQUENCER_503 0x31F7
737#define WM8995_WRITE_SEQUENCER_504 0x31F8
738#define WM8995_WRITE_SEQUENCER_505 0x31F9
739#define WM8995_WRITE_SEQUENCER_506 0x31FA
740#define WM8995_WRITE_SEQUENCER_507 0x31FB
741#define WM8995_WRITE_SEQUENCER_508 0x31FC
742#define WM8995_WRITE_SEQUENCER_509 0x31FD
743#define WM8995_WRITE_SEQUENCER_510 0x31FE
744#define WM8995_WRITE_SEQUENCER_511 0x31FF
745
746#define WM8995_REGISTER_COUNT 725
747#define WM8995_MAX_REGISTER 0x31FF
748
749#define WM8995_MAX_CACHED_REGISTER WM8995_MAX_REGISTER
750
751/*
752 * Field Definitions.
753 */
754
755/*
756 * R0 (0x00) - Software Reset
757 */
758#define WM8995_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */
759#define WM8995_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */
760#define WM8995_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */
761
762/*
763 * R1 (0x01) - Power Management (1)
764 */
765#define WM8995_MICB2_ENA 0x0200 /* MICB2_ENA */
766#define WM8995_MICB2_ENA_MASK 0x0200 /* MICB2_ENA */
767#define WM8995_MICB2_ENA_SHIFT 9 /* MICB2_ENA */
768#define WM8995_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
769#define WM8995_MICB1_ENA 0x0100 /* MICB1_ENA */
770#define WM8995_MICB1_ENA_MASK 0x0100 /* MICB1_ENA */
771#define WM8995_MICB1_ENA_SHIFT 8 /* MICB1_ENA */
772#define WM8995_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
773#define WM8995_HPOUT2L_ENA 0x0080 /* HPOUT2L_ENA */
774#define WM8995_HPOUT2L_ENA_MASK 0x0080 /* HPOUT2L_ENA */
775#define WM8995_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */
776#define WM8995_HPOUT2L_ENA_WIDTH 1 /* HPOUT2L_ENA */
777#define WM8995_HPOUT2R_ENA 0x0040 /* HPOUT2R_ENA */
778#define WM8995_HPOUT2R_ENA_MASK 0x0040 /* HPOUT2R_ENA */
779#define WM8995_HPOUT2R_ENA_SHIFT 6 /* HPOUT2R_ENA */
780#define WM8995_HPOUT2R_ENA_WIDTH 1 /* HPOUT2R_ENA */
781#define WM8995_HPOUT1L_ENA 0x0020 /* HPOUT1L_ENA */
782#define WM8995_HPOUT1L_ENA_MASK 0x0020 /* HPOUT1L_ENA */
783#define WM8995_HPOUT1L_ENA_SHIFT 5 /* HPOUT1L_ENA */
784#define WM8995_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */
785#define WM8995_HPOUT1R_ENA 0x0010 /* HPOUT1R_ENA */
786#define WM8995_HPOUT1R_ENA_MASK 0x0010 /* HPOUT1R_ENA */
787#define WM8995_HPOUT1R_ENA_SHIFT 4 /* HPOUT1R_ENA */
788#define WM8995_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */
789#define WM8995_BG_ENA 0x0001 /* BG_ENA */
790#define WM8995_BG_ENA_MASK 0x0001 /* BG_ENA */
791#define WM8995_BG_ENA_SHIFT 0 /* BG_ENA */
792#define WM8995_BG_ENA_WIDTH 1 /* BG_ENA */
793
794/*
795 * R2 (0x02) - Power Management (2)
796 */
797#define WM8995_OPCLK_ENA 0x0800 /* OPCLK_ENA */
798#define WM8995_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */
799#define WM8995_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */
800#define WM8995_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
801#define WM8995_IN1L_ENA 0x0020 /* IN1L_ENA */
802#define WM8995_IN1L_ENA_MASK 0x0020 /* IN1L_ENA */
803#define WM8995_IN1L_ENA_SHIFT 5 /* IN1L_ENA */
804#define WM8995_IN1L_ENA_WIDTH 1 /* IN1L_ENA */
805#define WM8995_IN1R_ENA 0x0010 /* IN1R_ENA */
806#define WM8995_IN1R_ENA_MASK 0x0010 /* IN1R_ENA */
807#define WM8995_IN1R_ENA_SHIFT 4 /* IN1R_ENA */
808#define WM8995_IN1R_ENA_WIDTH 1 /* IN1R_ENA */
809#define WM8995_LDO2_ENA 0x0002 /* LDO2_ENA */
810#define WM8995_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */
811#define WM8995_LDO2_ENA_SHIFT 1 /* LDO2_ENA */
812#define WM8995_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
813
814/*
815 * R3 (0x03) - Power Management (3)
816 */
817#define WM8995_AIF2ADCL_ENA 0x2000 /* AIF2ADCL_ENA */
818#define WM8995_AIF2ADCL_ENA_MASK 0x2000 /* AIF2ADCL_ENA */
819#define WM8995_AIF2ADCL_ENA_SHIFT 13 /* AIF2ADCL_ENA */
820#define WM8995_AIF2ADCL_ENA_WIDTH 1 /* AIF2ADCL_ENA */
821#define WM8995_AIF2ADCR_ENA 0x1000 /* AIF2ADCR_ENA */
822#define WM8995_AIF2ADCR_ENA_MASK 0x1000 /* AIF2ADCR_ENA */
823#define WM8995_AIF2ADCR_ENA_SHIFT 12 /* AIF2ADCR_ENA */
824#define WM8995_AIF2ADCR_ENA_WIDTH 1 /* AIF2ADCR_ENA */
825#define WM8995_AIF1ADC2L_ENA 0x0800 /* AIF1ADC2L_ENA */
826#define WM8995_AIF1ADC2L_ENA_MASK 0x0800 /* AIF1ADC2L_ENA */
827#define WM8995_AIF1ADC2L_ENA_SHIFT 11 /* AIF1ADC2L_ENA */
828#define WM8995_AIF1ADC2L_ENA_WIDTH 1 /* AIF1ADC2L_ENA */
829#define WM8995_AIF1ADC2R_ENA 0x0400 /* AIF1ADC2R_ENA */
830#define WM8995_AIF1ADC2R_ENA_MASK 0x0400 /* AIF1ADC2R_ENA */
831#define WM8995_AIF1ADC2R_ENA_SHIFT 10 /* AIF1ADC2R_ENA */
832#define WM8995_AIF1ADC2R_ENA_WIDTH 1 /* AIF1ADC2R_ENA */
833#define WM8995_AIF1ADC1L_ENA 0x0200 /* AIF1ADC1L_ENA */
834#define WM8995_AIF1ADC1L_ENA_MASK 0x0200 /* AIF1ADC1L_ENA */
835#define WM8995_AIF1ADC1L_ENA_SHIFT 9 /* AIF1ADC1L_ENA */
836#define WM8995_AIF1ADC1L_ENA_WIDTH 1 /* AIF1ADC1L_ENA */
837#define WM8995_AIF1ADC1R_ENA 0x0100 /* AIF1ADC1R_ENA */
838#define WM8995_AIF1ADC1R_ENA_MASK 0x0100 /* AIF1ADC1R_ENA */
839#define WM8995_AIF1ADC1R_ENA_SHIFT 8 /* AIF1ADC1R_ENA */
840#define WM8995_AIF1ADC1R_ENA_WIDTH 1 /* AIF1ADC1R_ENA */
841#define WM8995_DMIC3L_ENA 0x0080 /* DMIC3L_ENA */
842#define WM8995_DMIC3L_ENA_MASK 0x0080 /* DMIC3L_ENA */
843#define WM8995_DMIC3L_ENA_SHIFT 7 /* DMIC3L_ENA */
844#define WM8995_DMIC3L_ENA_WIDTH 1 /* DMIC3L_ENA */
845#define WM8995_DMIC3R_ENA 0x0040 /* DMIC3R_ENA */
846#define WM8995_DMIC3R_ENA_MASK 0x0040 /* DMIC3R_ENA */
847#define WM8995_DMIC3R_ENA_SHIFT 6 /* DMIC3R_ENA */
848#define WM8995_DMIC3R_ENA_WIDTH 1 /* DMIC3R_ENA */
849#define WM8995_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */
850#define WM8995_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */
851#define WM8995_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */
852#define WM8995_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */
853#define WM8995_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */
854#define WM8995_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */
855#define WM8995_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */
856#define WM8995_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */
857#define WM8995_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */
858#define WM8995_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */
859#define WM8995_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */
860#define WM8995_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */
861#define WM8995_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */
862#define WM8995_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */
863#define WM8995_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */
864#define WM8995_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */
865#define WM8995_ADCL_ENA 0x0002 /* ADCL_ENA */
866#define WM8995_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */
867#define WM8995_ADCL_ENA_SHIFT 1 /* ADCL_ENA */
868#define WM8995_ADCL_ENA_WIDTH 1 /* ADCL_ENA */
869#define WM8995_ADCR_ENA 0x0001 /* ADCR_ENA */
870#define WM8995_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
871#define WM8995_ADCR_ENA_SHIFT 0 /* ADCR_ENA */
872#define WM8995_ADCR_ENA_WIDTH 1 /* ADCR_ENA */
873
874/*
875 * R4 (0x04) - Power Management (4)
876 */
877#define WM8995_AIF2DACL_ENA 0x2000 /* AIF2DACL_ENA */
878#define WM8995_AIF2DACL_ENA_MASK 0x2000 /* AIF2DACL_ENA */
879#define WM8995_AIF2DACL_ENA_SHIFT 13 /* AIF2DACL_ENA */
880#define WM8995_AIF2DACL_ENA_WIDTH 1 /* AIF2DACL_ENA */
881#define WM8995_AIF2DACR_ENA 0x1000 /* AIF2DACR_ENA */
882#define WM8995_AIF2DACR_ENA_MASK 0x1000 /* AIF2DACR_ENA */
883#define WM8995_AIF2DACR_ENA_SHIFT 12 /* AIF2DACR_ENA */
884#define WM8995_AIF2DACR_ENA_WIDTH 1 /* AIF2DACR_ENA */
885#define WM8995_AIF1DAC2L_ENA 0x0800 /* AIF1DAC2L_ENA */
886#define WM8995_AIF1DAC2L_ENA_MASK 0x0800 /* AIF1DAC2L_ENA */
887#define WM8995_AIF1DAC2L_ENA_SHIFT 11 /* AIF1DAC2L_ENA */
888#define WM8995_AIF1DAC2L_ENA_WIDTH 1 /* AIF1DAC2L_ENA */
889#define WM8995_AIF1DAC2R_ENA 0x0400 /* AIF1DAC2R_ENA */
890#define WM8995_AIF1DAC2R_ENA_MASK 0x0400 /* AIF1DAC2R_ENA */
891#define WM8995_AIF1DAC2R_ENA_SHIFT 10 /* AIF1DAC2R_ENA */
892#define WM8995_AIF1DAC2R_ENA_WIDTH 1 /* AIF1DAC2R_ENA */
893#define WM8995_AIF1DAC1L_ENA 0x0200 /* AIF1DAC1L_ENA */
894#define WM8995_AIF1DAC1L_ENA_MASK 0x0200 /* AIF1DAC1L_ENA */
895#define WM8995_AIF1DAC1L_ENA_SHIFT 9 /* AIF1DAC1L_ENA */
896#define WM8995_AIF1DAC1L_ENA_WIDTH 1 /* AIF1DAC1L_ENA */
897#define WM8995_AIF1DAC1R_ENA 0x0100 /* AIF1DAC1R_ENA */
898#define WM8995_AIF1DAC1R_ENA_MASK 0x0100 /* AIF1DAC1R_ENA */
899#define WM8995_AIF1DAC1R_ENA_SHIFT 8 /* AIF1DAC1R_ENA */
900#define WM8995_AIF1DAC1R_ENA_WIDTH 1 /* AIF1DAC1R_ENA */
901#define WM8995_DAC2L_ENA 0x0008 /* DAC2L_ENA */
902#define WM8995_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */
903#define WM8995_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */
904#define WM8995_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */
905#define WM8995_DAC2R_ENA 0x0004 /* DAC2R_ENA */
906#define WM8995_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */
907#define WM8995_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */
908#define WM8995_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */
909#define WM8995_DAC1L_ENA 0x0002 /* DAC1L_ENA */
910#define WM8995_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */
911#define WM8995_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */
912#define WM8995_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */
913#define WM8995_DAC1R_ENA 0x0001 /* DAC1R_ENA */
914#define WM8995_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */
915#define WM8995_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */
916#define WM8995_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */
917
918/*
919 * R5 (0x05) - Power Management (5)
920 */
921#define WM8995_DMIC_SRC2_MASK 0x0300 /* DMIC_SRC2 - [9:8] */
922#define WM8995_DMIC_SRC2_SHIFT 8 /* DMIC_SRC2 - [9:8] */
923#define WM8995_DMIC_SRC2_WIDTH 2 /* DMIC_SRC2 - [9:8] */
924#define WM8995_DMIC_SRC1_MASK 0x00C0 /* DMIC_SRC1 - [7:6] */
925#define WM8995_DMIC_SRC1_SHIFT 6 /* DMIC_SRC1 - [7:6] */
926#define WM8995_DMIC_SRC1_WIDTH 2 /* DMIC_SRC1 - [7:6] */
927#define WM8995_AIF3_TRI 0x0020 /* AIF3_TRI */
928#define WM8995_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */
929#define WM8995_AIF3_TRI_SHIFT 5 /* AIF3_TRI */
930#define WM8995_AIF3_TRI_WIDTH 1 /* AIF3_TRI */
931#define WM8995_AIF3_ADCDAT_SRC_MASK 0x0018 /* AIF3_ADCDAT_SRC - [4:3] */
932#define WM8995_AIF3_ADCDAT_SRC_SHIFT 3 /* AIF3_ADCDAT_SRC - [4:3] */
933#define WM8995_AIF3_ADCDAT_SRC_WIDTH 2 /* AIF3_ADCDAT_SRC - [4:3] */
934#define WM8995_AIF2_ADCDAT_SRC 0x0004 /* AIF2_ADCDAT_SRC */
935#define WM8995_AIF2_ADCDAT_SRC_MASK 0x0004 /* AIF2_ADCDAT_SRC */
936#define WM8995_AIF2_ADCDAT_SRC_SHIFT 2 /* AIF2_ADCDAT_SRC */
937#define WM8995_AIF2_ADCDAT_SRC_WIDTH 1 /* AIF2_ADCDAT_SRC */
938#define WM8995_AIF2_DACDAT_SRC 0x0002 /* AIF2_DACDAT_SRC */
939#define WM8995_AIF2_DACDAT_SRC_MASK 0x0002 /* AIF2_DACDAT_SRC */
940#define WM8995_AIF2_DACDAT_SRC_SHIFT 1 /* AIF2_DACDAT_SRC */
941#define WM8995_AIF2_DACDAT_SRC_WIDTH 1 /* AIF2_DACDAT_SRC */
942#define WM8995_AIF1_DACDAT_SRC 0x0001 /* AIF1_DACDAT_SRC */
943#define WM8995_AIF1_DACDAT_SRC_MASK 0x0001 /* AIF1_DACDAT_SRC */
944#define WM8995_AIF1_DACDAT_SRC_SHIFT 0 /* AIF1_DACDAT_SRC */
945#define WM8995_AIF1_DACDAT_SRC_WIDTH 1 /* AIF1_DACDAT_SRC */
946
947/*
948 * R16 (0x10) - Left Line Input 1 Volume
949 */
950#define WM8995_IN1_VU 0x0080 /* IN1_VU */
951#define WM8995_IN1_VU_MASK 0x0080 /* IN1_VU */
952#define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */
953#define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */
954#define WM8995_IN1L_ZC 0x0020 /* IN1L_ZC */
955#define WM8995_IN1L_ZC_MASK 0x0020 /* IN1L_ZC */
956#define WM8995_IN1L_ZC_SHIFT 5 /* IN1L_ZC */
957#define WM8995_IN1L_ZC_WIDTH 1 /* IN1L_ZC */
958#define WM8995_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */
959#define WM8995_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */
960#define WM8995_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */
961
962/*
963 * R17 (0x11) - Right Line Input 1 Volume
964 */
965#define WM8995_IN1_VU 0x0080 /* IN1_VU */
966#define WM8995_IN1_VU_MASK 0x0080 /* IN1_VU */
967#define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */
968#define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */
969#define WM8995_IN1R_ZC 0x0020 /* IN1R_ZC */
970#define WM8995_IN1R_ZC_MASK 0x0020 /* IN1R_ZC */
971#define WM8995_IN1R_ZC_SHIFT 5 /* IN1R_ZC */
972#define WM8995_IN1R_ZC_WIDTH 1 /* IN1R_ZC */
973#define WM8995_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */
974#define WM8995_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */
975#define WM8995_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */
976
977/*
978 * R18 (0x12) - Left Line Input Control
979 */
980#define WM8995_IN1L_BOOST_MASK 0x0030 /* IN1L_BOOST - [5:4] */
981#define WM8995_IN1L_BOOST_SHIFT 4 /* IN1L_BOOST - [5:4] */
982#define WM8995_IN1L_BOOST_WIDTH 2 /* IN1L_BOOST - [5:4] */
983#define WM8995_IN1L_MODE_MASK 0x000C /* IN1L_MODE - [3:2] */
984#define WM8995_IN1L_MODE_SHIFT 2 /* IN1L_MODE - [3:2] */
985#define WM8995_IN1L_MODE_WIDTH 2 /* IN1L_MODE - [3:2] */
986#define WM8995_IN1R_MODE_MASK 0x0003 /* IN1R_MODE - [1:0] */
987#define WM8995_IN1R_MODE_SHIFT 0 /* IN1R_MODE - [1:0] */
988#define WM8995_IN1R_MODE_WIDTH 2 /* IN1R_MODE - [1:0] */
989
990/*
991 * R24 (0x18) - DAC1 Left Volume
992 */
993#define WM8995_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */
994#define WM8995_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */
995#define WM8995_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */
996#define WM8995_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */
997#define WM8995_DAC1_VU 0x0100 /* DAC1_VU */
998#define WM8995_DAC1_VU_MASK 0x0100 /* DAC1_VU */
999#define WM8995_DAC1_VU_SHIFT 8 /* DAC1_VU */
1000#define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */
1001#define WM8995_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */
1002#define WM8995_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */
1003#define WM8995_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */
1004
1005/*
1006 * R25 (0x19) - DAC1 Right Volume
1007 */
1008#define WM8995_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */
1009#define WM8995_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */
1010#define WM8995_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */
1011#define WM8995_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */
1012#define WM8995_DAC1_VU 0x0100 /* DAC1_VU */
1013#define WM8995_DAC1_VU_MASK 0x0100 /* DAC1_VU */
1014#define WM8995_DAC1_VU_SHIFT 8 /* DAC1_VU */
1015#define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */
1016#define WM8995_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */
1017#define WM8995_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */
1018#define WM8995_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */
1019
1020/*
1021 * R26 (0x1A) - DAC2 Left Volume
1022 */
1023#define WM8995_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */
1024#define WM8995_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */
1025#define WM8995_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */
1026#define WM8995_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */
1027#define WM8995_DAC2_VU 0x0100 /* DAC2_VU */
1028#define WM8995_DAC2_VU_MASK 0x0100 /* DAC2_VU */
1029#define WM8995_DAC2_VU_SHIFT 8 /* DAC2_VU */
1030#define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */
1031#define WM8995_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */
1032#define WM8995_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */
1033#define WM8995_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */
1034
1035/*
1036 * R27 (0x1B) - DAC2 Right Volume
1037 */
1038#define WM8995_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */
1039#define WM8995_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */
1040#define WM8995_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */
1041#define WM8995_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */
1042#define WM8995_DAC2_VU 0x0100 /* DAC2_VU */
1043#define WM8995_DAC2_VU_MASK 0x0100 /* DAC2_VU */
1044#define WM8995_DAC2_VU_SHIFT 8 /* DAC2_VU */
1045#define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */
1046#define WM8995_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */
1047#define WM8995_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */
1048#define WM8995_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */
1049
1050/*
1051 * R28 (0x1C) - Output Volume ZC (1)
1052 */
1053#define WM8995_HPOUT2L_ZC 0x0008 /* HPOUT2L_ZC */
1054#define WM8995_HPOUT2L_ZC_MASK 0x0008 /* HPOUT2L_ZC */
1055#define WM8995_HPOUT2L_ZC_SHIFT 3 /* HPOUT2L_ZC */
1056#define WM8995_HPOUT2L_ZC_WIDTH 1 /* HPOUT2L_ZC */
1057#define WM8995_HPOUT2R_ZC 0x0004 /* HPOUT2R_ZC */
1058#define WM8995_HPOUT2R_ZC_MASK 0x0004 /* HPOUT2R_ZC */
1059#define WM8995_HPOUT2R_ZC_SHIFT 2 /* HPOUT2R_ZC */
1060#define WM8995_HPOUT2R_ZC_WIDTH 1 /* HPOUT2R_ZC */
1061#define WM8995_HPOUT1L_ZC 0x0002 /* HPOUT1L_ZC */
1062#define WM8995_HPOUT1L_ZC_MASK 0x0002 /* HPOUT1L_ZC */
1063#define WM8995_HPOUT1L_ZC_SHIFT 1 /* HPOUT1L_ZC */
1064#define WM8995_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */
1065#define WM8995_HPOUT1R_ZC 0x0001 /* HPOUT1R_ZC */
1066#define WM8995_HPOUT1R_ZC_MASK 0x0001 /* HPOUT1R_ZC */
1067#define WM8995_HPOUT1R_ZC_SHIFT 0 /* HPOUT1R_ZC */
1068#define WM8995_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */
1069
1070/*
1071 * R32 (0x20) - MICBIAS (1)
1072 */
1073#define WM8995_MICB1_MODE 0x0008 /* MICB1_MODE */
1074#define WM8995_MICB1_MODE_MASK 0x0008 /* MICB1_MODE */
1075#define WM8995_MICB1_MODE_SHIFT 3 /* MICB1_MODE */
1076#define WM8995_MICB1_MODE_WIDTH 1 /* MICB1_MODE */
1077#define WM8995_MICB1_LVL_MASK 0x0006 /* MICB1_LVL - [2:1] */
1078#define WM8995_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [2:1] */
1079#define WM8995_MICB1_LVL_WIDTH 2 /* MICB1_LVL - [2:1] */
1080#define WM8995_MICB1_DISCH 0x0001 /* MICB1_DISCH */
1081#define WM8995_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */
1082#define WM8995_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */
1083#define WM8995_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
1084
1085/*
1086 * R33 (0x21) - MICBIAS (2)
1087 */
1088#define WM8995_MICB2_MODE 0x0008 /* MICB2_MODE */
1089#define WM8995_MICB2_MODE_MASK 0x0008 /* MICB2_MODE */
1090#define WM8995_MICB2_MODE_SHIFT 3 /* MICB2_MODE */
1091#define WM8995_MICB2_MODE_WIDTH 1 /* MICB2_MODE */
1092#define WM8995_MICB2_LVL_MASK 0x0006 /* MICB2_LVL - [2:1] */
1093#define WM8995_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [2:1] */
1094#define WM8995_MICB2_LVL_WIDTH 2 /* MICB2_LVL - [2:1] */
1095#define WM8995_MICB2_DISCH 0x0001 /* MICB2_DISCH */
1096#define WM8995_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */
1097#define WM8995_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */
1098#define WM8995_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
1099
1100/*
1101 * R40 (0x28) - LDO 1
1102 */
1103#define WM8995_LDO1_MODE 0x0020 /* LDO1_MODE */
1104#define WM8995_LDO1_MODE_MASK 0x0020 /* LDO1_MODE */
1105#define WM8995_LDO1_MODE_SHIFT 5 /* LDO1_MODE */
1106#define WM8995_LDO1_MODE_WIDTH 1 /* LDO1_MODE */
1107#define WM8995_LDO1_VSEL_MASK 0x0006 /* LDO1_VSEL - [2:1] */
1108#define WM8995_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [2:1] */
1109#define WM8995_LDO1_VSEL_WIDTH 2 /* LDO1_VSEL - [2:1] */
1110#define WM8995_LDO1_DISCH 0x0001 /* LDO1_DISCH */
1111#define WM8995_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */
1112#define WM8995_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */
1113#define WM8995_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */
1114
1115/*
1116 * R41 (0x29) - LDO 2
1117 */
1118#define WM8995_LDO2_MODE 0x0020 /* LDO2_MODE */
1119#define WM8995_LDO2_MODE_MASK 0x0020 /* LDO2_MODE */
1120#define WM8995_LDO2_MODE_SHIFT 5 /* LDO2_MODE */
1121#define WM8995_LDO2_MODE_WIDTH 1 /* LDO2_MODE */
1122#define WM8995_LDO2_VSEL_MASK 0x001E /* LDO2_VSEL - [4:1] */
1123#define WM8995_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [4:1] */
1124#define WM8995_LDO2_VSEL_WIDTH 4 /* LDO2_VSEL - [4:1] */
1125#define WM8995_LDO2_DISCH 0x0001 /* LDO2_DISCH */
1126#define WM8995_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */
1127#define WM8995_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */
1128#define WM8995_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */
1129
1130/*
1131 * R48 (0x30) - Accessory Detect Mode1
1132 */
1133#define WM8995_JD_MODE_MASK 0x0003 /* JD_MODE - [1:0] */
1134#define WM8995_JD_MODE_SHIFT 0 /* JD_MODE - [1:0] */
1135#define WM8995_JD_MODE_WIDTH 2 /* JD_MODE - [1:0] */
1136
1137/*
1138 * R49 (0x31) - Accessory Detect Mode2
1139 */
1140#define WM8995_VID_ENA 0x0001 /* VID_ENA */
1141#define WM8995_VID_ENA_MASK 0x0001 /* VID_ENA */
1142#define WM8995_VID_ENA_SHIFT 0 /* VID_ENA */
1143#define WM8995_VID_ENA_WIDTH 1 /* VID_ENA */
1144
1145/*
1146 * R52 (0x34) - Headphone Detect1
1147 */
1148#define WM8995_HP_RAMPRATE 0x0002 /* HP_RAMPRATE */
1149#define WM8995_HP_RAMPRATE_MASK 0x0002 /* HP_RAMPRATE */
1150#define WM8995_HP_RAMPRATE_SHIFT 1 /* HP_RAMPRATE */
1151#define WM8995_HP_RAMPRATE_WIDTH 1 /* HP_RAMPRATE */
1152#define WM8995_HP_POLL 0x0001 /* HP_POLL */
1153#define WM8995_HP_POLL_MASK 0x0001 /* HP_POLL */
1154#define WM8995_HP_POLL_SHIFT 0 /* HP_POLL */
1155#define WM8995_HP_POLL_WIDTH 1 /* HP_POLL */
1156
1157/*
1158 * R53 (0x35) - Headphone Detect2
1159 */
1160#define WM8995_HP_DONE 0x0080 /* HP_DONE */
1161#define WM8995_HP_DONE_MASK 0x0080 /* HP_DONE */
1162#define WM8995_HP_DONE_SHIFT 7 /* HP_DONE */
1163#define WM8995_HP_DONE_WIDTH 1 /* HP_DONE */
1164#define WM8995_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */
1165#define WM8995_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */
1166#define WM8995_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */
1167
1168/*
1169 * R56 (0x38) - Mic Detect (1)
1170 */
1171#define WM8995_MICD_RATE_MASK 0x7800 /* MICD_RATE - [14:11] */
1172#define WM8995_MICD_RATE_SHIFT 11 /* MICD_RATE - [14:11] */
1173#define WM8995_MICD_RATE_WIDTH 4 /* MICD_RATE - [14:11] */
1174#define WM8995_MICD_LVL_SEL_MASK 0x01F8 /* MICD_LVL_SEL - [8:3] */
1175#define WM8995_MICD_LVL_SEL_SHIFT 3 /* MICD_LVL_SEL - [8:3] */
1176#define WM8995_MICD_LVL_SEL_WIDTH 6 /* MICD_LVL_SEL - [8:3] */
1177#define WM8995_MICD_DBTIME 0x0002 /* MICD_DBTIME */
1178#define WM8995_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */
1179#define WM8995_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */
1180#define WM8995_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */
1181#define WM8995_MICD_ENA 0x0001 /* MICD_ENA */
1182#define WM8995_MICD_ENA_MASK 0x0001 /* MICD_ENA */
1183#define WM8995_MICD_ENA_SHIFT 0 /* MICD_ENA */
1184#define WM8995_MICD_ENA_WIDTH 1 /* MICD_ENA */
1185
1186/*
1187 * R57 (0x39) - Mic Detect (2)
1188 */
1189#define WM8995_MICD_LVL_MASK 0x01FC /* MICD_LVL - [8:2] */
1190#define WM8995_MICD_LVL_SHIFT 2 /* MICD_LVL - [8:2] */
1191#define WM8995_MICD_LVL_WIDTH 7 /* MICD_LVL - [8:2] */
1192#define WM8995_MICD_VALID 0x0002 /* MICD_VALID */
1193#define WM8995_MICD_VALID_MASK 0x0002 /* MICD_VALID */
1194#define WM8995_MICD_VALID_SHIFT 1 /* MICD_VALID */
1195#define WM8995_MICD_VALID_WIDTH 1 /* MICD_VALID */
1196#define WM8995_MICD_STS 0x0001 /* MICD_STS */
1197#define WM8995_MICD_STS_MASK 0x0001 /* MICD_STS */
1198#define WM8995_MICD_STS_SHIFT 0 /* MICD_STS */
1199#define WM8995_MICD_STS_WIDTH 1 /* MICD_STS */
1200
1201/*
1202 * R64 (0x40) - Charge Pump (1)
1203 */
1204#define WM8995_CP_ENA 0x8000 /* CP_ENA */
1205#define WM8995_CP_ENA_MASK 0x8000 /* CP_ENA */
1206#define WM8995_CP_ENA_SHIFT 15 /* CP_ENA */
1207#define WM8995_CP_ENA_WIDTH 1 /* CP_ENA */
1208
1209/*
1210 * R69 (0x45) - Class W (1)
1211 */
1212#define WM8995_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */
1213#define WM8995_CP_DYN_SRC_SEL_SHIFT 8 /* CP_DYN_SRC_SEL - [9:8] */
1214#define WM8995_CP_DYN_SRC_SEL_WIDTH 2 /* CP_DYN_SRC_SEL - [9:8] */
1215#define WM8995_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */
1216#define WM8995_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */
1217#define WM8995_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */
1218#define WM8995_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */
1219
1220/*
1221 * R80 (0x50) - DC Servo (1)
1222 */
1223#define WM8995_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */
1224#define WM8995_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */
1225#define WM8995_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */
1226#define WM8995_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */
1227#define WM8995_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */
1228#define WM8995_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */
1229#define WM8995_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */
1230#define WM8995_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */
1231#define WM8995_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */
1232#define WM8995_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */
1233#define WM8995_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */
1234#define WM8995_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */
1235#define WM8995_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */
1236#define WM8995_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */
1237#define WM8995_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */
1238#define WM8995_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */
1239
1240/*
1241 * R81 (0x51) - DC Servo (2)
1242 */
1243#define WM8995_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */
1244#define WM8995_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */
1245#define WM8995_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */
1246#define WM8995_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */
1247#define WM8995_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */
1248#define WM8995_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */
1249#define WM8995_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */
1250#define WM8995_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */
1251#define WM8995_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */
1252#define WM8995_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */
1253#define WM8995_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */
1254#define WM8995_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */
1255#define WM8995_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */
1256#define WM8995_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */
1257#define WM8995_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */
1258#define WM8995_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */
1259#define WM8995_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */
1260#define WM8995_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */
1261#define WM8995_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */
1262#define WM8995_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */
1263#define WM8995_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */
1264#define WM8995_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */
1265#define WM8995_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */
1266#define WM8995_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */
1267#define WM8995_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */
1268#define WM8995_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */
1269#define WM8995_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */
1270#define WM8995_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */
1271#define WM8995_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */
1272#define WM8995_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */
1273#define WM8995_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */
1274#define WM8995_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */
1275#define WM8995_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */
1276#define WM8995_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */
1277#define WM8995_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */
1278#define WM8995_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */
1279#define WM8995_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */
1280#define WM8995_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */
1281#define WM8995_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */
1282#define WM8995_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */
1283#define WM8995_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */
1284#define WM8995_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */
1285#define WM8995_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */
1286#define WM8995_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */
1287#define WM8995_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */
1288#define WM8995_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */
1289#define WM8995_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */
1290#define WM8995_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */
1291#define WM8995_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */
1292#define WM8995_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */
1293#define WM8995_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */
1294#define WM8995_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */
1295#define WM8995_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */
1296#define WM8995_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */
1297#define WM8995_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */
1298#define WM8995_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */
1299#define WM8995_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */
1300#define WM8995_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */
1301#define WM8995_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */
1302#define WM8995_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */
1303#define WM8995_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */
1304#define WM8995_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */
1305#define WM8995_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */
1306#define WM8995_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */
1307
1308/*
1309 * R82 (0x52) - DC Servo (3)
1310 */
1311#define WM8995_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */
1312#define WM8995_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */
1313#define WM8995_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */
1314#define WM8995_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */
1315#define WM8995_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */
1316#define WM8995_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */
1317
1318/*
1319 * R84 (0x54) - DC Servo (5)
1320 */
1321#define WM8995_DCS_SERIES_NO_23_MASK 0x7F00 /* DCS_SERIES_NO_23 - [14:8] */
1322#define WM8995_DCS_SERIES_NO_23_SHIFT 8 /* DCS_SERIES_NO_23 - [14:8] */
1323#define WM8995_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [14:8] */
1324#define WM8995_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */
1325#define WM8995_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */
1326#define WM8995_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */
1327
1328/*
1329 * R85 (0x55) - DC Servo (6)
1330 */
1331#define WM8995_DCS_DAC_WR_VAL_3_MASK 0xFF00 /* DCS_DAC_WR_VAL_3 - [15:8] */
1332#define WM8995_DCS_DAC_WR_VAL_3_SHIFT 8 /* DCS_DAC_WR_VAL_3 - [15:8] */
1333#define WM8995_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [15:8] */
1334#define WM8995_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */
1335#define WM8995_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */
1336#define WM8995_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */
1337
1338/*
1339 * R86 (0x56) - DC Servo (7)
1340 */
1341#define WM8995_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */
1342#define WM8995_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
1343#define WM8995_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
1344#define WM8995_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */
1345#define WM8995_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */
1346#define WM8995_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */
1347
1348/*
1349 * R87 (0x57) - DC Servo Readback 0
1350 */
1351#define WM8995_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */
1352#define WM8995_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */
1353#define WM8995_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */
1354#define WM8995_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */
1355#define WM8995_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */
1356#define WM8995_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */
1357#define WM8995_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */
1358#define WM8995_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */
1359#define WM8995_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */
1360
1361/*
1362 * R96 (0x60) - Analogue HP (1)
1363 */
1364#define WM8995_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */
1365#define WM8995_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */
1366#define WM8995_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */
1367#define WM8995_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */
1368#define WM8995_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */
1369#define WM8995_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */
1370#define WM8995_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */
1371#define WM8995_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */
1372#define WM8995_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */
1373#define WM8995_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */
1374#define WM8995_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */
1375#define WM8995_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */
1376#define WM8995_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */
1377#define WM8995_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */
1378#define WM8995_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */
1379#define WM8995_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */
1380#define WM8995_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */
1381#define WM8995_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */
1382#define WM8995_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */
1383#define WM8995_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */
1384#define WM8995_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */
1385#define WM8995_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */
1386#define WM8995_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */
1387#define WM8995_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */
1388
1389/*
1390 * R97 (0x61) - Analogue HP (2)
1391 */
1392#define WM8995_HPOUT2L_RMV_SHORT 0x0080 /* HPOUT2L_RMV_SHORT */
1393#define WM8995_HPOUT2L_RMV_SHORT_MASK 0x0080 /* HPOUT2L_RMV_SHORT */
1394#define WM8995_HPOUT2L_RMV_SHORT_SHIFT 7 /* HPOUT2L_RMV_SHORT */
1395#define WM8995_HPOUT2L_RMV_SHORT_WIDTH 1 /* HPOUT2L_RMV_SHORT */
1396#define WM8995_HPOUT2L_OUTP 0x0040 /* HPOUT2L_OUTP */
1397#define WM8995_HPOUT2L_OUTP_MASK 0x0040 /* HPOUT2L_OUTP */
1398#define WM8995_HPOUT2L_OUTP_SHIFT 6 /* HPOUT2L_OUTP */
1399#define WM8995_HPOUT2L_OUTP_WIDTH 1 /* HPOUT2L_OUTP */
1400#define WM8995_HPOUT2L_DLY 0x0020 /* HPOUT2L_DLY */
1401#define WM8995_HPOUT2L_DLY_MASK 0x0020 /* HPOUT2L_DLY */
1402#define WM8995_HPOUT2L_DLY_SHIFT 5 /* HPOUT2L_DLY */
1403#define WM8995_HPOUT2L_DLY_WIDTH 1 /* HPOUT2L_DLY */
1404#define WM8995_HPOUT2R_RMV_SHORT 0x0008 /* HPOUT2R_RMV_SHORT */
1405#define WM8995_HPOUT2R_RMV_SHORT_MASK 0x0008 /* HPOUT2R_RMV_SHORT */
1406#define WM8995_HPOUT2R_RMV_SHORT_SHIFT 3 /* HPOUT2R_RMV_SHORT */
1407#define WM8995_HPOUT2R_RMV_SHORT_WIDTH 1 /* HPOUT2R_RMV_SHORT */
1408#define WM8995_HPOUT2R_OUTP 0x0004 /* HPOUT2R_OUTP */
1409#define WM8995_HPOUT2R_OUTP_MASK 0x0004 /* HPOUT2R_OUTP */
1410#define WM8995_HPOUT2R_OUTP_SHIFT 2 /* HPOUT2R_OUTP */
1411#define WM8995_HPOUT2R_OUTP_WIDTH 1 /* HPOUT2R_OUTP */
1412#define WM8995_HPOUT2R_DLY 0x0002 /* HPOUT2R_DLY */
1413#define WM8995_HPOUT2R_DLY_MASK 0x0002 /* HPOUT2R_DLY */
1414#define WM8995_HPOUT2R_DLY_SHIFT 1 /* HPOUT2R_DLY */
1415#define WM8995_HPOUT2R_DLY_WIDTH 1 /* HPOUT2R_DLY */
1416
1417/*
1418 * R256 (0x100) - Chip Revision
1419 */
1420#define WM8995_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */
1421#define WM8995_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */
1422#define WM8995_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */
1423
1424/*
1425 * R257 (0x101) - Control Interface (1)
1426 */
1427#define WM8995_REG_SYNC 0x8000 /* REG_SYNC */
1428#define WM8995_REG_SYNC_MASK 0x8000 /* REG_SYNC */
1429#define WM8995_REG_SYNC_SHIFT 15 /* REG_SYNC */
1430#define WM8995_REG_SYNC_WIDTH 1 /* REG_SYNC */
1431#define WM8995_SPI_CONTRD 0x0040 /* SPI_CONTRD */
1432#define WM8995_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */
1433#define WM8995_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */
1434#define WM8995_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */
1435#define WM8995_SPI_4WIRE 0x0020 /* SPI_4WIRE */
1436#define WM8995_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */
1437#define WM8995_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */
1438#define WM8995_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
1439#define WM8995_SPI_CFG 0x0010 /* SPI_CFG */
1440#define WM8995_SPI_CFG_MASK 0x0010 /* SPI_CFG */
1441#define WM8995_SPI_CFG_SHIFT 4 /* SPI_CFG */
1442#define WM8995_SPI_CFG_WIDTH 1 /* SPI_CFG */
1443#define WM8995_AUTO_INC 0x0004 /* AUTO_INC */
1444#define WM8995_AUTO_INC_MASK 0x0004 /* AUTO_INC */
1445#define WM8995_AUTO_INC_SHIFT 2 /* AUTO_INC */
1446#define WM8995_AUTO_INC_WIDTH 1 /* AUTO_INC */
1447
1448/*
1449 * R258 (0x102) - Control Interface (2)
1450 */
1451#define WM8995_CTRL_IF_SRC 0x0001 /* CTRL_IF_SRC */
1452#define WM8995_CTRL_IF_SRC_MASK 0x0001 /* CTRL_IF_SRC */
1453#define WM8995_CTRL_IF_SRC_SHIFT 0 /* CTRL_IF_SRC */
1454#define WM8995_CTRL_IF_SRC_WIDTH 1 /* CTRL_IF_SRC */
1455
1456/*
1457 * R272 (0x110) - Write Sequencer Ctrl (1)
1458 */
1459#define WM8995_WSEQ_ENA 0x8000 /* WSEQ_ENA */
1460#define WM8995_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */
1461#define WM8995_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */
1462#define WM8995_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
1463#define WM8995_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
1464#define WM8995_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
1465#define WM8995_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
1466#define WM8995_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
1467#define WM8995_WSEQ_START 0x0100 /* WSEQ_START */
1468#define WM8995_WSEQ_START_MASK 0x0100 /* WSEQ_START */
1469#define WM8995_WSEQ_START_SHIFT 8 /* WSEQ_START */
1470#define WM8995_WSEQ_START_WIDTH 1 /* WSEQ_START */
1471#define WM8995_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
1472#define WM8995_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
1473#define WM8995_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
1474
1475/*
1476 * R273 (0x111) - Write Sequencer Ctrl (2)
1477 */
1478#define WM8995_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */
1479#define WM8995_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */
1480#define WM8995_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */
1481#define WM8995_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
1482#define WM8995_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */
1483#define WM8995_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */
1484#define WM8995_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */
1485
1486/*
1487 * R512 (0x200) - AIF1 Clocking (1)
1488 */
1489#define WM8995_AIF1CLK_SRC_MASK 0x0018 /* AIF1CLK_SRC - [4:3] */
1490#define WM8995_AIF1CLK_SRC_SHIFT 3 /* AIF1CLK_SRC - [4:3] */
1491#define WM8995_AIF1CLK_SRC_WIDTH 2 /* AIF1CLK_SRC - [4:3] */
1492#define WM8995_AIF1CLK_INV 0x0004 /* AIF1CLK_INV */
1493#define WM8995_AIF1CLK_INV_MASK 0x0004 /* AIF1CLK_INV */
1494#define WM8995_AIF1CLK_INV_SHIFT 2 /* AIF1CLK_INV */
1495#define WM8995_AIF1CLK_INV_WIDTH 1 /* AIF1CLK_INV */
1496#define WM8995_AIF1CLK_DIV 0x0002 /* AIF1CLK_DIV */
1497#define WM8995_AIF1CLK_DIV_MASK 0x0002 /* AIF1CLK_DIV */
1498#define WM8995_AIF1CLK_DIV_SHIFT 1 /* AIF1CLK_DIV */
1499#define WM8995_AIF1CLK_DIV_WIDTH 1 /* AIF1CLK_DIV */
1500#define WM8995_AIF1CLK_ENA 0x0001 /* AIF1CLK_ENA */
1501#define WM8995_AIF1CLK_ENA_MASK 0x0001 /* AIF1CLK_ENA */
1502#define WM8995_AIF1CLK_ENA_SHIFT 0 /* AIF1CLK_ENA */
1503#define WM8995_AIF1CLK_ENA_WIDTH 1 /* AIF1CLK_ENA */
1504
1505/*
1506 * R513 (0x201) - AIF1 Clocking (2)
1507 */
1508#define WM8995_AIF1DAC_DIV_MASK 0x0038 /* AIF1DAC_DIV - [5:3] */
1509#define WM8995_AIF1DAC_DIV_SHIFT 3 /* AIF1DAC_DIV - [5:3] */
1510#define WM8995_AIF1DAC_DIV_WIDTH 3 /* AIF1DAC_DIV - [5:3] */
1511#define WM8995_AIF1ADC_DIV_MASK 0x0007 /* AIF1ADC_DIV - [2:0] */
1512#define WM8995_AIF1ADC_DIV_SHIFT 0 /* AIF1ADC_DIV - [2:0] */
1513#define WM8995_AIF1ADC_DIV_WIDTH 3 /* AIF1ADC_DIV - [2:0] */
1514
1515/*
1516 * R516 (0x204) - AIF2 Clocking (1)
1517 */
1518#define WM8995_AIF2CLK_SRC_MASK 0x0018 /* AIF2CLK_SRC - [4:3] */
1519#define WM8995_AIF2CLK_SRC_SHIFT 3 /* AIF2CLK_SRC - [4:3] */
1520#define WM8995_AIF2CLK_SRC_WIDTH 2 /* AIF2CLK_SRC - [4:3] */
1521#define WM8995_AIF2CLK_INV 0x0004 /* AIF2CLK_INV */
1522#define WM8995_AIF2CLK_INV_MASK 0x0004 /* AIF2CLK_INV */
1523#define WM8995_AIF2CLK_INV_SHIFT 2 /* AIF2CLK_INV */
1524#define WM8995_AIF2CLK_INV_WIDTH 1 /* AIF2CLK_INV */
1525#define WM8995_AIF2CLK_DIV 0x0002 /* AIF2CLK_DIV */
1526#define WM8995_AIF2CLK_DIV_MASK 0x0002 /* AIF2CLK_DIV */
1527#define WM8995_AIF2CLK_DIV_SHIFT 1 /* AIF2CLK_DIV */
1528#define WM8995_AIF2CLK_DIV_WIDTH 1 /* AIF2CLK_DIV */
1529#define WM8995_AIF2CLK_ENA 0x0001 /* AIF2CLK_ENA */
1530#define WM8995_AIF2CLK_ENA_MASK 0x0001 /* AIF2CLK_ENA */
1531#define WM8995_AIF2CLK_ENA_SHIFT 0 /* AIF2CLK_ENA */
1532#define WM8995_AIF2CLK_ENA_WIDTH 1 /* AIF2CLK_ENA */
1533
1534/*
1535 * R517 (0x205) - AIF2 Clocking (2)
1536 */
1537#define WM8995_AIF2DAC_DIV_MASK 0x0038 /* AIF2DAC_DIV - [5:3] */
1538#define WM8995_AIF2DAC_DIV_SHIFT 3 /* AIF2DAC_DIV - [5:3] */
1539#define WM8995_AIF2DAC_DIV_WIDTH 3 /* AIF2DAC_DIV - [5:3] */
1540#define WM8995_AIF2ADC_DIV_MASK 0x0007 /* AIF2ADC_DIV - [2:0] */
1541#define WM8995_AIF2ADC_DIV_SHIFT 0 /* AIF2ADC_DIV - [2:0] */
1542#define WM8995_AIF2ADC_DIV_WIDTH 3 /* AIF2ADC_DIV - [2:0] */
1543
1544/*
1545 * R520 (0x208) - Clocking (1)
1546 */
1547#define WM8995_LFCLK_ENA 0x0020 /* LFCLK_ENA */
1548#define WM8995_LFCLK_ENA_MASK 0x0020 /* LFCLK_ENA */
1549#define WM8995_LFCLK_ENA_SHIFT 5 /* LFCLK_ENA */
1550#define WM8995_LFCLK_ENA_WIDTH 1 /* LFCLK_ENA */
1551#define WM8995_TOCLK_ENA 0x0010 /* TOCLK_ENA */
1552#define WM8995_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */
1553#define WM8995_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */
1554#define WM8995_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
1555#define WM8995_AIF1DSPCLK_ENA 0x0008 /* AIF1DSPCLK_ENA */
1556#define WM8995_AIF1DSPCLK_ENA_MASK 0x0008 /* AIF1DSPCLK_ENA */
1557#define WM8995_AIF1DSPCLK_ENA_SHIFT 3 /* AIF1DSPCLK_ENA */
1558#define WM8995_AIF1DSPCLK_ENA_WIDTH 1 /* AIF1DSPCLK_ENA */
1559#define WM8995_AIF2DSPCLK_ENA 0x0004 /* AIF2DSPCLK_ENA */
1560#define WM8995_AIF2DSPCLK_ENA_MASK 0x0004 /* AIF2DSPCLK_ENA */
1561#define WM8995_AIF2DSPCLK_ENA_SHIFT 2 /* AIF2DSPCLK_ENA */
1562#define WM8995_AIF2DSPCLK_ENA_WIDTH 1 /* AIF2DSPCLK_ENA */
1563#define WM8995_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */
1564#define WM8995_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */
1565#define WM8995_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */
1566#define WM8995_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */
1567#define WM8995_SYSCLK_SRC 0x0001 /* SYSCLK_SRC */
1568#define WM8995_SYSCLK_SRC_MASK 0x0001 /* SYSCLK_SRC */
1569#define WM8995_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC */
1570#define WM8995_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */
1571
1572/*
1573 * R521 (0x209) - Clocking (2)
1574 */
1575#define WM8995_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */
1576#define WM8995_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */
1577#define WM8995_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */
1578#define WM8995_DBCLK_DIV_MASK 0x00F0 /* DBCLK_DIV - [7:4] */
1579#define WM8995_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [7:4] */
1580#define WM8995_DBCLK_DIV_WIDTH 4 /* DBCLK_DIV - [7:4] */
1581#define WM8995_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */
1582#define WM8995_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */
1583#define WM8995_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */
1584
1585/*
1586 * R528 (0x210) - AIF1 Rate
1587 */
1588#define WM8995_AIF1_SR_MASK 0x00F0 /* AIF1_SR - [7:4] */
1589#define WM8995_AIF1_SR_SHIFT 4 /* AIF1_SR - [7:4] */
1590#define WM8995_AIF1_SR_WIDTH 4 /* AIF1_SR - [7:4] */
1591#define WM8995_AIF1CLK_RATE_MASK 0x000F /* AIF1CLK_RATE - [3:0] */
1592#define WM8995_AIF1CLK_RATE_SHIFT 0 /* AIF1CLK_RATE - [3:0] */
1593#define WM8995_AIF1CLK_RATE_WIDTH 4 /* AIF1CLK_RATE - [3:0] */
1594
1595/*
1596 * R529 (0x211) - AIF2 Rate
1597 */
1598#define WM8995_AIF2_SR_MASK 0x00F0 /* AIF2_SR - [7:4] */
1599#define WM8995_AIF2_SR_SHIFT 4 /* AIF2_SR - [7:4] */
1600#define WM8995_AIF2_SR_WIDTH 4 /* AIF2_SR - [7:4] */
1601#define WM8995_AIF2CLK_RATE_MASK 0x000F /* AIF2CLK_RATE - [3:0] */
1602#define WM8995_AIF2CLK_RATE_SHIFT 0 /* AIF2CLK_RATE - [3:0] */
1603#define WM8995_AIF2CLK_RATE_WIDTH 4 /* AIF2CLK_RATE - [3:0] */
1604
1605/*
1606 * R530 (0x212) - Rate Status
1607 */
1608#define WM8995_SR_ERROR_MASK 0x000F /* SR_ERROR - [3:0] */
1609#define WM8995_SR_ERROR_SHIFT 0 /* SR_ERROR - [3:0] */
1610#define WM8995_SR_ERROR_WIDTH 4 /* SR_ERROR - [3:0] */
1611
1612/*
1613 * R544 (0x220) - FLL1 Control (1)
1614 */
1615#define WM8995_FLL1_OSC_ENA 0x0002 /* FLL1_OSC_ENA */
1616#define WM8995_FLL1_OSC_ENA_MASK 0x0002 /* FLL1_OSC_ENA */
1617#define WM8995_FLL1_OSC_ENA_SHIFT 1 /* FLL1_OSC_ENA */
1618#define WM8995_FLL1_OSC_ENA_WIDTH 1 /* FLL1_OSC_ENA */
1619#define WM8995_FLL1_ENA 0x0001 /* FLL1_ENA */
1620#define WM8995_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */
1621#define WM8995_FLL1_ENA_SHIFT 0 /* FLL1_ENA */
1622#define WM8995_FLL1_ENA_WIDTH 1 /* FLL1_ENA */
1623
1624/*
1625 * R545 (0x221) - FLL1 Control (2)
1626 */
1627#define WM8995_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */
1628#define WM8995_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */
1629#define WM8995_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */
1630#define WM8995_FLL1_CTRL_RATE_MASK 0x0070 /* FLL1_CTRL_RATE - [6:4] */
1631#define WM8995_FLL1_CTRL_RATE_SHIFT 4 /* FLL1_CTRL_RATE - [6:4] */
1632#define WM8995_FLL1_CTRL_RATE_WIDTH 3 /* FLL1_CTRL_RATE - [6:4] */
1633#define WM8995_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */
1634#define WM8995_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */
1635#define WM8995_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */
1636
1637/*
1638 * R546 (0x222) - FLL1 Control (3)
1639 */
1640#define WM8995_FLL1_K_MASK 0xFFFF /* FLL1_K - [15:0] */
1641#define WM8995_FLL1_K_SHIFT 0 /* FLL1_K - [15:0] */
1642#define WM8995_FLL1_K_WIDTH 16 /* FLL1_K - [15:0] */
1643
1644/*
1645 * R547 (0x223) - FLL1 Control (4)
1646 */
1647#define WM8995_FLL1_N_MASK 0x7FE0 /* FLL1_N - [14:5] */
1648#define WM8995_FLL1_N_SHIFT 5 /* FLL1_N - [14:5] */
1649#define WM8995_FLL1_N_WIDTH 10 /* FLL1_N - [14:5] */
1650#define WM8995_FLL1_LOOP_GAIN_MASK 0x000F /* FLL1_LOOP_GAIN - [3:0] */
1651#define WM8995_FLL1_LOOP_GAIN_SHIFT 0 /* FLL1_LOOP_GAIN - [3:0] */
1652#define WM8995_FLL1_LOOP_GAIN_WIDTH 4 /* FLL1_LOOP_GAIN - [3:0] */
1653
1654/*
1655 * R548 (0x224) - FLL1 Control (5)
1656 */
1657#define WM8995_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */
1658#define WM8995_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */
1659#define WM8995_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */
1660#define WM8995_FLL1_FRC_NCO 0x0040 /* FLL1_FRC_NCO */
1661#define WM8995_FLL1_FRC_NCO_MASK 0x0040 /* FLL1_FRC_NCO */
1662#define WM8995_FLL1_FRC_NCO_SHIFT 6 /* FLL1_FRC_NCO */
1663#define WM8995_FLL1_FRC_NCO_WIDTH 1 /* FLL1_FRC_NCO */
1664#define WM8995_FLL1_REFCLK_DIV_MASK 0x0018 /* FLL1_REFCLK_DIV - [4:3] */
1665#define WM8995_FLL1_REFCLK_DIV_SHIFT 3 /* FLL1_REFCLK_DIV - [4:3] */
1666#define WM8995_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [4:3] */
1667#define WM8995_FLL1_REFCLK_SRC_MASK 0x0003 /* FLL1_REFCLK_SRC - [1:0] */
1668#define WM8995_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [1:0] */
1669#define WM8995_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */
1670
1671/*
1672 * R576 (0x240) - FLL2 Control (1)
1673 */
1674#define WM8995_FLL2_OSC_ENA 0x0002 /* FLL2_OSC_ENA */
1675#define WM8995_FLL2_OSC_ENA_MASK 0x0002 /* FLL2_OSC_ENA */
1676#define WM8995_FLL2_OSC_ENA_SHIFT 1 /* FLL2_OSC_ENA */
1677#define WM8995_FLL2_OSC_ENA_WIDTH 1 /* FLL2_OSC_ENA */
1678#define WM8995_FLL2_ENA 0x0001 /* FLL2_ENA */
1679#define WM8995_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */
1680#define WM8995_FLL2_ENA_SHIFT 0 /* FLL2_ENA */
1681#define WM8995_FLL2_ENA_WIDTH 1 /* FLL2_ENA */
1682
1683/*
1684 * R577 (0x241) - FLL2 Control (2)
1685 */
1686#define WM8995_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */
1687#define WM8995_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */
1688#define WM8995_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */
1689#define WM8995_FLL2_CTRL_RATE_MASK 0x0070 /* FLL2_CTRL_RATE - [6:4] */
1690#define WM8995_FLL2_CTRL_RATE_SHIFT 4 /* FLL2_CTRL_RATE - [6:4] */
1691#define WM8995_FLL2_CTRL_RATE_WIDTH 3 /* FLL2_CTRL_RATE - [6:4] */
1692#define WM8995_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */
1693#define WM8995_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */
1694#define WM8995_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */
1695
1696/*
1697 * R578 (0x242) - FLL2 Control (3)
1698 */
1699#define WM8995_FLL2_K_MASK 0xFFFF /* FLL2_K - [15:0] */
1700#define WM8995_FLL2_K_SHIFT 0 /* FLL2_K - [15:0] */
1701#define WM8995_FLL2_K_WIDTH 16 /* FLL2_K - [15:0] */
1702
1703/*
1704 * R579 (0x243) - FLL2 Control (4)
1705 */
1706#define WM8995_FLL2_N_MASK 0x7FE0 /* FLL2_N - [14:5] */
1707#define WM8995_FLL2_N_SHIFT 5 /* FLL2_N - [14:5] */
1708#define WM8995_FLL2_N_WIDTH 10 /* FLL2_N - [14:5] */
1709#define WM8995_FLL2_LOOP_GAIN_MASK 0x000F /* FLL2_LOOP_GAIN - [3:0] */
1710#define WM8995_FLL2_LOOP_GAIN_SHIFT 0 /* FLL2_LOOP_GAIN - [3:0] */
1711#define WM8995_FLL2_LOOP_GAIN_WIDTH 4 /* FLL2_LOOP_GAIN - [3:0] */
1712
1713/*
1714 * R580 (0x244) - FLL2 Control (5)
1715 */
1716#define WM8995_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */
1717#define WM8995_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */
1718#define WM8995_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */
1719#define WM8995_FLL2_FRC_NCO 0x0040 /* FLL2_FRC_NCO */
1720#define WM8995_FLL2_FRC_NCO_MASK 0x0040 /* FLL2_FRC_NCO */
1721#define WM8995_FLL2_FRC_NCO_SHIFT 6 /* FLL2_FRC_NCO */
1722#define WM8995_FLL2_FRC_NCO_WIDTH 1 /* FLL2_FRC_NCO */
1723#define WM8995_FLL2_REFCLK_DIV_MASK 0x0018 /* FLL2_REFCLK_DIV - [4:3] */
1724#define WM8995_FLL2_REFCLK_DIV_SHIFT 3 /* FLL2_REFCLK_DIV - [4:3] */
1725#define WM8995_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [4:3] */
1726#define WM8995_FLL2_REFCLK_SRC_MASK 0x0003 /* FLL2_REFCLK_SRC - [1:0] */
1727#define WM8995_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [1:0] */
1728#define WM8995_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */
1729
1730/*
1731 * R768 (0x300) - AIF1 Control (1)
1732 */
1733#define WM8995_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */
1734#define WM8995_AIF1ADCL_SRC_MASK 0x8000 /* AIF1ADCL_SRC */
1735#define WM8995_AIF1ADCL_SRC_SHIFT 15 /* AIF1ADCL_SRC */
1736#define WM8995_AIF1ADCL_SRC_WIDTH 1 /* AIF1ADCL_SRC */
1737#define WM8995_AIF1ADCR_SRC 0x4000 /* AIF1ADCR_SRC */
1738#define WM8995_AIF1ADCR_SRC_MASK 0x4000 /* AIF1ADCR_SRC */
1739#define WM8995_AIF1ADCR_SRC_SHIFT 14 /* AIF1ADCR_SRC */
1740#define WM8995_AIF1ADCR_SRC_WIDTH 1 /* AIF1ADCR_SRC */
1741#define WM8995_AIF1ADC_TDM 0x2000 /* AIF1ADC_TDM */
1742#define WM8995_AIF1ADC_TDM_MASK 0x2000 /* AIF1ADC_TDM */
1743#define WM8995_AIF1ADC_TDM_SHIFT 13 /* AIF1ADC_TDM */
1744#define WM8995_AIF1ADC_TDM_WIDTH 1 /* AIF1ADC_TDM */
1745#define WM8995_AIF1_BCLK_INV 0x0100 /* AIF1_BCLK_INV */
1746#define WM8995_AIF1_BCLK_INV_MASK 0x0100 /* AIF1_BCLK_INV */
1747#define WM8995_AIF1_BCLK_INV_SHIFT 8 /* AIF1_BCLK_INV */
1748#define WM8995_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
1749#define WM8995_AIF1_LRCLK_INV 0x0080 /* AIF1_LRCLK_INV */
1750#define WM8995_AIF1_LRCLK_INV_MASK 0x0080 /* AIF1_LRCLK_INV */
1751#define WM8995_AIF1_LRCLK_INV_SHIFT 7 /* AIF1_LRCLK_INV */
1752#define WM8995_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */
1753#define WM8995_AIF1_WL_MASK 0x0060 /* AIF1_WL - [6:5] */
1754#define WM8995_AIF1_WL_SHIFT 5 /* AIF1_WL - [6:5] */
1755#define WM8995_AIF1_WL_WIDTH 2 /* AIF1_WL - [6:5] */
1756#define WM8995_AIF1_FMT_MASK 0x0018 /* AIF1_FMT - [4:3] */
1757#define WM8995_AIF1_FMT_SHIFT 3 /* AIF1_FMT - [4:3] */
1758#define WM8995_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [4:3] */
1759
1760/*
1761 * R769 (0x301) - AIF1 Control (2)
1762 */
1763#define WM8995_AIF1DACL_SRC 0x8000 /* AIF1DACL_SRC */
1764#define WM8995_AIF1DACL_SRC_MASK 0x8000 /* AIF1DACL_SRC */
1765#define WM8995_AIF1DACL_SRC_SHIFT 15 /* AIF1DACL_SRC */
1766#define WM8995_AIF1DACL_SRC_WIDTH 1 /* AIF1DACL_SRC */
1767#define WM8995_AIF1DACR_SRC 0x4000 /* AIF1DACR_SRC */
1768#define WM8995_AIF1DACR_SRC_MASK 0x4000 /* AIF1DACR_SRC */
1769#define WM8995_AIF1DACR_SRC_SHIFT 14 /* AIF1DACR_SRC */
1770#define WM8995_AIF1DACR_SRC_WIDTH 1 /* AIF1DACR_SRC */
1771#define WM8995_AIF1DAC_BOOST_MASK 0x0C00 /* AIF1DAC_BOOST - [11:10] */
1772#define WM8995_AIF1DAC_BOOST_SHIFT 10 /* AIF1DAC_BOOST - [11:10] */
1773#define WM8995_AIF1DAC_BOOST_WIDTH 2 /* AIF1DAC_BOOST - [11:10] */
1774#define WM8995_AIF1DAC_COMP 0x0010 /* AIF1DAC_COMP */
1775#define WM8995_AIF1DAC_COMP_MASK 0x0010 /* AIF1DAC_COMP */
1776#define WM8995_AIF1DAC_COMP_SHIFT 4 /* AIF1DAC_COMP */
1777#define WM8995_AIF1DAC_COMP_WIDTH 1 /* AIF1DAC_COMP */
1778#define WM8995_AIF1DAC_COMPMODE 0x0008 /* AIF1DAC_COMPMODE */
1779#define WM8995_AIF1DAC_COMPMODE_MASK 0x0008 /* AIF1DAC_COMPMODE */
1780#define WM8995_AIF1DAC_COMPMODE_SHIFT 3 /* AIF1DAC_COMPMODE */
1781#define WM8995_AIF1DAC_COMPMODE_WIDTH 1 /* AIF1DAC_COMPMODE */
1782#define WM8995_AIF1ADC_COMP 0x0004 /* AIF1ADC_COMP */
1783#define WM8995_AIF1ADC_COMP_MASK 0x0004 /* AIF1ADC_COMP */
1784#define WM8995_AIF1ADC_COMP_SHIFT 2 /* AIF1ADC_COMP */
1785#define WM8995_AIF1ADC_COMP_WIDTH 1 /* AIF1ADC_COMP */
1786#define WM8995_AIF1ADC_COMPMODE 0x0002 /* AIF1ADC_COMPMODE */
1787#define WM8995_AIF1ADC_COMPMODE_MASK 0x0002 /* AIF1ADC_COMPMODE */
1788#define WM8995_AIF1ADC_COMPMODE_SHIFT 1 /* AIF1ADC_COMPMODE */
1789#define WM8995_AIF1ADC_COMPMODE_WIDTH 1 /* AIF1ADC_COMPMODE */
1790#define WM8995_AIF1_LOOPBACK 0x0001 /* AIF1_LOOPBACK */
1791#define WM8995_AIF1_LOOPBACK_MASK 0x0001 /* AIF1_LOOPBACK */
1792#define WM8995_AIF1_LOOPBACK_SHIFT 0 /* AIF1_LOOPBACK */
1793#define WM8995_AIF1_LOOPBACK_WIDTH 1 /* AIF1_LOOPBACK */
1794
1795/*
1796 * R770 (0x302) - AIF1 Master/Slave
1797 */
1798#define WM8995_AIF1_TRI 0x8000 /* AIF1_TRI */
1799#define WM8995_AIF1_TRI_MASK 0x8000 /* AIF1_TRI */
1800#define WM8995_AIF1_TRI_SHIFT 15 /* AIF1_TRI */
1801#define WM8995_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
1802#define WM8995_AIF1_MSTR 0x4000 /* AIF1_MSTR */
1803#define WM8995_AIF1_MSTR_MASK 0x4000 /* AIF1_MSTR */
1804#define WM8995_AIF1_MSTR_SHIFT 14 /* AIF1_MSTR */
1805#define WM8995_AIF1_MSTR_WIDTH 1 /* AIF1_MSTR */
1806#define WM8995_AIF1_CLK_FRC 0x2000 /* AIF1_CLK_FRC */
1807#define WM8995_AIF1_CLK_FRC_MASK 0x2000 /* AIF1_CLK_FRC */
1808#define WM8995_AIF1_CLK_FRC_SHIFT 13 /* AIF1_CLK_FRC */
1809#define WM8995_AIF1_CLK_FRC_WIDTH 1 /* AIF1_CLK_FRC */
1810#define WM8995_AIF1_LRCLK_FRC 0x1000 /* AIF1_LRCLK_FRC */
1811#define WM8995_AIF1_LRCLK_FRC_MASK 0x1000 /* AIF1_LRCLK_FRC */
1812#define WM8995_AIF1_LRCLK_FRC_SHIFT 12 /* AIF1_LRCLK_FRC */
1813#define WM8995_AIF1_LRCLK_FRC_WIDTH 1 /* AIF1_LRCLK_FRC */
1814
1815/*
1816 * R771 (0x303) - AIF1 BCLK
1817 */
1818#define WM8995_AIF1_BCLK_DIV_MASK 0x00F0 /* AIF1_BCLK_DIV - [7:4] */
1819#define WM8995_AIF1_BCLK_DIV_SHIFT 4 /* AIF1_BCLK_DIV - [7:4] */
1820#define WM8995_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [7:4] */
1821
1822/*
1823 * R772 (0x304) - AIF1ADC LRCLK
1824 */
1825#define WM8995_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */
1826#define WM8995_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */
1827#define WM8995_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */
1828#define WM8995_AIF1ADC_LRCLK_DIR_WIDTH 1 /* AIF1ADC_LRCLK_DIR */
1829#define WM8995_AIF1ADC_RATE_MASK 0x07FF /* AIF1ADC_RATE - [10:0] */
1830#define WM8995_AIF1ADC_RATE_SHIFT 0 /* AIF1ADC_RATE - [10:0] */
1831#define WM8995_AIF1ADC_RATE_WIDTH 11 /* AIF1ADC_RATE - [10:0] */
1832
1833/*
1834 * R773 (0x305) - AIF1DAC LRCLK
1835 */
1836#define WM8995_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */
1837#define WM8995_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */
1838#define WM8995_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */
1839#define WM8995_AIF1DAC_LRCLK_DIR_WIDTH 1 /* AIF1DAC_LRCLK_DIR */
1840#define WM8995_AIF1DAC_RATE_MASK 0x07FF /* AIF1DAC_RATE - [10:0] */
1841#define WM8995_AIF1DAC_RATE_SHIFT 0 /* AIF1DAC_RATE - [10:0] */
1842#define WM8995_AIF1DAC_RATE_WIDTH 11 /* AIF1DAC_RATE - [10:0] */
1843
1844/*
1845 * R774 (0x306) - AIF1DAC Data
1846 */
1847#define WM8995_AIF1DACL_DAT_INV 0x0002 /* AIF1DACL_DAT_INV */
1848#define WM8995_AIF1DACL_DAT_INV_MASK 0x0002 /* AIF1DACL_DAT_INV */
1849#define WM8995_AIF1DACL_DAT_INV_SHIFT 1 /* AIF1DACL_DAT_INV */
1850#define WM8995_AIF1DACL_DAT_INV_WIDTH 1 /* AIF1DACL_DAT_INV */
1851#define WM8995_AIF1DACR_DAT_INV 0x0001 /* AIF1DACR_DAT_INV */
1852#define WM8995_AIF1DACR_DAT_INV_MASK 0x0001 /* AIF1DACR_DAT_INV */
1853#define WM8995_AIF1DACR_DAT_INV_SHIFT 0 /* AIF1DACR_DAT_INV */
1854#define WM8995_AIF1DACR_DAT_INV_WIDTH 1 /* AIF1DACR_DAT_INV */
1855
1856/*
1857 * R775 (0x307) - AIF1ADC Data
1858 */
1859#define WM8995_AIF1ADCL_DAT_INV 0x0002 /* AIF1ADCL_DAT_INV */
1860#define WM8995_AIF1ADCL_DAT_INV_MASK 0x0002 /* AIF1ADCL_DAT_INV */
1861#define WM8995_AIF1ADCL_DAT_INV_SHIFT 1 /* AIF1ADCL_DAT_INV */
1862#define WM8995_AIF1ADCL_DAT_INV_WIDTH 1 /* AIF1ADCL_DAT_INV */
1863#define WM8995_AIF1ADCR_DAT_INV 0x0001 /* AIF1ADCR_DAT_INV */
1864#define WM8995_AIF1ADCR_DAT_INV_MASK 0x0001 /* AIF1ADCR_DAT_INV */
1865#define WM8995_AIF1ADCR_DAT_INV_SHIFT 0 /* AIF1ADCR_DAT_INV */
1866#define WM8995_AIF1ADCR_DAT_INV_WIDTH 1 /* AIF1ADCR_DAT_INV */
1867
1868/*
1869 * R784 (0x310) - AIF2 Control (1)
1870 */
1871#define WM8995_AIF2ADCL_SRC 0x8000 /* AIF2ADCL_SRC */
1872#define WM8995_AIF2ADCL_SRC_MASK 0x8000 /* AIF2ADCL_SRC */
1873#define WM8995_AIF2ADCL_SRC_SHIFT 15 /* AIF2ADCL_SRC */
1874#define WM8995_AIF2ADCL_SRC_WIDTH 1 /* AIF2ADCL_SRC */
1875#define WM8995_AIF2ADCR_SRC 0x4000 /* AIF2ADCR_SRC */
1876#define WM8995_AIF2ADCR_SRC_MASK 0x4000 /* AIF2ADCR_SRC */
1877#define WM8995_AIF2ADCR_SRC_SHIFT 14 /* AIF2ADCR_SRC */
1878#define WM8995_AIF2ADCR_SRC_WIDTH 1 /* AIF2ADCR_SRC */
1879#define WM8995_AIF2ADC_TDM 0x2000 /* AIF2ADC_TDM */
1880#define WM8995_AIF2ADC_TDM_MASK 0x2000 /* AIF2ADC_TDM */
1881#define WM8995_AIF2ADC_TDM_SHIFT 13 /* AIF2ADC_TDM */
1882#define WM8995_AIF2ADC_TDM_WIDTH 1 /* AIF2ADC_TDM */
1883#define WM8995_AIF2ADC_TDM_CHAN 0x1000 /* AIF2ADC_TDM_CHAN */
1884#define WM8995_AIF2ADC_TDM_CHAN_MASK 0x1000 /* AIF2ADC_TDM_CHAN */
1885#define WM8995_AIF2ADC_TDM_CHAN_SHIFT 12 /* AIF2ADC_TDM_CHAN */
1886#define WM8995_AIF2ADC_TDM_CHAN_WIDTH 1 /* AIF2ADC_TDM_CHAN */
1887#define WM8995_AIF2_BCLK_INV 0x0100 /* AIF2_BCLK_INV */
1888#define WM8995_AIF2_BCLK_INV_MASK 0x0100 /* AIF2_BCLK_INV */
1889#define WM8995_AIF2_BCLK_INV_SHIFT 8 /* AIF2_BCLK_INV */
1890#define WM8995_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */
1891#define WM8995_AIF2_LRCLK_INV 0x0080 /* AIF2_LRCLK_INV */
1892#define WM8995_AIF2_LRCLK_INV_MASK 0x0080 /* AIF2_LRCLK_INV */
1893#define WM8995_AIF2_LRCLK_INV_SHIFT 7 /* AIF2_LRCLK_INV */
1894#define WM8995_AIF2_LRCLK_INV_WIDTH 1 /* AIF2_LRCLK_INV */
1895#define WM8995_AIF2_WL_MASK 0x0060 /* AIF2_WL - [6:5] */
1896#define WM8995_AIF2_WL_SHIFT 5 /* AIF2_WL - [6:5] */
1897#define WM8995_AIF2_WL_WIDTH 2 /* AIF2_WL - [6:5] */
1898#define WM8995_AIF2_FMT_MASK 0x0018 /* AIF2_FMT - [4:3] */
1899#define WM8995_AIF2_FMT_SHIFT 3 /* AIF2_FMT - [4:3] */
1900#define WM8995_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [4:3] */
1901
1902/*
1903 * R785 (0x311) - AIF2 Control (2)
1904 */
1905#define WM8995_AIF2DACL_SRC 0x8000 /* AIF2DACL_SRC */
1906#define WM8995_AIF2DACL_SRC_MASK 0x8000 /* AIF2DACL_SRC */
1907#define WM8995_AIF2DACL_SRC_SHIFT 15 /* AIF2DACL_SRC */
1908#define WM8995_AIF2DACL_SRC_WIDTH 1 /* AIF2DACL_SRC */
1909#define WM8995_AIF2DACR_SRC 0x4000 /* AIF2DACR_SRC */
1910#define WM8995_AIF2DACR_SRC_MASK 0x4000 /* AIF2DACR_SRC */
1911#define WM8995_AIF2DACR_SRC_SHIFT 14 /* AIF2DACR_SRC */
1912#define WM8995_AIF2DACR_SRC_WIDTH 1 /* AIF2DACR_SRC */
1913#define WM8995_AIF2DAC_TDM 0x2000 /* AIF2DAC_TDM */
1914#define WM8995_AIF2DAC_TDM_MASK 0x2000 /* AIF2DAC_TDM */
1915#define WM8995_AIF2DAC_TDM_SHIFT 13 /* AIF2DAC_TDM */
1916#define WM8995_AIF2DAC_TDM_WIDTH 1 /* AIF2DAC_TDM */
1917#define WM8995_AIF2DAC_TDM_CHAN 0x1000 /* AIF2DAC_TDM_CHAN */
1918#define WM8995_AIF2DAC_TDM_CHAN_MASK 0x1000 /* AIF2DAC_TDM_CHAN */
1919#define WM8995_AIF2DAC_TDM_CHAN_SHIFT 12 /* AIF2DAC_TDM_CHAN */
1920#define WM8995_AIF2DAC_TDM_CHAN_WIDTH 1 /* AIF2DAC_TDM_CHAN */
1921#define WM8995_AIF2DAC_BOOST_MASK 0x0C00 /* AIF2DAC_BOOST - [11:10] */
1922#define WM8995_AIF2DAC_BOOST_SHIFT 10 /* AIF2DAC_BOOST - [11:10] */
1923#define WM8995_AIF2DAC_BOOST_WIDTH 2 /* AIF2DAC_BOOST - [11:10] */
1924#define WM8995_AIF2DAC_COMP 0x0010 /* AIF2DAC_COMP */
1925#define WM8995_AIF2DAC_COMP_MASK 0x0010 /* AIF2DAC_COMP */
1926#define WM8995_AIF2DAC_COMP_SHIFT 4 /* AIF2DAC_COMP */
1927#define WM8995_AIF2DAC_COMP_WIDTH 1 /* AIF2DAC_COMP */
1928#define WM8995_AIF2DAC_COMPMODE 0x0008 /* AIF2DAC_COMPMODE */
1929#define WM8995_AIF2DAC_COMPMODE_MASK 0x0008 /* AIF2DAC_COMPMODE */
1930#define WM8995_AIF2DAC_COMPMODE_SHIFT 3 /* AIF2DAC_COMPMODE */
1931#define WM8995_AIF2DAC_COMPMODE_WIDTH 1 /* AIF2DAC_COMPMODE */
1932#define WM8995_AIF2ADC_COMP 0x0004 /* AIF2ADC_COMP */
1933#define WM8995_AIF2ADC_COMP_MASK 0x0004 /* AIF2ADC_COMP */
1934#define WM8995_AIF2ADC_COMP_SHIFT 2 /* AIF2ADC_COMP */
1935#define WM8995_AIF2ADC_COMP_WIDTH 1 /* AIF2ADC_COMP */
1936#define WM8995_AIF2ADC_COMPMODE 0x0002 /* AIF2ADC_COMPMODE */
1937#define WM8995_AIF2ADC_COMPMODE_MASK 0x0002 /* AIF2ADC_COMPMODE */
1938#define WM8995_AIF2ADC_COMPMODE_SHIFT 1 /* AIF2ADC_COMPMODE */
1939#define WM8995_AIF2ADC_COMPMODE_WIDTH 1 /* AIF2ADC_COMPMODE */
1940#define WM8995_AIF2_LOOPBACK 0x0001 /* AIF2_LOOPBACK */
1941#define WM8995_AIF2_LOOPBACK_MASK 0x0001 /* AIF2_LOOPBACK */
1942#define WM8995_AIF2_LOOPBACK_SHIFT 0 /* AIF2_LOOPBACK */
1943#define WM8995_AIF2_LOOPBACK_WIDTH 1 /* AIF2_LOOPBACK */
1944
1945/*
1946 * R786 (0x312) - AIF2 Master/Slave
1947 */
1948#define WM8995_AIF2_TRI 0x8000 /* AIF2_TRI */
1949#define WM8995_AIF2_TRI_MASK 0x8000 /* AIF2_TRI */
1950#define WM8995_AIF2_TRI_SHIFT 15 /* AIF2_TRI */
1951#define WM8995_AIF2_TRI_WIDTH 1 /* AIF2_TRI */
1952#define WM8995_AIF2_MSTR 0x4000 /* AIF2_MSTR */
1953#define WM8995_AIF2_MSTR_MASK 0x4000 /* AIF2_MSTR */
1954#define WM8995_AIF2_MSTR_SHIFT 14 /* AIF2_MSTR */
1955#define WM8995_AIF2_MSTR_WIDTH 1 /* AIF2_MSTR */
1956#define WM8995_AIF2_CLK_FRC 0x2000 /* AIF2_CLK_FRC */
1957#define WM8995_AIF2_CLK_FRC_MASK 0x2000 /* AIF2_CLK_FRC */
1958#define WM8995_AIF2_CLK_FRC_SHIFT 13 /* AIF2_CLK_FRC */
1959#define WM8995_AIF2_CLK_FRC_WIDTH 1 /* AIF2_CLK_FRC */
1960#define WM8995_AIF2_LRCLK_FRC 0x1000 /* AIF2_LRCLK_FRC */
1961#define WM8995_AIF2_LRCLK_FRC_MASK 0x1000 /* AIF2_LRCLK_FRC */
1962#define WM8995_AIF2_LRCLK_FRC_SHIFT 12 /* AIF2_LRCLK_FRC */
1963#define WM8995_AIF2_LRCLK_FRC_WIDTH 1 /* AIF2_LRCLK_FRC */
1964
1965/*
1966 * R787 (0x313) - AIF2 BCLK
1967 */
1968#define WM8995_AIF2_BCLK_DIV_MASK 0x00F0 /* AIF2_BCLK_DIV - [7:4] */
1969#define WM8995_AIF2_BCLK_DIV_SHIFT 4 /* AIF2_BCLK_DIV - [7:4] */
1970#define WM8995_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [7:4] */
1971
1972/*
1973 * R788 (0x314) - AIF2ADC LRCLK
1974 */
1975#define WM8995_AIF2ADC_LRCLK_DIR 0x0800 /* AIF2ADC_LRCLK_DIR */
1976#define WM8995_AIF2ADC_LRCLK_DIR_MASK 0x0800 /* AIF2ADC_LRCLK_DIR */
1977#define WM8995_AIF2ADC_LRCLK_DIR_SHIFT 11 /* AIF2ADC_LRCLK_DIR */
1978#define WM8995_AIF2ADC_LRCLK_DIR_WIDTH 1 /* AIF2ADC_LRCLK_DIR */
1979#define WM8995_AIF2ADC_RATE_MASK 0x07FF /* AIF2ADC_RATE - [10:0] */
1980#define WM8995_AIF2ADC_RATE_SHIFT 0 /* AIF2ADC_RATE - [10:0] */
1981#define WM8995_AIF2ADC_RATE_WIDTH 11 /* AIF2ADC_RATE - [10:0] */
1982
1983/*
1984 * R789 (0x315) - AIF2DAC LRCLK
1985 */
1986#define WM8995_AIF2DAC_LRCLK_DIR 0x0800 /* AIF2DAC_LRCLK_DIR */
1987#define WM8995_AIF2DAC_LRCLK_DIR_MASK 0x0800 /* AIF2DAC_LRCLK_DIR */
1988#define WM8995_AIF2DAC_LRCLK_DIR_SHIFT 11 /* AIF2DAC_LRCLK_DIR */
1989#define WM8995_AIF2DAC_LRCLK_DIR_WIDTH 1 /* AIF2DAC_LRCLK_DIR */
1990#define WM8995_AIF2DAC_RATE_MASK 0x07FF /* AIF2DAC_RATE - [10:0] */
1991#define WM8995_AIF2DAC_RATE_SHIFT 0 /* AIF2DAC_RATE - [10:0] */
1992#define WM8995_AIF2DAC_RATE_WIDTH 11 /* AIF2DAC_RATE - [10:0] */
1993
1994/*
1995 * R790 (0x316) - AIF2DAC Data
1996 */
1997#define WM8995_AIF2DACL_DAT_INV 0x0002 /* AIF2DACL_DAT_INV */
1998#define WM8995_AIF2DACL_DAT_INV_MASK 0x0002 /* AIF2DACL_DAT_INV */
1999#define WM8995_AIF2DACL_DAT_INV_SHIFT 1 /* AIF2DACL_DAT_INV */
2000#define WM8995_AIF2DACL_DAT_INV_WIDTH 1 /* AIF2DACL_DAT_INV */
2001#define WM8995_AIF2DACR_DAT_INV 0x0001 /* AIF2DACR_DAT_INV */
2002#define WM8995_AIF2DACR_DAT_INV_MASK 0x0001 /* AIF2DACR_DAT_INV */
2003#define WM8995_AIF2DACR_DAT_INV_SHIFT 0 /* AIF2DACR_DAT_INV */
2004#define WM8995_AIF2DACR_DAT_INV_WIDTH 1 /* AIF2DACR_DAT_INV */
2005
2006/*
2007 * R791 (0x317) - AIF2ADC Data
2008 */
2009#define WM8995_AIF2ADCL_DAT_INV 0x0002 /* AIF2ADCL_DAT_INV */
2010#define WM8995_AIF2ADCL_DAT_INV_MASK 0x0002 /* AIF2ADCL_DAT_INV */
2011#define WM8995_AIF2ADCL_DAT_INV_SHIFT 1 /* AIF2ADCL_DAT_INV */
2012#define WM8995_AIF2ADCL_DAT_INV_WIDTH 1 /* AIF2ADCL_DAT_INV */
2013#define WM8995_AIF2ADCR_DAT_INV 0x0001 /* AIF2ADCR_DAT_INV */
2014#define WM8995_AIF2ADCR_DAT_INV_MASK 0x0001 /* AIF2ADCR_DAT_INV */
2015#define WM8995_AIF2ADCR_DAT_INV_SHIFT 0 /* AIF2ADCR_DAT_INV */
2016#define WM8995_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */
2017
2018/*
2019 * R1024 (0x400) - AIF1 ADC1 Left Volume
2020 */
2021#define WM8995_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */
2022#define WM8995_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */
2023#define WM8995_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */
2024#define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */
2025#define WM8995_AIF1ADC1L_VOL_MASK 0x00FF /* AIF1ADC1L_VOL - [7:0] */
2026#define WM8995_AIF1ADC1L_VOL_SHIFT 0 /* AIF1ADC1L_VOL - [7:0] */
2027#define WM8995_AIF1ADC1L_VOL_WIDTH 8 /* AIF1ADC1L_VOL - [7:0] */
2028
2029/*
2030 * R1025 (0x401) - AIF1 ADC1 Right Volume
2031 */
2032#define WM8995_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */
2033#define WM8995_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */
2034#define WM8995_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */
2035#define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */
2036#define WM8995_AIF1ADC1R_VOL_MASK 0x00FF /* AIF1ADC1R_VOL - [7:0] */
2037#define WM8995_AIF1ADC1R_VOL_SHIFT 0 /* AIF1ADC1R_VOL - [7:0] */
2038#define WM8995_AIF1ADC1R_VOL_WIDTH 8 /* AIF1ADC1R_VOL - [7:0] */
2039
2040/*
2041 * R1026 (0x402) - AIF1 DAC1 Left Volume
2042 */
2043#define WM8995_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */
2044#define WM8995_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */
2045#define WM8995_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */
2046#define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */
2047#define WM8995_AIF1DAC1L_VOL_MASK 0x00FF /* AIF1DAC1L_VOL - [7:0] */
2048#define WM8995_AIF1DAC1L_VOL_SHIFT 0 /* AIF1DAC1L_VOL - [7:0] */
2049#define WM8995_AIF1DAC1L_VOL_WIDTH 8 /* AIF1DAC1L_VOL - [7:0] */
2050
2051/*
2052 * R1027 (0x403) - AIF1 DAC1 Right Volume
2053 */
2054#define WM8995_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */
2055#define WM8995_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */
2056#define WM8995_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */
2057#define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */
2058#define WM8995_AIF1DAC1R_VOL_MASK 0x00FF /* AIF1DAC1R_VOL - [7:0] */
2059#define WM8995_AIF1DAC1R_VOL_SHIFT 0 /* AIF1DAC1R_VOL - [7:0] */
2060#define WM8995_AIF1DAC1R_VOL_WIDTH 8 /* AIF1DAC1R_VOL - [7:0] */
2061
2062/*
2063 * R1028 (0x404) - AIF1 ADC2 Left Volume
2064 */
2065#define WM8995_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */
2066#define WM8995_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */
2067#define WM8995_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */
2068#define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */
2069#define WM8995_AIF1ADC2L_VOL_MASK 0x00FF /* AIF1ADC2L_VOL - [7:0] */
2070#define WM8995_AIF1ADC2L_VOL_SHIFT 0 /* AIF1ADC2L_VOL - [7:0] */
2071#define WM8995_AIF1ADC2L_VOL_WIDTH 8 /* AIF1ADC2L_VOL - [7:0] */
2072
2073/*
2074 * R1029 (0x405) - AIF1 ADC2 Right Volume
2075 */
2076#define WM8995_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */
2077#define WM8995_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */
2078#define WM8995_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */
2079#define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */
2080#define WM8995_AIF1ADC2R_VOL_MASK 0x00FF /* AIF1ADC2R_VOL - [7:0] */
2081#define WM8995_AIF1ADC2R_VOL_SHIFT 0 /* AIF1ADC2R_VOL - [7:0] */
2082#define WM8995_AIF1ADC2R_VOL_WIDTH 8 /* AIF1ADC2R_VOL - [7:0] */
2083
2084/*
2085 * R1030 (0x406) - AIF1 DAC2 Left Volume
2086 */
2087#define WM8995_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */
2088#define WM8995_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */
2089#define WM8995_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */
2090#define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */
2091#define WM8995_AIF1DAC2L_VOL_MASK 0x00FF /* AIF1DAC2L_VOL - [7:0] */
2092#define WM8995_AIF1DAC2L_VOL_SHIFT 0 /* AIF1DAC2L_VOL - [7:0] */
2093#define WM8995_AIF1DAC2L_VOL_WIDTH 8 /* AIF1DAC2L_VOL - [7:0] */
2094
2095/*
2096 * R1031 (0x407) - AIF1 DAC2 Right Volume
2097 */
2098#define WM8995_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */
2099#define WM8995_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */
2100#define WM8995_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */
2101#define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */
2102#define WM8995_AIF1DAC2R_VOL_MASK 0x00FF /* AIF1DAC2R_VOL - [7:0] */
2103#define WM8995_AIF1DAC2R_VOL_SHIFT 0 /* AIF1DAC2R_VOL - [7:0] */
2104#define WM8995_AIF1DAC2R_VOL_WIDTH 8 /* AIF1DAC2R_VOL - [7:0] */
2105
2106/*
2107 * R1040 (0x410) - AIF1 ADC1 Filters
2108 */
2109#define WM8995_AIF1ADC_4FS 0x8000 /* AIF1ADC_4FS */
2110#define WM8995_AIF1ADC_4FS_MASK 0x8000 /* AIF1ADC_4FS */
2111#define WM8995_AIF1ADC_4FS_SHIFT 15 /* AIF1ADC_4FS */
2112#define WM8995_AIF1ADC_4FS_WIDTH 1 /* AIF1ADC_4FS */
2113#define WM8995_AIF1ADC1L_HPF 0x1000 /* AIF1ADC1L_HPF */
2114#define WM8995_AIF1ADC1L_HPF_MASK 0x1000 /* AIF1ADC1L_HPF */
2115#define WM8995_AIF1ADC1L_HPF_SHIFT 12 /* AIF1ADC1L_HPF */
2116#define WM8995_AIF1ADC1L_HPF_WIDTH 1 /* AIF1ADC1L_HPF */
2117#define WM8995_AIF1ADC1R_HPF 0x0800 /* AIF1ADC1R_HPF */
2118#define WM8995_AIF1ADC1R_HPF_MASK 0x0800 /* AIF1ADC1R_HPF */
2119#define WM8995_AIF1ADC1R_HPF_SHIFT 11 /* AIF1ADC1R_HPF */
2120#define WM8995_AIF1ADC1R_HPF_WIDTH 1 /* AIF1ADC1R_HPF */
2121#define WM8995_AIF1ADC1_HPF_MODE 0x0008 /* AIF1ADC1_HPF_MODE */
2122#define WM8995_AIF1ADC1_HPF_MODE_MASK 0x0008 /* AIF1ADC1_HPF_MODE */
2123#define WM8995_AIF1ADC1_HPF_MODE_SHIFT 3 /* AIF1ADC1_HPF_MODE */
2124#define WM8995_AIF1ADC1_HPF_MODE_WIDTH 1 /* AIF1ADC1_HPF_MODE */
2125#define WM8995_AIF1ADC1_HPF_CUT_MASK 0x0007 /* AIF1ADC1_HPF_CUT - [2:0] */
2126#define WM8995_AIF1ADC1_HPF_CUT_SHIFT 0 /* AIF1ADC1_HPF_CUT - [2:0] */
2127#define WM8995_AIF1ADC1_HPF_CUT_WIDTH 3 /* AIF1ADC1_HPF_CUT - [2:0] */
2128
2129/*
2130 * R1041 (0x411) - AIF1 ADC2 Filters
2131 */
2132#define WM8995_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */
2133#define WM8995_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */
2134#define WM8995_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */
2135#define WM8995_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */
2136#define WM8995_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */
2137#define WM8995_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */
2138#define WM8995_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */
2139#define WM8995_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */
2140#define WM8995_AIF1ADC2_HPF_MODE 0x0008 /* AIF1ADC2_HPF_MODE */
2141#define WM8995_AIF1ADC2_HPF_MODE_MASK 0x0008 /* AIF1ADC2_HPF_MODE */
2142#define WM8995_AIF1ADC2_HPF_MODE_SHIFT 3 /* AIF1ADC2_HPF_MODE */
2143#define WM8995_AIF1ADC2_HPF_MODE_WIDTH 1 /* AIF1ADC2_HPF_MODE */
2144#define WM8995_AIF1ADC2_HPF_CUT_MASK 0x0007 /* AIF1ADC2_HPF_CUT - [2:0] */
2145#define WM8995_AIF1ADC2_HPF_CUT_SHIFT 0 /* AIF1ADC2_HPF_CUT - [2:0] */
2146#define WM8995_AIF1ADC2_HPF_CUT_WIDTH 3 /* AIF1ADC2_HPF_CUT - [2:0] */
2147
2148/*
2149 * R1056 (0x420) - AIF1 DAC1 Filters (1)
2150 */
2151#define WM8995_AIF1DAC1_MUTE 0x0200 /* AIF1DAC1_MUTE */
2152#define WM8995_AIF1DAC1_MUTE_MASK 0x0200 /* AIF1DAC1_MUTE */
2153#define WM8995_AIF1DAC1_MUTE_SHIFT 9 /* AIF1DAC1_MUTE */
2154#define WM8995_AIF1DAC1_MUTE_WIDTH 1 /* AIF1DAC1_MUTE */
2155#define WM8995_AIF1DAC1_MONO 0x0080 /* AIF1DAC1_MONO */
2156#define WM8995_AIF1DAC1_MONO_MASK 0x0080 /* AIF1DAC1_MONO */
2157#define WM8995_AIF1DAC1_MONO_SHIFT 7 /* AIF1DAC1_MONO */
2158#define WM8995_AIF1DAC1_MONO_WIDTH 1 /* AIF1DAC1_MONO */
2159#define WM8995_AIF1DAC1_MUTERATE 0x0020 /* AIF1DAC1_MUTERATE */
2160#define WM8995_AIF1DAC1_MUTERATE_MASK 0x0020 /* AIF1DAC1_MUTERATE */
2161#define WM8995_AIF1DAC1_MUTERATE_SHIFT 5 /* AIF1DAC1_MUTERATE */
2162#define WM8995_AIF1DAC1_MUTERATE_WIDTH 1 /* AIF1DAC1_MUTERATE */
2163#define WM8995_AIF1DAC1_UNMUTE_RAMP 0x0010 /* AIF1DAC1_UNMUTE_RAMP */
2164#define WM8995_AIF1DAC1_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC1_UNMUTE_RAMP */
2165#define WM8995_AIF1DAC1_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC1_UNMUTE_RAMP */
2166#define WM8995_AIF1DAC1_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC1_UNMUTE_RAMP */
2167#define WM8995_AIF1DAC1_DEEMP_MASK 0x0006 /* AIF1DAC1_DEEMP - [2:1] */
2168#define WM8995_AIF1DAC1_DEEMP_SHIFT 1 /* AIF1DAC1_DEEMP - [2:1] */
2169#define WM8995_AIF1DAC1_DEEMP_WIDTH 2 /* AIF1DAC1_DEEMP - [2:1] */
2170
2171/*
2172 * R1057 (0x421) - AIF1 DAC1 Filters (2)
2173 */
2174#define WM8995_AIF1DAC1_3D_GAIN_MASK 0x3E00 /* AIF1DAC1_3D_GAIN - [13:9] */
2175#define WM8995_AIF1DAC1_3D_GAIN_SHIFT 9 /* AIF1DAC1_3D_GAIN - [13:9] */
2176#define WM8995_AIF1DAC1_3D_GAIN_WIDTH 5 /* AIF1DAC1_3D_GAIN - [13:9] */
2177#define WM8995_AIF1DAC1_3D_ENA 0x0100 /* AIF1DAC1_3D_ENA */
2178#define WM8995_AIF1DAC1_3D_ENA_MASK 0x0100 /* AIF1DAC1_3D_ENA */
2179#define WM8995_AIF1DAC1_3D_ENA_SHIFT 8 /* AIF1DAC1_3D_ENA */
2180#define WM8995_AIF1DAC1_3D_ENA_WIDTH 1 /* AIF1DAC1_3D_ENA */
2181
2182/*
2183 * R1058 (0x422) - AIF1 DAC2 Filters (1)
2184 */
2185#define WM8995_AIF1DAC2_MUTE 0x0200 /* AIF1DAC2_MUTE */
2186#define WM8995_AIF1DAC2_MUTE_MASK 0x0200 /* AIF1DAC2_MUTE */
2187#define WM8995_AIF1DAC2_MUTE_SHIFT 9 /* AIF1DAC2_MUTE */
2188#define WM8995_AIF1DAC2_MUTE_WIDTH 1 /* AIF1DAC2_MUTE */
2189#define WM8995_AIF1DAC2_MONO 0x0080 /* AIF1DAC2_MONO */
2190#define WM8995_AIF1DAC2_MONO_MASK 0x0080 /* AIF1DAC2_MONO */
2191#define WM8995_AIF1DAC2_MONO_SHIFT 7 /* AIF1DAC2_MONO */
2192#define WM8995_AIF1DAC2_MONO_WIDTH 1 /* AIF1DAC2_MONO */
2193#define WM8995_AIF1DAC2_MUTERATE 0x0020 /* AIF1DAC2_MUTERATE */
2194#define WM8995_AIF1DAC2_MUTERATE_MASK 0x0020 /* AIF1DAC2_MUTERATE */
2195#define WM8995_AIF1DAC2_MUTERATE_SHIFT 5 /* AIF1DAC2_MUTERATE */
2196#define WM8995_AIF1DAC2_MUTERATE_WIDTH 1 /* AIF1DAC2_MUTERATE */
2197#define WM8995_AIF1DAC2_UNMUTE_RAMP 0x0010 /* AIF1DAC2_UNMUTE_RAMP */
2198#define WM8995_AIF1DAC2_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC2_UNMUTE_RAMP */
2199#define WM8995_AIF1DAC2_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC2_UNMUTE_RAMP */
2200#define WM8995_AIF1DAC2_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC2_UNMUTE_RAMP */
2201#define WM8995_AIF1DAC2_DEEMP_MASK 0x0006 /* AIF1DAC2_DEEMP - [2:1] */
2202#define WM8995_AIF1DAC2_DEEMP_SHIFT 1 /* AIF1DAC2_DEEMP - [2:1] */
2203#define WM8995_AIF1DAC2_DEEMP_WIDTH 2 /* AIF1DAC2_DEEMP - [2:1] */
2204
2205/*
2206 * R1059 (0x423) - AIF1 DAC2 Filters (2)
2207 */
2208#define WM8995_AIF1DAC2_3D_GAIN_MASK 0x3E00 /* AIF1DAC2_3D_GAIN - [13:9] */
2209#define WM8995_AIF1DAC2_3D_GAIN_SHIFT 9 /* AIF1DAC2_3D_GAIN - [13:9] */
2210#define WM8995_AIF1DAC2_3D_GAIN_WIDTH 5 /* AIF1DAC2_3D_GAIN - [13:9] */
2211#define WM8995_AIF1DAC2_3D_ENA 0x0100 /* AIF1DAC2_3D_ENA */
2212#define WM8995_AIF1DAC2_3D_ENA_MASK 0x0100 /* AIF1DAC2_3D_ENA */
2213#define WM8995_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */
2214#define WM8995_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */
2215
2216/*
2217 * R1088 (0x440) - AIF1 DRC1 (1)
2218 */
2219#define WM8995_AIF1DRC1_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
2220#define WM8995_AIF1DRC1_SIG_DET_RMS_SHIFT 11 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
2221#define WM8995_AIF1DRC1_SIG_DET_RMS_WIDTH 5 /* AIF1DRC1_SIG_DET_RMS - [15:11] */
2222#define WM8995_AIF1DRC1_SIG_DET_PK_MASK 0x0600 /* AIF1DRC1_SIG_DET_PK - [10:9] */
2223#define WM8995_AIF1DRC1_SIG_DET_PK_SHIFT 9 /* AIF1DRC1_SIG_DET_PK - [10:9] */
2224#define WM8995_AIF1DRC1_SIG_DET_PK_WIDTH 2 /* AIF1DRC1_SIG_DET_PK - [10:9] */
2225#define WM8995_AIF1DRC1_NG_ENA 0x0100 /* AIF1DRC1_NG_ENA */
2226#define WM8995_AIF1DRC1_NG_ENA_MASK 0x0100 /* AIF1DRC1_NG_ENA */
2227#define WM8995_AIF1DRC1_NG_ENA_SHIFT 8 /* AIF1DRC1_NG_ENA */
2228#define WM8995_AIF1DRC1_NG_ENA_WIDTH 1 /* AIF1DRC1_NG_ENA */
2229#define WM8995_AIF1DRC1_SIG_DET_MODE 0x0080 /* AIF1DRC1_SIG_DET_MODE */
2230#define WM8995_AIF1DRC1_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC1_SIG_DET_MODE */
2231#define WM8995_AIF1DRC1_SIG_DET_MODE_SHIFT 7 /* AIF1DRC1_SIG_DET_MODE */
2232#define WM8995_AIF1DRC1_SIG_DET_MODE_WIDTH 1 /* AIF1DRC1_SIG_DET_MODE */
2233#define WM8995_AIF1DRC1_SIG_DET 0x0040 /* AIF1DRC1_SIG_DET */
2234#define WM8995_AIF1DRC1_SIG_DET_MASK 0x0040 /* AIF1DRC1_SIG_DET */
2235#define WM8995_AIF1DRC1_SIG_DET_SHIFT 6 /* AIF1DRC1_SIG_DET */
2236#define WM8995_AIF1DRC1_SIG_DET_WIDTH 1 /* AIF1DRC1_SIG_DET */
2237#define WM8995_AIF1DRC1_KNEE2_OP_ENA 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */
2238#define WM8995_AIF1DRC1_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */
2239#define WM8995_AIF1DRC1_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC1_KNEE2_OP_ENA */
2240#define WM8995_AIF1DRC1_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC1_KNEE2_OP_ENA */
2241#define WM8995_AIF1DRC1_QR 0x0010 /* AIF1DRC1_QR */
2242#define WM8995_AIF1DRC1_QR_MASK 0x0010 /* AIF1DRC1_QR */
2243#define WM8995_AIF1DRC1_QR_SHIFT 4 /* AIF1DRC1_QR */
2244#define WM8995_AIF1DRC1_QR_WIDTH 1 /* AIF1DRC1_QR */
2245#define WM8995_AIF1DRC1_ANTICLIP 0x0008 /* AIF1DRC1_ANTICLIP */
2246#define WM8995_AIF1DRC1_ANTICLIP_MASK 0x0008 /* AIF1DRC1_ANTICLIP */
2247#define WM8995_AIF1DRC1_ANTICLIP_SHIFT 3 /* AIF1DRC1_ANTICLIP */
2248#define WM8995_AIF1DRC1_ANTICLIP_WIDTH 1 /* AIF1DRC1_ANTICLIP */
2249#define WM8995_AIF1DAC1_DRC_ENA 0x0004 /* AIF1DAC1_DRC_ENA */
2250#define WM8995_AIF1DAC1_DRC_ENA_MASK 0x0004 /* AIF1DAC1_DRC_ENA */
2251#define WM8995_AIF1DAC1_DRC_ENA_SHIFT 2 /* AIF1DAC1_DRC_ENA */
2252#define WM8995_AIF1DAC1_DRC_ENA_WIDTH 1 /* AIF1DAC1_DRC_ENA */
2253#define WM8995_AIF1ADC1L_DRC_ENA 0x0002 /* AIF1ADC1L_DRC_ENA */
2254#define WM8995_AIF1ADC1L_DRC_ENA_MASK 0x0002 /* AIF1ADC1L_DRC_ENA */
2255#define WM8995_AIF1ADC1L_DRC_ENA_SHIFT 1 /* AIF1ADC1L_DRC_ENA */
2256#define WM8995_AIF1ADC1L_DRC_ENA_WIDTH 1 /* AIF1ADC1L_DRC_ENA */
2257#define WM8995_AIF1ADC1R_DRC_ENA 0x0001 /* AIF1ADC1R_DRC_ENA */
2258#define WM8995_AIF1ADC1R_DRC_ENA_MASK 0x0001 /* AIF1ADC1R_DRC_ENA */
2259#define WM8995_AIF1ADC1R_DRC_ENA_SHIFT 0 /* AIF1ADC1R_DRC_ENA */
2260#define WM8995_AIF1ADC1R_DRC_ENA_WIDTH 1 /* AIF1ADC1R_DRC_ENA */
2261
2262/*
2263 * R1089 (0x441) - AIF1 DRC1 (2)
2264 */
2265#define WM8995_AIF1DRC1_ATK_MASK 0x1E00 /* AIF1DRC1_ATK - [12:9] */
2266#define WM8995_AIF1DRC1_ATK_SHIFT 9 /* AIF1DRC1_ATK - [12:9] */
2267#define WM8995_AIF1DRC1_ATK_WIDTH 4 /* AIF1DRC1_ATK - [12:9] */
2268#define WM8995_AIF1DRC1_DCY_MASK 0x01E0 /* AIF1DRC1_DCY - [8:5] */
2269#define WM8995_AIF1DRC1_DCY_SHIFT 5 /* AIF1DRC1_DCY - [8:5] */
2270#define WM8995_AIF1DRC1_DCY_WIDTH 4 /* AIF1DRC1_DCY - [8:5] */
2271#define WM8995_AIF1DRC1_MINGAIN_MASK 0x001C /* AIF1DRC1_MINGAIN - [4:2] */
2272#define WM8995_AIF1DRC1_MINGAIN_SHIFT 2 /* AIF1DRC1_MINGAIN - [4:2] */
2273#define WM8995_AIF1DRC1_MINGAIN_WIDTH 3 /* AIF1DRC1_MINGAIN - [4:2] */
2274#define WM8995_AIF1DRC1_MAXGAIN_MASK 0x0003 /* AIF1DRC1_MAXGAIN - [1:0] */
2275#define WM8995_AIF1DRC1_MAXGAIN_SHIFT 0 /* AIF1DRC1_MAXGAIN - [1:0] */
2276#define WM8995_AIF1DRC1_MAXGAIN_WIDTH 2 /* AIF1DRC1_MAXGAIN - [1:0] */
2277
2278/*
2279 * R1090 (0x442) - AIF1 DRC1 (3)
2280 */
2281#define WM8995_AIF1DRC1_NG_MINGAIN_MASK 0xF000 /* AIF1DRC1_NG_MINGAIN - [15:12] */
2282#define WM8995_AIF1DRC1_NG_MINGAIN_SHIFT 12 /* AIF1DRC1_NG_MINGAIN - [15:12] */
2283#define WM8995_AIF1DRC1_NG_MINGAIN_WIDTH 4 /* AIF1DRC1_NG_MINGAIN - [15:12] */
2284#define WM8995_AIF1DRC1_NG_EXP_MASK 0x0C00 /* AIF1DRC1_NG_EXP - [11:10] */
2285#define WM8995_AIF1DRC1_NG_EXP_SHIFT 10 /* AIF1DRC1_NG_EXP - [11:10] */
2286#define WM8995_AIF1DRC1_NG_EXP_WIDTH 2 /* AIF1DRC1_NG_EXP - [11:10] */
2287#define WM8995_AIF1DRC1_QR_THR_MASK 0x0300 /* AIF1DRC1_QR_THR - [9:8] */
2288#define WM8995_AIF1DRC1_QR_THR_SHIFT 8 /* AIF1DRC1_QR_THR - [9:8] */
2289#define WM8995_AIF1DRC1_QR_THR_WIDTH 2 /* AIF1DRC1_QR_THR - [9:8] */
2290#define WM8995_AIF1DRC1_QR_DCY_MASK 0x00C0 /* AIF1DRC1_QR_DCY - [7:6] */
2291#define WM8995_AIF1DRC1_QR_DCY_SHIFT 6 /* AIF1DRC1_QR_DCY - [7:6] */
2292#define WM8995_AIF1DRC1_QR_DCY_WIDTH 2 /* AIF1DRC1_QR_DCY - [7:6] */
2293#define WM8995_AIF1DRC1_HI_COMP_MASK 0x0038 /* AIF1DRC1_HI_COMP - [5:3] */
2294#define WM8995_AIF1DRC1_HI_COMP_SHIFT 3 /* AIF1DRC1_HI_COMP - [5:3] */
2295#define WM8995_AIF1DRC1_HI_COMP_WIDTH 3 /* AIF1DRC1_HI_COMP - [5:3] */
2296#define WM8995_AIF1DRC1_LO_COMP_MASK 0x0007 /* AIF1DRC1_LO_COMP - [2:0] */
2297#define WM8995_AIF1DRC1_LO_COMP_SHIFT 0 /* AIF1DRC1_LO_COMP - [2:0] */
2298#define WM8995_AIF1DRC1_LO_COMP_WIDTH 3 /* AIF1DRC1_LO_COMP - [2:0] */
2299
2300/*
2301 * R1091 (0x443) - AIF1 DRC1 (4)
2302 */
2303#define WM8995_AIF1DRC1_KNEE_IP_MASK 0x07E0 /* AIF1DRC1_KNEE_IP - [10:5] */
2304#define WM8995_AIF1DRC1_KNEE_IP_SHIFT 5 /* AIF1DRC1_KNEE_IP - [10:5] */
2305#define WM8995_AIF1DRC1_KNEE_IP_WIDTH 6 /* AIF1DRC1_KNEE_IP - [10:5] */
2306#define WM8995_AIF1DRC1_KNEE_OP_MASK 0x001F /* AIF1DRC1_KNEE_OP - [4:0] */
2307#define WM8995_AIF1DRC1_KNEE_OP_SHIFT 0 /* AIF1DRC1_KNEE_OP - [4:0] */
2308#define WM8995_AIF1DRC1_KNEE_OP_WIDTH 5 /* AIF1DRC1_KNEE_OP - [4:0] */
2309
2310/*
2311 * R1092 (0x444) - AIF1 DRC1 (5)
2312 */
2313#define WM8995_AIF1DRC1_KNEE2_IP_MASK 0x03E0 /* AIF1DRC1_KNEE2_IP - [9:5] */
2314#define WM8995_AIF1DRC1_KNEE2_IP_SHIFT 5 /* AIF1DRC1_KNEE2_IP - [9:5] */
2315#define WM8995_AIF1DRC1_KNEE2_IP_WIDTH 5 /* AIF1DRC1_KNEE2_IP - [9:5] */
2316#define WM8995_AIF1DRC1_KNEE2_OP_MASK 0x001F /* AIF1DRC1_KNEE2_OP - [4:0] */
2317#define WM8995_AIF1DRC1_KNEE2_OP_SHIFT 0 /* AIF1DRC1_KNEE2_OP - [4:0] */
2318#define WM8995_AIF1DRC1_KNEE2_OP_WIDTH 5 /* AIF1DRC1_KNEE2_OP - [4:0] */
2319
2320/*
2321 * R1104 (0x450) - AIF1 DRC2 (1)
2322 */
2323#define WM8995_AIF1DRC2_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
2324#define WM8995_AIF1DRC2_SIG_DET_RMS_SHIFT 11 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
2325#define WM8995_AIF1DRC2_SIG_DET_RMS_WIDTH 5 /* AIF1DRC2_SIG_DET_RMS - [15:11] */
2326#define WM8995_AIF1DRC2_SIG_DET_PK_MASK 0x0600 /* AIF1DRC2_SIG_DET_PK - [10:9] */
2327#define WM8995_AIF1DRC2_SIG_DET_PK_SHIFT 9 /* AIF1DRC2_SIG_DET_PK - [10:9] */
2328#define WM8995_AIF1DRC2_SIG_DET_PK_WIDTH 2 /* AIF1DRC2_SIG_DET_PK - [10:9] */
2329#define WM8995_AIF1DRC2_NG_ENA 0x0100 /* AIF1DRC2_NG_ENA */
2330#define WM8995_AIF1DRC2_NG_ENA_MASK 0x0100 /* AIF1DRC2_NG_ENA */
2331#define WM8995_AIF1DRC2_NG_ENA_SHIFT 8 /* AIF1DRC2_NG_ENA */
2332#define WM8995_AIF1DRC2_NG_ENA_WIDTH 1 /* AIF1DRC2_NG_ENA */
2333#define WM8995_AIF1DRC2_SIG_DET_MODE 0x0080 /* AIF1DRC2_SIG_DET_MODE */
2334#define WM8995_AIF1DRC2_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC2_SIG_DET_MODE */
2335#define WM8995_AIF1DRC2_SIG_DET_MODE_SHIFT 7 /* AIF1DRC2_SIG_DET_MODE */
2336#define WM8995_AIF1DRC2_SIG_DET_MODE_WIDTH 1 /* AIF1DRC2_SIG_DET_MODE */
2337#define WM8995_AIF1DRC2_SIG_DET 0x0040 /* AIF1DRC2_SIG_DET */
2338#define WM8995_AIF1DRC2_SIG_DET_MASK 0x0040 /* AIF1DRC2_SIG_DET */
2339#define WM8995_AIF1DRC2_SIG_DET_SHIFT 6 /* AIF1DRC2_SIG_DET */
2340#define WM8995_AIF1DRC2_SIG_DET_WIDTH 1 /* AIF1DRC2_SIG_DET */
2341#define WM8995_AIF1DRC2_KNEE2_OP_ENA 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */
2342#define WM8995_AIF1DRC2_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */
2343#define WM8995_AIF1DRC2_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC2_KNEE2_OP_ENA */
2344#define WM8995_AIF1DRC2_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC2_KNEE2_OP_ENA */
2345#define WM8995_AIF1DRC2_QR 0x0010 /* AIF1DRC2_QR */
2346#define WM8995_AIF1DRC2_QR_MASK 0x0010 /* AIF1DRC2_QR */
2347#define WM8995_AIF1DRC2_QR_SHIFT 4 /* AIF1DRC2_QR */
2348#define WM8995_AIF1DRC2_QR_WIDTH 1 /* AIF1DRC2_QR */
2349#define WM8995_AIF1DRC2_ANTICLIP 0x0008 /* AIF1DRC2_ANTICLIP */
2350#define WM8995_AIF1DRC2_ANTICLIP_MASK 0x0008 /* AIF1DRC2_ANTICLIP */
2351#define WM8995_AIF1DRC2_ANTICLIP_SHIFT 3 /* AIF1DRC2_ANTICLIP */
2352#define WM8995_AIF1DRC2_ANTICLIP_WIDTH 1 /* AIF1DRC2_ANTICLIP */
2353#define WM8995_AIF1DAC2_DRC_ENA 0x0004 /* AIF1DAC2_DRC_ENA */
2354#define WM8995_AIF1DAC2_DRC_ENA_MASK 0x0004 /* AIF1DAC2_DRC_ENA */
2355#define WM8995_AIF1DAC2_DRC_ENA_SHIFT 2 /* AIF1DAC2_DRC_ENA */
2356#define WM8995_AIF1DAC2_DRC_ENA_WIDTH 1 /* AIF1DAC2_DRC_ENA */
2357#define WM8995_AIF1ADC2L_DRC_ENA 0x0002 /* AIF1ADC2L_DRC_ENA */
2358#define WM8995_AIF1ADC2L_DRC_ENA_MASK 0x0002 /* AIF1ADC2L_DRC_ENA */
2359#define WM8995_AIF1ADC2L_DRC_ENA_SHIFT 1 /* AIF1ADC2L_DRC_ENA */
2360#define WM8995_AIF1ADC2L_DRC_ENA_WIDTH 1 /* AIF1ADC2L_DRC_ENA */
2361#define WM8995_AIF1ADC2R_DRC_ENA 0x0001 /* AIF1ADC2R_DRC_ENA */
2362#define WM8995_AIF1ADC2R_DRC_ENA_MASK 0x0001 /* AIF1ADC2R_DRC_ENA */
2363#define WM8995_AIF1ADC2R_DRC_ENA_SHIFT 0 /* AIF1ADC2R_DRC_ENA */
2364#define WM8995_AIF1ADC2R_DRC_ENA_WIDTH 1 /* AIF1ADC2R_DRC_ENA */
2365
2366/*
2367 * R1105 (0x451) - AIF1 DRC2 (2)
2368 */
2369#define WM8995_AIF1DRC2_ATK_MASK 0x1E00 /* AIF1DRC2_ATK - [12:9] */
2370#define WM8995_AIF1DRC2_ATK_SHIFT 9 /* AIF1DRC2_ATK - [12:9] */
2371#define WM8995_AIF1DRC2_ATK_WIDTH 4 /* AIF1DRC2_ATK - [12:9] */
2372#define WM8995_AIF1DRC2_DCY_MASK 0x01E0 /* AIF1DRC2_DCY - [8:5] */
2373#define WM8995_AIF1DRC2_DCY_SHIFT 5 /* AIF1DRC2_DCY - [8:5] */
2374#define WM8995_AIF1DRC2_DCY_WIDTH 4 /* AIF1DRC2_DCY - [8:5] */
2375#define WM8995_AIF1DRC2_MINGAIN_MASK 0x001C /* AIF1DRC2_MINGAIN - [4:2] */
2376#define WM8995_AIF1DRC2_MINGAIN_SHIFT 2 /* AIF1DRC2_MINGAIN - [4:2] */
2377#define WM8995_AIF1DRC2_MINGAIN_WIDTH 3 /* AIF1DRC2_MINGAIN - [4:2] */
2378#define WM8995_AIF1DRC2_MAXGAIN_MASK 0x0003 /* AIF1DRC2_MAXGAIN - [1:0] */
2379#define WM8995_AIF1DRC2_MAXGAIN_SHIFT 0 /* AIF1DRC2_MAXGAIN - [1:0] */
2380#define WM8995_AIF1DRC2_MAXGAIN_WIDTH 2 /* AIF1DRC2_MAXGAIN - [1:0] */
2381
2382/*
2383 * R1106 (0x452) - AIF1 DRC2 (3)
2384 */
2385#define WM8995_AIF1DRC2_NG_MINGAIN_MASK 0xF000 /* AIF1DRC2_NG_MINGAIN - [15:12] */
2386#define WM8995_AIF1DRC2_NG_MINGAIN_SHIFT 12 /* AIF1DRC2_NG_MINGAIN - [15:12] */
2387#define WM8995_AIF1DRC2_NG_MINGAIN_WIDTH 4 /* AIF1DRC2_NG_MINGAIN - [15:12] */
2388#define WM8995_AIF1DRC2_NG_EXP_MASK 0x0C00 /* AIF1DRC2_NG_EXP - [11:10] */
2389#define WM8995_AIF1DRC2_NG_EXP_SHIFT 10 /* AIF1DRC2_NG_EXP - [11:10] */
2390#define WM8995_AIF1DRC2_NG_EXP_WIDTH 2 /* AIF1DRC2_NG_EXP - [11:10] */
2391#define WM8995_AIF1DRC2_QR_THR_MASK 0x0300 /* AIF1DRC2_QR_THR - [9:8] */
2392#define WM8995_AIF1DRC2_QR_THR_SHIFT 8 /* AIF1DRC2_QR_THR - [9:8] */
2393#define WM8995_AIF1DRC2_QR_THR_WIDTH 2 /* AIF1DRC2_QR_THR - [9:8] */
2394#define WM8995_AIF1DRC2_QR_DCY_MASK 0x00C0 /* AIF1DRC2_QR_DCY - [7:6] */
2395#define WM8995_AIF1DRC2_QR_DCY_SHIFT 6 /* AIF1DRC2_QR_DCY - [7:6] */
2396#define WM8995_AIF1DRC2_QR_DCY_WIDTH 2 /* AIF1DRC2_QR_DCY - [7:6] */
2397#define WM8995_AIF1DRC2_HI_COMP_MASK 0x0038 /* AIF1DRC2_HI_COMP - [5:3] */
2398#define WM8995_AIF1DRC2_HI_COMP_SHIFT 3 /* AIF1DRC2_HI_COMP - [5:3] */
2399#define WM8995_AIF1DRC2_HI_COMP_WIDTH 3 /* AIF1DRC2_HI_COMP - [5:3] */
2400#define WM8995_AIF1DRC2_LO_COMP_MASK 0x0007 /* AIF1DRC2_LO_COMP - [2:0] */
2401#define WM8995_AIF1DRC2_LO_COMP_SHIFT 0 /* AIF1DRC2_LO_COMP - [2:0] */
2402#define WM8995_AIF1DRC2_LO_COMP_WIDTH 3 /* AIF1DRC2_LO_COMP - [2:0] */
2403
2404/*
2405 * R1107 (0x453) - AIF1 DRC2 (4)
2406 */
2407#define WM8995_AIF1DRC2_KNEE_IP_MASK 0x07E0 /* AIF1DRC2_KNEE_IP - [10:5] */
2408#define WM8995_AIF1DRC2_KNEE_IP_SHIFT 5 /* AIF1DRC2_KNEE_IP - [10:5] */
2409#define WM8995_AIF1DRC2_KNEE_IP_WIDTH 6 /* AIF1DRC2_KNEE_IP - [10:5] */
2410#define WM8995_AIF1DRC2_KNEE_OP_MASK 0x001F /* AIF1DRC2_KNEE_OP - [4:0] */
2411#define WM8995_AIF1DRC2_KNEE_OP_SHIFT 0 /* AIF1DRC2_KNEE_OP - [4:0] */
2412#define WM8995_AIF1DRC2_KNEE_OP_WIDTH 5 /* AIF1DRC2_KNEE_OP - [4:0] */
2413
2414/*
2415 * R1108 (0x454) - AIF1 DRC2 (5)
2416 */
2417#define WM8995_AIF1DRC2_KNEE2_IP_MASK 0x03E0 /* AIF1DRC2_KNEE2_IP - [9:5] */
2418#define WM8995_AIF1DRC2_KNEE2_IP_SHIFT 5 /* AIF1DRC2_KNEE2_IP - [9:5] */
2419#define WM8995_AIF1DRC2_KNEE2_IP_WIDTH 5 /* AIF1DRC2_KNEE2_IP - [9:5] */
2420#define WM8995_AIF1DRC2_KNEE2_OP_MASK 0x001F /* AIF1DRC2_KNEE2_OP - [4:0] */
2421#define WM8995_AIF1DRC2_KNEE2_OP_SHIFT 0 /* AIF1DRC2_KNEE2_OP - [4:0] */
2422#define WM8995_AIF1DRC2_KNEE2_OP_WIDTH 5 /* AIF1DRC2_KNEE2_OP - [4:0] */
2423
2424/*
2425 * R1152 (0x480) - AIF1 DAC1 EQ Gains (1)
2426 */
2427#define WM8995_AIF1DAC1_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
2428#define WM8995_AIF1DAC1_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
2429#define WM8995_AIF1DAC1_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
2430#define WM8995_AIF1DAC1_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
2431#define WM8995_AIF1DAC1_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
2432#define WM8995_AIF1DAC1_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
2433#define WM8995_AIF1DAC1_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
2434#define WM8995_AIF1DAC1_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
2435#define WM8995_AIF1DAC1_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
2436#define WM8995_AIF1DAC1_EQ_ENA 0x0001 /* AIF1DAC1_EQ_ENA */
2437#define WM8995_AIF1DAC1_EQ_ENA_MASK 0x0001 /* AIF1DAC1_EQ_ENA */
2438#define WM8995_AIF1DAC1_EQ_ENA_SHIFT 0 /* AIF1DAC1_EQ_ENA */
2439#define WM8995_AIF1DAC1_EQ_ENA_WIDTH 1 /* AIF1DAC1_EQ_ENA */
2440
2441/*
2442 * R1153 (0x481) - AIF1 DAC1 EQ Gains (2)
2443 */
2444#define WM8995_AIF1DAC1_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
2445#define WM8995_AIF1DAC1_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
2446#define WM8995_AIF1DAC1_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
2447#define WM8995_AIF1DAC1_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
2448#define WM8995_AIF1DAC1_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
2449#define WM8995_AIF1DAC1_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
2450
2451/*
2452 * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A
2453 */
2454#define WM8995_AIF1DAC1_EQ_B1_A_MASK 0xFFFF /* AIF1DAC1_EQ_B1_A - [15:0] */
2455#define WM8995_AIF1DAC1_EQ_B1_A_SHIFT 0 /* AIF1DAC1_EQ_B1_A - [15:0] */
2456#define WM8995_AIF1DAC1_EQ_B1_A_WIDTH 16 /* AIF1DAC1_EQ_B1_A - [15:0] */
2457
2458/*
2459 * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B
2460 */
2461#define WM8995_AIF1DAC1_EQ_B1_B_MASK 0xFFFF /* AIF1DAC1_EQ_B1_B - [15:0] */
2462#define WM8995_AIF1DAC1_EQ_B1_B_SHIFT 0 /* AIF1DAC1_EQ_B1_B - [15:0] */
2463#define WM8995_AIF1DAC1_EQ_B1_B_WIDTH 16 /* AIF1DAC1_EQ_B1_B - [15:0] */
2464
2465/*
2466 * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG
2467 */
2468#define WM8995_AIF1DAC1_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B1_PG - [15:0] */
2469#define WM8995_AIF1DAC1_EQ_B1_PG_SHIFT 0 /* AIF1DAC1_EQ_B1_PG - [15:0] */
2470#define WM8995_AIF1DAC1_EQ_B1_PG_WIDTH 16 /* AIF1DAC1_EQ_B1_PG - [15:0] */
2471
2472/*
2473 * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A
2474 */
2475#define WM8995_AIF1DAC1_EQ_B2_A_MASK 0xFFFF /* AIF1DAC1_EQ_B2_A - [15:0] */
2476#define WM8995_AIF1DAC1_EQ_B2_A_SHIFT 0 /* AIF1DAC1_EQ_B2_A - [15:0] */
2477#define WM8995_AIF1DAC1_EQ_B2_A_WIDTH 16 /* AIF1DAC1_EQ_B2_A - [15:0] */
2478
2479/*
2480 * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B
2481 */
2482#define WM8995_AIF1DAC1_EQ_B2_B_MASK 0xFFFF /* AIF1DAC1_EQ_B2_B - [15:0] */
2483#define WM8995_AIF1DAC1_EQ_B2_B_SHIFT 0 /* AIF1DAC1_EQ_B2_B - [15:0] */
2484#define WM8995_AIF1DAC1_EQ_B2_B_WIDTH 16 /* AIF1DAC1_EQ_B2_B - [15:0] */
2485
2486/*
2487 * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C
2488 */
2489#define WM8995_AIF1DAC1_EQ_B2_C_MASK 0xFFFF /* AIF1DAC1_EQ_B2_C - [15:0] */
2490#define WM8995_AIF1DAC1_EQ_B2_C_SHIFT 0 /* AIF1DAC1_EQ_B2_C - [15:0] */
2491#define WM8995_AIF1DAC1_EQ_B2_C_WIDTH 16 /* AIF1DAC1_EQ_B2_C - [15:0] */
2492
2493/*
2494 * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG
2495 */
2496#define WM8995_AIF1DAC1_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B2_PG - [15:0] */
2497#define WM8995_AIF1DAC1_EQ_B2_PG_SHIFT 0 /* AIF1DAC1_EQ_B2_PG - [15:0] */
2498#define WM8995_AIF1DAC1_EQ_B2_PG_WIDTH 16 /* AIF1DAC1_EQ_B2_PG - [15:0] */
2499
2500/*
2501 * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A
2502 */
2503#define WM8995_AIF1DAC1_EQ_B3_A_MASK 0xFFFF /* AIF1DAC1_EQ_B3_A - [15:0] */
2504#define WM8995_AIF1DAC1_EQ_B3_A_SHIFT 0 /* AIF1DAC1_EQ_B3_A - [15:0] */
2505#define WM8995_AIF1DAC1_EQ_B3_A_WIDTH 16 /* AIF1DAC1_EQ_B3_A - [15:0] */
2506
2507/*
2508 * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B
2509 */
2510#define WM8995_AIF1DAC1_EQ_B3_B_MASK 0xFFFF /* AIF1DAC1_EQ_B3_B - [15:0] */
2511#define WM8995_AIF1DAC1_EQ_B3_B_SHIFT 0 /* AIF1DAC1_EQ_B3_B - [15:0] */
2512#define WM8995_AIF1DAC1_EQ_B3_B_WIDTH 16 /* AIF1DAC1_EQ_B3_B - [15:0] */
2513
2514/*
2515 * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C
2516 */
2517#define WM8995_AIF1DAC1_EQ_B3_C_MASK 0xFFFF /* AIF1DAC1_EQ_B3_C - [15:0] */
2518#define WM8995_AIF1DAC1_EQ_B3_C_SHIFT 0 /* AIF1DAC1_EQ_B3_C - [15:0] */
2519#define WM8995_AIF1DAC1_EQ_B3_C_WIDTH 16 /* AIF1DAC1_EQ_B3_C - [15:0] */
2520
2521/*
2522 * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG
2523 */
2524#define WM8995_AIF1DAC1_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B3_PG - [15:0] */
2525#define WM8995_AIF1DAC1_EQ_B3_PG_SHIFT 0 /* AIF1DAC1_EQ_B3_PG - [15:0] */
2526#define WM8995_AIF1DAC1_EQ_B3_PG_WIDTH 16 /* AIF1DAC1_EQ_B3_PG - [15:0] */
2527
2528/*
2529 * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A
2530 */
2531#define WM8995_AIF1DAC1_EQ_B4_A_MASK 0xFFFF /* AIF1DAC1_EQ_B4_A - [15:0] */
2532#define WM8995_AIF1DAC1_EQ_B4_A_SHIFT 0 /* AIF1DAC1_EQ_B4_A - [15:0] */
2533#define WM8995_AIF1DAC1_EQ_B4_A_WIDTH 16 /* AIF1DAC1_EQ_B4_A - [15:0] */
2534
2535/*
2536 * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B
2537 */
2538#define WM8995_AIF1DAC1_EQ_B4_B_MASK 0xFFFF /* AIF1DAC1_EQ_B4_B - [15:0] */
2539#define WM8995_AIF1DAC1_EQ_B4_B_SHIFT 0 /* AIF1DAC1_EQ_B4_B - [15:0] */
2540#define WM8995_AIF1DAC1_EQ_B4_B_WIDTH 16 /* AIF1DAC1_EQ_B4_B - [15:0] */
2541
2542/*
2543 * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C
2544 */
2545#define WM8995_AIF1DAC1_EQ_B4_C_MASK 0xFFFF /* AIF1DAC1_EQ_B4_C - [15:0] */
2546#define WM8995_AIF1DAC1_EQ_B4_C_SHIFT 0 /* AIF1DAC1_EQ_B4_C - [15:0] */
2547#define WM8995_AIF1DAC1_EQ_B4_C_WIDTH 16 /* AIF1DAC1_EQ_B4_C - [15:0] */
2548
2549/*
2550 * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG
2551 */
2552#define WM8995_AIF1DAC1_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B4_PG - [15:0] */
2553#define WM8995_AIF1DAC1_EQ_B4_PG_SHIFT 0 /* AIF1DAC1_EQ_B4_PG - [15:0] */
2554#define WM8995_AIF1DAC1_EQ_B4_PG_WIDTH 16 /* AIF1DAC1_EQ_B4_PG - [15:0] */
2555
2556/*
2557 * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A
2558 */
2559#define WM8995_AIF1DAC1_EQ_B5_A_MASK 0xFFFF /* AIF1DAC1_EQ_B5_A - [15:0] */
2560#define WM8995_AIF1DAC1_EQ_B5_A_SHIFT 0 /* AIF1DAC1_EQ_B5_A - [15:0] */
2561#define WM8995_AIF1DAC1_EQ_B5_A_WIDTH 16 /* AIF1DAC1_EQ_B5_A - [15:0] */
2562
2563/*
2564 * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B
2565 */
2566#define WM8995_AIF1DAC1_EQ_B5_B_MASK 0xFFFF /* AIF1DAC1_EQ_B5_B - [15:0] */
2567#define WM8995_AIF1DAC1_EQ_B5_B_SHIFT 0 /* AIF1DAC1_EQ_B5_B - [15:0] */
2568#define WM8995_AIF1DAC1_EQ_B5_B_WIDTH 16 /* AIF1DAC1_EQ_B5_B - [15:0] */
2569
2570/*
2571 * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG
2572 */
2573#define WM8995_AIF1DAC1_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B5_PG - [15:0] */
2574#define WM8995_AIF1DAC1_EQ_B5_PG_SHIFT 0 /* AIF1DAC1_EQ_B5_PG - [15:0] */
2575#define WM8995_AIF1DAC1_EQ_B5_PG_WIDTH 16 /* AIF1DAC1_EQ_B5_PG - [15:0] */
2576
2577/*
2578 * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1)
2579 */
2580#define WM8995_AIF1DAC2_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
2581#define WM8995_AIF1DAC2_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
2582#define WM8995_AIF1DAC2_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
2583#define WM8995_AIF1DAC2_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
2584#define WM8995_AIF1DAC2_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
2585#define WM8995_AIF1DAC2_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
2586#define WM8995_AIF1DAC2_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
2587#define WM8995_AIF1DAC2_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
2588#define WM8995_AIF1DAC2_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
2589#define WM8995_AIF1DAC2_EQ_ENA 0x0001 /* AIF1DAC2_EQ_ENA */
2590#define WM8995_AIF1DAC2_EQ_ENA_MASK 0x0001 /* AIF1DAC2_EQ_ENA */
2591#define WM8995_AIF1DAC2_EQ_ENA_SHIFT 0 /* AIF1DAC2_EQ_ENA */
2592#define WM8995_AIF1DAC2_EQ_ENA_WIDTH 1 /* AIF1DAC2_EQ_ENA */
2593
2594/*
2595 * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2)
2596 */
2597#define WM8995_AIF1DAC2_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
2598#define WM8995_AIF1DAC2_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
2599#define WM8995_AIF1DAC2_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
2600#define WM8995_AIF1DAC2_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
2601#define WM8995_AIF1DAC2_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
2602#define WM8995_AIF1DAC2_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
2603
2604/*
2605 * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A
2606 */
2607#define WM8995_AIF1DAC2_EQ_B1_A_MASK 0xFFFF /* AIF1DAC2_EQ_B1_A - [15:0] */
2608#define WM8995_AIF1DAC2_EQ_B1_A_SHIFT 0 /* AIF1DAC2_EQ_B1_A - [15:0] */
2609#define WM8995_AIF1DAC2_EQ_B1_A_WIDTH 16 /* AIF1DAC2_EQ_B1_A - [15:0] */
2610
2611/*
2612 * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B
2613 */
2614#define WM8995_AIF1DAC2_EQ_B1_B_MASK 0xFFFF /* AIF1DAC2_EQ_B1_B - [15:0] */
2615#define WM8995_AIF1DAC2_EQ_B1_B_SHIFT 0 /* AIF1DAC2_EQ_B1_B - [15:0] */
2616#define WM8995_AIF1DAC2_EQ_B1_B_WIDTH 16 /* AIF1DAC2_EQ_B1_B - [15:0] */
2617
2618/*
2619 * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG
2620 */
2621#define WM8995_AIF1DAC2_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B1_PG - [15:0] */
2622#define WM8995_AIF1DAC2_EQ_B1_PG_SHIFT 0 /* AIF1DAC2_EQ_B1_PG - [15:0] */
2623#define WM8995_AIF1DAC2_EQ_B1_PG_WIDTH 16 /* AIF1DAC2_EQ_B1_PG - [15:0] */
2624
2625/*
2626 * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A
2627 */
2628#define WM8995_AIF1DAC2_EQ_B2_A_MASK 0xFFFF /* AIF1DAC2_EQ_B2_A - [15:0] */
2629#define WM8995_AIF1DAC2_EQ_B2_A_SHIFT 0 /* AIF1DAC2_EQ_B2_A - [15:0] */
2630#define WM8995_AIF1DAC2_EQ_B2_A_WIDTH 16 /* AIF1DAC2_EQ_B2_A - [15:0] */
2631
2632/*
2633 * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B
2634 */
2635#define WM8995_AIF1DAC2_EQ_B2_B_MASK 0xFFFF /* AIF1DAC2_EQ_B2_B - [15:0] */
2636#define WM8995_AIF1DAC2_EQ_B2_B_SHIFT 0 /* AIF1DAC2_EQ_B2_B - [15:0] */
2637#define WM8995_AIF1DAC2_EQ_B2_B_WIDTH 16 /* AIF1DAC2_EQ_B2_B - [15:0] */
2638
2639/*
2640 * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C
2641 */
2642#define WM8995_AIF1DAC2_EQ_B2_C_MASK 0xFFFF /* AIF1DAC2_EQ_B2_C - [15:0] */
2643#define WM8995_AIF1DAC2_EQ_B2_C_SHIFT 0 /* AIF1DAC2_EQ_B2_C - [15:0] */
2644#define WM8995_AIF1DAC2_EQ_B2_C_WIDTH 16 /* AIF1DAC2_EQ_B2_C - [15:0] */
2645
2646/*
2647 * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG
2648 */
2649#define WM8995_AIF1DAC2_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B2_PG - [15:0] */
2650#define WM8995_AIF1DAC2_EQ_B2_PG_SHIFT 0 /* AIF1DAC2_EQ_B2_PG - [15:0] */
2651#define WM8995_AIF1DAC2_EQ_B2_PG_WIDTH 16 /* AIF1DAC2_EQ_B2_PG - [15:0] */
2652
2653/*
2654 * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A
2655 */
2656#define WM8995_AIF1DAC2_EQ_B3_A_MASK 0xFFFF /* AIF1DAC2_EQ_B3_A - [15:0] */
2657#define WM8995_AIF1DAC2_EQ_B3_A_SHIFT 0 /* AIF1DAC2_EQ_B3_A - [15:0] */
2658#define WM8995_AIF1DAC2_EQ_B3_A_WIDTH 16 /* AIF1DAC2_EQ_B3_A - [15:0] */
2659
2660/*
2661 * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B
2662 */
2663#define WM8995_AIF1DAC2_EQ_B3_B_MASK 0xFFFF /* AIF1DAC2_EQ_B3_B - [15:0] */
2664#define WM8995_AIF1DAC2_EQ_B3_B_SHIFT 0 /* AIF1DAC2_EQ_B3_B - [15:0] */
2665#define WM8995_AIF1DAC2_EQ_B3_B_WIDTH 16 /* AIF1DAC2_EQ_B3_B - [15:0] */
2666
2667/*
2668 * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C
2669 */
2670#define WM8995_AIF1DAC2_EQ_B3_C_MASK 0xFFFF /* AIF1DAC2_EQ_B3_C - [15:0] */
2671#define WM8995_AIF1DAC2_EQ_B3_C_SHIFT 0 /* AIF1DAC2_EQ_B3_C - [15:0] */
2672#define WM8995_AIF1DAC2_EQ_B3_C_WIDTH 16 /* AIF1DAC2_EQ_B3_C - [15:0] */
2673
2674/*
2675 * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG
2676 */
2677#define WM8995_AIF1DAC2_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B3_PG - [15:0] */
2678#define WM8995_AIF1DAC2_EQ_B3_PG_SHIFT 0 /* AIF1DAC2_EQ_B3_PG - [15:0] */
2679#define WM8995_AIF1DAC2_EQ_B3_PG_WIDTH 16 /* AIF1DAC2_EQ_B3_PG - [15:0] */
2680
2681/*
2682 * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A
2683 */
2684#define WM8995_AIF1DAC2_EQ_B4_A_MASK 0xFFFF /* AIF1DAC2_EQ_B4_A - [15:0] */
2685#define WM8995_AIF1DAC2_EQ_B4_A_SHIFT 0 /* AIF1DAC2_EQ_B4_A - [15:0] */
2686#define WM8995_AIF1DAC2_EQ_B4_A_WIDTH 16 /* AIF1DAC2_EQ_B4_A - [15:0] */
2687
2688/*
2689 * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B
2690 */
2691#define WM8995_AIF1DAC2_EQ_B4_B_MASK 0xFFFF /* AIF1DAC2_EQ_B4_B - [15:0] */
2692#define WM8995_AIF1DAC2_EQ_B4_B_SHIFT 0 /* AIF1DAC2_EQ_B4_B - [15:0] */
2693#define WM8995_AIF1DAC2_EQ_B4_B_WIDTH 16 /* AIF1DAC2_EQ_B4_B - [15:0] */
2694
2695/*
2696 * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C
2697 */
2698#define WM8995_AIF1DAC2_EQ_B4_C_MASK 0xFFFF /* AIF1DAC2_EQ_B4_C - [15:0] */
2699#define WM8995_AIF1DAC2_EQ_B4_C_SHIFT 0 /* AIF1DAC2_EQ_B4_C - [15:0] */
2700#define WM8995_AIF1DAC2_EQ_B4_C_WIDTH 16 /* AIF1DAC2_EQ_B4_C - [15:0] */
2701
2702/*
2703 * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG
2704 */
2705#define WM8995_AIF1DAC2_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B4_PG - [15:0] */
2706#define WM8995_AIF1DAC2_EQ_B4_PG_SHIFT 0 /* AIF1DAC2_EQ_B4_PG - [15:0] */
2707#define WM8995_AIF1DAC2_EQ_B4_PG_WIDTH 16 /* AIF1DAC2_EQ_B4_PG - [15:0] */
2708
2709/*
2710 * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A
2711 */
2712#define WM8995_AIF1DAC2_EQ_B5_A_MASK 0xFFFF /* AIF1DAC2_EQ_B5_A - [15:0] */
2713#define WM8995_AIF1DAC2_EQ_B5_A_SHIFT 0 /* AIF1DAC2_EQ_B5_A - [15:0] */
2714#define WM8995_AIF1DAC2_EQ_B5_A_WIDTH 16 /* AIF1DAC2_EQ_B5_A - [15:0] */
2715
2716/*
2717 * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B
2718 */
2719#define WM8995_AIF1DAC2_EQ_B5_B_MASK 0xFFFF /* AIF1DAC2_EQ_B5_B - [15:0] */
2720#define WM8995_AIF1DAC2_EQ_B5_B_SHIFT 0 /* AIF1DAC2_EQ_B5_B - [15:0] */
2721#define WM8995_AIF1DAC2_EQ_B5_B_WIDTH 16 /* AIF1DAC2_EQ_B5_B - [15:0] */
2722
2723/*
2724 * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG
2725 */
2726#define WM8995_AIF1DAC2_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B5_PG - [15:0] */
2727#define WM8995_AIF1DAC2_EQ_B5_PG_SHIFT 0 /* AIF1DAC2_EQ_B5_PG - [15:0] */
2728#define WM8995_AIF1DAC2_EQ_B5_PG_WIDTH 16 /* AIF1DAC2_EQ_B5_PG - [15:0] */
2729
2730/*
2731 * R1280 (0x500) - AIF2 ADC Left Volume
2732 */
2733#define WM8995_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */
2734#define WM8995_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */
2735#define WM8995_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */
2736#define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */
2737#define WM8995_AIF2ADCL_VOL_MASK 0x00FF /* AIF2ADCL_VOL - [7:0] */
2738#define WM8995_AIF2ADCL_VOL_SHIFT 0 /* AIF2ADCL_VOL - [7:0] */
2739#define WM8995_AIF2ADCL_VOL_WIDTH 8 /* AIF2ADCL_VOL - [7:0] */
2740
2741/*
2742 * R1281 (0x501) - AIF2 ADC Right Volume
2743 */
2744#define WM8995_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */
2745#define WM8995_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */
2746#define WM8995_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */
2747#define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */
2748#define WM8995_AIF2ADCR_VOL_MASK 0x00FF /* AIF2ADCR_VOL - [7:0] */
2749#define WM8995_AIF2ADCR_VOL_SHIFT 0 /* AIF2ADCR_VOL - [7:0] */
2750#define WM8995_AIF2ADCR_VOL_WIDTH 8 /* AIF2ADCR_VOL - [7:0] */
2751
2752/*
2753 * R1282 (0x502) - AIF2 DAC Left Volume
2754 */
2755#define WM8995_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */
2756#define WM8995_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */
2757#define WM8995_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */
2758#define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */
2759#define WM8995_AIF2DACL_VOL_MASK 0x00FF /* AIF2DACL_VOL - [7:0] */
2760#define WM8995_AIF2DACL_VOL_SHIFT 0 /* AIF2DACL_VOL - [7:0] */
2761#define WM8995_AIF2DACL_VOL_WIDTH 8 /* AIF2DACL_VOL - [7:0] */
2762
2763/*
2764 * R1283 (0x503) - AIF2 DAC Right Volume
2765 */
2766#define WM8995_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */
2767#define WM8995_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */
2768#define WM8995_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */
2769#define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */
2770#define WM8995_AIF2DACR_VOL_MASK 0x00FF /* AIF2DACR_VOL - [7:0] */
2771#define WM8995_AIF2DACR_VOL_SHIFT 0 /* AIF2DACR_VOL - [7:0] */
2772#define WM8995_AIF2DACR_VOL_WIDTH 8 /* AIF2DACR_VOL - [7:0] */
2773
2774/*
2775 * R1296 (0x510) - AIF2 ADC Filters
2776 */
2777#define WM8995_AIF2ADC_4FS 0x8000 /* AIF2ADC_4FS */
2778#define WM8995_AIF2ADC_4FS_MASK 0x8000 /* AIF2ADC_4FS */
2779#define WM8995_AIF2ADC_4FS_SHIFT 15 /* AIF2ADC_4FS */
2780#define WM8995_AIF2ADC_4FS_WIDTH 1 /* AIF2ADC_4FS */
2781#define WM8995_AIF2ADCL_HPF 0x1000 /* AIF2ADCL_HPF */
2782#define WM8995_AIF2ADCL_HPF_MASK 0x1000 /* AIF2ADCL_HPF */
2783#define WM8995_AIF2ADCL_HPF_SHIFT 12 /* AIF2ADCL_HPF */
2784#define WM8995_AIF2ADCL_HPF_WIDTH 1 /* AIF2ADCL_HPF */
2785#define WM8995_AIF2ADCR_HPF 0x0800 /* AIF2ADCR_HPF */
2786#define WM8995_AIF2ADCR_HPF_MASK 0x0800 /* AIF2ADCR_HPF */
2787#define WM8995_AIF2ADCR_HPF_SHIFT 11 /* AIF2ADCR_HPF */
2788#define WM8995_AIF2ADCR_HPF_WIDTH 1 /* AIF2ADCR_HPF */
2789#define WM8995_AIF2ADC_HPF_MODE 0x0008 /* AIF2ADC_HPF_MODE */
2790#define WM8995_AIF2ADC_HPF_MODE_MASK 0x0008 /* AIF2ADC_HPF_MODE */
2791#define WM8995_AIF2ADC_HPF_MODE_SHIFT 3 /* AIF2ADC_HPF_MODE */
2792#define WM8995_AIF2ADC_HPF_MODE_WIDTH 1 /* AIF2ADC_HPF_MODE */
2793#define WM8995_AIF2ADC_HPF_CUT_MASK 0x0007 /* AIF2ADC_HPF_CUT - [2:0] */
2794#define WM8995_AIF2ADC_HPF_CUT_SHIFT 0 /* AIF2ADC_HPF_CUT - [2:0] */
2795#define WM8995_AIF2ADC_HPF_CUT_WIDTH 3 /* AIF2ADC_HPF_CUT - [2:0] */
2796
2797/*
2798 * R1312 (0x520) - AIF2 DAC Filters (1)
2799 */
2800#define WM8995_AIF2DAC_MUTE 0x0200 /* AIF2DAC_MUTE */
2801#define WM8995_AIF2DAC_MUTE_MASK 0x0200 /* AIF2DAC_MUTE */
2802#define WM8995_AIF2DAC_MUTE_SHIFT 9 /* AIF2DAC_MUTE */
2803#define WM8995_AIF2DAC_MUTE_WIDTH 1 /* AIF2DAC_MUTE */
2804#define WM8995_AIF2DAC_MONO 0x0080 /* AIF2DAC_MONO */
2805#define WM8995_AIF2DAC_MONO_MASK 0x0080 /* AIF2DAC_MONO */
2806#define WM8995_AIF2DAC_MONO_SHIFT 7 /* AIF2DAC_MONO */
2807#define WM8995_AIF2DAC_MONO_WIDTH 1 /* AIF2DAC_MONO */
2808#define WM8995_AIF2DAC_MUTERATE 0x0020 /* AIF2DAC_MUTERATE */
2809#define WM8995_AIF2DAC_MUTERATE_MASK 0x0020 /* AIF2DAC_MUTERATE */
2810#define WM8995_AIF2DAC_MUTERATE_SHIFT 5 /* AIF2DAC_MUTERATE */
2811#define WM8995_AIF2DAC_MUTERATE_WIDTH 1 /* AIF2DAC_MUTERATE */
2812#define WM8995_AIF2DAC_UNMUTE_RAMP 0x0010 /* AIF2DAC_UNMUTE_RAMP */
2813#define WM8995_AIF2DAC_UNMUTE_RAMP_MASK 0x0010 /* AIF2DAC_UNMUTE_RAMP */
2814#define WM8995_AIF2DAC_UNMUTE_RAMP_SHIFT 4 /* AIF2DAC_UNMUTE_RAMP */
2815#define WM8995_AIF2DAC_UNMUTE_RAMP_WIDTH 1 /* AIF2DAC_UNMUTE_RAMP */
2816#define WM8995_AIF2DAC_DEEMP_MASK 0x0006 /* AIF2DAC_DEEMP - [2:1] */
2817#define WM8995_AIF2DAC_DEEMP_SHIFT 1 /* AIF2DAC_DEEMP - [2:1] */
2818#define WM8995_AIF2DAC_DEEMP_WIDTH 2 /* AIF2DAC_DEEMP - [2:1] */
2819
2820/*
2821 * R1313 (0x521) - AIF2 DAC Filters (2)
2822 */
2823#define WM8995_AIF2DAC_3D_GAIN_MASK 0x3E00 /* AIF2DAC_3D_GAIN - [13:9] */
2824#define WM8995_AIF2DAC_3D_GAIN_SHIFT 9 /* AIF2DAC_3D_GAIN - [13:9] */
2825#define WM8995_AIF2DAC_3D_GAIN_WIDTH 5 /* AIF2DAC_3D_GAIN - [13:9] */
2826#define WM8995_AIF2DAC_3D_ENA 0x0100 /* AIF2DAC_3D_ENA */
2827#define WM8995_AIF2DAC_3D_ENA_MASK 0x0100 /* AIF2DAC_3D_ENA */
2828#define WM8995_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */
2829#define WM8995_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */
2830
2831/*
2832 * R1344 (0x540) - AIF2 DRC (1)
2833 */
2834#define WM8995_AIF2DRC_SIG_DET_RMS_MASK 0xF800 /* AIF2DRC_SIG_DET_RMS - [15:11] */
2835#define WM8995_AIF2DRC_SIG_DET_RMS_SHIFT 11 /* AIF2DRC_SIG_DET_RMS - [15:11] */
2836#define WM8995_AIF2DRC_SIG_DET_RMS_WIDTH 5 /* AIF2DRC_SIG_DET_RMS - [15:11] */
2837#define WM8995_AIF2DRC_SIG_DET_PK_MASK 0x0600 /* AIF2DRC_SIG_DET_PK - [10:9] */
2838#define WM8995_AIF2DRC_SIG_DET_PK_SHIFT 9 /* AIF2DRC_SIG_DET_PK - [10:9] */
2839#define WM8995_AIF2DRC_SIG_DET_PK_WIDTH 2 /* AIF2DRC_SIG_DET_PK - [10:9] */
2840#define WM8995_AIF2DRC_NG_ENA 0x0100 /* AIF2DRC_NG_ENA */
2841#define WM8995_AIF2DRC_NG_ENA_MASK 0x0100 /* AIF2DRC_NG_ENA */
2842#define WM8995_AIF2DRC_NG_ENA_SHIFT 8 /* AIF2DRC_NG_ENA */
2843#define WM8995_AIF2DRC_NG_ENA_WIDTH 1 /* AIF2DRC_NG_ENA */
2844#define WM8995_AIF2DRC_SIG_DET_MODE 0x0080 /* AIF2DRC_SIG_DET_MODE */
2845#define WM8995_AIF2DRC_SIG_DET_MODE_MASK 0x0080 /* AIF2DRC_SIG_DET_MODE */
2846#define WM8995_AIF2DRC_SIG_DET_MODE_SHIFT 7 /* AIF2DRC_SIG_DET_MODE */
2847#define WM8995_AIF2DRC_SIG_DET_MODE_WIDTH 1 /* AIF2DRC_SIG_DET_MODE */
2848#define WM8995_AIF2DRC_SIG_DET 0x0040 /* AIF2DRC_SIG_DET */
2849#define WM8995_AIF2DRC_SIG_DET_MASK 0x0040 /* AIF2DRC_SIG_DET */
2850#define WM8995_AIF2DRC_SIG_DET_SHIFT 6 /* AIF2DRC_SIG_DET */
2851#define WM8995_AIF2DRC_SIG_DET_WIDTH 1 /* AIF2DRC_SIG_DET */
2852#define WM8995_AIF2DRC_KNEE2_OP_ENA 0x0020 /* AIF2DRC_KNEE2_OP_ENA */
2853#define WM8995_AIF2DRC_KNEE2_OP_ENA_MASK 0x0020 /* AIF2DRC_KNEE2_OP_ENA */
2854#define WM8995_AIF2DRC_KNEE2_OP_ENA_SHIFT 5 /* AIF2DRC_KNEE2_OP_ENA */
2855#define WM8995_AIF2DRC_KNEE2_OP_ENA_WIDTH 1 /* AIF2DRC_KNEE2_OP_ENA */
2856#define WM8995_AIF2DRC_QR 0x0010 /* AIF2DRC_QR */
2857#define WM8995_AIF2DRC_QR_MASK 0x0010 /* AIF2DRC_QR */
2858#define WM8995_AIF2DRC_QR_SHIFT 4 /* AIF2DRC_QR */
2859#define WM8995_AIF2DRC_QR_WIDTH 1 /* AIF2DRC_QR */
2860#define WM8995_AIF2DRC_ANTICLIP 0x0008 /* AIF2DRC_ANTICLIP */
2861#define WM8995_AIF2DRC_ANTICLIP_MASK 0x0008 /* AIF2DRC_ANTICLIP */
2862#define WM8995_AIF2DRC_ANTICLIP_SHIFT 3 /* AIF2DRC_ANTICLIP */
2863#define WM8995_AIF2DRC_ANTICLIP_WIDTH 1 /* AIF2DRC_ANTICLIP */
2864#define WM8995_AIF2DAC_DRC_ENA 0x0004 /* AIF2DAC_DRC_ENA */
2865#define WM8995_AIF2DAC_DRC_ENA_MASK 0x0004 /* AIF2DAC_DRC_ENA */
2866#define WM8995_AIF2DAC_DRC_ENA_SHIFT 2 /* AIF2DAC_DRC_ENA */
2867#define WM8995_AIF2DAC_DRC_ENA_WIDTH 1 /* AIF2DAC_DRC_ENA */
2868#define WM8995_AIF2ADCL_DRC_ENA 0x0002 /* AIF2ADCL_DRC_ENA */
2869#define WM8995_AIF2ADCL_DRC_ENA_MASK 0x0002 /* AIF2ADCL_DRC_ENA */
2870#define WM8995_AIF2ADCL_DRC_ENA_SHIFT 1 /* AIF2ADCL_DRC_ENA */
2871#define WM8995_AIF2ADCL_DRC_ENA_WIDTH 1 /* AIF2ADCL_DRC_ENA */
2872#define WM8995_AIF2ADCR_DRC_ENA 0x0001 /* AIF2ADCR_DRC_ENA */
2873#define WM8995_AIF2ADCR_DRC_ENA_MASK 0x0001 /* AIF2ADCR_DRC_ENA */
2874#define WM8995_AIF2ADCR_DRC_ENA_SHIFT 0 /* AIF2ADCR_DRC_ENA */
2875#define WM8995_AIF2ADCR_DRC_ENA_WIDTH 1 /* AIF2ADCR_DRC_ENA */
2876
2877/*
2878 * R1345 (0x541) - AIF2 DRC (2)
2879 */
2880#define WM8995_AIF2DRC_ATK_MASK 0x1E00 /* AIF2DRC_ATK - [12:9] */
2881#define WM8995_AIF2DRC_ATK_SHIFT 9 /* AIF2DRC_ATK - [12:9] */
2882#define WM8995_AIF2DRC_ATK_WIDTH 4 /* AIF2DRC_ATK - [12:9] */
2883#define WM8995_AIF2DRC_DCY_MASK 0x01E0 /* AIF2DRC_DCY - [8:5] */
2884#define WM8995_AIF2DRC_DCY_SHIFT 5 /* AIF2DRC_DCY - [8:5] */
2885#define WM8995_AIF2DRC_DCY_WIDTH 4 /* AIF2DRC_DCY - [8:5] */
2886#define WM8995_AIF2DRC_MINGAIN_MASK 0x001C /* AIF2DRC_MINGAIN - [4:2] */
2887#define WM8995_AIF2DRC_MINGAIN_SHIFT 2 /* AIF2DRC_MINGAIN - [4:2] */
2888#define WM8995_AIF2DRC_MINGAIN_WIDTH 3 /* AIF2DRC_MINGAIN - [4:2] */
2889#define WM8995_AIF2DRC_MAXGAIN_MASK 0x0003 /* AIF2DRC_MAXGAIN - [1:0] */
2890#define WM8995_AIF2DRC_MAXGAIN_SHIFT 0 /* AIF2DRC_MAXGAIN - [1:0] */
2891#define WM8995_AIF2DRC_MAXGAIN_WIDTH 2 /* AIF2DRC_MAXGAIN - [1:0] */
2892
2893/*
2894 * R1346 (0x542) - AIF2 DRC (3)
2895 */
2896#define WM8995_AIF2DRC_NG_MINGAIN_MASK 0xF000 /* AIF2DRC_NG_MINGAIN - [15:12] */
2897#define WM8995_AIF2DRC_NG_MINGAIN_SHIFT 12 /* AIF2DRC_NG_MINGAIN - [15:12] */
2898#define WM8995_AIF2DRC_NG_MINGAIN_WIDTH 4 /* AIF2DRC_NG_MINGAIN - [15:12] */
2899#define WM8995_AIF2DRC_NG_EXP_MASK 0x0C00 /* AIF2DRC_NG_EXP - [11:10] */
2900#define WM8995_AIF2DRC_NG_EXP_SHIFT 10 /* AIF2DRC_NG_EXP - [11:10] */
2901#define WM8995_AIF2DRC_NG_EXP_WIDTH 2 /* AIF2DRC_NG_EXP - [11:10] */
2902#define WM8995_AIF2DRC_QR_THR_MASK 0x0300 /* AIF2DRC_QR_THR - [9:8] */
2903#define WM8995_AIF2DRC_QR_THR_SHIFT 8 /* AIF2DRC_QR_THR - [9:8] */
2904#define WM8995_AIF2DRC_QR_THR_WIDTH 2 /* AIF2DRC_QR_THR - [9:8] */
2905#define WM8995_AIF2DRC_QR_DCY_MASK 0x00C0 /* AIF2DRC_QR_DCY - [7:6] */
2906#define WM8995_AIF2DRC_QR_DCY_SHIFT 6 /* AIF2DRC_QR_DCY - [7:6] */
2907#define WM8995_AIF2DRC_QR_DCY_WIDTH 2 /* AIF2DRC_QR_DCY - [7:6] */
2908#define WM8995_AIF2DRC_HI_COMP_MASK 0x0038 /* AIF2DRC_HI_COMP - [5:3] */
2909#define WM8995_AIF2DRC_HI_COMP_SHIFT 3 /* AIF2DRC_HI_COMP - [5:3] */
2910#define WM8995_AIF2DRC_HI_COMP_WIDTH 3 /* AIF2DRC_HI_COMP - [5:3] */
2911#define WM8995_AIF2DRC_LO_COMP_MASK 0x0007 /* AIF2DRC_LO_COMP - [2:0] */
2912#define WM8995_AIF2DRC_LO_COMP_SHIFT 0 /* AIF2DRC_LO_COMP - [2:0] */
2913#define WM8995_AIF2DRC_LO_COMP_WIDTH 3 /* AIF2DRC_LO_COMP - [2:0] */
2914
2915/*
2916 * R1347 (0x543) - AIF2 DRC (4)
2917 */
2918#define WM8995_AIF2DRC_KNEE_IP_MASK 0x07E0 /* AIF2DRC_KNEE_IP - [10:5] */
2919#define WM8995_AIF2DRC_KNEE_IP_SHIFT 5 /* AIF2DRC_KNEE_IP - [10:5] */
2920#define WM8995_AIF2DRC_KNEE_IP_WIDTH 6 /* AIF2DRC_KNEE_IP - [10:5] */
2921#define WM8995_AIF2DRC_KNEE_OP_MASK 0x001F /* AIF2DRC_KNEE_OP - [4:0] */
2922#define WM8995_AIF2DRC_KNEE_OP_SHIFT 0 /* AIF2DRC_KNEE_OP - [4:0] */
2923#define WM8995_AIF2DRC_KNEE_OP_WIDTH 5 /* AIF2DRC_KNEE_OP - [4:0] */
2924
2925/*
2926 * R1348 (0x544) - AIF2 DRC (5)
2927 */
2928#define WM8995_AIF2DRC_KNEE2_IP_MASK 0x03E0 /* AIF2DRC_KNEE2_IP - [9:5] */
2929#define WM8995_AIF2DRC_KNEE2_IP_SHIFT 5 /* AIF2DRC_KNEE2_IP - [9:5] */
2930#define WM8995_AIF2DRC_KNEE2_IP_WIDTH 5 /* AIF2DRC_KNEE2_IP - [9:5] */
2931#define WM8995_AIF2DRC_KNEE2_OP_MASK 0x001F /* AIF2DRC_KNEE2_OP - [4:0] */
2932#define WM8995_AIF2DRC_KNEE2_OP_SHIFT 0 /* AIF2DRC_KNEE2_OP - [4:0] */
2933#define WM8995_AIF2DRC_KNEE2_OP_WIDTH 5 /* AIF2DRC_KNEE2_OP - [4:0] */
2934
2935/*
2936 * R1408 (0x580) - AIF2 EQ Gains (1)
2937 */
2938#define WM8995_AIF2DAC_EQ_B1_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
2939#define WM8995_AIF2DAC_EQ_B1_GAIN_SHIFT 11 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
2940#define WM8995_AIF2DAC_EQ_B1_GAIN_WIDTH 5 /* AIF2DAC_EQ_B1_GAIN - [15:11] */
2941#define WM8995_AIF2DAC_EQ_B2_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
2942#define WM8995_AIF2DAC_EQ_B2_GAIN_SHIFT 6 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
2943#define WM8995_AIF2DAC_EQ_B2_GAIN_WIDTH 5 /* AIF2DAC_EQ_B2_GAIN - [10:6] */
2944#define WM8995_AIF2DAC_EQ_B3_GAIN_MASK 0x003E /* AIF2DAC_EQ_B3_GAIN - [5:1] */
2945#define WM8995_AIF2DAC_EQ_B3_GAIN_SHIFT 1 /* AIF2DAC_EQ_B3_GAIN - [5:1] */
2946#define WM8995_AIF2DAC_EQ_B3_GAIN_WIDTH 5 /* AIF2DAC_EQ_B3_GAIN - [5:1] */
2947#define WM8995_AIF2DAC_EQ_ENA 0x0001 /* AIF2DAC_EQ_ENA */
2948#define WM8995_AIF2DAC_EQ_ENA_MASK 0x0001 /* AIF2DAC_EQ_ENA */
2949#define WM8995_AIF2DAC_EQ_ENA_SHIFT 0 /* AIF2DAC_EQ_ENA */
2950#define WM8995_AIF2DAC_EQ_ENA_WIDTH 1 /* AIF2DAC_EQ_ENA */
2951
2952/*
2953 * R1409 (0x581) - AIF2 EQ Gains (2)
2954 */
2955#define WM8995_AIF2DAC_EQ_B4_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
2956#define WM8995_AIF2DAC_EQ_B4_GAIN_SHIFT 11 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
2957#define WM8995_AIF2DAC_EQ_B4_GAIN_WIDTH 5 /* AIF2DAC_EQ_B4_GAIN - [15:11] */
2958#define WM8995_AIF2DAC_EQ_B5_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
2959#define WM8995_AIF2DAC_EQ_B5_GAIN_SHIFT 6 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
2960#define WM8995_AIF2DAC_EQ_B5_GAIN_WIDTH 5 /* AIF2DAC_EQ_B5_GAIN - [10:6] */
2961
2962/*
2963 * R1410 (0x582) - AIF2 EQ Band 1 A
2964 */
2965#define WM8995_AIF2DAC_EQ_B1_A_MASK 0xFFFF /* AIF2DAC_EQ_B1_A - [15:0] */
2966#define WM8995_AIF2DAC_EQ_B1_A_SHIFT 0 /* AIF2DAC_EQ_B1_A - [15:0] */
2967#define WM8995_AIF2DAC_EQ_B1_A_WIDTH 16 /* AIF2DAC_EQ_B1_A - [15:0] */
2968
2969/*
2970 * R1411 (0x583) - AIF2 EQ Band 1 B
2971 */
2972#define WM8995_AIF2DAC_EQ_B1_B_MASK 0xFFFF /* AIF2DAC_EQ_B1_B - [15:0] */
2973#define WM8995_AIF2DAC_EQ_B1_B_SHIFT 0 /* AIF2DAC_EQ_B1_B - [15:0] */
2974#define WM8995_AIF2DAC_EQ_B1_B_WIDTH 16 /* AIF2DAC_EQ_B1_B - [15:0] */
2975
2976/*
2977 * R1412 (0x584) - AIF2 EQ Band 1 PG
2978 */
2979#define WM8995_AIF2DAC_EQ_B1_PG_MASK 0xFFFF /* AIF2DAC_EQ_B1_PG - [15:0] */
2980#define WM8995_AIF2DAC_EQ_B1_PG_SHIFT 0 /* AIF2DAC_EQ_B1_PG - [15:0] */
2981#define WM8995_AIF2DAC_EQ_B1_PG_WIDTH 16 /* AIF2DAC_EQ_B1_PG - [15:0] */
2982
2983/*
2984 * R1413 (0x585) - AIF2 EQ Band 2 A
2985 */
2986#define WM8995_AIF2DAC_EQ_B2_A_MASK 0xFFFF /* AIF2DAC_EQ_B2_A - [15:0] */
2987#define WM8995_AIF2DAC_EQ_B2_A_SHIFT 0 /* AIF2DAC_EQ_B2_A - [15:0] */
2988#define WM8995_AIF2DAC_EQ_B2_A_WIDTH 16 /* AIF2DAC_EQ_B2_A - [15:0] */
2989
2990/*
2991 * R1414 (0x586) - AIF2 EQ Band 2 B
2992 */
2993#define WM8995_AIF2DAC_EQ_B2_B_MASK 0xFFFF /* AIF2DAC_EQ_B2_B - [15:0] */
2994#define WM8995_AIF2DAC_EQ_B2_B_SHIFT 0 /* AIF2DAC_EQ_B2_B - [15:0] */
2995#define WM8995_AIF2DAC_EQ_B2_B_WIDTH 16 /* AIF2DAC_EQ_B2_B - [15:0] */
2996
2997/*
2998 * R1415 (0x587) - AIF2 EQ Band 2 C
2999 */
3000#define WM8995_AIF2DAC_EQ_B2_C_MASK 0xFFFF /* AIF2DAC_EQ_B2_C - [15:0] */
3001#define WM8995_AIF2DAC_EQ_B2_C_SHIFT 0 /* AIF2DAC_EQ_B2_C - [15:0] */
3002#define WM8995_AIF2DAC_EQ_B2_C_WIDTH 16 /* AIF2DAC_EQ_B2_C - [15:0] */
3003
3004/*
3005 * R1416 (0x588) - AIF2 EQ Band 2 PG
3006 */
3007#define WM8995_AIF2DAC_EQ_B2_PG_MASK 0xFFFF /* AIF2DAC_EQ_B2_PG - [15:0] */
3008#define WM8995_AIF2DAC_EQ_B2_PG_SHIFT 0 /* AIF2DAC_EQ_B2_PG - [15:0] */
3009#define WM8995_AIF2DAC_EQ_B2_PG_WIDTH 16 /* AIF2DAC_EQ_B2_PG - [15:0] */
3010
3011/*
3012 * R1417 (0x589) - AIF2 EQ Band 3 A
3013 */
3014#define WM8995_AIF2DAC_EQ_B3_A_MASK 0xFFFF /* AIF2DAC_EQ_B3_A - [15:0] */
3015#define WM8995_AIF2DAC_EQ_B3_A_SHIFT 0 /* AIF2DAC_EQ_B3_A - [15:0] */
3016#define WM8995_AIF2DAC_EQ_B3_A_WIDTH 16 /* AIF2DAC_EQ_B3_A - [15:0] */
3017
3018/*
3019 * R1418 (0x58A) - AIF2 EQ Band 3 B
3020 */
3021#define WM8995_AIF2DAC_EQ_B3_B_MASK 0xFFFF /* AIF2DAC_EQ_B3_B - [15:0] */
3022#define WM8995_AIF2DAC_EQ_B3_B_SHIFT 0 /* AIF2DAC_EQ_B3_B - [15:0] */
3023#define WM8995_AIF2DAC_EQ_B3_B_WIDTH 16 /* AIF2DAC_EQ_B3_B - [15:0] */
3024
3025/*
3026 * R1419 (0x58B) - AIF2 EQ Band 3 C
3027 */
3028#define WM8995_AIF2DAC_EQ_B3_C_MASK 0xFFFF /* AIF2DAC_EQ_B3_C - [15:0] */
3029#define WM8995_AIF2DAC_EQ_B3_C_SHIFT 0 /* AIF2DAC_EQ_B3_C - [15:0] */
3030#define WM8995_AIF2DAC_EQ_B3_C_WIDTH 16 /* AIF2DAC_EQ_B3_C - [15:0] */
3031
3032/*
3033 * R1420 (0x58C) - AIF2 EQ Band 3 PG
3034 */
3035#define WM8995_AIF2DAC_EQ_B3_PG_MASK 0xFFFF /* AIF2DAC_EQ_B3_PG - [15:0] */
3036#define WM8995_AIF2DAC_EQ_B3_PG_SHIFT 0 /* AIF2DAC_EQ_B3_PG - [15:0] */
3037#define WM8995_AIF2DAC_EQ_B3_PG_WIDTH 16 /* AIF2DAC_EQ_B3_PG - [15:0] */
3038
3039/*
3040 * R1421 (0x58D) - AIF2 EQ Band 4 A
3041 */
3042#define WM8995_AIF2DAC_EQ_B4_A_MASK 0xFFFF /* AIF2DAC_EQ_B4_A - [15:0] */
3043#define WM8995_AIF2DAC_EQ_B4_A_SHIFT 0 /* AIF2DAC_EQ_B4_A - [15:0] */
3044#define WM8995_AIF2DAC_EQ_B4_A_WIDTH 16 /* AIF2DAC_EQ_B4_A - [15:0] */
3045
3046/*
3047 * R1422 (0x58E) - AIF2 EQ Band 4 B
3048 */
3049#define WM8995_AIF2DAC_EQ_B4_B_MASK 0xFFFF /* AIF2DAC_EQ_B4_B - [15:0] */
3050#define WM8995_AIF2DAC_EQ_B4_B_SHIFT 0 /* AIF2DAC_EQ_B4_B - [15:0] */
3051#define WM8995_AIF2DAC_EQ_B4_B_WIDTH 16 /* AIF2DAC_EQ_B4_B - [15:0] */
3052
3053/*
3054 * R1423 (0x58F) - AIF2 EQ Band 4 C
3055 */
3056#define WM8995_AIF2DAC_EQ_B4_C_MASK 0xFFFF /* AIF2DAC_EQ_B4_C - [15:0] */
3057#define WM8995_AIF2DAC_EQ_B4_C_SHIFT 0 /* AIF2DAC_EQ_B4_C - [15:0] */
3058#define WM8995_AIF2DAC_EQ_B4_C_WIDTH 16 /* AIF2DAC_EQ_B4_C - [15:0] */
3059
3060/*
3061 * R1424 (0x590) - AIF2 EQ Band 4 PG
3062 */
3063#define WM8995_AIF2DAC_EQ_B4_PG_MASK 0xFFFF /* AIF2DAC_EQ_B4_PG - [15:0] */
3064#define WM8995_AIF2DAC_EQ_B4_PG_SHIFT 0 /* AIF2DAC_EQ_B4_PG - [15:0] */
3065#define WM8995_AIF2DAC_EQ_B4_PG_WIDTH 16 /* AIF2DAC_EQ_B4_PG - [15:0] */
3066
3067/*
3068 * R1425 (0x591) - AIF2 EQ Band 5 A
3069 */
3070#define WM8995_AIF2DAC_EQ_B5_A_MASK 0xFFFF /* AIF2DAC_EQ_B5_A - [15:0] */
3071#define WM8995_AIF2DAC_EQ_B5_A_SHIFT 0 /* AIF2DAC_EQ_B5_A - [15:0] */
3072#define WM8995_AIF2DAC_EQ_B5_A_WIDTH 16 /* AIF2DAC_EQ_B5_A - [15:0] */
3073
3074/*
3075 * R1426 (0x592) - AIF2 EQ Band 5 B
3076 */
3077#define WM8995_AIF2DAC_EQ_B5_B_MASK 0xFFFF /* AIF2DAC_EQ_B5_B - [15:0] */
3078#define WM8995_AIF2DAC_EQ_B5_B_SHIFT 0 /* AIF2DAC_EQ_B5_B - [15:0] */
3079#define WM8995_AIF2DAC_EQ_B5_B_WIDTH 16 /* AIF2DAC_EQ_B5_B - [15:0] */
3080
3081/*
3082 * R1427 (0x593) - AIF2 EQ Band 5 PG
3083 */
3084#define WM8995_AIF2DAC_EQ_B5_PG_MASK 0xFFFF /* AIF2DAC_EQ_B5_PG - [15:0] */
3085#define WM8995_AIF2DAC_EQ_B5_PG_SHIFT 0 /* AIF2DAC_EQ_B5_PG - [15:0] */
3086#define WM8995_AIF2DAC_EQ_B5_PG_WIDTH 16 /* AIF2DAC_EQ_B5_PG - [15:0] */
3087
3088/*
3089 * R1536 (0x600) - DAC1 Mixer Volumes
3090 */
3091#define WM8995_ADCR_DAC1_VOL_MASK 0x03E0 /* ADCR_DAC1_VOL - [9:5] */
3092#define WM8995_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [9:5] */
3093#define WM8995_ADCR_DAC1_VOL_WIDTH 5 /* ADCR_DAC1_VOL - [9:5] */
3094#define WM8995_ADCL_DAC1_VOL_MASK 0x001F /* ADCL_DAC1_VOL - [4:0] */
3095#define WM8995_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [4:0] */
3096#define WM8995_ADCL_DAC1_VOL_WIDTH 5 /* ADCL_DAC1_VOL - [4:0] */
3097
3098/*
3099 * R1537 (0x601) - DAC1 Left Mixer Routing
3100 */
3101#define WM8995_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */
3102#define WM8995_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */
3103#define WM8995_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */
3104#define WM8995_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */
3105#define WM8995_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */
3106#define WM8995_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */
3107#define WM8995_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */
3108#define WM8995_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */
3109#define WM8995_AIF2DACL_TO_DAC1L 0x0004 /* AIF2DACL_TO_DAC1L */
3110#define WM8995_AIF2DACL_TO_DAC1L_MASK 0x0004 /* AIF2DACL_TO_DAC1L */
3111#define WM8995_AIF2DACL_TO_DAC1L_SHIFT 2 /* AIF2DACL_TO_DAC1L */
3112#define WM8995_AIF2DACL_TO_DAC1L_WIDTH 1 /* AIF2DACL_TO_DAC1L */
3113#define WM8995_AIF1DAC2L_TO_DAC1L 0x0002 /* AIF1DAC2L_TO_DAC1L */
3114#define WM8995_AIF1DAC2L_TO_DAC1L_MASK 0x0002 /* AIF1DAC2L_TO_DAC1L */
3115#define WM8995_AIF1DAC2L_TO_DAC1L_SHIFT 1 /* AIF1DAC2L_TO_DAC1L */
3116#define WM8995_AIF1DAC2L_TO_DAC1L_WIDTH 1 /* AIF1DAC2L_TO_DAC1L */
3117#define WM8995_AIF1DAC1L_TO_DAC1L 0x0001 /* AIF1DAC1L_TO_DAC1L */
3118#define WM8995_AIF1DAC1L_TO_DAC1L_MASK 0x0001 /* AIF1DAC1L_TO_DAC1L */
3119#define WM8995_AIF1DAC1L_TO_DAC1L_SHIFT 0 /* AIF1DAC1L_TO_DAC1L */
3120#define WM8995_AIF1DAC1L_TO_DAC1L_WIDTH 1 /* AIF1DAC1L_TO_DAC1L */
3121
3122/*
3123 * R1538 (0x602) - DAC1 Right Mixer Routing
3124 */
3125#define WM8995_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */
3126#define WM8995_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */
3127#define WM8995_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */
3128#define WM8995_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */
3129#define WM8995_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */
3130#define WM8995_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */
3131#define WM8995_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */
3132#define WM8995_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */
3133#define WM8995_AIF2DACR_TO_DAC1R 0x0004 /* AIF2DACR_TO_DAC1R */
3134#define WM8995_AIF2DACR_TO_DAC1R_MASK 0x0004 /* AIF2DACR_TO_DAC1R */
3135#define WM8995_AIF2DACR_TO_DAC1R_SHIFT 2 /* AIF2DACR_TO_DAC1R */
3136#define WM8995_AIF2DACR_TO_DAC1R_WIDTH 1 /* AIF2DACR_TO_DAC1R */
3137#define WM8995_AIF1DAC2R_TO_DAC1R 0x0002 /* AIF1DAC2R_TO_DAC1R */
3138#define WM8995_AIF1DAC2R_TO_DAC1R_MASK 0x0002 /* AIF1DAC2R_TO_DAC1R */
3139#define WM8995_AIF1DAC2R_TO_DAC1R_SHIFT 1 /* AIF1DAC2R_TO_DAC1R */
3140#define WM8995_AIF1DAC2R_TO_DAC1R_WIDTH 1 /* AIF1DAC2R_TO_DAC1R */
3141#define WM8995_AIF1DAC1R_TO_DAC1R 0x0001 /* AIF1DAC1R_TO_DAC1R */
3142#define WM8995_AIF1DAC1R_TO_DAC1R_MASK 0x0001 /* AIF1DAC1R_TO_DAC1R */
3143#define WM8995_AIF1DAC1R_TO_DAC1R_SHIFT 0 /* AIF1DAC1R_TO_DAC1R */
3144#define WM8995_AIF1DAC1R_TO_DAC1R_WIDTH 1 /* AIF1DAC1R_TO_DAC1R */
3145
3146/*
3147 * R1539 (0x603) - DAC2 Mixer Volumes
3148 */
3149#define WM8995_ADCR_DAC2_VOL_MASK 0x03E0 /* ADCR_DAC2_VOL - [9:5] */
3150#define WM8995_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [9:5] */
3151#define WM8995_ADCR_DAC2_VOL_WIDTH 5 /* ADCR_DAC2_VOL - [9:5] */
3152#define WM8995_ADCL_DAC2_VOL_MASK 0x001F /* ADCL_DAC2_VOL - [4:0] */
3153#define WM8995_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [4:0] */
3154#define WM8995_ADCL_DAC2_VOL_WIDTH 5 /* ADCL_DAC2_VOL - [4:0] */
3155
3156/*
3157 * R1540 (0x604) - DAC2 Left Mixer Routing
3158 */
3159#define WM8995_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */
3160#define WM8995_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */
3161#define WM8995_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */
3162#define WM8995_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */
3163#define WM8995_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */
3164#define WM8995_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */
3165#define WM8995_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */
3166#define WM8995_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */
3167#define WM8995_AIF2DACL_TO_DAC2L 0x0004 /* AIF2DACL_TO_DAC2L */
3168#define WM8995_AIF2DACL_TO_DAC2L_MASK 0x0004 /* AIF2DACL_TO_DAC2L */
3169#define WM8995_AIF2DACL_TO_DAC2L_SHIFT 2 /* AIF2DACL_TO_DAC2L */
3170#define WM8995_AIF2DACL_TO_DAC2L_WIDTH 1 /* AIF2DACL_TO_DAC2L */
3171#define WM8995_AIF1DAC2L_TO_DAC2L 0x0002 /* AIF1DAC2L_TO_DAC2L */
3172#define WM8995_AIF1DAC2L_TO_DAC2L_MASK 0x0002 /* AIF1DAC2L_TO_DAC2L */
3173#define WM8995_AIF1DAC2L_TO_DAC2L_SHIFT 1 /* AIF1DAC2L_TO_DAC2L */
3174#define WM8995_AIF1DAC2L_TO_DAC2L_WIDTH 1 /* AIF1DAC2L_TO_DAC2L */
3175#define WM8995_AIF1DAC1L_TO_DAC2L 0x0001 /* AIF1DAC1L_TO_DAC2L */
3176#define WM8995_AIF1DAC1L_TO_DAC2L_MASK 0x0001 /* AIF1DAC1L_TO_DAC2L */
3177#define WM8995_AIF1DAC1L_TO_DAC2L_SHIFT 0 /* AIF1DAC1L_TO_DAC2L */
3178#define WM8995_AIF1DAC1L_TO_DAC2L_WIDTH 1 /* AIF1DAC1L_TO_DAC2L */
3179
3180/*
3181 * R1541 (0x605) - DAC2 Right Mixer Routing
3182 */
3183#define WM8995_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */
3184#define WM8995_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */
3185#define WM8995_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */
3186#define WM8995_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */
3187#define WM8995_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */
3188#define WM8995_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */
3189#define WM8995_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */
3190#define WM8995_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */
3191#define WM8995_AIF2DACR_TO_DAC2R 0x0004 /* AIF2DACR_TO_DAC2R */
3192#define WM8995_AIF2DACR_TO_DAC2R_MASK 0x0004 /* AIF2DACR_TO_DAC2R */
3193#define WM8995_AIF2DACR_TO_DAC2R_SHIFT 2 /* AIF2DACR_TO_DAC2R */
3194#define WM8995_AIF2DACR_TO_DAC2R_WIDTH 1 /* AIF2DACR_TO_DAC2R */
3195#define WM8995_AIF1DAC2R_TO_DAC2R 0x0002 /* AIF1DAC2R_TO_DAC2R */
3196#define WM8995_AIF1DAC2R_TO_DAC2R_MASK 0x0002 /* AIF1DAC2R_TO_DAC2R */
3197#define WM8995_AIF1DAC2R_TO_DAC2R_SHIFT 1 /* AIF1DAC2R_TO_DAC2R */
3198#define WM8995_AIF1DAC2R_TO_DAC2R_WIDTH 1 /* AIF1DAC2R_TO_DAC2R */
3199#define WM8995_AIF1DAC1R_TO_DAC2R 0x0001 /* AIF1DAC1R_TO_DAC2R */
3200#define WM8995_AIF1DAC1R_TO_DAC2R_MASK 0x0001 /* AIF1DAC1R_TO_DAC2R */
3201#define WM8995_AIF1DAC1R_TO_DAC2R_SHIFT 0 /* AIF1DAC1R_TO_DAC2R */
3202#define WM8995_AIF1DAC1R_TO_DAC2R_WIDTH 1 /* AIF1DAC1R_TO_DAC2R */
3203
3204/*
3205 * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing
3206 */
3207#define WM8995_ADC1L_TO_AIF1ADC1L 0x0002 /* ADC1L_TO_AIF1ADC1L */
3208#define WM8995_ADC1L_TO_AIF1ADC1L_MASK 0x0002 /* ADC1L_TO_AIF1ADC1L */
3209#define WM8995_ADC1L_TO_AIF1ADC1L_SHIFT 1 /* ADC1L_TO_AIF1ADC1L */
3210#define WM8995_ADC1L_TO_AIF1ADC1L_WIDTH 1 /* ADC1L_TO_AIF1ADC1L */
3211#define WM8995_AIF2DACL_TO_AIF1ADC1L 0x0001 /* AIF2DACL_TO_AIF1ADC1L */
3212#define WM8995_AIF2DACL_TO_AIF1ADC1L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC1L */
3213#define WM8995_AIF2DACL_TO_AIF1ADC1L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC1L */
3214#define WM8995_AIF2DACL_TO_AIF1ADC1L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC1L */
3215
3216/*
3217 * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing
3218 */
3219#define WM8995_ADC1R_TO_AIF1ADC1R 0x0002 /* ADC1R_TO_AIF1ADC1R */
3220#define WM8995_ADC1R_TO_AIF1ADC1R_MASK 0x0002 /* ADC1R_TO_AIF1ADC1R */
3221#define WM8995_ADC1R_TO_AIF1ADC1R_SHIFT 1 /* ADC1R_TO_AIF1ADC1R */
3222#define WM8995_ADC1R_TO_AIF1ADC1R_WIDTH 1 /* ADC1R_TO_AIF1ADC1R */
3223#define WM8995_AIF2DACR_TO_AIF1ADC1R 0x0001 /* AIF2DACR_TO_AIF1ADC1R */
3224#define WM8995_AIF2DACR_TO_AIF1ADC1R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC1R */
3225#define WM8995_AIF2DACR_TO_AIF1ADC1R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC1R */
3226#define WM8995_AIF2DACR_TO_AIF1ADC1R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC1R */
3227
3228/*
3229 * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing
3230 */
3231#define WM8995_ADC2L_TO_AIF1ADC2L 0x0002 /* ADC2L_TO_AIF1ADC2L */
3232#define WM8995_ADC2L_TO_AIF1ADC2L_MASK 0x0002 /* ADC2L_TO_AIF1ADC2L */
3233#define WM8995_ADC2L_TO_AIF1ADC2L_SHIFT 1 /* ADC2L_TO_AIF1ADC2L */
3234#define WM8995_ADC2L_TO_AIF1ADC2L_WIDTH 1 /* ADC2L_TO_AIF1ADC2L */
3235#define WM8995_AIF2DACL_TO_AIF1ADC2L 0x0001 /* AIF2DACL_TO_AIF1ADC2L */
3236#define WM8995_AIF2DACL_TO_AIF1ADC2L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC2L */
3237#define WM8995_AIF2DACL_TO_AIF1ADC2L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC2L */
3238#define WM8995_AIF2DACL_TO_AIF1ADC2L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC2L */
3239
3240/*
3241 * R1545 (0x609) - AIF1 ADC2 Right mixer Routing
3242 */
3243#define WM8995_ADC2R_TO_AIF1ADC2R 0x0002 /* ADC2R_TO_AIF1ADC2R */
3244#define WM8995_ADC2R_TO_AIF1ADC2R_MASK 0x0002 /* ADC2R_TO_AIF1ADC2R */
3245#define WM8995_ADC2R_TO_AIF1ADC2R_SHIFT 1 /* ADC2R_TO_AIF1ADC2R */
3246#define WM8995_ADC2R_TO_AIF1ADC2R_WIDTH 1 /* ADC2R_TO_AIF1ADC2R */
3247#define WM8995_AIF2DACR_TO_AIF1ADC2R 0x0001 /* AIF2DACR_TO_AIF1ADC2R */
3248#define WM8995_AIF2DACR_TO_AIF1ADC2R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC2R */
3249#define WM8995_AIF2DACR_TO_AIF1ADC2R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC2R */
3250#define WM8995_AIF2DACR_TO_AIF1ADC2R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC2R */
3251
3252/*
3253 * R1552 (0x610) - DAC Softmute
3254 */
3255#define WM8995_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */
3256#define WM8995_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */
3257#define WM8995_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */
3258#define WM8995_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */
3259#define WM8995_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */
3260#define WM8995_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */
3261#define WM8995_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */
3262#define WM8995_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
3263
3264/*
3265 * R1568 (0x620) - Oversampling
3266 */
3267#define WM8995_ADC_OSR128 0x0002 /* ADC_OSR128 */
3268#define WM8995_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */
3269#define WM8995_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */
3270#define WM8995_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */
3271#define WM8995_DAC_OSR128 0x0001 /* DAC_OSR128 */
3272#define WM8995_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */
3273#define WM8995_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */
3274#define WM8995_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */
3275
3276/*
3277 * R1569 (0x621) - Sidetone
3278 */
3279#define WM8995_ST_LPF 0x1000 /* ST_LPF */
3280#define WM8995_ST_LPF_MASK 0x1000 /* ST_LPF */
3281#define WM8995_ST_LPF_SHIFT 12 /* ST_LPF */
3282#define WM8995_ST_LPF_WIDTH 1 /* ST_LPF */
3283#define WM8995_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */
3284#define WM8995_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */
3285#define WM8995_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */
3286#define WM8995_ST_HPF 0x0040 /* ST_HPF */
3287#define WM8995_ST_HPF_MASK 0x0040 /* ST_HPF */
3288#define WM8995_ST_HPF_SHIFT 6 /* ST_HPF */
3289#define WM8995_ST_HPF_WIDTH 1 /* ST_HPF */
3290#define WM8995_STR_SEL 0x0002 /* STR_SEL */
3291#define WM8995_STR_SEL_MASK 0x0002 /* STR_SEL */
3292#define WM8995_STR_SEL_SHIFT 1 /* STR_SEL */
3293#define WM8995_STR_SEL_WIDTH 1 /* STR_SEL */
3294#define WM8995_STL_SEL 0x0001 /* STL_SEL */
3295#define WM8995_STL_SEL_MASK 0x0001 /* STL_SEL */
3296#define WM8995_STL_SEL_SHIFT 0 /* STL_SEL */
3297#define WM8995_STL_SEL_WIDTH 1 /* STL_SEL */
3298
3299/*
3300 * R1792 (0x700) - GPIO 1
3301 */
3302#define WM8995_GP1_DIR 0x8000 /* GP1_DIR */
3303#define WM8995_GP1_DIR_MASK 0x8000 /* GP1_DIR */
3304#define WM8995_GP1_DIR_SHIFT 15 /* GP1_DIR */
3305#define WM8995_GP1_DIR_WIDTH 1 /* GP1_DIR */
3306#define WM8995_GP1_PU 0x4000 /* GP1_PU */
3307#define WM8995_GP1_PU_MASK 0x4000 /* GP1_PU */
3308#define WM8995_GP1_PU_SHIFT 14 /* GP1_PU */
3309#define WM8995_GP1_PU_WIDTH 1 /* GP1_PU */
3310#define WM8995_GP1_PD 0x2000 /* GP1_PD */
3311#define WM8995_GP1_PD_MASK 0x2000 /* GP1_PD */
3312#define WM8995_GP1_PD_SHIFT 13 /* GP1_PD */
3313#define WM8995_GP1_PD_WIDTH 1 /* GP1_PD */
3314#define WM8995_GP1_POL 0x0400 /* GP1_POL */
3315#define WM8995_GP1_POL_MASK 0x0400 /* GP1_POL */
3316#define WM8995_GP1_POL_SHIFT 10 /* GP1_POL */
3317#define WM8995_GP1_POL_WIDTH 1 /* GP1_POL */
3318#define WM8995_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */
3319#define WM8995_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */
3320#define WM8995_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */
3321#define WM8995_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */
3322#define WM8995_GP1_DB 0x0100 /* GP1_DB */
3323#define WM8995_GP1_DB_MASK 0x0100 /* GP1_DB */
3324#define WM8995_GP1_DB_SHIFT 8 /* GP1_DB */
3325#define WM8995_GP1_DB_WIDTH 1 /* GP1_DB */
3326#define WM8995_GP1_LVL 0x0040 /* GP1_LVL */
3327#define WM8995_GP1_LVL_MASK 0x0040 /* GP1_LVL */
3328#define WM8995_GP1_LVL_SHIFT 6 /* GP1_LVL */
3329#define WM8995_GP1_LVL_WIDTH 1 /* GP1_LVL */
3330#define WM8995_GP1_FN_MASK 0x001F /* GP1_FN - [4:0] */
3331#define WM8995_GP1_FN_SHIFT 0 /* GP1_FN - [4:0] */
3332#define WM8995_GP1_FN_WIDTH 5 /* GP1_FN - [4:0] */
3333
3334/*
3335 * R1793 (0x701) - GPIO 2
3336 */
3337#define WM8995_GP2_DIR 0x8000 /* GP2_DIR */
3338#define WM8995_GP2_DIR_MASK 0x8000 /* GP2_DIR */
3339#define WM8995_GP2_DIR_SHIFT 15 /* GP2_DIR */
3340#define WM8995_GP2_DIR_WIDTH 1 /* GP2_DIR */
3341#define WM8995_GP2_PU 0x4000 /* GP2_PU */
3342#define WM8995_GP2_PU_MASK 0x4000 /* GP2_PU */
3343#define WM8995_GP2_PU_SHIFT 14 /* GP2_PU */
3344#define WM8995_GP2_PU_WIDTH 1 /* GP2_PU */
3345#define WM8995_GP2_PD 0x2000 /* GP2_PD */
3346#define WM8995_GP2_PD_MASK 0x2000 /* GP2_PD */
3347#define WM8995_GP2_PD_SHIFT 13 /* GP2_PD */
3348#define WM8995_GP2_PD_WIDTH 1 /* GP2_PD */
3349#define WM8995_GP2_POL 0x0400 /* GP2_POL */
3350#define WM8995_GP2_POL_MASK 0x0400 /* GP2_POL */
3351#define WM8995_GP2_POL_SHIFT 10 /* GP2_POL */
3352#define WM8995_GP2_POL_WIDTH 1 /* GP2_POL */
3353#define WM8995_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */
3354#define WM8995_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */
3355#define WM8995_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */
3356#define WM8995_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */
3357#define WM8995_GP2_DB 0x0100 /* GP2_DB */
3358#define WM8995_GP2_DB_MASK 0x0100 /* GP2_DB */
3359#define WM8995_GP2_DB_SHIFT 8 /* GP2_DB */
3360#define WM8995_GP2_DB_WIDTH 1 /* GP2_DB */
3361#define WM8995_GP2_LVL 0x0040 /* GP2_LVL */
3362#define WM8995_GP2_LVL_MASK 0x0040 /* GP2_LVL */
3363#define WM8995_GP2_LVL_SHIFT 6 /* GP2_LVL */
3364#define WM8995_GP2_LVL_WIDTH 1 /* GP2_LVL */
3365#define WM8995_GP2_FN_MASK 0x001F /* GP2_FN - [4:0] */
3366#define WM8995_GP2_FN_SHIFT 0 /* GP2_FN - [4:0] */
3367#define WM8995_GP2_FN_WIDTH 5 /* GP2_FN - [4:0] */
3368
3369/*
3370 * R1794 (0x702) - GPIO 3
3371 */
3372#define WM8995_GP3_DIR 0x8000 /* GP3_DIR */
3373#define WM8995_GP3_DIR_MASK 0x8000 /* GP3_DIR */
3374#define WM8995_GP3_DIR_SHIFT 15 /* GP3_DIR */
3375#define WM8995_GP3_DIR_WIDTH 1 /* GP3_DIR */
3376#define WM8995_GP3_PU 0x4000 /* GP3_PU */
3377#define WM8995_GP3_PU_MASK 0x4000 /* GP3_PU */
3378#define WM8995_GP3_PU_SHIFT 14 /* GP3_PU */
3379#define WM8995_GP3_PU_WIDTH 1 /* GP3_PU */
3380#define WM8995_GP3_PD 0x2000 /* GP3_PD */
3381#define WM8995_GP3_PD_MASK 0x2000 /* GP3_PD */
3382#define WM8995_GP3_PD_SHIFT 13 /* GP3_PD */
3383#define WM8995_GP3_PD_WIDTH 1 /* GP3_PD */
3384#define WM8995_GP3_POL 0x0400 /* GP3_POL */
3385#define WM8995_GP3_POL_MASK 0x0400 /* GP3_POL */
3386#define WM8995_GP3_POL_SHIFT 10 /* GP3_POL */
3387#define WM8995_GP3_POL_WIDTH 1 /* GP3_POL */
3388#define WM8995_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */
3389#define WM8995_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */
3390#define WM8995_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */
3391#define WM8995_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */
3392#define WM8995_GP3_DB 0x0100 /* GP3_DB */
3393#define WM8995_GP3_DB_MASK 0x0100 /* GP3_DB */
3394#define WM8995_GP3_DB_SHIFT 8 /* GP3_DB */
3395#define WM8995_GP3_DB_WIDTH 1 /* GP3_DB */
3396#define WM8995_GP3_LVL 0x0040 /* GP3_LVL */
3397#define WM8995_GP3_LVL_MASK 0x0040 /* GP3_LVL */
3398#define WM8995_GP3_LVL_SHIFT 6 /* GP3_LVL */
3399#define WM8995_GP3_LVL_WIDTH 1 /* GP3_LVL */
3400#define WM8995_GP3_FN_MASK 0x001F /* GP3_FN - [4:0] */
3401#define WM8995_GP3_FN_SHIFT 0 /* GP3_FN - [4:0] */
3402#define WM8995_GP3_FN_WIDTH 5 /* GP3_FN - [4:0] */
3403
3404/*
3405 * R1795 (0x703) - GPIO 4
3406 */
3407#define WM8995_GP4_DIR 0x8000 /* GP4_DIR */
3408#define WM8995_GP4_DIR_MASK 0x8000 /* GP4_DIR */
3409#define WM8995_GP4_DIR_SHIFT 15 /* GP4_DIR */
3410#define WM8995_GP4_DIR_WIDTH 1 /* GP4_DIR */
3411#define WM8995_GP4_PU 0x4000 /* GP4_PU */
3412#define WM8995_GP4_PU_MASK 0x4000 /* GP4_PU */
3413#define WM8995_GP4_PU_SHIFT 14 /* GP4_PU */
3414#define WM8995_GP4_PU_WIDTH 1 /* GP4_PU */
3415#define WM8995_GP4_PD 0x2000 /* GP4_PD */
3416#define WM8995_GP4_PD_MASK 0x2000 /* GP4_PD */
3417#define WM8995_GP4_PD_SHIFT 13 /* GP4_PD */
3418#define WM8995_GP4_PD_WIDTH 1 /* GP4_PD */
3419#define WM8995_GP4_POL 0x0400 /* GP4_POL */
3420#define WM8995_GP4_POL_MASK 0x0400 /* GP4_POL */
3421#define WM8995_GP4_POL_SHIFT 10 /* GP4_POL */
3422#define WM8995_GP4_POL_WIDTH 1 /* GP4_POL */
3423#define WM8995_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */
3424#define WM8995_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */
3425#define WM8995_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */
3426#define WM8995_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */
3427#define WM8995_GP4_DB 0x0100 /* GP4_DB */
3428#define WM8995_GP4_DB_MASK 0x0100 /* GP4_DB */
3429#define WM8995_GP4_DB_SHIFT 8 /* GP4_DB */
3430#define WM8995_GP4_DB_WIDTH 1 /* GP4_DB */
3431#define WM8995_GP4_LVL 0x0040 /* GP4_LVL */
3432#define WM8995_GP4_LVL_MASK 0x0040 /* GP4_LVL */
3433#define WM8995_GP4_LVL_SHIFT 6 /* GP4_LVL */
3434#define WM8995_GP4_LVL_WIDTH 1 /* GP4_LVL */
3435#define WM8995_GP4_FN_MASK 0x001F /* GP4_FN - [4:0] */
3436#define WM8995_GP4_FN_SHIFT 0 /* GP4_FN - [4:0] */
3437#define WM8995_GP4_FN_WIDTH 5 /* GP4_FN - [4:0] */
3438
3439/*
3440 * R1796 (0x704) - GPIO 5
3441 */
3442#define WM8995_GP5_DIR 0x8000 /* GP5_DIR */
3443#define WM8995_GP5_DIR_MASK 0x8000 /* GP5_DIR */
3444#define WM8995_GP5_DIR_SHIFT 15 /* GP5_DIR */
3445#define WM8995_GP5_DIR_WIDTH 1 /* GP5_DIR */
3446#define WM8995_GP5_PU 0x4000 /* GP5_PU */
3447#define WM8995_GP5_PU_MASK 0x4000 /* GP5_PU */
3448#define WM8995_GP5_PU_SHIFT 14 /* GP5_PU */
3449#define WM8995_GP5_PU_WIDTH 1 /* GP5_PU */
3450#define WM8995_GP5_PD 0x2000 /* GP5_PD */
3451#define WM8995_GP5_PD_MASK 0x2000 /* GP5_PD */
3452#define WM8995_GP5_PD_SHIFT 13 /* GP5_PD */
3453#define WM8995_GP5_PD_WIDTH 1 /* GP5_PD */
3454#define WM8995_GP5_POL 0x0400 /* GP5_POL */
3455#define WM8995_GP5_POL_MASK 0x0400 /* GP5_POL */
3456#define WM8995_GP5_POL_SHIFT 10 /* GP5_POL */
3457#define WM8995_GP5_POL_WIDTH 1 /* GP5_POL */
3458#define WM8995_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */
3459#define WM8995_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */
3460#define WM8995_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */
3461#define WM8995_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */
3462#define WM8995_GP5_DB 0x0100 /* GP5_DB */
3463#define WM8995_GP5_DB_MASK 0x0100 /* GP5_DB */
3464#define WM8995_GP5_DB_SHIFT 8 /* GP5_DB */
3465#define WM8995_GP5_DB_WIDTH 1 /* GP5_DB */
3466#define WM8995_GP5_LVL 0x0040 /* GP5_LVL */
3467#define WM8995_GP5_LVL_MASK 0x0040 /* GP5_LVL */
3468#define WM8995_GP5_LVL_SHIFT 6 /* GP5_LVL */
3469#define WM8995_GP5_LVL_WIDTH 1 /* GP5_LVL */
3470#define WM8995_GP5_FN_MASK 0x001F /* GP5_FN - [4:0] */
3471#define WM8995_GP5_FN_SHIFT 0 /* GP5_FN - [4:0] */
3472#define WM8995_GP5_FN_WIDTH 5 /* GP5_FN - [4:0] */
3473
3474/*
3475 * R1797 (0x705) - GPIO 6
3476 */
3477#define WM8995_GP6_DIR 0x8000 /* GP6_DIR */
3478#define WM8995_GP6_DIR_MASK 0x8000 /* GP6_DIR */
3479#define WM8995_GP6_DIR_SHIFT 15 /* GP6_DIR */
3480#define WM8995_GP6_DIR_WIDTH 1 /* GP6_DIR */
3481#define WM8995_GP6_PU 0x4000 /* GP6_PU */
3482#define WM8995_GP6_PU_MASK 0x4000 /* GP6_PU */
3483#define WM8995_GP6_PU_SHIFT 14 /* GP6_PU */
3484#define WM8995_GP6_PU_WIDTH 1 /* GP6_PU */
3485#define WM8995_GP6_PD 0x2000 /* GP6_PD */
3486#define WM8995_GP6_PD_MASK 0x2000 /* GP6_PD */
3487#define WM8995_GP6_PD_SHIFT 13 /* GP6_PD */
3488#define WM8995_GP6_PD_WIDTH 1 /* GP6_PD */
3489#define WM8995_GP6_POL 0x0400 /* GP6_POL */
3490#define WM8995_GP6_POL_MASK 0x0400 /* GP6_POL */
3491#define WM8995_GP6_POL_SHIFT 10 /* GP6_POL */
3492#define WM8995_GP6_POL_WIDTH 1 /* GP6_POL */
3493#define WM8995_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */
3494#define WM8995_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */
3495#define WM8995_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */
3496#define WM8995_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */
3497#define WM8995_GP6_DB 0x0100 /* GP6_DB */
3498#define WM8995_GP6_DB_MASK 0x0100 /* GP6_DB */
3499#define WM8995_GP6_DB_SHIFT 8 /* GP6_DB */
3500#define WM8995_GP6_DB_WIDTH 1 /* GP6_DB */
3501#define WM8995_GP6_LVL 0x0040 /* GP6_LVL */
3502#define WM8995_GP6_LVL_MASK 0x0040 /* GP6_LVL */
3503#define WM8995_GP6_LVL_SHIFT 6 /* GP6_LVL */
3504#define WM8995_GP6_LVL_WIDTH 1 /* GP6_LVL */
3505#define WM8995_GP6_FN_MASK 0x001F /* GP6_FN - [4:0] */
3506#define WM8995_GP6_FN_SHIFT 0 /* GP6_FN - [4:0] */
3507#define WM8995_GP6_FN_WIDTH 5 /* GP6_FN - [4:0] */
3508
3509/*
3510 * R1798 (0x706) - GPIO 7
3511 */
3512#define WM8995_GP7_DIR 0x8000 /* GP7_DIR */
3513#define WM8995_GP7_DIR_MASK 0x8000 /* GP7_DIR */
3514#define WM8995_GP7_DIR_SHIFT 15 /* GP7_DIR */
3515#define WM8995_GP7_DIR_WIDTH 1 /* GP7_DIR */
3516#define WM8995_GP7_PU 0x4000 /* GP7_PU */
3517#define WM8995_GP7_PU_MASK 0x4000 /* GP7_PU */
3518#define WM8995_GP7_PU_SHIFT 14 /* GP7_PU */
3519#define WM8995_GP7_PU_WIDTH 1 /* GP7_PU */
3520#define WM8995_GP7_PD 0x2000 /* GP7_PD */
3521#define WM8995_GP7_PD_MASK 0x2000 /* GP7_PD */
3522#define WM8995_GP7_PD_SHIFT 13 /* GP7_PD */
3523#define WM8995_GP7_PD_WIDTH 1 /* GP7_PD */
3524#define WM8995_GP7_POL 0x0400 /* GP7_POL */
3525#define WM8995_GP7_POL_MASK 0x0400 /* GP7_POL */
3526#define WM8995_GP7_POL_SHIFT 10 /* GP7_POL */
3527#define WM8995_GP7_POL_WIDTH 1 /* GP7_POL */
3528#define WM8995_GP7_OP_CFG 0x0200 /* GP7_OP_CFG */
3529#define WM8995_GP7_OP_CFG_MASK 0x0200 /* GP7_OP_CFG */
3530#define WM8995_GP7_OP_CFG_SHIFT 9 /* GP7_OP_CFG */
3531#define WM8995_GP7_OP_CFG_WIDTH 1 /* GP7_OP_CFG */
3532#define WM8995_GP7_DB 0x0100 /* GP7_DB */
3533#define WM8995_GP7_DB_MASK 0x0100 /* GP7_DB */
3534#define WM8995_GP7_DB_SHIFT 8 /* GP7_DB */
3535#define WM8995_GP7_DB_WIDTH 1 /* GP7_DB */
3536#define WM8995_GP7_LVL 0x0040 /* GP7_LVL */
3537#define WM8995_GP7_LVL_MASK 0x0040 /* GP7_LVL */
3538#define WM8995_GP7_LVL_SHIFT 6 /* GP7_LVL */
3539#define WM8995_GP7_LVL_WIDTH 1 /* GP7_LVL */
3540#define WM8995_GP7_FN_MASK 0x001F /* GP7_FN - [4:0] */
3541#define WM8995_GP7_FN_SHIFT 0 /* GP7_FN - [4:0] */
3542#define WM8995_GP7_FN_WIDTH 5 /* GP7_FN - [4:0] */
3543
3544/*
3545 * R1799 (0x707) - GPIO 8
3546 */
3547#define WM8995_GP8_DIR 0x8000 /* GP8_DIR */
3548#define WM8995_GP8_DIR_MASK 0x8000 /* GP8_DIR */
3549#define WM8995_GP8_DIR_SHIFT 15 /* GP8_DIR */
3550#define WM8995_GP8_DIR_WIDTH 1 /* GP8_DIR */
3551#define WM8995_GP8_PU 0x4000 /* GP8_PU */
3552#define WM8995_GP8_PU_MASK 0x4000 /* GP8_PU */
3553#define WM8995_GP8_PU_SHIFT 14 /* GP8_PU */
3554#define WM8995_GP8_PU_WIDTH 1 /* GP8_PU */
3555#define WM8995_GP8_PD 0x2000 /* GP8_PD */
3556#define WM8995_GP8_PD_MASK 0x2000 /* GP8_PD */
3557#define WM8995_GP8_PD_SHIFT 13 /* GP8_PD */
3558#define WM8995_GP8_PD_WIDTH 1 /* GP8_PD */
3559#define WM8995_GP8_POL 0x0400 /* GP8_POL */
3560#define WM8995_GP8_POL_MASK 0x0400 /* GP8_POL */
3561#define WM8995_GP8_POL_SHIFT 10 /* GP8_POL */
3562#define WM8995_GP8_POL_WIDTH 1 /* GP8_POL */
3563#define WM8995_GP8_OP_CFG 0x0200 /* GP8_OP_CFG */
3564#define WM8995_GP8_OP_CFG_MASK 0x0200 /* GP8_OP_CFG */
3565#define WM8995_GP8_OP_CFG_SHIFT 9 /* GP8_OP_CFG */
3566#define WM8995_GP8_OP_CFG_WIDTH 1 /* GP8_OP_CFG */
3567#define WM8995_GP8_DB 0x0100 /* GP8_DB */
3568#define WM8995_GP8_DB_MASK 0x0100 /* GP8_DB */
3569#define WM8995_GP8_DB_SHIFT 8 /* GP8_DB */
3570#define WM8995_GP8_DB_WIDTH 1 /* GP8_DB */
3571#define WM8995_GP8_LVL 0x0040 /* GP8_LVL */
3572#define WM8995_GP8_LVL_MASK 0x0040 /* GP8_LVL */
3573#define WM8995_GP8_LVL_SHIFT 6 /* GP8_LVL */
3574#define WM8995_GP8_LVL_WIDTH 1 /* GP8_LVL */
3575#define WM8995_GP8_FN_MASK 0x001F /* GP8_FN - [4:0] */
3576#define WM8995_GP8_FN_SHIFT 0 /* GP8_FN - [4:0] */
3577#define WM8995_GP8_FN_WIDTH 5 /* GP8_FN - [4:0] */
3578
3579/*
3580 * R1800 (0x708) - GPIO 9
3581 */
3582#define WM8995_GP9_DIR 0x8000 /* GP9_DIR */
3583#define WM8995_GP9_DIR_MASK 0x8000 /* GP9_DIR */
3584#define WM8995_GP9_DIR_SHIFT 15 /* GP9_DIR */
3585#define WM8995_GP9_DIR_WIDTH 1 /* GP9_DIR */
3586#define WM8995_GP9_PU 0x4000 /* GP9_PU */
3587#define WM8995_GP9_PU_MASK 0x4000 /* GP9_PU */
3588#define WM8995_GP9_PU_SHIFT 14 /* GP9_PU */
3589#define WM8995_GP9_PU_WIDTH 1 /* GP9_PU */
3590#define WM8995_GP9_PD 0x2000 /* GP9_PD */
3591#define WM8995_GP9_PD_MASK 0x2000 /* GP9_PD */
3592#define WM8995_GP9_PD_SHIFT 13 /* GP9_PD */
3593#define WM8995_GP9_PD_WIDTH 1 /* GP9_PD */
3594#define WM8995_GP9_POL 0x0400 /* GP9_POL */
3595#define WM8995_GP9_POL_MASK 0x0400 /* GP9_POL */
3596#define WM8995_GP9_POL_SHIFT 10 /* GP9_POL */
3597#define WM8995_GP9_POL_WIDTH 1 /* GP9_POL */
3598#define WM8995_GP9_OP_CFG 0x0200 /* GP9_OP_CFG */
3599#define WM8995_GP9_OP_CFG_MASK 0x0200 /* GP9_OP_CFG */
3600#define WM8995_GP9_OP_CFG_SHIFT 9 /* GP9_OP_CFG */
3601#define WM8995_GP9_OP_CFG_WIDTH 1 /* GP9_OP_CFG */
3602#define WM8995_GP9_DB 0x0100 /* GP9_DB */
3603#define WM8995_GP9_DB_MASK 0x0100 /* GP9_DB */
3604#define WM8995_GP9_DB_SHIFT 8 /* GP9_DB */
3605#define WM8995_GP9_DB_WIDTH 1 /* GP9_DB */
3606#define WM8995_GP9_LVL 0x0040 /* GP9_LVL */
3607#define WM8995_GP9_LVL_MASK 0x0040 /* GP9_LVL */
3608#define WM8995_GP9_LVL_SHIFT 6 /* GP9_LVL */
3609#define WM8995_GP9_LVL_WIDTH 1 /* GP9_LVL */
3610#define WM8995_GP9_FN_MASK 0x001F /* GP9_FN - [4:0] */
3611#define WM8995_GP9_FN_SHIFT 0 /* GP9_FN - [4:0] */
3612#define WM8995_GP9_FN_WIDTH 5 /* GP9_FN - [4:0] */
3613
3614/*
3615 * R1801 (0x709) - GPIO 10
3616 */
3617#define WM8995_GP10_DIR 0x8000 /* GP10_DIR */
3618#define WM8995_GP10_DIR_MASK 0x8000 /* GP10_DIR */
3619#define WM8995_GP10_DIR_SHIFT 15 /* GP10_DIR */
3620#define WM8995_GP10_DIR_WIDTH 1 /* GP10_DIR */
3621#define WM8995_GP10_PU 0x4000 /* GP10_PU */
3622#define WM8995_GP10_PU_MASK 0x4000 /* GP10_PU */
3623#define WM8995_GP10_PU_SHIFT 14 /* GP10_PU */
3624#define WM8995_GP10_PU_WIDTH 1 /* GP10_PU */
3625#define WM8995_GP10_PD 0x2000 /* GP10_PD */
3626#define WM8995_GP10_PD_MASK 0x2000 /* GP10_PD */
3627#define WM8995_GP10_PD_SHIFT 13 /* GP10_PD */
3628#define WM8995_GP10_PD_WIDTH 1 /* GP10_PD */
3629#define WM8995_GP10_POL 0x0400 /* GP10_POL */
3630#define WM8995_GP10_POL_MASK 0x0400 /* GP10_POL */
3631#define WM8995_GP10_POL_SHIFT 10 /* GP10_POL */
3632#define WM8995_GP10_POL_WIDTH 1 /* GP10_POL */
3633#define WM8995_GP10_OP_CFG 0x0200 /* GP10_OP_CFG */
3634#define WM8995_GP10_OP_CFG_MASK 0x0200 /* GP10_OP_CFG */
3635#define WM8995_GP10_OP_CFG_SHIFT 9 /* GP10_OP_CFG */
3636#define WM8995_GP10_OP_CFG_WIDTH 1 /* GP10_OP_CFG */
3637#define WM8995_GP10_DB 0x0100 /* GP10_DB */
3638#define WM8995_GP10_DB_MASK 0x0100 /* GP10_DB */
3639#define WM8995_GP10_DB_SHIFT 8 /* GP10_DB */
3640#define WM8995_GP10_DB_WIDTH 1 /* GP10_DB */
3641#define WM8995_GP10_LVL 0x0040 /* GP10_LVL */
3642#define WM8995_GP10_LVL_MASK 0x0040 /* GP10_LVL */
3643#define WM8995_GP10_LVL_SHIFT 6 /* GP10_LVL */
3644#define WM8995_GP10_LVL_WIDTH 1 /* GP10_LVL */
3645#define WM8995_GP10_FN_MASK 0x001F /* GP10_FN - [4:0] */
3646#define WM8995_GP10_FN_SHIFT 0 /* GP10_FN - [4:0] */
3647#define WM8995_GP10_FN_WIDTH 5 /* GP10_FN - [4:0] */
3648
3649/*
3650 * R1802 (0x70A) - GPIO 11
3651 */
3652#define WM8995_GP11_DIR 0x8000 /* GP11_DIR */
3653#define WM8995_GP11_DIR_MASK 0x8000 /* GP11_DIR */
3654#define WM8995_GP11_DIR_SHIFT 15 /* GP11_DIR */
3655#define WM8995_GP11_DIR_WIDTH 1 /* GP11_DIR */
3656#define WM8995_GP11_PU 0x4000 /* GP11_PU */
3657#define WM8995_GP11_PU_MASK 0x4000 /* GP11_PU */
3658#define WM8995_GP11_PU_SHIFT 14 /* GP11_PU */
3659#define WM8995_GP11_PU_WIDTH 1 /* GP11_PU */
3660#define WM8995_GP11_PD 0x2000 /* GP11_PD */
3661#define WM8995_GP11_PD_MASK 0x2000 /* GP11_PD */
3662#define WM8995_GP11_PD_SHIFT 13 /* GP11_PD */
3663#define WM8995_GP11_PD_WIDTH 1 /* GP11_PD */
3664#define WM8995_GP11_POL 0x0400 /* GP11_POL */
3665#define WM8995_GP11_POL_MASK 0x0400 /* GP11_POL */
3666#define WM8995_GP11_POL_SHIFT 10 /* GP11_POL */
3667#define WM8995_GP11_POL_WIDTH 1 /* GP11_POL */
3668#define WM8995_GP11_OP_CFG 0x0200 /* GP11_OP_CFG */
3669#define WM8995_GP11_OP_CFG_MASK 0x0200 /* GP11_OP_CFG */
3670#define WM8995_GP11_OP_CFG_SHIFT 9 /* GP11_OP_CFG */
3671#define WM8995_GP11_OP_CFG_WIDTH 1 /* GP11_OP_CFG */
3672#define WM8995_GP11_DB 0x0100 /* GP11_DB */
3673#define WM8995_GP11_DB_MASK 0x0100 /* GP11_DB */
3674#define WM8995_GP11_DB_SHIFT 8 /* GP11_DB */
3675#define WM8995_GP11_DB_WIDTH 1 /* GP11_DB */
3676#define WM8995_GP11_LVL 0x0040 /* GP11_LVL */
3677#define WM8995_GP11_LVL_MASK 0x0040 /* GP11_LVL */
3678#define WM8995_GP11_LVL_SHIFT 6 /* GP11_LVL */
3679#define WM8995_GP11_LVL_WIDTH 1 /* GP11_LVL */
3680#define WM8995_GP11_FN_MASK 0x001F /* GP11_FN - [4:0] */
3681#define WM8995_GP11_FN_SHIFT 0 /* GP11_FN - [4:0] */
3682#define WM8995_GP11_FN_WIDTH 5 /* GP11_FN - [4:0] */
3683
3684/*
3685 * R1803 (0x70B) - GPIO 12
3686 */
3687#define WM8995_GP12_DIR 0x8000 /* GP12_DIR */
3688#define WM8995_GP12_DIR_MASK 0x8000 /* GP12_DIR */
3689#define WM8995_GP12_DIR_SHIFT 15 /* GP12_DIR */
3690#define WM8995_GP12_DIR_WIDTH 1 /* GP12_DIR */
3691#define WM8995_GP12_PU 0x4000 /* GP12_PU */
3692#define WM8995_GP12_PU_MASK 0x4000 /* GP12_PU */
3693#define WM8995_GP12_PU_SHIFT 14 /* GP12_PU */
3694#define WM8995_GP12_PU_WIDTH 1 /* GP12_PU */
3695#define WM8995_GP12_PD 0x2000 /* GP12_PD */
3696#define WM8995_GP12_PD_MASK 0x2000 /* GP12_PD */
3697#define WM8995_GP12_PD_SHIFT 13 /* GP12_PD */
3698#define WM8995_GP12_PD_WIDTH 1 /* GP12_PD */
3699#define WM8995_GP12_POL 0x0400 /* GP12_POL */
3700#define WM8995_GP12_POL_MASK 0x0400 /* GP12_POL */
3701#define WM8995_GP12_POL_SHIFT 10 /* GP12_POL */
3702#define WM8995_GP12_POL_WIDTH 1 /* GP12_POL */
3703#define WM8995_GP12_OP_CFG 0x0200 /* GP12_OP_CFG */
3704#define WM8995_GP12_OP_CFG_MASK 0x0200 /* GP12_OP_CFG */
3705#define WM8995_GP12_OP_CFG_SHIFT 9 /* GP12_OP_CFG */
3706#define WM8995_GP12_OP_CFG_WIDTH 1 /* GP12_OP_CFG */
3707#define WM8995_GP12_DB 0x0100 /* GP12_DB */
3708#define WM8995_GP12_DB_MASK 0x0100 /* GP12_DB */
3709#define WM8995_GP12_DB_SHIFT 8 /* GP12_DB */
3710#define WM8995_GP12_DB_WIDTH 1 /* GP12_DB */
3711#define WM8995_GP12_LVL 0x0040 /* GP12_LVL */
3712#define WM8995_GP12_LVL_MASK 0x0040 /* GP12_LVL */
3713#define WM8995_GP12_LVL_SHIFT 6 /* GP12_LVL */
3714#define WM8995_GP12_LVL_WIDTH 1 /* GP12_LVL */
3715#define WM8995_GP12_FN_MASK 0x001F /* GP12_FN - [4:0] */
3716#define WM8995_GP12_FN_SHIFT 0 /* GP12_FN - [4:0] */
3717#define WM8995_GP12_FN_WIDTH 5 /* GP12_FN - [4:0] */
3718
3719/*
3720 * R1804 (0x70C) - GPIO 13
3721 */
3722#define WM8995_GP13_DIR 0x8000 /* GP13_DIR */
3723#define WM8995_GP13_DIR_MASK 0x8000 /* GP13_DIR */
3724#define WM8995_GP13_DIR_SHIFT 15 /* GP13_DIR */
3725#define WM8995_GP13_DIR_WIDTH 1 /* GP13_DIR */
3726#define WM8995_GP13_PU 0x4000 /* GP13_PU */
3727#define WM8995_GP13_PU_MASK 0x4000 /* GP13_PU */
3728#define WM8995_GP13_PU_SHIFT 14 /* GP13_PU */
3729#define WM8995_GP13_PU_WIDTH 1 /* GP13_PU */
3730#define WM8995_GP13_PD 0x2000 /* GP13_PD */
3731#define WM8995_GP13_PD_MASK 0x2000 /* GP13_PD */
3732#define WM8995_GP13_PD_SHIFT 13 /* GP13_PD */
3733#define WM8995_GP13_PD_WIDTH 1 /* GP13_PD */
3734#define WM8995_GP13_POL 0x0400 /* GP13_POL */
3735#define WM8995_GP13_POL_MASK 0x0400 /* GP13_POL */
3736#define WM8995_GP13_POL_SHIFT 10 /* GP13_POL */
3737#define WM8995_GP13_POL_WIDTH 1 /* GP13_POL */
3738#define WM8995_GP13_OP_CFG 0x0200 /* GP13_OP_CFG */
3739#define WM8995_GP13_OP_CFG_MASK 0x0200 /* GP13_OP_CFG */
3740#define WM8995_GP13_OP_CFG_SHIFT 9 /* GP13_OP_CFG */
3741#define WM8995_GP13_OP_CFG_WIDTH 1 /* GP13_OP_CFG */
3742#define WM8995_GP13_DB 0x0100 /* GP13_DB */
3743#define WM8995_GP13_DB_MASK 0x0100 /* GP13_DB */
3744#define WM8995_GP13_DB_SHIFT 8 /* GP13_DB */
3745#define WM8995_GP13_DB_WIDTH 1 /* GP13_DB */
3746#define WM8995_GP13_LVL 0x0040 /* GP13_LVL */
3747#define WM8995_GP13_LVL_MASK 0x0040 /* GP13_LVL */
3748#define WM8995_GP13_LVL_SHIFT 6 /* GP13_LVL */
3749#define WM8995_GP13_LVL_WIDTH 1 /* GP13_LVL */
3750#define WM8995_GP13_FN_MASK 0x001F /* GP13_FN - [4:0] */
3751#define WM8995_GP13_FN_SHIFT 0 /* GP13_FN - [4:0] */
3752#define WM8995_GP13_FN_WIDTH 5 /* GP13_FN - [4:0] */
3753
3754/*
3755 * R1805 (0x70D) - GPIO 14
3756 */
3757#define WM8995_GP14_DIR 0x8000 /* GP14_DIR */
3758#define WM8995_GP14_DIR_MASK 0x8000 /* GP14_DIR */
3759#define WM8995_GP14_DIR_SHIFT 15 /* GP14_DIR */
3760#define WM8995_GP14_DIR_WIDTH 1 /* GP14_DIR */
3761#define WM8995_GP14_PU 0x4000 /* GP14_PU */
3762#define WM8995_GP14_PU_MASK 0x4000 /* GP14_PU */
3763#define WM8995_GP14_PU_SHIFT 14 /* GP14_PU */
3764#define WM8995_GP14_PU_WIDTH 1 /* GP14_PU */
3765#define WM8995_GP14_PD 0x2000 /* GP14_PD */
3766#define WM8995_GP14_PD_MASK 0x2000 /* GP14_PD */
3767#define WM8995_GP14_PD_SHIFT 13 /* GP14_PD */
3768#define WM8995_GP14_PD_WIDTH 1 /* GP14_PD */
3769#define WM8995_GP14_POL 0x0400 /* GP14_POL */
3770#define WM8995_GP14_POL_MASK 0x0400 /* GP14_POL */
3771#define WM8995_GP14_POL_SHIFT 10 /* GP14_POL */
3772#define WM8995_GP14_POL_WIDTH 1 /* GP14_POL */
3773#define WM8995_GP14_OP_CFG 0x0200 /* GP14_OP_CFG */
3774#define WM8995_GP14_OP_CFG_MASK 0x0200 /* GP14_OP_CFG */
3775#define WM8995_GP14_OP_CFG_SHIFT 9 /* GP14_OP_CFG */
3776#define WM8995_GP14_OP_CFG_WIDTH 1 /* GP14_OP_CFG */
3777#define WM8995_GP14_DB 0x0100 /* GP14_DB */
3778#define WM8995_GP14_DB_MASK 0x0100 /* GP14_DB */
3779#define WM8995_GP14_DB_SHIFT 8 /* GP14_DB */
3780#define WM8995_GP14_DB_WIDTH 1 /* GP14_DB */
3781#define WM8995_GP14_LVL 0x0040 /* GP14_LVL */
3782#define WM8995_GP14_LVL_MASK 0x0040 /* GP14_LVL */
3783#define WM8995_GP14_LVL_SHIFT 6 /* GP14_LVL */
3784#define WM8995_GP14_LVL_WIDTH 1 /* GP14_LVL */
3785#define WM8995_GP14_FN_MASK 0x001F /* GP14_FN - [4:0] */
3786#define WM8995_GP14_FN_SHIFT 0 /* GP14_FN - [4:0] */
3787#define WM8995_GP14_FN_WIDTH 5 /* GP14_FN - [4:0] */
3788
3789/*
3790 * R1824 (0x720) - Pull Control (1)
3791 */
3792#define WM8995_DMICDAT3_PD 0x4000 /* DMICDAT3_PD */
3793#define WM8995_DMICDAT3_PD_MASK 0x4000 /* DMICDAT3_PD */
3794#define WM8995_DMICDAT3_PD_SHIFT 14 /* DMICDAT3_PD */
3795#define WM8995_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */
3796#define WM8995_DMICDAT2_PD 0x1000 /* DMICDAT2_PD */
3797#define WM8995_DMICDAT2_PD_MASK 0x1000 /* DMICDAT2_PD */
3798#define WM8995_DMICDAT2_PD_SHIFT 12 /* DMICDAT2_PD */
3799#define WM8995_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
3800#define WM8995_DMICDAT1_PD 0x0400 /* DMICDAT1_PD */
3801#define WM8995_DMICDAT1_PD_MASK 0x0400 /* DMICDAT1_PD */
3802#define WM8995_DMICDAT1_PD_SHIFT 10 /* DMICDAT1_PD */
3803#define WM8995_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
3804#define WM8995_MCLK2_PU 0x0200 /* MCLK2_PU */
3805#define WM8995_MCLK2_PU_MASK 0x0200 /* MCLK2_PU */
3806#define WM8995_MCLK2_PU_SHIFT 9 /* MCLK2_PU */
3807#define WM8995_MCLK2_PU_WIDTH 1 /* MCLK2_PU */
3808#define WM8995_MCLK2_PD 0x0100 /* MCLK2_PD */
3809#define WM8995_MCLK2_PD_MASK 0x0100 /* MCLK2_PD */
3810#define WM8995_MCLK2_PD_SHIFT 8 /* MCLK2_PD */
3811#define WM8995_MCLK2_PD_WIDTH 1 /* MCLK2_PD */
3812#define WM8995_MCLK1_PU 0x0080 /* MCLK1_PU */
3813#define WM8995_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */
3814#define WM8995_MCLK1_PU_SHIFT 7 /* MCLK1_PU */
3815#define WM8995_MCLK1_PU_WIDTH 1 /* MCLK1_PU */
3816#define WM8995_MCLK1_PD 0x0040 /* MCLK1_PD */
3817#define WM8995_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */
3818#define WM8995_MCLK1_PD_SHIFT 6 /* MCLK1_PD */
3819#define WM8995_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
3820#define WM8995_DACDAT1_PU 0x0020 /* DACDAT1_PU */
3821#define WM8995_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */
3822#define WM8995_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */
3823#define WM8995_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */
3824#define WM8995_DACDAT1_PD 0x0010 /* DACDAT1_PD */
3825#define WM8995_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */
3826#define WM8995_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */
3827#define WM8995_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */
3828#define WM8995_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */
3829#define WM8995_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */
3830#define WM8995_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */
3831#define WM8995_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */
3832#define WM8995_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */
3833#define WM8995_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */
3834#define WM8995_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */
3835#define WM8995_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */
3836#define WM8995_BCLK1_PU 0x0002 /* BCLK1_PU */
3837#define WM8995_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */
3838#define WM8995_BCLK1_PU_SHIFT 1 /* BCLK1_PU */
3839#define WM8995_BCLK1_PU_WIDTH 1 /* BCLK1_PU */
3840#define WM8995_BCLK1_PD 0x0001 /* BCLK1_PD */
3841#define WM8995_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */
3842#define WM8995_BCLK1_PD_SHIFT 0 /* BCLK1_PD */
3843#define WM8995_BCLK1_PD_WIDTH 1 /* BCLK1_PD */
3844
3845/*
3846 * R1825 (0x721) - Pull Control (2)
3847 */
3848#define WM8995_LDO1ENA_PD 0x0010 /* LDO1ENA_PD */
3849#define WM8995_LDO1ENA_PD_MASK 0x0010 /* LDO1ENA_PD */
3850#define WM8995_LDO1ENA_PD_SHIFT 4 /* LDO1ENA_PD */
3851#define WM8995_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */
3852#define WM8995_MODE_PD 0x0004 /* MODE_PD */
3853#define WM8995_MODE_PD_MASK 0x0004 /* MODE_PD */
3854#define WM8995_MODE_PD_SHIFT 2 /* MODE_PD */
3855#define WM8995_MODE_PD_WIDTH 1 /* MODE_PD */
3856#define WM8995_CSNADDR_PD 0x0001 /* CSNADDR_PD */
3857#define WM8995_CSNADDR_PD_MASK 0x0001 /* CSNADDR_PD */
3858#define WM8995_CSNADDR_PD_SHIFT 0 /* CSNADDR_PD */
3859#define WM8995_CSNADDR_PD_WIDTH 1 /* CSNADDR_PD */
3860
3861/*
3862 * R1840 (0x730) - Interrupt Status 1
3863 */
3864#define WM8995_GP14_EINT 0x2000 /* GP14_EINT */
3865#define WM8995_GP14_EINT_MASK 0x2000 /* GP14_EINT */
3866#define WM8995_GP14_EINT_SHIFT 13 /* GP14_EINT */
3867#define WM8995_GP14_EINT_WIDTH 1 /* GP14_EINT */
3868#define WM8995_GP13_EINT 0x1000 /* GP13_EINT */
3869#define WM8995_GP13_EINT_MASK 0x1000 /* GP13_EINT */
3870#define WM8995_GP13_EINT_SHIFT 12 /* GP13_EINT */
3871#define WM8995_GP13_EINT_WIDTH 1 /* GP13_EINT */
3872#define WM8995_GP12_EINT 0x0800 /* GP12_EINT */
3873#define WM8995_GP12_EINT_MASK 0x0800 /* GP12_EINT */
3874#define WM8995_GP12_EINT_SHIFT 11 /* GP12_EINT */
3875#define WM8995_GP12_EINT_WIDTH 1 /* GP12_EINT */
3876#define WM8995_GP11_EINT 0x0400 /* GP11_EINT */
3877#define WM8995_GP11_EINT_MASK 0x0400 /* GP11_EINT */
3878#define WM8995_GP11_EINT_SHIFT 10 /* GP11_EINT */
3879#define WM8995_GP11_EINT_WIDTH 1 /* GP11_EINT */
3880#define WM8995_GP10_EINT 0x0200 /* GP10_EINT */
3881#define WM8995_GP10_EINT_MASK 0x0200 /* GP10_EINT */
3882#define WM8995_GP10_EINT_SHIFT 9 /* GP10_EINT */
3883#define WM8995_GP10_EINT_WIDTH 1 /* GP10_EINT */
3884#define WM8995_GP9_EINT 0x0100 /* GP9_EINT */
3885#define WM8995_GP9_EINT_MASK 0x0100 /* GP9_EINT */
3886#define WM8995_GP9_EINT_SHIFT 8 /* GP9_EINT */
3887#define WM8995_GP9_EINT_WIDTH 1 /* GP9_EINT */
3888#define WM8995_GP8_EINT 0x0080 /* GP8_EINT */
3889#define WM8995_GP8_EINT_MASK 0x0080 /* GP8_EINT */
3890#define WM8995_GP8_EINT_SHIFT 7 /* GP8_EINT */
3891#define WM8995_GP8_EINT_WIDTH 1 /* GP8_EINT */
3892#define WM8995_GP7_EINT 0x0040 /* GP7_EINT */
3893#define WM8995_GP7_EINT_MASK 0x0040 /* GP7_EINT */
3894#define WM8995_GP7_EINT_SHIFT 6 /* GP7_EINT */
3895#define WM8995_GP7_EINT_WIDTH 1 /* GP7_EINT */
3896#define WM8995_GP6_EINT 0x0020 /* GP6_EINT */
3897#define WM8995_GP6_EINT_MASK 0x0020 /* GP6_EINT */
3898#define WM8995_GP6_EINT_SHIFT 5 /* GP6_EINT */
3899#define WM8995_GP6_EINT_WIDTH 1 /* GP6_EINT */
3900#define WM8995_GP5_EINT 0x0010 /* GP5_EINT */
3901#define WM8995_GP5_EINT_MASK 0x0010 /* GP5_EINT */
3902#define WM8995_GP5_EINT_SHIFT 4 /* GP5_EINT */
3903#define WM8995_GP5_EINT_WIDTH 1 /* GP5_EINT */
3904#define WM8995_GP4_EINT 0x0008 /* GP4_EINT */
3905#define WM8995_GP4_EINT_MASK 0x0008 /* GP4_EINT */
3906#define WM8995_GP4_EINT_SHIFT 3 /* GP4_EINT */
3907#define WM8995_GP4_EINT_WIDTH 1 /* GP4_EINT */
3908#define WM8995_GP3_EINT 0x0004 /* GP3_EINT */
3909#define WM8995_GP3_EINT_MASK 0x0004 /* GP3_EINT */
3910#define WM8995_GP3_EINT_SHIFT 2 /* GP3_EINT */
3911#define WM8995_GP3_EINT_WIDTH 1 /* GP3_EINT */
3912#define WM8995_GP2_EINT 0x0002 /* GP2_EINT */
3913#define WM8995_GP2_EINT_MASK 0x0002 /* GP2_EINT */
3914#define WM8995_GP2_EINT_SHIFT 1 /* GP2_EINT */
3915#define WM8995_GP2_EINT_WIDTH 1 /* GP2_EINT */
3916#define WM8995_GP1_EINT 0x0001 /* GP1_EINT */
3917#define WM8995_GP1_EINT_MASK 0x0001 /* GP1_EINT */
3918#define WM8995_GP1_EINT_SHIFT 0 /* GP1_EINT */
3919#define WM8995_GP1_EINT_WIDTH 1 /* GP1_EINT */
3920
3921/*
3922 * R1841 (0x731) - Interrupt Status 2
3923 */
3924#define WM8995_DCS_DONE_23_EINT 0x1000 /* DCS_DONE_23_EINT */
3925#define WM8995_DCS_DONE_23_EINT_MASK 0x1000 /* DCS_DONE_23_EINT */
3926#define WM8995_DCS_DONE_23_EINT_SHIFT 12 /* DCS_DONE_23_EINT */
3927#define WM8995_DCS_DONE_23_EINT_WIDTH 1 /* DCS_DONE_23_EINT */
3928#define WM8995_DCS_DONE_01_EINT 0x0800 /* DCS_DONE_01_EINT */
3929#define WM8995_DCS_DONE_01_EINT_MASK 0x0800 /* DCS_DONE_01_EINT */
3930#define WM8995_DCS_DONE_01_EINT_SHIFT 11 /* DCS_DONE_01_EINT */
3931#define WM8995_DCS_DONE_01_EINT_WIDTH 1 /* DCS_DONE_01_EINT */
3932#define WM8995_WSEQ_DONE_EINT 0x0400 /* WSEQ_DONE_EINT */
3933#define WM8995_WSEQ_DONE_EINT_MASK 0x0400 /* WSEQ_DONE_EINT */
3934#define WM8995_WSEQ_DONE_EINT_SHIFT 10 /* WSEQ_DONE_EINT */
3935#define WM8995_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */
3936#define WM8995_FIFOS_ERR_EINT 0x0200 /* FIFOS_ERR_EINT */
3937#define WM8995_FIFOS_ERR_EINT_MASK 0x0200 /* FIFOS_ERR_EINT */
3938#define WM8995_FIFOS_ERR_EINT_SHIFT 9 /* FIFOS_ERR_EINT */
3939#define WM8995_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */
3940#define WM8995_AIF2DRC_SIG_DET_EINT 0x0100 /* AIF2DRC_SIG_DET_EINT */
3941#define WM8995_AIF2DRC_SIG_DET_EINT_MASK 0x0100 /* AIF2DRC_SIG_DET_EINT */
3942#define WM8995_AIF2DRC_SIG_DET_EINT_SHIFT 8 /* AIF2DRC_SIG_DET_EINT */
3943#define WM8995_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* AIF2DRC_SIG_DET_EINT */
3944#define WM8995_AIF1DRC2_SIG_DET_EINT 0x0080 /* AIF1DRC2_SIG_DET_EINT */
3945#define WM8995_AIF1DRC2_SIG_DET_EINT_MASK 0x0080 /* AIF1DRC2_SIG_DET_EINT */
3946#define WM8995_AIF1DRC2_SIG_DET_EINT_SHIFT 7 /* AIF1DRC2_SIG_DET_EINT */
3947#define WM8995_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* AIF1DRC2_SIG_DET_EINT */
3948#define WM8995_AIF1DRC1_SIG_DET_EINT 0x0040 /* AIF1DRC1_SIG_DET_EINT */
3949#define WM8995_AIF1DRC1_SIG_DET_EINT_MASK 0x0040 /* AIF1DRC1_SIG_DET_EINT */
3950#define WM8995_AIF1DRC1_SIG_DET_EINT_SHIFT 6 /* AIF1DRC1_SIG_DET_EINT */
3951#define WM8995_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* AIF1DRC1_SIG_DET_EINT */
3952#define WM8995_SRC2_LOCK_EINT 0x0020 /* SRC2_LOCK_EINT */
3953#define WM8995_SRC2_LOCK_EINT_MASK 0x0020 /* SRC2_LOCK_EINT */
3954#define WM8995_SRC2_LOCK_EINT_SHIFT 5 /* SRC2_LOCK_EINT */
3955#define WM8995_SRC2_LOCK_EINT_WIDTH 1 /* SRC2_LOCK_EINT */
3956#define WM8995_SRC1_LOCK_EINT 0x0010 /* SRC1_LOCK_EINT */
3957#define WM8995_SRC1_LOCK_EINT_MASK 0x0010 /* SRC1_LOCK_EINT */
3958#define WM8995_SRC1_LOCK_EINT_SHIFT 4 /* SRC1_LOCK_EINT */
3959#define WM8995_SRC1_LOCK_EINT_WIDTH 1 /* SRC1_LOCK_EINT */
3960#define WM8995_FLL2_LOCK_EINT 0x0008 /* FLL2_LOCK_EINT */
3961#define WM8995_FLL2_LOCK_EINT_MASK 0x0008 /* FLL2_LOCK_EINT */
3962#define WM8995_FLL2_LOCK_EINT_SHIFT 3 /* FLL2_LOCK_EINT */
3963#define WM8995_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */
3964#define WM8995_FLL1_LOCK_EINT 0x0004 /* FLL1_LOCK_EINT */
3965#define WM8995_FLL1_LOCK_EINT_MASK 0x0004 /* FLL1_LOCK_EINT */
3966#define WM8995_FLL1_LOCK_EINT_SHIFT 2 /* FLL1_LOCK_EINT */
3967#define WM8995_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */
3968#define WM8995_HP_DONE_EINT 0x0002 /* HP_DONE_EINT */
3969#define WM8995_HP_DONE_EINT_MASK 0x0002 /* HP_DONE_EINT */
3970#define WM8995_HP_DONE_EINT_SHIFT 1 /* HP_DONE_EINT */
3971#define WM8995_HP_DONE_EINT_WIDTH 1 /* HP_DONE_EINT */
3972#define WM8995_MICD_EINT 0x0001 /* MICD_EINT */
3973#define WM8995_MICD_EINT_MASK 0x0001 /* MICD_EINT */
3974#define WM8995_MICD_EINT_SHIFT 0 /* MICD_EINT */
3975#define WM8995_MICD_EINT_WIDTH 1 /* MICD_EINT */
3976
3977/*
3978 * R1842 (0x732) - Interrupt Raw Status 2
3979 */
3980#define WM8995_DCS_DONE_23_STS 0x1000 /* DCS_DONE_23_STS */
3981#define WM8995_DCS_DONE_23_STS_MASK 0x1000 /* DCS_DONE_23_STS */
3982#define WM8995_DCS_DONE_23_STS_SHIFT 12 /* DCS_DONE_23_STS */
3983#define WM8995_DCS_DONE_23_STS_WIDTH 1 /* DCS_DONE_23_STS */
3984#define WM8995_DCS_DONE_01_STS 0x0800 /* DCS_DONE_01_STS */
3985#define WM8995_DCS_DONE_01_STS_MASK 0x0800 /* DCS_DONE_01_STS */
3986#define WM8995_DCS_DONE_01_STS_SHIFT 11 /* DCS_DONE_01_STS */
3987#define WM8995_DCS_DONE_01_STS_WIDTH 1 /* DCS_DONE_01_STS */
3988#define WM8995_WSEQ_DONE_STS 0x0400 /* WSEQ_DONE_STS */
3989#define WM8995_WSEQ_DONE_STS_MASK 0x0400 /* WSEQ_DONE_STS */
3990#define WM8995_WSEQ_DONE_STS_SHIFT 10 /* WSEQ_DONE_STS */
3991#define WM8995_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */
3992#define WM8995_FIFOS_ERR_STS 0x0200 /* FIFOS_ERR_STS */
3993#define WM8995_FIFOS_ERR_STS_MASK 0x0200 /* FIFOS_ERR_STS */
3994#define WM8995_FIFOS_ERR_STS_SHIFT 9 /* FIFOS_ERR_STS */
3995#define WM8995_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */
3996#define WM8995_AIF2DRC_SIG_DET_STS 0x0100 /* AIF2DRC_SIG_DET_STS */
3997#define WM8995_AIF2DRC_SIG_DET_STS_MASK 0x0100 /* AIF2DRC_SIG_DET_STS */
3998#define WM8995_AIF2DRC_SIG_DET_STS_SHIFT 8 /* AIF2DRC_SIG_DET_STS */
3999#define WM8995_AIF2DRC_SIG_DET_STS_WIDTH 1 /* AIF2DRC_SIG_DET_STS */
4000#define WM8995_AIF1DRC2_SIG_DET_STS 0x0080 /* AIF1DRC2_SIG_DET_STS */
4001#define WM8995_AIF1DRC2_SIG_DET_STS_MASK 0x0080 /* AIF1DRC2_SIG_DET_STS */
4002#define WM8995_AIF1DRC2_SIG_DET_STS_SHIFT 7 /* AIF1DRC2_SIG_DET_STS */
4003#define WM8995_AIF1DRC2_SIG_DET_STS_WIDTH 1 /* AIF1DRC2_SIG_DET_STS */
4004#define WM8995_AIF1DRC1_SIG_DET_STS 0x0040 /* AIF1DRC1_SIG_DET_STS */
4005#define WM8995_AIF1DRC1_SIG_DET_STS_MASK 0x0040 /* AIF1DRC1_SIG_DET_STS */
4006#define WM8995_AIF1DRC1_SIG_DET_STS_SHIFT 6 /* AIF1DRC1_SIG_DET_STS */
4007#define WM8995_AIF1DRC1_SIG_DET_STS_WIDTH 1 /* AIF1DRC1_SIG_DET_STS */
4008#define WM8995_SRC2_LOCK_STS 0x0020 /* SRC2_LOCK_STS */
4009#define WM8995_SRC2_LOCK_STS_MASK 0x0020 /* SRC2_LOCK_STS */
4010#define WM8995_SRC2_LOCK_STS_SHIFT 5 /* SRC2_LOCK_STS */
4011#define WM8995_SRC2_LOCK_STS_WIDTH 1 /* SRC2_LOCK_STS */
4012#define WM8995_SRC1_LOCK_STS 0x0010 /* SRC1_LOCK_STS */
4013#define WM8995_SRC1_LOCK_STS_MASK 0x0010 /* SRC1_LOCK_STS */
4014#define WM8995_SRC1_LOCK_STS_SHIFT 4 /* SRC1_LOCK_STS */
4015#define WM8995_SRC1_LOCK_STS_WIDTH 1 /* SRC1_LOCK_STS */
4016#define WM8995_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */
4017#define WM8995_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */
4018#define WM8995_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */
4019#define WM8995_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */
4020#define WM8995_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */
4021#define WM8995_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */
4022#define WM8995_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */
4023#define WM8995_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */
4024
4025/*
4026 * R1848 (0x738) - Interrupt Status 1 Mask
4027 */
4028#define WM8995_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */
4029#define WM8995_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */
4030#define WM8995_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */
4031#define WM8995_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */
4032#define WM8995_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */
4033#define WM8995_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */
4034#define WM8995_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */
4035#define WM8995_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */
4036#define WM8995_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */
4037#define WM8995_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */
4038#define WM8995_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */
4039#define WM8995_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */
4040#define WM8995_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */
4041#define WM8995_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */
4042#define WM8995_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */
4043#define WM8995_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */
4044#define WM8995_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */
4045#define WM8995_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */
4046#define WM8995_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */
4047#define WM8995_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */
4048#define WM8995_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */
4049#define WM8995_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */
4050#define WM8995_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */
4051#define WM8995_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */
4052#define WM8995_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */
4053#define WM8995_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */
4054#define WM8995_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */
4055#define WM8995_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */
4056#define WM8995_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */
4057#define WM8995_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */
4058#define WM8995_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */
4059#define WM8995_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */
4060#define WM8995_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */
4061#define WM8995_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */
4062#define WM8995_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */
4063#define WM8995_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */
4064#define WM8995_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
4065#define WM8995_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
4066#define WM8995_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
4067#define WM8995_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
4068#define WM8995_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
4069#define WM8995_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
4070#define WM8995_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
4071#define WM8995_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
4072#define WM8995_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
4073#define WM8995_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
4074#define WM8995_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
4075#define WM8995_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
4076#define WM8995_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
4077#define WM8995_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
4078#define WM8995_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
4079#define WM8995_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
4080#define WM8995_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
4081#define WM8995_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
4082#define WM8995_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
4083#define WM8995_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
4084
4085/*
4086 * R1849 (0x739) - Interrupt Status 2 Mask
4087 */
4088#define WM8995_IM_DCS_DONE_23_EINT 0x1000 /* IM_DCS_DONE_23_EINT */
4089#define WM8995_IM_DCS_DONE_23_EINT_MASK 0x1000 /* IM_DCS_DONE_23_EINT */
4090#define WM8995_IM_DCS_DONE_23_EINT_SHIFT 12 /* IM_DCS_DONE_23_EINT */
4091#define WM8995_IM_DCS_DONE_23_EINT_WIDTH 1 /* IM_DCS_DONE_23_EINT */
4092#define WM8995_IM_DCS_DONE_01_EINT 0x0800 /* IM_DCS_DONE_01_EINT */
4093#define WM8995_IM_DCS_DONE_01_EINT_MASK 0x0800 /* IM_DCS_DONE_01_EINT */
4094#define WM8995_IM_DCS_DONE_01_EINT_SHIFT 11 /* IM_DCS_DONE_01_EINT */
4095#define WM8995_IM_DCS_DONE_01_EINT_WIDTH 1 /* IM_DCS_DONE_01_EINT */
4096#define WM8995_IM_WSEQ_DONE_EINT 0x0400 /* IM_WSEQ_DONE_EINT */
4097#define WM8995_IM_WSEQ_DONE_EINT_MASK 0x0400 /* IM_WSEQ_DONE_EINT */
4098#define WM8995_IM_WSEQ_DONE_EINT_SHIFT 10 /* IM_WSEQ_DONE_EINT */
4099#define WM8995_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */
4100#define WM8995_IM_FIFOS_ERR_EINT 0x0200 /* IM_FIFOS_ERR_EINT */
4101#define WM8995_IM_FIFOS_ERR_EINT_MASK 0x0200 /* IM_FIFOS_ERR_EINT */
4102#define WM8995_IM_FIFOS_ERR_EINT_SHIFT 9 /* IM_FIFOS_ERR_EINT */
4103#define WM8995_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */
4104#define WM8995_IM_AIF2DRC_SIG_DET_EINT 0x0100 /* IM_AIF2DRC_SIG_DET_EINT */
4105#define WM8995_IM_AIF2DRC_SIG_DET_EINT_MASK 0x0100 /* IM_AIF2DRC_SIG_DET_EINT */
4106#define WM8995_IM_AIF2DRC_SIG_DET_EINT_SHIFT 8 /* IM_AIF2DRC_SIG_DET_EINT */
4107#define WM8995_IM_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* IM_AIF2DRC_SIG_DET_EINT */
4108#define WM8995_IM_AIF1DRC2_SIG_DET_EINT 0x0080 /* IM_AIF1DRC2_SIG_DET_EINT */
4109#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_MASK 0x0080 /* IM_AIF1DRC2_SIG_DET_EINT */
4110#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_SHIFT 7 /* IM_AIF1DRC2_SIG_DET_EINT */
4111#define WM8995_IM_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC2_SIG_DET_EINT */
4112#define WM8995_IM_AIF1DRC1_SIG_DET_EINT 0x0040 /* IM_AIF1DRC1_SIG_DET_EINT */
4113#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_MASK 0x0040 /* IM_AIF1DRC1_SIG_DET_EINT */
4114#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_SHIFT 6 /* IM_AIF1DRC1_SIG_DET_EINT */
4115#define WM8995_IM_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC1_SIG_DET_EINT */
4116#define WM8995_IM_SRC2_LOCK_EINT 0x0020 /* IM_SRC2_LOCK_EINT */
4117#define WM8995_IM_SRC2_LOCK_EINT_MASK 0x0020 /* IM_SRC2_LOCK_EINT */
4118#define WM8995_IM_SRC2_LOCK_EINT_SHIFT 5 /* IM_SRC2_LOCK_EINT */
4119#define WM8995_IM_SRC2_LOCK_EINT_WIDTH 1 /* IM_SRC2_LOCK_EINT */
4120#define WM8995_IM_SRC1_LOCK_EINT 0x0010 /* IM_SRC1_LOCK_EINT */
4121#define WM8995_IM_SRC1_LOCK_EINT_MASK 0x0010 /* IM_SRC1_LOCK_EINT */
4122#define WM8995_IM_SRC1_LOCK_EINT_SHIFT 4 /* IM_SRC1_LOCK_EINT */
4123#define WM8995_IM_SRC1_LOCK_EINT_WIDTH 1 /* IM_SRC1_LOCK_EINT */
4124#define WM8995_IM_FLL2_LOCK_EINT 0x0008 /* IM_FLL2_LOCK_EINT */
4125#define WM8995_IM_FLL2_LOCK_EINT_MASK 0x0008 /* IM_FLL2_LOCK_EINT */
4126#define WM8995_IM_FLL2_LOCK_EINT_SHIFT 3 /* IM_FLL2_LOCK_EINT */
4127#define WM8995_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */
4128#define WM8995_IM_FLL1_LOCK_EINT 0x0004 /* IM_FLL1_LOCK_EINT */
4129#define WM8995_IM_FLL1_LOCK_EINT_MASK 0x0004 /* IM_FLL1_LOCK_EINT */
4130#define WM8995_IM_FLL1_LOCK_EINT_SHIFT 2 /* IM_FLL1_LOCK_EINT */
4131#define WM8995_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */
4132#define WM8995_IM_HP_DONE_EINT 0x0002 /* IM_HP_DONE_EINT */
4133#define WM8995_IM_HP_DONE_EINT_MASK 0x0002 /* IM_HP_DONE_EINT */
4134#define WM8995_IM_HP_DONE_EINT_SHIFT 1 /* IM_HP_DONE_EINT */
4135#define WM8995_IM_HP_DONE_EINT_WIDTH 1 /* IM_HP_DONE_EINT */
4136#define WM8995_IM_MICD_EINT 0x0001 /* IM_MICD_EINT */
4137#define WM8995_IM_MICD_EINT_MASK 0x0001 /* IM_MICD_EINT */
4138#define WM8995_IM_MICD_EINT_SHIFT 0 /* IM_MICD_EINT */
4139#define WM8995_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */
4140
4141/*
4142 * R1856 (0x740) - Interrupt Control
4143 */
4144#define WM8995_IM_IRQ 0x0001 /* IM_IRQ */
4145#define WM8995_IM_IRQ_MASK 0x0001 /* IM_IRQ */
4146#define WM8995_IM_IRQ_SHIFT 0 /* IM_IRQ */
4147#define WM8995_IM_IRQ_WIDTH 1 /* IM_IRQ */
4148
4149/*
4150 * R2048 (0x800) - Left PDM Speaker 1
4151 */
4152#define WM8995_SPK1L_ENA 0x0010 /* SPK1L_ENA */
4153#define WM8995_SPK1L_ENA_MASK 0x0010 /* SPK1L_ENA */
4154#define WM8995_SPK1L_ENA_SHIFT 4 /* SPK1L_ENA */
4155#define WM8995_SPK1L_ENA_WIDTH 1 /* SPK1L_ENA */
4156#define WM8995_SPK1L_MUTE 0x0008 /* SPK1L_MUTE */
4157#define WM8995_SPK1L_MUTE_MASK 0x0008 /* SPK1L_MUTE */
4158#define WM8995_SPK1L_MUTE_SHIFT 3 /* SPK1L_MUTE */
4159#define WM8995_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */
4160#define WM8995_SPK1L_MUTE_ZC 0x0004 /* SPK1L_MUTE_ZC */
4161#define WM8995_SPK1L_MUTE_ZC_MASK 0x0004 /* SPK1L_MUTE_ZC */
4162#define WM8995_SPK1L_MUTE_ZC_SHIFT 2 /* SPK1L_MUTE_ZC */
4163#define WM8995_SPK1L_MUTE_ZC_WIDTH 1 /* SPK1L_MUTE_ZC */
4164#define WM8995_SPK1L_SRC_MASK 0x0003 /* SPK1L_SRC - [1:0] */
4165#define WM8995_SPK1L_SRC_SHIFT 0 /* SPK1L_SRC - [1:0] */
4166#define WM8995_SPK1L_SRC_WIDTH 2 /* SPK1L_SRC - [1:0] */
4167
4168/*
4169 * R2049 (0x801) - Right PDM Speaker 1
4170 */
4171#define WM8995_SPK1R_ENA 0x0010 /* SPK1R_ENA */
4172#define WM8995_SPK1R_ENA_MASK 0x0010 /* SPK1R_ENA */
4173#define WM8995_SPK1R_ENA_SHIFT 4 /* SPK1R_ENA */
4174#define WM8995_SPK1R_ENA_WIDTH 1 /* SPK1R_ENA */
4175#define WM8995_SPK1R_MUTE 0x0008 /* SPK1R_MUTE */
4176#define WM8995_SPK1R_MUTE_MASK 0x0008 /* SPK1R_MUTE */
4177#define WM8995_SPK1R_MUTE_SHIFT 3 /* SPK1R_MUTE */
4178#define WM8995_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */
4179#define WM8995_SPK1R_MUTE_ZC 0x0004 /* SPK1R_MUTE_ZC */
4180#define WM8995_SPK1R_MUTE_ZC_MASK 0x0004 /* SPK1R_MUTE_ZC */
4181#define WM8995_SPK1R_MUTE_ZC_SHIFT 2 /* SPK1R_MUTE_ZC */
4182#define WM8995_SPK1R_MUTE_ZC_WIDTH 1 /* SPK1R_MUTE_ZC */
4183#define WM8995_SPK1R_SRC_MASK 0x0003 /* SPK1R_SRC - [1:0] */
4184#define WM8995_SPK1R_SRC_SHIFT 0 /* SPK1R_SRC - [1:0] */
4185#define WM8995_SPK1R_SRC_WIDTH 2 /* SPK1R_SRC - [1:0] */
4186
4187/*
4188 * R2050 (0x802) - PDM Speaker 1 Mute Sequence
4189 */
4190#define WM8995_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */
4191#define WM8995_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */
4192#define WM8995_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */
4193
4194/*
4195 * R2056 (0x808) - Left PDM Speaker 2
4196 */
4197#define WM8995_SPK2L_ENA 0x0010 /* SPK2L_ENA */
4198#define WM8995_SPK2L_ENA_MASK 0x0010 /* SPK2L_ENA */
4199#define WM8995_SPK2L_ENA_SHIFT 4 /* SPK2L_ENA */
4200#define WM8995_SPK2L_ENA_WIDTH 1 /* SPK2L_ENA */
4201#define WM8995_SPK2L_MUTE 0x0008 /* SPK2L_MUTE */
4202#define WM8995_SPK2L_MUTE_MASK 0x0008 /* SPK2L_MUTE */
4203#define WM8995_SPK2L_MUTE_SHIFT 3 /* SPK2L_MUTE */
4204#define WM8995_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */
4205#define WM8995_SPK2L_MUTE_ZC 0x0004 /* SPK2L_MUTE_ZC */
4206#define WM8995_SPK2L_MUTE_ZC_MASK 0x0004 /* SPK2L_MUTE_ZC */
4207#define WM8995_SPK2L_MUTE_ZC_SHIFT 2 /* SPK2L_MUTE_ZC */
4208#define WM8995_SPK2L_MUTE_ZC_WIDTH 1 /* SPK2L_MUTE_ZC */
4209#define WM8995_SPK2L_SRC_MASK 0x0003 /* SPK2L_SRC - [1:0] */
4210#define WM8995_SPK2L_SRC_SHIFT 0 /* SPK2L_SRC - [1:0] */
4211#define WM8995_SPK2L_SRC_WIDTH 2 /* SPK2L_SRC - [1:0] */
4212
4213/*
4214 * R2057 (0x809) - Right PDM Speaker 2
4215 */
4216#define WM8995_SPK2R_ENA 0x0010 /* SPK2R_ENA */
4217#define WM8995_SPK2R_ENA_MASK 0x0010 /* SPK2R_ENA */
4218#define WM8995_SPK2R_ENA_SHIFT 4 /* SPK2R_ENA */
4219#define WM8995_SPK2R_ENA_WIDTH 1 /* SPK2R_ENA */
4220#define WM8995_SPK2R_MUTE 0x0008 /* SPK2R_MUTE */
4221#define WM8995_SPK2R_MUTE_MASK 0x0008 /* SPK2R_MUTE */
4222#define WM8995_SPK2R_MUTE_SHIFT 3 /* SPK2R_MUTE */
4223#define WM8995_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */
4224#define WM8995_SPK2R_MUTE_ZC 0x0004 /* SPK2R_MUTE_ZC */
4225#define WM8995_SPK2R_MUTE_ZC_MASK 0x0004 /* SPK2R_MUTE_ZC */
4226#define WM8995_SPK2R_MUTE_ZC_SHIFT 2 /* SPK2R_MUTE_ZC */
4227#define WM8995_SPK2R_MUTE_ZC_WIDTH 1 /* SPK2R_MUTE_ZC */
4228#define WM8995_SPK2R_SRC_MASK 0x0003 /* SPK2R_SRC - [1:0] */
4229#define WM8995_SPK2R_SRC_SHIFT 0 /* SPK2R_SRC - [1:0] */
4230#define WM8995_SPK2R_SRC_WIDTH 2 /* SPK2R_SRC - [1:0] */
4231
4232/*
4233 * R2058 (0x80A) - PDM Speaker 2 Mute Sequence
4234 */
4235#define WM8995_SPK2_MUTE_SEQ1_MASK 0x00FF /* SPK2_MUTE_SEQ1 - [7:0] */
4236#define WM8995_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */
4237#define WM8995_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */
4238
4239#define WM8995_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
4240{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
4241 .info = snd_soc_info_volsw, \
4242 .get = snd_soc_dapm_get_volsw, .put = wm8995_put_class_w, \
4243 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) \
4244}
4245
4246struct wm8995_reg_access {
4247 u16 read;
4248 u16 write;
4249 u16 vol;
4250};
4251
4252/* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */
4253enum clk_src {
4254 WM8995_SYSCLK_MCLK1 = 1,
4255 WM8995_SYSCLK_MCLK2,
4256 WM8995_SYSCLK_FLL1,
4257 WM8995_SYSCLK_FLL2,
4258 WM8995_SYSCLK_OPCLK
4259};
4260
4261#define WM8995_FLL1 1
4262#define WM8995_FLL2 2
4263
4264#define WM8995_FLL_SRC_MCLK1 1
4265#define WM8995_FLL_SRC_MCLK2 2
4266#define WM8995_FLL_SRC_LRCLK 3
4267#define WM8995_FLL_SRC_BCLK 4
4268
4269#endif /* _WM8995_H */
diff --git a/sound/soc/codecs/wm9081.c b/sound/soc/codecs/wm9081.c
index a486670966bd..43825b2102a5 100644
--- a/sound/soc/codecs/wm9081.c
+++ b/sound/soc/codecs/wm9081.c
@@ -23,7 +23,6 @@
23#include <sound/pcm.h> 23#include <sound/pcm.h>
24#include <sound/pcm_params.h> 24#include <sound/pcm_params.h>
25#include <sound/soc.h> 25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h> 26#include <sound/initval.h>
28#include <sound/tlv.h> 27#include <sound/tlv.h>
29 28
@@ -158,7 +157,6 @@ static struct {
158struct wm9081_priv { 157struct wm9081_priv {
159 enum snd_soc_control_type control_type; 158 enum snd_soc_control_type control_type;
160 void *control_data; 159 void *control_data;
161 u16 reg_cache[WM9081_MAX_REGISTER + 1];
162 int sysclk_source; 160 int sysclk_source;
163 int mclk_rate; 161 int mclk_rate;
164 int sysclk_rate; 162 int sysclk_rate;
@@ -591,6 +589,10 @@ static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
591 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT; 589 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
592 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5); 590 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
593 591
592 /* Set gain to the recommended value */
593 snd_soc_update_bits(codec, WM9081_FLL_CONTROL_4,
594 WM9081_FLL_GAIN_MASK, 0);
595
594 /* Enable the FLL */ 596 /* Enable the FLL */
595 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA); 597 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
596 598
@@ -805,7 +807,7 @@ static int wm9081_set_bias_level(struct snd_soc_codec *codec,
805 807
806 case SND_SOC_BIAS_STANDBY: 808 case SND_SOC_BIAS_STANDBY:
807 /* Initial cold start */ 809 /* Initial cold start */
808 if (codec->bias_level == SND_SOC_BIAS_OFF) { 810 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
809 /* Disable LINEOUT discharge */ 811 /* Disable LINEOUT discharge */
810 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL); 812 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
811 reg &= ~WM9081_LINEOUT_DISCH; 813 reg &= ~WM9081_LINEOUT_DISCH;
@@ -865,7 +867,7 @@ static int wm9081_set_bias_level(struct snd_soc_codec *codec,
865 break; 867 break;
866 } 868 }
867 869
868 codec->bias_level = level; 870 codec->dapm.bias_level = level;
869 871
870 return 0; 872 return 0;
871} 873}
@@ -1228,6 +1230,7 @@ static struct snd_soc_dai_driver wm9081_dai = {
1228static int wm9081_probe(struct snd_soc_codec *codec) 1230static int wm9081_probe(struct snd_soc_codec *codec)
1229{ 1231{
1230 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec); 1232 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1233 struct snd_soc_dapm_context *dapm = &codec->dapm;
1231 int ret; 1234 int ret;
1232 u16 reg; 1235 u16 reg;
1233 1236
@@ -1269,9 +1272,9 @@ static int wm9081_probe(struct snd_soc_codec *codec)
1269 ARRAY_SIZE(wm9081_eq_controls)); 1272 ARRAY_SIZE(wm9081_eq_controls));
1270 } 1273 }
1271 1274
1272 snd_soc_dapm_new_controls(codec, wm9081_dapm_widgets, 1275 snd_soc_dapm_new_controls(dapm, wm9081_dapm_widgets,
1273 ARRAY_SIZE(wm9081_dapm_widgets)); 1276 ARRAY_SIZE(wm9081_dapm_widgets));
1274 snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths)); 1277 snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
1275 1278
1276 return ret; 1279 return ret;
1277} 1280}
diff --git a/sound/soc/codecs/wm9090.c b/sound/soc/codecs/wm9090.c
index 6e5f64f627cb..a788c4297046 100644
--- a/sound/soc/codecs/wm9090.c
+++ b/sound/soc/codecs/wm9090.c
@@ -28,7 +28,6 @@
28#include <linux/slab.h> 28#include <linux/slab.h>
29#include <sound/initval.h> 29#include <sound/initval.h>
30#include <sound/soc.h> 30#include <sound/soc.h>
31#include <sound/soc-dapm.h>
32#include <sound/tlv.h> 31#include <sound/tlv.h>
33#include <sound/wm9090.h> 32#include <sound/wm9090.h>
34 33
@@ -442,31 +441,32 @@ static const struct snd_soc_dapm_route audio_map_in2_diff[] = {
442static int wm9090_add_controls(struct snd_soc_codec *codec) 441static int wm9090_add_controls(struct snd_soc_codec *codec)
443{ 442{
444 struct wm9090_priv *wm9090 = snd_soc_codec_get_drvdata(codec); 443 struct wm9090_priv *wm9090 = snd_soc_codec_get_drvdata(codec);
444 struct snd_soc_dapm_context *dapm = &codec->dapm;
445 int i; 445 int i;
446 446
447 snd_soc_dapm_new_controls(codec, wm9090_dapm_widgets, 447 snd_soc_dapm_new_controls(dapm, wm9090_dapm_widgets,
448 ARRAY_SIZE(wm9090_dapm_widgets)); 448 ARRAY_SIZE(wm9090_dapm_widgets));
449 449
450 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 450 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
451 451
452 snd_soc_add_controls(codec, wm9090_controls, 452 snd_soc_add_controls(codec, wm9090_controls,
453 ARRAY_SIZE(wm9090_controls)); 453 ARRAY_SIZE(wm9090_controls));
454 454
455 if (wm9090->pdata.lin1_diff) { 455 if (wm9090->pdata.lin1_diff) {
456 snd_soc_dapm_add_routes(codec, audio_map_in1_diff, 456 snd_soc_dapm_add_routes(dapm, audio_map_in1_diff,
457 ARRAY_SIZE(audio_map_in1_diff)); 457 ARRAY_SIZE(audio_map_in1_diff));
458 } else { 458 } else {
459 snd_soc_dapm_add_routes(codec, audio_map_in1_se, 459 snd_soc_dapm_add_routes(dapm, audio_map_in1_se,
460 ARRAY_SIZE(audio_map_in1_se)); 460 ARRAY_SIZE(audio_map_in1_se));
461 snd_soc_add_controls(codec, wm9090_in1_se_controls, 461 snd_soc_add_controls(codec, wm9090_in1_se_controls,
462 ARRAY_SIZE(wm9090_in1_se_controls)); 462 ARRAY_SIZE(wm9090_in1_se_controls));
463 } 463 }
464 464
465 if (wm9090->pdata.lin2_diff) { 465 if (wm9090->pdata.lin2_diff) {
466 snd_soc_dapm_add_routes(codec, audio_map_in2_diff, 466 snd_soc_dapm_add_routes(dapm, audio_map_in2_diff,
467 ARRAY_SIZE(audio_map_in2_diff)); 467 ARRAY_SIZE(audio_map_in2_diff));
468 } else { 468 } else {
469 snd_soc_dapm_add_routes(codec, audio_map_in2_se, 469 snd_soc_dapm_add_routes(dapm, audio_map_in2_se,
470 ARRAY_SIZE(audio_map_in2_se)); 470 ARRAY_SIZE(audio_map_in2_se));
471 snd_soc_add_controls(codec, wm9090_in2_se_controls, 471 snd_soc_add_controls(codec, wm9090_in2_se_controls,
472 ARRAY_SIZE(wm9090_in2_se_controls)); 472 ARRAY_SIZE(wm9090_in2_se_controls));
@@ -513,7 +513,7 @@ static int wm9090_set_bias_level(struct snd_soc_codec *codec,
513 break; 513 break;
514 514
515 case SND_SOC_BIAS_STANDBY: 515 case SND_SOC_BIAS_STANDBY:
516 if (codec->bias_level == SND_SOC_BIAS_OFF) { 516 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
517 /* Restore the register cache */ 517 /* Restore the register cache */
518 for (i = 1; i < codec->driver->reg_cache_size; i++) { 518 for (i = 1; i < codec->driver->reg_cache_size; i++) {
519 if (reg_cache[i] == wm9090_reg_defaults[i]) 519 if (reg_cache[i] == wm9090_reg_defaults[i])
@@ -543,7 +543,7 @@ static int wm9090_set_bias_level(struct snd_soc_codec *codec,
543 break; 543 break;
544 } 544 }
545 545
546 codec->bias_level = level; 546 codec->dapm.bias_level = level;
547 547
548 return 0; 548 return 0;
549} 549}
diff --git a/sound/soc/codecs/wm9705.c b/sound/soc/codecs/wm9705.c
index a144acda751c..47b357adabdd 100644
--- a/sound/soc/codecs/wm9705.c
+++ b/sound/soc/codecs/wm9705.c
@@ -19,7 +19,6 @@
19#include <sound/ac97_codec.h> 19#include <sound/ac97_codec.h>
20#include <sound/initval.h> 20#include <sound/initval.h>
21#include <sound/soc.h> 21#include <sound/soc.h>
22#include <sound/soc-dapm.h>
23 22
24#include "wm9705.h" 23#include "wm9705.h"
25 24
@@ -203,9 +202,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
203 202
204static int wm9705_add_widgets(struct snd_soc_codec *codec) 203static int wm9705_add_widgets(struct snd_soc_codec *codec)
205{ 204{
206 snd_soc_dapm_new_controls(codec, wm9705_dapm_widgets, 205 struct snd_soc_dapm_context *dapm = &codec->dapm;
206
207 snd_soc_dapm_new_controls(dapm, wm9705_dapm_widgets,
207 ARRAY_SIZE(wm9705_dapm_widgets)); 208 ARRAY_SIZE(wm9705_dapm_widgets));
208 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 209 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
209 210
210 return 0; 211 return 0;
211} 212}
diff --git a/sound/soc/codecs/wm9712.c b/sound/soc/codecs/wm9712.c
index d2f224d62744..bf5d4ef1a2a6 100644
--- a/sound/soc/codecs/wm9712.c
+++ b/sound/soc/codecs/wm9712.c
@@ -20,7 +20,6 @@
20#include <sound/ac97_codec.h> 20#include <sound/ac97_codec.h>
21#include <sound/initval.h> 21#include <sound/initval.h>
22#include <sound/soc.h> 22#include <sound/soc.h>
23#include <sound/soc-dapm.h>
24#include "wm9712.h" 23#include "wm9712.h"
25 24
26#define WM9712_VERSION "0.4" 25#define WM9712_VERSION "0.4"
@@ -432,10 +431,11 @@ static const struct snd_soc_dapm_route audio_map[] = {
432 431
433static int wm9712_add_widgets(struct snd_soc_codec *codec) 432static int wm9712_add_widgets(struct snd_soc_codec *codec)
434{ 433{
435 snd_soc_dapm_new_controls(codec, wm9712_dapm_widgets, 434 struct snd_soc_dapm_context *dapm = &codec->dapm;
436 ARRAY_SIZE(wm9712_dapm_widgets));
437 435
438 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 436 snd_soc_dapm_new_controls(dapm, wm9712_dapm_widgets,
437 ARRAY_SIZE(wm9712_dapm_widgets));
438 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
439 439
440 return 0; 440 return 0;
441} 441}
@@ -570,7 +570,7 @@ static int wm9712_set_bias_level(struct snd_soc_codec *codec,
570 ac97_write(codec, AC97_POWERDOWN, 0xffff); 570 ac97_write(codec, AC97_POWERDOWN, 0xffff);
571 break; 571 break;
572 } 572 }
573 codec->bias_level = level; 573 codec->dapm.bias_level = level;
574 return 0; 574 return 0;
575} 575}
576 576
diff --git a/sound/soc/codecs/wm9713.c b/sound/soc/codecs/wm9713.c
index 7da13b07a53d..38ed98558718 100644
--- a/sound/soc/codecs/wm9713.c
+++ b/sound/soc/codecs/wm9713.c
@@ -26,7 +26,6 @@
26#include <sound/pcm_params.h> 26#include <sound/pcm_params.h>
27#include <sound/tlv.h> 27#include <sound/tlv.h>
28#include <sound/soc.h> 28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30 29
31#include "wm9713.h" 30#include "wm9713.h"
32 31
@@ -647,10 +646,12 @@ static const struct snd_soc_dapm_route audio_map[] = {
647 646
648static int wm9713_add_widgets(struct snd_soc_codec *codec) 647static int wm9713_add_widgets(struct snd_soc_codec *codec)
649{ 648{
650 snd_soc_dapm_new_controls(codec, wm9713_dapm_widgets, 649 struct snd_soc_dapm_context *dapm = &codec->dapm;
650
651 snd_soc_dapm_new_controls(dapm, wm9713_dapm_widgets,
651 ARRAY_SIZE(wm9713_dapm_widgets)); 652 ARRAY_SIZE(wm9713_dapm_widgets));
652 653
653 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); 654 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
654 655
655 return 0; 656 return 0;
656} 657}
@@ -1147,7 +1148,7 @@ static int wm9713_set_bias_level(struct snd_soc_codec *codec,
1147 ac97_write(codec, AC97_POWERDOWN, 0xffff); 1148 ac97_write(codec, AC97_POWERDOWN, 0xffff);
1148 break; 1149 break;
1149 } 1150 }
1150 codec->bias_level = level; 1151 codec->dapm.bias_level = level;
1151 return 0; 1152 return 0;
1152} 1153}
1153 1154
diff --git a/sound/soc/codecs/wm_hubs.c b/sound/soc/codecs/wm_hubs.c
index 0e24092722c3..c466982eed23 100644
--- a/sound/soc/codecs/wm_hubs.c
+++ b/sound/soc/codecs/wm_hubs.c
@@ -22,7 +22,6 @@
22#include <sound/pcm.h> 22#include <sound/pcm.h>
23#include <sound/pcm_params.h> 23#include <sound/pcm_params.h>
24#include <sound/soc.h> 24#include <sound/soc.h>
25#include <sound/soc-dapm.h>
26#include <sound/initval.h> 25#include <sound/initval.h>
27#include <sound/tlv.h> 26#include <sound/tlv.h>
28 27
@@ -94,41 +93,61 @@ static void calibrate_dc_servo(struct snd_soc_codec *codec)
94 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec); 93 struct wm_hubs_data *hubs = snd_soc_codec_get_drvdata(codec);
95 u16 reg, reg_l, reg_r, dcs_cfg; 94 u16 reg, reg_l, reg_r, dcs_cfg;
96 95
97 /* Set for 32 series updates */ 96 /* If we're using a digital only path and have a previously
98 snd_soc_update_bits(codec, WM8993_DC_SERVO_1, 97 * callibrated DC servo offset stored then use that. */
99 WM8993_DCS_SERIES_NO_01_MASK, 98 if (hubs->class_w && hubs->class_w_dcs) {
100 32 << WM8993_DCS_SERIES_NO_01_SHIFT); 99 dev_dbg(codec->dev, "Using cached DC servo offset %x\n",
101 wait_for_dc_servo(codec, 100 hubs->class_w_dcs);
102 WM8993_DCS_TRIG_SERIES_0 | WM8993_DCS_TRIG_SERIES_1); 101 snd_soc_write(codec, WM8993_DC_SERVO_3, hubs->class_w_dcs);
102 wait_for_dc_servo(codec,
103 WM8993_DCS_TRIG_DAC_WR_0 |
104 WM8993_DCS_TRIG_DAC_WR_1);
105 return;
106 }
107
108 /* Devices not using a DCS code correction have startup mode */
109 if (hubs->dcs_codes) {
110 /* Set for 32 series updates */
111 snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
112 WM8993_DCS_SERIES_NO_01_MASK,
113 32 << WM8993_DCS_SERIES_NO_01_SHIFT);
114 wait_for_dc_servo(codec,
115 WM8993_DCS_TRIG_SERIES_0 |
116 WM8993_DCS_TRIG_SERIES_1);
117 } else {
118 wait_for_dc_servo(codec,
119 WM8993_DCS_TRIG_STARTUP_0 |
120 WM8993_DCS_TRIG_STARTUP_1);
121 }
122
123 /* Different chips in the family support different readback
124 * methods.
125 */
126 switch (hubs->dcs_readback_mode) {
127 case 0:
128 reg_l = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_1)
129 & WM8993_DCS_INTEG_CHAN_0_MASK;
130 reg_r = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_2)
131 & WM8993_DCS_INTEG_CHAN_1_MASK;
132 break;
133 case 1:
134 reg = snd_soc_read(codec, WM8993_DC_SERVO_3);
135 reg_l = (reg & WM8993_DCS_DAC_WR_VAL_1_MASK)
136 >> WM8993_DCS_DAC_WR_VAL_1_SHIFT;
137 reg_r = reg & WM8993_DCS_DAC_WR_VAL_0_MASK;
138 break;
139 default:
140 WARN(1, "Unknown DCS readback method\n");
141 break;
142 }
143
144 dev_dbg(codec->dev, "DCS input: %x %x\n", reg_l, reg_r);
103 145
104 /* Apply correction to DC servo result */ 146 /* Apply correction to DC servo result */
105 if (hubs->dcs_codes) { 147 if (hubs->dcs_codes) {
106 dev_dbg(codec->dev, "Applying %d code DC servo correction\n", 148 dev_dbg(codec->dev, "Applying %d code DC servo correction\n",
107 hubs->dcs_codes); 149 hubs->dcs_codes);
108 150
109 /* Different chips in the family support different
110 * readback methods.
111 */
112 switch (hubs->dcs_readback_mode) {
113 case 0:
114 reg_l = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_1)
115 & WM8993_DCS_INTEG_CHAN_0_MASK;;
116 reg_r = snd_soc_read(codec, WM8993_DC_SERVO_READBACK_2)
117 & WM8993_DCS_INTEG_CHAN_1_MASK;
118 break;
119 case 1:
120 reg = snd_soc_read(codec, WM8993_DC_SERVO_3);
121 reg_l = (reg & WM8993_DCS_DAC_WR_VAL_1_MASK)
122 >> WM8993_DCS_DAC_WR_VAL_1_SHIFT;
123 reg_r = reg & WM8993_DCS_DAC_WR_VAL_0_MASK;
124 break;
125 default:
126 WARN(1, "Unknown DCS readback method\n");
127 break;
128 }
129
130 dev_dbg(codec->dev, "DCS input: %x %x\n", reg_l, reg_r);
131
132 /* HPOUT1L */ 151 /* HPOUT1L */
133 if (reg_l + hubs->dcs_codes > 0 && 152 if (reg_l + hubs->dcs_codes > 0 &&
134 reg_l + hubs->dcs_codes < 0xff) 153 reg_l + hubs->dcs_codes < 0xff)
@@ -148,7 +167,15 @@ static void calibrate_dc_servo(struct snd_soc_codec *codec)
148 wait_for_dc_servo(codec, 167 wait_for_dc_servo(codec,
149 WM8993_DCS_TRIG_DAC_WR_0 | 168 WM8993_DCS_TRIG_DAC_WR_0 |
150 WM8993_DCS_TRIG_DAC_WR_1); 169 WM8993_DCS_TRIG_DAC_WR_1);
170 } else {
171 dcs_cfg = reg_l << WM8993_DCS_DAC_WR_VAL_1_SHIFT;
172 dcs_cfg |= reg_r;
151 } 173 }
174
175 /* Save the callibrated offset if we're in class W mode and
176 * therefore don't have any analogue signal mixed in. */
177 if (hubs->class_w)
178 hubs->class_w_dcs = dcs_cfg;
152} 179}
153 180
154/* 181/*
@@ -163,6 +190,9 @@ static int wm8993_put_dc_servo(struct snd_kcontrol *kcontrol,
163 190
164 ret = snd_soc_put_volsw_2r(kcontrol, ucontrol); 191 ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
165 192
193 /* Updating the analogue gains invalidates the DC servo cache */
194 hubs->class_w_dcs = 0;
195
166 /* If we're applying an offset correction then updating the 196 /* If we're applying an offset correction then updating the
167 * callibration would be likely to introduce further offsets. */ 197 * callibration would be likely to introduce further offsets. */
168 if (hubs->dcs_codes) 198 if (hubs->dcs_codes)
@@ -791,6 +821,8 @@ static const struct snd_soc_dapm_route lineout2_se_routes[] = {
791 821
792int wm_hubs_add_analogue_controls(struct snd_soc_codec *codec) 822int wm_hubs_add_analogue_controls(struct snd_soc_codec *codec)
793{ 823{
824 struct snd_soc_dapm_context *dapm = &codec->dapm;
825
794 /* Latch volume update bits & default ZC on */ 826 /* Latch volume update bits & default ZC on */
795 snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_1_2_VOLUME, 827 snd_soc_update_bits(codec, WM8993_LEFT_LINE_INPUT_1_2_VOLUME,
796 WM8993_IN1_VU, WM8993_IN1_VU); 828 WM8993_IN1_VU, WM8993_IN1_VU);
@@ -819,7 +851,7 @@ int wm_hubs_add_analogue_controls(struct snd_soc_codec *codec)
819 snd_soc_add_controls(codec, analogue_snd_controls, 851 snd_soc_add_controls(codec, analogue_snd_controls,
820 ARRAY_SIZE(analogue_snd_controls)); 852 ARRAY_SIZE(analogue_snd_controls));
821 853
822 snd_soc_dapm_new_controls(codec, analogue_dapm_widgets, 854 snd_soc_dapm_new_controls(dapm, analogue_dapm_widgets,
823 ARRAY_SIZE(analogue_dapm_widgets)); 855 ARRAY_SIZE(analogue_dapm_widgets));
824 return 0; 856 return 0;
825} 857}
@@ -828,24 +860,26 @@ EXPORT_SYMBOL_GPL(wm_hubs_add_analogue_controls);
828int wm_hubs_add_analogue_routes(struct snd_soc_codec *codec, 860int wm_hubs_add_analogue_routes(struct snd_soc_codec *codec,
829 int lineout1_diff, int lineout2_diff) 861 int lineout1_diff, int lineout2_diff)
830{ 862{
831 snd_soc_dapm_add_routes(codec, analogue_routes, 863 struct snd_soc_dapm_context *dapm = &codec->dapm;
864
865 snd_soc_dapm_add_routes(dapm, analogue_routes,
832 ARRAY_SIZE(analogue_routes)); 866 ARRAY_SIZE(analogue_routes));
833 867
834 if (lineout1_diff) 868 if (lineout1_diff)
835 snd_soc_dapm_add_routes(codec, 869 snd_soc_dapm_add_routes(dapm,
836 lineout1_diff_routes, 870 lineout1_diff_routes,
837 ARRAY_SIZE(lineout1_diff_routes)); 871 ARRAY_SIZE(lineout1_diff_routes));
838 else 872 else
839 snd_soc_dapm_add_routes(codec, 873 snd_soc_dapm_add_routes(dapm,
840 lineout1_se_routes, 874 lineout1_se_routes,
841 ARRAY_SIZE(lineout1_se_routes)); 875 ARRAY_SIZE(lineout1_se_routes));
842 876
843 if (lineout2_diff) 877 if (lineout2_diff)
844 snd_soc_dapm_add_routes(codec, 878 snd_soc_dapm_add_routes(dapm,
845 lineout2_diff_routes, 879 lineout2_diff_routes,
846 ARRAY_SIZE(lineout2_diff_routes)); 880 ARRAY_SIZE(lineout2_diff_routes));
847 else 881 else
848 snd_soc_dapm_add_routes(codec, 882 snd_soc_dapm_add_routes(dapm,
849 lineout2_se_routes, 883 lineout2_se_routes,
850 ARRAY_SIZE(lineout2_se_routes)); 884 ARRAY_SIZE(lineout2_se_routes));
851 885
@@ -872,7 +906,7 @@ int wm_hubs_handle_analogue_pdata(struct snd_soc_codec *codec,
872 * VMID as an output and can disable it. 906 * VMID as an output and can disable it.
873 */ 907 */
874 if (lineout1_diff && lineout2_diff) 908 if (lineout1_diff && lineout2_diff)
875 codec->idle_bias_off = 1; 909 codec->dapm.idle_bias_off = 1;
876 910
877 if (lineout1fb) 911 if (lineout1fb)
878 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL, 912 snd_soc_update_bits(codec, WM8993_ADDITIONAL_CONTROL,
diff --git a/sound/soc/codecs/wm_hubs.h b/sound/soc/codecs/wm_hubs.h
index e51c16683589..f8a5e976b5e6 100644
--- a/sound/soc/codecs/wm_hubs.h
+++ b/sound/soc/codecs/wm_hubs.h
@@ -23,6 +23,9 @@ struct wm_hubs_data {
23 int dcs_codes; 23 int dcs_codes;
24 int dcs_readback_mode; 24 int dcs_readback_mode;
25 int hp_startup_mode; 25 int hp_startup_mode;
26
27 bool class_w;
28 u16 class_w_dcs;
26}; 29};
27 30
28extern int wm_hubs_add_analogue_controls(struct snd_soc_codec *); 31extern int wm_hubs_add_analogue_controls(struct snd_soc_codec *);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-08 21:15:32 -0400