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-rw-r--r--sound/soc/codecs/88pm860x-codec.c75
-rw-r--r--sound/soc/codecs/88pm860x-codec.h117
-rw-r--r--sound/soc/codecs/ab8500-codec.c92
-rw-r--r--sound/soc/codecs/adau1373.c298
-rw-r--r--sound/soc/codecs/adav80x.c147
-rw-r--r--sound/soc/codecs/ak4104.c11
-rw-r--r--sound/soc/codecs/ak4642.c4
-rw-r--r--sound/soc/codecs/arizona.c23
-rw-r--r--sound/soc/codecs/cq93vc.c46
-rw-r--r--sound/soc/codecs/cs4271.c1
-rw-r--r--sound/soc/codecs/cs42l52.c93
-rw-r--r--sound/soc/codecs/cs42l52.h2
-rw-r--r--sound/soc/codecs/cs42l73.c114
-rw-r--r--sound/soc/codecs/cs42l73.h105
-rw-r--r--sound/soc/codecs/max98088.c624
-rw-r--r--sound/soc/codecs/max98095.c466
-rw-r--r--sound/soc/codecs/max9850.c39
-rw-r--r--sound/soc/codecs/mc13783.c135
-rw-r--r--sound/soc/codecs/ml26124.c2
-rw-r--r--sound/soc/codecs/pcm1681.c2
-rw-r--r--sound/soc/codecs/pcm1792a.c2
-rw-r--r--sound/soc/codecs/tlv320aic3x.c4
-rw-r--r--sound/soc/codecs/wm5110.c12
-rw-r--r--sound/soc/codecs/wm_adsp.c32
-rw-r--r--sound/soc/codecs/wm_hubs.c1
25 files changed, 1274 insertions, 1173 deletions
diff --git a/sound/soc/codecs/88pm860x-codec.c b/sound/soc/codecs/88pm860x-codec.c
index 259d1ac4492f..75d0ad5d2dcb 100644
--- a/sound/soc/codecs/88pm860x-codec.c
+++ b/sound/soc/codecs/88pm860x-codec.c
@@ -16,6 +16,7 @@
16#include <linux/mfd/88pm860x.h> 16#include <linux/mfd/88pm860x.h>
17#include <linux/slab.h> 17#include <linux/slab.h>
18#include <linux/delay.h> 18#include <linux/delay.h>
19#include <linux/regmap.h>
19#include <sound/core.h> 20#include <sound/core.h>
20#include <sound/pcm.h> 21#include <sound/pcm.h>
21#include <sound/pcm_params.h> 22#include <sound/pcm_params.h>
@@ -140,6 +141,7 @@ struct pm860x_priv {
140 unsigned int filter; 141 unsigned int filter;
141 struct snd_soc_codec *codec; 142 struct snd_soc_codec *codec;
142 struct i2c_client *i2c; 143 struct i2c_client *i2c;
144 struct regmap *regmap;
143 struct pm860x_chip *chip; 145 struct pm860x_chip *chip;
144 struct pm860x_det det; 146 struct pm860x_det det;
145 147
@@ -269,48 +271,6 @@ static struct st_gain st_table[] = {
269 { -86, 29, 0}, { -56, 30, 0}, { -28, 31, 0}, { 0, 0, 0}, 271 { -86, 29, 0}, { -56, 30, 0}, { -28, 31, 0}, { 0, 0, 0},
270}; 272};
271 273
272static int pm860x_volatile(unsigned int reg)
273{
274 BUG_ON(reg >= REG_CACHE_SIZE);
275
276 switch (reg) {
277 case PM860X_AUDIO_SUPPLIES_2:
278 return 1;
279 }
280
281 return 0;
282}
283
284static unsigned int pm860x_read_reg_cache(struct snd_soc_codec *codec,
285 unsigned int reg)
286{
287 unsigned char *cache = codec->reg_cache;
288
289 BUG_ON(reg >= REG_CACHE_SIZE);
290
291 if (pm860x_volatile(reg))
292 return cache[reg];
293
294 reg += REG_CACHE_BASE;
295
296 return pm860x_reg_read(codec->control_data, reg);
297}
298
299static int pm860x_write_reg_cache(struct snd_soc_codec *codec,
300 unsigned int reg, unsigned int value)
301{
302 unsigned char *cache = codec->reg_cache;
303
304 BUG_ON(reg >= REG_CACHE_SIZE);
305
306 if (!pm860x_volatile(reg))
307 cache[reg] = (unsigned char)value;
308
309 reg += REG_CACHE_BASE;
310
311 return pm860x_reg_write(codec->control_data, reg, value);
312}
313
314static int snd_soc_get_volsw_2r_st(struct snd_kcontrol *kcontrol, 274static int snd_soc_get_volsw_2r_st(struct snd_kcontrol *kcontrol,
315 struct snd_ctl_elem_value *ucontrol) 275 struct snd_ctl_elem_value *ucontrol)
316{ 276{
@@ -1169,6 +1129,7 @@ static int pm860x_i2s_set_dai_fmt(struct snd_soc_dai *codec_dai,
1169static int pm860x_set_bias_level(struct snd_soc_codec *codec, 1129static int pm860x_set_bias_level(struct snd_soc_codec *codec,
1170 enum snd_soc_bias_level level) 1130 enum snd_soc_bias_level level)
1171{ 1131{
1132 struct pm860x_priv *pm860x = snd_soc_codec_get_drvdata(codec);
1172 int data; 1133 int data;
1173 1134
1174 switch (level) { 1135 switch (level) {
@@ -1182,17 +1143,17 @@ static int pm860x_set_bias_level(struct snd_soc_codec *codec,
1182 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1143 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1183 /* Enable Audio PLL & Audio section */ 1144 /* Enable Audio PLL & Audio section */
1184 data = AUDIO_PLL | AUDIO_SECTION_ON; 1145 data = AUDIO_PLL | AUDIO_SECTION_ON;
1185 pm860x_reg_write(codec->control_data, REG_MISC2, data); 1146 pm860x_reg_write(pm860x->i2c, REG_MISC2, data);
1186 udelay(300); 1147 udelay(300);
1187 data = AUDIO_PLL | AUDIO_SECTION_RESET 1148 data = AUDIO_PLL | AUDIO_SECTION_RESET
1188 | AUDIO_SECTION_ON; 1149 | AUDIO_SECTION_ON;
1189 pm860x_reg_write(codec->control_data, REG_MISC2, data); 1150 pm860x_reg_write(pm860x->i2c, REG_MISC2, data);
1190 } 1151 }
1191 break; 1152 break;
1192 1153
1193 case SND_SOC_BIAS_OFF: 1154 case SND_SOC_BIAS_OFF:
1194 data = AUDIO_PLL | AUDIO_SECTION_RESET | AUDIO_SECTION_ON; 1155 data = AUDIO_PLL | AUDIO_SECTION_RESET | AUDIO_SECTION_ON;
1195 pm860x_set_bits(codec->control_data, REG_MISC2, data, 0); 1156 pm860x_set_bits(pm860x->i2c, REG_MISC2, data, 0);
1196 break; 1157 break;
1197 } 1158 }
1198 codec->dapm.bias_level = level; 1159 codec->dapm.bias_level = level;
@@ -1322,17 +1283,17 @@ int pm860x_hs_jack_detect(struct snd_soc_codec *codec,
1322 pm860x->det.lo_shrt = lo_shrt; 1283 pm860x->det.lo_shrt = lo_shrt;
1323 1284
1324 if (det & SND_JACK_HEADPHONE) 1285 if (det & SND_JACK_HEADPHONE)
1325 pm860x_set_bits(codec->control_data, REG_HS_DET, 1286 pm860x_set_bits(pm860x->i2c, REG_HS_DET,
1326 EN_HS_DET, EN_HS_DET); 1287 EN_HS_DET, EN_HS_DET);
1327 /* headset short detect */ 1288 /* headset short detect */
1328 if (hs_shrt) { 1289 if (hs_shrt) {
1329 data = CLR_SHORT_HS2 | CLR_SHORT_HS1; 1290 data = CLR_SHORT_HS2 | CLR_SHORT_HS1;
1330 pm860x_set_bits(codec->control_data, REG_SHORTS, data, data); 1291 pm860x_set_bits(pm860x->i2c, REG_SHORTS, data, data);
1331 } 1292 }
1332 /* Lineout short detect */ 1293 /* Lineout short detect */
1333 if (lo_shrt) { 1294 if (lo_shrt) {
1334 data = CLR_SHORT_LO2 | CLR_SHORT_LO1; 1295 data = CLR_SHORT_LO2 | CLR_SHORT_LO1;
1335 pm860x_set_bits(codec->control_data, REG_SHORTS, data, data); 1296 pm860x_set_bits(pm860x->i2c, REG_SHORTS, data, data);
1336 } 1297 }
1337 1298
1338 /* sync status */ 1299 /* sync status */
@@ -1350,7 +1311,7 @@ int pm860x_mic_jack_detect(struct snd_soc_codec *codec,
1350 pm860x->det.mic_det = det; 1311 pm860x->det.mic_det = det;
1351 1312
1352 if (det & SND_JACK_MICROPHONE) 1313 if (det & SND_JACK_MICROPHONE)
1353 pm860x_set_bits(codec->control_data, REG_MIC_DET, 1314 pm860x_set_bits(pm860x->i2c, REG_MIC_DET,
1354 MICDET_MASK, MICDET_MASK); 1315 MICDET_MASK, MICDET_MASK);
1355 1316
1356 /* sync status */ 1317 /* sync status */
@@ -1366,7 +1327,7 @@ static int pm860x_probe(struct snd_soc_codec *codec)
1366 1327
1367 pm860x->codec = codec; 1328 pm860x->codec = codec;
1368 1329
1369 codec->control_data = pm860x->i2c; 1330 codec->control_data = pm860x->regmap;
1370 1331
1371 for (i = 0; i < 4; i++) { 1332 for (i = 0; i < 4; i++) {
1372 ret = request_threaded_irq(pm860x->irq[i], NULL, 1333 ret = request_threaded_irq(pm860x->irq[i], NULL,
@@ -1380,14 +1341,6 @@ static int pm860x_probe(struct snd_soc_codec *codec)
1380 1341
1381 pm860x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1342 pm860x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1382 1343
1383 ret = pm860x_bulk_read(codec->control_data, REG_CACHE_BASE,
1384 REG_CACHE_SIZE, codec->reg_cache);
1385 if (ret < 0) {
1386 dev_err(codec->dev, "Failed to fill register cache: %d\n",
1387 ret);
1388 goto out;
1389 }
1390
1391 return 0; 1344 return 0;
1392 1345
1393out: 1346out:
@@ -1410,10 +1363,6 @@ static int pm860x_remove(struct snd_soc_codec *codec)
1410static struct snd_soc_codec_driver soc_codec_dev_pm860x = { 1363static struct snd_soc_codec_driver soc_codec_dev_pm860x = {
1411 .probe = pm860x_probe, 1364 .probe = pm860x_probe,
1412 .remove = pm860x_remove, 1365 .remove = pm860x_remove,
1413 .read = pm860x_read_reg_cache,
1414 .write = pm860x_write_reg_cache,
1415 .reg_cache_size = REG_CACHE_SIZE,
1416 .reg_word_size = sizeof(u8),
1417 .set_bias_level = pm860x_set_bias_level, 1366 .set_bias_level = pm860x_set_bias_level,
1418 1367
1419 .controls = pm860x_snd_controls, 1368 .controls = pm860x_snd_controls,
@@ -1439,6 +1388,8 @@ static int pm860x_codec_probe(struct platform_device *pdev)
1439 pm860x->chip = chip; 1388 pm860x->chip = chip;
1440 pm860x->i2c = (chip->id == CHIP_PM8607) ? chip->client 1389 pm860x->i2c = (chip->id == CHIP_PM8607) ? chip->client
1441 : chip->companion; 1390 : chip->companion;
1391 pm860x->regmap = (chip->id == CHIP_PM8607) ? chip->regmap
1392 : chip->regmap_companion;
1442 platform_set_drvdata(pdev, pm860x); 1393 platform_set_drvdata(pdev, pm860x);
1443 1394
1444 for (i = 0; i < 4; i++) { 1395 for (i = 0; i < 4; i++) {
diff --git a/sound/soc/codecs/88pm860x-codec.h b/sound/soc/codecs/88pm860x-codec.h
index 3364ba4a3607..f7282f4f4a79 100644
--- a/sound/soc/codecs/88pm860x-codec.h
+++ b/sound/soc/codecs/88pm860x-codec.h
@@ -12,67 +12,66 @@
12#ifndef __88PM860X_H 12#ifndef __88PM860X_H
13#define __88PM860X_H 13#define __88PM860X_H
14 14
15/* The offset of these registers are 0xb0 */ 15#define PM860X_PCM_IFACE_1 0xb0
16#define PM860X_PCM_IFACE_1 0x00 16#define PM860X_PCM_IFACE_2 0xb1
17#define PM860X_PCM_IFACE_2 0x01 17#define PM860X_PCM_IFACE_3 0xb2
18#define PM860X_PCM_IFACE_3 0x02 18#define PM860X_PCM_RATE 0xb3
19#define PM860X_PCM_RATE 0x03 19#define PM860X_EC_PATH 0xb4
20#define PM860X_EC_PATH 0x04 20#define PM860X_SIDETONE_L_GAIN 0xb5
21#define PM860X_SIDETONE_L_GAIN 0x05 21#define PM860X_SIDETONE_R_GAIN 0xb6
22#define PM860X_SIDETONE_R_GAIN 0x06 22#define PM860X_SIDETONE_SHIFT 0xb7
23#define PM860X_SIDETONE_SHIFT 0x07 23#define PM860X_ADC_OFFSET_1 0xb8
24#define PM860X_ADC_OFFSET_1 0x08 24#define PM860X_ADC_OFFSET_2 0xb9
25#define PM860X_ADC_OFFSET_2 0x09 25#define PM860X_DMIC_DELAY 0xba
26#define PM860X_DMIC_DELAY 0x0a
27 26
28#define PM860X_I2S_IFACE_1 0x0b 27#define PM860X_I2S_IFACE_1 0xbb
29#define PM860X_I2S_IFACE_2 0x0c 28#define PM860X_I2S_IFACE_2 0xbc
30#define PM860X_I2S_IFACE_3 0x0d 29#define PM860X_I2S_IFACE_3 0xbd
31#define PM860X_I2S_IFACE_4 0x0e 30#define PM860X_I2S_IFACE_4 0xbe
32#define PM860X_EQUALIZER_N0_1 0x0f 31#define PM860X_EQUALIZER_N0_1 0xbf
33#define PM860X_EQUALIZER_N0_2 0x10 32#define PM860X_EQUALIZER_N0_2 0xc0
34#define PM860X_EQUALIZER_N1_1 0x11 33#define PM860X_EQUALIZER_N1_1 0xc1
35#define PM860X_EQUALIZER_N1_2 0x12 34#define PM860X_EQUALIZER_N1_2 0xc2
36#define PM860X_EQUALIZER_D1_1 0x13 35#define PM860X_EQUALIZER_D1_1 0xc3
37#define PM860X_EQUALIZER_D1_2 0x14 36#define PM860X_EQUALIZER_D1_2 0xc4
38#define PM860X_LOFI_GAIN_LEFT 0x15 37#define PM860X_LOFI_GAIN_LEFT 0xc5
39#define PM860X_LOFI_GAIN_RIGHT 0x16 38#define PM860X_LOFI_GAIN_RIGHT 0xc6
40#define PM860X_HIFIL_GAIN_LEFT 0x17 39#define PM860X_HIFIL_GAIN_LEFT 0xc7
41#define PM860X_HIFIL_GAIN_RIGHT 0x18 40#define PM860X_HIFIL_GAIN_RIGHT 0xc8
42#define PM860X_HIFIR_GAIN_LEFT 0x19 41#define PM860X_HIFIR_GAIN_LEFT 0xc9
43#define PM860X_HIFIR_GAIN_RIGHT 0x1a 42#define PM860X_HIFIR_GAIN_RIGHT 0xca
44#define PM860X_DAC_OFFSET 0x1b 43#define PM860X_DAC_OFFSET 0xcb
45#define PM860X_OFFSET_LEFT_1 0x1c 44#define PM860X_OFFSET_LEFT_1 0xcc
46#define PM860X_OFFSET_LEFT_2 0x1d 45#define PM860X_OFFSET_LEFT_2 0xcd
47#define PM860X_OFFSET_RIGHT_1 0x1e 46#define PM860X_OFFSET_RIGHT_1 0xce
48#define PM860X_OFFSET_RIGHT_2 0x1f 47#define PM860X_OFFSET_RIGHT_2 0xcf
49#define PM860X_ADC_ANA_1 0x20 48#define PM860X_ADC_ANA_1 0xd0
50#define PM860X_ADC_ANA_2 0x21 49#define PM860X_ADC_ANA_2 0xd1
51#define PM860X_ADC_ANA_3 0x22 50#define PM860X_ADC_ANA_3 0xd2
52#define PM860X_ADC_ANA_4 0x23 51#define PM860X_ADC_ANA_4 0xd3
53#define PM860X_ANA_TO_ANA 0x24 52#define PM860X_ANA_TO_ANA 0xd4
54#define PM860X_HS1_CTRL 0x25 53#define PM860X_HS1_CTRL 0xd5
55#define PM860X_HS2_CTRL 0x26 54#define PM860X_HS2_CTRL 0xd6
56#define PM860X_LO1_CTRL 0x27 55#define PM860X_LO1_CTRL 0xd7
57#define PM860X_LO2_CTRL 0x28 56#define PM860X_LO2_CTRL 0xd8
58#define PM860X_EAR_CTRL_1 0x29 57#define PM860X_EAR_CTRL_1 0xd9
59#define PM860X_EAR_CTRL_2 0x2a 58#define PM860X_EAR_CTRL_2 0xda
60#define PM860X_AUDIO_SUPPLIES_1 0x2b 59#define PM860X_AUDIO_SUPPLIES_1 0xdb
61#define PM860X_AUDIO_SUPPLIES_2 0x2c 60#define PM860X_AUDIO_SUPPLIES_2 0xdc
62#define PM860X_ADC_EN_1 0x2d 61#define PM860X_ADC_EN_1 0xdd
63#define PM860X_ADC_EN_2 0x2e 62#define PM860X_ADC_EN_2 0xde
64#define PM860X_DAC_EN_1 0x2f 63#define PM860X_DAC_EN_1 0xdf
65#define PM860X_DAC_EN_2 0x31 64#define PM860X_DAC_EN_2 0xe1
66#define PM860X_AUDIO_CAL_1 0x32 65#define PM860X_AUDIO_CAL_1 0xe2
67#define PM860X_AUDIO_CAL_2 0x33 66#define PM860X_AUDIO_CAL_2 0xe3
68#define PM860X_AUDIO_CAL_3 0x34 67#define PM860X_AUDIO_CAL_3 0xe4
69#define PM860X_AUDIO_CAL_4 0x35 68#define PM860X_AUDIO_CAL_4 0xe5
70#define PM860X_AUDIO_CAL_5 0x36 69#define PM860X_AUDIO_CAL_5 0xe6
71#define PM860X_ANA_INPUT_SEL_1 0x37 70#define PM860X_ANA_INPUT_SEL_1 0xe7
72#define PM860X_ANA_INPUT_SEL_2 0x38 71#define PM860X_ANA_INPUT_SEL_2 0xe8
73 72
74#define PM860X_PCM_IFACE_4 0x39 73#define PM860X_PCM_IFACE_4 0xe9
75#define PM860X_I2S_IFACE_5 0x3a 74#define PM860X_I2S_IFACE_5 0xea
76 75
77#define PM860X_SHORTS 0x3b 76#define PM860X_SHORTS 0x3b
78#define PM860X_PLL_ADJ_1 0x3c 77#define PM860X_PLL_ADJ_1 0x3c
diff --git a/sound/soc/codecs/ab8500-codec.c b/sound/soc/codecs/ab8500-codec.c
index 80555d7551e6..21ae8d4fdbfb 100644
--- a/sound/soc/codecs/ab8500-codec.c
+++ b/sound/soc/codecs/ab8500-codec.c
@@ -126,6 +126,8 @@ struct ab8500_codec_drvdata_dbg {
126 126
127/* Private data for AB8500 device-driver */ 127/* Private data for AB8500 device-driver */
128struct ab8500_codec_drvdata { 128struct ab8500_codec_drvdata {
129 struct regmap *regmap;
130
129 /* Sidetone */ 131 /* Sidetone */
130 long *sid_fir_values; 132 long *sid_fir_values;
131 enum sid_state sid_status; 133 enum sid_state sid_status;
@@ -166,49 +168,35 @@ static inline const char *amic_type_str(enum amic_type type)
166 */ 168 */
167 169
168/* Read a register from the audio-bank of AB8500 */ 170/* Read a register from the audio-bank of AB8500 */
169static unsigned int ab8500_codec_read_reg(struct snd_soc_codec *codec, 171static int ab8500_codec_read_reg(void *context, unsigned int reg,
170 unsigned int reg) 172 unsigned int *value)
171{ 173{
174 struct device *dev = context;
172 int status; 175 int status;
173 unsigned int value = 0;
174 176
175 u8 value8; 177 u8 value8;
176 status = abx500_get_register_interruptible(codec->dev, AB8500_AUDIO, 178 status = abx500_get_register_interruptible(dev, AB8500_AUDIO,
177 reg, &value8); 179 reg, &value8);
178 if (status < 0) { 180 *value = (unsigned int)value8;
179 dev_err(codec->dev,
180 "%s: ERROR: Register (0x%02x:0x%02x) read failed (%d).\n",
181 __func__, (u8)AB8500_AUDIO, (u8)reg, status);
182 } else {
183 dev_dbg(codec->dev,
184 "%s: Read 0x%02x from register 0x%02x:0x%02x\n",
185 __func__, value8, (u8)AB8500_AUDIO, (u8)reg);
186 value = (unsigned int)value8;
187 }
188 181
189 return value; 182 return status;
190} 183}
191 184
192/* Write to a register in the audio-bank of AB8500 */ 185/* Write to a register in the audio-bank of AB8500 */
193static int ab8500_codec_write_reg(struct snd_soc_codec *codec, 186static int ab8500_codec_write_reg(void *context, unsigned int reg,
194 unsigned int reg, unsigned int value) 187 unsigned int value)
195{ 188{
196 int status; 189 struct device *dev = context;
197
198 status = abx500_set_register_interruptible(codec->dev, AB8500_AUDIO,
199 reg, value);
200 if (status < 0)
201 dev_err(codec->dev,
202 "%s: ERROR: Register (%02x:%02x) write failed (%d).\n",
203 __func__, (u8)AB8500_AUDIO, (u8)reg, status);
204 else
205 dev_dbg(codec->dev,
206 "%s: Wrote 0x%02x into register %02x:%02x\n",
207 __func__, (u8)value, (u8)AB8500_AUDIO, (u8)reg);
208 190
209 return status; 191 return abx500_set_register_interruptible(dev, AB8500_AUDIO,
192 reg, value);
210} 193}
211 194
195static const struct regmap_config ab8500_codec_regmap = {
196 .reg_read = ab8500_codec_read_reg,
197 .reg_write = ab8500_codec_write_reg,
198};
199
212/* 200/*
213 * Controls - DAPM 201 * Controls - DAPM
214 */ 202 */
@@ -2312,17 +2300,17 @@ static int ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai *dai,
2312 case 0: 2300 case 0:
2313 break; 2301 break;
2314 case 1: 2302 case 1:
2315 slot = find_first_bit((unsigned long *)&tx_mask, 32); 2303 slot = ffs(tx_mask);
2316 snd_soc_update_bits(codec, AB8500_DASLOTCONF1, mask, slot); 2304 snd_soc_update_bits(codec, AB8500_DASLOTCONF1, mask, slot);
2317 snd_soc_update_bits(codec, AB8500_DASLOTCONF3, mask, slot); 2305 snd_soc_update_bits(codec, AB8500_DASLOTCONF3, mask, slot);
2318 snd_soc_update_bits(codec, AB8500_DASLOTCONF2, mask, slot); 2306 snd_soc_update_bits(codec, AB8500_DASLOTCONF2, mask, slot);
2319 snd_soc_update_bits(codec, AB8500_DASLOTCONF4, mask, slot); 2307 snd_soc_update_bits(codec, AB8500_DASLOTCONF4, mask, slot);
2320 break; 2308 break;
2321 case 2: 2309 case 2:
2322 slot = find_first_bit((unsigned long *)&tx_mask, 32); 2310 slot = ffs(tx_mask);
2323 snd_soc_update_bits(codec, AB8500_DASLOTCONF1, mask, slot); 2311 snd_soc_update_bits(codec, AB8500_DASLOTCONF1, mask, slot);
2324 snd_soc_update_bits(codec, AB8500_DASLOTCONF3, mask, slot); 2312 snd_soc_update_bits(codec, AB8500_DASLOTCONF3, mask, slot);
2325 slot = find_next_bit((unsigned long *)&tx_mask, 32, slot + 1); 2313 slot = fls(tx_mask);
2326 snd_soc_update_bits(codec, AB8500_DASLOTCONF2, mask, slot); 2314 snd_soc_update_bits(codec, AB8500_DASLOTCONF2, mask, slot);
2327 snd_soc_update_bits(codec, AB8500_DASLOTCONF4, mask, slot); 2315 snd_soc_update_bits(codec, AB8500_DASLOTCONF4, mask, slot);
2328 break; 2316 break;
@@ -2353,18 +2341,18 @@ static int ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai *dai,
2353 case 0: 2341 case 0:
2354 break; 2342 break;
2355 case 1: 2343 case 1:
2356 slot = find_first_bit((unsigned long *)&rx_mask, 32); 2344 slot = ffs(rx_mask);
2357 snd_soc_update_bits(codec, AB8500_ADSLOTSEL(slot), 2345 snd_soc_update_bits(codec, AB8500_ADSLOTSEL(slot),
2358 AB8500_MASK_SLOT(slot), 2346 AB8500_MASK_SLOT(slot),
2359 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot)); 2347 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
2360 break; 2348 break;
2361 case 2: 2349 case 2:
2362 slot = find_first_bit((unsigned long *)&rx_mask, 32); 2350 slot = ffs(rx_mask);
2363 snd_soc_update_bits(codec, 2351 snd_soc_update_bits(codec,
2364 AB8500_ADSLOTSEL(slot), 2352 AB8500_ADSLOTSEL(slot),
2365 AB8500_MASK_SLOT(slot), 2353 AB8500_MASK_SLOT(slot),
2366 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot)); 2354 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
2367 slot = find_next_bit((unsigned long *)&rx_mask, 32, slot + 1); 2355 slot = fls(rx_mask);
2368 snd_soc_update_bits(codec, 2356 snd_soc_update_bits(codec,
2369 AB8500_ADSLOTSEL(slot), 2357 AB8500_ADSLOTSEL(slot),
2370 AB8500_MASK_SLOT(slot), 2358 AB8500_MASK_SLOT(slot),
@@ -2485,9 +2473,13 @@ static int ab8500_codec_probe(struct snd_soc_codec *codec)
2485 2473
2486 dev_dbg(dev, "%s: Enter.\n", __func__); 2474 dev_dbg(dev, "%s: Enter.\n", __func__);
2487 2475
2476 snd_soc_codec_set_cache_io(codec, 0, 0, SND_SOC_REGMAP);
2477
2488 /* Setup AB8500 according to board-settings */ 2478 /* Setup AB8500 according to board-settings */
2489 pdata = dev_get_platdata(dev->parent); 2479 pdata = dev_get_platdata(dev->parent);
2490 2480
2481 codec->control_data = drvdata->regmap;
2482
2491 if (np) { 2483 if (np) {
2492 if (!pdata) 2484 if (!pdata)
2493 pdata = devm_kzalloc(dev, 2485 pdata = devm_kzalloc(dev,
@@ -2532,12 +2524,10 @@ static int ab8500_codec_probe(struct snd_soc_codec *codec)
2532 } 2524 }
2533 2525
2534 /* Override HW-defaults */ 2526 /* Override HW-defaults */
2535 ab8500_codec_write_reg(codec, 2527 snd_soc_write(codec, AB8500_ANACONF5,
2536 AB8500_ANACONF5, 2528 BIT(AB8500_ANACONF5_HSAUTOEN));
2537 BIT(AB8500_ANACONF5_HSAUTOEN)); 2529 snd_soc_write(codec, AB8500_SHORTCIRCONF,
2538 ab8500_codec_write_reg(codec, 2530 BIT(AB8500_SHORTCIRCONF_HSZCDDIS));
2539 AB8500_SHORTCIRCONF,
2540 BIT(AB8500_SHORTCIRCONF_HSZCDDIS));
2541 2531
2542 /* Add filter controls */ 2532 /* Add filter controls */
2543 status = snd_soc_add_codec_controls(codec, ab8500_filter_controls, 2533 status = snd_soc_add_codec_controls(codec, ab8500_filter_controls,
@@ -2567,9 +2557,6 @@ static int ab8500_codec_probe(struct snd_soc_codec *codec)
2567 2557
2568static struct snd_soc_codec_driver ab8500_codec_driver = { 2558static struct snd_soc_codec_driver ab8500_codec_driver = {
2569 .probe = ab8500_codec_probe, 2559 .probe = ab8500_codec_probe,
2570 .read = ab8500_codec_read_reg,
2571 .write = ab8500_codec_write_reg,
2572 .reg_word_size = sizeof(u8),
2573 .controls = ab8500_ctrls, 2560 .controls = ab8500_ctrls,
2574 .num_controls = ARRAY_SIZE(ab8500_ctrls), 2561 .num_controls = ARRAY_SIZE(ab8500_ctrls),
2575 .dapm_widgets = ab8500_dapm_widgets, 2562 .dapm_widgets = ab8500_dapm_widgets,
@@ -2588,10 +2575,21 @@ static int ab8500_codec_driver_probe(struct platform_device *pdev)
2588 /* Create driver private-data struct */ 2575 /* Create driver private-data struct */
2589 drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_codec_drvdata), 2576 drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_codec_drvdata),
2590 GFP_KERNEL); 2577 GFP_KERNEL);
2578 if (!drvdata)
2579 return -ENOMEM;
2591 drvdata->sid_status = SID_UNCONFIGURED; 2580 drvdata->sid_status = SID_UNCONFIGURED;
2592 drvdata->anc_status = ANC_UNCONFIGURED; 2581 drvdata->anc_status = ANC_UNCONFIGURED;
2593 dev_set_drvdata(&pdev->dev, drvdata); 2582 dev_set_drvdata(&pdev->dev, drvdata);
2594 2583
2584 drvdata->regmap = devm_regmap_init(&pdev->dev, NULL, &pdev->dev,
2585 &ab8500_codec_regmap);
2586 if (IS_ERR(drvdata->regmap)) {
2587 status = PTR_ERR(drvdata->regmap);
2588 dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
2589 __func__, status);
2590 return status;
2591 }
2592
2595 dev_dbg(&pdev->dev, "%s: Register codec.\n", __func__); 2593 dev_dbg(&pdev->dev, "%s: Register codec.\n", __func__);
2596 status = snd_soc_register_codec(&pdev->dev, &ab8500_codec_driver, 2594 status = snd_soc_register_codec(&pdev->dev, &ab8500_codec_driver,
2597 ab8500_codec_dai, 2595 ab8500_codec_dai,
@@ -2606,7 +2604,7 @@ static int ab8500_codec_driver_probe(struct platform_device *pdev)
2606 2604
2607static int ab8500_codec_driver_remove(struct platform_device *pdev) 2605static int ab8500_codec_driver_remove(struct platform_device *pdev)
2608{ 2606{
2609 dev_info(&pdev->dev, "%s Enter.\n", __func__); 2607 dev_dbg(&pdev->dev, "%s Enter.\n", __func__);
2610 2608
2611 snd_soc_unregister_codec(&pdev->dev); 2609 snd_soc_unregister_codec(&pdev->dev);
2612 2610
diff --git a/sound/soc/codecs/adau1373.c b/sound/soc/codecs/adau1373.c
index 1aa10ddf3a61..59654b1e7f3f 100644
--- a/sound/soc/codecs/adau1373.c
+++ b/sound/soc/codecs/adau1373.c
@@ -32,6 +32,7 @@ struct adau1373_dai {
32}; 32};
33 33
34struct adau1373 { 34struct adau1373 {
35 struct regmap *regmap;
35 struct adau1373_dai dais[3]; 36 struct adau1373_dai dais[3];
36}; 37};
37 38
@@ -73,7 +74,6 @@ struct adau1373 {
73#define ADAU1373_PLL_CTRL4(x) (0x2c + (x) * 7) 74#define ADAU1373_PLL_CTRL4(x) (0x2c + (x) * 7)
74#define ADAU1373_PLL_CTRL5(x) (0x2d + (x) * 7) 75#define ADAU1373_PLL_CTRL5(x) (0x2d + (x) * 7)
75#define ADAU1373_PLL_CTRL6(x) (0x2e + (x) * 7) 76#define ADAU1373_PLL_CTRL6(x) (0x2e + (x) * 7)
76#define ADAU1373_PLL_CTRL7(x) (0x2f + (x) * 7)
77#define ADAU1373_HEADDECT 0x36 77#define ADAU1373_HEADDECT 0x36
78#define ADAU1373_ADC_DAC_STATUS 0x37 78#define ADAU1373_ADC_DAC_STATUS 0x37
79#define ADAU1373_ADC_CTRL 0x3c 79#define ADAU1373_ADC_CTRL 0x3c
@@ -152,37 +152,172 @@ struct adau1373 {
152#define ADAU1373_EP_CTRL_MICBIAS1_OFFSET 4 152#define ADAU1373_EP_CTRL_MICBIAS1_OFFSET 4
153#define ADAU1373_EP_CTRL_MICBIAS2_OFFSET 2 153#define ADAU1373_EP_CTRL_MICBIAS2_OFFSET 2
154 154
155static const uint8_t adau1373_default_regs[] = { 155static const struct reg_default adau1373_reg_defaults[] = {
156 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x00 */ 156 { ADAU1373_INPUT_MODE, 0x00 },
157 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 157 { ADAU1373_AINL_CTRL(0), 0x00 },
158 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x10 */ 158 { ADAU1373_AINR_CTRL(0), 0x00 },
159 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 159 { ADAU1373_AINL_CTRL(1), 0x00 },
160 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */ 160 { ADAU1373_AINR_CTRL(1), 0x00 },
161 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 161 { ADAU1373_AINL_CTRL(2), 0x00 },
162 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, /* 0x30 */ 162 { ADAU1373_AINR_CTRL(2), 0x00 },
163 0x00, 0x00, 0x00, 0x80, 0x00, 0x01, 0x00, 0x00, 163 { ADAU1373_AINL_CTRL(3), 0x00 },
164 0x00, 0x00, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x00, /* 0x40 */ 164 { ADAU1373_AINR_CTRL(3), 0x00 },
165 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 165 { ADAU1373_LLINE_OUT(0), 0x00 },
166 0x00, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, /* 0x50 */ 166 { ADAU1373_RLINE_OUT(0), 0x00 },
167 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 167 { ADAU1373_LLINE_OUT(1), 0x00 },
168 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x60 */ 168 { ADAU1373_RLINE_OUT(1), 0x00 },
169 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 169 { ADAU1373_LSPK_OUT, 0x00 },
170 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x70 */ 170 { ADAU1373_RSPK_OUT, 0x00 },
171 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 171 { ADAU1373_LHP_OUT, 0x00 },
172 0x78, 0x18, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, /* 0x80 */ 172 { ADAU1373_RHP_OUT, 0x00 },
173 0x00, 0xc0, 0x88, 0x7a, 0xdf, 0x20, 0x00, 0x00, 173 { ADAU1373_ADC_GAIN, 0x00 },
174 0x78, 0x18, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, /* 0x90 */ 174 { ADAU1373_LADC_MIXER, 0x00 },
175 0x00, 0xc0, 0x88, 0x7a, 0xdf, 0x20, 0x00, 0x00, 175 { ADAU1373_RADC_MIXER, 0x00 },
176 0x78, 0x18, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, /* 0xa0 */ 176 { ADAU1373_LLINE1_MIX, 0x00 },
177 0x00, 0xc0, 0x88, 0x7a, 0xdf, 0x20, 0x00, 0x00, 177 { ADAU1373_RLINE1_MIX, 0x00 },
178 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0xb0 */ 178 { ADAU1373_LLINE2_MIX, 0x00 },
179 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 179 { ADAU1373_RLINE2_MIX, 0x00 },
180 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xc0 */ 180 { ADAU1373_LSPK_MIX, 0x00 },
181 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 181 { ADAU1373_RSPK_MIX, 0x00 },
182 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xd0 */ 182 { ADAU1373_LHP_MIX, 0x00 },
183 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 183 { ADAU1373_RHP_MIX, 0x00 },
184 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, /* 0xe0 */ 184 { ADAU1373_EP_MIX, 0x00 },
185 0x00, 0x1f, 0x0f, 0x00, 0x00, 185 { ADAU1373_HP_CTRL, 0x00 },
186 { ADAU1373_HP_CTRL2, 0x00 },
187 { ADAU1373_LS_CTRL, 0x00 },
188 { ADAU1373_EP_CTRL, 0x00 },
189 { ADAU1373_MICBIAS_CTRL1, 0x00 },
190 { ADAU1373_MICBIAS_CTRL2, 0x00 },
191 { ADAU1373_OUTPUT_CTRL, 0x00 },
192 { ADAU1373_PWDN_CTRL1, 0x00 },
193 { ADAU1373_PWDN_CTRL2, 0x00 },
194 { ADAU1373_PWDN_CTRL3, 0x00 },
195 { ADAU1373_DPLL_CTRL(0), 0x00 },
196 { ADAU1373_PLL_CTRL1(0), 0x00 },
197 { ADAU1373_PLL_CTRL2(0), 0x00 },
198 { ADAU1373_PLL_CTRL3(0), 0x00 },
199 { ADAU1373_PLL_CTRL4(0), 0x00 },
200 { ADAU1373_PLL_CTRL5(0), 0x00 },
201 { ADAU1373_PLL_CTRL6(0), 0x02 },
202 { ADAU1373_DPLL_CTRL(1), 0x00 },
203 { ADAU1373_PLL_CTRL1(1), 0x00 },
204 { ADAU1373_PLL_CTRL2(1), 0x00 },
205 { ADAU1373_PLL_CTRL3(1), 0x00 },
206 { ADAU1373_PLL_CTRL4(1), 0x00 },
207 { ADAU1373_PLL_CTRL5(1), 0x00 },
208 { ADAU1373_PLL_CTRL6(1), 0x02 },
209 { ADAU1373_HEADDECT, 0x00 },
210 { ADAU1373_ADC_CTRL, 0x00 },
211 { ADAU1373_CLK_SRC_DIV(0), 0x00 },
212 { ADAU1373_CLK_SRC_DIV(1), 0x00 },
213 { ADAU1373_DAI(0), 0x0a },
214 { ADAU1373_DAI(1), 0x0a },
215 { ADAU1373_DAI(2), 0x0a },
216 { ADAU1373_BCLKDIV(0), 0x00 },
217 { ADAU1373_BCLKDIV(1), 0x00 },
218 { ADAU1373_BCLKDIV(2), 0x00 },
219 { ADAU1373_SRC_RATIOA(0), 0x00 },
220 { ADAU1373_SRC_RATIOB(0), 0x00 },
221 { ADAU1373_SRC_RATIOA(1), 0x00 },
222 { ADAU1373_SRC_RATIOB(1), 0x00 },
223 { ADAU1373_SRC_RATIOA(2), 0x00 },
224 { ADAU1373_SRC_RATIOB(2), 0x00 },
225 { ADAU1373_DEEMP_CTRL, 0x00 },
226 { ADAU1373_SRC_DAI_CTRL(0), 0x08 },
227 { ADAU1373_SRC_DAI_CTRL(1), 0x08 },
228 { ADAU1373_SRC_DAI_CTRL(2), 0x08 },
229 { ADAU1373_DIN_MIX_CTRL(0), 0x00 },
230 { ADAU1373_DIN_MIX_CTRL(1), 0x00 },
231 { ADAU1373_DIN_MIX_CTRL(2), 0x00 },
232 { ADAU1373_DIN_MIX_CTRL(3), 0x00 },
233 { ADAU1373_DIN_MIX_CTRL(4), 0x00 },
234 { ADAU1373_DOUT_MIX_CTRL(0), 0x00 },
235 { ADAU1373_DOUT_MIX_CTRL(1), 0x00 },
236 { ADAU1373_DOUT_MIX_CTRL(2), 0x00 },
237 { ADAU1373_DOUT_MIX_CTRL(3), 0x00 },
238 { ADAU1373_DOUT_MIX_CTRL(4), 0x00 },
239 { ADAU1373_DAI_PBL_VOL(0), 0x00 },
240 { ADAU1373_DAI_PBR_VOL(0), 0x00 },
241 { ADAU1373_DAI_PBL_VOL(1), 0x00 },
242 { ADAU1373_DAI_PBR_VOL(1), 0x00 },
243 { ADAU1373_DAI_PBL_VOL(2), 0x00 },
244 { ADAU1373_DAI_PBR_VOL(2), 0x00 },
245 { ADAU1373_DAI_RECL_VOL(0), 0x00 },
246 { ADAU1373_DAI_RECR_VOL(0), 0x00 },
247 { ADAU1373_DAI_RECL_VOL(1), 0x00 },
248 { ADAU1373_DAI_RECR_VOL(1), 0x00 },
249 { ADAU1373_DAI_RECL_VOL(2), 0x00 },
250 { ADAU1373_DAI_RECR_VOL(2), 0x00 },
251 { ADAU1373_DAC1_PBL_VOL, 0x00 },
252 { ADAU1373_DAC1_PBR_VOL, 0x00 },
253 { ADAU1373_DAC2_PBL_VOL, 0x00 },
254 { ADAU1373_DAC2_PBR_VOL, 0x00 },
255 { ADAU1373_ADC_RECL_VOL, 0x00 },
256 { ADAU1373_ADC_RECR_VOL, 0x00 },
257 { ADAU1373_DMIC_RECL_VOL, 0x00 },
258 { ADAU1373_DMIC_RECR_VOL, 0x00 },
259 { ADAU1373_VOL_GAIN1, 0x00 },
260 { ADAU1373_VOL_GAIN2, 0x00 },
261 { ADAU1373_VOL_GAIN3, 0x00 },
262 { ADAU1373_HPF_CTRL, 0x00 },
263 { ADAU1373_BASS1, 0x00 },
264 { ADAU1373_BASS2, 0x00 },
265 { ADAU1373_DRC(0) + 0x0, 0x78 },
266 { ADAU1373_DRC(0) + 0x1, 0x18 },
267 { ADAU1373_DRC(0) + 0x2, 0x00 },
268 { ADAU1373_DRC(0) + 0x3, 0x00 },
269 { ADAU1373_DRC(0) + 0x4, 0x00 },
270 { ADAU1373_DRC(0) + 0x5, 0xc0 },
271 { ADAU1373_DRC(0) + 0x6, 0x00 },
272 { ADAU1373_DRC(0) + 0x7, 0x00 },
273 { ADAU1373_DRC(0) + 0x8, 0x00 },
274 { ADAU1373_DRC(0) + 0x9, 0xc0 },
275 { ADAU1373_DRC(0) + 0xa, 0x88 },
276 { ADAU1373_DRC(0) + 0xb, 0x7a },
277 { ADAU1373_DRC(0) + 0xc, 0xdf },
278 { ADAU1373_DRC(0) + 0xd, 0x20 },
279 { ADAU1373_DRC(0) + 0xe, 0x00 },
280 { ADAU1373_DRC(0) + 0xf, 0x00 },
281 { ADAU1373_DRC(1) + 0x0, 0x78 },
282 { ADAU1373_DRC(1) + 0x1, 0x18 },
283 { ADAU1373_DRC(1) + 0x2, 0x00 },
284 { ADAU1373_DRC(1) + 0x3, 0x00 },
285 { ADAU1373_DRC(1) + 0x4, 0x00 },
286 { ADAU1373_DRC(1) + 0x5, 0xc0 },
287 { ADAU1373_DRC(1) + 0x6, 0x00 },
288 { ADAU1373_DRC(1) + 0x7, 0x00 },
289 { ADAU1373_DRC(1) + 0x8, 0x00 },
290 { ADAU1373_DRC(1) + 0x9, 0xc0 },
291 { ADAU1373_DRC(1) + 0xa, 0x88 },
292 { ADAU1373_DRC(1) + 0xb, 0x7a },
293 { ADAU1373_DRC(1) + 0xc, 0xdf },
294 { ADAU1373_DRC(1) + 0xd, 0x20 },
295 { ADAU1373_DRC(1) + 0xe, 0x00 },
296 { ADAU1373_DRC(1) + 0xf, 0x00 },
297 { ADAU1373_DRC(2) + 0x0, 0x78 },
298 { ADAU1373_DRC(2) + 0x1, 0x18 },
299 { ADAU1373_DRC(2) + 0x2, 0x00 },
300 { ADAU1373_DRC(2) + 0x3, 0x00 },
301 { ADAU1373_DRC(2) + 0x4, 0x00 },
302 { ADAU1373_DRC(2) + 0x5, 0xc0 },
303 { ADAU1373_DRC(2) + 0x6, 0x00 },
304 { ADAU1373_DRC(2) + 0x7, 0x00 },
305 { ADAU1373_DRC(2) + 0x8, 0x00 },
306 { ADAU1373_DRC(2) + 0x9, 0xc0 },
307 { ADAU1373_DRC(2) + 0xa, 0x88 },
308 { ADAU1373_DRC(2) + 0xb, 0x7a },
309 { ADAU1373_DRC(2) + 0xc, 0xdf },
310 { ADAU1373_DRC(2) + 0xd, 0x20 },
311 { ADAU1373_DRC(2) + 0xe, 0x00 },
312 { ADAU1373_DRC(2) + 0xf, 0x00 },
313 { ADAU1373_3D_CTRL1, 0x00 },
314 { ADAU1373_3D_CTRL2, 0x00 },
315 { ADAU1373_FDSP_SEL1, 0x00 },
316 { ADAU1373_FDSP_SEL2, 0x00 },
317 { ADAU1373_FDSP_SEL2, 0x00 },
318 { ADAU1373_FDSP_SEL4, 0x00 },
319 { ADAU1373_DIGMICCTRL, 0x00 },
320 { ADAU1373_DIGEN, 0x00 },
186}; 321};
187 322
188static const unsigned int adau1373_out_tlv[] = { 323static const unsigned int adau1373_out_tlv[] = {
@@ -418,6 +553,7 @@ static int adau1373_pll_event(struct snd_soc_dapm_widget *w,
418 struct snd_kcontrol *kcontrol, int event) 553 struct snd_kcontrol *kcontrol, int event)
419{ 554{
420 struct snd_soc_codec *codec = w->codec; 555 struct snd_soc_codec *codec = w->codec;
556 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
421 unsigned int pll_id = w->name[3] - '1'; 557 unsigned int pll_id = w->name[3] - '1';
422 unsigned int val; 558 unsigned int val;
423 559
@@ -426,7 +562,7 @@ static int adau1373_pll_event(struct snd_soc_dapm_widget *w,
426 else 562 else
427 val = 0; 563 val = 0;
428 564
429 snd_soc_update_bits(codec, ADAU1373_PLL_CTRL6(pll_id), 565 regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
430 ADAU1373_PLL_CTRL6_PLL_EN, val); 566 ADAU1373_PLL_CTRL6_PLL_EN, val);
431 567
432 if (SND_SOC_DAPM_EVENT_ON(event)) 568 if (SND_SOC_DAPM_EVENT_ON(event))
@@ -938,7 +1074,7 @@ static int adau1373_hw_params(struct snd_pcm_substream *substream,
938 1074
939 adau1373_dai->enable_src = (div != 0); 1075 adau1373_dai->enable_src = (div != 0);
940 1076
941 snd_soc_update_bits(codec, ADAU1373_BCLKDIV(dai->id), 1077 regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id),
942 ADAU1373_BCLKDIV_SR_MASK | ADAU1373_BCLKDIV_BCLK_MASK, 1078 ADAU1373_BCLKDIV_SR_MASK | ADAU1373_BCLKDIV_BCLK_MASK,
943 (div << 2) | ADAU1373_BCLKDIV_64); 1079 (div << 2) | ADAU1373_BCLKDIV_64);
944 1080
@@ -959,7 +1095,7 @@ static int adau1373_hw_params(struct snd_pcm_substream *substream,
959 return -EINVAL; 1095 return -EINVAL;
960 } 1096 }
961 1097
962 return snd_soc_update_bits(codec, ADAU1373_DAI(dai->id), 1098 return regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),
963 ADAU1373_DAI_WLEN_MASK, ctrl); 1099 ADAU1373_DAI_WLEN_MASK, ctrl);
964} 1100}
965 1101
@@ -1016,7 +1152,7 @@ static int adau1373_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1016 return -EINVAL; 1152 return -EINVAL;
1017 } 1153 }
1018 1154
1019 snd_soc_update_bits(codec, ADAU1373_DAI(dai->id), 1155 regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),
1020 ~ADAU1373_DAI_WLEN_MASK, ctrl); 1156 ~ADAU1373_DAI_WLEN_MASK, ctrl);
1021 1157
1022 return 0; 1158 return 0;
@@ -1039,7 +1175,7 @@ static int adau1373_set_dai_sysclk(struct snd_soc_dai *dai,
1039 adau1373_dai->sysclk = freq; 1175 adau1373_dai->sysclk = freq;
1040 adau1373_dai->clk_src = clk_id; 1176 adau1373_dai->clk_src = clk_id;
1041 1177
1042 snd_soc_update_bits(dai->codec, ADAU1373_BCLKDIV(dai->id), 1178 regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id),
1043 ADAU1373_BCLKDIV_SOURCE, clk_id << 5); 1179 ADAU1373_BCLKDIV_SOURCE, clk_id << 5);
1044 1180
1045 return 0; 1181 return 0;
@@ -1120,6 +1256,7 @@ static struct snd_soc_dai_driver adau1373_dai_driver[] = {
1120static int adau1373_set_pll(struct snd_soc_codec *codec, int pll_id, 1256static int adau1373_set_pll(struct snd_soc_codec *codec, int pll_id,
1121 int source, unsigned int freq_in, unsigned int freq_out) 1257 int source, unsigned int freq_in, unsigned int freq_out)
1122{ 1258{
1259 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1123 unsigned int dpll_div = 0; 1260 unsigned int dpll_div = 0;
1124 unsigned int x, r, n, m, i, j, mode; 1261 unsigned int x, r, n, m, i, j, mode;
1125 1262
@@ -1187,36 +1324,36 @@ static int adau1373_set_pll(struct snd_soc_codec *codec, int pll_id,
1187 1324
1188 if (dpll_div) { 1325 if (dpll_div) {
1189 dpll_div = 11 - dpll_div; 1326 dpll_div = 11 - dpll_div;
1190 snd_soc_update_bits(codec, ADAU1373_PLL_CTRL6(pll_id), 1327 regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
1191 ADAU1373_PLL_CTRL6_DPLL_BYPASS, 0); 1328 ADAU1373_PLL_CTRL6_DPLL_BYPASS, 0);
1192 } else { 1329 } else {
1193 snd_soc_update_bits(codec, ADAU1373_PLL_CTRL6(pll_id), 1330 regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
1194 ADAU1373_PLL_CTRL6_DPLL_BYPASS, 1331 ADAU1373_PLL_CTRL6_DPLL_BYPASS,
1195 ADAU1373_PLL_CTRL6_DPLL_BYPASS); 1332 ADAU1373_PLL_CTRL6_DPLL_BYPASS);
1196 } 1333 }
1197 1334
1198 snd_soc_write(codec, ADAU1373_DPLL_CTRL(pll_id), 1335 regmap_write(adau1373->regmap, ADAU1373_DPLL_CTRL(pll_id),
1199 (source << 4) | dpll_div); 1336 (source << 4) | dpll_div);
1200 snd_soc_write(codec, ADAU1373_PLL_CTRL1(pll_id), (m >> 8) & 0xff); 1337 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL1(pll_id), (m >> 8) & 0xff);
1201 snd_soc_write(codec, ADAU1373_PLL_CTRL2(pll_id), m & 0xff); 1338 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL2(pll_id), m & 0xff);
1202 snd_soc_write(codec, ADAU1373_PLL_CTRL3(pll_id), (n >> 8) & 0xff); 1339 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL3(pll_id), (n >> 8) & 0xff);
1203 snd_soc_write(codec, ADAU1373_PLL_CTRL4(pll_id), n & 0xff); 1340 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL4(pll_id), n & 0xff);
1204 snd_soc_write(codec, ADAU1373_PLL_CTRL5(pll_id), 1341 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL5(pll_id),
1205 (r << 3) | (x << 1) | mode); 1342 (r << 3) | (x << 1) | mode);
1206 1343
1207 /* Set sysclk to pll_rate / 4 */ 1344 /* Set sysclk to pll_rate / 4 */
1208 snd_soc_update_bits(codec, ADAU1373_CLK_SRC_DIV(pll_id), 0x3f, 0x09); 1345 regmap_update_bits(adau1373->regmap, ADAU1373_CLK_SRC_DIV(pll_id), 0x3f, 0x09);
1209 1346
1210 return 0; 1347 return 0;
1211} 1348}
1212 1349
1213static void adau1373_load_drc_settings(struct snd_soc_codec *codec, 1350static void adau1373_load_drc_settings(struct adau1373 *adau1373,
1214 unsigned int nr, uint8_t *drc) 1351 unsigned int nr, uint8_t *drc)
1215{ 1352{
1216 unsigned int i; 1353 unsigned int i;
1217 1354
1218 for (i = 0; i < ADAU1373_DRC_SIZE; ++i) 1355 for (i = 0; i < ADAU1373_DRC_SIZE; ++i)
1219 snd_soc_write(codec, ADAU1373_DRC(nr) + i, drc[i]); 1356 regmap_write(adau1373->regmap, ADAU1373_DRC(nr) + i, drc[i]);
1220} 1357}
1221 1358
1222static bool adau1373_valid_micbias(enum adau1373_micbias_voltage micbias) 1359static bool adau1373_valid_micbias(enum adau1373_micbias_voltage micbias)
@@ -1235,13 +1372,14 @@ static bool adau1373_valid_micbias(enum adau1373_micbias_voltage micbias)
1235 1372
1236static int adau1373_probe(struct snd_soc_codec *codec) 1373static int adau1373_probe(struct snd_soc_codec *codec)
1237{ 1374{
1375 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1238 struct adau1373_platform_data *pdata = codec->dev->platform_data; 1376 struct adau1373_platform_data *pdata = codec->dev->platform_data;
1239 bool lineout_differential = false; 1377 bool lineout_differential = false;
1240 unsigned int val; 1378 unsigned int val;
1241 int ret; 1379 int ret;
1242 int i; 1380 int i;
1243 1381
1244 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); 1382 ret = snd_soc_codec_set_cache_io(codec, 0, 0, SND_SOC_REGMAP);
1245 if (ret) { 1383 if (ret) {
1246 dev_err(codec->dev, "failed to set cache I/O: %d\n", ret); 1384 dev_err(codec->dev, "failed to set cache I/O: %d\n", ret);
1247 return ret; 1385 return ret;
@@ -1256,7 +1394,7 @@ static int adau1373_probe(struct snd_soc_codec *codec)
1256 return -EINVAL; 1394 return -EINVAL;
1257 1395
1258 for (i = 0; i < pdata->num_drc; ++i) { 1396 for (i = 0; i < pdata->num_drc; ++i) {
1259 adau1373_load_drc_settings(codec, i, 1397 adau1373_load_drc_settings(adau1373, i,
1260 pdata->drc_setting[i]); 1398 pdata->drc_setting[i]);
1261 } 1399 }
1262 1400
@@ -1268,18 +1406,18 @@ static int adau1373_probe(struct snd_soc_codec *codec)
1268 if (pdata->input_differential[i]) 1406 if (pdata->input_differential[i])
1269 val |= BIT(i); 1407 val |= BIT(i);
1270 } 1408 }
1271 snd_soc_write(codec, ADAU1373_INPUT_MODE, val); 1409 regmap_write(adau1373->regmap, ADAU1373_INPUT_MODE, val);
1272 1410
1273 val = 0; 1411 val = 0;
1274 if (pdata->lineout_differential) 1412 if (pdata->lineout_differential)
1275 val |= ADAU1373_OUTPUT_CTRL_LDIFF; 1413 val |= ADAU1373_OUTPUT_CTRL_LDIFF;
1276 if (pdata->lineout_ground_sense) 1414 if (pdata->lineout_ground_sense)
1277 val |= ADAU1373_OUTPUT_CTRL_LNFBEN; 1415 val |= ADAU1373_OUTPUT_CTRL_LNFBEN;
1278 snd_soc_write(codec, ADAU1373_OUTPUT_CTRL, val); 1416 regmap_write(adau1373->regmap, ADAU1373_OUTPUT_CTRL, val);
1279 1417
1280 lineout_differential = pdata->lineout_differential; 1418 lineout_differential = pdata->lineout_differential;
1281 1419
1282 snd_soc_write(codec, ADAU1373_EP_CTRL, 1420 regmap_write(adau1373->regmap, ADAU1373_EP_CTRL,
1283 (pdata->micbias1 << ADAU1373_EP_CTRL_MICBIAS1_OFFSET) | 1421 (pdata->micbias1 << ADAU1373_EP_CTRL_MICBIAS1_OFFSET) |
1284 (pdata->micbias2 << ADAU1373_EP_CTRL_MICBIAS2_OFFSET)); 1422 (pdata->micbias2 << ADAU1373_EP_CTRL_MICBIAS2_OFFSET));
1285 } 1423 }
@@ -1289,7 +1427,7 @@ static int adau1373_probe(struct snd_soc_codec *codec)
1289 ARRAY_SIZE(adau1373_lineout2_controls)); 1427 ARRAY_SIZE(adau1373_lineout2_controls));
1290 } 1428 }
1291 1429
1292 snd_soc_write(codec, ADAU1373_ADC_CTRL, 1430 regmap_write(adau1373->regmap, ADAU1373_ADC_CTRL,
1293 ADAU1373_ADC_CTRL_RESET_FORCE | ADAU1373_ADC_CTRL_PEAK_DETECT); 1431 ADAU1373_ADC_CTRL_RESET_FORCE | ADAU1373_ADC_CTRL_PEAK_DETECT);
1294 1432
1295 return 0; 1433 return 0;
@@ -1298,17 +1436,19 @@ static int adau1373_probe(struct snd_soc_codec *codec)
1298static int adau1373_set_bias_level(struct snd_soc_codec *codec, 1436static int adau1373_set_bias_level(struct snd_soc_codec *codec,
1299 enum snd_soc_bias_level level) 1437 enum snd_soc_bias_level level)
1300{ 1438{
1439 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1440
1301 switch (level) { 1441 switch (level) {
1302 case SND_SOC_BIAS_ON: 1442 case SND_SOC_BIAS_ON:
1303 break; 1443 break;
1304 case SND_SOC_BIAS_PREPARE: 1444 case SND_SOC_BIAS_PREPARE:
1305 break; 1445 break;
1306 case SND_SOC_BIAS_STANDBY: 1446 case SND_SOC_BIAS_STANDBY:
1307 snd_soc_update_bits(codec, ADAU1373_PWDN_CTRL3, 1447 regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3,
1308 ADAU1373_PWDN_CTRL3_PWR_EN, ADAU1373_PWDN_CTRL3_PWR_EN); 1448 ADAU1373_PWDN_CTRL3_PWR_EN, ADAU1373_PWDN_CTRL3_PWR_EN);
1309 break; 1449 break;
1310 case SND_SOC_BIAS_OFF: 1450 case SND_SOC_BIAS_OFF:
1311 snd_soc_update_bits(codec, ADAU1373_PWDN_CTRL3, 1451 regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3,
1312 ADAU1373_PWDN_CTRL3_PWR_EN, 0); 1452 ADAU1373_PWDN_CTRL3_PWR_EN, 0);
1313 break; 1453 break;
1314 } 1454 }
@@ -1324,17 +1464,49 @@ static int adau1373_remove(struct snd_soc_codec *codec)
1324 1464
1325static int adau1373_suspend(struct snd_soc_codec *codec) 1465static int adau1373_suspend(struct snd_soc_codec *codec)
1326{ 1466{
1327 return adau1373_set_bias_level(codec, SND_SOC_BIAS_OFF); 1467 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1468 int ret;
1469
1470 ret = adau1373_set_bias_level(codec, SND_SOC_BIAS_OFF);
1471 regcache_cache_only(adau1373->regmap, true);
1472
1473 return ret;
1328} 1474}
1329 1475
1330static int adau1373_resume(struct snd_soc_codec *codec) 1476static int adau1373_resume(struct snd_soc_codec *codec)
1331{ 1477{
1478 struct adau1373 *adau1373 = snd_soc_codec_get_drvdata(codec);
1479
1480 regcache_cache_only(adau1373->regmap, false);
1332 adau1373_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1481 adau1373_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1333 snd_soc_cache_sync(codec); 1482 regcache_sync(adau1373->regmap);
1334 1483
1335 return 0; 1484 return 0;
1336} 1485}
1337 1486
1487static bool adau1373_register_volatile(struct device *dev, unsigned int reg)
1488{
1489 switch (reg) {
1490 case ADAU1373_SOFT_RESET:
1491 case ADAU1373_ADC_DAC_STATUS:
1492 return true;
1493 default:
1494 return false;
1495 }
1496}
1497
1498static const struct regmap_config adau1373_regmap_config = {
1499 .val_bits = 8,
1500 .reg_bits = 8,
1501
1502 .volatile_reg = adau1373_register_volatile,
1503 .max_register = ADAU1373_SOFT_RESET,
1504
1505 .cache_type = REGCACHE_RBTREE,
1506 .reg_defaults = adau1373_reg_defaults,
1507 .num_reg_defaults = ARRAY_SIZE(adau1373_reg_defaults),
1508};
1509
1338static struct snd_soc_codec_driver adau1373_codec_driver = { 1510static struct snd_soc_codec_driver adau1373_codec_driver = {
1339 .probe = adau1373_probe, 1511 .probe = adau1373_probe,
1340 .remove = adau1373_remove, 1512 .remove = adau1373_remove,
@@ -1342,9 +1514,6 @@ static struct snd_soc_codec_driver adau1373_codec_driver = {
1342 .resume = adau1373_resume, 1514 .resume = adau1373_resume,
1343 .set_bias_level = adau1373_set_bias_level, 1515 .set_bias_level = adau1373_set_bias_level,
1344 .idle_bias_off = true, 1516 .idle_bias_off = true,
1345 .reg_cache_size = ARRAY_SIZE(adau1373_default_regs),
1346 .reg_cache_default = adau1373_default_regs,
1347 .reg_word_size = sizeof(uint8_t),
1348 1517
1349 .set_pll = adau1373_set_pll, 1518 .set_pll = adau1373_set_pll,
1350 1519
@@ -1366,6 +1535,13 @@ static int adau1373_i2c_probe(struct i2c_client *client,
1366 if (!adau1373) 1535 if (!adau1373)
1367 return -ENOMEM; 1536 return -ENOMEM;
1368 1537
1538 adau1373->regmap = devm_regmap_init_i2c(client,
1539 &adau1373_regmap_config);
1540 if (IS_ERR(adau1373->regmap))
1541 return PTR_ERR(adau1373->regmap);
1542
1543 regmap_write(adau1373->regmap, ADAU1373_SOFT_RESET, 0x00);
1544
1369 dev_set_drvdata(&client->dev, adau1373); 1545 dev_set_drvdata(&client->dev, adau1373);
1370 1546
1371 ret = snd_soc_register_codec(&client->dev, &adau1373_codec_driver, 1547 ret = snd_soc_register_codec(&client->dev, &adau1373_codec_driver,
diff --git a/sound/soc/codecs/adav80x.c b/sound/soc/codecs/adav80x.c
index 15b012d0f226..14a7c169d004 100644
--- a/sound/soc/codecs/adav80x.c
+++ b/sound/soc/codecs/adav80x.c
@@ -115,22 +115,34 @@
115 115
116#define ADAV80X_PLL_OUTE_SYSCLKPD(x) BIT(2 - (x)) 116#define ADAV80X_PLL_OUTE_SYSCLKPD(x) BIT(2 - (x))
117 117
118static u8 adav80x_default_regs[] = { 118static struct reg_default adav80x_reg_defaults[] = {
119 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x02, 0x01, 0x80, 0x26, 0x00, 0x00, 119 { ADAV80X_PLAYBACK_CTRL, 0x01 },
120 0x02, 0x40, 0x20, 0x00, 0x09, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 120 { ADAV80X_AUX_IN_CTRL, 0x01 },
121 0x04, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd1, 0x92, 0xb1, 0x37, 121 { ADAV80X_REC_CTRL, 0x02 },
122 0x48, 0xd2, 0xfb, 0xca, 0xd2, 0x15, 0xe8, 0x29, 0xb9, 0x6a, 0xda, 0x2b, 122 { ADAV80X_AUX_OUT_CTRL, 0x01 },
123 0xb7, 0xc0, 0x11, 0x65, 0x5c, 0xf6, 0xff, 0x8d, 0x00, 0x00, 0x00, 0x00, 123 { ADAV80X_DPATH_CTRL1, 0xc0 },
124 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 124 { ADAV80X_DPATH_CTRL2, 0x11 },
125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa5, 0x00, 0x00, 125 { ADAV80X_DAC_CTRL1, 0x00 },
126 0x00, 0xe8, 0x46, 0xe1, 0x5b, 0xd3, 0x43, 0x77, 0x93, 0xa7, 0x44, 0xee, 126 { ADAV80X_DAC_CTRL2, 0x00 },
127 0x32, 0x12, 0xc0, 0x11, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x3f, 0x3f, 127 { ADAV80X_DAC_CTRL3, 0x00 },
128 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x1d, 0x00, 0x00, 0x00, 0x00, 128 { ADAV80X_DAC_L_VOL, 0xff },
129 0x00, 0x00, 0x00, 0x00, 0x52, 0x00, 129 { ADAV80X_DAC_R_VOL, 0xff },
130 { ADAV80X_PGA_L_VOL, 0x00 },
131 { ADAV80X_PGA_R_VOL, 0x00 },
132 { ADAV80X_ADC_CTRL1, 0x00 },
133 { ADAV80X_ADC_CTRL2, 0x00 },
134 { ADAV80X_ADC_L_VOL, 0xff },
135 { ADAV80X_ADC_R_VOL, 0xff },
136 { ADAV80X_PLL_CTRL1, 0x00 },
137 { ADAV80X_PLL_CTRL2, 0x00 },
138 { ADAV80X_ICLK_CTRL1, 0x00 },
139 { ADAV80X_ICLK_CTRL2, 0x00 },
140 { ADAV80X_PLL_CLK_SRC, 0x00 },
141 { ADAV80X_PLL_OUTE, 0x00 },
130}; 142};
131 143
132struct adav80x { 144struct adav80x {
133 enum snd_soc_control_type control_type; 145 struct regmap *regmap;
134 146
135 enum adav80x_clk_src clk_src; 147 enum adav80x_clk_src clk_src;
136 unsigned int sysclk; 148 unsigned int sysclk;
@@ -298,7 +310,7 @@ static int adav80x_set_deemph(struct snd_soc_codec *codec)
298 val = ADAV80X_DAC_CTRL2_DEEMPH_NONE; 310 val = ADAV80X_DAC_CTRL2_DEEMPH_NONE;
299 } 311 }
300 312
301 return snd_soc_update_bits(codec, ADAV80X_DAC_CTRL2, 313 return regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2,
302 ADAV80X_DAC_CTRL2_DEEMPH_MASK, val); 314 ADAV80X_DAC_CTRL2_DEEMPH_MASK, val);
303} 315}
304 316
@@ -394,10 +406,11 @@ static int adav80x_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
394 return -EINVAL; 406 return -EINVAL;
395 } 407 }
396 408
397 snd_soc_update_bits(codec, adav80x_port_ctrl_regs[dai->id][0], 409 regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0],
398 ADAV80X_CAPTURE_MODE_MASK | ADAV80X_CAPTURE_MODE_MASTER, 410 ADAV80X_CAPTURE_MODE_MASK | ADAV80X_CAPTURE_MODE_MASTER,
399 capture); 411 capture);
400 snd_soc_write(codec, adav80x_port_ctrl_regs[dai->id][1], playback); 412 regmap_write(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1],
413 playback);
401 414
402 adav80x->dai_fmt[dai->id] = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 415 adav80x->dai_fmt[dai->id] = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
403 416
@@ -407,6 +420,7 @@ static int adav80x_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
407static int adav80x_set_adc_clock(struct snd_soc_codec *codec, 420static int adav80x_set_adc_clock(struct snd_soc_codec *codec,
408 unsigned int sample_rate) 421 unsigned int sample_rate)
409{ 422{
423 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec);
410 unsigned int val; 424 unsigned int val;
411 425
412 if (sample_rate <= 48000) 426 if (sample_rate <= 48000)
@@ -414,7 +428,7 @@ static int adav80x_set_adc_clock(struct snd_soc_codec *codec,
414 else 428 else
415 val = ADAV80X_ADC_CTRL1_MODULATOR_64FS; 429 val = ADAV80X_ADC_CTRL1_MODULATOR_64FS;
416 430
417 snd_soc_update_bits(codec, ADAV80X_ADC_CTRL1, 431 regmap_update_bits(adav80x->regmap, ADAV80X_ADC_CTRL1,
418 ADAV80X_ADC_CTRL1_MODULATOR_MASK, val); 432 ADAV80X_ADC_CTRL1_MODULATOR_MASK, val);
419 433
420 return 0; 434 return 0;
@@ -423,6 +437,7 @@ static int adav80x_set_adc_clock(struct snd_soc_codec *codec,
423static int adav80x_set_dac_clock(struct snd_soc_codec *codec, 437static int adav80x_set_dac_clock(struct snd_soc_codec *codec,
424 unsigned int sample_rate) 438 unsigned int sample_rate)
425{ 439{
440 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec);
426 unsigned int val; 441 unsigned int val;
427 442
428 if (sample_rate <= 48000) 443 if (sample_rate <= 48000)
@@ -430,7 +445,7 @@ static int adav80x_set_dac_clock(struct snd_soc_codec *codec,
430 else 445 else
431 val = ADAV80X_DAC_CTRL2_DIV2 | ADAV80X_DAC_CTRL2_INTERPOL_128FS; 446 val = ADAV80X_DAC_CTRL2_DIV2 | ADAV80X_DAC_CTRL2_INTERPOL_128FS;
432 447
433 snd_soc_update_bits(codec, ADAV80X_DAC_CTRL2, 448 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL2,
434 ADAV80X_DAC_CTRL2_DIV_MASK | ADAV80X_DAC_CTRL2_INTERPOL_MASK, 449 ADAV80X_DAC_CTRL2_DIV_MASK | ADAV80X_DAC_CTRL2_INTERPOL_MASK,
435 val); 450 val);
436 451
@@ -440,6 +455,7 @@ static int adav80x_set_dac_clock(struct snd_soc_codec *codec,
440static int adav80x_set_capture_pcm_format(struct snd_soc_codec *codec, 455static int adav80x_set_capture_pcm_format(struct snd_soc_codec *codec,
441 struct snd_soc_dai *dai, snd_pcm_format_t format) 456 struct snd_soc_dai *dai, snd_pcm_format_t format)
442{ 457{
458 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec);
443 unsigned int val; 459 unsigned int val;
444 460
445 switch (format) { 461 switch (format) {
@@ -459,7 +475,7 @@ static int adav80x_set_capture_pcm_format(struct snd_soc_codec *codec,
459 return -EINVAL; 475 return -EINVAL;
460 } 476 }
461 477
462 snd_soc_update_bits(codec, adav80x_port_ctrl_regs[dai->id][0], 478 regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][0],
463 ADAV80X_CAPTURE_WORD_LEN_MASK, val); 479 ADAV80X_CAPTURE_WORD_LEN_MASK, val);
464 480
465 return 0; 481 return 0;
@@ -491,7 +507,7 @@ static int adav80x_set_playback_pcm_format(struct snd_soc_codec *codec,
491 return -EINVAL; 507 return -EINVAL;
492 } 508 }
493 509
494 snd_soc_update_bits(codec, adav80x_port_ctrl_regs[dai->id][1], 510 regmap_update_bits(adav80x->regmap, adav80x_port_ctrl_regs[dai->id][1],
495 ADAV80X_PLAYBACK_MODE_MASK, val); 511 ADAV80X_PLAYBACK_MODE_MASK, val);
496 512
497 return 0; 513 return 0;
@@ -554,8 +570,10 @@ static int adav80x_set_sysclk(struct snd_soc_codec *codec,
554 ADAV80X_ICLK_CTRL1_ICLK2_SRC(clk_id); 570 ADAV80X_ICLK_CTRL1_ICLK2_SRC(clk_id);
555 iclk_ctrl2 = ADAV80X_ICLK_CTRL2_ICLK1_SRC(clk_id); 571 iclk_ctrl2 = ADAV80X_ICLK_CTRL2_ICLK1_SRC(clk_id);
556 572
557 snd_soc_write(codec, ADAV80X_ICLK_CTRL1, iclk_ctrl1); 573 regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL1,
558 snd_soc_write(codec, ADAV80X_ICLK_CTRL2, iclk_ctrl2); 574 iclk_ctrl1);
575 regmap_write(adav80x->regmap, ADAV80X_ICLK_CTRL2,
576 iclk_ctrl2);
559 577
560 snd_soc_dapm_sync(&codec->dapm); 578 snd_soc_dapm_sync(&codec->dapm);
561 } 579 }
@@ -575,10 +593,12 @@ static int adav80x_set_sysclk(struct snd_soc_codec *codec,
575 mask = ADAV80X_PLL_OUTE_SYSCLKPD(clk_id); 593 mask = ADAV80X_PLL_OUTE_SYSCLKPD(clk_id);
576 594
577 if (freq == 0) { 595 if (freq == 0) {
578 snd_soc_update_bits(codec, ADAV80X_PLL_OUTE, mask, mask); 596 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE,
597 mask, mask);
579 adav80x->sysclk_pd[clk_id] = true; 598 adav80x->sysclk_pd[clk_id] = true;
580 } else { 599 } else {
581 snd_soc_update_bits(codec, ADAV80X_PLL_OUTE, mask, 0); 600 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_OUTE,
601 mask, 0);
582 adav80x->sysclk_pd[clk_id] = false; 602 adav80x->sysclk_pd[clk_id] = false;
583 } 603 }
584 604
@@ -650,9 +670,9 @@ static int adav80x_set_pll(struct snd_soc_codec *codec, int pll_id,
650 return -EINVAL; 670 return -EINVAL;
651 } 671 }
652 672
653 snd_soc_update_bits(codec, ADAV80X_PLL_CTRL1, ADAV80X_PLL_CTRL1_PLLDIV, 673 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL1,
654 pll_ctrl1); 674 ADAV80X_PLL_CTRL1_PLLDIV, pll_ctrl1);
655 snd_soc_update_bits(codec, ADAV80X_PLL_CTRL2, 675 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CTRL2,
656 ADAV80X_PLL_CTRL2_PLL_MASK(pll_id), pll_ctrl2); 676 ADAV80X_PLL_CTRL2_PLL_MASK(pll_id), pll_ctrl2);
657 677
658 if (source != adav80x->pll_src) { 678 if (source != adav80x->pll_src) {
@@ -661,7 +681,7 @@ static int adav80x_set_pll(struct snd_soc_codec *codec, int pll_id,
661 else 681 else
662 pll_src = ADAV80X_PLL_CLK_SRC_PLL_XIN(pll_id); 682 pll_src = ADAV80X_PLL_CLK_SRC_PLL_XIN(pll_id);
663 683
664 snd_soc_update_bits(codec, ADAV80X_PLL_CLK_SRC, 684 regmap_update_bits(adav80x->regmap, ADAV80X_PLL_CLK_SRC,
665 ADAV80X_PLL_CLK_SRC_PLL_MASK(pll_id), pll_src); 685 ADAV80X_PLL_CLK_SRC_PLL_MASK(pll_id), pll_src);
666 686
667 adav80x->pll_src = source; 687 adav80x->pll_src = source;
@@ -675,6 +695,7 @@ static int adav80x_set_pll(struct snd_soc_codec *codec, int pll_id,
675static int adav80x_set_bias_level(struct snd_soc_codec *codec, 695static int adav80x_set_bias_level(struct snd_soc_codec *codec,
676 enum snd_soc_bias_level level) 696 enum snd_soc_bias_level level)
677{ 697{
698 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec);
678 unsigned int mask = ADAV80X_DAC_CTRL1_PD; 699 unsigned int mask = ADAV80X_DAC_CTRL1_PD;
679 700
680 switch (level) { 701 switch (level) {
@@ -683,10 +704,12 @@ static int adav80x_set_bias_level(struct snd_soc_codec *codec,
683 case SND_SOC_BIAS_PREPARE: 704 case SND_SOC_BIAS_PREPARE:
684 break; 705 break;
685 case SND_SOC_BIAS_STANDBY: 706 case SND_SOC_BIAS_STANDBY:
686 snd_soc_update_bits(codec, ADAV80X_DAC_CTRL1, mask, 0x00); 707 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask,
708 0x00);
687 break; 709 break;
688 case SND_SOC_BIAS_OFF: 710 case SND_SOC_BIAS_OFF:
689 snd_soc_update_bits(codec, ADAV80X_DAC_CTRL1, mask, mask); 711 regmap_update_bits(adav80x->regmap, ADAV80X_DAC_CTRL1, mask,
712 mask);
690 break; 713 break;
691 } 714 }
692 715
@@ -780,7 +803,7 @@ static int adav80x_probe(struct snd_soc_codec *codec)
780 int ret; 803 int ret;
781 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec); 804 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec);
782 805
783 ret = snd_soc_codec_set_cache_io(codec, 7, 9, adav80x->control_type); 806 ret = snd_soc_codec_set_cache_io(codec, 0, 0, SND_SOC_REGMAP);
784 if (ret) { 807 if (ret) {
785 dev_err(codec->dev, "failed to set cache I/O: %d\n", ret); 808 dev_err(codec->dev, "failed to set cache I/O: %d\n", ret);
786 return ret; 809 return ret;
@@ -791,23 +814,31 @@ static int adav80x_probe(struct snd_soc_codec *codec)
791 snd_soc_dapm_force_enable_pin(&codec->dapm, "PLL2"); 814 snd_soc_dapm_force_enable_pin(&codec->dapm, "PLL2");
792 815
793 /* Power down S/PDIF receiver, since it is currently not supported */ 816 /* Power down S/PDIF receiver, since it is currently not supported */
794 snd_soc_write(codec, ADAV80X_PLL_OUTE, 0x20); 817 regmap_write(adav80x->regmap, ADAV80X_PLL_OUTE, 0x20);
795 /* Disable DAC zero flag */ 818 /* Disable DAC zero flag */
796 snd_soc_write(codec, ADAV80X_DAC_CTRL3, 0x6); 819 regmap_write(adav80x->regmap, ADAV80X_DAC_CTRL3, 0x6);
797 820
798 return adav80x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 821 return adav80x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
799} 822}
800 823
801static int adav80x_suspend(struct snd_soc_codec *codec) 824static int adav80x_suspend(struct snd_soc_codec *codec)
802{ 825{
803 return adav80x_set_bias_level(codec, SND_SOC_BIAS_OFF); 826 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec);
827 int ret;
828
829 ret = adav80x_set_bias_level(codec, SND_SOC_BIAS_OFF);
830 regcache_cache_only(adav80x->regmap, true);
831
832 return ret;
804} 833}
805 834
806static int adav80x_resume(struct snd_soc_codec *codec) 835static int adav80x_resume(struct snd_soc_codec *codec)
807{ 836{
837 struct adav80x *adav80x = snd_soc_codec_get_drvdata(codec);
838
839 regcache_cache_only(adav80x->regmap, false);
808 adav80x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 840 adav80x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
809 codec->cache_sync = 1; 841 regcache_sync(adav80x->regmap);
810 snd_soc_cache_sync(codec);
811 842
812 return 0; 843 return 0;
813} 844}
@@ -827,10 +858,6 @@ static struct snd_soc_codec_driver adav80x_codec_driver = {
827 .set_pll = adav80x_set_pll, 858 .set_pll = adav80x_set_pll,
828 .set_sysclk = adav80x_set_sysclk, 859 .set_sysclk = adav80x_set_sysclk,
829 860
830 .reg_word_size = sizeof(u8),
831 .reg_cache_size = ARRAY_SIZE(adav80x_default_regs),
832 .reg_cache_default = adav80x_default_regs,
833
834 .controls = adav80x_controls, 861 .controls = adav80x_controls,
835 .num_controls = ARRAY_SIZE(adav80x_controls), 862 .num_controls = ARRAY_SIZE(adav80x_controls),
836 .dapm_widgets = adav80x_dapm_widgets, 863 .dapm_widgets = adav80x_dapm_widgets,
@@ -839,18 +866,21 @@ static struct snd_soc_codec_driver adav80x_codec_driver = {
839 .num_dapm_routes = ARRAY_SIZE(adav80x_dapm_routes), 866 .num_dapm_routes = ARRAY_SIZE(adav80x_dapm_routes),
840}; 867};
841 868
842static int adav80x_bus_probe(struct device *dev, 869static int adav80x_bus_probe(struct device *dev, struct regmap *regmap)
843 enum snd_soc_control_type control_type)
844{ 870{
845 struct adav80x *adav80x; 871 struct adav80x *adav80x;
846 int ret; 872 int ret;
847 873
874 if (IS_ERR(regmap))
875 return PTR_ERR(regmap);
876
848 adav80x = kzalloc(sizeof(*adav80x), GFP_KERNEL); 877 adav80x = kzalloc(sizeof(*adav80x), GFP_KERNEL);
849 if (!adav80x) 878 if (!adav80x)
850 return -ENOMEM; 879 return -ENOMEM;
851 880
881
852 dev_set_drvdata(dev, adav80x); 882 dev_set_drvdata(dev, adav80x);
853 adav80x->control_type = control_type; 883 adav80x->regmap = regmap;
854 884
855 ret = snd_soc_register_codec(dev, &adav80x_codec_driver, 885 ret = snd_soc_register_codec(dev, &adav80x_codec_driver,
856 adav80x_dais, ARRAY_SIZE(adav80x_dais)); 886 adav80x_dais, ARRAY_SIZE(adav80x_dais));
@@ -868,6 +898,19 @@ static int adav80x_bus_remove(struct device *dev)
868} 898}
869 899
870#if defined(CONFIG_SPI_MASTER) 900#if defined(CONFIG_SPI_MASTER)
901static const struct regmap_config adav80x_spi_regmap_config = {
902 .val_bits = 8,
903 .pad_bits = 1,
904 .reg_bits = 7,
905 .read_flag_mask = 0x01,
906
907 .max_register = ADAV80X_PLL_OUTE,
908
909 .cache_type = REGCACHE_RBTREE,
910 .reg_defaults = adav80x_reg_defaults,
911 .num_reg_defaults = ARRAY_SIZE(adav80x_reg_defaults),
912};
913
871static const struct spi_device_id adav80x_spi_id[] = { 914static const struct spi_device_id adav80x_spi_id[] = {
872 { "adav801", 0 }, 915 { "adav801", 0 },
873 { } 916 { }
@@ -876,7 +919,8 @@ MODULE_DEVICE_TABLE(spi, adav80x_spi_id);
876 919
877static int adav80x_spi_probe(struct spi_device *spi) 920static int adav80x_spi_probe(struct spi_device *spi)
878{ 921{
879 return adav80x_bus_probe(&spi->dev, SND_SOC_SPI); 922 return adav80x_bus_probe(&spi->dev,
923 devm_regmap_init_spi(spi, &adav80x_spi_regmap_config));
880} 924}
881 925
882static int adav80x_spi_remove(struct spi_device *spi) 926static int adav80x_spi_remove(struct spi_device *spi)
@@ -896,6 +940,18 @@ static struct spi_driver adav80x_spi_driver = {
896#endif 940#endif
897 941
898#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 942#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
943static const struct regmap_config adav80x_i2c_regmap_config = {
944 .val_bits = 8,
945 .pad_bits = 1,
946 .reg_bits = 7,
947
948 .max_register = ADAV80X_PLL_OUTE,
949
950 .cache_type = REGCACHE_RBTREE,
951 .reg_defaults = adav80x_reg_defaults,
952 .num_reg_defaults = ARRAY_SIZE(adav80x_reg_defaults),
953};
954
899static const struct i2c_device_id adav80x_i2c_id[] = { 955static const struct i2c_device_id adav80x_i2c_id[] = {
900 { "adav803", 0 }, 956 { "adav803", 0 },
901 { } 957 { }
@@ -905,7 +961,8 @@ MODULE_DEVICE_TABLE(i2c, adav80x_i2c_id);
905static int adav80x_i2c_probe(struct i2c_client *client, 961static int adav80x_i2c_probe(struct i2c_client *client,
906 const struct i2c_device_id *id) 962 const struct i2c_device_id *id)
907{ 963{
908 return adav80x_bus_probe(&client->dev, SND_SOC_I2C); 964 return adav80x_bus_probe(&client->dev,
965 devm_regmap_init_i2c(client, &adav80x_i2c_regmap_config));
909} 966}
910 967
911static int adav80x_i2c_remove(struct i2c_client *client) 968static int adav80x_i2c_remove(struct i2c_client *client)
diff --git a/sound/soc/codecs/ak4104.c b/sound/soc/codecs/ak4104.c
index 71059c07ae7b..b4819dcd4f4d 100644
--- a/sound/soc/codecs/ak4104.c
+++ b/sound/soc/codecs/ak4104.c
@@ -45,8 +45,6 @@
45#define AK4104_TX_TXE (1 << 0) 45#define AK4104_TX_TXE (1 << 0)
46#define AK4104_TX_V (1 << 1) 46#define AK4104_TX_V (1 << 1)
47 47
48#define DRV_NAME "ak4104-codec"
49
50struct ak4104_private { 48struct ak4104_private {
51 struct regmap *regmap; 49 struct regmap *regmap;
52}; 50};
@@ -291,12 +289,19 @@ static const struct of_device_id ak4104_of_match[] = {
291}; 289};
292MODULE_DEVICE_TABLE(of, ak4104_of_match); 290MODULE_DEVICE_TABLE(of, ak4104_of_match);
293 291
292static const struct spi_device_id ak4104_id_table[] = {
293 { "ak4104", 0 },
294 { }
295};
296MODULE_DEVICE_TABLE(spi, ak4104_id_table);
297
294static struct spi_driver ak4104_spi_driver = { 298static struct spi_driver ak4104_spi_driver = {
295 .driver = { 299 .driver = {
296 .name = DRV_NAME, 300 .name = "ak4104",
297 .owner = THIS_MODULE, 301 .owner = THIS_MODULE,
298 .of_match_table = ak4104_of_match, 302 .of_match_table = ak4104_of_match,
299 }, 303 },
304 .id_table = ak4104_id_table,
300 .probe = ak4104_spi_probe, 305 .probe = ak4104_spi_probe,
301 .remove = ak4104_spi_remove, 306 .remove = ak4104_spi_remove,
302}; 307};
diff --git a/sound/soc/codecs/ak4642.c b/sound/soc/codecs/ak4642.c
index 2d0378709702..090d499bb7eb 100644
--- a/sound/soc/codecs/ak4642.c
+++ b/sound/soc/codecs/ak4642.c
@@ -257,7 +257,7 @@ static int ak4642_dai_startup(struct snd_pcm_substream *substream,
257 * This operation came from example code of 257 * This operation came from example code of
258 * "ASAHI KASEI AK4642" (japanese) manual p94. 258 * "ASAHI KASEI AK4642" (japanese) manual p94.
259 */ 259 */
260 snd_soc_write(codec, SG_SL1, PMMP | MGAIN0); 260 snd_soc_update_bits(codec, SG_SL1, PMMP | MGAIN0, PMMP | MGAIN0);
261 snd_soc_write(codec, TIMER, ZTM(0x3) | WTM(0x3)); 261 snd_soc_write(codec, TIMER, ZTM(0x3) | WTM(0x3));
262 snd_soc_write(codec, ALC_CTL1, ALC | LMTH0); 262 snd_soc_write(codec, ALC_CTL1, ALC | LMTH0);
263 snd_soc_update_bits(codec, PW_MGMT1, PMADL, PMADL); 263 snd_soc_update_bits(codec, PW_MGMT1, PMADL, PMADL);
@@ -352,7 +352,6 @@ static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
352 */ 352 */
353 default: 353 default:
354 return -EINVAL; 354 return -EINVAL;
355 break;
356 } 355 }
357 snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data); 356 snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);
358 357
@@ -405,7 +404,6 @@ static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
405 break; 404 break;
406 default: 405 default:
407 return -EINVAL; 406 return -EINVAL;
408 break;
409 } 407 }
410 snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate); 408 snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);
411 409
diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c
index 657808ba1418..6f05b17d1965 100644
--- a/sound/soc/codecs/arizona.c
+++ b/sound/soc/codecs/arizona.c
@@ -1477,21 +1477,25 @@ static void arizona_enable_fll(struct arizona_fll *fll,
1477{ 1477{
1478 struct arizona *arizona = fll->arizona; 1478 struct arizona *arizona = fll->arizona;
1479 int ret; 1479 int ret;
1480 bool use_sync = false;
1480 1481
1481 /* 1482 /*
1482 * If we have both REFCLK and SYNCCLK then enable both, 1483 * If we have both REFCLK and SYNCCLK then enable both,
1483 * otherwise apply the SYNCCLK settings to REFCLK. 1484 * otherwise apply the SYNCCLK settings to REFCLK.
1484 */ 1485 */
1485 if (fll->ref_src >= 0 && fll->ref_src != fll->sync_src) { 1486 if (fll->ref_src >= 0 && fll->ref_freq &&
1487 fll->ref_src != fll->sync_src) {
1486 regmap_update_bits(arizona->regmap, fll->base + 5, 1488 regmap_update_bits(arizona->regmap, fll->base + 5,
1487 ARIZONA_FLL1_OUTDIV_MASK, 1489 ARIZONA_FLL1_OUTDIV_MASK,
1488 ref->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT); 1490 ref->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
1489 1491
1490 arizona_apply_fll(arizona, fll->base, ref, fll->ref_src, 1492 arizona_apply_fll(arizona, fll->base, ref, fll->ref_src,
1491 false); 1493 false);
1492 if (fll->sync_src >= 0) 1494 if (fll->sync_src >= 0) {
1493 arizona_apply_fll(arizona, fll->base + 0x10, sync, 1495 arizona_apply_fll(arizona, fll->base + 0x10, sync,
1494 fll->sync_src, true); 1496 fll->sync_src, true);
1497 use_sync = true;
1498 }
1495 } else if (fll->sync_src >= 0) { 1499 } else if (fll->sync_src >= 0) {
1496 regmap_update_bits(arizona->regmap, fll->base + 5, 1500 regmap_update_bits(arizona->regmap, fll->base + 5,
1497 ARIZONA_FLL1_OUTDIV_MASK, 1501 ARIZONA_FLL1_OUTDIV_MASK,
@@ -1511,7 +1515,7 @@ static void arizona_enable_fll(struct arizona_fll *fll,
1511 * Increase the bandwidth if we're not using a low frequency 1515 * Increase the bandwidth if we're not using a low frequency
1512 * sync source. 1516 * sync source.
1513 */ 1517 */
1514 if (fll->sync_src >= 0 && fll->sync_freq > 100000) 1518 if (use_sync && fll->sync_freq > 100000)
1515 regmap_update_bits(arizona->regmap, fll->base + 0x17, 1519 regmap_update_bits(arizona->regmap, fll->base + 0x17,
1516 ARIZONA_FLL1_SYNC_BW, 0); 1520 ARIZONA_FLL1_SYNC_BW, 0);
1517 else 1521 else
@@ -1526,8 +1530,7 @@ static void arizona_enable_fll(struct arizona_fll *fll,
1526 1530
1527 regmap_update_bits(arizona->regmap, fll->base + 1, 1531 regmap_update_bits(arizona->regmap, fll->base + 1,
1528 ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA); 1532 ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
1529 if (fll->ref_src >= 0 && fll->sync_src >= 0 && 1533 if (use_sync)
1530 fll->ref_src != fll->sync_src)
1531 regmap_update_bits(arizona->regmap, fll->base + 0x11, 1534 regmap_update_bits(arizona->regmap, fll->base + 0x11,
1532 ARIZONA_FLL1_SYNC_ENA, 1535 ARIZONA_FLL1_SYNC_ENA,
1533 ARIZONA_FLL1_SYNC_ENA); 1536 ARIZONA_FLL1_SYNC_ENA);
@@ -1561,10 +1564,12 @@ int arizona_set_fll_refclk(struct arizona_fll *fll, int source,
1561 if (fll->ref_src == source && fll->ref_freq == Fref) 1564 if (fll->ref_src == source && fll->ref_freq == Fref)
1562 return 0; 1565 return 0;
1563 1566
1564 if (fll->fout && Fref > 0) { 1567 if (fll->fout) {
1565 ret = arizona_calc_fll(fll, &ref, Fref, fll->fout); 1568 if (Fref > 0) {
1566 if (ret != 0) 1569 ret = arizona_calc_fll(fll, &ref, Fref, fll->fout);
1567 return ret; 1570 if (ret != 0)
1571 return ret;
1572 }
1568 1573
1569 if (fll->sync_src >= 0) { 1574 if (fll->sync_src >= 0) {
1570 ret = arizona_calc_fll(fll, &sync, fll->sync_freq, 1575 ret = arizona_calc_fll(fll, &sync, fll->sync_freq,
diff --git a/sound/soc/codecs/cq93vc.c b/sound/soc/codecs/cq93vc.c
index 23316c887b19..43737a27d79c 100644
--- a/sound/soc/codecs/cq93vc.c
+++ b/sound/soc/codecs/cq93vc.c
@@ -38,24 +38,6 @@
38#include <sound/soc.h> 38#include <sound/soc.h>
39#include <sound/initval.h> 39#include <sound/initval.h>
40 40
41static inline unsigned int cq93vc_read(struct snd_soc_codec *codec,
42 unsigned int reg)
43{
44 struct davinci_vc *davinci_vc = codec->control_data;
45
46 return readl(davinci_vc->base + reg);
47}
48
49static inline int cq93vc_write(struct snd_soc_codec *codec, unsigned int reg,
50 unsigned int value)
51{
52 struct davinci_vc *davinci_vc = codec->control_data;
53
54 writel(value, davinci_vc->base + reg);
55
56 return 0;
57}
58
59static const struct snd_kcontrol_new cq93vc_snd_controls[] = { 41static const struct snd_kcontrol_new cq93vc_snd_controls[] = {
60 SOC_SINGLE("PGA Capture Volume", DAVINCI_VC_REG05, 0, 0x03, 0), 42 SOC_SINGLE("PGA Capture Volume", DAVINCI_VC_REG05, 0, 0x03, 0),
61 SOC_SINGLE("Mono DAC Playback Volume", DAVINCI_VC_REG09, 0, 0x3f, 0), 43 SOC_SINGLE("Mono DAC Playback Volume", DAVINCI_VC_REG09, 0, 0x3f, 0),
@@ -64,13 +46,15 @@ static const struct snd_kcontrol_new cq93vc_snd_controls[] = {
64static int cq93vc_mute(struct snd_soc_dai *dai, int mute) 46static int cq93vc_mute(struct snd_soc_dai *dai, int mute)
65{ 47{
66 struct snd_soc_codec *codec = dai->codec; 48 struct snd_soc_codec *codec = dai->codec;
67 u8 reg = cq93vc_read(codec, DAVINCI_VC_REG09) & ~DAVINCI_VC_REG09_MUTE; 49 u8 reg;
68 50
69 if (mute) 51 if (mute)
70 cq93vc_write(codec, DAVINCI_VC_REG09, 52 reg = DAVINCI_VC_REG09_MUTE;
71 reg | DAVINCI_VC_REG09_MUTE);
72 else 53 else
73 cq93vc_write(codec, DAVINCI_VC_REG09, reg); 54 reg = 0;
55
56 snd_soc_update_bits(codec, DAVINCI_VC_REG09, DAVINCI_VC_REG09_MUTE,
57 reg);
74 58
75 return 0; 59 return 0;
76} 60}
@@ -79,7 +63,7 @@ static int cq93vc_set_dai_sysclk(struct snd_soc_dai *codec_dai,
79 int clk_id, unsigned int freq, int dir) 63 int clk_id, unsigned int freq, int dir)
80{ 64{
81 struct snd_soc_codec *codec = codec_dai->codec; 65 struct snd_soc_codec *codec = codec_dai->codec;
82 struct davinci_vc *davinci_vc = codec->control_data; 66 struct davinci_vc *davinci_vc = codec->dev->platform_data;
83 67
84 switch (freq) { 68 switch (freq) {
85 case 22579200: 69 case 22579200:
@@ -97,18 +81,18 @@ static int cq93vc_set_bias_level(struct snd_soc_codec *codec,
97{ 81{
98 switch (level) { 82 switch (level) {
99 case SND_SOC_BIAS_ON: 83 case SND_SOC_BIAS_ON:
100 cq93vc_write(codec, DAVINCI_VC_REG12, 84 snd_soc_write(codec, DAVINCI_VC_REG12,
101 DAVINCI_VC_REG12_POWER_ALL_ON); 85 DAVINCI_VC_REG12_POWER_ALL_ON);
102 break; 86 break;
103 case SND_SOC_BIAS_PREPARE: 87 case SND_SOC_BIAS_PREPARE:
104 break; 88 break;
105 case SND_SOC_BIAS_STANDBY: 89 case SND_SOC_BIAS_STANDBY:
106 cq93vc_write(codec, DAVINCI_VC_REG12, 90 snd_soc_write(codec, DAVINCI_VC_REG12,
107 DAVINCI_VC_REG12_POWER_ALL_OFF); 91 DAVINCI_VC_REG12_POWER_ALL_OFF);
108 break; 92 break;
109 case SND_SOC_BIAS_OFF: 93 case SND_SOC_BIAS_OFF:
110 /* force all power off */ 94 /* force all power off */
111 cq93vc_write(codec, DAVINCI_VC_REG12, 95 snd_soc_write(codec, DAVINCI_VC_REG12,
112 DAVINCI_VC_REG12_POWER_ALL_OFF); 96 DAVINCI_VC_REG12_POWER_ALL_OFF);
113 break; 97 break;
114 } 98 }
@@ -154,11 +138,9 @@ static int cq93vc_probe(struct snd_soc_codec *codec)
154 struct davinci_vc *davinci_vc = codec->dev->platform_data; 138 struct davinci_vc *davinci_vc = codec->dev->platform_data;
155 139
156 davinci_vc->cq93vc.codec = codec; 140 davinci_vc->cq93vc.codec = codec;
157 codec->control_data = davinci_vc; 141 codec->control_data = davinci_vc->regmap;
158 142
159 /* Set controls */ 143 snd_soc_codec_set_cache_io(codec, 32, 32, SND_SOC_REGMAP);
160 snd_soc_add_codec_controls(codec, cq93vc_snd_controls,
161 ARRAY_SIZE(cq93vc_snd_controls));
162 144
163 /* Off, with power on */ 145 /* Off, with power on */
164 cq93vc_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 146 cq93vc_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
@@ -174,12 +156,12 @@ static int cq93vc_remove(struct snd_soc_codec *codec)
174} 156}
175 157
176static struct snd_soc_codec_driver soc_codec_dev_cq93vc = { 158static struct snd_soc_codec_driver soc_codec_dev_cq93vc = {
177 .read = cq93vc_read,
178 .write = cq93vc_write,
179 .set_bias_level = cq93vc_set_bias_level, 159 .set_bias_level = cq93vc_set_bias_level,
180 .probe = cq93vc_probe, 160 .probe = cq93vc_probe,
181 .remove = cq93vc_remove, 161 .remove = cq93vc_remove,
182 .resume = cq93vc_resume, 162 .resume = cq93vc_resume,
163 .controls = cq93vc_snd_controls,
164 .num_controls = ARRAY_SIZE(cq93vc_snd_controls),
183}; 165};
184 166
185static int cq93vc_platform_probe(struct platform_device *pdev) 167static int cq93vc_platform_probe(struct platform_device *pdev)
diff --git a/sound/soc/codecs/cs4271.c b/sound/soc/codecs/cs4271.c
index a20f1bb8f071..f6e953454bc0 100644
--- a/sound/soc/codecs/cs4271.c
+++ b/sound/soc/codecs/cs4271.c
@@ -25,6 +25,7 @@
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <linux/i2c.h> 26#include <linux/i2c.h>
27#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
28#include <linux/of.h>
28#include <linux/of_device.h> 29#include <linux/of_device.h>
29#include <linux/of_gpio.h> 30#include <linux/of_gpio.h>
30#include <sound/pcm.h> 31#include <sound/pcm.h>
diff --git a/sound/soc/codecs/cs42l52.c b/sound/soc/codecs/cs42l52.c
index be2ba1b6fe4a..8b427c977083 100644
--- a/sound/soc/codecs/cs42l52.c
+++ b/sound/soc/codecs/cs42l52.c
@@ -17,6 +17,7 @@
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/delay.h> 19#include <linux/delay.h>
20#include <linux/gpio.h>
20#include <linux/pm.h> 21#include <linux/pm.h>
21#include <linux/i2c.h> 22#include <linux/i2c.h>
22#include <linux/input.h> 23#include <linux/input.h>
@@ -1116,40 +1117,6 @@ static int cs42l52_probe(struct snd_soc_codec *codec)
1116 cs42l52->sysclk = CS42L52_DEFAULT_CLK; 1117 cs42l52->sysclk = CS42L52_DEFAULT_CLK;
1117 cs42l52->config.format = CS42L52_DEFAULT_FORMAT; 1118 cs42l52->config.format = CS42L52_DEFAULT_FORMAT;
1118 1119
1119 /* Set Platform MICx CFG */
1120 snd_soc_update_bits(codec, CS42L52_MICA_CTL,
1121 CS42L52_MIC_CTL_TYPE_MASK,
1122 cs42l52->pdata.mica_cfg <<
1123 CS42L52_MIC_CTL_TYPE_SHIFT);
1124
1125 snd_soc_update_bits(codec, CS42L52_MICB_CTL,
1126 CS42L52_MIC_CTL_TYPE_MASK,
1127 cs42l52->pdata.micb_cfg <<
1128 CS42L52_MIC_CTL_TYPE_SHIFT);
1129
1130 /* if Single Ended, Get Mic_Select */
1131 if (cs42l52->pdata.mica_cfg)
1132 snd_soc_update_bits(codec, CS42L52_MICA_CTL,
1133 CS42L52_MIC_CTL_MIC_SEL_MASK,
1134 cs42l52->pdata.mica_sel <<
1135 CS42L52_MIC_CTL_MIC_SEL_SHIFT);
1136 if (cs42l52->pdata.micb_cfg)
1137 snd_soc_update_bits(codec, CS42L52_MICB_CTL,
1138 CS42L52_MIC_CTL_MIC_SEL_MASK,
1139 cs42l52->pdata.micb_sel <<
1140 CS42L52_MIC_CTL_MIC_SEL_SHIFT);
1141
1142 /* Set Platform Charge Pump Freq */
1143 snd_soc_update_bits(codec, CS42L52_CHARGE_PUMP,
1144 CS42L52_CHARGE_PUMP_MASK,
1145 cs42l52->pdata.chgfreq <<
1146 CS42L52_CHARGE_PUMP_SHIFT);
1147
1148 /* Set Platform Bias Level */
1149 snd_soc_update_bits(codec, CS42L52_IFACE_CTL2,
1150 CS42L52_IFACE_CTL2_BIAS_LVL,
1151 cs42l52->pdata.micbias_lvl);
1152
1153 return ret; 1120 return ret;
1154} 1121}
1155 1122
@@ -1205,6 +1172,7 @@ static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1205 const struct i2c_device_id *id) 1172 const struct i2c_device_id *id)
1206{ 1173{
1207 struct cs42l52_private *cs42l52; 1174 struct cs42l52_private *cs42l52;
1175 struct cs42l52_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
1208 int ret; 1176 int ret;
1209 unsigned int devid = 0; 1177 unsigned int devid = 0;
1210 unsigned int reg; 1178 unsigned int reg;
@@ -1222,11 +1190,22 @@ static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1222 return ret; 1190 return ret;
1223 } 1191 }
1224 1192
1225 i2c_set_clientdata(i2c_client, cs42l52); 1193 if (pdata)
1194 cs42l52->pdata = *pdata;
1195
1196 if (cs42l52->pdata.reset_gpio) {
1197 ret = gpio_request_one(cs42l52->pdata.reset_gpio,
1198 GPIOF_OUT_INIT_HIGH, "CS42L52 /RST");
1199 if (ret < 0) {
1200 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1201 cs42l52->pdata.reset_gpio, ret);
1202 return ret;
1203 }
1204 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 0);
1205 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 1);
1206 }
1226 1207
1227 if (dev_get_platdata(&i2c_client->dev)) 1208 i2c_set_clientdata(i2c_client, cs42l52);
1228 memcpy(&cs42l52->pdata, dev_get_platdata(&i2c_client->dev),
1229 sizeof(cs42l52->pdata));
1230 1209
1231 ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch, 1210 ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch,
1232 ARRAY_SIZE(cs42l52_threshold_patch)); 1211 ARRAY_SIZE(cs42l52_threshold_patch));
@@ -1244,7 +1223,43 @@ static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1244 return ret; 1223 return ret;
1245 } 1224 }
1246 1225
1247 regcache_cache_only(cs42l52->regmap, true); 1226 dev_info(&i2c_client->dev, "Cirrus Logic CS42L52, Revision: %02X\n",
1227 reg & 0xFF);
1228
1229 /* Set Platform Data */
1230 if (cs42l52->pdata.mica_cfg)
1231 regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL,
1232 CS42L52_MIC_CTL_TYPE_MASK,
1233 cs42l52->pdata.mica_cfg <<
1234 CS42L52_MIC_CTL_TYPE_SHIFT);
1235
1236 if (cs42l52->pdata.micb_cfg)
1237 regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL,
1238 CS42L52_MIC_CTL_TYPE_MASK,
1239 cs42l52->pdata.micb_cfg <<
1240 CS42L52_MIC_CTL_TYPE_SHIFT);
1241
1242 if (cs42l52->pdata.mica_sel)
1243 regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL,
1244 CS42L52_MIC_CTL_MIC_SEL_MASK,
1245 cs42l52->pdata.mica_sel <<
1246 CS42L52_MIC_CTL_MIC_SEL_SHIFT);
1247 if (cs42l52->pdata.micb_sel)
1248 regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL,
1249 CS42L52_MIC_CTL_MIC_SEL_MASK,
1250 cs42l52->pdata.micb_sel <<
1251 CS42L52_MIC_CTL_MIC_SEL_SHIFT);
1252
1253 if (cs42l52->pdata.chgfreq)
1254 regmap_update_bits(cs42l52->regmap, CS42L52_CHARGE_PUMP,
1255 CS42L52_CHARGE_PUMP_MASK,
1256 cs42l52->pdata.chgfreq <<
1257 CS42L52_CHARGE_PUMP_SHIFT);
1258
1259 if (cs42l52->pdata.micbias_lvl)
1260 regmap_update_bits(cs42l52->regmap, CS42L52_IFACE_CTL2,
1261 CS42L52_IFACE_CTL2_BIAS_LVL,
1262 cs42l52->pdata.micbias_lvl);
1248 1263
1249 ret = snd_soc_register_codec(&i2c_client->dev, 1264 ret = snd_soc_register_codec(&i2c_client->dev,
1250 &soc_codec_dev_cs42l52, &cs42l52_dai, 1); 1265 &soc_codec_dev_cs42l52, &cs42l52_dai, 1);
diff --git a/sound/soc/codecs/cs42l52.h b/sound/soc/codecs/cs42l52.h
index 4277012c4719..1a9412d86d17 100644
--- a/sound/soc/codecs/cs42l52.h
+++ b/sound/soc/codecs/cs42l52.h
@@ -269,6 +269,6 @@
269#define CS42L52_FIX_BITS1 0x3E 269#define CS42L52_FIX_BITS1 0x3E
270#define CS42L52_FIX_BITS2 0x47 270#define CS42L52_FIX_BITS2 0x47
271 271
272#define CS42L52_MAX_REGISTER 0x34 272#define CS42L52_MAX_REGISTER 0x47
273 273
274#endif 274#endif
diff --git a/sound/soc/codecs/cs42l73.c b/sound/soc/codecs/cs42l73.c
index 3b20c86cdb01..549d5d6a3fef 100644
--- a/sound/soc/codecs/cs42l73.c
+++ b/sound/soc/codecs/cs42l73.c
@@ -17,6 +17,7 @@
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/delay.h> 19#include <linux/delay.h>
20#include <linux/of_gpio.h>
20#include <linux/pm.h> 21#include <linux/pm.h>
21#include <linux/i2c.h> 22#include <linux/i2c.h>
22#include <linux/regmap.h> 23#include <linux/regmap.h>
@@ -28,6 +29,7 @@
28#include <sound/soc-dapm.h> 29#include <sound/soc-dapm.h>
29#include <sound/initval.h> 30#include <sound/initval.h>
30#include <sound/tlv.h> 31#include <sound/tlv.h>
32#include <sound/cs42l73.h>
31#include "cs42l73.h" 33#include "cs42l73.h"
32 34
33struct sp_config { 35struct sp_config {
@@ -35,6 +37,7 @@ struct sp_config {
35 u32 srate; 37 u32 srate;
36}; 38};
37struct cs42l73_private { 39struct cs42l73_private {
40 struct cs42l73_platform_data pdata;
38 struct sp_config config[3]; 41 struct sp_config config[3];
39 struct regmap *regmap; 42 struct regmap *regmap;
40 u32 sysclk; 43 u32 sysclk;
@@ -310,15 +313,6 @@ static const struct soc_enum ng_delay_enum =
310 SOC_ENUM_SINGLE(CS42L73_NGCAB, 0, 313 SOC_ENUM_SINGLE(CS42L73_NGCAB, 0,
311 ARRAY_SIZE(cs42l73_ng_delay_text), cs42l73_ng_delay_text); 314 ARRAY_SIZE(cs42l73_ng_delay_text), cs42l73_ng_delay_text);
312 315
313static const char * const charge_pump_freq_text[] = {
314 "0", "1", "2", "3", "4",
315 "5", "6", "7", "8", "9",
316 "10", "11", "12", "13", "14", "15" };
317
318static const struct soc_enum charge_pump_enum =
319 SOC_ENUM_SINGLE(CS42L73_CPFCHC, 4,
320 ARRAY_SIZE(charge_pump_freq_text), charge_pump_freq_text);
321
322static const char * const cs42l73_mono_mix_texts[] = { 316static const char * const cs42l73_mono_mix_texts[] = {
323 "Left", "Right", "Mono Mix"}; 317 "Left", "Right", "Mono Mix"};
324 318
@@ -511,8 +505,6 @@ static const struct snd_kcontrol_new cs42l73_snd_controls[] = {
511 SOC_SINGLE("NG Threshold", CS42L73_NGCAB, 2, 7, 0), 505 SOC_SINGLE("NG Threshold", CS42L73_NGCAB, 2, 7, 0),
512 SOC_ENUM("NG Delay", ng_delay_enum), 506 SOC_ENUM("NG Delay", ng_delay_enum),
513 507
514 SOC_ENUM("Charge Pump Frequency", charge_pump_enum),
515
516 SOC_DOUBLE_R_TLV("XSP-IP Volume", 508 SOC_DOUBLE_R_TLV("XSP-IP Volume",
517 CS42L73_XSPAIPAA, CS42L73_XSPBIPBA, 0, 0x3F, 1, 509 CS42L73_XSPAIPAA, CS42L73_XSPBIPBA, 0, 0x3F, 1,
518 attn_tlv), 510 attn_tlv),
@@ -1055,11 +1047,11 @@ static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1055 1047
1056 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1048 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1057 case SND_SOC_DAIFMT_CBM_CFM: 1049 case SND_SOC_DAIFMT_CBM_CFM:
1058 mmcc |= MS_MASTER; 1050 mmcc |= CS42L73_MS_MASTER;
1059 break; 1051 break;
1060 1052
1061 case SND_SOC_DAIFMT_CBS_CFS: 1053 case SND_SOC_DAIFMT_CBS_CFS:
1062 mmcc &= ~MS_MASTER; 1054 mmcc &= ~CS42L73_MS_MASTER;
1063 break; 1055 break;
1064 1056
1065 default: 1057 default:
@@ -1071,11 +1063,11 @@ static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1071 1063
1072 switch (format) { 1064 switch (format) {
1073 case SND_SOC_DAIFMT_I2S: 1065 case SND_SOC_DAIFMT_I2S:
1074 spc &= ~SPDIF_PCM; 1066 spc &= ~CS42L73_SPDIF_PCM;
1075 break; 1067 break;
1076 case SND_SOC_DAIFMT_DSP_A: 1068 case SND_SOC_DAIFMT_DSP_A:
1077 case SND_SOC_DAIFMT_DSP_B: 1069 case SND_SOC_DAIFMT_DSP_B:
1078 if (mmcc & MS_MASTER) { 1070 if (mmcc & CS42L73_MS_MASTER) {
1079 dev_err(codec->dev, 1071 dev_err(codec->dev,
1080 "PCM format in slave mode only\n"); 1072 "PCM format in slave mode only\n");
1081 return -EINVAL; 1073 return -EINVAL;
@@ -1085,25 +1077,25 @@ static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1085 "PCM format is not supported on ASP port\n"); 1077 "PCM format is not supported on ASP port\n");
1086 return -EINVAL; 1078 return -EINVAL;
1087 } 1079 }
1088 spc |= SPDIF_PCM; 1080 spc |= CS42L73_SPDIF_PCM;
1089 break; 1081 break;
1090 default: 1082 default:
1091 return -EINVAL; 1083 return -EINVAL;
1092 } 1084 }
1093 1085
1094 if (spc & SPDIF_PCM) { 1086 if (spc & CS42L73_SPDIF_PCM) {
1095 /* Clear PCM mode, clear PCM_BIT_ORDER bit for MSB->LSB */ 1087 /* Clear PCM mode, clear PCM_BIT_ORDER bit for MSB->LSB */
1096 spc &= ~(PCM_MODE_MASK | PCM_BIT_ORDER); 1088 spc &= ~(CS42L73_PCM_MODE_MASK | CS42L73_PCM_BIT_ORDER);
1097 switch (format) { 1089 switch (format) {
1098 case SND_SOC_DAIFMT_DSP_B: 1090 case SND_SOC_DAIFMT_DSP_B:
1099 if (inv == SND_SOC_DAIFMT_IB_IF) 1091 if (inv == SND_SOC_DAIFMT_IB_IF)
1100 spc |= PCM_MODE0; 1092 spc |= CS42L73_PCM_MODE0;
1101 if (inv == SND_SOC_DAIFMT_IB_NF) 1093 if (inv == SND_SOC_DAIFMT_IB_NF)
1102 spc |= PCM_MODE1; 1094 spc |= CS42L73_PCM_MODE1;
1103 break; 1095 break;
1104 case SND_SOC_DAIFMT_DSP_A: 1096 case SND_SOC_DAIFMT_DSP_A:
1105 if (inv == SND_SOC_DAIFMT_IB_IF) 1097 if (inv == SND_SOC_DAIFMT_IB_IF)
1106 spc |= PCM_MODE1; 1098 spc |= CS42L73_PCM_MODE1;
1107 break; 1099 break;
1108 default: 1100 default:
1109 return -EINVAL; 1101 return -EINVAL;
@@ -1163,7 +1155,7 @@ static int cs42l73_pcm_hw_params(struct snd_pcm_substream *substream,
1163 int mclk_coeff; 1155 int mclk_coeff;
1164 int srate = params_rate(params); 1156 int srate = params_rate(params);
1165 1157
1166 if (priv->config[id].mmcc & MS_MASTER) { 1158 if (priv->config[id].mmcc & CS42L73_MS_MASTER) {
1167 /* CS42L73 Master */ 1159 /* CS42L73 Master */
1168 /* MCLK -> srate */ 1160 /* MCLK -> srate */
1169 mclk_coeff = 1161 mclk_coeff =
@@ -1182,13 +1174,13 @@ static int cs42l73_pcm_hw_params(struct snd_pcm_substream *substream,
1182 priv->config[id].spc &= 0xFC; 1174 priv->config[id].spc &= 0xFC;
1183 /* Use SCLK=64*Fs if internal MCLK >= 6.4MHz */ 1175 /* Use SCLK=64*Fs if internal MCLK >= 6.4MHz */
1184 if (priv->mclk >= 6400000) 1176 if (priv->mclk >= 6400000)
1185 priv->config[id].spc |= MCK_SCLK_64FS; 1177 priv->config[id].spc |= CS42L73_MCK_SCLK_64FS;
1186 else 1178 else
1187 priv->config[id].spc |= MCK_SCLK_MCLK; 1179 priv->config[id].spc |= CS42L73_MCK_SCLK_MCLK;
1188 } else { 1180 } else {
1189 /* CS42L73 Slave */ 1181 /* CS42L73 Slave */
1190 priv->config[id].spc &= 0xFC; 1182 priv->config[id].spc &= 0xFC;
1191 priv->config[id].spc |= MCK_SCLK_64FS; 1183 priv->config[id].spc |= CS42L73_MCK_SCLK_64FS;
1192 } 1184 }
1193 /* Update ASRCs */ 1185 /* Update ASRCs */
1194 priv->config[id].srate = srate; 1186 priv->config[id].srate = srate;
@@ -1208,8 +1200,8 @@ static int cs42l73_set_bias_level(struct snd_soc_codec *codec,
1208 1200
1209 switch (level) { 1201 switch (level) {
1210 case SND_SOC_BIAS_ON: 1202 case SND_SOC_BIAS_ON:
1211 snd_soc_update_bits(codec, CS42L73_DMMCC, MCLKDIS, 0); 1203 snd_soc_update_bits(codec, CS42L73_DMMCC, CS42L73_MCLKDIS, 0);
1212 snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 0); 1204 snd_soc_update_bits(codec, CS42L73_PWRCTL1, CS42L73_PDN, 0);
1213 break; 1205 break;
1214 1206
1215 case SND_SOC_BIAS_PREPARE: 1207 case SND_SOC_BIAS_PREPARE:
@@ -1220,11 +1212,11 @@ static int cs42l73_set_bias_level(struct snd_soc_codec *codec,
1220 regcache_cache_only(cs42l73->regmap, false); 1212 regcache_cache_only(cs42l73->regmap, false);
1221 regcache_sync(cs42l73->regmap); 1213 regcache_sync(cs42l73->regmap);
1222 } 1214 }
1223 snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 1); 1215 snd_soc_update_bits(codec, CS42L73_PWRCTL1, CS42L73_PDN, 1);
1224 break; 1216 break;
1225 1217
1226 case SND_SOC_BIAS_OFF: 1218 case SND_SOC_BIAS_OFF:
1227 snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 1); 1219 snd_soc_update_bits(codec, CS42L73_PWRCTL1, CS42L73_PDN, 1);
1228 if (cs42l73->shutdwn_delay > 0) { 1220 if (cs42l73->shutdwn_delay > 0) {
1229 mdelay(cs42l73->shutdwn_delay); 1221 mdelay(cs42l73->shutdwn_delay);
1230 cs42l73->shutdwn_delay = 0; 1222 cs42l73->shutdwn_delay = 0;
@@ -1233,7 +1225,7 @@ static int cs42l73_set_bias_level(struct snd_soc_codec *codec,
1233 * down. 1225 * down.
1234 */ 1226 */
1235 } 1227 }
1236 snd_soc_update_bits(codec, CS42L73_DMMCC, MCLKDIS, 1); 1228 snd_soc_update_bits(codec, CS42L73_DMMCC, CS42L73_MCLKDIS, 1);
1237 break; 1229 break;
1238 } 1230 }
1239 codec->dapm.bias_level = level; 1231 codec->dapm.bias_level = level;
@@ -1367,11 +1359,16 @@ static int cs42l73_probe(struct snd_soc_codec *codec)
1367 return ret; 1359 return ret;
1368 } 1360 }
1369 1361
1370 regcache_cache_only(cs42l73->regmap, true);
1371
1372 cs42l73_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1362 cs42l73_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1373 1363
1374 cs42l73->mclksel = CS42L73_CLKID_MCLK1; /* MCLK1 as master clk */ 1364 /* Set Charge Pump Frequency */
1365 if (cs42l73->pdata.chgfreq)
1366 snd_soc_update_bits(codec, CS42L73_CPFCHC,
1367 CS42L73_CHARGEPUMP_MASK,
1368 cs42l73->pdata.chgfreq << 4);
1369
1370 /* MCLK1 as master clk */
1371 cs42l73->mclksel = CS42L73_CLKID_MCLK1;
1375 cs42l73->mclk = 0; 1372 cs42l73->mclk = 0;
1376 1373
1377 return ret; 1374 return ret;
@@ -1415,9 +1412,11 @@ static int cs42l73_i2c_probe(struct i2c_client *i2c_client,
1415 const struct i2c_device_id *id) 1412 const struct i2c_device_id *id)
1416{ 1413{
1417 struct cs42l73_private *cs42l73; 1414 struct cs42l73_private *cs42l73;
1415 struct cs42l73_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
1418 int ret; 1416 int ret;
1419 unsigned int devid = 0; 1417 unsigned int devid = 0;
1420 unsigned int reg; 1418 unsigned int reg;
1419 u32 val32;
1421 1420
1422 cs42l73 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l73_private), 1421 cs42l73 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l73_private),
1423 GFP_KERNEL); 1422 GFP_KERNEL);
@@ -1426,14 +1425,49 @@ static int cs42l73_i2c_probe(struct i2c_client *i2c_client,
1426 return -ENOMEM; 1425 return -ENOMEM;
1427 } 1426 }
1428 1427
1429 i2c_set_clientdata(i2c_client, cs42l73);
1430
1431 cs42l73->regmap = devm_regmap_init_i2c(i2c_client, &cs42l73_regmap); 1428 cs42l73->regmap = devm_regmap_init_i2c(i2c_client, &cs42l73_regmap);
1432 if (IS_ERR(cs42l73->regmap)) { 1429 if (IS_ERR(cs42l73->regmap)) {
1433 ret = PTR_ERR(cs42l73->regmap); 1430 ret = PTR_ERR(cs42l73->regmap);
1434 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 1431 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1435 return ret; 1432 return ret;
1436 } 1433 }
1434
1435 if (pdata) {
1436 cs42l73->pdata = *pdata;
1437 } else {
1438 pdata = devm_kzalloc(&i2c_client->dev,
1439 sizeof(struct cs42l73_platform_data),
1440 GFP_KERNEL);
1441 if (!pdata) {
1442 dev_err(&i2c_client->dev, "could not allocate pdata\n");
1443 return -ENOMEM;
1444 }
1445 if (i2c_client->dev.of_node) {
1446 if (of_property_read_u32(i2c_client->dev.of_node,
1447 "chgfreq", &val32) >= 0)
1448 pdata->chgfreq = val32;
1449 }
1450 pdata->reset_gpio = of_get_named_gpio(i2c_client->dev.of_node,
1451 "reset-gpio", 0);
1452 cs42l73->pdata = *pdata;
1453 }
1454
1455 i2c_set_clientdata(i2c_client, cs42l73);
1456
1457 if (cs42l73->pdata.reset_gpio) {
1458 ret = gpio_request_one(cs42l73->pdata.reset_gpio,
1459 GPIOF_OUT_INIT_HIGH, "CS42L73 /RST");
1460 if (ret < 0) {
1461 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1462 cs42l73->pdata.reset_gpio, ret);
1463 return ret;
1464 }
1465 gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 0);
1466 gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 1);
1467 }
1468
1469 regcache_cache_bypass(cs42l73->regmap, true);
1470
1437 /* initialize codec */ 1471 /* initialize codec */
1438 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_AB, &reg); 1472 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_AB, &reg);
1439 devid = (reg & 0xFF) << 12; 1473 devid = (reg & 0xFF) << 12;
@@ -1444,7 +1478,6 @@ static int cs42l73_i2c_probe(struct i2c_client *i2c_client,
1444 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_E, &reg); 1478 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_E, &reg);
1445 devid |= (reg & 0xF0) >> 4; 1479 devid |= (reg & 0xF0) >> 4;
1446 1480
1447
1448 if (devid != CS42L73_DEVID) { 1481 if (devid != CS42L73_DEVID) {
1449 ret = -ENODEV; 1482 ret = -ENODEV;
1450 dev_err(&i2c_client->dev, 1483 dev_err(&i2c_client->dev,
@@ -1462,7 +1495,7 @@ static int cs42l73_i2c_probe(struct i2c_client *i2c_client,
1462 dev_info(&i2c_client->dev, 1495 dev_info(&i2c_client->dev,
1463 "Cirrus Logic CS42L73, Revision: %02X\n", reg & 0xFF); 1496 "Cirrus Logic CS42L73, Revision: %02X\n", reg & 0xFF);
1464 1497
1465 regcache_cache_only(cs42l73->regmap, true); 1498 regcache_cache_bypass(cs42l73->regmap, false);
1466 1499
1467 ret = snd_soc_register_codec(&i2c_client->dev, 1500 ret = snd_soc_register_codec(&i2c_client->dev,
1468 &soc_codec_dev_cs42l73, cs42l73_dai, 1501 &soc_codec_dev_cs42l73, cs42l73_dai,
@@ -1478,6 +1511,12 @@ static int cs42l73_i2c_remove(struct i2c_client *client)
1478 return 0; 1511 return 0;
1479} 1512}
1480 1513
1514static const struct of_device_id cs42l73_of_match[] = {
1515 { .compatible = "cirrus,cs42l73", },
1516 {},
1517};
1518MODULE_DEVICE_TABLE(of, cs42l73_of_match);
1519
1481static const struct i2c_device_id cs42l73_id[] = { 1520static const struct i2c_device_id cs42l73_id[] = {
1482 {"cs42l73", 0}, 1521 {"cs42l73", 0},
1483 {} 1522 {}
@@ -1489,6 +1528,7 @@ static struct i2c_driver cs42l73_i2c_driver = {
1489 .driver = { 1528 .driver = {
1490 .name = "cs42l73", 1529 .name = "cs42l73",
1491 .owner = THIS_MODULE, 1530 .owner = THIS_MODULE,
1531 .of_match_table = cs42l73_of_match,
1492 }, 1532 },
1493 .id_table = cs42l73_id, 1533 .id_table = cs42l73_id,
1494 .probe = cs42l73_i2c_probe, 1534 .probe = cs42l73_i2c_probe,
diff --git a/sound/soc/codecs/cs42l73.h b/sound/soc/codecs/cs42l73.h
index f30a4c4d62e6..45746186a678 100644
--- a/sound/soc/codecs/cs42l73.h
+++ b/sound/soc/codecs/cs42l73.h
@@ -128,59 +128,60 @@
128/* Bitfield Definitions */ 128/* Bitfield Definitions */
129 129
130/* CS42L73_PWRCTL1 */ 130/* CS42L73_PWRCTL1 */
131#define PDN_ADCB (1 << 7) 131#define CS42L73_PDN_ADCB (1 << 7)
132#define PDN_DMICB (1 << 6) 132#define CS42L73_PDN_DMICB (1 << 6)
133#define PDN_ADCA (1 << 5) 133#define CS42L73_PDN_ADCA (1 << 5)
134#define PDN_DMICA (1 << 4) 134#define CS42L73_PDN_DMICA (1 << 4)
135#define PDN_LDO (1 << 2) 135#define CS42L73_PDN_LDO (1 << 2)
136#define DISCHG_FILT (1 << 1) 136#define CS42L73_DISCHG_FILT (1 << 1)
137#define PDN (1 << 0) 137#define CS42L73_PDN (1 << 0)
138 138
139/* CS42L73_PWRCTL2 */ 139/* CS42L73_PWRCTL2 */
140#define PDN_MIC2_BIAS (1 << 7) 140#define CS42L73_PDN_MIC2_BIAS (1 << 7)
141#define PDN_MIC1_BIAS (1 << 6) 141#define CS42L73_PDN_MIC1_BIAS (1 << 6)
142#define PDN_VSP (1 << 4) 142#define CS42L73_PDN_VSP (1 << 4)
143#define PDN_ASP_SDOUT (1 << 3) 143#define CS42L73_PDN_ASP_SDOUT (1 << 3)
144#define PDN_ASP_SDIN (1 << 2) 144#define CS42L73_PDN_ASP_SDIN (1 << 2)
145#define PDN_XSP_SDOUT (1 << 1) 145#define CS42L73_PDN_XSP_SDOUT (1 << 1)
146#define PDN_XSP_SDIN (1 << 0) 146#define CS42L73_PDN_XSP_SDIN (1 << 0)
147 147
148/* CS42L73_PWRCTL3 */ 148/* CS42L73_PWRCTL3 */
149#define PDN_THMS (1 << 5) 149#define CS42L73_PDN_THMS (1 << 5)
150#define PDN_SPKLO (1 << 4) 150#define CS42L73_PDN_SPKLO (1 << 4)
151#define PDN_EAR (1 << 3) 151#define CS42L73_PDN_EAR (1 << 3)
152#define PDN_SPK (1 << 2) 152#define CS42L73_PDN_SPK (1 << 2)
153#define PDN_LO (1 << 1) 153#define CS42L73_PDN_LO (1 << 1)
154#define PDN_HP (1 << 0) 154#define CS42L73_PDN_HP (1 << 0)
155 155
156/* Thermal Overload Detect. Requires interrupt ... */ 156/* Thermal Overload Detect. Requires interrupt ... */
157#define THMOVLD_150C 0 157#define CS42L73_THMOVLD_150C 0
158#define THMOVLD_132C 1 158#define CS42L73_THMOVLD_132C 1
159#define THMOVLD_115C 2 159#define CS42L73_THMOVLD_115C 2
160#define THMOVLD_098C 3 160#define CS42L73_THMOVLD_098C 3
161 161
162#define CS42L73_CHARGEPUMP_MASK (0xF0)
162 163
163/* CS42L73_ASPC, CS42L73_XSPC, CS42L73_VSPC */ 164/* CS42L73_ASPC, CS42L73_XSPC, CS42L73_VSPC */
164#define SP_3ST (1 << 7) 165#define CS42L73_SP_3ST (1 << 7)
165#define SPDIF_I2S (0 << 6) 166#define CS42L73_SPDIF_I2S (0 << 6)
166#define SPDIF_PCM (1 << 6) 167#define CS42L73_SPDIF_PCM (1 << 6)
167#define PCM_MODE0 (0 << 4) 168#define CS42L73_PCM_MODE0 (0 << 4)
168#define PCM_MODE1 (1 << 4) 169#define CS42L73_PCM_MODE1 (1 << 4)
169#define PCM_MODE2 (2 << 4) 170#define CS42L73_PCM_MODE2 (2 << 4)
170#define PCM_MODE_MASK (3 << 4) 171#define CS42L73_PCM_MODE_MASK (3 << 4)
171#define PCM_BIT_ORDER (1 << 3) 172#define CS42L73_PCM_BIT_ORDER (1 << 3)
172#define MCK_SCLK_64FS (0 << 0) 173#define CS42L73_MCK_SCLK_64FS (0 << 0)
173#define MCK_SCLK_MCLK (2 << 0) 174#define CS42L73_MCK_SCLK_MCLK (2 << 0)
174#define MCK_SCLK_PREMCLK (3 << 0) 175#define CS42L73_MCK_SCLK_PREMCLK (3 << 0)
175 176
176/* CS42L73_xSPMMCC */ 177/* CS42L73_xSPMMCC */
177#define MS_MASTER (1 << 7) 178#define CS42L73_MS_MASTER (1 << 7)
178 179
179 180
180/* CS42L73_DMMCC */ 181/* CS42L73_DMMCC */
181#define MCLKDIS (1 << 0) 182#define CS42L73_MCLKDIS (1 << 0)
182#define MCLKSEL_MCLK2 (1 << 4) 183#define CS42L73_MCLKSEL_MCLK2 (1 << 4)
183#define MCLKSEL_MCLK1 (0 << 4) 184#define CS42L73_MCLKSEL_MCLK1 (0 << 4)
184 185
185/* CS42L73 MCLK derived from MCLK1 or MCLK2 */ 186/* CS42L73 MCLK derived from MCLK1 or MCLK2 */
186#define CS42L73_CLKID_MCLK1 0 187#define CS42L73_CLKID_MCLK1 0
@@ -194,28 +195,26 @@
194#define CS42L73_VSP 2 195#define CS42L73_VSP 2
195 196
196/* IS1, IM1 */ 197/* IS1, IM1 */
197#define MIC2_SDET (1 << 6) 198#define CS42L73_MIC2_SDET (1 << 6)
198#define THMOVLD (1 << 4) 199#define CS42L73_THMOVLD (1 << 4)
199#define DIGMIXOVFL (1 << 3) 200#define CS42L73_DIGMIXOVFL (1 << 3)
200#define IPBOVFL (1 << 1) 201#define CS42L73_IPBOVFL (1 << 1)
201#define IPAOVFL (1 << 0) 202#define CS42L73_IPAOVFL (1 << 0)
202 203
203/* Analog Softramp */ 204/* Analog Softramp */
204#define ANLGOSFT (1 << 0) 205#define CS42L73_ANLGOSFT (1 << 0)
205 206
206/* HP A/B Analog Mute */ 207/* HP A/B Analog Mute */
207#define HPA_MUTE (1 << 7) 208#define CS42L73_HPA_MUTE (1 << 7)
208/* LO A/B Analog Mute */ 209/* LO A/B Analog Mute */
209#define LOA_MUTE (1 << 7) 210#define CS42L73_LOA_MUTE (1 << 7)
210/* Digital Mute */ 211/* Digital Mute */
211#define HLAD_MUTE (1 << 0) 212#define CS42L73_HLAD_MUTE (1 << 0)
212#define HLBD_MUTE (1 << 1) 213#define CS42L73_HLBD_MUTE (1 << 1)
213#define SPKD_MUTE (1 << 2) 214#define CS42L73_SPKD_MUTE (1 << 2)
214#define ESLD_MUTE (1 << 3) 215#define CS42L73_ESLD_MUTE (1 << 3)
215 216
216/* Misc defines for codec */ 217/* Misc defines for codec */
217#define CS42L73_RESET_GPIO 143
218
219#define CS42L73_DEVID 0x00042A73 218#define CS42L73_DEVID 0x00042A73
220#define CS42L73_MCLKX_MIN 5644800 219#define CS42L73_MCLKX_MIN 5644800
221#define CS42L73_MCLKX_MAX 38400000 220#define CS42L73_MCLKX_MAX 38400000
diff --git a/sound/soc/codecs/max98088.c b/sound/soc/codecs/max98088.c
index 566a367c94fa..66ceee22fdad 100644
--- a/sound/soc/codecs/max98088.c
+++ b/sound/soc/codecs/max98088.c
@@ -15,6 +15,7 @@
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/pm.h> 16#include <linux/pm.h>
17#include <linux/i2c.h> 17#include <linux/i2c.h>
18#include <linux/regmap.h>
18#include <sound/core.h> 19#include <sound/core.h>
19#include <sound/pcm.h> 20#include <sound/pcm.h>
20#include <sound/pcm_params.h> 21#include <sound/pcm_params.h>
@@ -38,294 +39,223 @@ struct max98088_cdata {
38}; 39};
39 40
40struct max98088_priv { 41struct max98088_priv {
41 enum max98088_type devtype; 42 struct regmap *regmap;
42 struct max98088_pdata *pdata; 43 enum max98088_type devtype;
43 unsigned int sysclk; 44 struct max98088_pdata *pdata;
44 struct max98088_cdata dai[2]; 45 unsigned int sysclk;
45 int eq_textcnt; 46 struct max98088_cdata dai[2];
46 const char **eq_texts; 47 int eq_textcnt;
47 struct soc_enum eq_enum; 48 const char **eq_texts;
48 u8 ina_state; 49 struct soc_enum eq_enum;
49 u8 inb_state; 50 u8 ina_state;
50 unsigned int ex_mode; 51 u8 inb_state;
51 unsigned int digmic; 52 unsigned int ex_mode;
52 unsigned int mic1pre; 53 unsigned int digmic;
53 unsigned int mic2pre; 54 unsigned int mic1pre;
54 unsigned int extmic_mode; 55 unsigned int mic2pre;
56 unsigned int extmic_mode;
55}; 57};
56 58
57static const u8 max98088_reg[M98088_REG_CNT] = { 59static const struct reg_default max98088_reg[] = {
58 0x00, /* 00 IRQ status */ 60 { 0xf, 0x00 }, /* 0F interrupt enable */
59 0x00, /* 01 MIC status */ 61
60 0x00, /* 02 jack status */ 62 { 0x10, 0x00 }, /* 10 master clock */
61 0x00, /* 03 battery voltage */ 63 { 0x11, 0x00 }, /* 11 DAI1 clock mode */
62 0x00, /* 04 */ 64 { 0x12, 0x00 }, /* 12 DAI1 clock control */
63 0x00, /* 05 */ 65 { 0x13, 0x00 }, /* 13 DAI1 clock control */
64 0x00, /* 06 */ 66 { 0x14, 0x00 }, /* 14 DAI1 format */
65 0x00, /* 07 */ 67 { 0x15, 0x00 }, /* 15 DAI1 clock */
66 0x00, /* 08 */ 68 { 0x16, 0x00 }, /* 16 DAI1 config */
67 0x00, /* 09 */ 69 { 0x17, 0x00 }, /* 17 DAI1 TDM */
68 0x00, /* 0A */ 70 { 0x18, 0x00 }, /* 18 DAI1 filters */
69 0x00, /* 0B */ 71 { 0x19, 0x00 }, /* 19 DAI2 clock mode */
70 0x00, /* 0C */ 72 { 0x1a, 0x00 }, /* 1A DAI2 clock control */
71 0x00, /* 0D */ 73 { 0x1b, 0x00 }, /* 1B DAI2 clock control */
72 0x00, /* 0E */ 74 { 0x1c, 0x00 }, /* 1C DAI2 format */
73 0x00, /* 0F interrupt enable */ 75 { 0x1d, 0x00 }, /* 1D DAI2 clock */
74 76 { 0x1e, 0x00 }, /* 1E DAI2 config */
75 0x00, /* 10 master clock */ 77 { 0x1f, 0x00 }, /* 1F DAI2 TDM */
76 0x00, /* 11 DAI1 clock mode */ 78
77 0x00, /* 12 DAI1 clock control */ 79 { 0x20, 0x00 }, /* 20 DAI2 filters */
78 0x00, /* 13 DAI1 clock control */ 80 { 0x21, 0x00 }, /* 21 data config */
79 0x00, /* 14 DAI1 format */ 81 { 0x22, 0x00 }, /* 22 DAC mixer */
80 0x00, /* 15 DAI1 clock */ 82 { 0x23, 0x00 }, /* 23 left ADC mixer */
81 0x00, /* 16 DAI1 config */ 83 { 0x24, 0x00 }, /* 24 right ADC mixer */
82 0x00, /* 17 DAI1 TDM */ 84 { 0x25, 0x00 }, /* 25 left HP mixer */
83 0x00, /* 18 DAI1 filters */ 85 { 0x26, 0x00 }, /* 26 right HP mixer */
84 0x00, /* 19 DAI2 clock mode */ 86 { 0x27, 0x00 }, /* 27 HP control */
85 0x00, /* 1A DAI2 clock control */ 87 { 0x28, 0x00 }, /* 28 left REC mixer */
86 0x00, /* 1B DAI2 clock control */ 88 { 0x29, 0x00 }, /* 29 right REC mixer */
87 0x00, /* 1C DAI2 format */ 89 { 0x2a, 0x00 }, /* 2A REC control */
88 0x00, /* 1D DAI2 clock */ 90 { 0x2b, 0x00 }, /* 2B left SPK mixer */
89 0x00, /* 1E DAI2 config */ 91 { 0x2c, 0x00 }, /* 2C right SPK mixer */
90 0x00, /* 1F DAI2 TDM */ 92 { 0x2d, 0x00 }, /* 2D SPK control */
91 93 { 0x2e, 0x00 }, /* 2E sidetone */
92 0x00, /* 20 DAI2 filters */ 94 { 0x2f, 0x00 }, /* 2F DAI1 playback level */
93 0x00, /* 21 data config */ 95
94 0x00, /* 22 DAC mixer */ 96 { 0x30, 0x00 }, /* 30 DAI1 playback level */
95 0x00, /* 23 left ADC mixer */ 97 { 0x31, 0x00 }, /* 31 DAI2 playback level */
96 0x00, /* 24 right ADC mixer */ 98 { 0x32, 0x00 }, /* 32 DAI2 playbakc level */
97 0x00, /* 25 left HP mixer */ 99 { 0x33, 0x00 }, /* 33 left ADC level */
98 0x00, /* 26 right HP mixer */ 100 { 0x34, 0x00 }, /* 34 right ADC level */
99 0x00, /* 27 HP control */ 101 { 0x35, 0x00 }, /* 35 MIC1 level */
100 0x00, /* 28 left REC mixer */ 102 { 0x36, 0x00 }, /* 36 MIC2 level */
101 0x00, /* 29 right REC mixer */ 103 { 0x37, 0x00 }, /* 37 INA level */
102 0x00, /* 2A REC control */ 104 { 0x38, 0x00 }, /* 38 INB level */
103 0x00, /* 2B left SPK mixer */ 105 { 0x39, 0x00 }, /* 39 left HP volume */
104 0x00, /* 2C right SPK mixer */ 106 { 0x3a, 0x00 }, /* 3A right HP volume */
105 0x00, /* 2D SPK control */ 107 { 0x3b, 0x00 }, /* 3B left REC volume */
106 0x00, /* 2E sidetone */ 108 { 0x3c, 0x00 }, /* 3C right REC volume */
107 0x00, /* 2F DAI1 playback level */ 109 { 0x3d, 0x00 }, /* 3D left SPK volume */
108 110 { 0x3e, 0x00 }, /* 3E right SPK volume */
109 0x00, /* 30 DAI1 playback level */ 111 { 0x3f, 0x00 }, /* 3F MIC config */
110 0x00, /* 31 DAI2 playback level */ 112
111 0x00, /* 32 DAI2 playbakc level */ 113 { 0x40, 0x00 }, /* 40 MIC threshold */
112 0x00, /* 33 left ADC level */ 114 { 0x41, 0x00 }, /* 41 excursion limiter filter */
113 0x00, /* 34 right ADC level */ 115 { 0x42, 0x00 }, /* 42 excursion limiter threshold */
114 0x00, /* 35 MIC1 level */ 116 { 0x43, 0x00 }, /* 43 ALC */
115 0x00, /* 36 MIC2 level */ 117 { 0x44, 0x00 }, /* 44 power limiter threshold */
116 0x00, /* 37 INA level */ 118 { 0x45, 0x00 }, /* 45 power limiter config */
117 0x00, /* 38 INB level */ 119 { 0x46, 0x00 }, /* 46 distortion limiter config */
118 0x00, /* 39 left HP volume */ 120 { 0x47, 0x00 }, /* 47 audio input */
119 0x00, /* 3A right HP volume */ 121 { 0x48, 0x00 }, /* 48 microphone */
120 0x00, /* 3B left REC volume */ 122 { 0x49, 0x00 }, /* 49 level control */
121 0x00, /* 3C right REC volume */ 123 { 0x4a, 0x00 }, /* 4A bypass switches */
122 0x00, /* 3D left SPK volume */ 124 { 0x4b, 0x00 }, /* 4B jack detect */
123 0x00, /* 3E right SPK volume */ 125 { 0x4c, 0x00 }, /* 4C input enable */
124 0x00, /* 3F MIC config */ 126 { 0x4d, 0x00 }, /* 4D output enable */
125 127 { 0x4e, 0xF0 }, /* 4E bias control */
126 0x00, /* 40 MIC threshold */ 128 { 0x4f, 0x00 }, /* 4F DAC power */
127 0x00, /* 41 excursion limiter filter */ 129
128 0x00, /* 42 excursion limiter threshold */ 130 { 0x50, 0x0F }, /* 50 DAC power */
129 0x00, /* 43 ALC */ 131 { 0x51, 0x00 }, /* 51 system */
130 0x00, /* 44 power limiter threshold */ 132 { 0x52, 0x00 }, /* 52 DAI1 EQ1 */
131 0x00, /* 45 power limiter config */ 133 { 0x53, 0x00 }, /* 53 DAI1 EQ1 */
132 0x00, /* 46 distortion limiter config */ 134 { 0x54, 0x00 }, /* 54 DAI1 EQ1 */
133 0x00, /* 47 audio input */ 135 { 0x55, 0x00 }, /* 55 DAI1 EQ1 */
134 0x00, /* 48 microphone */ 136 { 0x56, 0x00 }, /* 56 DAI1 EQ1 */
135 0x00, /* 49 level control */ 137 { 0x57, 0x00 }, /* 57 DAI1 EQ1 */
136 0x00, /* 4A bypass switches */ 138 { 0x58, 0x00 }, /* 58 DAI1 EQ1 */
137 0x00, /* 4B jack detect */ 139 { 0x59, 0x00 }, /* 59 DAI1 EQ1 */
138 0x00, /* 4C input enable */ 140 { 0x5a, 0x00 }, /* 5A DAI1 EQ1 */
139 0x00, /* 4D output enable */ 141 { 0x5b, 0x00 }, /* 5B DAI1 EQ1 */
140 0xF0, /* 4E bias control */ 142 { 0x5c, 0x00 }, /* 5C DAI1 EQ2 */
141 0x00, /* 4F DAC power */ 143 { 0x5d, 0x00 }, /* 5D DAI1 EQ2 */
142 144 { 0x5e, 0x00 }, /* 5E DAI1 EQ2 */
143 0x0F, /* 50 DAC power */ 145 { 0x5f, 0x00 }, /* 5F DAI1 EQ2 */
144 0x00, /* 51 system */ 146
145 0x00, /* 52 DAI1 EQ1 */ 147 { 0x60, 0x00 }, /* 60 DAI1 EQ2 */
146 0x00, /* 53 DAI1 EQ1 */ 148 { 0x61, 0x00 }, /* 61 DAI1 EQ2 */
147 0x00, /* 54 DAI1 EQ1 */ 149 { 0x62, 0x00 }, /* 62 DAI1 EQ2 */
148 0x00, /* 55 DAI1 EQ1 */ 150 { 0x63, 0x00 }, /* 63 DAI1 EQ2 */
149 0x00, /* 56 DAI1 EQ1 */ 151 { 0x64, 0x00 }, /* 64 DAI1 EQ2 */
150 0x00, /* 57 DAI1 EQ1 */ 152 { 0x65, 0x00 }, /* 65 DAI1 EQ2 */
151 0x00, /* 58 DAI1 EQ1 */ 153 { 0x66, 0x00 }, /* 66 DAI1 EQ3 */
152 0x00, /* 59 DAI1 EQ1 */ 154 { 0x67, 0x00 }, /* 67 DAI1 EQ3 */
153 0x00, /* 5A DAI1 EQ1 */ 155 { 0x68, 0x00 }, /* 68 DAI1 EQ3 */
154 0x00, /* 5B DAI1 EQ1 */ 156 { 0x69, 0x00 }, /* 69 DAI1 EQ3 */
155 0x00, /* 5C DAI1 EQ2 */ 157 { 0x6a, 0x00 }, /* 6A DAI1 EQ3 */
156 0x00, /* 5D DAI1 EQ2 */ 158 { 0x6b, 0x00 }, /* 6B DAI1 EQ3 */
157 0x00, /* 5E DAI1 EQ2 */ 159 { 0x6c, 0x00 }, /* 6C DAI1 EQ3 */
158 0x00, /* 5F DAI1 EQ2 */ 160 { 0x6d, 0x00 }, /* 6D DAI1 EQ3 */
159 161 { 0x6e, 0x00 }, /* 6E DAI1 EQ3 */
160 0x00, /* 60 DAI1 EQ2 */ 162 { 0x6f, 0x00 }, /* 6F DAI1 EQ3 */
161 0x00, /* 61 DAI1 EQ2 */ 163
162 0x00, /* 62 DAI1 EQ2 */ 164 { 0x70, 0x00 }, /* 70 DAI1 EQ4 */
163 0x00, /* 63 DAI1 EQ2 */ 165 { 0x71, 0x00 }, /* 71 DAI1 EQ4 */
164 0x00, /* 64 DAI1 EQ2 */ 166 { 0x72, 0x00 }, /* 72 DAI1 EQ4 */
165 0x00, /* 65 DAI1 EQ2 */ 167 { 0x73, 0x00 }, /* 73 DAI1 EQ4 */
166 0x00, /* 66 DAI1 EQ3 */ 168 { 0x74, 0x00 }, /* 74 DAI1 EQ4 */
167 0x00, /* 67 DAI1 EQ3 */ 169 { 0x75, 0x00 }, /* 75 DAI1 EQ4 */
168 0x00, /* 68 DAI1 EQ3 */ 170 { 0x76, 0x00 }, /* 76 DAI1 EQ4 */
169 0x00, /* 69 DAI1 EQ3 */ 171 { 0x77, 0x00 }, /* 77 DAI1 EQ4 */
170 0x00, /* 6A DAI1 EQ3 */ 172 { 0x78, 0x00 }, /* 78 DAI1 EQ4 */
171 0x00, /* 6B DAI1 EQ3 */ 173 { 0x79, 0x00 }, /* 79 DAI1 EQ4 */
172 0x00, /* 6C DAI1 EQ3 */ 174 { 0x7a, 0x00 }, /* 7A DAI1 EQ5 */
173 0x00, /* 6D DAI1 EQ3 */ 175 { 0x7b, 0x00 }, /* 7B DAI1 EQ5 */
174 0x00, /* 6E DAI1 EQ3 */ 176 { 0x7c, 0x00 }, /* 7C DAI1 EQ5 */
175 0x00, /* 6F DAI1 EQ3 */ 177 { 0x7d, 0x00 }, /* 7D DAI1 EQ5 */
176 178 { 0x7e, 0x00 }, /* 7E DAI1 EQ5 */
177 0x00, /* 70 DAI1 EQ4 */ 179 { 0x7f, 0x00 }, /* 7F DAI1 EQ5 */
178 0x00, /* 71 DAI1 EQ4 */ 180
179 0x00, /* 72 DAI1 EQ4 */ 181 { 0x80, 0x00 }, /* 80 DAI1 EQ5 */
180 0x00, /* 73 DAI1 EQ4 */ 182 { 0x81, 0x00 }, /* 81 DAI1 EQ5 */
181 0x00, /* 74 DAI1 EQ4 */ 183 { 0x82, 0x00 }, /* 82 DAI1 EQ5 */
182 0x00, /* 75 DAI1 EQ4 */ 184 { 0x83, 0x00 }, /* 83 DAI1 EQ5 */
183 0x00, /* 76 DAI1 EQ4 */ 185 { 0x84, 0x00 }, /* 84 DAI2 EQ1 */
184 0x00, /* 77 DAI1 EQ4 */ 186 { 0x85, 0x00 }, /* 85 DAI2 EQ1 */
185 0x00, /* 78 DAI1 EQ4 */ 187 { 0x86, 0x00 }, /* 86 DAI2 EQ1 */
186 0x00, /* 79 DAI1 EQ4 */ 188 { 0x87, 0x00 }, /* 87 DAI2 EQ1 */
187 0x00, /* 7A DAI1 EQ5 */ 189 { 0x88, 0x00 }, /* 88 DAI2 EQ1 */
188 0x00, /* 7B DAI1 EQ5 */ 190 { 0x89, 0x00 }, /* 89 DAI2 EQ1 */
189 0x00, /* 7C DAI1 EQ5 */ 191 { 0x8a, 0x00 }, /* 8A DAI2 EQ1 */
190 0x00, /* 7D DAI1 EQ5 */ 192 { 0x8b, 0x00 }, /* 8B DAI2 EQ1 */
191 0x00, /* 7E DAI1 EQ5 */ 193 { 0x8c, 0x00 }, /* 8C DAI2 EQ1 */
192 0x00, /* 7F DAI1 EQ5 */ 194 { 0x8d, 0x00 }, /* 8D DAI2 EQ1 */
193 195 { 0x8e, 0x00 }, /* 8E DAI2 EQ2 */
194 0x00, /* 80 DAI1 EQ5 */ 196 { 0x8f, 0x00 }, /* 8F DAI2 EQ2 */
195 0x00, /* 81 DAI1 EQ5 */ 197
196 0x00, /* 82 DAI1 EQ5 */ 198 { 0x90, 0x00 }, /* 90 DAI2 EQ2 */
197 0x00, /* 83 DAI1 EQ5 */ 199 { 0x91, 0x00 }, /* 91 DAI2 EQ2 */
198 0x00, /* 84 DAI2 EQ1 */ 200 { 0x92, 0x00 }, /* 92 DAI2 EQ2 */
199 0x00, /* 85 DAI2 EQ1 */ 201 { 0x93, 0x00 }, /* 93 DAI2 EQ2 */
200 0x00, /* 86 DAI2 EQ1 */ 202 { 0x94, 0x00 }, /* 94 DAI2 EQ2 */
201 0x00, /* 87 DAI2 EQ1 */ 203 { 0x95, 0x00 }, /* 95 DAI2 EQ2 */
202 0x00, /* 88 DAI2 EQ1 */ 204 { 0x96, 0x00 }, /* 96 DAI2 EQ2 */
203 0x00, /* 89 DAI2 EQ1 */ 205 { 0x97, 0x00 }, /* 97 DAI2 EQ2 */
204 0x00, /* 8A DAI2 EQ1 */ 206 { 0x98, 0x00 }, /* 98 DAI2 EQ3 */
205 0x00, /* 8B DAI2 EQ1 */ 207 { 0x99, 0x00 }, /* 99 DAI2 EQ3 */
206 0x00, /* 8C DAI2 EQ1 */ 208 { 0x9a, 0x00 }, /* 9A DAI2 EQ3 */
207 0x00, /* 8D DAI2 EQ1 */ 209 { 0x9b, 0x00 }, /* 9B DAI2 EQ3 */
208 0x00, /* 8E DAI2 EQ2 */ 210 { 0x9c, 0x00 }, /* 9C DAI2 EQ3 */
209 0x00, /* 8F DAI2 EQ2 */ 211 { 0x9d, 0x00 }, /* 9D DAI2 EQ3 */
210 212 { 0x9e, 0x00 }, /* 9E DAI2 EQ3 */
211 0x00, /* 90 DAI2 EQ2 */ 213 { 0x9f, 0x00 }, /* 9F DAI2 EQ3 */
212 0x00, /* 91 DAI2 EQ2 */ 214
213 0x00, /* 92 DAI2 EQ2 */ 215 { 0xa0, 0x00 }, /* A0 DAI2 EQ3 */
214 0x00, /* 93 DAI2 EQ2 */ 216 { 0xa1, 0x00 }, /* A1 DAI2 EQ3 */
215 0x00, /* 94 DAI2 EQ2 */ 217 { 0xa2, 0x00 }, /* A2 DAI2 EQ4 */
216 0x00, /* 95 DAI2 EQ2 */ 218 { 0xa3, 0x00 }, /* A3 DAI2 EQ4 */
217 0x00, /* 96 DAI2 EQ2 */ 219 { 0xa4, 0x00 }, /* A4 DAI2 EQ4 */
218 0x00, /* 97 DAI2 EQ2 */ 220 { 0xa5, 0x00 }, /* A5 DAI2 EQ4 */
219 0x00, /* 98 DAI2 EQ3 */ 221 { 0xa6, 0x00 }, /* A6 DAI2 EQ4 */
220 0x00, /* 99 DAI2 EQ3 */ 222 { 0xa7, 0x00 }, /* A7 DAI2 EQ4 */
221 0x00, /* 9A DAI2 EQ3 */ 223 { 0xa8, 0x00 }, /* A8 DAI2 EQ4 */
222 0x00, /* 9B DAI2 EQ3 */ 224 { 0xa9, 0x00 }, /* A9 DAI2 EQ4 */
223 0x00, /* 9C DAI2 EQ3 */ 225 { 0xaa, 0x00 }, /* AA DAI2 EQ4 */
224 0x00, /* 9D DAI2 EQ3 */ 226 { 0xab, 0x00 }, /* AB DAI2 EQ4 */
225 0x00, /* 9E DAI2 EQ3 */ 227 { 0xac, 0x00 }, /* AC DAI2 EQ5 */
226 0x00, /* 9F DAI2 EQ3 */ 228 { 0xad, 0x00 }, /* AD DAI2 EQ5 */
227 229 { 0xae, 0x00 }, /* AE DAI2 EQ5 */
228 0x00, /* A0 DAI2 EQ3 */ 230 { 0xaf, 0x00 }, /* AF DAI2 EQ5 */
229 0x00, /* A1 DAI2 EQ3 */ 231
230 0x00, /* A2 DAI2 EQ4 */ 232 { 0xb0, 0x00 }, /* B0 DAI2 EQ5 */
231 0x00, /* A3 DAI2 EQ4 */ 233 { 0xb1, 0x00 }, /* B1 DAI2 EQ5 */
232 0x00, /* A4 DAI2 EQ4 */ 234 { 0xb2, 0x00 }, /* B2 DAI2 EQ5 */
233 0x00, /* A5 DAI2 EQ4 */ 235 { 0xb3, 0x00 }, /* B3 DAI2 EQ5 */
234 0x00, /* A6 DAI2 EQ4 */ 236 { 0xb4, 0x00 }, /* B4 DAI2 EQ5 */
235 0x00, /* A7 DAI2 EQ4 */ 237 { 0xb5, 0x00 }, /* B5 DAI2 EQ5 */
236 0x00, /* A8 DAI2 EQ4 */ 238 { 0xb6, 0x00 }, /* B6 DAI1 biquad */
237 0x00, /* A9 DAI2 EQ4 */ 239 { 0xb7, 0x00 }, /* B7 DAI1 biquad */
238 0x00, /* AA DAI2 EQ4 */ 240 { 0xb8 ,0x00 }, /* B8 DAI1 biquad */
239 0x00, /* AB DAI2 EQ4 */ 241 { 0xb9, 0x00 }, /* B9 DAI1 biquad */
240 0x00, /* AC DAI2 EQ5 */ 242 { 0xba, 0x00 }, /* BA DAI1 biquad */
241 0x00, /* AD DAI2 EQ5 */ 243 { 0xbb, 0x00 }, /* BB DAI1 biquad */
242 0x00, /* AE DAI2 EQ5 */ 244 { 0xbc, 0x00 }, /* BC DAI1 biquad */
243 0x00, /* AF DAI2 EQ5 */ 245 { 0xbd, 0x00 }, /* BD DAI1 biquad */
244 246 { 0xbe, 0x00 }, /* BE DAI1 biquad */
245 0x00, /* B0 DAI2 EQ5 */ 247 { 0xbf, 0x00 }, /* BF DAI1 biquad */
246 0x00, /* B1 DAI2 EQ5 */ 248
247 0x00, /* B2 DAI2 EQ5 */ 249 { 0xc0, 0x00 }, /* C0 DAI2 biquad */
248 0x00, /* B3 DAI2 EQ5 */ 250 { 0xc1, 0x00 }, /* C1 DAI2 biquad */
249 0x00, /* B4 DAI2 EQ5 */ 251 { 0xc2, 0x00 }, /* C2 DAI2 biquad */
250 0x00, /* B5 DAI2 EQ5 */ 252 { 0xc3, 0x00 }, /* C3 DAI2 biquad */
251 0x00, /* B6 DAI1 biquad */ 253 { 0xc4, 0x00 }, /* C4 DAI2 biquad */
252 0x00, /* B7 DAI1 biquad */ 254 { 0xc5, 0x00 }, /* C5 DAI2 biquad */
253 0x00, /* B8 DAI1 biquad */ 255 { 0xc6, 0x00 }, /* C6 DAI2 biquad */
254 0x00, /* B9 DAI1 biquad */ 256 { 0xc7, 0x00 }, /* C7 DAI2 biquad */
255 0x00, /* BA DAI1 biquad */ 257 { 0xc8, 0x00 }, /* C8 DAI2 biquad */
256 0x00, /* BB DAI1 biquad */ 258 { 0xc9, 0x00 }, /* C9 DAI2 biquad */
257 0x00, /* BC DAI1 biquad */
258 0x00, /* BD DAI1 biquad */
259 0x00, /* BE DAI1 biquad */
260 0x00, /* BF DAI1 biquad */
261
262 0x00, /* C0 DAI2 biquad */
263 0x00, /* C1 DAI2 biquad */
264 0x00, /* C2 DAI2 biquad */
265 0x00, /* C3 DAI2 biquad */
266 0x00, /* C4 DAI2 biquad */
267 0x00, /* C5 DAI2 biquad */
268 0x00, /* C6 DAI2 biquad */
269 0x00, /* C7 DAI2 biquad */
270 0x00, /* C8 DAI2 biquad */
271 0x00, /* C9 DAI2 biquad */
272 0x00, /* CA */
273 0x00, /* CB */
274 0x00, /* CC */
275 0x00, /* CD */
276 0x00, /* CE */
277 0x00, /* CF */
278
279 0x00, /* D0 */
280 0x00, /* D1 */
281 0x00, /* D2 */
282 0x00, /* D3 */
283 0x00, /* D4 */
284 0x00, /* D5 */
285 0x00, /* D6 */
286 0x00, /* D7 */
287 0x00, /* D8 */
288 0x00, /* D9 */
289 0x00, /* DA */
290 0x70, /* DB */
291 0x00, /* DC */
292 0x00, /* DD */
293 0x00, /* DE */
294 0x00, /* DF */
295
296 0x00, /* E0 */
297 0x00, /* E1 */
298 0x00, /* E2 */
299 0x00, /* E3 */
300 0x00, /* E4 */
301 0x00, /* E5 */
302 0x00, /* E6 */
303 0x00, /* E7 */
304 0x00, /* E8 */
305 0x00, /* E9 */
306 0x00, /* EA */
307 0x00, /* EB */
308 0x00, /* EC */
309 0x00, /* ED */
310 0x00, /* EE */
311 0x00, /* EF */
312
313 0x00, /* F0 */
314 0x00, /* F1 */
315 0x00, /* F2 */
316 0x00, /* F3 */
317 0x00, /* F4 */
318 0x00, /* F5 */
319 0x00, /* F6 */
320 0x00, /* F7 */
321 0x00, /* F8 */
322 0x00, /* F9 */
323 0x00, /* FA */
324 0x00, /* FB */
325 0x00, /* FC */
326 0x00, /* FD */
327 0x00, /* FE */
328 0x00, /* FF */
329}; 259};
330 260
331static struct { 261static struct {
@@ -606,11 +536,28 @@ static struct {
606 { 0xFF, 0x00, 1 }, /* FF */ 536 { 0xFF, 0x00, 1 }, /* FF */
607}; 537};
608 538
609static int max98088_volatile_register(struct snd_soc_codec *codec, unsigned int reg) 539static bool max98088_readable_register(struct device *dev, unsigned int reg)
540{
541 return max98088_access[reg].readable;
542}
543
544static bool max98088_volatile_register(struct device *dev, unsigned int reg)
610{ 545{
611 return max98088_access[reg].vol; 546 return max98088_access[reg].vol;
612} 547}
613 548
549static const struct regmap_config max98088_regmap = {
550 .reg_bits = 8,
551 .val_bits = 8,
552
553 .readable_reg = max98088_readable_register,
554 .volatile_reg = max98088_volatile_register,
555 .max_register = 0xff,
556
557 .reg_defaults = max98088_reg,
558 .num_reg_defaults = ARRAY_SIZE(max98088_reg),
559 .cache_type = REGCACHE_RBTREE,
560};
614 561
615/* 562/*
616 * Load equalizer DSP coefficient configurations registers 563 * Load equalizer DSP coefficient configurations registers
@@ -1610,58 +1557,34 @@ static int max98088_dai2_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1610 return 0; 1557 return 0;
1611} 1558}
1612 1559
1613static void max98088_sync_cache(struct snd_soc_codec *codec)
1614{
1615 u8 *reg_cache = codec->reg_cache;
1616 int i;
1617
1618 if (!codec->cache_sync)
1619 return;
1620
1621 codec->cache_only = 0;
1622
1623 /* write back cached values if they're writeable and
1624 * different from the hardware default.
1625 */
1626 for (i = 1; i < codec->driver->reg_cache_size; i++) {
1627 if (!max98088_access[i].writable)
1628 continue;
1629
1630 if (reg_cache[i] == max98088_reg[i])
1631 continue;
1632
1633 snd_soc_write(codec, i, reg_cache[i]);
1634 }
1635
1636 codec->cache_sync = 0;
1637}
1638
1639static int max98088_set_bias_level(struct snd_soc_codec *codec, 1560static int max98088_set_bias_level(struct snd_soc_codec *codec,
1640 enum snd_soc_bias_level level) 1561 enum snd_soc_bias_level level)
1641{ 1562{
1642 switch (level) { 1563 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec);
1643 case SND_SOC_BIAS_ON: 1564
1644 break; 1565 switch (level) {
1645 1566 case SND_SOC_BIAS_ON:
1646 case SND_SOC_BIAS_PREPARE: 1567 break;
1647 break; 1568
1648 1569 case SND_SOC_BIAS_PREPARE:
1649 case SND_SOC_BIAS_STANDBY: 1570 break;
1650 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) 1571
1651 max98088_sync_cache(codec); 1572 case SND_SOC_BIAS_STANDBY:
1652 1573 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1653 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN, 1574 regcache_sync(max98088->regmap);
1654 M98088_MBEN, M98088_MBEN); 1575
1655 break; 1576 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
1656 1577 M98088_MBEN, M98088_MBEN);
1657 case SND_SOC_BIAS_OFF: 1578 break;
1658 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN, 1579
1659 M98088_MBEN, 0); 1580 case SND_SOC_BIAS_OFF:
1660 codec->cache_sync = 1; 1581 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN,
1661 break; 1582 M98088_MBEN, 0);
1662 } 1583 regcache_mark_dirty(max98088->regmap);
1663 codec->dapm.bias_level = level; 1584 break;
1664 return 0; 1585 }
1586 codec->dapm.bias_level = level;
1587 return 0;
1665} 1588}
1666 1589
1667#define MAX98088_RATES SNDRV_PCM_RATE_8000_96000 1590#define MAX98088_RATES SNDRV_PCM_RATE_8000_96000
@@ -1988,9 +1911,9 @@ static int max98088_probe(struct snd_soc_codec *codec)
1988 struct max98088_cdata *cdata; 1911 struct max98088_cdata *cdata;
1989 int ret = 0; 1912 int ret = 0;
1990 1913
1991 codec->cache_sync = 1; 1914 regcache_mark_dirty(max98088->regmap);
1992 1915
1993 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); 1916 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
1994 if (ret != 0) { 1917 if (ret != 0) {
1995 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1918 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1996 return ret; 1919 return ret;
@@ -2048,9 +1971,6 @@ static int max98088_probe(struct snd_soc_codec *codec)
2048 1971
2049 max98088_handle_pdata(codec); 1972 max98088_handle_pdata(codec);
2050 1973
2051 snd_soc_add_codec_controls(codec, max98088_snd_controls,
2052 ARRAY_SIZE(max98088_snd_controls));
2053
2054err_access: 1974err_access:
2055 return ret; 1975 return ret;
2056} 1976}
@@ -2066,15 +1986,13 @@ static int max98088_remove(struct snd_soc_codec *codec)
2066} 1986}
2067 1987
2068static struct snd_soc_codec_driver soc_codec_dev_max98088 = { 1988static struct snd_soc_codec_driver soc_codec_dev_max98088 = {
2069 .probe = max98088_probe, 1989 .probe = max98088_probe,
2070 .remove = max98088_remove, 1990 .remove = max98088_remove,
2071 .suspend = max98088_suspend, 1991 .suspend = max98088_suspend,
2072 .resume = max98088_resume, 1992 .resume = max98088_resume,
2073 .set_bias_level = max98088_set_bias_level, 1993 .set_bias_level = max98088_set_bias_level,
2074 .reg_cache_size = ARRAY_SIZE(max98088_reg), 1994 .controls = max98088_snd_controls,
2075 .reg_word_size = sizeof(u8), 1995 .num_controls = ARRAY_SIZE(max98088_snd_controls),
2076 .reg_cache_default = max98088_reg,
2077 .volatile_register = max98088_volatile_register,
2078 .dapm_widgets = max98088_dapm_widgets, 1996 .dapm_widgets = max98088_dapm_widgets,
2079 .num_dapm_widgets = ARRAY_SIZE(max98088_dapm_widgets), 1997 .num_dapm_widgets = ARRAY_SIZE(max98088_dapm_widgets),
2080 .dapm_routes = max98088_audio_map, 1998 .dapm_routes = max98088_audio_map,
@@ -2082,7 +2000,7 @@ static struct snd_soc_codec_driver soc_codec_dev_max98088 = {
2082}; 2000};
2083 2001
2084static int max98088_i2c_probe(struct i2c_client *i2c, 2002static int max98088_i2c_probe(struct i2c_client *i2c,
2085 const struct i2c_device_id *id) 2003 const struct i2c_device_id *id)
2086{ 2004{
2087 struct max98088_priv *max98088; 2005 struct max98088_priv *max98088;
2088 int ret; 2006 int ret;
@@ -2092,6 +2010,10 @@ static int max98088_i2c_probe(struct i2c_client *i2c,
2092 if (max98088 == NULL) 2010 if (max98088 == NULL)
2093 return -ENOMEM; 2011 return -ENOMEM;
2094 2012
2013 max98088->regmap = devm_regmap_init_i2c(i2c, &max98088_regmap);
2014 if (IS_ERR(max98088->regmap))
2015 return PTR_ERR(max98088->regmap);
2016
2095 max98088->devtype = id->driver_data; 2017 max98088->devtype = id->driver_data;
2096 2018
2097 i2c_set_clientdata(i2c, max98088); 2019 i2c_set_clientdata(i2c, max98088);
diff --git a/sound/soc/codecs/max98095.c b/sound/soc/codecs/max98095.c
index 8dbcacd44e6a..8fb072455802 100644
--- a/sound/soc/codecs/max98095.c
+++ b/sound/soc/codecs/max98095.c
@@ -39,6 +39,7 @@ struct max98095_cdata {
39}; 39};
40 40
41struct max98095_priv { 41struct max98095_priv {
42 struct regmap *regmap;
42 enum max98095_type devtype; 43 enum max98095_type devtype;
43 struct max98095_pdata *pdata; 44 struct max98095_pdata *pdata;
44 unsigned int sysclk; 45 unsigned int sysclk;
@@ -56,263 +57,145 @@ struct max98095_priv {
56 struct snd_soc_jack *mic_jack; 57 struct snd_soc_jack *mic_jack;
57}; 58};
58 59
59static const u8 max98095_reg_def[M98095_REG_CNT] = { 60static const struct reg_default max98095_reg_def[] = {
60 0x00, /* 00 */ 61 { 0xf, 0x00 }, /* 0F */
61 0x00, /* 01 */ 62 { 0x10, 0x00 }, /* 10 */
62 0x00, /* 02 */ 63 { 0x11, 0x00 }, /* 11 */
63 0x00, /* 03 */ 64 { 0x12, 0x00 }, /* 12 */
64 0x00, /* 04 */ 65 { 0x13, 0x00 }, /* 13 */
65 0x00, /* 05 */ 66 { 0x14, 0x00 }, /* 14 */
66 0x00, /* 06 */ 67 { 0x15, 0x00 }, /* 15 */
67 0x00, /* 07 */ 68 { 0x16, 0x00 }, /* 16 */
68 0x00, /* 08 */ 69 { 0x17, 0x00 }, /* 17 */
69 0x00, /* 09 */ 70 { 0x18, 0x00 }, /* 18 */
70 0x00, /* 0A */ 71 { 0x19, 0x00 }, /* 19 */
71 0x00, /* 0B */ 72 { 0x1a, 0x00 }, /* 1A */
72 0x00, /* 0C */ 73 { 0x1b, 0x00 }, /* 1B */
73 0x00, /* 0D */ 74 { 0x1c, 0x00 }, /* 1C */
74 0x00, /* 0E */ 75 { 0x1d, 0x00 }, /* 1D */
75 0x00, /* 0F */ 76 { 0x1e, 0x00 }, /* 1E */
76 0x00, /* 10 */ 77 { 0x1f, 0x00 }, /* 1F */
77 0x00, /* 11 */ 78 { 0x20, 0x00 }, /* 20 */
78 0x00, /* 12 */ 79 { 0x21, 0x00 }, /* 21 */
79 0x00, /* 13 */ 80 { 0x22, 0x00 }, /* 22 */
80 0x00, /* 14 */ 81 { 0x23, 0x00 }, /* 23 */
81 0x00, /* 15 */ 82 { 0x24, 0x00 }, /* 24 */
82 0x00, /* 16 */ 83 { 0x25, 0x00 }, /* 25 */
83 0x00, /* 17 */ 84 { 0x26, 0x00 }, /* 26 */
84 0x00, /* 18 */ 85 { 0x27, 0x00 }, /* 27 */
85 0x00, /* 19 */ 86 { 0x28, 0x00 }, /* 28 */
86 0x00, /* 1A */ 87 { 0x29, 0x00 }, /* 29 */
87 0x00, /* 1B */ 88 { 0x2a, 0x00 }, /* 2A */
88 0x00, /* 1C */ 89 { 0x2b, 0x00 }, /* 2B */
89 0x00, /* 1D */ 90 { 0x2c, 0x00 }, /* 2C */
90 0x00, /* 1E */ 91 { 0x2d, 0x00 }, /* 2D */
91 0x00, /* 1F */ 92 { 0x2e, 0x00 }, /* 2E */
92 0x00, /* 20 */ 93 { 0x2f, 0x00 }, /* 2F */
93 0x00, /* 21 */ 94 { 0x30, 0x00 }, /* 30 */
94 0x00, /* 22 */ 95 { 0x31, 0x00 }, /* 31 */
95 0x00, /* 23 */ 96 { 0x32, 0x00 }, /* 32 */
96 0x00, /* 24 */ 97 { 0x33, 0x00 }, /* 33 */
97 0x00, /* 25 */ 98 { 0x34, 0x00 }, /* 34 */
98 0x00, /* 26 */ 99 { 0x35, 0x00 }, /* 35 */
99 0x00, /* 27 */ 100 { 0x36, 0x00 }, /* 36 */
100 0x00, /* 28 */ 101 { 0x37, 0x00 }, /* 37 */
101 0x00, /* 29 */ 102 { 0x38, 0x00 }, /* 38 */
102 0x00, /* 2A */ 103 { 0x39, 0x00 }, /* 39 */
103 0x00, /* 2B */ 104 { 0x3a, 0x00 }, /* 3A */
104 0x00, /* 2C */ 105 { 0x3b, 0x00 }, /* 3B */
105 0x00, /* 2D */ 106 { 0x3c, 0x00 }, /* 3C */
106 0x00, /* 2E */ 107 { 0x3d, 0x00 }, /* 3D */
107 0x00, /* 2F */ 108 { 0x3e, 0x00 }, /* 3E */
108 0x00, /* 30 */ 109 { 0x3f, 0x00 }, /* 3F */
109 0x00, /* 31 */ 110 { 0x40, 0x00 }, /* 40 */
110 0x00, /* 32 */ 111 { 0x41, 0x00 }, /* 41 */
111 0x00, /* 33 */ 112 { 0x42, 0x00 }, /* 42 */
112 0x00, /* 34 */ 113 { 0x43, 0x00 }, /* 43 */
113 0x00, /* 35 */ 114 { 0x44, 0x00 }, /* 44 */
114 0x00, /* 36 */ 115 { 0x45, 0x00 }, /* 45 */
115 0x00, /* 37 */ 116 { 0x46, 0x00 }, /* 46 */
116 0x00, /* 38 */ 117 { 0x47, 0x00 }, /* 47 */
117 0x00, /* 39 */ 118 { 0x48, 0x00 }, /* 48 */
118 0x00, /* 3A */ 119 { 0x49, 0x00 }, /* 49 */
119 0x00, /* 3B */ 120 { 0x4a, 0x00 }, /* 4A */
120 0x00, /* 3C */ 121 { 0x4b, 0x00 }, /* 4B */
121 0x00, /* 3D */ 122 { 0x4c, 0x00 }, /* 4C */
122 0x00, /* 3E */ 123 { 0x4d, 0x00 }, /* 4D */
123 0x00, /* 3F */ 124 { 0x4e, 0x00 }, /* 4E */
124 0x00, /* 40 */ 125 { 0x4f, 0x00 }, /* 4F */
125 0x00, /* 41 */ 126 { 0x50, 0x00 }, /* 50 */
126 0x00, /* 42 */ 127 { 0x51, 0x00 }, /* 51 */
127 0x00, /* 43 */ 128 { 0x52, 0x00 }, /* 52 */
128 0x00, /* 44 */ 129 { 0x53, 0x00 }, /* 53 */
129 0x00, /* 45 */ 130 { 0x54, 0x00 }, /* 54 */
130 0x00, /* 46 */ 131 { 0x55, 0x00 }, /* 55 */
131 0x00, /* 47 */ 132 { 0x56, 0x00 }, /* 56 */
132 0x00, /* 48 */ 133 { 0x57, 0x00 }, /* 57 */
133 0x00, /* 49 */ 134 { 0x58, 0x00 }, /* 58 */
134 0x00, /* 4A */ 135 { 0x59, 0x00 }, /* 59 */
135 0x00, /* 4B */ 136 { 0x5a, 0x00 }, /* 5A */
136 0x00, /* 4C */ 137 { 0x5b, 0x00 }, /* 5B */
137 0x00, /* 4D */ 138 { 0x5c, 0x00 }, /* 5C */
138 0x00, /* 4E */ 139 { 0x5d, 0x00 }, /* 5D */
139 0x00, /* 4F */ 140 { 0x5e, 0x00 }, /* 5E */
140 0x00, /* 50 */ 141 { 0x5f, 0x00 }, /* 5F */
141 0x00, /* 51 */ 142 { 0x60, 0x00 }, /* 60 */
142 0x00, /* 52 */ 143 { 0x61, 0x00 }, /* 61 */
143 0x00, /* 53 */ 144 { 0x62, 0x00 }, /* 62 */
144 0x00, /* 54 */ 145 { 0x63, 0x00 }, /* 63 */
145 0x00, /* 55 */ 146 { 0x64, 0x00 }, /* 64 */
146 0x00, /* 56 */ 147 { 0x65, 0x00 }, /* 65 */
147 0x00, /* 57 */ 148 { 0x66, 0x00 }, /* 66 */
148 0x00, /* 58 */ 149 { 0x67, 0x00 }, /* 67 */
149 0x00, /* 59 */ 150 { 0x68, 0x00 }, /* 68 */
150 0x00, /* 5A */ 151 { 0x69, 0x00 }, /* 69 */
151 0x00, /* 5B */ 152 { 0x6a, 0x00 }, /* 6A */
152 0x00, /* 5C */ 153 { 0x6b, 0x00 }, /* 6B */
153 0x00, /* 5D */ 154 { 0x6c, 0x00 }, /* 6C */
154 0x00, /* 5E */ 155 { 0x6d, 0x00 }, /* 6D */
155 0x00, /* 5F */ 156 { 0x6e, 0x00 }, /* 6E */
156 0x00, /* 60 */ 157 { 0x6f, 0x00 }, /* 6F */
157 0x00, /* 61 */ 158 { 0x70, 0x00 }, /* 70 */
158 0x00, /* 62 */ 159 { 0x71, 0x00 }, /* 71 */
159 0x00, /* 63 */ 160 { 0x72, 0x00 }, /* 72 */
160 0x00, /* 64 */ 161 { 0x73, 0x00 }, /* 73 */
161 0x00, /* 65 */ 162 { 0x74, 0x00 }, /* 74 */
162 0x00, /* 66 */ 163 { 0x75, 0x00 }, /* 75 */
163 0x00, /* 67 */ 164 { 0x76, 0x00 }, /* 76 */
164 0x00, /* 68 */ 165 { 0x77, 0x00 }, /* 77 */
165 0x00, /* 69 */ 166 { 0x78, 0x00 }, /* 78 */
166 0x00, /* 6A */ 167 { 0x79, 0x00 }, /* 79 */
167 0x00, /* 6B */ 168 { 0x7a, 0x00 }, /* 7A */
168 0x00, /* 6C */ 169 { 0x7b, 0x00 }, /* 7B */
169 0x00, /* 6D */ 170 { 0x7c, 0x00 }, /* 7C */
170 0x00, /* 6E */ 171 { 0x7d, 0x00 }, /* 7D */
171 0x00, /* 6F */ 172 { 0x7e, 0x00 }, /* 7E */
172 0x00, /* 70 */ 173 { 0x7f, 0x00 }, /* 7F */
173 0x00, /* 71 */ 174 { 0x80, 0x00 }, /* 80 */
174 0x00, /* 72 */ 175 { 0x81, 0x00 }, /* 81 */
175 0x00, /* 73 */ 176 { 0x82, 0x00 }, /* 82 */
176 0x00, /* 74 */ 177 { 0x83, 0x00 }, /* 83 */
177 0x00, /* 75 */ 178 { 0x84, 0x00 }, /* 84 */
178 0x00, /* 76 */ 179 { 0x85, 0x00 }, /* 85 */
179 0x00, /* 77 */ 180 { 0x86, 0x00 }, /* 86 */
180 0x00, /* 78 */ 181 { 0x87, 0x00 }, /* 87 */
181 0x00, /* 79 */ 182 { 0x88, 0x00 }, /* 88 */
182 0x00, /* 7A */ 183 { 0x89, 0x00 }, /* 89 */
183 0x00, /* 7B */ 184 { 0x8a, 0x00 }, /* 8A */
184 0x00, /* 7C */ 185 { 0x8b, 0x00 }, /* 8B */
185 0x00, /* 7D */ 186 { 0x8c, 0x00 }, /* 8C */
186 0x00, /* 7E */ 187 { 0x8d, 0x00 }, /* 8D */
187 0x00, /* 7F */ 188 { 0x8e, 0x00 }, /* 8E */
188 0x00, /* 80 */ 189 { 0x8f, 0x00 }, /* 8F */
189 0x00, /* 81 */ 190 { 0x90, 0x00 }, /* 90 */
190 0x00, /* 82 */ 191 { 0x91, 0x00 }, /* 91 */
191 0x00, /* 83 */ 192 { 0x92, 0x30 }, /* 92 */
192 0x00, /* 84 */ 193 { 0x93, 0xF0 }, /* 93 */
193 0x00, /* 85 */ 194 { 0x94, 0x00 }, /* 94 */
194 0x00, /* 86 */ 195 { 0x95, 0x00 }, /* 95 */
195 0x00, /* 87 */ 196 { 0x96, 0x3F }, /* 96 */
196 0x00, /* 88 */ 197 { 0x97, 0x00 }, /* 97 */
197 0x00, /* 89 */ 198 { 0xff, 0x00 }, /* FF */
198 0x00, /* 8A */
199 0x00, /* 8B */
200 0x00, /* 8C */
201 0x00, /* 8D */
202 0x00, /* 8E */
203 0x00, /* 8F */
204 0x00, /* 90 */
205 0x00, /* 91 */
206 0x30, /* 92 */
207 0xF0, /* 93 */
208 0x00, /* 94 */
209 0x00, /* 95 */
210 0x3F, /* 96 */
211 0x00, /* 97 */
212 0x00, /* 98 */
213 0x00, /* 99 */
214 0x00, /* 9A */
215 0x00, /* 9B */
216 0x00, /* 9C */
217 0x00, /* 9D */
218 0x00, /* 9E */
219 0x00, /* 9F */
220 0x00, /* A0 */
221 0x00, /* A1 */
222 0x00, /* A2 */
223 0x00, /* A3 */
224 0x00, /* A4 */
225 0x00, /* A5 */
226 0x00, /* A6 */
227 0x00, /* A7 */
228 0x00, /* A8 */
229 0x00, /* A9 */
230 0x00, /* AA */
231 0x00, /* AB */
232 0x00, /* AC */
233 0x00, /* AD */
234 0x00, /* AE */
235 0x00, /* AF */
236 0x00, /* B0 */
237 0x00, /* B1 */
238 0x00, /* B2 */
239 0x00, /* B3 */
240 0x00, /* B4 */
241 0x00, /* B5 */
242 0x00, /* B6 */
243 0x00, /* B7 */
244 0x00, /* B8 */
245 0x00, /* B9 */
246 0x00, /* BA */
247 0x00, /* BB */
248 0x00, /* BC */
249 0x00, /* BD */
250 0x00, /* BE */
251 0x00, /* BF */
252 0x00, /* C0 */
253 0x00, /* C1 */
254 0x00, /* C2 */
255 0x00, /* C3 */
256 0x00, /* C4 */
257 0x00, /* C5 */
258 0x00, /* C6 */
259 0x00, /* C7 */
260 0x00, /* C8 */
261 0x00, /* C9 */
262 0x00, /* CA */
263 0x00, /* CB */
264 0x00, /* CC */
265 0x00, /* CD */
266 0x00, /* CE */
267 0x00, /* CF */
268 0x00, /* D0 */
269 0x00, /* D1 */
270 0x00, /* D2 */
271 0x00, /* D3 */
272 0x00, /* D4 */
273 0x00, /* D5 */
274 0x00, /* D6 */
275 0x00, /* D7 */
276 0x00, /* D8 */
277 0x00, /* D9 */
278 0x00, /* DA */
279 0x00, /* DB */
280 0x00, /* DC */
281 0x00, /* DD */
282 0x00, /* DE */
283 0x00, /* DF */
284 0x00, /* E0 */
285 0x00, /* E1 */
286 0x00, /* E2 */
287 0x00, /* E3 */
288 0x00, /* E4 */
289 0x00, /* E5 */
290 0x00, /* E6 */
291 0x00, /* E7 */
292 0x00, /* E8 */
293 0x00, /* E9 */
294 0x00, /* EA */
295 0x00, /* EB */
296 0x00, /* EC */
297 0x00, /* ED */
298 0x00, /* EE */
299 0x00, /* EF */
300 0x00, /* F0 */
301 0x00, /* F1 */
302 0x00, /* F2 */
303 0x00, /* F3 */
304 0x00, /* F4 */
305 0x00, /* F5 */
306 0x00, /* F6 */
307 0x00, /* F7 */
308 0x00, /* F8 */
309 0x00, /* F9 */
310 0x00, /* FA */
311 0x00, /* FB */
312 0x00, /* FC */
313 0x00, /* FD */
314 0x00, /* FE */
315 0x00, /* FF */
316}; 199};
317 200
318static struct { 201static struct {
@@ -577,14 +460,14 @@ static struct {
577 { 0xFF, 0x00 }, /* FF */ 460 { 0xFF, 0x00 }, /* FF */
578}; 461};
579 462
580static int max98095_readable(struct snd_soc_codec *codec, unsigned int reg) 463static bool max98095_readable(struct device *dev, unsigned int reg)
581{ 464{
582 if (reg >= M98095_REG_CNT) 465 if (reg >= M98095_REG_CNT)
583 return 0; 466 return 0;
584 return max98095_access[reg].readable != 0; 467 return max98095_access[reg].readable != 0;
585} 468}
586 469
587static int max98095_volatile(struct snd_soc_codec *codec, unsigned int reg) 470static bool max98095_volatile(struct device *dev, unsigned int reg)
588{ 471{
589 if (reg > M98095_REG_MAX_CACHED) 472 if (reg > M98095_REG_MAX_CACHED)
590 return 1; 473 return 1;
@@ -611,22 +494,18 @@ static int max98095_volatile(struct snd_soc_codec *codec, unsigned int reg)
611 return 0; 494 return 0;
612} 495}
613 496
614/* 497static const struct regmap_config max98095_regmap = {
615 * Filter coefficients are in a separate register segment 498 .reg_bits = 8,
616 * and they share the address space of the normal registers. 499 .val_bits = 8,
617 * The coefficient registers do not need or share the cache.
618 */
619static int max98095_hw_write(struct snd_soc_codec *codec, unsigned int reg,
620 unsigned int value)
621{
622 int ret;
623 500
624 codec->cache_bypass = 1; 501 .reg_defaults = max98095_reg_def,
625 ret = snd_soc_write(codec, reg, value); 502 .num_reg_defaults = ARRAY_SIZE(max98095_reg_def),
626 codec->cache_bypass = 0; 503 .max_register = M98095_0FF_REV_ID,
504 .cache_type = REGCACHE_RBTREE,
627 505
628 return ret ? -EIO : 0; 506 .readable_reg = max98095_readable,
629} 507 .volatile_reg = max98095_volatile,
508};
630 509
631/* 510/*
632 * Load equalizer DSP coefficient configurations registers 511 * Load equalizer DSP coefficient configurations registers
@@ -648,8 +527,8 @@ static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai,
648 527
649 /* Step through the registers and coefs */ 528 /* Step through the registers and coefs */
650 for (i = 0; i < M98095_COEFS_PER_BAND; i++) { 529 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
651 max98095_hw_write(codec, eq_reg++, M98095_BYTE1(coefs[i])); 530 snd_soc_write(codec, eq_reg++, M98095_BYTE1(coefs[i]));
652 max98095_hw_write(codec, eq_reg++, M98095_BYTE0(coefs[i])); 531 snd_soc_write(codec, eq_reg++, M98095_BYTE0(coefs[i]));
653 } 532 }
654} 533}
655 534
@@ -673,8 +552,8 @@ static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai,
673 552
674 /* Step through the registers and coefs */ 553 /* Step through the registers and coefs */
675 for (i = 0; i < M98095_COEFS_PER_BAND; i++) { 554 for (i = 0; i < M98095_COEFS_PER_BAND; i++) {
676 max98095_hw_write(codec, bq_reg++, M98095_BYTE1(coefs[i])); 555 snd_soc_write(codec, bq_reg++, M98095_BYTE1(coefs[i]));
677 max98095_hw_write(codec, bq_reg++, M98095_BYTE0(coefs[i])); 556 snd_soc_write(codec, bq_reg++, M98095_BYTE0(coefs[i]));
678 } 557 }
679} 558}
680 559
@@ -1285,14 +1164,6 @@ static const struct snd_soc_dapm_route max98095_audio_map[] = {
1285 {"MIC2 Input", NULL, "MIC2"}, 1164 {"MIC2 Input", NULL, "MIC2"},
1286}; 1165};
1287 1166
1288static int max98095_add_widgets(struct snd_soc_codec *codec)
1289{
1290 snd_soc_add_codec_controls(codec, max98095_snd_controls,
1291 ARRAY_SIZE(max98095_snd_controls));
1292
1293 return 0;
1294}
1295
1296/* codec mclk clock divider coefficients */ 1167/* codec mclk clock divider coefficients */
1297static const struct { 1168static const struct {
1298 u32 rate; 1169 u32 rate;
@@ -1748,6 +1619,7 @@ static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai,
1748static int max98095_set_bias_level(struct snd_soc_codec *codec, 1619static int max98095_set_bias_level(struct snd_soc_codec *codec,
1749 enum snd_soc_bias_level level) 1620 enum snd_soc_bias_level level)
1750{ 1621{
1622 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec);
1751 int ret; 1623 int ret;
1752 1624
1753 switch (level) { 1625 switch (level) {
@@ -1759,7 +1631,7 @@ static int max98095_set_bias_level(struct snd_soc_codec *codec,
1759 1631
1760 case SND_SOC_BIAS_STANDBY: 1632 case SND_SOC_BIAS_STANDBY:
1761 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1633 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1762 ret = snd_soc_cache_sync(codec); 1634 ret = regcache_sync(max98095->regmap);
1763 1635
1764 if (ret != 0) { 1636 if (ret != 0) {
1765 dev_err(codec->dev, "Failed to sync cache: %d\n", ret); 1637 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
@@ -1774,7 +1646,7 @@ static int max98095_set_bias_level(struct snd_soc_codec *codec,
1774 case SND_SOC_BIAS_OFF: 1646 case SND_SOC_BIAS_OFF:
1775 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, 1647 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN,
1776 M98095_MBEN, 0); 1648 M98095_MBEN, 0);
1777 codec->cache_sync = 1; 1649 regcache_mark_dirty(max98095->regmap);
1778 break; 1650 break;
1779 } 1651 }
1780 codec->dapm.bias_level = level; 1652 codec->dapm.bias_level = level;
@@ -2341,7 +2213,7 @@ static int max98095_reset(struct snd_soc_codec *codec)
2341 /* Reset to hardware default for registers, as there is not 2213 /* Reset to hardware default for registers, as there is not
2342 * a soft reset hardware control register */ 2214 * a soft reset hardware control register */
2343 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) { 2215 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
2344 ret = snd_soc_write(codec, i, max98095_reg_def[i]); 2216 ret = snd_soc_write(codec, i, snd_soc_read(codec, i));
2345 if (ret < 0) { 2217 if (ret < 0) {
2346 dev_err(codec->dev, "Failed to reset: %d\n", ret); 2218 dev_err(codec->dev, "Failed to reset: %d\n", ret);
2347 return ret; 2219 return ret;
@@ -2358,7 +2230,7 @@ static int max98095_probe(struct snd_soc_codec *codec)
2358 struct i2c_client *client; 2230 struct i2c_client *client;
2359 int ret = 0; 2231 int ret = 0;
2360 2232
2361 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); 2233 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
2362 if (ret != 0) { 2234 if (ret != 0) {
2363 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 2235 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2364 return ret; 2236 return ret;
@@ -2447,8 +2319,6 @@ static int max98095_probe(struct snd_soc_codec *codec)
2447 snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN, 2319 snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN,
2448 M98095_SHDNRUN); 2320 M98095_SHDNRUN);
2449 2321
2450 max98095_add_widgets(codec);
2451
2452 return 0; 2322 return 0;
2453 2323
2454err_irq: 2324err_irq:
@@ -2480,11 +2350,8 @@ static struct snd_soc_codec_driver soc_codec_dev_max98095 = {
2480 .suspend = max98095_suspend, 2350 .suspend = max98095_suspend,
2481 .resume = max98095_resume, 2351 .resume = max98095_resume,
2482 .set_bias_level = max98095_set_bias_level, 2352 .set_bias_level = max98095_set_bias_level,
2483 .reg_cache_size = ARRAY_SIZE(max98095_reg_def), 2353 .controls = max98095_snd_controls,
2484 .reg_word_size = sizeof(u8), 2354 .num_controls = ARRAY_SIZE(max98095_snd_controls),
2485 .reg_cache_default = max98095_reg_def,
2486 .readable_register = max98095_readable,
2487 .volatile_register = max98095_volatile,
2488 .dapm_widgets = max98095_dapm_widgets, 2355 .dapm_widgets = max98095_dapm_widgets,
2489 .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets), 2356 .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets),
2490 .dapm_routes = max98095_audio_map, 2357 .dapm_routes = max98095_audio_map,
@@ -2502,6 +2369,13 @@ static int max98095_i2c_probe(struct i2c_client *i2c,
2502 if (max98095 == NULL) 2369 if (max98095 == NULL)
2503 return -ENOMEM; 2370 return -ENOMEM;
2504 2371
2372 max98095->regmap = devm_regmap_init_i2c(i2c, &max98095_regmap);
2373 if (IS_ERR(max98095->regmap)) {
2374 ret = PTR_ERR(max98095->regmap);
2375 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2376 return ret;
2377 }
2378
2505 max98095->devtype = id->driver_data; 2379 max98095->devtype = id->driver_data;
2506 i2c_set_clientdata(i2c, max98095); 2380 i2c_set_clientdata(i2c, max98095);
2507 max98095->pdata = i2c->dev.platform_data; 2381 max98095->pdata = i2c->dev.platform_data;
diff --git a/sound/soc/codecs/max9850.c b/sound/soc/codecs/max9850.c
index 58c38a5b481c..c5dd61785f8d 100644
--- a/sound/soc/codecs/max9850.c
+++ b/sound/soc/codecs/max9850.c
@@ -18,6 +18,7 @@
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/i2c.h> 20#include <linux/i2c.h>
21#include <linux/regmap.h>
21#include <linux/slab.h> 22#include <linux/slab.h>
22#include <sound/pcm.h> 23#include <sound/pcm.h>
23#include <sound/pcm_params.h> 24#include <sound/pcm_params.h>
@@ -27,18 +28,26 @@
27#include "max9850.h" 28#include "max9850.h"
28 29
29struct max9850_priv { 30struct max9850_priv {
31 struct regmap *regmap;
30 unsigned int sysclk; 32 unsigned int sysclk;
31}; 33};
32 34
33/* max9850 register cache */ 35/* max9850 register cache */
34static const u8 max9850_reg[MAX9850_CACHEREGNUM] = { 36static const struct reg_default max9850_reg[] = {
35 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 37 { 2, 0x0c },
38 { 3, 0x00 },
39 { 4, 0x00 },
40 { 5, 0x00 },
41 { 6, 0x00 },
42 { 7, 0x00 },
43 { 8, 0x00 },
44 { 9, 0x00 },
45 { 10, 0x00 },
36}; 46};
37 47
38/* these registers are not used at the moment but provided for the sake of 48/* these registers are not used at the moment but provided for the sake of
39 * completeness */ 49 * completeness */
40static int max9850_volatile_register(struct snd_soc_codec *codec, 50static bool max9850_volatile_register(struct device *dev, unsigned int reg)
41 unsigned int reg)
42{ 51{
43 switch (reg) { 52 switch (reg) {
44 case MAX9850_STATUSA: 53 case MAX9850_STATUSA:
@@ -49,6 +58,15 @@ static int max9850_volatile_register(struct snd_soc_codec *codec,
49 } 58 }
50} 59}
51 60
61static const struct regmap_config max9850_regmap = {
62 .reg_bits = 8,
63 .val_bits = 8,
64
65 .max_register = MAX9850_DIGITAL_AUDIO,
66 .volatile_reg = max9850_volatile_register,
67 .cache_type = REGCACHE_RBTREE,
68};
69
52static const unsigned int max9850_tlv[] = { 70static const unsigned int max9850_tlv[] = {
53 TLV_DB_RANGE_HEAD(4), 71 TLV_DB_RANGE_HEAD(4),
54 0x18, 0x1f, TLV_DB_SCALE_ITEM(-7450, 400, 0), 72 0x18, 0x1f, TLV_DB_SCALE_ITEM(-7450, 400, 0),
@@ -225,6 +243,7 @@ static int max9850_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
225static int max9850_set_bias_level(struct snd_soc_codec *codec, 243static int max9850_set_bias_level(struct snd_soc_codec *codec,
226 enum snd_soc_bias_level level) 244 enum snd_soc_bias_level level)
227{ 245{
246 struct max9850_priv *max9850 = snd_soc_codec_get_drvdata(codec);
228 int ret; 247 int ret;
229 248
230 switch (level) { 249 switch (level) {
@@ -234,7 +253,7 @@ static int max9850_set_bias_level(struct snd_soc_codec *codec,
234 break; 253 break;
235 case SND_SOC_BIAS_STANDBY: 254 case SND_SOC_BIAS_STANDBY:
236 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 255 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
237 ret = snd_soc_cache_sync(codec); 256 ret = regcache_sync(max9850->regmap);
238 if (ret) { 257 if (ret) {
239 dev_err(codec->dev, 258 dev_err(codec->dev,
240 "Failed to sync cache: %d\n", ret); 259 "Failed to sync cache: %d\n", ret);
@@ -295,7 +314,7 @@ static int max9850_probe(struct snd_soc_codec *codec)
295{ 314{
296 int ret; 315 int ret;
297 316
298 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); 317 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
299 if (ret < 0) { 318 if (ret < 0) {
300 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 319 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
301 return ret; 320 return ret;
@@ -316,10 +335,6 @@ static struct snd_soc_codec_driver soc_codec_dev_max9850 = {
316 .suspend = max9850_suspend, 335 .suspend = max9850_suspend,
317 .resume = max9850_resume, 336 .resume = max9850_resume,
318 .set_bias_level = max9850_set_bias_level, 337 .set_bias_level = max9850_set_bias_level,
319 .reg_cache_size = ARRAY_SIZE(max9850_reg),
320 .reg_word_size = sizeof(u8),
321 .reg_cache_default = max9850_reg,
322 .volatile_register = max9850_volatile_register,
323 338
324 .controls = max9850_controls, 339 .controls = max9850_controls,
325 .num_controls = ARRAY_SIZE(max9850_controls), 340 .num_controls = ARRAY_SIZE(max9850_controls),
@@ -340,6 +355,10 @@ static int max9850_i2c_probe(struct i2c_client *i2c,
340 if (max9850 == NULL) 355 if (max9850 == NULL)
341 return -ENOMEM; 356 return -ENOMEM;
342 357
358 max9850->regmap = devm_regmap_init_i2c(i2c, &max9850_regmap);
359 if (IS_ERR(max9850->regmap))
360 return PTR_ERR(max9850->regmap);
361
343 i2c_set_clientdata(i2c, max9850); 362 i2c_set_clientdata(i2c, max9850);
344 363
345 ret = snd_soc_register_codec(&i2c->dev, 364 ret = snd_soc_register_codec(&i2c->dev,
diff --git a/sound/soc/codecs/mc13783.c b/sound/soc/codecs/mc13783.c
index ea141e1d6f28..f5472adee674 100644
--- a/sound/soc/codecs/mc13783.c
+++ b/sound/soc/codecs/mc13783.c
@@ -30,16 +30,10 @@
30#include <sound/soc.h> 30#include <sound/soc.h>
31#include <sound/initval.h> 31#include <sound/initval.h>
32#include <sound/soc-dapm.h> 32#include <sound/soc-dapm.h>
33#include <linux/regmap.h>
33 34
34#include "mc13783.h" 35#include "mc13783.h"
35 36
36#define MC13783_AUDIO_RX0 36
37#define MC13783_AUDIO_RX1 37
38#define MC13783_AUDIO_TX 38
39#define MC13783_SSI_NETWORK 39
40#define MC13783_AUDIO_CODEC 40
41#define MC13783_AUDIO_DAC 41
42
43#define AUDIO_RX0_ALSPEN (1 << 5) 37#define AUDIO_RX0_ALSPEN (1 << 5)
44#define AUDIO_RX0_ALSPSEL (1 << 7) 38#define AUDIO_RX0_ALSPSEL (1 << 7)
45#define AUDIO_RX0_ADDCDC (1 << 21) 39#define AUDIO_RX0_ADDCDC (1 << 21)
@@ -95,45 +89,12 @@
95 89
96struct mc13783_priv { 90struct mc13783_priv {
97 struct mc13xxx *mc13xxx; 91 struct mc13xxx *mc13xxx;
92 struct regmap *regmap;
98 93
99 enum mc13783_ssi_port adc_ssi_port; 94 enum mc13783_ssi_port adc_ssi_port;
100 enum mc13783_ssi_port dac_ssi_port; 95 enum mc13783_ssi_port dac_ssi_port;
101}; 96};
102 97
103static unsigned int mc13783_read(struct snd_soc_codec *codec,
104 unsigned int reg)
105{
106 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
107 unsigned int value = 0;
108
109 mc13xxx_lock(priv->mc13xxx);
110
111 mc13xxx_reg_read(priv->mc13xxx, reg, &value);
112
113 mc13xxx_unlock(priv->mc13xxx);
114
115 return value;
116}
117
118static int mc13783_write(struct snd_soc_codec *codec,
119 unsigned int reg, unsigned int value)
120{
121 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
122 int ret;
123
124 mc13xxx_lock(priv->mc13xxx);
125
126 ret = mc13xxx_reg_write(priv->mc13xxx, reg, value);
127
128 /* include errata fix for spi audio problems */
129 if (reg == MC13783_AUDIO_CODEC || reg == MC13783_AUDIO_DAC)
130 ret = mc13xxx_reg_write(priv->mc13xxx, reg, value);
131
132 mc13xxx_unlock(priv->mc13xxx);
133
134 return ret;
135}
136
137/* Mapping between sample rates and register value */ 98/* Mapping between sample rates and register value */
138static unsigned int mc13783_rates[] = { 99static unsigned int mc13783_rates[] = {
139 8000, 11025, 12000, 16000, 100 8000, 11025, 12000, 16000,
@@ -466,6 +427,29 @@ static const struct snd_kcontrol_new right_input_mux =
466static const struct snd_kcontrol_new samp_ctl = 427static const struct snd_kcontrol_new samp_ctl =
467 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 3, 1, 0); 428 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 3, 1, 0);
468 429
430static const char * const speaker_amp_source_text[] = {
431 "CODEC", "Right"
432};
433static const SOC_ENUM_SINGLE_DECL(speaker_amp_source, MC13783_AUDIO_RX0, 4,
434 speaker_amp_source_text);
435static const struct snd_kcontrol_new speaker_amp_source_mux =
436 SOC_DAPM_ENUM("Speaker Amp Source MUX", speaker_amp_source);
437
438static const char * const headset_amp_source_text[] = {
439 "CODEC", "Mixer"
440};
441
442static const SOC_ENUM_SINGLE_DECL(headset_amp_source, MC13783_AUDIO_RX0, 11,
443 headset_amp_source_text);
444static const struct snd_kcontrol_new headset_amp_source_mux =
445 SOC_DAPM_ENUM("Headset Amp Source MUX", headset_amp_source);
446
447static const struct snd_kcontrol_new cdcout_ctl =
448 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 18, 1, 0);
449
450static const struct snd_kcontrol_new adc_bypass_ctl =
451 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_CODEC, 16, 1, 0);
452
469static const struct snd_kcontrol_new lamp_ctl = 453static const struct snd_kcontrol_new lamp_ctl =
470 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 5, 1, 0); 454 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 5, 1, 0);
471 455
@@ -503,12 +487,22 @@ static const struct snd_soc_dapm_widget mc13783_dapm_widgets[] = {
503 SND_SOC_DAPM_VIRT_MUX("PGA Right Input Mux", SND_SOC_NOPM, 0, 0, 487 SND_SOC_DAPM_VIRT_MUX("PGA Right Input Mux", SND_SOC_NOPM, 0, 0,
504 &right_input_mux), 488 &right_input_mux),
505 489
490 SND_SOC_DAPM_MUX("Speaker Amp Source MUX", SND_SOC_NOPM, 0, 0,
491 &speaker_amp_source_mux),
492
493 SND_SOC_DAPM_MUX("Headset Amp Source MUX", SND_SOC_NOPM, 0, 0,
494 &headset_amp_source_mux),
495
506 SND_SOC_DAPM_PGA("PGA Left Input", SND_SOC_NOPM, 0, 0, NULL, 0), 496 SND_SOC_DAPM_PGA("PGA Left Input", SND_SOC_NOPM, 0, 0, NULL, 0),
507 SND_SOC_DAPM_PGA("PGA Right Input", SND_SOC_NOPM, 0, 0, NULL, 0), 497 SND_SOC_DAPM_PGA("PGA Right Input", SND_SOC_NOPM, 0, 0, NULL, 0),
508 498
509 SND_SOC_DAPM_ADC("ADC", "Capture", MC13783_AUDIO_CODEC, 11, 0), 499 SND_SOC_DAPM_ADC("ADC", "Capture", MC13783_AUDIO_CODEC, 11, 0),
510 SND_SOC_DAPM_SUPPLY("ADC_Reset", MC13783_AUDIO_CODEC, 15, 0, NULL, 0), 500 SND_SOC_DAPM_SUPPLY("ADC_Reset", MC13783_AUDIO_CODEC, 15, 0, NULL, 0),
511 501
502 SND_SOC_DAPM_PGA("Voice CODEC PGA", MC13783_AUDIO_RX1, 0, 0, NULL, 0),
503 SND_SOC_DAPM_SWITCH("Voice CODEC Bypass", MC13783_AUDIO_CODEC, 16, 0,
504 &adc_bypass_ctl),
505
512/* Output */ 506/* Output */
513 SND_SOC_DAPM_SUPPLY("DAC_E", MC13783_AUDIO_DAC, 11, 0, NULL, 0), 507 SND_SOC_DAPM_SUPPLY("DAC_E", MC13783_AUDIO_DAC, 11, 0, NULL, 0),
514 SND_SOC_DAPM_SUPPLY("DAC_Reset", MC13783_AUDIO_DAC, 15, 0, NULL, 0), 508 SND_SOC_DAPM_SUPPLY("DAC_Reset", MC13783_AUDIO_DAC, 15, 0, NULL, 0),
@@ -516,10 +510,15 @@ static const struct snd_soc_dapm_widget mc13783_dapm_widgets[] = {
516 SND_SOC_DAPM_OUTPUT("RXOUTR"), 510 SND_SOC_DAPM_OUTPUT("RXOUTR"),
517 SND_SOC_DAPM_OUTPUT("HSL"), 511 SND_SOC_DAPM_OUTPUT("HSL"),
518 SND_SOC_DAPM_OUTPUT("HSR"), 512 SND_SOC_DAPM_OUTPUT("HSR"),
513 SND_SOC_DAPM_OUTPUT("LSPL"),
519 SND_SOC_DAPM_OUTPUT("LSP"), 514 SND_SOC_DAPM_OUTPUT("LSP"),
520 SND_SOC_DAPM_OUTPUT("SP"), 515 SND_SOC_DAPM_OUTPUT("SP"),
516 SND_SOC_DAPM_OUTPUT("CDCOUT"),
521 517
522 SND_SOC_DAPM_SWITCH("Speaker Amp", MC13783_AUDIO_RX0, 3, 0, &samp_ctl), 518 SND_SOC_DAPM_SWITCH("CDCOUT Switch", MC13783_AUDIO_RX0, 18, 0,
519 &cdcout_ctl),
520 SND_SOC_DAPM_SWITCH("Speaker Amp Switch", MC13783_AUDIO_RX0, 3, 0,
521 &samp_ctl),
523 SND_SOC_DAPM_SWITCH("Loudspeaker Amp", SND_SOC_NOPM, 0, 0, &lamp_ctl), 522 SND_SOC_DAPM_SWITCH("Loudspeaker Amp", SND_SOC_NOPM, 0, 0, &lamp_ctl),
524 SND_SOC_DAPM_SWITCH("Headset Amp Left", MC13783_AUDIO_RX0, 10, 0, 523 SND_SOC_DAPM_SWITCH("Headset Amp Left", MC13783_AUDIO_RX0, 10, 0,
525 &hlamp_ctl), 524 &hlamp_ctl),
@@ -554,20 +553,28 @@ static struct snd_soc_dapm_route mc13783_routes[] = {
554 { "ADC", NULL, "PGA Right Input"}, 553 { "ADC", NULL, "PGA Right Input"},
555 { "ADC", NULL, "ADC_Reset"}, 554 { "ADC", NULL, "ADC_Reset"},
556 555
556 { "Voice CODEC PGA", "Voice CODEC Bypass", "ADC" },
557
558 { "Speaker Amp Source MUX", "CODEC", "Voice CODEC PGA"},
559 { "Speaker Amp Source MUX", "Right", "DAC PGA"},
560
561 { "Headset Amp Source MUX", "CODEC", "Voice CODEC PGA"},
562 { "Headset Amp Source MUX", "Mixer", "DAC PGA"},
563
557/* Output */ 564/* Output */
558 { "HSL", NULL, "Headset Amp Left" }, 565 { "HSL", NULL, "Headset Amp Left" },
559 { "HSR", NULL, "Headset Amp Right"}, 566 { "HSR", NULL, "Headset Amp Right"},
560 { "RXOUTL", NULL, "Line out Amp Left"}, 567 { "RXOUTL", NULL, "Line out Amp Left"},
561 { "RXOUTR", NULL, "Line out Amp Right"}, 568 { "RXOUTR", NULL, "Line out Amp Right"},
562 { "SP", NULL, "Speaker Amp"}, 569 { "SP", "Speaker Amp Switch", "Speaker Amp Source MUX"},
563 { "Speaker Amp", NULL, "DAC PGA"}, 570 { "LSP", "Loudspeaker Amp", "Speaker Amp Source MUX"},
564 { "LSP", NULL, "DAC PGA"}, 571 { "HSL", "Headset Amp Left", "Headset Amp Source MUX"},
565 { "Headset Amp Left", NULL, "DAC PGA"}, 572 { "HSR", "Headset Amp Right", "Headset Amp Source MUX"},
566 { "Headset Amp Right", NULL, "DAC PGA"},
567 { "Line out Amp Left", NULL, "DAC PGA"}, 573 { "Line out Amp Left", NULL, "DAC PGA"},
568 { "Line out Amp Right", NULL, "DAC PGA"}, 574 { "Line out Amp Right", NULL, "DAC PGA"},
569 { "DAC PGA", NULL, "DAC"}, 575 { "DAC PGA", NULL, "DAC"},
570 { "DAC", NULL, "DAC_E"}, 576 { "DAC", NULL, "DAC_E"},
577 { "CDCOUT", "CDCOUT Switch", "Voice CODEC PGA"},
571}; 578};
572 579
573static const char * const mc13783_3d_mixer[] = {"Stereo", "Phase Mix", 580static const char * const mc13783_3d_mixer[] = {"Stereo", "Phase Mix",
@@ -580,15 +587,39 @@ static const struct soc_enum mc13783_enum_3d_mixer =
580static struct snd_kcontrol_new mc13783_control_list[] = { 587static struct snd_kcontrol_new mc13783_control_list[] = {
581 SOC_SINGLE("Loudspeaker enable", MC13783_AUDIO_RX0, 5, 1, 0), 588 SOC_SINGLE("Loudspeaker enable", MC13783_AUDIO_RX0, 5, 1, 0),
582 SOC_SINGLE("PCM Playback Volume", MC13783_AUDIO_RX1, 6, 15, 0), 589 SOC_SINGLE("PCM Playback Volume", MC13783_AUDIO_RX1, 6, 15, 0),
590 SOC_SINGLE("PCM Playback Switch", MC13783_AUDIO_RX1, 5, 1, 0),
583 SOC_DOUBLE("PCM Capture Volume", MC13783_AUDIO_TX, 19, 14, 31, 0), 591 SOC_DOUBLE("PCM Capture Volume", MC13783_AUDIO_TX, 19, 14, 31, 0),
584 SOC_ENUM("3D Control", mc13783_enum_3d_mixer), 592 SOC_ENUM("3D Control", mc13783_enum_3d_mixer),
593
594 SOC_SINGLE("CDCOUT Switch", MC13783_AUDIO_RX0, 18, 1, 0),
595 SOC_SINGLE("Earpiece Amp Switch", MC13783_AUDIO_RX0, 3, 1, 0),
596 SOC_DOUBLE("Headset Amp Switch", MC13783_AUDIO_RX0, 10, 9, 1, 0),
597 SOC_DOUBLE("Line out Amp Switch", MC13783_AUDIO_RX0, 16, 15, 1, 0),
598
599 SOC_SINGLE("PCM Capture Mixin Switch", MC13783_AUDIO_RX0, 22, 1, 0),
600 SOC_SINGLE("Line in Capture Mixin Switch", MC13783_AUDIO_RX0, 23, 1, 0),
601
602 SOC_SINGLE("CODEC Capture Volume", MC13783_AUDIO_RX1, 1, 15, 0),
603 SOC_SINGLE("CODEC Capture Mixin Switch", MC13783_AUDIO_RX0, 21, 1, 0),
604
605 SOC_SINGLE("Line in Capture Volume", MC13783_AUDIO_RX1, 12, 15, 0),
606 SOC_SINGLE("Line in Capture Switch", MC13783_AUDIO_RX1, 10, 1, 0),
607
608 SOC_SINGLE("MC1 Capture Bias Switch", MC13783_AUDIO_TX, 0, 1, 0),
609 SOC_SINGLE("MC2 Capture Bias Switch", MC13783_AUDIO_TX, 1, 1, 0),
585}; 610};
586 611
587static int mc13783_probe(struct snd_soc_codec *codec) 612static int mc13783_probe(struct snd_soc_codec *codec)
588{ 613{
589 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec); 614 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
615 int ret;
590 616
591 mc13xxx_lock(priv->mc13xxx); 617 codec->control_data = dev_get_regmap(codec->dev->parent, NULL);
618 ret = snd_soc_codec_set_cache_io(codec, 8, 24, SND_SOC_REGMAP);
619 if (ret != 0) {
620 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
621 return ret;
622 }
592 623
593 /* these are the reset values */ 624 /* these are the reset values */
594 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893); 625 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893);
@@ -612,8 +643,6 @@ static int mc13783_probe(struct snd_soc_codec *codec)
612 mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_DAC, 643 mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_DAC,
613 0, AUDIO_SSI_SEL); 644 0, AUDIO_SSI_SEL);
614 645
615 mc13xxx_unlock(priv->mc13xxx);
616
617 return 0; 646 return 0;
618} 647}
619 648
@@ -621,13 +650,9 @@ static int mc13783_remove(struct snd_soc_codec *codec)
621{ 650{
622 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec); 651 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
623 652
624 mc13xxx_lock(priv->mc13xxx);
625
626 /* Make sure VAUDIOON is off */ 653 /* Make sure VAUDIOON is off */
627 mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_RX0, 0x3, 0); 654 mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_RX0, 0x3, 0);
628 655
629 mc13xxx_unlock(priv->mc13xxx);
630
631 return 0; 656 return 0;
632} 657}
633 658
@@ -717,8 +742,6 @@ static struct snd_soc_dai_driver mc13783_dai_sync[] = {
717static struct snd_soc_codec_driver soc_codec_dev_mc13783 = { 742static struct snd_soc_codec_driver soc_codec_dev_mc13783 = {
718 .probe = mc13783_probe, 743 .probe = mc13783_probe,
719 .remove = mc13783_remove, 744 .remove = mc13783_remove,
720 .read = mc13783_read,
721 .write = mc13783_write,
722 .controls = mc13783_control_list, 745 .controls = mc13783_control_list,
723 .num_controls = ARRAY_SIZE(mc13783_control_list), 746 .num_controls = ARRAY_SIZE(mc13783_control_list),
724 .dapm_widgets = mc13783_dapm_widgets, 747 .dapm_widgets = mc13783_dapm_widgets,
diff --git a/sound/soc/codecs/ml26124.c b/sound/soc/codecs/ml26124.c
index 26118828782b..185fa3bc3052 100644
--- a/sound/soc/codecs/ml26124.c
+++ b/sound/soc/codecs/ml26124.c
@@ -342,6 +342,8 @@ static int ml26124_hw_params(struct snd_pcm_substream *substream,
342 struct ml26124_priv *priv = snd_soc_codec_get_drvdata(codec); 342 struct ml26124_priv *priv = snd_soc_codec_get_drvdata(codec);
343 int i = get_coeff(priv->mclk, params_rate(hw_params)); 343 int i = get_coeff(priv->mclk, params_rate(hw_params));
344 344
345 if (i < 0)
346 return i;
345 priv->substream = substream; 347 priv->substream = substream;
346 priv->rate = params_rate(hw_params); 348 priv->rate = params_rate(hw_params);
347 349
diff --git a/sound/soc/codecs/pcm1681.c b/sound/soc/codecs/pcm1681.c
index 54ea15b87bfc..73f9c3630e2c 100644
--- a/sound/soc/codecs/pcm1681.c
+++ b/sound/soc/codecs/pcm1681.c
@@ -271,7 +271,7 @@ MODULE_DEVICE_TABLE(of, pcm1681_dt_ids);
271static const struct regmap_config pcm1681_regmap = { 271static const struct regmap_config pcm1681_regmap = {
272 .reg_bits = 8, 272 .reg_bits = 8,
273 .val_bits = 8, 273 .val_bits = 8,
274 .max_register = ARRAY_SIZE(pcm1681_reg_defaults) + 1, 274 .max_register = 0x13,
275 .reg_defaults = pcm1681_reg_defaults, 275 .reg_defaults = pcm1681_reg_defaults,
276 .num_reg_defaults = ARRAY_SIZE(pcm1681_reg_defaults), 276 .num_reg_defaults = ARRAY_SIZE(pcm1681_reg_defaults),
277 .writeable_reg = pcm1681_writeable_reg, 277 .writeable_reg = pcm1681_writeable_reg,
diff --git a/sound/soc/codecs/pcm1792a.c b/sound/soc/codecs/pcm1792a.c
index 2a8eccf64c76..7613181123fe 100644
--- a/sound/soc/codecs/pcm1792a.c
+++ b/sound/soc/codecs/pcm1792a.c
@@ -188,7 +188,7 @@ MODULE_DEVICE_TABLE(of, pcm1792a_of_match);
188static const struct regmap_config pcm1792a_regmap = { 188static const struct regmap_config pcm1792a_regmap = {
189 .reg_bits = 8, 189 .reg_bits = 8,
190 .val_bits = 8, 190 .val_bits = 8,
191 .max_register = 24, 191 .max_register = 23,
192 .reg_defaults = pcm1792a_reg_defaults, 192 .reg_defaults = pcm1792a_reg_defaults,
193 .num_reg_defaults = ARRAY_SIZE(pcm1792a_reg_defaults), 193 .num_reg_defaults = ARRAY_SIZE(pcm1792a_reg_defaults),
194 .writeable_reg = pcm1792a_writeable_reg, 194 .writeable_reg = pcm1792a_writeable_reg,
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index 6e3f269243e0..64ad84d8a306 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -674,6 +674,8 @@ static const struct snd_soc_dapm_route intercon[] = {
674 /* Left Input */ 674 /* Left Input */
675 {"Left Line1L Mux", "single-ended", "LINE1L"}, 675 {"Left Line1L Mux", "single-ended", "LINE1L"},
676 {"Left Line1L Mux", "differential", "LINE1L"}, 676 {"Left Line1L Mux", "differential", "LINE1L"},
677 {"Left Line1R Mux", "single-ended", "LINE1R"},
678 {"Left Line1R Mux", "differential", "LINE1R"},
677 679
678 {"Left Line2L Mux", "single-ended", "LINE2L"}, 680 {"Left Line2L Mux", "single-ended", "LINE2L"},
679 {"Left Line2L Mux", "differential", "LINE2L"}, 681 {"Left Line2L Mux", "differential", "LINE2L"},
@@ -690,6 +692,8 @@ static const struct snd_soc_dapm_route intercon[] = {
690 /* Right Input */ 692 /* Right Input */
691 {"Right Line1R Mux", "single-ended", "LINE1R"}, 693 {"Right Line1R Mux", "single-ended", "LINE1R"},
692 {"Right Line1R Mux", "differential", "LINE1R"}, 694 {"Right Line1R Mux", "differential", "LINE1R"},
695 {"Right Line1L Mux", "single-ended", "LINE1L"},
696 {"Right Line1L Mux", "differential", "LINE1L"},
693 697
694 {"Right Line2R Mux", "single-ended", "LINE2R"}, 698 {"Right Line2R Mux", "single-ended", "LINE2R"},
695 {"Right Line2R Mux", "differential", "LINE2R"}, 699 {"Right Line2R Mux", "differential", "LINE2R"},
diff --git a/sound/soc/codecs/wm5110.c b/sound/soc/codecs/wm5110.c
index bbd64384ca1c..8c91be5d67e3 100644
--- a/sound/soc/codecs/wm5110.c
+++ b/sound/soc/codecs/wm5110.c
@@ -983,24 +983,36 @@ static const struct snd_soc_dapm_route wm5110_dapm_routes[] = {
983 ARIZONA_MUX_ROUTES("ASRC2L", "ASRC2L"), 983 ARIZONA_MUX_ROUTES("ASRC2L", "ASRC2L"),
984 ARIZONA_MUX_ROUTES("ASRC2R", "ASRC2R"), 984 ARIZONA_MUX_ROUTES("ASRC2R", "ASRC2R"),
985 985
986 { "AEC Loopback", "HPOUT1L", "OUT1L" },
987 { "AEC Loopback", "HPOUT1R", "OUT1R" },
986 { "HPOUT1L", NULL, "OUT1L" }, 988 { "HPOUT1L", NULL, "OUT1L" },
987 { "HPOUT1R", NULL, "OUT1R" }, 989 { "HPOUT1R", NULL, "OUT1R" },
988 990
991 { "AEC Loopback", "HPOUT2L", "OUT2L" },
992 { "AEC Loopback", "HPOUT2R", "OUT2R" },
989 { "HPOUT2L", NULL, "OUT2L" }, 993 { "HPOUT2L", NULL, "OUT2L" },
990 { "HPOUT2R", NULL, "OUT2R" }, 994 { "HPOUT2R", NULL, "OUT2R" },
991 995
996 { "AEC Loopback", "HPOUT3L", "OUT3L" },
997 { "AEC Loopback", "HPOUT3R", "OUT3R" },
992 { "HPOUT3L", NULL, "OUT3L" }, 998 { "HPOUT3L", NULL, "OUT3L" },
993 { "HPOUT3R", NULL, "OUT3L" }, 999 { "HPOUT3R", NULL, "OUT3L" },
994 1000
1001 { "AEC Loopback", "SPKOUTL", "OUT4L" },
995 { "SPKOUTLN", NULL, "OUT4L" }, 1002 { "SPKOUTLN", NULL, "OUT4L" },
996 { "SPKOUTLP", NULL, "OUT4L" }, 1003 { "SPKOUTLP", NULL, "OUT4L" },
997 1004
1005 { "AEC Loopback", "SPKOUTR", "OUT4R" },
998 { "SPKOUTRN", NULL, "OUT4R" }, 1006 { "SPKOUTRN", NULL, "OUT4R" },
999 { "SPKOUTRP", NULL, "OUT4R" }, 1007 { "SPKOUTRP", NULL, "OUT4R" },
1000 1008
1009 { "AEC Loopback", "SPKDAT1L", "OUT5L" },
1010 { "AEC Loopback", "SPKDAT1R", "OUT5R" },
1001 { "SPKDAT1L", NULL, "OUT5L" }, 1011 { "SPKDAT1L", NULL, "OUT5L" },
1002 { "SPKDAT1R", NULL, "OUT5R" }, 1012 { "SPKDAT1R", NULL, "OUT5R" },
1003 1013
1014 { "AEC Loopback", "SPKDAT2L", "OUT6L" },
1015 { "AEC Loopback", "SPKDAT2R", "OUT6R" },
1004 { "SPKDAT2L", NULL, "OUT6L" }, 1016 { "SPKDAT2L", NULL, "OUT6L" },
1005 { "SPKDAT2R", NULL, "OUT6R" }, 1017 { "SPKDAT2R", NULL, "OUT6R" },
1006 1018
diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c
index b38f3506418f..df95e5a83889 100644
--- a/sound/soc/codecs/wm_adsp.c
+++ b/sound/soc/codecs/wm_adsp.c
@@ -396,11 +396,12 @@ static int wm_coeff_write_control(struct snd_kcontrol *kcontrol,
396 ret = regmap_raw_write(adsp->regmap, reg, scratch, 396 ret = regmap_raw_write(adsp->regmap, reg, scratch,
397 ctl->len); 397 ctl->len);
398 if (ret) { 398 if (ret) {
399 adsp_err(adsp, "Failed to write %zu bytes to %x\n", 399 adsp_err(adsp, "Failed to write %zu bytes to %x: %d\n",
400 ctl->len, reg); 400 ctl->len, reg, ret);
401 kfree(scratch); 401 kfree(scratch);
402 return ret; 402 return ret;
403 } 403 }
404 adsp_dbg(adsp, "Wrote %zu bytes to %x\n", ctl->len, reg);
404 405
405 kfree(scratch); 406 kfree(scratch);
406 407
@@ -450,11 +451,12 @@ static int wm_coeff_read_control(struct snd_kcontrol *kcontrol,
450 451
451 ret = regmap_raw_read(adsp->regmap, reg, scratch, ctl->len); 452 ret = regmap_raw_read(adsp->regmap, reg, scratch, ctl->len);
452 if (ret) { 453 if (ret) {
453 adsp_err(adsp, "Failed to read %zu bytes from %x\n", 454 adsp_err(adsp, "Failed to read %zu bytes from %x: %d\n",
454 ctl->len, reg); 455 ctl->len, reg, ret);
455 kfree(scratch); 456 kfree(scratch);
456 return ret; 457 return ret;
457 } 458 }
459 adsp_dbg(adsp, "Read %zu bytes from %x\n", ctl->len, reg);
458 460
459 memcpy(buf, scratch, ctl->len); 461 memcpy(buf, scratch, ctl->len);
460 kfree(scratch); 462 kfree(scratch);
@@ -568,6 +570,7 @@ static int wm_adsp_load(struct wm_adsp *dsp)
568 file, header->ver); 570 file, header->ver);
569 goto out_fw; 571 goto out_fw;
570 } 572 }
573 adsp_info(dsp, "Firmware version: %d\n", header->ver);
571 574
572 if (header->core != dsp->type) { 575 if (header->core != dsp->type) {
573 adsp_err(dsp, "%s: invalid core %d != %d\n", 576 adsp_err(dsp, "%s: invalid core %d != %d\n",
@@ -689,7 +692,8 @@ static int wm_adsp_load(struct wm_adsp *dsp)
689 &buf_list); 692 &buf_list);
690 if (!buf) { 693 if (!buf) {
691 adsp_err(dsp, "Out of memory\n"); 694 adsp_err(dsp, "Out of memory\n");
692 return -ENOMEM; 695 ret = -ENOMEM;
696 goto out_fw;
693 } 697 }
694 698
695 ret = regmap_raw_write_async(regmap, reg, buf->buf, 699 ret = regmap_raw_write_async(regmap, reg, buf->buf,
@@ -1062,6 +1066,7 @@ static int wm_adsp_setup_algs(struct wm_adsp *dsp)
1062 if (i + 1 < algs) { 1066 if (i + 1 < algs) {
1063 region->len = be32_to_cpu(adsp1_alg[i + 1].dm); 1067 region->len = be32_to_cpu(adsp1_alg[i + 1].dm);
1064 region->len -= be32_to_cpu(adsp1_alg[i].dm); 1068 region->len -= be32_to_cpu(adsp1_alg[i].dm);
1069 region->len *= 4;
1065 wm_adsp_create_control(dsp, region); 1070 wm_adsp_create_control(dsp, region);
1066 } else { 1071 } else {
1067 adsp_warn(dsp, "Missing length info for region DM with ID %x\n", 1072 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
@@ -1079,6 +1084,7 @@ static int wm_adsp_setup_algs(struct wm_adsp *dsp)
1079 if (i + 1 < algs) { 1084 if (i + 1 < algs) {
1080 region->len = be32_to_cpu(adsp1_alg[i + 1].zm); 1085 region->len = be32_to_cpu(adsp1_alg[i + 1].zm);
1081 region->len -= be32_to_cpu(adsp1_alg[i].zm); 1086 region->len -= be32_to_cpu(adsp1_alg[i].zm);
1087 region->len *= 4;
1082 wm_adsp_create_control(dsp, region); 1088 wm_adsp_create_control(dsp, region);
1083 } else { 1089 } else {
1084 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n", 1090 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
@@ -1108,6 +1114,7 @@ static int wm_adsp_setup_algs(struct wm_adsp *dsp)
1108 if (i + 1 < algs) { 1114 if (i + 1 < algs) {
1109 region->len = be32_to_cpu(adsp2_alg[i + 1].xm); 1115 region->len = be32_to_cpu(adsp2_alg[i + 1].xm);
1110 region->len -= be32_to_cpu(adsp2_alg[i].xm); 1116 region->len -= be32_to_cpu(adsp2_alg[i].xm);
1117 region->len *= 4;
1111 wm_adsp_create_control(dsp, region); 1118 wm_adsp_create_control(dsp, region);
1112 } else { 1119 } else {
1113 adsp_warn(dsp, "Missing length info for region XM with ID %x\n", 1120 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
@@ -1125,6 +1132,7 @@ static int wm_adsp_setup_algs(struct wm_adsp *dsp)
1125 if (i + 1 < algs) { 1132 if (i + 1 < algs) {
1126 region->len = be32_to_cpu(adsp2_alg[i + 1].ym); 1133 region->len = be32_to_cpu(adsp2_alg[i + 1].ym);
1127 region->len -= be32_to_cpu(adsp2_alg[i].ym); 1134 region->len -= be32_to_cpu(adsp2_alg[i].ym);
1135 region->len *= 4;
1128 wm_adsp_create_control(dsp, region); 1136 wm_adsp_create_control(dsp, region);
1129 } else { 1137 } else {
1130 adsp_warn(dsp, "Missing length info for region YM with ID %x\n", 1138 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
@@ -1142,6 +1150,7 @@ static int wm_adsp_setup_algs(struct wm_adsp *dsp)
1142 if (i + 1 < algs) { 1150 if (i + 1 < algs) {
1143 region->len = be32_to_cpu(adsp2_alg[i + 1].zm); 1151 region->len = be32_to_cpu(adsp2_alg[i + 1].zm);
1144 region->len -= be32_to_cpu(adsp2_alg[i].zm); 1152 region->len -= be32_to_cpu(adsp2_alg[i].zm);
1153 region->len *= 4;
1145 wm_adsp_create_control(dsp, region); 1154 wm_adsp_create_control(dsp, region);
1146 } else { 1155 } else {
1147 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n", 1156 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
@@ -1313,8 +1322,8 @@ static int wm_adsp_load_coeff(struct wm_adsp *dsp)
1313 le32_to_cpu(blk->len)); 1322 le32_to_cpu(blk->len));
1314 if (ret != 0) { 1323 if (ret != 0) {
1315 adsp_err(dsp, 1324 adsp_err(dsp,
1316 "%s.%d: Failed to write to %x in %s\n", 1325 "%s.%d: Failed to write to %x in %s: %d\n",
1317 file, blocks, reg, region_name); 1326 file, blocks, reg, region_name, ret);
1318 } 1327 }
1319 } 1328 }
1320 1329
@@ -1358,6 +1367,7 @@ int wm_adsp1_event(struct snd_soc_dapm_widget *w,
1358 struct snd_soc_codec *codec = w->codec; 1367 struct snd_soc_codec *codec = w->codec;
1359 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec); 1368 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1360 struct wm_adsp *dsp = &dsps[w->shift]; 1369 struct wm_adsp *dsp = &dsps[w->shift];
1370 struct wm_adsp_alg_region *alg_region;
1361 struct wm_coeff_ctl *ctl; 1371 struct wm_coeff_ctl *ctl;
1362 int ret; 1372 int ret;
1363 int val; 1373 int val;
@@ -1435,6 +1445,14 @@ int wm_adsp1_event(struct snd_soc_dapm_widget *w,
1435 1445
1436 list_for_each_entry(ctl, &dsp->ctl_list, list) 1446 list_for_each_entry(ctl, &dsp->ctl_list, list)
1437 ctl->enabled = 0; 1447 ctl->enabled = 0;
1448
1449 while (!list_empty(&dsp->alg_regions)) {
1450 alg_region = list_first_entry(&dsp->alg_regions,
1451 struct wm_adsp_alg_region,
1452 list);
1453 list_del(&alg_region->list);
1454 kfree(alg_region);
1455 }
1438 break; 1456 break;
1439 1457
1440 default: 1458 default:
diff --git a/sound/soc/codecs/wm_hubs.c b/sound/soc/codecs/wm_hubs.c
index 8b50e5958de5..01daf655e20b 100644
--- a/sound/soc/codecs/wm_hubs.c
+++ b/sound/soc/codecs/wm_hubs.c
@@ -530,6 +530,7 @@ static int hp_supply_event(struct snd_soc_dapm_widget *w,
530 hubs->hp_startup_mode); 530 hubs->hp_startup_mode);
531 break; 531 break;
532 } 532 }
533 break;
533 534
534 case SND_SOC_DAPM_PRE_PMD: 535 case SND_SOC_DAPM_PRE_PMD:
535 snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1, 536 snd_soc_update_bits(codec, WM8993_CHARGE_PUMP_1,
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-20 18:11:46 -0500