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-rw-r--r--sound/soc/codecs/Kconfig8
-rw-r--r--sound/soc/codecs/Makefile4
-rw-r--r--sound/soc/codecs/sgtl5000.c128
-rw-r--r--sound/soc/codecs/wm8750.c8
-rw-r--r--sound/soc/codecs/wm8903.c5
-rw-r--r--sound/soc/codecs/wm8915.c2995
-rw-r--r--sound/soc/codecs/wm8915.h3717
-rw-r--r--sound/soc/codecs/wm8994.c1
-rw-r--r--sound/soc/codecs/wm8996.c2994
-rw-r--r--sound/soc/codecs/wm8996.h3717
-rw-r--r--sound/soc/codecs/wm_hubs.c3
11 files changed, 6767 insertions, 6813 deletions
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 379b2e3afd98..665d9240c4ae 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -78,7 +78,6 @@ config SND_SOC_ALL_CODECS
78 select SND_SOC_WM8900 if I2C 78 select SND_SOC_WM8900 if I2C
79 select SND_SOC_WM8903 if I2C 79 select SND_SOC_WM8903 if I2C
80 select SND_SOC_WM8904 if I2C 80 select SND_SOC_WM8904 if I2C
81 select SND_SOC_WM8915 if I2C
82 select SND_SOC_WM8940 if I2C 81 select SND_SOC_WM8940 if I2C
83 select SND_SOC_WM8955 if I2C 82 select SND_SOC_WM8955 if I2C
84 select SND_SOC_WM8960 if I2C 83 select SND_SOC_WM8960 if I2C
@@ -95,6 +94,7 @@ config SND_SOC_ALL_CODECS
95 select SND_SOC_WM8993 if I2C 94 select SND_SOC_WM8993 if I2C
96 select SND_SOC_WM8994 if MFD_WM8994 95 select SND_SOC_WM8994 if MFD_WM8994
97 select SND_SOC_WM8995 if SND_SOC_I2C_AND_SPI 96 select SND_SOC_WM8995 if SND_SOC_I2C_AND_SPI
97 select SND_SOC_WM8996 if I2C
98 select SND_SOC_WM9081 if I2C 98 select SND_SOC_WM9081 if I2C
99 select SND_SOC_WM9090 if I2C 99 select SND_SOC_WM9090 if I2C
100 select SND_SOC_WM9705 if SND_SOC_AC97_BUS 100 select SND_SOC_WM9705 if SND_SOC_AC97_BUS
@@ -329,9 +329,6 @@ config SND_SOC_WM8903
329config SND_SOC_WM8904 329config SND_SOC_WM8904
330 tristate 330 tristate
331 331
332config SND_SOC_WM8915
333 tristate
334
335config SND_SOC_WM8940 332config SND_SOC_WM8940
336 tristate 333 tristate
337 334
@@ -380,6 +377,9 @@ config SND_SOC_WM8994
380config SND_SOC_WM8995 377config SND_SOC_WM8995
381 tristate 378 tristate
382 379
380config SND_SOC_WM8996
381 tristate
382
383config SND_SOC_WM9081 383config SND_SOC_WM9081
384 tristate 384 tristate
385 385
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index da9990fb8569..5119a7e2c1a8 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -63,7 +63,7 @@ snd-soc-wm8804-objs := wm8804.o
63snd-soc-wm8900-objs := wm8900.o 63snd-soc-wm8900-objs := wm8900.o
64snd-soc-wm8903-objs := wm8903.o 64snd-soc-wm8903-objs := wm8903.o
65snd-soc-wm8904-objs := wm8904.o 65snd-soc-wm8904-objs := wm8904.o
66snd-soc-wm8915-objs := wm8915.o 66snd-soc-wm8996-objs := wm8996.o
67snd-soc-wm8940-objs := wm8940.o 67snd-soc-wm8940-objs := wm8940.o
68snd-soc-wm8955-objs := wm8955.o 68snd-soc-wm8955-objs := wm8955.o
69snd-soc-wm8960-objs := wm8960.o 69snd-soc-wm8960-objs := wm8960.o
@@ -160,7 +160,7 @@ obj-$(CONFIG_SND_SOC_WM8804) += snd-soc-wm8804.o
160obj-$(CONFIG_SND_SOC_WM8900) += snd-soc-wm8900.o 160obj-$(CONFIG_SND_SOC_WM8900) += snd-soc-wm8900.o
161obj-$(CONFIG_SND_SOC_WM8903) += snd-soc-wm8903.o 161obj-$(CONFIG_SND_SOC_WM8903) += snd-soc-wm8903.o
162obj-$(CONFIG_SND_SOC_WM8904) += snd-soc-wm8904.o 162obj-$(CONFIG_SND_SOC_WM8904) += snd-soc-wm8904.o
163obj-$(CONFIG_SND_SOC_WM8915) += snd-soc-wm8915.o 163obj-$(CONFIG_SND_SOC_WM8996) += snd-soc-wm8996.o
164obj-$(CONFIG_SND_SOC_WM8940) += snd-soc-wm8940.o 164obj-$(CONFIG_SND_SOC_WM8940) += snd-soc-wm8940.o
165obj-$(CONFIG_SND_SOC_WM8955) += snd-soc-wm8955.o 165obj-$(CONFIG_SND_SOC_WM8955) += snd-soc-wm8955.o
166obj-$(CONFIG_SND_SOC_WM8960) += snd-soc-wm8960.o 166obj-$(CONFIG_SND_SOC_WM8960) += snd-soc-wm8960.o
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index 76258f2a2ffb..7e4066e131e6 100644
--- a/sound/soc/codecs/sgtl5000.c
+++ b/sound/soc/codecs/sgtl5000.c
@@ -33,73 +33,31 @@
33#define SGTL5000_DAP_REG_OFFSET 0x0100 33#define SGTL5000_DAP_REG_OFFSET 0x0100
34#define SGTL5000_MAX_REG_OFFSET 0x013A 34#define SGTL5000_MAX_REG_OFFSET 0x013A
35 35
36/* default value of sgtl5000 registers except DAP */ 36/* default value of sgtl5000 registers */
37static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET >> 1] = { 37static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET] = {
38 0xa011, /* 0x0000, CHIP_ID. 11 stand for revison 17 */ 38 [SGTL5000_CHIP_CLK_CTRL] = 0x0008,
39 0x0000, /* 0x0002, CHIP_DIG_POWER. */ 39 [SGTL5000_CHIP_I2S_CTRL] = 0x0010,
40 0x0008, /* 0x0004, CHIP_CKL_CTRL */ 40 [SGTL5000_CHIP_SSS_CTRL] = 0x0008,
41 0x0010, /* 0x0006, CHIP_I2S_CTRL */ 41 [SGTL5000_CHIP_DAC_VOL] = 0x3c3c,
42 0x0000, /* 0x0008, reserved */ 42 [SGTL5000_CHIP_PAD_STRENGTH] = 0x015f,
43 0x0008, /* 0x000A, CHIP_SSS_CTRL */ 43 [SGTL5000_CHIP_ANA_HP_CTRL] = 0x1818,
44 0x0000, /* 0x000C, reserved */ 44 [SGTL5000_CHIP_ANA_CTRL] = 0x0111,
45 0x020c, /* 0x000E, CHIP_ADCDAC_CTRL */ 45 [SGTL5000_CHIP_LINE_OUT_VOL] = 0x0404,
46 0x3c3c, /* 0x0010, CHIP_DAC_VOL */ 46 [SGTL5000_CHIP_ANA_POWER] = 0x7060,
47 0x0000, /* 0x0012, reserved */ 47 [SGTL5000_CHIP_PLL_CTRL] = 0x5000,
48 0x015f, /* 0x0014, CHIP_PAD_STRENGTH */ 48 [SGTL5000_DAP_BASS_ENHANCE] = 0x0040,
49 0x0000, /* 0x0016, reserved */ 49 [SGTL5000_DAP_BASS_ENHANCE_CTRL] = 0x051f,
50 0x0000, /* 0x0018, reserved */ 50 [SGTL5000_DAP_SURROUND] = 0x0040,
51 0x0000, /* 0x001A, reserved */ 51 [SGTL5000_DAP_EQ_BASS_BAND0] = 0x002f,
52 0x0000, /* 0x001E, reserved */ 52 [SGTL5000_DAP_EQ_BASS_BAND1] = 0x002f,
53 0x0000, /* 0x0020, CHIP_ANA_ADC_CTRL */ 53 [SGTL5000_DAP_EQ_BASS_BAND2] = 0x002f,
54 0x1818, /* 0x0022, CHIP_ANA_HP_CTRL */ 54 [SGTL5000_DAP_EQ_BASS_BAND3] = 0x002f,
55 0x0111, /* 0x0024, CHIP_ANN_CTRL */ 55 [SGTL5000_DAP_EQ_BASS_BAND4] = 0x002f,
56 0x0000, /* 0x0026, CHIP_LINREG_CTRL */ 56 [SGTL5000_DAP_MAIN_CHAN] = 0x8000,
57 0x0000, /* 0x0028, CHIP_REF_CTRL */ 57 [SGTL5000_DAP_AVC_CTRL] = 0x0510,
58 0x0000, /* 0x002A, CHIP_MIC_CTRL */ 58 [SGTL5000_DAP_AVC_THRESHOLD] = 0x1473,
59 0x0000, /* 0x002C, CHIP_LINE_OUT_CTRL */ 59 [SGTL5000_DAP_AVC_ATTACK] = 0x0028,
60 0x0404, /* 0x002E, CHIP_LINE_OUT_VOL */ 60 [SGTL5000_DAP_AVC_DECAY] = 0x0050,
61 0x7060, /* 0x0030, CHIP_ANA_POWER */
62 0x5000, /* 0x0032, CHIP_PLL_CTRL */
63 0x0000, /* 0x0034, CHIP_CLK_TOP_CTRL */
64 0x0000, /* 0x0036, CHIP_ANA_STATUS */
65 0x0000, /* 0x0038, reserved */
66 0x0000, /* 0x003A, CHIP_ANA_TEST2 */
67 0x0000, /* 0x003C, CHIP_SHORT_CTRL */
68 0x0000, /* reserved */
69};
70
71/* default value of dap registers */
72static const u16 sgtl5000_dap_regs[] = {
73 0x0000, /* 0x0100, DAP_CONTROL */
74 0x0000, /* 0x0102, DAP_PEQ */
75 0x0040, /* 0x0104, DAP_BASS_ENHANCE */
76 0x051f, /* 0x0106, DAP_BASS_ENHANCE_CTRL */
77 0x0000, /* 0x0108, DAP_AUDIO_EQ */
78 0x0040, /* 0x010A, DAP_SGTL_SURROUND */
79 0x0000, /* 0x010C, DAP_FILTER_COEF_ACCESS */
80 0x0000, /* 0x010E, DAP_COEF_WR_B0_MSB */
81 0x0000, /* 0x0110, DAP_COEF_WR_B0_LSB */
82 0x0000, /* 0x0112, reserved */
83 0x0000, /* 0x0114, reserved */
84 0x002f, /* 0x0116, DAP_AUDIO_EQ_BASS_BAND0 */
85 0x002f, /* 0x0118, DAP_AUDIO_EQ_BAND0 */
86 0x002f, /* 0x011A, DAP_AUDIO_EQ_BAND2 */
87 0x002f, /* 0x011C, DAP_AUDIO_EQ_BAND3 */
88 0x002f, /* 0x011E, DAP_AUDIO_EQ_TREBLE_BAND4 */
89 0x8000, /* 0x0120, DAP_MAIN_CHAN */
90 0x0000, /* 0x0122, DAP_MIX_CHAN */
91 0x0510, /* 0x0124, DAP_AVC_CTRL */
92 0x1473, /* 0x0126, DAP_AVC_THRESHOLD */
93 0x0028, /* 0x0128, DAP_AVC_ATTACK */
94 0x0050, /* 0x012A, DAP_AVC_DECAY */
95 0x0000, /* 0x012C, DAP_COEF_WR_B1_MSB */
96 0x0000, /* 0x012E, DAP_COEF_WR_B1_LSB */
97 0x0000, /* 0x0130, DAP_COEF_WR_B2_MSB */
98 0x0000, /* 0x0132, DAP_COEF_WR_B2_LSB */
99 0x0000, /* 0x0134, DAP_COEF_WR_A1_MSB */
100 0x0000, /* 0x0136, DAP_COEF_WR_A1_LSB */
101 0x0000, /* 0x0138, DAP_COEF_WR_A2_MSB */
102 0x0000, /* 0x013A, DAP_COEF_WR_A2_LSB */
103}; 61};
104 62
105/* regulator supplies for sgtl5000, VDDD is an optional external supply */ 63/* regulator supplies for sgtl5000, VDDD is an optional external supply */
@@ -1023,12 +981,10 @@ static int sgtl5000_suspend(struct snd_soc_codec *codec, pm_message_t state)
1023static int sgtl5000_restore_regs(struct snd_soc_codec *codec) 981static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
1024{ 982{
1025 u16 *cache = codec->reg_cache; 983 u16 *cache = codec->reg_cache;
1026 int i; 984 u16 reg;
1027 int regular_regs = SGTL5000_CHIP_SHORT_CTRL >> 1;
1028 985
1029 /* restore regular registers */ 986 /* restore regular registers */
1030 for (i = 0; i < regular_regs; i++) { 987 for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) {
1031 int reg = i << 1;
1032 988
1033 /* this regs depends on the others */ 989 /* this regs depends on the others */
1034 if (reg == SGTL5000_CHIP_ANA_POWER || 990 if (reg == SGTL5000_CHIP_ANA_POWER ||
@@ -1038,35 +994,31 @@ static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
1038 reg == SGTL5000_CHIP_CLK_CTRL) 994 reg == SGTL5000_CHIP_CLK_CTRL)
1039 continue; 995 continue;
1040 996
1041 snd_soc_write(codec, reg, cache[i]); 997 snd_soc_write(codec, reg, cache[reg]);
1042 } 998 }
1043 999
1044 /* restore dap registers */ 1000 /* restore dap registers */
1045 for (i = SGTL5000_DAP_REG_OFFSET >> 1; 1001 for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2)
1046 i < SGTL5000_MAX_REG_OFFSET >> 1; i++) { 1002 snd_soc_write(codec, reg, cache[reg]);
1047 int reg = i << 1;
1048
1049 snd_soc_write(codec, reg, cache[i]);
1050 }
1051 1003
1052 /* 1004 /*
1053 * restore power and other regs according 1005 * restore power and other regs according
1054 * to set_power() and set_clock() 1006 * to set_power() and set_clock()
1055 */ 1007 */
1056 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, 1008 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
1057 cache[SGTL5000_CHIP_LINREG_CTRL >> 1]); 1009 cache[SGTL5000_CHIP_LINREG_CTRL]);
1058 1010
1059 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, 1011 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
1060 cache[SGTL5000_CHIP_ANA_POWER >> 1]); 1012 cache[SGTL5000_CHIP_ANA_POWER]);
1061 1013
1062 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, 1014 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
1063 cache[SGTL5000_CHIP_CLK_CTRL >> 1]); 1015 cache[SGTL5000_CHIP_CLK_CTRL]);
1064 1016
1065 snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL, 1017 snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
1066 cache[SGTL5000_CHIP_REF_CTRL >> 1]); 1018 cache[SGTL5000_CHIP_REF_CTRL]);
1067 1019
1068 snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL, 1020 snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1069 cache[SGTL5000_CHIP_LINE_OUT_CTRL >> 1]); 1021 cache[SGTL5000_CHIP_LINE_OUT_CTRL]);
1070 return 0; 1022 return 0;
1071} 1023}
1072 1024
@@ -1454,16 +1406,6 @@ static __devinit int sgtl5000_i2c_probe(struct i2c_client *client,
1454 if (!sgtl5000) 1406 if (!sgtl5000)
1455 return -ENOMEM; 1407 return -ENOMEM;
1456 1408
1457 /*
1458 * copy DAP default values to default value array.
1459 * sgtl5000 register space has a big hole, merge it
1460 * at init phase makes life easy.
1461 * FIXME: should we drop 'const' of sgtl5000_regs?
1462 */
1463 memcpy((void *)(&sgtl5000_regs[0] + (SGTL5000_DAP_REG_OFFSET >> 1)),
1464 sgtl5000_dap_regs,
1465 SGTL5000_MAX_REG_OFFSET - SGTL5000_DAP_REG_OFFSET);
1466
1467 i2c_set_clientdata(client, sgtl5000); 1409 i2c_set_clientdata(client, sgtl5000);
1468 1410
1469 ret = snd_soc_register_codec(&client->dev, 1411 ret = snd_soc_register_codec(&client->dev,
diff --git a/sound/soc/codecs/wm8750.c b/sound/soc/codecs/wm8750.c
index 38f38fddd190..d0003cc3bcd6 100644
--- a/sound/soc/codecs/wm8750.c
+++ b/sound/soc/codecs/wm8750.c
@@ -778,11 +778,19 @@ static int __devexit wm8750_spi_remove(struct spi_device *spi)
778 return 0; 778 return 0;
779} 779}
780 780
781static const struct spi_device_id wm8750_spi_ids[] = {
782 { "wm8750", 0 },
783 { "wm8987", 0 },
784 { },
785};
786MODULE_DEVICE_TABLE(spi, wm8750_spi_ids);
787
781static struct spi_driver wm8750_spi_driver = { 788static struct spi_driver wm8750_spi_driver = {
782 .driver = { 789 .driver = {
783 .name = "wm8750-codec", 790 .name = "wm8750-codec",
784 .owner = THIS_MODULE, 791 .owner = THIS_MODULE,
785 }, 792 },
793 .id_table = wm8750_spi_ids,
786 .probe = wm8750_spi_probe, 794 .probe = wm8750_spi_probe,
787 .remove = __devexit_p(wm8750_spi_remove), 795 .remove = __devexit_p(wm8750_spi_remove),
788}; 796};
diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c
index 43e3d760766f..4ad8ebd290e3 100644
--- a/sound/soc/codecs/wm8903.c
+++ b/sound/soc/codecs/wm8903.c
@@ -2046,8 +2046,13 @@ static int wm8903_probe(struct snd_soc_codec *codec)
2046/* power down chip */ 2046/* power down chip */
2047static int wm8903_remove(struct snd_soc_codec *codec) 2047static int wm8903_remove(struct snd_soc_codec *codec)
2048{ 2048{
2049 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
2050
2049 wm8903_free_gpio(codec); 2051 wm8903_free_gpio(codec);
2050 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); 2052 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
2053 if (wm8903->irq)
2054 free_irq(wm8903->irq, codec);
2055
2051 return 0; 2056 return 0;
2052} 2057}
2053 2058
diff --git a/sound/soc/codecs/wm8915.c b/sound/soc/codecs/wm8915.c
deleted file mode 100644
index 423baa9be241..000000000000
--- a/sound/soc/codecs/wm8915.c
+++ /dev/null
@@ -1,2995 +0,0 @@
1/*
2 * wm8915.c - WM8915 audio codec interface
3 *
4 * Copyright 2011 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/completion.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
20#include <linux/gpio.h>
21#include <linux/i2c.h>
22#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24#include <linux/workqueue.h>
25#include <sound/core.h>
26#include <sound/jack.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32#include <trace/events/asoc.h>
33
34#include <sound/wm8915.h>
35#include "wm8915.h"
36
37#define WM8915_AIFS 2
38
39#define HPOUT1L 1
40#define HPOUT1R 2
41#define HPOUT2L 4
42#define HPOUT2R 8
43
44#define WM8915_NUM_SUPPLIES 4
45static const char *wm8915_supply_names[WM8915_NUM_SUPPLIES] = {
46 "DBVDD",
47 "AVDD1",
48 "AVDD2",
49 "CPVDD",
50};
51
52struct wm8915_priv {
53 struct snd_soc_codec *codec;
54
55 int ldo1ena;
56
57 int sysclk;
58 int sysclk_src;
59
60 int fll_src;
61 int fll_fref;
62 int fll_fout;
63
64 struct completion fll_lock;
65
66 u16 dcs_pending;
67 struct completion dcs_done;
68
69 u16 hpout_ena;
70 u16 hpout_pending;
71
72 struct regulator_bulk_data supplies[WM8915_NUM_SUPPLIES];
73 struct notifier_block disable_nb[WM8915_NUM_SUPPLIES];
74
75 struct wm8915_pdata pdata;
76
77 int rx_rate[WM8915_AIFS];
78 int bclk_rate[WM8915_AIFS];
79
80 /* Platform dependant ReTune mobile configuration */
81 int num_retune_mobile_texts;
82 const char **retune_mobile_texts;
83 int retune_mobile_cfg[2];
84 struct soc_enum retune_mobile_enum;
85
86 struct snd_soc_jack *jack;
87 bool detecting;
88 bool jack_mic;
89 wm8915_polarity_fn polarity_cb;
90
91#ifdef CONFIG_GPIOLIB
92 struct gpio_chip gpio_chip;
93#endif
94};
95
96/* We can't use the same notifier block for more than one supply and
97 * there's no way I can see to get from a callback to the caller
98 * except container_of().
99 */
100#define WM8915_REGULATOR_EVENT(n) \
101static int wm8915_regulator_event_##n(struct notifier_block *nb, \
102 unsigned long event, void *data) \
103{ \
104 struct wm8915_priv *wm8915 = container_of(nb, struct wm8915_priv, \
105 disable_nb[n]); \
106 if (event & REGULATOR_EVENT_DISABLE) { \
107 wm8915->codec->cache_sync = 1; \
108 } \
109 return 0; \
110}
111
112WM8915_REGULATOR_EVENT(0)
113WM8915_REGULATOR_EVENT(1)
114WM8915_REGULATOR_EVENT(2)
115WM8915_REGULATOR_EVENT(3)
116
117static const u16 wm8915_reg[WM8915_MAX_REGISTER] = {
118 [WM8915_SOFTWARE_RESET] = 0x8915,
119 [WM8915_POWER_MANAGEMENT_7] = 0x10,
120 [WM8915_DAC1_HPOUT1_VOLUME] = 0x88,
121 [WM8915_DAC2_HPOUT2_VOLUME] = 0x88,
122 [WM8915_DAC1_LEFT_VOLUME] = 0x2c0,
123 [WM8915_DAC1_RIGHT_VOLUME] = 0x2c0,
124 [WM8915_DAC2_LEFT_VOLUME] = 0x2c0,
125 [WM8915_DAC2_RIGHT_VOLUME] = 0x2c0,
126 [WM8915_OUTPUT1_LEFT_VOLUME] = 0x80,
127 [WM8915_OUTPUT1_RIGHT_VOLUME] = 0x80,
128 [WM8915_OUTPUT2_LEFT_VOLUME] = 0x80,
129 [WM8915_OUTPUT2_RIGHT_VOLUME] = 0x80,
130 [WM8915_MICBIAS_1] = 0x39,
131 [WM8915_MICBIAS_2] = 0x39,
132 [WM8915_LDO_1] = 0x3,
133 [WM8915_LDO_2] = 0x13,
134 [WM8915_ACCESSORY_DETECT_MODE_1] = 0x4,
135 [WM8915_HEADPHONE_DETECT_1] = 0x20,
136 [WM8915_MIC_DETECT_1] = 0x7600,
137 [WM8915_MIC_DETECT_2] = 0xbf,
138 [WM8915_CHARGE_PUMP_1] = 0x1f25,
139 [WM8915_CHARGE_PUMP_2] = 0xab19,
140 [WM8915_DC_SERVO_5] = 0x2a2a,
141 [WM8915_CONTROL_INTERFACE_1] = 0x8004,
142 [WM8915_CLOCKING_1] = 0x10,
143 [WM8915_AIF_RATE] = 0x83,
144 [WM8915_FLL_CONTROL_4] = 0x5dc0,
145 [WM8915_FLL_CONTROL_5] = 0xc84,
146 [WM8915_FLL_EFS_2] = 0x2,
147 [WM8915_AIF1_TX_LRCLK_1] = 0x80,
148 [WM8915_AIF1_TX_LRCLK_2] = 0x8,
149 [WM8915_AIF1_RX_LRCLK_1] = 0x80,
150 [WM8915_AIF1TX_DATA_CONFIGURATION_1] = 0x1818,
151 [WM8915_AIF1RX_DATA_CONFIGURATION] = 0x1818,
152 [WM8915_AIF1TX_TEST] = 0x7,
153 [WM8915_AIF2_TX_LRCLK_1] = 0x80,
154 [WM8915_AIF2_TX_LRCLK_2] = 0x8,
155 [WM8915_AIF2_RX_LRCLK_1] = 0x80,
156 [WM8915_AIF2TX_DATA_CONFIGURATION_1] = 0x1818,
157 [WM8915_AIF2RX_DATA_CONFIGURATION] = 0x1818,
158 [WM8915_AIF2TX_TEST] = 0x1,
159 [WM8915_DSP1_TX_LEFT_VOLUME] = 0xc0,
160 [WM8915_DSP1_TX_RIGHT_VOLUME] = 0xc0,
161 [WM8915_DSP1_RX_LEFT_VOLUME] = 0xc0,
162 [WM8915_DSP1_RX_RIGHT_VOLUME] = 0xc0,
163 [WM8915_DSP1_TX_FILTERS] = 0x2000,
164 [WM8915_DSP1_RX_FILTERS_1] = 0x200,
165 [WM8915_DSP1_RX_FILTERS_2] = 0x10,
166 [WM8915_DSP1_DRC_1] = 0x98,
167 [WM8915_DSP1_DRC_2] = 0x845,
168 [WM8915_DSP1_RX_EQ_GAINS_1] = 0x6318,
169 [WM8915_DSP1_RX_EQ_GAINS_2] = 0x6300,
170 [WM8915_DSP1_RX_EQ_BAND_1_A] = 0xfca,
171 [WM8915_DSP1_RX_EQ_BAND_1_B] = 0x400,
172 [WM8915_DSP1_RX_EQ_BAND_1_PG] = 0xd8,
173 [WM8915_DSP1_RX_EQ_BAND_2_A] = 0x1eb5,
174 [WM8915_DSP1_RX_EQ_BAND_2_B] = 0xf145,
175 [WM8915_DSP1_RX_EQ_BAND_2_C] = 0xb75,
176 [WM8915_DSP1_RX_EQ_BAND_2_PG] = 0x1c5,
177 [WM8915_DSP1_RX_EQ_BAND_3_A] = 0x1c58,
178 [WM8915_DSP1_RX_EQ_BAND_3_B] = 0xf373,
179 [WM8915_DSP1_RX_EQ_BAND_3_C] = 0xa54,
180 [WM8915_DSP1_RX_EQ_BAND_3_PG] = 0x558,
181 [WM8915_DSP1_RX_EQ_BAND_4_A] = 0x168e,
182 [WM8915_DSP1_RX_EQ_BAND_4_B] = 0xf829,
183 [WM8915_DSP1_RX_EQ_BAND_4_C] = 0x7ad,
184 [WM8915_DSP1_RX_EQ_BAND_4_PG] = 0x1103,
185 [WM8915_DSP1_RX_EQ_BAND_5_A] = 0x564,
186 [WM8915_DSP1_RX_EQ_BAND_5_B] = 0x559,
187 [WM8915_DSP1_RX_EQ_BAND_5_PG] = 0x4000,
188 [WM8915_DSP2_TX_LEFT_VOLUME] = 0xc0,
189 [WM8915_DSP2_TX_RIGHT_VOLUME] = 0xc0,
190 [WM8915_DSP2_RX_LEFT_VOLUME] = 0xc0,
191 [WM8915_DSP2_RX_RIGHT_VOLUME] = 0xc0,
192 [WM8915_DSP2_TX_FILTERS] = 0x2000,
193 [WM8915_DSP2_RX_FILTERS_1] = 0x200,
194 [WM8915_DSP2_RX_FILTERS_2] = 0x10,
195 [WM8915_DSP2_DRC_1] = 0x98,
196 [WM8915_DSP2_DRC_2] = 0x845,
197 [WM8915_DSP2_RX_EQ_GAINS_1] = 0x6318,
198 [WM8915_DSP2_RX_EQ_GAINS_2] = 0x6300,
199 [WM8915_DSP2_RX_EQ_BAND_1_A] = 0xfca,
200 [WM8915_DSP2_RX_EQ_BAND_1_B] = 0x400,
201 [WM8915_DSP2_RX_EQ_BAND_1_PG] = 0xd8,
202 [WM8915_DSP2_RX_EQ_BAND_2_A] = 0x1eb5,
203 [WM8915_DSP2_RX_EQ_BAND_2_B] = 0xf145,
204 [WM8915_DSP2_RX_EQ_BAND_2_C] = 0xb75,
205 [WM8915_DSP2_RX_EQ_BAND_2_PG] = 0x1c5,
206 [WM8915_DSP2_RX_EQ_BAND_3_A] = 0x1c58,
207 [WM8915_DSP2_RX_EQ_BAND_3_B] = 0xf373,
208 [WM8915_DSP2_RX_EQ_BAND_3_C] = 0xa54,
209 [WM8915_DSP2_RX_EQ_BAND_3_PG] = 0x558,
210 [WM8915_DSP2_RX_EQ_BAND_4_A] = 0x168e,
211 [WM8915_DSP2_RX_EQ_BAND_4_B] = 0xf829,
212 [WM8915_DSP2_RX_EQ_BAND_4_C] = 0x7ad,
213 [WM8915_DSP2_RX_EQ_BAND_4_PG] = 0x1103,
214 [WM8915_DSP2_RX_EQ_BAND_5_A] = 0x564,
215 [WM8915_DSP2_RX_EQ_BAND_5_B] = 0x559,
216 [WM8915_DSP2_RX_EQ_BAND_5_PG] = 0x4000,
217 [WM8915_OVERSAMPLING] = 0xd,
218 [WM8915_SIDETONE] = 0x1040,
219 [WM8915_GPIO_1] = 0xa101,
220 [WM8915_GPIO_2] = 0xa101,
221 [WM8915_GPIO_3] = 0xa101,
222 [WM8915_GPIO_4] = 0xa101,
223 [WM8915_GPIO_5] = 0xa101,
224 [WM8915_PULL_CONTROL_2] = 0x140,
225 [WM8915_INTERRUPT_STATUS_1_MASK] = 0x1f,
226 [WM8915_INTERRUPT_STATUS_2_MASK] = 0x1ecf,
227 [WM8915_RIGHT_PDM_SPEAKER] = 0x1,
228 [WM8915_PDM_SPEAKER_MUTE_SEQUENCE] = 0x69,
229 [WM8915_PDM_SPEAKER_VOLUME] = 0x66,
230 [WM8915_WRITE_SEQUENCER_0] = 0x1,
231 [WM8915_WRITE_SEQUENCER_1] = 0x1,
232 [WM8915_WRITE_SEQUENCER_3] = 0x6,
233 [WM8915_WRITE_SEQUENCER_4] = 0x40,
234 [WM8915_WRITE_SEQUENCER_5] = 0x1,
235 [WM8915_WRITE_SEQUENCER_6] = 0xf,
236 [WM8915_WRITE_SEQUENCER_7] = 0x6,
237 [WM8915_WRITE_SEQUENCER_8] = 0x1,
238 [WM8915_WRITE_SEQUENCER_9] = 0x3,
239 [WM8915_WRITE_SEQUENCER_10] = 0x104,
240 [WM8915_WRITE_SEQUENCER_12] = 0x60,
241 [WM8915_WRITE_SEQUENCER_13] = 0x11,
242 [WM8915_WRITE_SEQUENCER_14] = 0x401,
243 [WM8915_WRITE_SEQUENCER_16] = 0x50,
244 [WM8915_WRITE_SEQUENCER_17] = 0x3,
245 [WM8915_WRITE_SEQUENCER_18] = 0x100,
246 [WM8915_WRITE_SEQUENCER_20] = 0x51,
247 [WM8915_WRITE_SEQUENCER_21] = 0x3,
248 [WM8915_WRITE_SEQUENCER_22] = 0x104,
249 [WM8915_WRITE_SEQUENCER_23] = 0xa,
250 [WM8915_WRITE_SEQUENCER_24] = 0x60,
251 [WM8915_WRITE_SEQUENCER_25] = 0x3b,
252 [WM8915_WRITE_SEQUENCER_26] = 0x502,
253 [WM8915_WRITE_SEQUENCER_27] = 0x100,
254 [WM8915_WRITE_SEQUENCER_28] = 0x2fff,
255 [WM8915_WRITE_SEQUENCER_32] = 0x2fff,
256 [WM8915_WRITE_SEQUENCER_36] = 0x2fff,
257 [WM8915_WRITE_SEQUENCER_40] = 0x2fff,
258 [WM8915_WRITE_SEQUENCER_44] = 0x2fff,
259 [WM8915_WRITE_SEQUENCER_48] = 0x2fff,
260 [WM8915_WRITE_SEQUENCER_52] = 0x2fff,
261 [WM8915_WRITE_SEQUENCER_56] = 0x2fff,
262 [WM8915_WRITE_SEQUENCER_60] = 0x2fff,
263 [WM8915_WRITE_SEQUENCER_64] = 0x1,
264 [WM8915_WRITE_SEQUENCER_65] = 0x1,
265 [WM8915_WRITE_SEQUENCER_67] = 0x6,
266 [WM8915_WRITE_SEQUENCER_68] = 0x40,
267 [WM8915_WRITE_SEQUENCER_69] = 0x1,
268 [WM8915_WRITE_SEQUENCER_70] = 0xf,
269 [WM8915_WRITE_SEQUENCER_71] = 0x6,
270 [WM8915_WRITE_SEQUENCER_72] = 0x1,
271 [WM8915_WRITE_SEQUENCER_73] = 0x3,
272 [WM8915_WRITE_SEQUENCER_74] = 0x104,
273 [WM8915_WRITE_SEQUENCER_76] = 0x60,
274 [WM8915_WRITE_SEQUENCER_77] = 0x11,
275 [WM8915_WRITE_SEQUENCER_78] = 0x401,
276 [WM8915_WRITE_SEQUENCER_80] = 0x50,
277 [WM8915_WRITE_SEQUENCER_81] = 0x3,
278 [WM8915_WRITE_SEQUENCER_82] = 0x100,
279 [WM8915_WRITE_SEQUENCER_84] = 0x60,
280 [WM8915_WRITE_SEQUENCER_85] = 0x3b,
281 [WM8915_WRITE_SEQUENCER_86] = 0x502,
282 [WM8915_WRITE_SEQUENCER_87] = 0x100,
283 [WM8915_WRITE_SEQUENCER_88] = 0x2fff,
284 [WM8915_WRITE_SEQUENCER_92] = 0x2fff,
285 [WM8915_WRITE_SEQUENCER_96] = 0x2fff,
286 [WM8915_WRITE_SEQUENCER_100] = 0x2fff,
287 [WM8915_WRITE_SEQUENCER_104] = 0x2fff,
288 [WM8915_WRITE_SEQUENCER_108] = 0x2fff,
289 [WM8915_WRITE_SEQUENCER_112] = 0x2fff,
290 [WM8915_WRITE_SEQUENCER_116] = 0x2fff,
291 [WM8915_WRITE_SEQUENCER_120] = 0x2fff,
292 [WM8915_WRITE_SEQUENCER_124] = 0x2fff,
293 [WM8915_WRITE_SEQUENCER_128] = 0x1,
294 [WM8915_WRITE_SEQUENCER_129] = 0x1,
295 [WM8915_WRITE_SEQUENCER_131] = 0x6,
296 [WM8915_WRITE_SEQUENCER_132] = 0x40,
297 [WM8915_WRITE_SEQUENCER_133] = 0x1,
298 [WM8915_WRITE_SEQUENCER_134] = 0xf,
299 [WM8915_WRITE_SEQUENCER_135] = 0x6,
300 [WM8915_WRITE_SEQUENCER_136] = 0x1,
301 [WM8915_WRITE_SEQUENCER_137] = 0x3,
302 [WM8915_WRITE_SEQUENCER_138] = 0x106,
303 [WM8915_WRITE_SEQUENCER_140] = 0x61,
304 [WM8915_WRITE_SEQUENCER_141] = 0x11,
305 [WM8915_WRITE_SEQUENCER_142] = 0x401,
306 [WM8915_WRITE_SEQUENCER_144] = 0x50,
307 [WM8915_WRITE_SEQUENCER_145] = 0x3,
308 [WM8915_WRITE_SEQUENCER_146] = 0x102,
309 [WM8915_WRITE_SEQUENCER_148] = 0x51,
310 [WM8915_WRITE_SEQUENCER_149] = 0x3,
311 [WM8915_WRITE_SEQUENCER_150] = 0x106,
312 [WM8915_WRITE_SEQUENCER_151] = 0xa,
313 [WM8915_WRITE_SEQUENCER_152] = 0x61,
314 [WM8915_WRITE_SEQUENCER_153] = 0x3b,
315 [WM8915_WRITE_SEQUENCER_154] = 0x502,
316 [WM8915_WRITE_SEQUENCER_155] = 0x100,
317 [WM8915_WRITE_SEQUENCER_156] = 0x2fff,
318 [WM8915_WRITE_SEQUENCER_160] = 0x2fff,
319 [WM8915_WRITE_SEQUENCER_164] = 0x2fff,
320 [WM8915_WRITE_SEQUENCER_168] = 0x2fff,
321 [WM8915_WRITE_SEQUENCER_172] = 0x2fff,
322 [WM8915_WRITE_SEQUENCER_176] = 0x2fff,
323 [WM8915_WRITE_SEQUENCER_180] = 0x2fff,
324 [WM8915_WRITE_SEQUENCER_184] = 0x2fff,
325 [WM8915_WRITE_SEQUENCER_188] = 0x2fff,
326 [WM8915_WRITE_SEQUENCER_192] = 0x1,
327 [WM8915_WRITE_SEQUENCER_193] = 0x1,
328 [WM8915_WRITE_SEQUENCER_195] = 0x6,
329 [WM8915_WRITE_SEQUENCER_196] = 0x40,
330 [WM8915_WRITE_SEQUENCER_197] = 0x1,
331 [WM8915_WRITE_SEQUENCER_198] = 0xf,
332 [WM8915_WRITE_SEQUENCER_199] = 0x6,
333 [WM8915_WRITE_SEQUENCER_200] = 0x1,
334 [WM8915_WRITE_SEQUENCER_201] = 0x3,
335 [WM8915_WRITE_SEQUENCER_202] = 0x106,
336 [WM8915_WRITE_SEQUENCER_204] = 0x61,
337 [WM8915_WRITE_SEQUENCER_205] = 0x11,
338 [WM8915_WRITE_SEQUENCER_206] = 0x401,
339 [WM8915_WRITE_SEQUENCER_208] = 0x50,
340 [WM8915_WRITE_SEQUENCER_209] = 0x3,
341 [WM8915_WRITE_SEQUENCER_210] = 0x102,
342 [WM8915_WRITE_SEQUENCER_212] = 0x61,
343 [WM8915_WRITE_SEQUENCER_213] = 0x3b,
344 [WM8915_WRITE_SEQUENCER_214] = 0x502,
345 [WM8915_WRITE_SEQUENCER_215] = 0x100,
346 [WM8915_WRITE_SEQUENCER_216] = 0x2fff,
347 [WM8915_WRITE_SEQUENCER_220] = 0x2fff,
348 [WM8915_WRITE_SEQUENCER_224] = 0x2fff,
349 [WM8915_WRITE_SEQUENCER_228] = 0x2fff,
350 [WM8915_WRITE_SEQUENCER_232] = 0x2fff,
351 [WM8915_WRITE_SEQUENCER_236] = 0x2fff,
352 [WM8915_WRITE_SEQUENCER_240] = 0x2fff,
353 [WM8915_WRITE_SEQUENCER_244] = 0x2fff,
354 [WM8915_WRITE_SEQUENCER_248] = 0x2fff,
355 [WM8915_WRITE_SEQUENCER_252] = 0x2fff,
356 [WM8915_WRITE_SEQUENCER_256] = 0x60,
357 [WM8915_WRITE_SEQUENCER_258] = 0x601,
358 [WM8915_WRITE_SEQUENCER_260] = 0x50,
359 [WM8915_WRITE_SEQUENCER_262] = 0x100,
360 [WM8915_WRITE_SEQUENCER_264] = 0x1,
361 [WM8915_WRITE_SEQUENCER_266] = 0x104,
362 [WM8915_WRITE_SEQUENCER_267] = 0x100,
363 [WM8915_WRITE_SEQUENCER_268] = 0x2fff,
364 [WM8915_WRITE_SEQUENCER_272] = 0x2fff,
365 [WM8915_WRITE_SEQUENCER_276] = 0x2fff,
366 [WM8915_WRITE_SEQUENCER_280] = 0x2fff,
367 [WM8915_WRITE_SEQUENCER_284] = 0x2fff,
368 [WM8915_WRITE_SEQUENCER_288] = 0x2fff,
369 [WM8915_WRITE_SEQUENCER_292] = 0x2fff,
370 [WM8915_WRITE_SEQUENCER_296] = 0x2fff,
371 [WM8915_WRITE_SEQUENCER_300] = 0x2fff,
372 [WM8915_WRITE_SEQUENCER_304] = 0x2fff,
373 [WM8915_WRITE_SEQUENCER_308] = 0x2fff,
374 [WM8915_WRITE_SEQUENCER_312] = 0x2fff,
375 [WM8915_WRITE_SEQUENCER_316] = 0x2fff,
376 [WM8915_WRITE_SEQUENCER_320] = 0x61,
377 [WM8915_WRITE_SEQUENCER_322] = 0x601,
378 [WM8915_WRITE_SEQUENCER_324] = 0x50,
379 [WM8915_WRITE_SEQUENCER_326] = 0x102,
380 [WM8915_WRITE_SEQUENCER_328] = 0x1,
381 [WM8915_WRITE_SEQUENCER_330] = 0x106,
382 [WM8915_WRITE_SEQUENCER_331] = 0x100,
383 [WM8915_WRITE_SEQUENCER_332] = 0x2fff,
384 [WM8915_WRITE_SEQUENCER_336] = 0x2fff,
385 [WM8915_WRITE_SEQUENCER_340] = 0x2fff,
386 [WM8915_WRITE_SEQUENCER_344] = 0x2fff,
387 [WM8915_WRITE_SEQUENCER_348] = 0x2fff,
388 [WM8915_WRITE_SEQUENCER_352] = 0x2fff,
389 [WM8915_WRITE_SEQUENCER_356] = 0x2fff,
390 [WM8915_WRITE_SEQUENCER_360] = 0x2fff,
391 [WM8915_WRITE_SEQUENCER_364] = 0x2fff,
392 [WM8915_WRITE_SEQUENCER_368] = 0x2fff,
393 [WM8915_WRITE_SEQUENCER_372] = 0x2fff,
394 [WM8915_WRITE_SEQUENCER_376] = 0x2fff,
395 [WM8915_WRITE_SEQUENCER_380] = 0x2fff,
396 [WM8915_WRITE_SEQUENCER_384] = 0x60,
397 [WM8915_WRITE_SEQUENCER_386] = 0x601,
398 [WM8915_WRITE_SEQUENCER_388] = 0x61,
399 [WM8915_WRITE_SEQUENCER_390] = 0x601,
400 [WM8915_WRITE_SEQUENCER_392] = 0x50,
401 [WM8915_WRITE_SEQUENCER_394] = 0x300,
402 [WM8915_WRITE_SEQUENCER_396] = 0x1,
403 [WM8915_WRITE_SEQUENCER_398] = 0x304,
404 [WM8915_WRITE_SEQUENCER_400] = 0x40,
405 [WM8915_WRITE_SEQUENCER_402] = 0xf,
406 [WM8915_WRITE_SEQUENCER_404] = 0x1,
407 [WM8915_WRITE_SEQUENCER_407] = 0x100,
408};
409
410static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
411static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
412static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
413static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
414static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
415static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
416static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
417
418static const char *sidetone_hpf_text[] = {
419 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
420};
421
422static const struct soc_enum sidetone_hpf =
423 SOC_ENUM_SINGLE(WM8915_SIDETONE, 7, 6, sidetone_hpf_text);
424
425static const char *hpf_mode_text[] = {
426 "HiFi", "Custom", "Voice"
427};
428
429static const struct soc_enum dsp1tx_hpf_mode =
430 SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
431
432static const struct soc_enum dsp2tx_hpf_mode =
433 SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
434
435static const char *hpf_cutoff_text[] = {
436 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
437};
438
439static const struct soc_enum dsp1tx_hpf_cutoff =
440 SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
441
442static const struct soc_enum dsp2tx_hpf_cutoff =
443 SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
444
445static void wm8915_set_retune_mobile(struct snd_soc_codec *codec, int block)
446{
447 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
448 struct wm8915_pdata *pdata = &wm8915->pdata;
449 int base, best, best_val, save, i, cfg, iface;
450
451 if (!wm8915->num_retune_mobile_texts)
452 return;
453
454 switch (block) {
455 case 0:
456 base = WM8915_DSP1_RX_EQ_GAINS_1;
457 if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) &
458 WM8915_DSP1RX_SRC)
459 iface = 1;
460 else
461 iface = 0;
462 break;
463 case 1:
464 base = WM8915_DSP1_RX_EQ_GAINS_2;
465 if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) &
466 WM8915_DSP2RX_SRC)
467 iface = 1;
468 else
469 iface = 0;
470 break;
471 default:
472 return;
473 }
474
475 /* Find the version of the currently selected configuration
476 * with the nearest sample rate. */
477 cfg = wm8915->retune_mobile_cfg[block];
478 best = 0;
479 best_val = INT_MAX;
480 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
481 if (strcmp(pdata->retune_mobile_cfgs[i].name,
482 wm8915->retune_mobile_texts[cfg]) == 0 &&
483 abs(pdata->retune_mobile_cfgs[i].rate
484 - wm8915->rx_rate[iface]) < best_val) {
485 best = i;
486 best_val = abs(pdata->retune_mobile_cfgs[i].rate
487 - wm8915->rx_rate[iface]);
488 }
489 }
490
491 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
492 block,
493 pdata->retune_mobile_cfgs[best].name,
494 pdata->retune_mobile_cfgs[best].rate,
495 wm8915->rx_rate[iface]);
496
497 /* The EQ will be disabled while reconfiguring it, remember the
498 * current configuration.
499 */
500 save = snd_soc_read(codec, base);
501 save &= WM8915_DSP1RX_EQ_ENA;
502
503 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
504 snd_soc_update_bits(codec, base + i, 0xffff,
505 pdata->retune_mobile_cfgs[best].regs[i]);
506
507 snd_soc_update_bits(codec, base, WM8915_DSP1RX_EQ_ENA, save);
508}
509
510/* Icky as hell but saves code duplication */
511static int wm8915_get_retune_mobile_block(const char *name)
512{
513 if (strcmp(name, "DSP1 EQ Mode") == 0)
514 return 0;
515 if (strcmp(name, "DSP2 EQ Mode") == 0)
516 return 1;
517 return -EINVAL;
518}
519
520static int wm8915_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
521 struct snd_ctl_elem_value *ucontrol)
522{
523 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
524 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
525 struct wm8915_pdata *pdata = &wm8915->pdata;
526 int block = wm8915_get_retune_mobile_block(kcontrol->id.name);
527 int value = ucontrol->value.integer.value[0];
528
529 if (block < 0)
530 return block;
531
532 if (value >= pdata->num_retune_mobile_cfgs)
533 return -EINVAL;
534
535 wm8915->retune_mobile_cfg[block] = value;
536
537 wm8915_set_retune_mobile(codec, block);
538
539 return 0;
540}
541
542static int wm8915_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
543 struct snd_ctl_elem_value *ucontrol)
544{
545 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
546 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
547 int block = wm8915_get_retune_mobile_block(kcontrol->id.name);
548
549 ucontrol->value.enumerated.item[0] = wm8915->retune_mobile_cfg[block];
550
551 return 0;
552}
553
554static const struct snd_kcontrol_new wm8915_snd_controls[] = {
555SOC_DOUBLE_R_TLV("Capture Volume", WM8915_LEFT_LINE_INPUT_VOLUME,
556 WM8915_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
557SOC_DOUBLE_R("Capture ZC Switch", WM8915_LEFT_LINE_INPUT_VOLUME,
558 WM8915_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
559
560SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8915_DAC1_MIXER_VOLUMES,
561 0, 5, 24, 0, sidetone_tlv),
562SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8915_DAC2_MIXER_VOLUMES,
563 0, 5, 24, 0, sidetone_tlv),
564SOC_SINGLE("Sidetone LPF Switch", WM8915_SIDETONE, 12, 1, 0),
565SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
566SOC_SINGLE("Sidetone HPF Switch", WM8915_SIDETONE, 6, 1, 0),
567
568SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8915_DSP1_TX_LEFT_VOLUME,
569 WM8915_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
570SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8915_DSP2_TX_LEFT_VOLUME,
571 WM8915_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
572
573SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8915_DSP1_TX_FILTERS,
574 13, 1, 0),
575SOC_DOUBLE("DSP1 Capture HPF Switch", WM8915_DSP1_TX_FILTERS, 12, 11, 1, 0),
576SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
577SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
578
579SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8915_DSP2_TX_FILTERS,
580 13, 1, 0),
581SOC_DOUBLE("DSP2 Capture HPF Switch", WM8915_DSP2_TX_FILTERS, 12, 11, 1, 0),
582SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
583SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
584
585SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8915_DSP1_RX_LEFT_VOLUME,
586 WM8915_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
587SOC_SINGLE("DSP1 Playback Switch", WM8915_DSP1_RX_FILTERS_1, 9, 1, 1),
588
589SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8915_DSP2_RX_LEFT_VOLUME,
590 WM8915_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
591SOC_SINGLE("DSP2 Playback Switch", WM8915_DSP2_RX_FILTERS_1, 9, 1, 1),
592
593SOC_DOUBLE_R_TLV("DAC1 Volume", WM8915_DAC1_LEFT_VOLUME,
594 WM8915_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
595SOC_DOUBLE_R("DAC1 Switch", WM8915_DAC1_LEFT_VOLUME,
596 WM8915_DAC1_RIGHT_VOLUME, 9, 1, 1),
597
598SOC_DOUBLE_R_TLV("DAC2 Volume", WM8915_DAC2_LEFT_VOLUME,
599 WM8915_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
600SOC_DOUBLE_R("DAC2 Switch", WM8915_DAC2_LEFT_VOLUME,
601 WM8915_DAC2_RIGHT_VOLUME, 9, 1, 1),
602
603SOC_SINGLE("Speaker High Performance Switch", WM8915_OVERSAMPLING, 3, 1, 0),
604SOC_SINGLE("DMIC High Performance Switch", WM8915_OVERSAMPLING, 2, 1, 0),
605SOC_SINGLE("ADC High Performance Switch", WM8915_OVERSAMPLING, 1, 1, 0),
606SOC_SINGLE("DAC High Performance Switch", WM8915_OVERSAMPLING, 0, 1, 0),
607
608SOC_SINGLE("DAC Soft Mute Switch", WM8915_DAC_SOFTMUTE, 1, 1, 0),
609SOC_SINGLE("DAC Slow Soft Mute Switch", WM8915_DAC_SOFTMUTE, 0, 1, 0),
610
611SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8915_DAC1_HPOUT1_VOLUME, 0, 4,
612 8, 0, out_digital_tlv),
613SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8915_DAC2_HPOUT2_VOLUME, 0, 4,
614 8, 0, out_digital_tlv),
615
616SOC_DOUBLE_R_TLV("Output 1 Volume", WM8915_OUTPUT1_LEFT_VOLUME,
617 WM8915_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
618SOC_DOUBLE_R("Output 1 ZC Switch", WM8915_OUTPUT1_LEFT_VOLUME,
619 WM8915_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
620
621SOC_DOUBLE_R_TLV("Output 2 Volume", WM8915_OUTPUT2_LEFT_VOLUME,
622 WM8915_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
623SOC_DOUBLE_R("Output 2 ZC Switch", WM8915_OUTPUT2_LEFT_VOLUME,
624 WM8915_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
625
626SOC_DOUBLE_TLV("Speaker Volume", WM8915_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
627 spk_tlv),
628SOC_DOUBLE_R("Speaker Switch", WM8915_LEFT_PDM_SPEAKER,
629 WM8915_RIGHT_PDM_SPEAKER, 3, 1, 1),
630SOC_DOUBLE_R("Speaker ZC Switch", WM8915_LEFT_PDM_SPEAKER,
631 WM8915_RIGHT_PDM_SPEAKER, 2, 1, 0),
632
633SOC_SINGLE("DSP1 EQ Switch", WM8915_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
634SOC_SINGLE("DSP2 EQ Switch", WM8915_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
635};
636
637static const struct snd_kcontrol_new wm8915_eq_controls[] = {
638SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
639 eq_tlv),
640SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
641 eq_tlv),
642SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
643 eq_tlv),
644SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
645 eq_tlv),
646SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
647 eq_tlv),
648
649SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
650 eq_tlv),
651SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
652 eq_tlv),
653SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
654 eq_tlv),
655SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
656 eq_tlv),
657SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
658 eq_tlv),
659};
660
661static int cp_event(struct snd_soc_dapm_widget *w,
662 struct snd_kcontrol *kcontrol, int event)
663{
664 switch (event) {
665 case SND_SOC_DAPM_POST_PMU:
666 msleep(5);
667 break;
668 default:
669 BUG();
670 return -EINVAL;
671 }
672
673 return 0;
674}
675
676static int rmv_short_event(struct snd_soc_dapm_widget *w,
677 struct snd_kcontrol *kcontrol, int event)
678{
679 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec);
680
681 /* Record which outputs we enabled */
682 switch (event) {
683 case SND_SOC_DAPM_PRE_PMD:
684 wm8915->hpout_pending &= ~w->shift;
685 break;
686 case SND_SOC_DAPM_PRE_PMU:
687 wm8915->hpout_pending |= w->shift;
688 break;
689 default:
690 BUG();
691 return -EINVAL;
692 }
693
694 return 0;
695}
696
697static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
698{
699 struct i2c_client *i2c = to_i2c_client(codec->dev);
700 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
701 int i, ret;
702 unsigned long timeout = 200;
703
704 snd_soc_write(codec, WM8915_DC_SERVO_2, mask);
705
706 /* Use the interrupt if possible */
707 do {
708 if (i2c->irq) {
709 timeout = wait_for_completion_timeout(&wm8915->dcs_done,
710 msecs_to_jiffies(200));
711 if (timeout == 0)
712 dev_err(codec->dev, "DC servo timed out\n");
713
714 } else {
715 msleep(1);
716 if (--i) {
717 timeout = 0;
718 break;
719 }
720 }
721
722 ret = snd_soc_read(codec, WM8915_DC_SERVO_2);
723 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
724 } while (ret & mask);
725
726 if (timeout == 0)
727 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
728 else
729 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
730}
731
732static void wm8915_seq_notifier(struct snd_soc_dapm_context *dapm,
733 enum snd_soc_dapm_type event, int subseq)
734{
735 struct snd_soc_codec *codec = container_of(dapm,
736 struct snd_soc_codec, dapm);
737 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
738 u16 val, mask;
739
740 /* Complete any pending DC servo starts */
741 if (wm8915->dcs_pending) {
742 dev_dbg(codec->dev, "Starting DC servo for %x\n",
743 wm8915->dcs_pending);
744
745 /* Trigger a startup sequence */
746 wait_for_dc_servo(codec, wm8915->dcs_pending
747 << WM8915_DCS_TRIG_STARTUP_0_SHIFT);
748
749 wm8915->dcs_pending = 0;
750 }
751
752 if (wm8915->hpout_pending != wm8915->hpout_ena) {
753 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
754 wm8915->hpout_ena, wm8915->hpout_pending);
755
756 val = 0;
757 mask = 0;
758 if (wm8915->hpout_pending & HPOUT1L) {
759 val |= WM8915_HPOUT1L_RMV_SHORT;
760 mask |= WM8915_HPOUT1L_RMV_SHORT;
761 } else {
762 mask |= WM8915_HPOUT1L_RMV_SHORT |
763 WM8915_HPOUT1L_OUTP |
764 WM8915_HPOUT1L_DLY;
765 }
766
767 if (wm8915->hpout_pending & HPOUT1R) {
768 val |= WM8915_HPOUT1R_RMV_SHORT;
769 mask |= WM8915_HPOUT1R_RMV_SHORT;
770 } else {
771 mask |= WM8915_HPOUT1R_RMV_SHORT |
772 WM8915_HPOUT1R_OUTP |
773 WM8915_HPOUT1R_DLY;
774 }
775
776 snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_1, mask, val);
777
778 val = 0;
779 mask = 0;
780 if (wm8915->hpout_pending & HPOUT2L) {
781 val |= WM8915_HPOUT2L_RMV_SHORT;
782 mask |= WM8915_HPOUT2L_RMV_SHORT;
783 } else {
784 mask |= WM8915_HPOUT2L_RMV_SHORT |
785 WM8915_HPOUT2L_OUTP |
786 WM8915_HPOUT2L_DLY;
787 }
788
789 if (wm8915->hpout_pending & HPOUT2R) {
790 val |= WM8915_HPOUT2R_RMV_SHORT;
791 mask |= WM8915_HPOUT2R_RMV_SHORT;
792 } else {
793 mask |= WM8915_HPOUT2R_RMV_SHORT |
794 WM8915_HPOUT2R_OUTP |
795 WM8915_HPOUT2R_DLY;
796 }
797
798 snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_2, mask, val);
799
800 wm8915->hpout_ena = wm8915->hpout_pending;
801 }
802}
803
804static int dcs_start(struct snd_soc_dapm_widget *w,
805 struct snd_kcontrol *kcontrol, int event)
806{
807 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec);
808
809 switch (event) {
810 case SND_SOC_DAPM_POST_PMU:
811 wm8915->dcs_pending |= 1 << w->shift;
812 break;
813 default:
814 BUG();
815 return -EINVAL;
816 }
817
818 return 0;
819}
820
821static const char *sidetone_text[] = {
822 "IN1", "IN2",
823};
824
825static const struct soc_enum left_sidetone_enum =
826 SOC_ENUM_SINGLE(WM8915_SIDETONE, 0, 2, sidetone_text);
827
828static const struct snd_kcontrol_new left_sidetone =
829 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
830
831static const struct soc_enum right_sidetone_enum =
832 SOC_ENUM_SINGLE(WM8915_SIDETONE, 1, 2, sidetone_text);
833
834static const struct snd_kcontrol_new right_sidetone =
835 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
836
837static const char *spk_text[] = {
838 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
839};
840
841static const struct soc_enum spkl_enum =
842 SOC_ENUM_SINGLE(WM8915_LEFT_PDM_SPEAKER, 0, 4, spk_text);
843
844static const struct snd_kcontrol_new spkl_mux =
845 SOC_DAPM_ENUM("SPKL", spkl_enum);
846
847static const struct soc_enum spkr_enum =
848 SOC_ENUM_SINGLE(WM8915_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
849
850static const struct snd_kcontrol_new spkr_mux =
851 SOC_DAPM_ENUM("SPKR", spkr_enum);
852
853static const char *dsp1rx_text[] = {
854 "AIF1", "AIF2"
855};
856
857static const struct soc_enum dsp1rx_enum =
858 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
859
860static const struct snd_kcontrol_new dsp1rx =
861 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
862
863static const char *dsp2rx_text[] = {
864 "AIF2", "AIF1"
865};
866
867static const struct soc_enum dsp2rx_enum =
868 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
869
870static const struct snd_kcontrol_new dsp2rx =
871 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
872
873static const char *aif2tx_text[] = {
874 "DSP2", "DSP1", "AIF1"
875};
876
877static const struct soc_enum aif2tx_enum =
878 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
879
880static const struct snd_kcontrol_new aif2tx =
881 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
882
883static const char *inmux_text[] = {
884 "ADC", "DMIC1", "DMIC2"
885};
886
887static const struct soc_enum in1_enum =
888 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 0, 3, inmux_text);
889
890static const struct snd_kcontrol_new in1_mux =
891 SOC_DAPM_ENUM("IN1 Mux", in1_enum);
892
893static const struct soc_enum in2_enum =
894 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 4, 3, inmux_text);
895
896static const struct snd_kcontrol_new in2_mux =
897 SOC_DAPM_ENUM("IN2 Mux", in2_enum);
898
899static const struct snd_kcontrol_new dac2r_mix[] = {
900SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING,
901 5, 1, 0),
902SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING,
903 4, 1, 0),
904SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
905SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
906};
907
908static const struct snd_kcontrol_new dac2l_mix[] = {
909SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING,
910 5, 1, 0),
911SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING,
912 4, 1, 0),
913SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
914SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
915};
916
917static const struct snd_kcontrol_new dac1r_mix[] = {
918SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING,
919 5, 1, 0),
920SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING,
921 4, 1, 0),
922SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
923SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
924};
925
926static const struct snd_kcontrol_new dac1l_mix[] = {
927SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING,
928 5, 1, 0),
929SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING,
930 4, 1, 0),
931SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
932SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
933};
934
935static const struct snd_kcontrol_new dsp1txl[] = {
936SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING,
937 1, 1, 0),
938SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING,
939 0, 1, 0),
940};
941
942static const struct snd_kcontrol_new dsp1txr[] = {
943SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING,
944 1, 1, 0),
945SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING,
946 0, 1, 0),
947};
948
949static const struct snd_kcontrol_new dsp2txl[] = {
950SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING,
951 1, 1, 0),
952SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING,
953 0, 1, 0),
954};
955
956static const struct snd_kcontrol_new dsp2txr[] = {
957SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING,
958 1, 1, 0),
959SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING,
960 0, 1, 0),
961};
962
963
964static const struct snd_soc_dapm_widget wm8915_dapm_widgets[] = {
965SND_SOC_DAPM_INPUT("IN1LN"),
966SND_SOC_DAPM_INPUT("IN1LP"),
967SND_SOC_DAPM_INPUT("IN1RN"),
968SND_SOC_DAPM_INPUT("IN1RP"),
969
970SND_SOC_DAPM_INPUT("IN2LN"),
971SND_SOC_DAPM_INPUT("IN2LP"),
972SND_SOC_DAPM_INPUT("IN2RN"),
973SND_SOC_DAPM_INPUT("IN2RP"),
974
975SND_SOC_DAPM_INPUT("DMIC1DAT"),
976SND_SOC_DAPM_INPUT("DMIC2DAT"),
977
978SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8915_AIF_CLOCKING_1, 0, 0, NULL, 0),
979SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8915_CLOCKING_1, 1, 0, NULL, 0),
980SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8915_CLOCKING_1, 2, 0, NULL, 0),
981SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8915_CHARGE_PUMP_1, 15, 0, cp_event,
982 SND_SOC_DAPM_POST_PMU),
983
984SND_SOC_DAPM_SUPPLY("LDO2", WM8915_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
985SND_SOC_DAPM_MICBIAS("MICB2", WM8915_POWER_MANAGEMENT_1, 9, 0),
986SND_SOC_DAPM_MICBIAS("MICB1", WM8915_POWER_MANAGEMENT_1, 8, 0),
987
988SND_SOC_DAPM_PGA("IN1L PGA", WM8915_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
989SND_SOC_DAPM_PGA("IN1R PGA", WM8915_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
990
991SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &in1_mux),
992SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &in1_mux),
993SND_SOC_DAPM_MUX("IN2L Mux", SND_SOC_NOPM, 0, 0, &in2_mux),
994SND_SOC_DAPM_MUX("IN2R Mux", SND_SOC_NOPM, 0, 0, &in2_mux),
995
996SND_SOC_DAPM_PGA("IN1L", WM8915_POWER_MANAGEMENT_7, 2, 0, NULL, 0),
997SND_SOC_DAPM_PGA("IN1R", WM8915_POWER_MANAGEMENT_7, 3, 0, NULL, 0),
998SND_SOC_DAPM_PGA("IN2L", WM8915_POWER_MANAGEMENT_7, 6, 0, NULL, 0),
999SND_SOC_DAPM_PGA("IN2R", WM8915_POWER_MANAGEMENT_7, 7, 0, NULL, 0),
1000
1001SND_SOC_DAPM_SUPPLY("DMIC2", WM8915_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
1002SND_SOC_DAPM_SUPPLY("DMIC1", WM8915_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
1003
1004SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8915_POWER_MANAGEMENT_3, 5, 0),
1005SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8915_POWER_MANAGEMENT_3, 4, 0),
1006SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8915_POWER_MANAGEMENT_3, 3, 0),
1007SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8915_POWER_MANAGEMENT_3, 2, 0),
1008
1009SND_SOC_DAPM_ADC("ADCL", NULL, WM8915_POWER_MANAGEMENT_3, 1, 0),
1010SND_SOC_DAPM_ADC("ADCR", NULL, WM8915_POWER_MANAGEMENT_3, 0, 0),
1011
1012SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
1013SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
1014
1015SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 11, 0),
1016SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 10, 0),
1017SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 9, 0),
1018SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 8, 0),
1019
1020SND_SOC_DAPM_MIXER("DSP2TXL", WM8915_POWER_MANAGEMENT_5, 11, 0,
1021 dsp2txl, ARRAY_SIZE(dsp2txl)),
1022SND_SOC_DAPM_MIXER("DSP2TXR", WM8915_POWER_MANAGEMENT_5, 10, 0,
1023 dsp2txr, ARRAY_SIZE(dsp2txr)),
1024SND_SOC_DAPM_MIXER("DSP1TXL", WM8915_POWER_MANAGEMENT_5, 9, 0,
1025 dsp1txl, ARRAY_SIZE(dsp1txl)),
1026SND_SOC_DAPM_MIXER("DSP1TXR", WM8915_POWER_MANAGEMENT_5, 8, 0,
1027 dsp1txr, ARRAY_SIZE(dsp1txr)),
1028
1029SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1030 dac2l_mix, ARRAY_SIZE(dac2l_mix)),
1031SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1032 dac2r_mix, ARRAY_SIZE(dac2r_mix)),
1033SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1034 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1035SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1036 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1037
1038SND_SOC_DAPM_DAC("DAC2L", NULL, WM8915_POWER_MANAGEMENT_5, 3, 0),
1039SND_SOC_DAPM_DAC("DAC2R", NULL, WM8915_POWER_MANAGEMENT_5, 2, 0),
1040SND_SOC_DAPM_DAC("DAC1L", NULL, WM8915_POWER_MANAGEMENT_5, 1, 0),
1041SND_SOC_DAPM_DAC("DAC1R", NULL, WM8915_POWER_MANAGEMENT_5, 0, 0),
1042
1043SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 1,
1044 WM8915_POWER_MANAGEMENT_4, 9, 0),
1045SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 2,
1046 WM8915_POWER_MANAGEMENT_4, 8, 0),
1047
1048SND_SOC_DAPM_AIF_IN("AIF2TX1", "AIF2 Capture", 1,
1049 WM8915_POWER_MANAGEMENT_6, 9, 0),
1050SND_SOC_DAPM_AIF_IN("AIF2TX0", "AIF2 Capture", 2,
1051 WM8915_POWER_MANAGEMENT_6, 8, 0),
1052
1053SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
1054 WM8915_POWER_MANAGEMENT_4, 5, 0),
1055SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
1056 WM8915_POWER_MANAGEMENT_4, 4, 0),
1057SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
1058 WM8915_POWER_MANAGEMENT_4, 3, 0),
1059SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
1060 WM8915_POWER_MANAGEMENT_4, 2, 0),
1061SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
1062 WM8915_POWER_MANAGEMENT_4, 1, 0),
1063SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
1064 WM8915_POWER_MANAGEMENT_4, 0, 0),
1065
1066SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
1067 WM8915_POWER_MANAGEMENT_6, 5, 0),
1068SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
1069 WM8915_POWER_MANAGEMENT_6, 4, 0),
1070SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
1071 WM8915_POWER_MANAGEMENT_6, 3, 0),
1072SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
1073 WM8915_POWER_MANAGEMENT_6, 2, 0),
1074SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
1075 WM8915_POWER_MANAGEMENT_6, 1, 0),
1076SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
1077 WM8915_POWER_MANAGEMENT_6, 0, 0),
1078
1079/* We route as stereo pairs so define some dummy widgets to squash
1080 * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1081SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1082SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1083SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1084SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1085SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1086
1087SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1088SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1089SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1090
1091SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1092SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1093SND_SOC_DAPM_PGA("SPKL PGA", WM8915_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1094SND_SOC_DAPM_PGA("SPKR PGA", WM8915_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1095
1096SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8915_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1097SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8915_ANALOGUE_HP_2, 5, 0, NULL, 0),
1098SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8915_DC_SERVO_1, 2, 0, dcs_start,
1099 SND_SOC_DAPM_POST_PMU),
1100SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8915_ANALOGUE_HP_2, 6, 0, NULL, 0),
1101SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1102 rmv_short_event,
1103 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1104
1105SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8915_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1106SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8915_ANALOGUE_HP_2, 1, 0, NULL, 0),
1107SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8915_DC_SERVO_1, 3, 0, dcs_start,
1108 SND_SOC_DAPM_POST_PMU),
1109SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8915_ANALOGUE_HP_2, 2, 0, NULL, 0),
1110SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1111 rmv_short_event,
1112 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1113
1114SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8915_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1115SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8915_ANALOGUE_HP_1, 5, 0, NULL, 0),
1116SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8915_DC_SERVO_1, 0, 0, dcs_start,
1117 SND_SOC_DAPM_POST_PMU),
1118SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8915_ANALOGUE_HP_1, 6, 0, NULL, 0),
1119SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1120 rmv_short_event,
1121 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1122
1123SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8915_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1124SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8915_ANALOGUE_HP_1, 1, 0, NULL, 0),
1125SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8915_DC_SERVO_1, 1, 0, dcs_start,
1126 SND_SOC_DAPM_POST_PMU),
1127SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8915_ANALOGUE_HP_1, 2, 0, NULL, 0),
1128SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1129 rmv_short_event,
1130 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1131
1132SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1133SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1134SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1135SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1136SND_SOC_DAPM_OUTPUT("SPKDAT"),
1137};
1138
1139static const struct snd_soc_dapm_route wm8915_dapm_routes[] = {
1140 { "AIFCLK", NULL, "SYSCLK" },
1141 { "SYSDSPCLK", NULL, "SYSCLK" },
1142 { "Charge Pump", NULL, "SYSCLK" },
1143
1144 { "MICB1", NULL, "LDO2" },
1145 { "MICB2", NULL, "LDO2" },
1146
1147 { "IN1L PGA", NULL, "IN2LN" },
1148 { "IN1L PGA", NULL, "IN2LP" },
1149 { "IN1L PGA", NULL, "IN1LN" },
1150 { "IN1L PGA", NULL, "IN1LP" },
1151
1152 { "IN1R PGA", NULL, "IN2RN" },
1153 { "IN1R PGA", NULL, "IN2RP" },
1154 { "IN1R PGA", NULL, "IN1RN" },
1155 { "IN1R PGA", NULL, "IN1RP" },
1156
1157 { "ADCL", NULL, "IN1L PGA" },
1158
1159 { "ADCR", NULL, "IN1R PGA" },
1160
1161 { "DMIC1L", NULL, "DMIC1DAT" },
1162 { "DMIC1R", NULL, "DMIC1DAT" },
1163 { "DMIC2L", NULL, "DMIC2DAT" },
1164 { "DMIC2R", NULL, "DMIC2DAT" },
1165
1166 { "DMIC2L", NULL, "DMIC2" },
1167 { "DMIC2R", NULL, "DMIC2" },
1168 { "DMIC1L", NULL, "DMIC1" },
1169 { "DMIC1R", NULL, "DMIC1" },
1170
1171 { "IN1L Mux", "ADC", "ADCL" },
1172 { "IN1L Mux", "DMIC1", "DMIC1L" },
1173 { "IN1L Mux", "DMIC2", "DMIC2L" },
1174
1175 { "IN1R Mux", "ADC", "ADCR" },
1176 { "IN1R Mux", "DMIC1", "DMIC1R" },
1177 { "IN1R Mux", "DMIC2", "DMIC2R" },
1178
1179 { "IN2L Mux", "ADC", "ADCL" },
1180 { "IN2L Mux", "DMIC1", "DMIC1L" },
1181 { "IN2L Mux", "DMIC2", "DMIC2L" },
1182
1183 { "IN2R Mux", "ADC", "ADCR" },
1184 { "IN2R Mux", "DMIC1", "DMIC1R" },
1185 { "IN2R Mux", "DMIC2", "DMIC2R" },
1186
1187 { "Left Sidetone", "IN1", "IN1L Mux" },
1188 { "Left Sidetone", "IN2", "IN2L Mux" },
1189
1190 { "Right Sidetone", "IN1", "IN1R Mux" },
1191 { "Right Sidetone", "IN2", "IN2R Mux" },
1192
1193 { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1194 { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1195
1196 { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1197 { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1198
1199 { "AIF1TX0", NULL, "DSP1TXL" },
1200 { "AIF1TX1", NULL, "DSP1TXR" },
1201 { "AIF1TX2", NULL, "DSP2TXL" },
1202 { "AIF1TX3", NULL, "DSP2TXR" },
1203 { "AIF1TX4", NULL, "AIF2RX0" },
1204 { "AIF1TX5", NULL, "AIF2RX1" },
1205
1206 { "AIF1RX0", NULL, "AIFCLK" },
1207 { "AIF1RX1", NULL, "AIFCLK" },
1208 { "AIF1RX2", NULL, "AIFCLK" },
1209 { "AIF1RX3", NULL, "AIFCLK" },
1210 { "AIF1RX4", NULL, "AIFCLK" },
1211 { "AIF1RX5", NULL, "AIFCLK" },
1212
1213 { "AIF2RX0", NULL, "AIFCLK" },
1214 { "AIF2RX1", NULL, "AIFCLK" },
1215
1216 { "DSP1RXL", NULL, "SYSDSPCLK" },
1217 { "DSP1RXR", NULL, "SYSDSPCLK" },
1218 { "DSP2RXL", NULL, "SYSDSPCLK" },
1219 { "DSP2RXR", NULL, "SYSDSPCLK" },
1220 { "DSP1TXL", NULL, "SYSDSPCLK" },
1221 { "DSP1TXR", NULL, "SYSDSPCLK" },
1222 { "DSP2TXL", NULL, "SYSDSPCLK" },
1223 { "DSP2TXR", NULL, "SYSDSPCLK" },
1224
1225 { "AIF1RXA", NULL, "AIF1RX0" },
1226 { "AIF1RXA", NULL, "AIF1RX1" },
1227 { "AIF1RXB", NULL, "AIF1RX2" },
1228 { "AIF1RXB", NULL, "AIF1RX3" },
1229 { "AIF1RXC", NULL, "AIF1RX4" },
1230 { "AIF1RXC", NULL, "AIF1RX5" },
1231
1232 { "AIF2RX", NULL, "AIF2RX0" },
1233 { "AIF2RX", NULL, "AIF2RX1" },
1234
1235 { "AIF2TX", "DSP2", "DSP2TX" },
1236 { "AIF2TX", "DSP1", "DSP1RX" },
1237 { "AIF2TX", "AIF1", "AIF1RXC" },
1238
1239 { "DSP1RXL", NULL, "DSP1RX" },
1240 { "DSP1RXR", NULL, "DSP1RX" },
1241 { "DSP2RXL", NULL, "DSP2RX" },
1242 { "DSP2RXR", NULL, "DSP2RX" },
1243
1244 { "DSP2TX", NULL, "DSP2TXL" },
1245 { "DSP2TX", NULL, "DSP2TXR" },
1246
1247 { "DSP1RX", "AIF1", "AIF1RXA" },
1248 { "DSP1RX", "AIF2", "AIF2RX" },
1249
1250 { "DSP2RX", "AIF1", "AIF1RXB" },
1251 { "DSP2RX", "AIF2", "AIF2RX" },
1252
1253 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1254 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1255 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1256 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1257
1258 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1259 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1260 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1261 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1262
1263 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1264 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1265 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1266 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1267
1268 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1269 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1270 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1271 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1272
1273 { "DAC1L", NULL, "DAC1L Mixer" },
1274 { "DAC1R", NULL, "DAC1R Mixer" },
1275 { "DAC2L", NULL, "DAC2L Mixer" },
1276 { "DAC2R", NULL, "DAC2R Mixer" },
1277
1278 { "HPOUT2L PGA", NULL, "Charge Pump" },
1279 { "HPOUT2L PGA", NULL, "DAC2L" },
1280 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1281 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1282 { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" },
1283 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" },
1284
1285 { "HPOUT2R PGA", NULL, "Charge Pump" },
1286 { "HPOUT2R PGA", NULL, "DAC2R" },
1287 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1288 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1289 { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" },
1290 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" },
1291
1292 { "HPOUT1L PGA", NULL, "Charge Pump" },
1293 { "HPOUT1L PGA", NULL, "DAC1L" },
1294 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1295 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1296 { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" },
1297 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" },
1298
1299 { "HPOUT1R PGA", NULL, "Charge Pump" },
1300 { "HPOUT1R PGA", NULL, "DAC1R" },
1301 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1302 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1303 { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" },
1304 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" },
1305
1306 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1307 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1308 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1309 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1310
1311 { "SPKL", "DAC1L", "DAC1L" },
1312 { "SPKL", "DAC1R", "DAC1R" },
1313 { "SPKL", "DAC2L", "DAC2L" },
1314 { "SPKL", "DAC2R", "DAC2R" },
1315
1316 { "SPKR", "DAC1L", "DAC1L" },
1317 { "SPKR", "DAC1R", "DAC1R" },
1318 { "SPKR", "DAC2L", "DAC2L" },
1319 { "SPKR", "DAC2R", "DAC2R" },
1320
1321 { "SPKL PGA", NULL, "SPKL" },
1322 { "SPKR PGA", NULL, "SPKR" },
1323
1324 { "SPKDAT", NULL, "SPKL PGA" },
1325 { "SPKDAT", NULL, "SPKR PGA" },
1326};
1327
1328static int wm8915_readable_register(struct snd_soc_codec *codec,
1329 unsigned int reg)
1330{
1331 /* Due to the sparseness of the register map the compiler
1332 * output from an explicit switch statement ends up being much
1333 * more efficient than a table.
1334 */
1335 switch (reg) {
1336 case WM8915_SOFTWARE_RESET:
1337 case WM8915_POWER_MANAGEMENT_1:
1338 case WM8915_POWER_MANAGEMENT_2:
1339 case WM8915_POWER_MANAGEMENT_3:
1340 case WM8915_POWER_MANAGEMENT_4:
1341 case WM8915_POWER_MANAGEMENT_5:
1342 case WM8915_POWER_MANAGEMENT_6:
1343 case WM8915_POWER_MANAGEMENT_7:
1344 case WM8915_POWER_MANAGEMENT_8:
1345 case WM8915_LEFT_LINE_INPUT_VOLUME:
1346 case WM8915_RIGHT_LINE_INPUT_VOLUME:
1347 case WM8915_LINE_INPUT_CONTROL:
1348 case WM8915_DAC1_HPOUT1_VOLUME:
1349 case WM8915_DAC2_HPOUT2_VOLUME:
1350 case WM8915_DAC1_LEFT_VOLUME:
1351 case WM8915_DAC1_RIGHT_VOLUME:
1352 case WM8915_DAC2_LEFT_VOLUME:
1353 case WM8915_DAC2_RIGHT_VOLUME:
1354 case WM8915_OUTPUT1_LEFT_VOLUME:
1355 case WM8915_OUTPUT1_RIGHT_VOLUME:
1356 case WM8915_OUTPUT2_LEFT_VOLUME:
1357 case WM8915_OUTPUT2_RIGHT_VOLUME:
1358 case WM8915_MICBIAS_1:
1359 case WM8915_MICBIAS_2:
1360 case WM8915_LDO_1:
1361 case WM8915_LDO_2:
1362 case WM8915_ACCESSORY_DETECT_MODE_1:
1363 case WM8915_ACCESSORY_DETECT_MODE_2:
1364 case WM8915_HEADPHONE_DETECT_1:
1365 case WM8915_HEADPHONE_DETECT_2:
1366 case WM8915_MIC_DETECT_1:
1367 case WM8915_MIC_DETECT_2:
1368 case WM8915_MIC_DETECT_3:
1369 case WM8915_CHARGE_PUMP_1:
1370 case WM8915_CHARGE_PUMP_2:
1371 case WM8915_DC_SERVO_1:
1372 case WM8915_DC_SERVO_2:
1373 case WM8915_DC_SERVO_3:
1374 case WM8915_DC_SERVO_5:
1375 case WM8915_DC_SERVO_6:
1376 case WM8915_DC_SERVO_7:
1377 case WM8915_DC_SERVO_READBACK_0:
1378 case WM8915_ANALOGUE_HP_1:
1379 case WM8915_ANALOGUE_HP_2:
1380 case WM8915_CHIP_REVISION:
1381 case WM8915_CONTROL_INTERFACE_1:
1382 case WM8915_WRITE_SEQUENCER_CTRL_1:
1383 case WM8915_WRITE_SEQUENCER_CTRL_2:
1384 case WM8915_AIF_CLOCKING_1:
1385 case WM8915_AIF_CLOCKING_2:
1386 case WM8915_CLOCKING_1:
1387 case WM8915_CLOCKING_2:
1388 case WM8915_AIF_RATE:
1389 case WM8915_FLL_CONTROL_1:
1390 case WM8915_FLL_CONTROL_2:
1391 case WM8915_FLL_CONTROL_3:
1392 case WM8915_FLL_CONTROL_4:
1393 case WM8915_FLL_CONTROL_5:
1394 case WM8915_FLL_CONTROL_6:
1395 case WM8915_FLL_EFS_1:
1396 case WM8915_FLL_EFS_2:
1397 case WM8915_AIF1_CONTROL:
1398 case WM8915_AIF1_BCLK:
1399 case WM8915_AIF1_TX_LRCLK_1:
1400 case WM8915_AIF1_TX_LRCLK_2:
1401 case WM8915_AIF1_RX_LRCLK_1:
1402 case WM8915_AIF1_RX_LRCLK_2:
1403 case WM8915_AIF1TX_DATA_CONFIGURATION_1:
1404 case WM8915_AIF1TX_DATA_CONFIGURATION_2:
1405 case WM8915_AIF1RX_DATA_CONFIGURATION:
1406 case WM8915_AIF1TX_CHANNEL_0_CONFIGURATION:
1407 case WM8915_AIF1TX_CHANNEL_1_CONFIGURATION:
1408 case WM8915_AIF1TX_CHANNEL_2_CONFIGURATION:
1409 case WM8915_AIF1TX_CHANNEL_3_CONFIGURATION:
1410 case WM8915_AIF1TX_CHANNEL_4_CONFIGURATION:
1411 case WM8915_AIF1TX_CHANNEL_5_CONFIGURATION:
1412 case WM8915_AIF1RX_CHANNEL_0_CONFIGURATION:
1413 case WM8915_AIF1RX_CHANNEL_1_CONFIGURATION:
1414 case WM8915_AIF1RX_CHANNEL_2_CONFIGURATION:
1415 case WM8915_AIF1RX_CHANNEL_3_CONFIGURATION:
1416 case WM8915_AIF1RX_CHANNEL_4_CONFIGURATION:
1417 case WM8915_AIF1RX_CHANNEL_5_CONFIGURATION:
1418 case WM8915_AIF1RX_MONO_CONFIGURATION:
1419 case WM8915_AIF1TX_TEST:
1420 case WM8915_AIF2_CONTROL:
1421 case WM8915_AIF2_BCLK:
1422 case WM8915_AIF2_TX_LRCLK_1:
1423 case WM8915_AIF2_TX_LRCLK_2:
1424 case WM8915_AIF2_RX_LRCLK_1:
1425 case WM8915_AIF2_RX_LRCLK_2:
1426 case WM8915_AIF2TX_DATA_CONFIGURATION_1:
1427 case WM8915_AIF2TX_DATA_CONFIGURATION_2:
1428 case WM8915_AIF2RX_DATA_CONFIGURATION:
1429 case WM8915_AIF2TX_CHANNEL_0_CONFIGURATION:
1430 case WM8915_AIF2TX_CHANNEL_1_CONFIGURATION:
1431 case WM8915_AIF2RX_CHANNEL_0_CONFIGURATION:
1432 case WM8915_AIF2RX_CHANNEL_1_CONFIGURATION:
1433 case WM8915_AIF2RX_MONO_CONFIGURATION:
1434 case WM8915_AIF2TX_TEST:
1435 case WM8915_DSP1_TX_LEFT_VOLUME:
1436 case WM8915_DSP1_TX_RIGHT_VOLUME:
1437 case WM8915_DSP1_RX_LEFT_VOLUME:
1438 case WM8915_DSP1_RX_RIGHT_VOLUME:
1439 case WM8915_DSP1_TX_FILTERS:
1440 case WM8915_DSP1_RX_FILTERS_1:
1441 case WM8915_DSP1_RX_FILTERS_2:
1442 case WM8915_DSP1_DRC_1:
1443 case WM8915_DSP1_DRC_2:
1444 case WM8915_DSP1_DRC_3:
1445 case WM8915_DSP1_DRC_4:
1446 case WM8915_DSP1_DRC_5:
1447 case WM8915_DSP1_RX_EQ_GAINS_1:
1448 case WM8915_DSP1_RX_EQ_GAINS_2:
1449 case WM8915_DSP1_RX_EQ_BAND_1_A:
1450 case WM8915_DSP1_RX_EQ_BAND_1_B:
1451 case WM8915_DSP1_RX_EQ_BAND_1_PG:
1452 case WM8915_DSP1_RX_EQ_BAND_2_A:
1453 case WM8915_DSP1_RX_EQ_BAND_2_B:
1454 case WM8915_DSP1_RX_EQ_BAND_2_C:
1455 case WM8915_DSP1_RX_EQ_BAND_2_PG:
1456 case WM8915_DSP1_RX_EQ_BAND_3_A:
1457 case WM8915_DSP1_RX_EQ_BAND_3_B:
1458 case WM8915_DSP1_RX_EQ_BAND_3_C:
1459 case WM8915_DSP1_RX_EQ_BAND_3_PG:
1460 case WM8915_DSP1_RX_EQ_BAND_4_A:
1461 case WM8915_DSP1_RX_EQ_BAND_4_B:
1462 case WM8915_DSP1_RX_EQ_BAND_4_C:
1463 case WM8915_DSP1_RX_EQ_BAND_4_PG:
1464 case WM8915_DSP1_RX_EQ_BAND_5_A:
1465 case WM8915_DSP1_RX_EQ_BAND_5_B:
1466 case WM8915_DSP1_RX_EQ_BAND_5_PG:
1467 case WM8915_DSP2_TX_LEFT_VOLUME:
1468 case WM8915_DSP2_TX_RIGHT_VOLUME:
1469 case WM8915_DSP2_RX_LEFT_VOLUME:
1470 case WM8915_DSP2_RX_RIGHT_VOLUME:
1471 case WM8915_DSP2_TX_FILTERS:
1472 case WM8915_DSP2_RX_FILTERS_1:
1473 case WM8915_DSP2_RX_FILTERS_2:
1474 case WM8915_DSP2_DRC_1:
1475 case WM8915_DSP2_DRC_2:
1476 case WM8915_DSP2_DRC_3:
1477 case WM8915_DSP2_DRC_4:
1478 case WM8915_DSP2_DRC_5:
1479 case WM8915_DSP2_RX_EQ_GAINS_1:
1480 case WM8915_DSP2_RX_EQ_GAINS_2:
1481 case WM8915_DSP2_RX_EQ_BAND_1_A:
1482 case WM8915_DSP2_RX_EQ_BAND_1_B:
1483 case WM8915_DSP2_RX_EQ_BAND_1_PG:
1484 case WM8915_DSP2_RX_EQ_BAND_2_A:
1485 case WM8915_DSP2_RX_EQ_BAND_2_B:
1486 case WM8915_DSP2_RX_EQ_BAND_2_C:
1487 case WM8915_DSP2_RX_EQ_BAND_2_PG:
1488 case WM8915_DSP2_RX_EQ_BAND_3_A:
1489 case WM8915_DSP2_RX_EQ_BAND_3_B:
1490 case WM8915_DSP2_RX_EQ_BAND_3_C:
1491 case WM8915_DSP2_RX_EQ_BAND_3_PG:
1492 case WM8915_DSP2_RX_EQ_BAND_4_A:
1493 case WM8915_DSP2_RX_EQ_BAND_4_B:
1494 case WM8915_DSP2_RX_EQ_BAND_4_C:
1495 case WM8915_DSP2_RX_EQ_BAND_4_PG:
1496 case WM8915_DSP2_RX_EQ_BAND_5_A:
1497 case WM8915_DSP2_RX_EQ_BAND_5_B:
1498 case WM8915_DSP2_RX_EQ_BAND_5_PG:
1499 case WM8915_DAC1_MIXER_VOLUMES:
1500 case WM8915_DAC1_LEFT_MIXER_ROUTING:
1501 case WM8915_DAC1_RIGHT_MIXER_ROUTING:
1502 case WM8915_DAC2_MIXER_VOLUMES:
1503 case WM8915_DAC2_LEFT_MIXER_ROUTING:
1504 case WM8915_DAC2_RIGHT_MIXER_ROUTING:
1505 case WM8915_DSP1_TX_LEFT_MIXER_ROUTING:
1506 case WM8915_DSP1_TX_RIGHT_MIXER_ROUTING:
1507 case WM8915_DSP2_TX_LEFT_MIXER_ROUTING:
1508 case WM8915_DSP2_TX_RIGHT_MIXER_ROUTING:
1509 case WM8915_DSP_TX_MIXER_SELECT:
1510 case WM8915_DAC_SOFTMUTE:
1511 case WM8915_OVERSAMPLING:
1512 case WM8915_SIDETONE:
1513 case WM8915_GPIO_1:
1514 case WM8915_GPIO_2:
1515 case WM8915_GPIO_3:
1516 case WM8915_GPIO_4:
1517 case WM8915_GPIO_5:
1518 case WM8915_PULL_CONTROL_1:
1519 case WM8915_PULL_CONTROL_2:
1520 case WM8915_INTERRUPT_STATUS_1:
1521 case WM8915_INTERRUPT_STATUS_2:
1522 case WM8915_INTERRUPT_RAW_STATUS_2:
1523 case WM8915_INTERRUPT_STATUS_1_MASK:
1524 case WM8915_INTERRUPT_STATUS_2_MASK:
1525 case WM8915_INTERRUPT_CONTROL:
1526 case WM8915_LEFT_PDM_SPEAKER:
1527 case WM8915_RIGHT_PDM_SPEAKER:
1528 case WM8915_PDM_SPEAKER_MUTE_SEQUENCE:
1529 case WM8915_PDM_SPEAKER_VOLUME:
1530 return 1;
1531 default:
1532 return 0;
1533 }
1534}
1535
1536static int wm8915_volatile_register(struct snd_soc_codec *codec,
1537 unsigned int reg)
1538{
1539 switch (reg) {
1540 case WM8915_SOFTWARE_RESET:
1541 case WM8915_CHIP_REVISION:
1542 case WM8915_LDO_1:
1543 case WM8915_LDO_2:
1544 case WM8915_INTERRUPT_STATUS_1:
1545 case WM8915_INTERRUPT_STATUS_2:
1546 case WM8915_INTERRUPT_RAW_STATUS_2:
1547 case WM8915_DC_SERVO_READBACK_0:
1548 case WM8915_DC_SERVO_2:
1549 case WM8915_DC_SERVO_6:
1550 case WM8915_DC_SERVO_7:
1551 case WM8915_FLL_CONTROL_6:
1552 case WM8915_MIC_DETECT_3:
1553 case WM8915_HEADPHONE_DETECT_1:
1554 case WM8915_HEADPHONE_DETECT_2:
1555 return 1;
1556 default:
1557 return 0;
1558 }
1559}
1560
1561static int wm8915_reset(struct snd_soc_codec *codec)
1562{
1563 return snd_soc_write(codec, WM8915_SOFTWARE_RESET, 0x8915);
1564}
1565
1566static const int bclk_divs[] = {
1567 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1568};
1569
1570static void wm8915_update_bclk(struct snd_soc_codec *codec)
1571{
1572 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1573 int aif, best, cur_val, bclk_rate, bclk_reg, i;
1574
1575 /* Don't bother if we're in a low frequency idle mode that
1576 * can't support audio.
1577 */
1578 if (wm8915->sysclk < 64000)
1579 return;
1580
1581 for (aif = 0; aif < WM8915_AIFS; aif++) {
1582 switch (aif) {
1583 case 0:
1584 bclk_reg = WM8915_AIF1_BCLK;
1585 break;
1586 case 1:
1587 bclk_reg = WM8915_AIF2_BCLK;
1588 break;
1589 }
1590
1591 bclk_rate = wm8915->bclk_rate[aif];
1592
1593 /* Pick a divisor for BCLK as close as we can get to ideal */
1594 best = 0;
1595 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1596 cur_val = (wm8915->sysclk / bclk_divs[i]) - bclk_rate;
1597 if (cur_val < 0) /* BCLK table is sorted */
1598 break;
1599 best = i;
1600 }
1601 bclk_rate = wm8915->sysclk / bclk_divs[best];
1602 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1603 bclk_divs[best], bclk_rate);
1604
1605 snd_soc_update_bits(codec, bclk_reg,
1606 WM8915_AIF1_BCLK_DIV_MASK, best);
1607 }
1608}
1609
1610static int wm8915_set_bias_level(struct snd_soc_codec *codec,
1611 enum snd_soc_bias_level level)
1612{
1613 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1614 int ret;
1615
1616 switch (level) {
1617 case SND_SOC_BIAS_ON:
1618 break;
1619
1620 case SND_SOC_BIAS_PREPARE:
1621 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1622 snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1,
1623 WM8915_BG_ENA, WM8915_BG_ENA);
1624 msleep(2);
1625 }
1626 break;
1627
1628 case SND_SOC_BIAS_STANDBY:
1629 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1630 ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies),
1631 wm8915->supplies);
1632 if (ret != 0) {
1633 dev_err(codec->dev,
1634 "Failed to enable supplies: %d\n",
1635 ret);
1636 return ret;
1637 }
1638
1639 if (wm8915->pdata.ldo_ena >= 0) {
1640 gpio_set_value_cansleep(wm8915->pdata.ldo_ena,
1641 1);
1642 msleep(5);
1643 }
1644
1645 codec->cache_only = false;
1646 snd_soc_cache_sync(codec);
1647 }
1648
1649 snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1,
1650 WM8915_BG_ENA, 0);
1651 break;
1652
1653 case SND_SOC_BIAS_OFF:
1654 codec->cache_only = true;
1655 if (wm8915->pdata.ldo_ena >= 0)
1656 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
1657 regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies),
1658 wm8915->supplies);
1659 break;
1660 }
1661
1662 codec->dapm.bias_level = level;
1663
1664 return 0;
1665}
1666
1667static int wm8915_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1668{
1669 struct snd_soc_codec *codec = dai->codec;
1670 int aifctrl = 0;
1671 int bclk = 0;
1672 int lrclk_tx = 0;
1673 int lrclk_rx = 0;
1674 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1675
1676 switch (dai->id) {
1677 case 0:
1678 aifctrl_reg = WM8915_AIF1_CONTROL;
1679 bclk_reg = WM8915_AIF1_BCLK;
1680 lrclk_tx_reg = WM8915_AIF1_TX_LRCLK_2;
1681 lrclk_rx_reg = WM8915_AIF1_RX_LRCLK_2;
1682 break;
1683 case 1:
1684 aifctrl_reg = WM8915_AIF2_CONTROL;
1685 bclk_reg = WM8915_AIF2_BCLK;
1686 lrclk_tx_reg = WM8915_AIF2_TX_LRCLK_2;
1687 lrclk_rx_reg = WM8915_AIF2_RX_LRCLK_2;
1688 break;
1689 default:
1690 BUG();
1691 return -EINVAL;
1692 }
1693
1694 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1695 case SND_SOC_DAIFMT_NB_NF:
1696 break;
1697 case SND_SOC_DAIFMT_IB_NF:
1698 bclk |= WM8915_AIF1_BCLK_INV;
1699 break;
1700 case SND_SOC_DAIFMT_NB_IF:
1701 lrclk_tx |= WM8915_AIF1TX_LRCLK_INV;
1702 lrclk_rx |= WM8915_AIF1RX_LRCLK_INV;
1703 break;
1704 case SND_SOC_DAIFMT_IB_IF:
1705 bclk |= WM8915_AIF1_BCLK_INV;
1706 lrclk_tx |= WM8915_AIF1TX_LRCLK_INV;
1707 lrclk_rx |= WM8915_AIF1RX_LRCLK_INV;
1708 break;
1709 }
1710
1711 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1712 case SND_SOC_DAIFMT_CBS_CFS:
1713 break;
1714 case SND_SOC_DAIFMT_CBS_CFM:
1715 lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR;
1716 lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR;
1717 break;
1718 case SND_SOC_DAIFMT_CBM_CFS:
1719 bclk |= WM8915_AIF1_BCLK_MSTR;
1720 break;
1721 case SND_SOC_DAIFMT_CBM_CFM:
1722 bclk |= WM8915_AIF1_BCLK_MSTR;
1723 lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR;
1724 lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR;
1725 break;
1726 default:
1727 return -EINVAL;
1728 }
1729
1730 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1731 case SND_SOC_DAIFMT_DSP_A:
1732 break;
1733 case SND_SOC_DAIFMT_DSP_B:
1734 aifctrl |= 1;
1735 break;
1736 case SND_SOC_DAIFMT_I2S:
1737 aifctrl |= 2;
1738 break;
1739 case SND_SOC_DAIFMT_LEFT_J:
1740 aifctrl |= 3;
1741 break;
1742 default:
1743 return -EINVAL;
1744 }
1745
1746 snd_soc_update_bits(codec, aifctrl_reg, WM8915_AIF1_FMT_MASK, aifctrl);
1747 snd_soc_update_bits(codec, bclk_reg,
1748 WM8915_AIF1_BCLK_INV | WM8915_AIF1_BCLK_MSTR,
1749 bclk);
1750 snd_soc_update_bits(codec, lrclk_tx_reg,
1751 WM8915_AIF1TX_LRCLK_INV |
1752 WM8915_AIF1TX_LRCLK_MSTR,
1753 lrclk_tx);
1754 snd_soc_update_bits(codec, lrclk_rx_reg,
1755 WM8915_AIF1RX_LRCLK_INV |
1756 WM8915_AIF1RX_LRCLK_MSTR,
1757 lrclk_rx);
1758
1759 return 0;
1760}
1761
1762static const int dsp_divs[] = {
1763 48000, 32000, 16000, 8000
1764};
1765
1766static int wm8915_hw_params(struct snd_pcm_substream *substream,
1767 struct snd_pcm_hw_params *params,
1768 struct snd_soc_dai *dai)
1769{
1770 struct snd_soc_codec *codec = dai->codec;
1771 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1772 int bits, i, bclk_rate;
1773 int aifdata = 0;
1774 int lrclk = 0;
1775 int dsp = 0;
1776 int aifdata_reg, lrclk_reg, dsp_shift;
1777
1778 switch (dai->id) {
1779 case 0:
1780 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1781 (snd_soc_read(codec, WM8915_GPIO_1)) & WM8915_GP1_FN_MASK) {
1782 aifdata_reg = WM8915_AIF1RX_DATA_CONFIGURATION;
1783 lrclk_reg = WM8915_AIF1_RX_LRCLK_1;
1784 } else {
1785 aifdata_reg = WM8915_AIF1TX_DATA_CONFIGURATION_1;
1786 lrclk_reg = WM8915_AIF1_TX_LRCLK_1;
1787 }
1788 dsp_shift = 0;
1789 break;
1790 case 1:
1791 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1792 (snd_soc_read(codec, WM8915_GPIO_2)) & WM8915_GP2_FN_MASK) {
1793 aifdata_reg = WM8915_AIF2RX_DATA_CONFIGURATION;
1794 lrclk_reg = WM8915_AIF2_RX_LRCLK_1;
1795 } else {
1796 aifdata_reg = WM8915_AIF2TX_DATA_CONFIGURATION_1;
1797 lrclk_reg = WM8915_AIF2_TX_LRCLK_1;
1798 }
1799 dsp_shift = WM8915_DSP2_DIV_SHIFT;
1800 break;
1801 default:
1802 BUG();
1803 return -EINVAL;
1804 }
1805
1806 bclk_rate = snd_soc_params_to_bclk(params);
1807 if (bclk_rate < 0) {
1808 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1809 return bclk_rate;
1810 }
1811
1812 wm8915->bclk_rate[dai->id] = bclk_rate;
1813 wm8915->rx_rate[dai->id] = params_rate(params);
1814
1815 /* Needs looking at for TDM */
1816 bits = snd_pcm_format_width(params_format(params));
1817 if (bits < 0)
1818 return bits;
1819 aifdata |= (bits << WM8915_AIF1TX_WL_SHIFT) | bits;
1820
1821 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1822 if (dsp_divs[i] == params_rate(params))
1823 break;
1824 }
1825 if (i == ARRAY_SIZE(dsp_divs)) {
1826 dev_err(codec->dev, "Unsupported sample rate %dHz\n",
1827 params_rate(params));
1828 return -EINVAL;
1829 }
1830 dsp |= i << dsp_shift;
1831
1832 wm8915_update_bclk(codec);
1833
1834 lrclk = bclk_rate / params_rate(params);
1835 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1836 lrclk, bclk_rate / lrclk);
1837
1838 snd_soc_update_bits(codec, aifdata_reg,
1839 WM8915_AIF1TX_WL_MASK |
1840 WM8915_AIF1TX_SLOT_LEN_MASK,
1841 aifdata);
1842 snd_soc_update_bits(codec, lrclk_reg, WM8915_AIF1RX_RATE_MASK,
1843 lrclk);
1844 snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_2,
1845 WM8915_DSP1_DIV_SHIFT << dsp_shift, dsp);
1846
1847 return 0;
1848}
1849
1850static int wm8915_set_sysclk(struct snd_soc_dai *dai,
1851 int clk_id, unsigned int freq, int dir)
1852{
1853 struct snd_soc_codec *codec = dai->codec;
1854 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1855 int lfclk = 0;
1856 int ratediv = 0;
1857 int src;
1858 int old;
1859
1860 if (freq == wm8915->sysclk && clk_id == wm8915->sysclk_src)
1861 return 0;
1862
1863 /* Disable SYSCLK while we reconfigure */
1864 old = snd_soc_read(codec, WM8915_AIF_CLOCKING_1) & WM8915_SYSCLK_ENA;
1865 snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
1866 WM8915_SYSCLK_ENA, 0);
1867
1868 switch (clk_id) {
1869 case WM8915_SYSCLK_MCLK1:
1870 wm8915->sysclk = freq;
1871 src = 0;
1872 break;
1873 case WM8915_SYSCLK_MCLK2:
1874 wm8915->sysclk = freq;
1875 src = 1;
1876 break;
1877 case WM8915_SYSCLK_FLL:
1878 wm8915->sysclk = freq;
1879 src = 2;
1880 break;
1881 default:
1882 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
1883 return -EINVAL;
1884 }
1885
1886 switch (wm8915->sysclk) {
1887 case 6144000:
1888 snd_soc_update_bits(codec, WM8915_AIF_RATE,
1889 WM8915_SYSCLK_RATE, 0);
1890 break;
1891 case 24576000:
1892 ratediv = WM8915_SYSCLK_DIV;
1893 case 12288000:
1894 snd_soc_update_bits(codec, WM8915_AIF_RATE,
1895 WM8915_SYSCLK_RATE, WM8915_SYSCLK_RATE);
1896 break;
1897 case 32000:
1898 case 32768:
1899 lfclk = WM8915_LFCLK_ENA;
1900 break;
1901 default:
1902 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
1903 wm8915->sysclk);
1904 return -EINVAL;
1905 }
1906
1907 wm8915_update_bclk(codec);
1908
1909 snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
1910 WM8915_SYSCLK_SRC_MASK | WM8915_SYSCLK_DIV_MASK,
1911 src << WM8915_SYSCLK_SRC_SHIFT | ratediv);
1912 snd_soc_update_bits(codec, WM8915_CLOCKING_1, WM8915_LFCLK_ENA, lfclk);
1913 snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
1914 WM8915_SYSCLK_ENA, old);
1915
1916 wm8915->sysclk_src = clk_id;
1917
1918 return 0;
1919}
1920
1921struct _fll_div {
1922 u16 fll_fratio;
1923 u16 fll_outdiv;
1924 u16 fll_refclk_div;
1925 u16 fll_loop_gain;
1926 u16 fll_ref_freq;
1927 u16 n;
1928 u16 theta;
1929 u16 lambda;
1930};
1931
1932static struct {
1933 unsigned int min;
1934 unsigned int max;
1935 u16 fll_fratio;
1936 int ratio;
1937} fll_fratios[] = {
1938 { 0, 64000, 4, 16 },
1939 { 64000, 128000, 3, 8 },
1940 { 128000, 256000, 2, 4 },
1941 { 256000, 1000000, 1, 2 },
1942 { 1000000, 13500000, 0, 1 },
1943};
1944
1945static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1946 unsigned int Fout)
1947{
1948 unsigned int target;
1949 unsigned int div;
1950 unsigned int fratio, gcd_fll;
1951 int i;
1952
1953 /* Fref must be <=13.5MHz */
1954 div = 1;
1955 fll_div->fll_refclk_div = 0;
1956 while ((Fref / div) > 13500000) {
1957 div *= 2;
1958 fll_div->fll_refclk_div++;
1959
1960 if (div > 8) {
1961 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1962 Fref);
1963 return -EINVAL;
1964 }
1965 }
1966
1967 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1968
1969 /* Apply the division for our remaining calculations */
1970 Fref /= div;
1971
1972 if (Fref >= 3000000)
1973 fll_div->fll_loop_gain = 5;
1974 else
1975 fll_div->fll_loop_gain = 0;
1976
1977 if (Fref >= 48000)
1978 fll_div->fll_ref_freq = 0;
1979 else
1980 fll_div->fll_ref_freq = 1;
1981
1982 /* Fvco should be 90-100MHz; don't check the upper bound */
1983 div = 2;
1984 while (Fout * div < 90000000) {
1985 div++;
1986 if (div > 64) {
1987 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1988 Fout);
1989 return -EINVAL;
1990 }
1991 }
1992 target = Fout * div;
1993 fll_div->fll_outdiv = div - 1;
1994
1995 pr_debug("FLL Fvco=%dHz\n", target);
1996
1997 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1998 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1999 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2000 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2001 fratio = fll_fratios[i].ratio;
2002 break;
2003 }
2004 }
2005 if (i == ARRAY_SIZE(fll_fratios)) {
2006 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2007 return -EINVAL;
2008 }
2009
2010 fll_div->n = target / (fratio * Fref);
2011
2012 if (target % Fref == 0) {
2013 fll_div->theta = 0;
2014 fll_div->lambda = 0;
2015 } else {
2016 gcd_fll = gcd(target, fratio * Fref);
2017
2018 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2019 / gcd_fll;
2020 fll_div->lambda = (fratio * Fref) / gcd_fll;
2021 }
2022
2023 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2024 fll_div->n, fll_div->theta, fll_div->lambda);
2025 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2026 fll_div->fll_fratio, fll_div->fll_outdiv,
2027 fll_div->fll_refclk_div);
2028
2029 return 0;
2030}
2031
2032static int wm8915_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2033 unsigned int Fref, unsigned int Fout)
2034{
2035 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2036 struct i2c_client *i2c = to_i2c_client(codec->dev);
2037 struct _fll_div fll_div;
2038 unsigned long timeout;
2039 int ret, reg;
2040
2041 /* Any change? */
2042 if (source == wm8915->fll_src && Fref == wm8915->fll_fref &&
2043 Fout == wm8915->fll_fout)
2044 return 0;
2045
2046 if (Fout == 0) {
2047 dev_dbg(codec->dev, "FLL disabled\n");
2048
2049 wm8915->fll_fref = 0;
2050 wm8915->fll_fout = 0;
2051
2052 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1,
2053 WM8915_FLL_ENA, 0);
2054
2055 return 0;
2056 }
2057
2058 ret = fll_factors(&fll_div, Fref, Fout);
2059 if (ret != 0)
2060 return ret;
2061
2062 switch (source) {
2063 case WM8915_FLL_MCLK1:
2064 reg = 0;
2065 break;
2066 case WM8915_FLL_MCLK2:
2067 reg = 1;
2068 break;
2069 case WM8915_FLL_DACLRCLK1:
2070 reg = 2;
2071 break;
2072 case WM8915_FLL_BCLK1:
2073 reg = 3;
2074 break;
2075 default:
2076 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2077 return -EINVAL;
2078 }
2079
2080 reg |= fll_div.fll_refclk_div << WM8915_FLL_REFCLK_DIV_SHIFT;
2081 reg |= fll_div.fll_ref_freq << WM8915_FLL_REF_FREQ_SHIFT;
2082
2083 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_5,
2084 WM8915_FLL_REFCLK_DIV_MASK | WM8915_FLL_REF_FREQ |
2085 WM8915_FLL_REFCLK_SRC_MASK, reg);
2086
2087 reg = 0;
2088 if (fll_div.theta || fll_div.lambda)
2089 reg |= WM8915_FLL_EFS_ENA | (3 << WM8915_FLL_LFSR_SEL_SHIFT);
2090 else
2091 reg |= 1 << WM8915_FLL_LFSR_SEL_SHIFT;
2092 snd_soc_write(codec, WM8915_FLL_EFS_2, reg);
2093
2094 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_2,
2095 WM8915_FLL_OUTDIV_MASK |
2096 WM8915_FLL_FRATIO_MASK,
2097 (fll_div.fll_outdiv << WM8915_FLL_OUTDIV_SHIFT) |
2098 (fll_div.fll_fratio));
2099
2100 snd_soc_write(codec, WM8915_FLL_CONTROL_3, fll_div.theta);
2101
2102 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_4,
2103 WM8915_FLL_N_MASK | WM8915_FLL_LOOP_GAIN_MASK,
2104 (fll_div.n << WM8915_FLL_N_SHIFT) |
2105 fll_div.fll_loop_gain);
2106
2107 snd_soc_write(codec, WM8915_FLL_EFS_1, fll_div.lambda);
2108
2109 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1,
2110 WM8915_FLL_ENA, WM8915_FLL_ENA);
2111
2112 /* The FLL supports live reconfiguration - kick that in case we were
2113 * already enabled.
2114 */
2115 snd_soc_write(codec, WM8915_FLL_CONTROL_6, WM8915_FLL_SWITCH_CLK);
2116
2117 /* Wait for the FLL to lock, using the interrupt if possible */
2118 if (Fref > 1000000)
2119 timeout = usecs_to_jiffies(300);
2120 else
2121 timeout = msecs_to_jiffies(2);
2122
2123 /* Allow substantially longer if we've actually got the IRQ */
2124 if (i2c->irq)
2125 timeout *= 1000;
2126
2127 ret = wait_for_completion_timeout(&wm8915->fll_lock, timeout);
2128
2129 if (ret == 0 && i2c->irq) {
2130 dev_err(codec->dev, "Timed out waiting for FLL\n");
2131 ret = -ETIMEDOUT;
2132 } else {
2133 ret = 0;
2134 }
2135
2136 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2137
2138 wm8915->fll_fref = Fref;
2139 wm8915->fll_fout = Fout;
2140 wm8915->fll_src = source;
2141
2142 return ret;
2143}
2144
2145#ifdef CONFIG_GPIOLIB
2146static inline struct wm8915_priv *gpio_to_wm8915(struct gpio_chip *chip)
2147{
2148 return container_of(chip, struct wm8915_priv, gpio_chip);
2149}
2150
2151static void wm8915_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2152{
2153 struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2154 struct snd_soc_codec *codec = wm8915->codec;
2155
2156 snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2157 WM8915_GP1_LVL, !!value << WM8915_GP1_LVL_SHIFT);
2158}
2159
2160static int wm8915_gpio_direction_out(struct gpio_chip *chip,
2161 unsigned offset, int value)
2162{
2163 struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2164 struct snd_soc_codec *codec = wm8915->codec;
2165 int val;
2166
2167 val = (1 << WM8915_GP1_FN_SHIFT) | (!!value << WM8915_GP1_LVL_SHIFT);
2168
2169 return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2170 WM8915_GP1_FN_MASK | WM8915_GP1_DIR |
2171 WM8915_GP1_LVL, val);
2172}
2173
2174static int wm8915_gpio_get(struct gpio_chip *chip, unsigned offset)
2175{
2176 struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2177 struct snd_soc_codec *codec = wm8915->codec;
2178 int ret;
2179
2180 ret = snd_soc_read(codec, WM8915_GPIO_1 + offset);
2181 if (ret < 0)
2182 return ret;
2183
2184 return (ret & WM8915_GP1_LVL) != 0;
2185}
2186
2187static int wm8915_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2188{
2189 struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2190 struct snd_soc_codec *codec = wm8915->codec;
2191
2192 return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2193 WM8915_GP1_FN_MASK | WM8915_GP1_DIR,
2194 (1 << WM8915_GP1_FN_SHIFT) |
2195 (1 << WM8915_GP1_DIR_SHIFT));
2196}
2197
2198static struct gpio_chip wm8915_template_chip = {
2199 .label = "wm8915",
2200 .owner = THIS_MODULE,
2201 .direction_output = wm8915_gpio_direction_out,
2202 .set = wm8915_gpio_set,
2203 .direction_input = wm8915_gpio_direction_in,
2204 .get = wm8915_gpio_get,
2205 .can_sleep = 1,
2206};
2207
2208static void wm8915_init_gpio(struct snd_soc_codec *codec)
2209{
2210 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2211 int ret;
2212
2213 wm8915->gpio_chip = wm8915_template_chip;
2214 wm8915->gpio_chip.ngpio = 5;
2215 wm8915->gpio_chip.dev = codec->dev;
2216
2217 if (wm8915->pdata.gpio_base)
2218 wm8915->gpio_chip.base = wm8915->pdata.gpio_base;
2219 else
2220 wm8915->gpio_chip.base = -1;
2221
2222 ret = gpiochip_add(&wm8915->gpio_chip);
2223 if (ret != 0)
2224 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
2225}
2226
2227static void wm8915_free_gpio(struct snd_soc_codec *codec)
2228{
2229 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2230 int ret;
2231
2232 ret = gpiochip_remove(&wm8915->gpio_chip);
2233 if (ret != 0)
2234 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
2235}
2236#else
2237static void wm8915_init_gpio(struct snd_soc_codec *codec)
2238{
2239}
2240
2241static void wm8915_free_gpio(struct snd_soc_codec *codec)
2242{
2243}
2244#endif
2245
2246/**
2247 * wm8915_detect - Enable default WM8915 jack detection
2248 *
2249 * The WM8915 has advanced accessory detection support for headsets.
2250 * This function provides a default implementation which integrates
2251 * the majority of this functionality with minimal user configuration.
2252 *
2253 * This will detect headset, headphone and short circuit button and
2254 * will also detect inverted microphone ground connections and update
2255 * the polarity of the connections.
2256 */
2257int wm8915_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2258 wm8915_polarity_fn polarity_cb)
2259{
2260 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2261
2262 wm8915->jack = jack;
2263 wm8915->detecting = true;
2264 wm8915->polarity_cb = polarity_cb;
2265
2266 if (wm8915->polarity_cb)
2267 wm8915->polarity_cb(codec, 0);
2268
2269 /* Clear discarge to avoid noise during detection */
2270 snd_soc_update_bits(codec, WM8915_MICBIAS_1,
2271 WM8915_MICB1_DISCH, 0);
2272 snd_soc_update_bits(codec, WM8915_MICBIAS_2,
2273 WM8915_MICB2_DISCH, 0);
2274
2275 /* LDO2 powers the microphones, SYSCLK clocks detection */
2276 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2277 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2278
2279 /* We start off just enabling microphone detection - even a
2280 * plain headphone will trigger detection.
2281 */
2282 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2283 WM8915_MICD_ENA, WM8915_MICD_ENA);
2284
2285 /* Slowest detection rate, gives debounce for initial detection */
2286 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2287 WM8915_MICD_RATE_MASK,
2288 WM8915_MICD_RATE_MASK);
2289
2290 /* Enable interrupts and we're off */
2291 snd_soc_update_bits(codec, WM8915_INTERRUPT_STATUS_2_MASK,
2292 WM8915_IM_MICD_EINT, 0);
2293
2294 return 0;
2295}
2296EXPORT_SYMBOL_GPL(wm8915_detect);
2297
2298static void wm8915_micd(struct snd_soc_codec *codec)
2299{
2300 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2301 int val, reg;
2302
2303 val = snd_soc_read(codec, WM8915_MIC_DETECT_3);
2304
2305 dev_dbg(codec->dev, "Microphone event: %x\n", val);
2306
2307 if (!(val & WM8915_MICD_VALID)) {
2308 dev_warn(codec->dev, "Microphone detection state invalid\n");
2309 return;
2310 }
2311
2312 /* No accessory, reset everything and report removal */
2313 if (!(val & WM8915_MICD_STS)) {
2314 dev_dbg(codec->dev, "Jack removal detected\n");
2315 wm8915->jack_mic = false;
2316 wm8915->detecting = true;
2317 snd_soc_jack_report(wm8915->jack, 0,
2318 SND_JACK_HEADSET | SND_JACK_BTN_0);
2319 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2320 WM8915_MICD_RATE_MASK,
2321 WM8915_MICD_RATE_MASK);
2322 return;
2323 }
2324
2325 /* If the measurement is very high we've got a microphone but
2326 * do a little debounce to account for mechanical issues.
2327 */
2328 if (val & 0x400) {
2329 dev_dbg(codec->dev, "Microphone detected\n");
2330 snd_soc_jack_report(wm8915->jack, SND_JACK_HEADSET,
2331 SND_JACK_HEADSET | SND_JACK_BTN_0);
2332 wm8915->jack_mic = true;
2333 wm8915->detecting = false;
2334
2335 /* Increase poll rate to give better responsiveness
2336 * for buttons */
2337 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2338 WM8915_MICD_RATE_MASK,
2339 5 << WM8915_MICD_RATE_SHIFT);
2340 }
2341
2342 /* If we detected a lower impedence during initial startup
2343 * then we probably have the wrong polarity, flip it. Don't
2344 * do this for the lowest impedences to speed up detection of
2345 * plain headphones.
2346 */
2347 if (wm8915->detecting && (val & 0x3f0)) {
2348 reg = snd_soc_read(codec, WM8915_ACCESSORY_DETECT_MODE_2);
2349 reg ^= WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC |
2350 WM8915_MICD_BIAS_SRC;
2351 snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2,
2352 WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC |
2353 WM8915_MICD_BIAS_SRC, reg);
2354
2355 if (wm8915->polarity_cb)
2356 wm8915->polarity_cb(codec,
2357 (reg & WM8915_MICD_SRC) != 0);
2358
2359 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2360 (reg & WM8915_MICD_SRC) != 0);
2361
2362 return;
2363 }
2364
2365 /* Don't distinguish between buttons, just report any low
2366 * impedence as BTN_0.
2367 */
2368 if (val & 0x3fc) {
2369 if (wm8915->jack_mic) {
2370 dev_dbg(codec->dev, "Mic button detected\n");
2371 snd_soc_jack_report(wm8915->jack,
2372 SND_JACK_HEADSET | SND_JACK_BTN_0,
2373 SND_JACK_HEADSET | SND_JACK_BTN_0);
2374 } else {
2375 dev_dbg(codec->dev, "Headphone detected\n");
2376 snd_soc_jack_report(wm8915->jack,
2377 SND_JACK_HEADPHONE,
2378 SND_JACK_HEADSET |
2379 SND_JACK_BTN_0);
2380
2381 /* Increase the detection rate a bit for
2382 * responsiveness.
2383 */
2384 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2385 WM8915_MICD_RATE_MASK,
2386 7 << WM8915_MICD_RATE_SHIFT);
2387
2388 wm8915->detecting = false;
2389 }
2390 }
2391}
2392
2393static irqreturn_t wm8915_irq(int irq, void *data)
2394{
2395 struct snd_soc_codec *codec = data;
2396 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2397 int irq_val;
2398
2399 irq_val = snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2);
2400 if (irq_val < 0) {
2401 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2402 irq_val);
2403 return IRQ_NONE;
2404 }
2405 irq_val &= ~snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2_MASK);
2406
2407 if (irq_val & (WM8915_DCS_DONE_01_EINT | WM8915_DCS_DONE_23_EINT)) {
2408 dev_dbg(codec->dev, "DC servo IRQ\n");
2409 complete(&wm8915->dcs_done);
2410 }
2411
2412 if (irq_val & WM8915_FIFOS_ERR_EINT)
2413 dev_err(codec->dev, "Digital core FIFO error\n");
2414
2415 if (irq_val & WM8915_FLL_LOCK_EINT) {
2416 dev_dbg(codec->dev, "FLL locked\n");
2417 complete(&wm8915->fll_lock);
2418 }
2419
2420 if (irq_val & WM8915_MICD_EINT)
2421 wm8915_micd(codec);
2422
2423 if (irq_val) {
2424 snd_soc_write(codec, WM8915_INTERRUPT_STATUS_2, irq_val);
2425
2426 return IRQ_HANDLED;
2427 } else {
2428 return IRQ_NONE;
2429 }
2430}
2431
2432static irqreturn_t wm8915_edge_irq(int irq, void *data)
2433{
2434 irqreturn_t ret = IRQ_NONE;
2435 irqreturn_t val;
2436
2437 do {
2438 val = wm8915_irq(irq, data);
2439 if (val != IRQ_NONE)
2440 ret = val;
2441 } while (val != IRQ_NONE);
2442
2443 return ret;
2444}
2445
2446static void wm8915_retune_mobile_pdata(struct snd_soc_codec *codec)
2447{
2448 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2449 struct wm8915_pdata *pdata = &wm8915->pdata;
2450
2451 struct snd_kcontrol_new controls[] = {
2452 SOC_ENUM_EXT("DSP1 EQ Mode",
2453 wm8915->retune_mobile_enum,
2454 wm8915_get_retune_mobile_enum,
2455 wm8915_put_retune_mobile_enum),
2456 SOC_ENUM_EXT("DSP2 EQ Mode",
2457 wm8915->retune_mobile_enum,
2458 wm8915_get_retune_mobile_enum,
2459 wm8915_put_retune_mobile_enum),
2460 };
2461 int ret, i, j;
2462 const char **t;
2463
2464 /* We need an array of texts for the enum API but the number
2465 * of texts is likely to be less than the number of
2466 * configurations due to the sample rate dependency of the
2467 * configurations. */
2468 wm8915->num_retune_mobile_texts = 0;
2469 wm8915->retune_mobile_texts = NULL;
2470 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2471 for (j = 0; j < wm8915->num_retune_mobile_texts; j++) {
2472 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2473 wm8915->retune_mobile_texts[j]) == 0)
2474 break;
2475 }
2476
2477 if (j != wm8915->num_retune_mobile_texts)
2478 continue;
2479
2480 /* Expand the array... */
2481 t = krealloc(wm8915->retune_mobile_texts,
2482 sizeof(char *) *
2483 (wm8915->num_retune_mobile_texts + 1),
2484 GFP_KERNEL);
2485 if (t == NULL)
2486 continue;
2487
2488 /* ...store the new entry... */
2489 t[wm8915->num_retune_mobile_texts] =
2490 pdata->retune_mobile_cfgs[i].name;
2491
2492 /* ...and remember the new version. */
2493 wm8915->num_retune_mobile_texts++;
2494 wm8915->retune_mobile_texts = t;
2495 }
2496
2497 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2498 wm8915->num_retune_mobile_texts);
2499
2500 wm8915->retune_mobile_enum.max = wm8915->num_retune_mobile_texts;
2501 wm8915->retune_mobile_enum.texts = wm8915->retune_mobile_texts;
2502
2503 ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
2504 if (ret != 0)
2505 dev_err(codec->dev,
2506 "Failed to add ReTune Mobile controls: %d\n", ret);
2507}
2508
2509static int wm8915_probe(struct snd_soc_codec *codec)
2510{
2511 int ret;
2512 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2513 struct i2c_client *i2c = to_i2c_client(codec->dev);
2514 struct snd_soc_dapm_context *dapm = &codec->dapm;
2515 int i, irq_flags;
2516
2517 wm8915->codec = codec;
2518
2519 init_completion(&wm8915->dcs_done);
2520 init_completion(&wm8915->fll_lock);
2521
2522 dapm->idle_bias_off = true;
2523 dapm->bias_level = SND_SOC_BIAS_OFF;
2524
2525 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
2526 if (ret != 0) {
2527 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2528 goto err;
2529 }
2530
2531 for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++)
2532 wm8915->supplies[i].supply = wm8915_supply_names[i];
2533
2534 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8915->supplies),
2535 wm8915->supplies);
2536 if (ret != 0) {
2537 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
2538 goto err;
2539 }
2540
2541 wm8915->disable_nb[0].notifier_call = wm8915_regulator_event_0;
2542 wm8915->disable_nb[1].notifier_call = wm8915_regulator_event_1;
2543 wm8915->disable_nb[2].notifier_call = wm8915_regulator_event_2;
2544 wm8915->disable_nb[3].notifier_call = wm8915_regulator_event_3;
2545
2546 /* This should really be moved into the regulator core */
2547 for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++) {
2548 ret = regulator_register_notifier(wm8915->supplies[i].consumer,
2549 &wm8915->disable_nb[i]);
2550 if (ret != 0) {
2551 dev_err(codec->dev,
2552 "Failed to register regulator notifier: %d\n",
2553 ret);
2554 }
2555 }
2556
2557 ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies),
2558 wm8915->supplies);
2559 if (ret != 0) {
2560 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
2561 goto err_get;
2562 }
2563
2564 if (wm8915->pdata.ldo_ena >= 0) {
2565 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 1);
2566 msleep(5);
2567 }
2568
2569 ret = snd_soc_read(codec, WM8915_SOFTWARE_RESET);
2570 if (ret < 0) {
2571 dev_err(codec->dev, "Failed to read ID register: %d\n", ret);
2572 goto err_enable;
2573 }
2574 if (ret != 0x8915) {
2575 dev_err(codec->dev, "Device is not a WM8915, ID %x\n", ret);
2576 ret = -EINVAL;
2577 goto err_enable;
2578 }
2579
2580 ret = snd_soc_read(codec, WM8915_CHIP_REVISION);
2581 if (ret < 0) {
2582 dev_err(codec->dev, "Failed to read device revision: %d\n",
2583 ret);
2584 goto err_enable;
2585 }
2586
2587 dev_info(codec->dev, "revision %c\n",
2588 (ret & WM8915_CHIP_REV_MASK) + 'A');
2589
2590 if (wm8915->pdata.ldo_ena >= 0) {
2591 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
2592 } else {
2593 ret = wm8915_reset(codec);
2594 if (ret < 0) {
2595 dev_err(codec->dev, "Failed to issue reset\n");
2596 goto err_enable;
2597 }
2598 }
2599
2600 codec->cache_only = true;
2601
2602 /* Apply platform data settings */
2603 snd_soc_update_bits(codec, WM8915_LINE_INPUT_CONTROL,
2604 WM8915_INL_MODE_MASK | WM8915_INR_MODE_MASK,
2605 wm8915->pdata.inl_mode << WM8915_INL_MODE_SHIFT |
2606 wm8915->pdata.inr_mode);
2607
2608 for (i = 0; i < ARRAY_SIZE(wm8915->pdata.gpio_default); i++) {
2609 if (!wm8915->pdata.gpio_default[i])
2610 continue;
2611
2612 snd_soc_write(codec, WM8915_GPIO_1 + i,
2613 wm8915->pdata.gpio_default[i] & 0xffff);
2614 }
2615
2616 if (wm8915->pdata.spkmute_seq)
2617 snd_soc_update_bits(codec, WM8915_PDM_SPEAKER_MUTE_SEQUENCE,
2618 WM8915_SPK_MUTE_ENDIAN |
2619 WM8915_SPK_MUTE_SEQ1_MASK,
2620 wm8915->pdata.spkmute_seq);
2621
2622 snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2,
2623 WM8915_MICD_BIAS_SRC | WM8915_HPOUT1FB_SRC |
2624 WM8915_MICD_SRC, wm8915->pdata.micdet_def);
2625
2626 /* Latch volume update bits */
2627 snd_soc_update_bits(codec, WM8915_LEFT_LINE_INPUT_VOLUME,
2628 WM8915_IN1_VU, WM8915_IN1_VU);
2629 snd_soc_update_bits(codec, WM8915_RIGHT_LINE_INPUT_VOLUME,
2630 WM8915_IN1_VU, WM8915_IN1_VU);
2631
2632 snd_soc_update_bits(codec, WM8915_DAC1_LEFT_VOLUME,
2633 WM8915_DAC1_VU, WM8915_DAC1_VU);
2634 snd_soc_update_bits(codec, WM8915_DAC1_RIGHT_VOLUME,
2635 WM8915_DAC1_VU, WM8915_DAC1_VU);
2636 snd_soc_update_bits(codec, WM8915_DAC2_LEFT_VOLUME,
2637 WM8915_DAC2_VU, WM8915_DAC2_VU);
2638 snd_soc_update_bits(codec, WM8915_DAC2_RIGHT_VOLUME,
2639 WM8915_DAC2_VU, WM8915_DAC2_VU);
2640
2641 snd_soc_update_bits(codec, WM8915_OUTPUT1_LEFT_VOLUME,
2642 WM8915_DAC1_VU, WM8915_DAC1_VU);
2643 snd_soc_update_bits(codec, WM8915_OUTPUT1_RIGHT_VOLUME,
2644 WM8915_DAC1_VU, WM8915_DAC1_VU);
2645 snd_soc_update_bits(codec, WM8915_OUTPUT2_LEFT_VOLUME,
2646 WM8915_DAC2_VU, WM8915_DAC2_VU);
2647 snd_soc_update_bits(codec, WM8915_OUTPUT2_RIGHT_VOLUME,
2648 WM8915_DAC2_VU, WM8915_DAC2_VU);
2649
2650 snd_soc_update_bits(codec, WM8915_DSP1_TX_LEFT_VOLUME,
2651 WM8915_DSP1TX_VU, WM8915_DSP1TX_VU);
2652 snd_soc_update_bits(codec, WM8915_DSP1_TX_RIGHT_VOLUME,
2653 WM8915_DSP1TX_VU, WM8915_DSP1TX_VU);
2654 snd_soc_update_bits(codec, WM8915_DSP2_TX_LEFT_VOLUME,
2655 WM8915_DSP2TX_VU, WM8915_DSP2TX_VU);
2656 snd_soc_update_bits(codec, WM8915_DSP2_TX_RIGHT_VOLUME,
2657 WM8915_DSP2TX_VU, WM8915_DSP2TX_VU);
2658
2659 snd_soc_update_bits(codec, WM8915_DSP1_RX_LEFT_VOLUME,
2660 WM8915_DSP1RX_VU, WM8915_DSP1RX_VU);
2661 snd_soc_update_bits(codec, WM8915_DSP1_RX_RIGHT_VOLUME,
2662 WM8915_DSP1RX_VU, WM8915_DSP1RX_VU);
2663 snd_soc_update_bits(codec, WM8915_DSP2_RX_LEFT_VOLUME,
2664 WM8915_DSP2RX_VU, WM8915_DSP2RX_VU);
2665 snd_soc_update_bits(codec, WM8915_DSP2_RX_RIGHT_VOLUME,
2666 WM8915_DSP2RX_VU, WM8915_DSP2RX_VU);
2667
2668 /* No support currently for the underclocked TDM modes and
2669 * pick a default TDM layout with each channel pair working with
2670 * slots 0 and 1. */
2671 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_0_CONFIGURATION,
2672 WM8915_AIF1RX_CHAN0_SLOTS_MASK |
2673 WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2674 1 << WM8915_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2675 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_1_CONFIGURATION,
2676 WM8915_AIF1RX_CHAN1_SLOTS_MASK |
2677 WM8915_AIF1RX_CHAN1_START_SLOT_MASK,
2678 1 << WM8915_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2679 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_2_CONFIGURATION,
2680 WM8915_AIF1RX_CHAN2_SLOTS_MASK |
2681 WM8915_AIF1RX_CHAN2_START_SLOT_MASK,
2682 1 << WM8915_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2683 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_3_CONFIGURATION,
2684 WM8915_AIF1RX_CHAN3_SLOTS_MASK |
2685 WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2686 1 << WM8915_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2687 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_4_CONFIGURATION,
2688 WM8915_AIF1RX_CHAN4_SLOTS_MASK |
2689 WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2690 1 << WM8915_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2691 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_5_CONFIGURATION,
2692 WM8915_AIF1RX_CHAN5_SLOTS_MASK |
2693 WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2694 1 << WM8915_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2695
2696 snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_0_CONFIGURATION,
2697 WM8915_AIF2RX_CHAN0_SLOTS_MASK |
2698 WM8915_AIF2RX_CHAN0_START_SLOT_MASK,
2699 1 << WM8915_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2700 snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_1_CONFIGURATION,
2701 WM8915_AIF2RX_CHAN1_SLOTS_MASK |
2702 WM8915_AIF2RX_CHAN1_START_SLOT_MASK,
2703 1 << WM8915_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2704
2705 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_0_CONFIGURATION,
2706 WM8915_AIF1TX_CHAN0_SLOTS_MASK |
2707 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2708 1 << WM8915_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2709 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION,
2710 WM8915_AIF1TX_CHAN1_SLOTS_MASK |
2711 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2712 1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2713 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_2_CONFIGURATION,
2714 WM8915_AIF1TX_CHAN2_SLOTS_MASK |
2715 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2716 1 << WM8915_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2717 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_3_CONFIGURATION,
2718 WM8915_AIF1TX_CHAN3_SLOTS_MASK |
2719 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2720 1 << WM8915_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2721 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_4_CONFIGURATION,
2722 WM8915_AIF1TX_CHAN4_SLOTS_MASK |
2723 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2724 1 << WM8915_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2725 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_5_CONFIGURATION,
2726 WM8915_AIF1TX_CHAN5_SLOTS_MASK |
2727 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2728 1 << WM8915_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
2729
2730 snd_soc_update_bits(codec, WM8915_AIF2TX_CHANNEL_0_CONFIGURATION,
2731 WM8915_AIF2TX_CHAN0_SLOTS_MASK |
2732 WM8915_AIF2TX_CHAN0_START_SLOT_MASK,
2733 1 << WM8915_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
2734 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION,
2735 WM8915_AIF2TX_CHAN1_SLOTS_MASK |
2736 WM8915_AIF2TX_CHAN1_START_SLOT_MASK,
2737 1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2738
2739 if (wm8915->pdata.num_retune_mobile_cfgs)
2740 wm8915_retune_mobile_pdata(codec);
2741 else
2742 snd_soc_add_controls(codec, wm8915_eq_controls,
2743 ARRAY_SIZE(wm8915_eq_controls));
2744
2745 /* If the TX LRCLK pins are not in LRCLK mode configure the
2746 * AIFs to source their clocks from the RX LRCLKs.
2747 */
2748 if ((snd_soc_read(codec, WM8915_GPIO_1)))
2749 snd_soc_update_bits(codec, WM8915_AIF1_TX_LRCLK_2,
2750 WM8915_AIF1TX_LRCLK_MODE,
2751 WM8915_AIF1TX_LRCLK_MODE);
2752
2753 if ((snd_soc_read(codec, WM8915_GPIO_2)))
2754 snd_soc_update_bits(codec, WM8915_AIF2_TX_LRCLK_2,
2755 WM8915_AIF2TX_LRCLK_MODE,
2756 WM8915_AIF2TX_LRCLK_MODE);
2757
2758 regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2759
2760 wm8915_init_gpio(codec);
2761
2762 if (i2c->irq) {
2763 if (wm8915->pdata.irq_flags)
2764 irq_flags = wm8915->pdata.irq_flags;
2765 else
2766 irq_flags = IRQF_TRIGGER_LOW;
2767
2768 irq_flags |= IRQF_ONESHOT;
2769
2770 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2771 ret = request_threaded_irq(i2c->irq, NULL,
2772 wm8915_edge_irq,
2773 irq_flags, "wm8915", codec);
2774 else
2775 ret = request_threaded_irq(i2c->irq, NULL, wm8915_irq,
2776 irq_flags, "wm8915", codec);
2777
2778 if (ret == 0) {
2779 /* Unmask the interrupt */
2780 snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL,
2781 WM8915_IM_IRQ, 0);
2782
2783 /* Enable error reporting and DC servo status */
2784 snd_soc_update_bits(codec,
2785 WM8915_INTERRUPT_STATUS_2_MASK,
2786 WM8915_IM_DCS_DONE_23_EINT |
2787 WM8915_IM_DCS_DONE_01_EINT |
2788 WM8915_IM_FLL_LOCK_EINT |
2789 WM8915_IM_FIFOS_ERR_EINT,
2790 0);
2791 } else {
2792 dev_err(codec->dev, "Failed to request IRQ: %d\n",
2793 ret);
2794 }
2795 }
2796
2797 return 0;
2798
2799err_enable:
2800 if (wm8915->pdata.ldo_ena >= 0)
2801 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
2802
2803 regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2804err_get:
2805 regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2806err:
2807 return ret;
2808}
2809
2810static int wm8915_remove(struct snd_soc_codec *codec)
2811{
2812 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2813 struct i2c_client *i2c = to_i2c_client(codec->dev);
2814 int i;
2815
2816 snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL,
2817 WM8915_IM_IRQ, WM8915_IM_IRQ);
2818
2819 if (i2c->irq)
2820 free_irq(i2c->irq, codec);
2821
2822 wm8915_free_gpio(codec);
2823
2824 for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++)
2825 regulator_unregister_notifier(wm8915->supplies[i].consumer,
2826 &wm8915->disable_nb[i]);
2827 regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2828
2829 return 0;
2830}
2831
2832static struct snd_soc_codec_driver soc_codec_dev_wm8915 = {
2833 .probe = wm8915_probe,
2834 .remove = wm8915_remove,
2835 .set_bias_level = wm8915_set_bias_level,
2836 .seq_notifier = wm8915_seq_notifier,
2837 .reg_cache_size = WM8915_MAX_REGISTER + 1,
2838 .reg_word_size = sizeof(u16),
2839 .reg_cache_default = wm8915_reg,
2840 .volatile_register = wm8915_volatile_register,
2841 .readable_register = wm8915_readable_register,
2842 .compress_type = SND_SOC_RBTREE_COMPRESSION,
2843 .controls = wm8915_snd_controls,
2844 .num_controls = ARRAY_SIZE(wm8915_snd_controls),
2845 .dapm_widgets = wm8915_dapm_widgets,
2846 .num_dapm_widgets = ARRAY_SIZE(wm8915_dapm_widgets),
2847 .dapm_routes = wm8915_dapm_routes,
2848 .num_dapm_routes = ARRAY_SIZE(wm8915_dapm_routes),
2849 .set_pll = wm8915_set_fll,
2850};
2851
2852#define WM8915_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
2853 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
2854#define WM8915_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
2855 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
2856 SNDRV_PCM_FMTBIT_S32_LE)
2857
2858static struct snd_soc_dai_ops wm8915_dai_ops = {
2859 .set_fmt = wm8915_set_fmt,
2860 .hw_params = wm8915_hw_params,
2861 .set_sysclk = wm8915_set_sysclk,
2862};
2863
2864static struct snd_soc_dai_driver wm8915_dai[] = {
2865 {
2866 .name = "wm8915-aif1",
2867 .playback = {
2868 .stream_name = "AIF1 Playback",
2869 .channels_min = 1,
2870 .channels_max = 6,
2871 .rates = WM8915_RATES,
2872 .formats = WM8915_FORMATS,
2873 },
2874 .capture = {
2875 .stream_name = "AIF1 Capture",
2876 .channels_min = 1,
2877 .channels_max = 6,
2878 .rates = WM8915_RATES,
2879 .formats = WM8915_FORMATS,
2880 },
2881 .ops = &wm8915_dai_ops,
2882 },
2883 {
2884 .name = "wm8915-aif2",
2885 .playback = {
2886 .stream_name = "AIF2 Playback",
2887 .channels_min = 1,
2888 .channels_max = 2,
2889 .rates = WM8915_RATES,
2890 .formats = WM8915_FORMATS,
2891 },
2892 .capture = {
2893 .stream_name = "AIF2 Capture",
2894 .channels_min = 1,
2895 .channels_max = 2,
2896 .rates = WM8915_RATES,
2897 .formats = WM8915_FORMATS,
2898 },
2899 .ops = &wm8915_dai_ops,
2900 },
2901};
2902
2903static __devinit int wm8915_i2c_probe(struct i2c_client *i2c,
2904 const struct i2c_device_id *id)
2905{
2906 struct wm8915_priv *wm8915;
2907 int ret;
2908
2909 wm8915 = kzalloc(sizeof(struct wm8915_priv), GFP_KERNEL);
2910 if (wm8915 == NULL)
2911 return -ENOMEM;
2912
2913 i2c_set_clientdata(i2c, wm8915);
2914
2915 if (dev_get_platdata(&i2c->dev))
2916 memcpy(&wm8915->pdata, dev_get_platdata(&i2c->dev),
2917 sizeof(wm8915->pdata));
2918
2919 if (wm8915->pdata.ldo_ena > 0) {
2920 ret = gpio_request_one(wm8915->pdata.ldo_ena,
2921 GPIOF_OUT_INIT_LOW, "WM8915 ENA");
2922 if (ret < 0) {
2923 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
2924 wm8915->pdata.ldo_ena, ret);
2925 goto err;
2926 }
2927 }
2928
2929 ret = snd_soc_register_codec(&i2c->dev,
2930 &soc_codec_dev_wm8915, wm8915_dai,
2931 ARRAY_SIZE(wm8915_dai));
2932 if (ret < 0)
2933 goto err_gpio;
2934
2935 return ret;
2936
2937err_gpio:
2938 if (wm8915->pdata.ldo_ena > 0)
2939 gpio_free(wm8915->pdata.ldo_ena);
2940err:
2941 kfree(wm8915);
2942
2943 return ret;
2944}
2945
2946static __devexit int wm8915_i2c_remove(struct i2c_client *client)
2947{
2948 struct wm8915_priv *wm8915 = i2c_get_clientdata(client);
2949
2950 snd_soc_unregister_codec(&client->dev);
2951 if (wm8915->pdata.ldo_ena > 0)
2952 gpio_free(wm8915->pdata.ldo_ena);
2953 kfree(i2c_get_clientdata(client));
2954 return 0;
2955}
2956
2957static const struct i2c_device_id wm8915_i2c_id[] = {
2958 { "wm8915", 0 },
2959 { }
2960};
2961MODULE_DEVICE_TABLE(i2c, wm8915_i2c_id);
2962
2963static struct i2c_driver wm8915_i2c_driver = {
2964 .driver = {
2965 .name = "wm8915",
2966 .owner = THIS_MODULE,
2967 },
2968 .probe = wm8915_i2c_probe,
2969 .remove = __devexit_p(wm8915_i2c_remove),
2970 .id_table = wm8915_i2c_id,
2971};
2972
2973static int __init wm8915_modinit(void)
2974{
2975 int ret;
2976
2977 ret = i2c_add_driver(&wm8915_i2c_driver);
2978 if (ret != 0) {
2979 printk(KERN_ERR "Failed to register WM8915 I2C driver: %d\n",
2980 ret);
2981 }
2982
2983 return ret;
2984}
2985module_init(wm8915_modinit);
2986
2987static void __exit wm8915_exit(void)
2988{
2989 i2c_del_driver(&wm8915_i2c_driver);
2990}
2991module_exit(wm8915_exit);
2992
2993MODULE_DESCRIPTION("ASoC WM8915 driver");
2994MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2995MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8915.h b/sound/soc/codecs/wm8915.h
deleted file mode 100644
index 200ffd7bf953..000000000000
--- a/sound/soc/codecs/wm8915.h
+++ /dev/null
@@ -1,3717 +0,0 @@
1/*
2 * wm8915.h - WM8915 audio codec interface
3 *
4 * Copyright 2011 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef _WM8915_H
14#define _WM8915_H
15
16#define WM8915_SYSCLK_MCLK1 1
17#define WM8915_SYSCLK_MCLK2 2
18#define WM8915_SYSCLK_FLL 3
19
20#define WM8915_FLL_MCLK1 1
21#define WM8915_FLL_MCLK2 2
22#define WM8915_FLL_DACLRCLK1 3
23#define WM8915_FLL_BCLK1 4
24
25typedef void (*wm8915_polarity_fn)(struct snd_soc_codec *codec, int polarity);
26
27int wm8915_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
28 wm8915_polarity_fn polarity_cb);
29
30/*
31 * Register values.
32 */
33#define WM8915_SOFTWARE_RESET 0x00
34#define WM8915_POWER_MANAGEMENT_1 0x01
35#define WM8915_POWER_MANAGEMENT_2 0x02
36#define WM8915_POWER_MANAGEMENT_3 0x03
37#define WM8915_POWER_MANAGEMENT_4 0x04
38#define WM8915_POWER_MANAGEMENT_5 0x05
39#define WM8915_POWER_MANAGEMENT_6 0x06
40#define WM8915_POWER_MANAGEMENT_7 0x07
41#define WM8915_POWER_MANAGEMENT_8 0x08
42#define WM8915_LEFT_LINE_INPUT_VOLUME 0x10
43#define WM8915_RIGHT_LINE_INPUT_VOLUME 0x11
44#define WM8915_LINE_INPUT_CONTROL 0x12
45#define WM8915_DAC1_HPOUT1_VOLUME 0x15
46#define WM8915_DAC2_HPOUT2_VOLUME 0x16
47#define WM8915_DAC1_LEFT_VOLUME 0x18
48#define WM8915_DAC1_RIGHT_VOLUME 0x19
49#define WM8915_DAC2_LEFT_VOLUME 0x1A
50#define WM8915_DAC2_RIGHT_VOLUME 0x1B
51#define WM8915_OUTPUT1_LEFT_VOLUME 0x1C
52#define WM8915_OUTPUT1_RIGHT_VOLUME 0x1D
53#define WM8915_OUTPUT2_LEFT_VOLUME 0x1E
54#define WM8915_OUTPUT2_RIGHT_VOLUME 0x1F
55#define WM8915_MICBIAS_1 0x20
56#define WM8915_MICBIAS_2 0x21
57#define WM8915_LDO_1 0x28
58#define WM8915_LDO_2 0x29
59#define WM8915_ACCESSORY_DETECT_MODE_1 0x30
60#define WM8915_ACCESSORY_DETECT_MODE_2 0x31
61#define WM8915_HEADPHONE_DETECT_1 0x34
62#define WM8915_HEADPHONE_DETECT_2 0x35
63#define WM8915_MIC_DETECT_1 0x38
64#define WM8915_MIC_DETECT_2 0x39
65#define WM8915_MIC_DETECT_3 0x3A
66#define WM8915_CHARGE_PUMP_1 0x40
67#define WM8915_CHARGE_PUMP_2 0x41
68#define WM8915_DC_SERVO_1 0x50
69#define WM8915_DC_SERVO_2 0x51
70#define WM8915_DC_SERVO_3 0x52
71#define WM8915_DC_SERVO_5 0x54
72#define WM8915_DC_SERVO_6 0x55
73#define WM8915_DC_SERVO_7 0x56
74#define WM8915_DC_SERVO_READBACK_0 0x57
75#define WM8915_ANALOGUE_HP_1 0x60
76#define WM8915_ANALOGUE_HP_2 0x61
77#define WM8915_CHIP_REVISION 0x100
78#define WM8915_CONTROL_INTERFACE_1 0x101
79#define WM8915_WRITE_SEQUENCER_CTRL_1 0x110
80#define WM8915_WRITE_SEQUENCER_CTRL_2 0x111
81#define WM8915_AIF_CLOCKING_1 0x200
82#define WM8915_AIF_CLOCKING_2 0x201
83#define WM8915_CLOCKING_1 0x208
84#define WM8915_CLOCKING_2 0x209
85#define WM8915_AIF_RATE 0x210
86#define WM8915_FLL_CONTROL_1 0x220
87#define WM8915_FLL_CONTROL_2 0x221
88#define WM8915_FLL_CONTROL_3 0x222
89#define WM8915_FLL_CONTROL_4 0x223
90#define WM8915_FLL_CONTROL_5 0x224
91#define WM8915_FLL_CONTROL_6 0x225
92#define WM8915_FLL_EFS_1 0x226
93#define WM8915_FLL_EFS_2 0x227
94#define WM8915_AIF1_CONTROL 0x300
95#define WM8915_AIF1_BCLK 0x301
96#define WM8915_AIF1_TX_LRCLK_1 0x302
97#define WM8915_AIF1_TX_LRCLK_2 0x303
98#define WM8915_AIF1_RX_LRCLK_1 0x304
99#define WM8915_AIF1_RX_LRCLK_2 0x305
100#define WM8915_AIF1TX_DATA_CONFIGURATION_1 0x306
101#define WM8915_AIF1TX_DATA_CONFIGURATION_2 0x307
102#define WM8915_AIF1RX_DATA_CONFIGURATION 0x308
103#define WM8915_AIF1TX_CHANNEL_0_CONFIGURATION 0x309
104#define WM8915_AIF1TX_CHANNEL_1_CONFIGURATION 0x30A
105#define WM8915_AIF1TX_CHANNEL_2_CONFIGURATION 0x30B
106#define WM8915_AIF1TX_CHANNEL_3_CONFIGURATION 0x30C
107#define WM8915_AIF1TX_CHANNEL_4_CONFIGURATION 0x30D
108#define WM8915_AIF1TX_CHANNEL_5_CONFIGURATION 0x30E
109#define WM8915_AIF1RX_CHANNEL_0_CONFIGURATION 0x30F
110#define WM8915_AIF1RX_CHANNEL_1_CONFIGURATION 0x310
111#define WM8915_AIF1RX_CHANNEL_2_CONFIGURATION 0x311
112#define WM8915_AIF1RX_CHANNEL_3_CONFIGURATION 0x312
113#define WM8915_AIF1RX_CHANNEL_4_CONFIGURATION 0x313
114#define WM8915_AIF1RX_CHANNEL_5_CONFIGURATION 0x314
115#define WM8915_AIF1RX_MONO_CONFIGURATION 0x315
116#define WM8915_AIF1TX_TEST 0x31A
117#define WM8915_AIF2_CONTROL 0x320
118#define WM8915_AIF2_BCLK 0x321
119#define WM8915_AIF2_TX_LRCLK_1 0x322
120#define WM8915_AIF2_TX_LRCLK_2 0x323
121#define WM8915_AIF2_RX_LRCLK_1 0x324
122#define WM8915_AIF2_RX_LRCLK_2 0x325
123#define WM8915_AIF2TX_DATA_CONFIGURATION_1 0x326
124#define WM8915_AIF2TX_DATA_CONFIGURATION_2 0x327
125#define WM8915_AIF2RX_DATA_CONFIGURATION 0x328
126#define WM8915_AIF2TX_CHANNEL_0_CONFIGURATION 0x329
127#define WM8915_AIF2TX_CHANNEL_1_CONFIGURATION 0x32A
128#define WM8915_AIF2RX_CHANNEL_0_CONFIGURATION 0x32B
129#define WM8915_AIF2RX_CHANNEL_1_CONFIGURATION 0x32C
130#define WM8915_AIF2RX_MONO_CONFIGURATION 0x32D
131#define WM8915_AIF2TX_TEST 0x32F
132#define WM8915_DSP1_TX_LEFT_VOLUME 0x400
133#define WM8915_DSP1_TX_RIGHT_VOLUME 0x401
134#define WM8915_DSP1_RX_LEFT_VOLUME 0x402
135#define WM8915_DSP1_RX_RIGHT_VOLUME 0x403
136#define WM8915_DSP1_TX_FILTERS 0x410
137#define WM8915_DSP1_RX_FILTERS_1 0x420
138#define WM8915_DSP1_RX_FILTERS_2 0x421
139#define WM8915_DSP1_DRC_1 0x440
140#define WM8915_DSP1_DRC_2 0x441
141#define WM8915_DSP1_DRC_3 0x442
142#define WM8915_DSP1_DRC_4 0x443
143#define WM8915_DSP1_DRC_5 0x444
144#define WM8915_DSP1_RX_EQ_GAINS_1 0x480
145#define WM8915_DSP1_RX_EQ_GAINS_2 0x481
146#define WM8915_DSP1_RX_EQ_BAND_1_A 0x482
147#define WM8915_DSP1_RX_EQ_BAND_1_B 0x483
148#define WM8915_DSP1_RX_EQ_BAND_1_PG 0x484
149#define WM8915_DSP1_RX_EQ_BAND_2_A 0x485
150#define WM8915_DSP1_RX_EQ_BAND_2_B 0x486
151#define WM8915_DSP1_RX_EQ_BAND_2_C 0x487
152#define WM8915_DSP1_RX_EQ_BAND_2_PG 0x488
153#define WM8915_DSP1_RX_EQ_BAND_3_A 0x489
154#define WM8915_DSP1_RX_EQ_BAND_3_B 0x48A
155#define WM8915_DSP1_RX_EQ_BAND_3_C 0x48B
156#define WM8915_DSP1_RX_EQ_BAND_3_PG 0x48C
157#define WM8915_DSP1_RX_EQ_BAND_4_A 0x48D
158#define WM8915_DSP1_RX_EQ_BAND_4_B 0x48E
159#define WM8915_DSP1_RX_EQ_BAND_4_C 0x48F
160#define WM8915_DSP1_RX_EQ_BAND_4_PG 0x490
161#define WM8915_DSP1_RX_EQ_BAND_5_A 0x491
162#define WM8915_DSP1_RX_EQ_BAND_5_B 0x492
163#define WM8915_DSP1_RX_EQ_BAND_5_PG 0x493
164#define WM8915_DSP2_TX_LEFT_VOLUME 0x500
165#define WM8915_DSP2_TX_RIGHT_VOLUME 0x501
166#define WM8915_DSP2_RX_LEFT_VOLUME 0x502
167#define WM8915_DSP2_RX_RIGHT_VOLUME 0x503
168#define WM8915_DSP2_TX_FILTERS 0x510
169#define WM8915_DSP2_RX_FILTERS_1 0x520
170#define WM8915_DSP2_RX_FILTERS_2 0x521
171#define WM8915_DSP2_DRC_1 0x540
172#define WM8915_DSP2_DRC_2 0x541
173#define WM8915_DSP2_DRC_3 0x542
174#define WM8915_DSP2_DRC_4 0x543
175#define WM8915_DSP2_DRC_5 0x544
176#define WM8915_DSP2_RX_EQ_GAINS_1 0x580
177#define WM8915_DSP2_RX_EQ_GAINS_2 0x581
178#define WM8915_DSP2_RX_EQ_BAND_1_A 0x582
179#define WM8915_DSP2_RX_EQ_BAND_1_B 0x583
180#define WM8915_DSP2_RX_EQ_BAND_1_PG 0x584
181#define WM8915_DSP2_RX_EQ_BAND_2_A 0x585
182#define WM8915_DSP2_RX_EQ_BAND_2_B 0x586
183#define WM8915_DSP2_RX_EQ_BAND_2_C 0x587
184#define WM8915_DSP2_RX_EQ_BAND_2_PG 0x588
185#define WM8915_DSP2_RX_EQ_BAND_3_A 0x589
186#define WM8915_DSP2_RX_EQ_BAND_3_B 0x58A
187#define WM8915_DSP2_RX_EQ_BAND_3_C 0x58B
188#define WM8915_DSP2_RX_EQ_BAND_3_PG 0x58C
189#define WM8915_DSP2_RX_EQ_BAND_4_A 0x58D
190#define WM8915_DSP2_RX_EQ_BAND_4_B 0x58E
191#define WM8915_DSP2_RX_EQ_BAND_4_C 0x58F
192#define WM8915_DSP2_RX_EQ_BAND_4_PG 0x590
193#define WM8915_DSP2_RX_EQ_BAND_5_A 0x591
194#define WM8915_DSP2_RX_EQ_BAND_5_B 0x592
195#define WM8915_DSP2_RX_EQ_BAND_5_PG 0x593
196#define WM8915_DAC1_MIXER_VOLUMES 0x600
197#define WM8915_DAC1_LEFT_MIXER_ROUTING 0x601
198#define WM8915_DAC1_RIGHT_MIXER_ROUTING 0x602
199#define WM8915_DAC2_MIXER_VOLUMES 0x603
200#define WM8915_DAC2_LEFT_MIXER_ROUTING 0x604
201#define WM8915_DAC2_RIGHT_MIXER_ROUTING 0x605
202#define WM8915_DSP1_TX_LEFT_MIXER_ROUTING 0x606
203#define WM8915_DSP1_TX_RIGHT_MIXER_ROUTING 0x607
204#define WM8915_DSP2_TX_LEFT_MIXER_ROUTING 0x608
205#define WM8915_DSP2_TX_RIGHT_MIXER_ROUTING 0x609
206#define WM8915_DSP_TX_MIXER_SELECT 0x60A
207#define WM8915_DAC_SOFTMUTE 0x610
208#define WM8915_OVERSAMPLING 0x620
209#define WM8915_SIDETONE 0x621
210#define WM8915_GPIO_1 0x700
211#define WM8915_GPIO_2 0x701
212#define WM8915_GPIO_3 0x702
213#define WM8915_GPIO_4 0x703
214#define WM8915_GPIO_5 0x704
215#define WM8915_PULL_CONTROL_1 0x720
216#define WM8915_PULL_CONTROL_2 0x721
217#define WM8915_INTERRUPT_STATUS_1 0x730
218#define WM8915_INTERRUPT_STATUS_2 0x731
219#define WM8915_INTERRUPT_RAW_STATUS_2 0x732
220#define WM8915_INTERRUPT_STATUS_1_MASK 0x738
221#define WM8915_INTERRUPT_STATUS_2_MASK 0x739
222#define WM8915_INTERRUPT_CONTROL 0x740
223#define WM8915_LEFT_PDM_SPEAKER 0x800
224#define WM8915_RIGHT_PDM_SPEAKER 0x801
225#define WM8915_PDM_SPEAKER_MUTE_SEQUENCE 0x802
226#define WM8915_PDM_SPEAKER_VOLUME 0x803
227#define WM8915_WRITE_SEQUENCER_0 0x3000
228#define WM8915_WRITE_SEQUENCER_1 0x3001
229#define WM8915_WRITE_SEQUENCER_2 0x3002
230#define WM8915_WRITE_SEQUENCER_3 0x3003
231#define WM8915_WRITE_SEQUENCER_4 0x3004
232#define WM8915_WRITE_SEQUENCER_5 0x3005
233#define WM8915_WRITE_SEQUENCER_6 0x3006
234#define WM8915_WRITE_SEQUENCER_7 0x3007
235#define WM8915_WRITE_SEQUENCER_8 0x3008
236#define WM8915_WRITE_SEQUENCER_9 0x3009
237#define WM8915_WRITE_SEQUENCER_10 0x300A
238#define WM8915_WRITE_SEQUENCER_11 0x300B
239#define WM8915_WRITE_SEQUENCER_12 0x300C
240#define WM8915_WRITE_SEQUENCER_13 0x300D
241#define WM8915_WRITE_SEQUENCER_14 0x300E
242#define WM8915_WRITE_SEQUENCER_15 0x300F
243#define WM8915_WRITE_SEQUENCER_16 0x3010
244#define WM8915_WRITE_SEQUENCER_17 0x3011
245#define WM8915_WRITE_SEQUENCER_18 0x3012
246#define WM8915_WRITE_SEQUENCER_19 0x3013
247#define WM8915_WRITE_SEQUENCER_20 0x3014
248#define WM8915_WRITE_SEQUENCER_21 0x3015
249#define WM8915_WRITE_SEQUENCER_22 0x3016
250#define WM8915_WRITE_SEQUENCER_23 0x3017
251#define WM8915_WRITE_SEQUENCER_24 0x3018
252#define WM8915_WRITE_SEQUENCER_25 0x3019
253#define WM8915_WRITE_SEQUENCER_26 0x301A
254#define WM8915_WRITE_SEQUENCER_27 0x301B
255#define WM8915_WRITE_SEQUENCER_28 0x301C
256#define WM8915_WRITE_SEQUENCER_29 0x301D
257#define WM8915_WRITE_SEQUENCER_30 0x301E
258#define WM8915_WRITE_SEQUENCER_31 0x301F
259#define WM8915_WRITE_SEQUENCER_32 0x3020
260#define WM8915_WRITE_SEQUENCER_33 0x3021
261#define WM8915_WRITE_SEQUENCER_34 0x3022
262#define WM8915_WRITE_SEQUENCER_35 0x3023
263#define WM8915_WRITE_SEQUENCER_36 0x3024
264#define WM8915_WRITE_SEQUENCER_37 0x3025
265#define WM8915_WRITE_SEQUENCER_38 0x3026
266#define WM8915_WRITE_SEQUENCER_39 0x3027
267#define WM8915_WRITE_SEQUENCER_40 0x3028
268#define WM8915_WRITE_SEQUENCER_41 0x3029
269#define WM8915_WRITE_SEQUENCER_42 0x302A
270#define WM8915_WRITE_SEQUENCER_43 0x302B
271#define WM8915_WRITE_SEQUENCER_44 0x302C
272#define WM8915_WRITE_SEQUENCER_45 0x302D
273#define WM8915_WRITE_SEQUENCER_46 0x302E
274#define WM8915_WRITE_SEQUENCER_47 0x302F
275#define WM8915_WRITE_SEQUENCER_48 0x3030
276#define WM8915_WRITE_SEQUENCER_49 0x3031
277#define WM8915_WRITE_SEQUENCER_50 0x3032
278#define WM8915_WRITE_SEQUENCER_51 0x3033
279#define WM8915_WRITE_SEQUENCER_52 0x3034
280#define WM8915_WRITE_SEQUENCER_53 0x3035
281#define WM8915_WRITE_SEQUENCER_54 0x3036
282#define WM8915_WRITE_SEQUENCER_55 0x3037
283#define WM8915_WRITE_SEQUENCER_56 0x3038
284#define WM8915_WRITE_SEQUENCER_57 0x3039
285#define WM8915_WRITE_SEQUENCER_58 0x303A
286#define WM8915_WRITE_SEQUENCER_59 0x303B
287#define WM8915_WRITE_SEQUENCER_60 0x303C
288#define WM8915_WRITE_SEQUENCER_61 0x303D
289#define WM8915_WRITE_SEQUENCER_62 0x303E
290#define WM8915_WRITE_SEQUENCER_63 0x303F
291#define WM8915_WRITE_SEQUENCER_64 0x3040
292#define WM8915_WRITE_SEQUENCER_65 0x3041
293#define WM8915_WRITE_SEQUENCER_66 0x3042
294#define WM8915_WRITE_SEQUENCER_67 0x3043
295#define WM8915_WRITE_SEQUENCER_68 0x3044
296#define WM8915_WRITE_SEQUENCER_69 0x3045
297#define WM8915_WRITE_SEQUENCER_70 0x3046
298#define WM8915_WRITE_SEQUENCER_71 0x3047
299#define WM8915_WRITE_SEQUENCER_72 0x3048
300#define WM8915_WRITE_SEQUENCER_73 0x3049
301#define WM8915_WRITE_SEQUENCER_74 0x304A
302#define WM8915_WRITE_SEQUENCER_75 0x304B
303#define WM8915_WRITE_SEQUENCER_76 0x304C
304#define WM8915_WRITE_SEQUENCER_77 0x304D
305#define WM8915_WRITE_SEQUENCER_78 0x304E
306#define WM8915_WRITE_SEQUENCER_79 0x304F
307#define WM8915_WRITE_SEQUENCER_80 0x3050
308#define WM8915_WRITE_SEQUENCER_81 0x3051
309#define WM8915_WRITE_SEQUENCER_82 0x3052
310#define WM8915_WRITE_SEQUENCER_83 0x3053
311#define WM8915_WRITE_SEQUENCER_84 0x3054
312#define WM8915_WRITE_SEQUENCER_85 0x3055
313#define WM8915_WRITE_SEQUENCER_86 0x3056
314#define WM8915_WRITE_SEQUENCER_87 0x3057
315#define WM8915_WRITE_SEQUENCER_88 0x3058
316#define WM8915_WRITE_SEQUENCER_89 0x3059
317#define WM8915_WRITE_SEQUENCER_90 0x305A
318#define WM8915_WRITE_SEQUENCER_91 0x305B
319#define WM8915_WRITE_SEQUENCER_92 0x305C
320#define WM8915_WRITE_SEQUENCER_93 0x305D
321#define WM8915_WRITE_SEQUENCER_94 0x305E
322#define WM8915_WRITE_SEQUENCER_95 0x305F
323#define WM8915_WRITE_SEQUENCER_96 0x3060
324#define WM8915_WRITE_SEQUENCER_97 0x3061
325#define WM8915_WRITE_SEQUENCER_98 0x3062
326#define WM8915_WRITE_SEQUENCER_99 0x3063
327#define WM8915_WRITE_SEQUENCER_100 0x3064
328#define WM8915_WRITE_SEQUENCER_101 0x3065
329#define WM8915_WRITE_SEQUENCER_102 0x3066
330#define WM8915_WRITE_SEQUENCER_103 0x3067
331#define WM8915_WRITE_SEQUENCER_104 0x3068
332#define WM8915_WRITE_SEQUENCER_105 0x3069
333#define WM8915_WRITE_SEQUENCER_106 0x306A
334#define WM8915_WRITE_SEQUENCER_107 0x306B
335#define WM8915_WRITE_SEQUENCER_108 0x306C
336#define WM8915_WRITE_SEQUENCER_109 0x306D
337#define WM8915_WRITE_SEQUENCER_110 0x306E
338#define WM8915_WRITE_SEQUENCER_111 0x306F
339#define WM8915_WRITE_SEQUENCER_112 0x3070
340#define WM8915_WRITE_SEQUENCER_113 0x3071
341#define WM8915_WRITE_SEQUENCER_114 0x3072
342#define WM8915_WRITE_SEQUENCER_115 0x3073
343#define WM8915_WRITE_SEQUENCER_116 0x3074
344#define WM8915_WRITE_SEQUENCER_117 0x3075
345#define WM8915_WRITE_SEQUENCER_118 0x3076
346#define WM8915_WRITE_SEQUENCER_119 0x3077
347#define WM8915_WRITE_SEQUENCER_120 0x3078
348#define WM8915_WRITE_SEQUENCER_121 0x3079
349#define WM8915_WRITE_SEQUENCER_122 0x307A
350#define WM8915_WRITE_SEQUENCER_123 0x307B
351#define WM8915_WRITE_SEQUENCER_124 0x307C
352#define WM8915_WRITE_SEQUENCER_125 0x307D
353#define WM8915_WRITE_SEQUENCER_126 0x307E
354#define WM8915_WRITE_SEQUENCER_127 0x307F
355#define WM8915_WRITE_SEQUENCER_128 0x3080
356#define WM8915_WRITE_SEQUENCER_129 0x3081
357#define WM8915_WRITE_SEQUENCER_130 0x3082
358#define WM8915_WRITE_SEQUENCER_131 0x3083
359#define WM8915_WRITE_SEQUENCER_132 0x3084
360#define WM8915_WRITE_SEQUENCER_133 0x3085
361#define WM8915_WRITE_SEQUENCER_134 0x3086
362#define WM8915_WRITE_SEQUENCER_135 0x3087
363#define WM8915_WRITE_SEQUENCER_136 0x3088
364#define WM8915_WRITE_SEQUENCER_137 0x3089
365#define WM8915_WRITE_SEQUENCER_138 0x308A
366#define WM8915_WRITE_SEQUENCER_139 0x308B
367#define WM8915_WRITE_SEQUENCER_140 0x308C
368#define WM8915_WRITE_SEQUENCER_141 0x308D
369#define WM8915_WRITE_SEQUENCER_142 0x308E
370#define WM8915_WRITE_SEQUENCER_143 0x308F
371#define WM8915_WRITE_SEQUENCER_144 0x3090
372#define WM8915_WRITE_SEQUENCER_145 0x3091
373#define WM8915_WRITE_SEQUENCER_146 0x3092
374#define WM8915_WRITE_SEQUENCER_147 0x3093
375#define WM8915_WRITE_SEQUENCER_148 0x3094
376#define WM8915_WRITE_SEQUENCER_149 0x3095
377#define WM8915_WRITE_SEQUENCER_150 0x3096
378#define WM8915_WRITE_SEQUENCER_151 0x3097
379#define WM8915_WRITE_SEQUENCER_152 0x3098
380#define WM8915_WRITE_SEQUENCER_153 0x3099
381#define WM8915_WRITE_SEQUENCER_154 0x309A
382#define WM8915_WRITE_SEQUENCER_155 0x309B
383#define WM8915_WRITE_SEQUENCER_156 0x309C
384#define WM8915_WRITE_SEQUENCER_157 0x309D
385#define WM8915_WRITE_SEQUENCER_158 0x309E
386#define WM8915_WRITE_SEQUENCER_159 0x309F
387#define WM8915_WRITE_SEQUENCER_160 0x30A0
388#define WM8915_WRITE_SEQUENCER_161 0x30A1
389#define WM8915_WRITE_SEQUENCER_162 0x30A2
390#define WM8915_WRITE_SEQUENCER_163 0x30A3
391#define WM8915_WRITE_SEQUENCER_164 0x30A4
392#define WM8915_WRITE_SEQUENCER_165 0x30A5
393#define WM8915_WRITE_SEQUENCER_166 0x30A6
394#define WM8915_WRITE_SEQUENCER_167 0x30A7
395#define WM8915_WRITE_SEQUENCER_168 0x30A8
396#define WM8915_WRITE_SEQUENCER_169 0x30A9
397#define WM8915_WRITE_SEQUENCER_170 0x30AA
398#define WM8915_WRITE_SEQUENCER_171 0x30AB
399#define WM8915_WRITE_SEQUENCER_172 0x30AC
400#define WM8915_WRITE_SEQUENCER_173 0x30AD
401#define WM8915_WRITE_SEQUENCER_174 0x30AE
402#define WM8915_WRITE_SEQUENCER_175 0x30AF
403#define WM8915_WRITE_SEQUENCER_176 0x30B0
404#define WM8915_WRITE_SEQUENCER_177 0x30B1
405#define WM8915_WRITE_SEQUENCER_178 0x30B2
406#define WM8915_WRITE_SEQUENCER_179 0x30B3
407#define WM8915_WRITE_SEQUENCER_180 0x30B4
408#define WM8915_WRITE_SEQUENCER_181 0x30B5
409#define WM8915_WRITE_SEQUENCER_182 0x30B6
410#define WM8915_WRITE_SEQUENCER_183 0x30B7
411#define WM8915_WRITE_SEQUENCER_184 0x30B8
412#define WM8915_WRITE_SEQUENCER_185 0x30B9
413#define WM8915_WRITE_SEQUENCER_186 0x30BA
414#define WM8915_WRITE_SEQUENCER_187 0x30BB
415#define WM8915_WRITE_SEQUENCER_188 0x30BC
416#define WM8915_WRITE_SEQUENCER_189 0x30BD
417#define WM8915_WRITE_SEQUENCER_190 0x30BE
418#define WM8915_WRITE_SEQUENCER_191 0x30BF
419#define WM8915_WRITE_SEQUENCER_192 0x30C0
420#define WM8915_WRITE_SEQUENCER_193 0x30C1
421#define WM8915_WRITE_SEQUENCER_194 0x30C2
422#define WM8915_WRITE_SEQUENCER_195 0x30C3
423#define WM8915_WRITE_SEQUENCER_196 0x30C4
424#define WM8915_WRITE_SEQUENCER_197 0x30C5
425#define WM8915_WRITE_SEQUENCER_198 0x30C6
426#define WM8915_WRITE_SEQUENCER_199 0x30C7
427#define WM8915_WRITE_SEQUENCER_200 0x30C8
428#define WM8915_WRITE_SEQUENCER_201 0x30C9
429#define WM8915_WRITE_SEQUENCER_202 0x30CA
430#define WM8915_WRITE_SEQUENCER_203 0x30CB
431#define WM8915_WRITE_SEQUENCER_204 0x30CC
432#define WM8915_WRITE_SEQUENCER_205 0x30CD
433#define WM8915_WRITE_SEQUENCER_206 0x30CE
434#define WM8915_WRITE_SEQUENCER_207 0x30CF
435#define WM8915_WRITE_SEQUENCER_208 0x30D0
436#define WM8915_WRITE_SEQUENCER_209 0x30D1
437#define WM8915_WRITE_SEQUENCER_210 0x30D2
438#define WM8915_WRITE_SEQUENCER_211 0x30D3
439#define WM8915_WRITE_SEQUENCER_212 0x30D4
440#define WM8915_WRITE_SEQUENCER_213 0x30D5
441#define WM8915_WRITE_SEQUENCER_214 0x30D6
442#define WM8915_WRITE_SEQUENCER_215 0x30D7
443#define WM8915_WRITE_SEQUENCER_216 0x30D8
444#define WM8915_WRITE_SEQUENCER_217 0x30D9
445#define WM8915_WRITE_SEQUENCER_218 0x30DA
446#define WM8915_WRITE_SEQUENCER_219 0x30DB
447#define WM8915_WRITE_SEQUENCER_220 0x30DC
448#define WM8915_WRITE_SEQUENCER_221 0x30DD
449#define WM8915_WRITE_SEQUENCER_222 0x30DE
450#define WM8915_WRITE_SEQUENCER_223 0x30DF
451#define WM8915_WRITE_SEQUENCER_224 0x30E0
452#define WM8915_WRITE_SEQUENCER_225 0x30E1
453#define WM8915_WRITE_SEQUENCER_226 0x30E2
454#define WM8915_WRITE_SEQUENCER_227 0x30E3
455#define WM8915_WRITE_SEQUENCER_228 0x30E4
456#define WM8915_WRITE_SEQUENCER_229 0x30E5
457#define WM8915_WRITE_SEQUENCER_230 0x30E6
458#define WM8915_WRITE_SEQUENCER_231 0x30E7
459#define WM8915_WRITE_SEQUENCER_232 0x30E8
460#define WM8915_WRITE_SEQUENCER_233 0x30E9
461#define WM8915_WRITE_SEQUENCER_234 0x30EA
462#define WM8915_WRITE_SEQUENCER_235 0x30EB
463#define WM8915_WRITE_SEQUENCER_236 0x30EC
464#define WM8915_WRITE_SEQUENCER_237 0x30ED
465#define WM8915_WRITE_SEQUENCER_238 0x30EE
466#define WM8915_WRITE_SEQUENCER_239 0x30EF
467#define WM8915_WRITE_SEQUENCER_240 0x30F0
468#define WM8915_WRITE_SEQUENCER_241 0x30F1
469#define WM8915_WRITE_SEQUENCER_242 0x30F2
470#define WM8915_WRITE_SEQUENCER_243 0x30F3
471#define WM8915_WRITE_SEQUENCER_244 0x30F4
472#define WM8915_WRITE_SEQUENCER_245 0x30F5
473#define WM8915_WRITE_SEQUENCER_246 0x30F6
474#define WM8915_WRITE_SEQUENCER_247 0x30F7
475#define WM8915_WRITE_SEQUENCER_248 0x30F8
476#define WM8915_WRITE_SEQUENCER_249 0x30F9
477#define WM8915_WRITE_SEQUENCER_250 0x30FA
478#define WM8915_WRITE_SEQUENCER_251 0x30FB
479#define WM8915_WRITE_SEQUENCER_252 0x30FC
480#define WM8915_WRITE_SEQUENCER_253 0x30FD
481#define WM8915_WRITE_SEQUENCER_254 0x30FE
482#define WM8915_WRITE_SEQUENCER_255 0x30FF
483#define WM8915_WRITE_SEQUENCER_256 0x3100
484#define WM8915_WRITE_SEQUENCER_257 0x3101
485#define WM8915_WRITE_SEQUENCER_258 0x3102
486#define WM8915_WRITE_SEQUENCER_259 0x3103
487#define WM8915_WRITE_SEQUENCER_260 0x3104
488#define WM8915_WRITE_SEQUENCER_261 0x3105
489#define WM8915_WRITE_SEQUENCER_262 0x3106
490#define WM8915_WRITE_SEQUENCER_263 0x3107
491#define WM8915_WRITE_SEQUENCER_264 0x3108
492#define WM8915_WRITE_SEQUENCER_265 0x3109
493#define WM8915_WRITE_SEQUENCER_266 0x310A
494#define WM8915_WRITE_SEQUENCER_267 0x310B
495#define WM8915_WRITE_SEQUENCER_268 0x310C
496#define WM8915_WRITE_SEQUENCER_269 0x310D
497#define WM8915_WRITE_SEQUENCER_270 0x310E
498#define WM8915_WRITE_SEQUENCER_271 0x310F
499#define WM8915_WRITE_SEQUENCER_272 0x3110
500#define WM8915_WRITE_SEQUENCER_273 0x3111
501#define WM8915_WRITE_SEQUENCER_274 0x3112
502#define WM8915_WRITE_SEQUENCER_275 0x3113
503#define WM8915_WRITE_SEQUENCER_276 0x3114
504#define WM8915_WRITE_SEQUENCER_277 0x3115
505#define WM8915_WRITE_SEQUENCER_278 0x3116
506#define WM8915_WRITE_SEQUENCER_279 0x3117
507#define WM8915_WRITE_SEQUENCER_280 0x3118
508#define WM8915_WRITE_SEQUENCER_281 0x3119
509#define WM8915_WRITE_SEQUENCER_282 0x311A
510#define WM8915_WRITE_SEQUENCER_283 0x311B
511#define WM8915_WRITE_SEQUENCER_284 0x311C
512#define WM8915_WRITE_SEQUENCER_285 0x311D
513#define WM8915_WRITE_SEQUENCER_286 0x311E
514#define WM8915_WRITE_SEQUENCER_287 0x311F
515#define WM8915_WRITE_SEQUENCER_288 0x3120
516#define WM8915_WRITE_SEQUENCER_289 0x3121
517#define WM8915_WRITE_SEQUENCER_290 0x3122
518#define WM8915_WRITE_SEQUENCER_291 0x3123
519#define WM8915_WRITE_SEQUENCER_292 0x3124
520#define WM8915_WRITE_SEQUENCER_293 0x3125
521#define WM8915_WRITE_SEQUENCER_294 0x3126
522#define WM8915_WRITE_SEQUENCER_295 0x3127
523#define WM8915_WRITE_SEQUENCER_296 0x3128
524#define WM8915_WRITE_SEQUENCER_297 0x3129
525#define WM8915_WRITE_SEQUENCER_298 0x312A
526#define WM8915_WRITE_SEQUENCER_299 0x312B
527#define WM8915_WRITE_SEQUENCER_300 0x312C
528#define WM8915_WRITE_SEQUENCER_301 0x312D
529#define WM8915_WRITE_SEQUENCER_302 0x312E
530#define WM8915_WRITE_SEQUENCER_303 0x312F
531#define WM8915_WRITE_SEQUENCER_304 0x3130
532#define WM8915_WRITE_SEQUENCER_305 0x3131
533#define WM8915_WRITE_SEQUENCER_306 0x3132
534#define WM8915_WRITE_SEQUENCER_307 0x3133
535#define WM8915_WRITE_SEQUENCER_308 0x3134
536#define WM8915_WRITE_SEQUENCER_309 0x3135
537#define WM8915_WRITE_SEQUENCER_310 0x3136
538#define WM8915_WRITE_SEQUENCER_311 0x3137
539#define WM8915_WRITE_SEQUENCER_312 0x3138
540#define WM8915_WRITE_SEQUENCER_313 0x3139
541#define WM8915_WRITE_SEQUENCER_314 0x313A
542#define WM8915_WRITE_SEQUENCER_315 0x313B
543#define WM8915_WRITE_SEQUENCER_316 0x313C
544#define WM8915_WRITE_SEQUENCER_317 0x313D
545#define WM8915_WRITE_SEQUENCER_318 0x313E
546#define WM8915_WRITE_SEQUENCER_319 0x313F
547#define WM8915_WRITE_SEQUENCER_320 0x3140
548#define WM8915_WRITE_SEQUENCER_321 0x3141
549#define WM8915_WRITE_SEQUENCER_322 0x3142
550#define WM8915_WRITE_SEQUENCER_323 0x3143
551#define WM8915_WRITE_SEQUENCER_324 0x3144
552#define WM8915_WRITE_SEQUENCER_325 0x3145
553#define WM8915_WRITE_SEQUENCER_326 0x3146
554#define WM8915_WRITE_SEQUENCER_327 0x3147
555#define WM8915_WRITE_SEQUENCER_328 0x3148
556#define WM8915_WRITE_SEQUENCER_329 0x3149
557#define WM8915_WRITE_SEQUENCER_330 0x314A
558#define WM8915_WRITE_SEQUENCER_331 0x314B
559#define WM8915_WRITE_SEQUENCER_332 0x314C
560#define WM8915_WRITE_SEQUENCER_333 0x314D
561#define WM8915_WRITE_SEQUENCER_334 0x314E
562#define WM8915_WRITE_SEQUENCER_335 0x314F
563#define WM8915_WRITE_SEQUENCER_336 0x3150
564#define WM8915_WRITE_SEQUENCER_337 0x3151
565#define WM8915_WRITE_SEQUENCER_338 0x3152
566#define WM8915_WRITE_SEQUENCER_339 0x3153
567#define WM8915_WRITE_SEQUENCER_340 0x3154
568#define WM8915_WRITE_SEQUENCER_341 0x3155
569#define WM8915_WRITE_SEQUENCER_342 0x3156
570#define WM8915_WRITE_SEQUENCER_343 0x3157
571#define WM8915_WRITE_SEQUENCER_344 0x3158
572#define WM8915_WRITE_SEQUENCER_345 0x3159
573#define WM8915_WRITE_SEQUENCER_346 0x315A
574#define WM8915_WRITE_SEQUENCER_347 0x315B
575#define WM8915_WRITE_SEQUENCER_348 0x315C
576#define WM8915_WRITE_SEQUENCER_349 0x315D
577#define WM8915_WRITE_SEQUENCER_350 0x315E
578#define WM8915_WRITE_SEQUENCER_351 0x315F
579#define WM8915_WRITE_SEQUENCER_352 0x3160
580#define WM8915_WRITE_SEQUENCER_353 0x3161
581#define WM8915_WRITE_SEQUENCER_354 0x3162
582#define WM8915_WRITE_SEQUENCER_355 0x3163
583#define WM8915_WRITE_SEQUENCER_356 0x3164
584#define WM8915_WRITE_SEQUENCER_357 0x3165
585#define WM8915_WRITE_SEQUENCER_358 0x3166
586#define WM8915_WRITE_SEQUENCER_359 0x3167
587#define WM8915_WRITE_SEQUENCER_360 0x3168
588#define WM8915_WRITE_SEQUENCER_361 0x3169
589#define WM8915_WRITE_SEQUENCER_362 0x316A
590#define WM8915_WRITE_SEQUENCER_363 0x316B
591#define WM8915_WRITE_SEQUENCER_364 0x316C
592#define WM8915_WRITE_SEQUENCER_365 0x316D
593#define WM8915_WRITE_SEQUENCER_366 0x316E
594#define WM8915_WRITE_SEQUENCER_367 0x316F
595#define WM8915_WRITE_SEQUENCER_368 0x3170
596#define WM8915_WRITE_SEQUENCER_369 0x3171
597#define WM8915_WRITE_SEQUENCER_370 0x3172
598#define WM8915_WRITE_SEQUENCER_371 0x3173
599#define WM8915_WRITE_SEQUENCER_372 0x3174
600#define WM8915_WRITE_SEQUENCER_373 0x3175
601#define WM8915_WRITE_SEQUENCER_374 0x3176
602#define WM8915_WRITE_SEQUENCER_375 0x3177
603#define WM8915_WRITE_SEQUENCER_376 0x3178
604#define WM8915_WRITE_SEQUENCER_377 0x3179
605#define WM8915_WRITE_SEQUENCER_378 0x317A
606#define WM8915_WRITE_SEQUENCER_379 0x317B
607#define WM8915_WRITE_SEQUENCER_380 0x317C
608#define WM8915_WRITE_SEQUENCER_381 0x317D
609#define WM8915_WRITE_SEQUENCER_382 0x317E
610#define WM8915_WRITE_SEQUENCER_383 0x317F
611#define WM8915_WRITE_SEQUENCER_384 0x3180
612#define WM8915_WRITE_SEQUENCER_385 0x3181
613#define WM8915_WRITE_SEQUENCER_386 0x3182
614#define WM8915_WRITE_SEQUENCER_387 0x3183
615#define WM8915_WRITE_SEQUENCER_388 0x3184
616#define WM8915_WRITE_SEQUENCER_389 0x3185
617#define WM8915_WRITE_SEQUENCER_390 0x3186
618#define WM8915_WRITE_SEQUENCER_391 0x3187
619#define WM8915_WRITE_SEQUENCER_392 0x3188
620#define WM8915_WRITE_SEQUENCER_393 0x3189
621#define WM8915_WRITE_SEQUENCER_394 0x318A
622#define WM8915_WRITE_SEQUENCER_395 0x318B
623#define WM8915_WRITE_SEQUENCER_396 0x318C
624#define WM8915_WRITE_SEQUENCER_397 0x318D
625#define WM8915_WRITE_SEQUENCER_398 0x318E
626#define WM8915_WRITE_SEQUENCER_399 0x318F
627#define WM8915_WRITE_SEQUENCER_400 0x3190
628#define WM8915_WRITE_SEQUENCER_401 0x3191
629#define WM8915_WRITE_SEQUENCER_402 0x3192
630#define WM8915_WRITE_SEQUENCER_403 0x3193
631#define WM8915_WRITE_SEQUENCER_404 0x3194
632#define WM8915_WRITE_SEQUENCER_405 0x3195
633#define WM8915_WRITE_SEQUENCER_406 0x3196
634#define WM8915_WRITE_SEQUENCER_407 0x3197
635#define WM8915_WRITE_SEQUENCER_408 0x3198
636#define WM8915_WRITE_SEQUENCER_409 0x3199
637#define WM8915_WRITE_SEQUENCER_410 0x319A
638#define WM8915_WRITE_SEQUENCER_411 0x319B
639#define WM8915_WRITE_SEQUENCER_412 0x319C
640#define WM8915_WRITE_SEQUENCER_413 0x319D
641#define WM8915_WRITE_SEQUENCER_414 0x319E
642#define WM8915_WRITE_SEQUENCER_415 0x319F
643#define WM8915_WRITE_SEQUENCER_416 0x31A0
644#define WM8915_WRITE_SEQUENCER_417 0x31A1
645#define WM8915_WRITE_SEQUENCER_418 0x31A2
646#define WM8915_WRITE_SEQUENCER_419 0x31A3
647#define WM8915_WRITE_SEQUENCER_420 0x31A4
648#define WM8915_WRITE_SEQUENCER_421 0x31A5
649#define WM8915_WRITE_SEQUENCER_422 0x31A6
650#define WM8915_WRITE_SEQUENCER_423 0x31A7
651#define WM8915_WRITE_SEQUENCER_424 0x31A8
652#define WM8915_WRITE_SEQUENCER_425 0x31A9
653#define WM8915_WRITE_SEQUENCER_426 0x31AA
654#define WM8915_WRITE_SEQUENCER_427 0x31AB
655#define WM8915_WRITE_SEQUENCER_428 0x31AC
656#define WM8915_WRITE_SEQUENCER_429 0x31AD
657#define WM8915_WRITE_SEQUENCER_430 0x31AE
658#define WM8915_WRITE_SEQUENCER_431 0x31AF
659#define WM8915_WRITE_SEQUENCER_432 0x31B0
660#define WM8915_WRITE_SEQUENCER_433 0x31B1
661#define WM8915_WRITE_SEQUENCER_434 0x31B2
662#define WM8915_WRITE_SEQUENCER_435 0x31B3
663#define WM8915_WRITE_SEQUENCER_436 0x31B4
664#define WM8915_WRITE_SEQUENCER_437 0x31B5
665#define WM8915_WRITE_SEQUENCER_438 0x31B6
666#define WM8915_WRITE_SEQUENCER_439 0x31B7
667#define WM8915_WRITE_SEQUENCER_440 0x31B8
668#define WM8915_WRITE_SEQUENCER_441 0x31B9
669#define WM8915_WRITE_SEQUENCER_442 0x31BA
670#define WM8915_WRITE_SEQUENCER_443 0x31BB
671#define WM8915_WRITE_SEQUENCER_444 0x31BC
672#define WM8915_WRITE_SEQUENCER_445 0x31BD
673#define WM8915_WRITE_SEQUENCER_446 0x31BE
674#define WM8915_WRITE_SEQUENCER_447 0x31BF
675#define WM8915_WRITE_SEQUENCER_448 0x31C0
676#define WM8915_WRITE_SEQUENCER_449 0x31C1
677#define WM8915_WRITE_SEQUENCER_450 0x31C2
678#define WM8915_WRITE_SEQUENCER_451 0x31C3
679#define WM8915_WRITE_SEQUENCER_452 0x31C4
680#define WM8915_WRITE_SEQUENCER_453 0x31C5
681#define WM8915_WRITE_SEQUENCER_454 0x31C6
682#define WM8915_WRITE_SEQUENCER_455 0x31C7
683#define WM8915_WRITE_SEQUENCER_456 0x31C8
684#define WM8915_WRITE_SEQUENCER_457 0x31C9
685#define WM8915_WRITE_SEQUENCER_458 0x31CA
686#define WM8915_WRITE_SEQUENCER_459 0x31CB
687#define WM8915_WRITE_SEQUENCER_460 0x31CC
688#define WM8915_WRITE_SEQUENCER_461 0x31CD
689#define WM8915_WRITE_SEQUENCER_462 0x31CE
690#define WM8915_WRITE_SEQUENCER_463 0x31CF
691#define WM8915_WRITE_SEQUENCER_464 0x31D0
692#define WM8915_WRITE_SEQUENCER_465 0x31D1
693#define WM8915_WRITE_SEQUENCER_466 0x31D2
694#define WM8915_WRITE_SEQUENCER_467 0x31D3
695#define WM8915_WRITE_SEQUENCER_468 0x31D4
696#define WM8915_WRITE_SEQUENCER_469 0x31D5
697#define WM8915_WRITE_SEQUENCER_470 0x31D6
698#define WM8915_WRITE_SEQUENCER_471 0x31D7
699#define WM8915_WRITE_SEQUENCER_472 0x31D8
700#define WM8915_WRITE_SEQUENCER_473 0x31D9
701#define WM8915_WRITE_SEQUENCER_474 0x31DA
702#define WM8915_WRITE_SEQUENCER_475 0x31DB
703#define WM8915_WRITE_SEQUENCER_476 0x31DC
704#define WM8915_WRITE_SEQUENCER_477 0x31DD
705#define WM8915_WRITE_SEQUENCER_478 0x31DE
706#define WM8915_WRITE_SEQUENCER_479 0x31DF
707#define WM8915_WRITE_SEQUENCER_480 0x31E0
708#define WM8915_WRITE_SEQUENCER_481 0x31E1
709#define WM8915_WRITE_SEQUENCER_482 0x31E2
710#define WM8915_WRITE_SEQUENCER_483 0x31E3
711#define WM8915_WRITE_SEQUENCER_484 0x31E4
712#define WM8915_WRITE_SEQUENCER_485 0x31E5
713#define WM8915_WRITE_SEQUENCER_486 0x31E6
714#define WM8915_WRITE_SEQUENCER_487 0x31E7
715#define WM8915_WRITE_SEQUENCER_488 0x31E8
716#define WM8915_WRITE_SEQUENCER_489 0x31E9
717#define WM8915_WRITE_SEQUENCER_490 0x31EA
718#define WM8915_WRITE_SEQUENCER_491 0x31EB
719#define WM8915_WRITE_SEQUENCER_492 0x31EC
720#define WM8915_WRITE_SEQUENCER_493 0x31ED
721#define WM8915_WRITE_SEQUENCER_494 0x31EE
722#define WM8915_WRITE_SEQUENCER_495 0x31EF
723#define WM8915_WRITE_SEQUENCER_496 0x31F0
724#define WM8915_WRITE_SEQUENCER_497 0x31F1
725#define WM8915_WRITE_SEQUENCER_498 0x31F2
726#define WM8915_WRITE_SEQUENCER_499 0x31F3
727#define WM8915_WRITE_SEQUENCER_500 0x31F4
728#define WM8915_WRITE_SEQUENCER_501 0x31F5
729#define WM8915_WRITE_SEQUENCER_502 0x31F6
730#define WM8915_WRITE_SEQUENCER_503 0x31F7
731#define WM8915_WRITE_SEQUENCER_504 0x31F8
732#define WM8915_WRITE_SEQUENCER_505 0x31F9
733#define WM8915_WRITE_SEQUENCER_506 0x31FA
734#define WM8915_WRITE_SEQUENCER_507 0x31FB
735#define WM8915_WRITE_SEQUENCER_508 0x31FC
736#define WM8915_WRITE_SEQUENCER_509 0x31FD
737#define WM8915_WRITE_SEQUENCER_510 0x31FE
738#define WM8915_WRITE_SEQUENCER_511 0x31FF
739
740#define WM8915_REGISTER_COUNT 706
741#define WM8915_MAX_REGISTER 0x31FF
742
743/*
744 * Field Definitions.
745 */
746
747/*
748 * R0 (0x00) - Software Reset
749 */
750#define WM8915_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */
751#define WM8915_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */
752#define WM8915_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */
753
754/*
755 * R1 (0x01) - Power Management (1)
756 */
757#define WM8915_MICB2_ENA 0x0200 /* MICB2_ENA */
758#define WM8915_MICB2_ENA_MASK 0x0200 /* MICB2_ENA */
759#define WM8915_MICB2_ENA_SHIFT 9 /* MICB2_ENA */
760#define WM8915_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
761#define WM8915_MICB1_ENA 0x0100 /* MICB1_ENA */
762#define WM8915_MICB1_ENA_MASK 0x0100 /* MICB1_ENA */
763#define WM8915_MICB1_ENA_SHIFT 8 /* MICB1_ENA */
764#define WM8915_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
765#define WM8915_HPOUT2L_ENA 0x0080 /* HPOUT2L_ENA */
766#define WM8915_HPOUT2L_ENA_MASK 0x0080 /* HPOUT2L_ENA */
767#define WM8915_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */
768#define WM8915_HPOUT2L_ENA_WIDTH 1 /* HPOUT2L_ENA */
769#define WM8915_HPOUT2R_ENA 0x0040 /* HPOUT2R_ENA */
770#define WM8915_HPOUT2R_ENA_MASK 0x0040 /* HPOUT2R_ENA */
771#define WM8915_HPOUT2R_ENA_SHIFT 6 /* HPOUT2R_ENA */
772#define WM8915_HPOUT2R_ENA_WIDTH 1 /* HPOUT2R_ENA */
773#define WM8915_HPOUT1L_ENA 0x0020 /* HPOUT1L_ENA */
774#define WM8915_HPOUT1L_ENA_MASK 0x0020 /* HPOUT1L_ENA */
775#define WM8915_HPOUT1L_ENA_SHIFT 5 /* HPOUT1L_ENA */
776#define WM8915_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */
777#define WM8915_HPOUT1R_ENA 0x0010 /* HPOUT1R_ENA */
778#define WM8915_HPOUT1R_ENA_MASK 0x0010 /* HPOUT1R_ENA */
779#define WM8915_HPOUT1R_ENA_SHIFT 4 /* HPOUT1R_ENA */
780#define WM8915_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */
781#define WM8915_BG_ENA 0x0001 /* BG_ENA */
782#define WM8915_BG_ENA_MASK 0x0001 /* BG_ENA */
783#define WM8915_BG_ENA_SHIFT 0 /* BG_ENA */
784#define WM8915_BG_ENA_WIDTH 1 /* BG_ENA */
785
786/*
787 * R2 (0x02) - Power Management (2)
788 */
789#define WM8915_OPCLK_ENA 0x0800 /* OPCLK_ENA */
790#define WM8915_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */
791#define WM8915_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */
792#define WM8915_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
793#define WM8915_INL_ENA 0x0020 /* INL_ENA */
794#define WM8915_INL_ENA_MASK 0x0020 /* INL_ENA */
795#define WM8915_INL_ENA_SHIFT 5 /* INL_ENA */
796#define WM8915_INL_ENA_WIDTH 1 /* INL_ENA */
797#define WM8915_INR_ENA 0x0010 /* INR_ENA */
798#define WM8915_INR_ENA_MASK 0x0010 /* INR_ENA */
799#define WM8915_INR_ENA_SHIFT 4 /* INR_ENA */
800#define WM8915_INR_ENA_WIDTH 1 /* INR_ENA */
801#define WM8915_LDO2_ENA 0x0002 /* LDO2_ENA */
802#define WM8915_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */
803#define WM8915_LDO2_ENA_SHIFT 1 /* LDO2_ENA */
804#define WM8915_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
805
806/*
807 * R3 (0x03) - Power Management (3)
808 */
809#define WM8915_DSP2RXL_ENA 0x0800 /* DSP2RXL_ENA */
810#define WM8915_DSP2RXL_ENA_MASK 0x0800 /* DSP2RXL_ENA */
811#define WM8915_DSP2RXL_ENA_SHIFT 11 /* DSP2RXL_ENA */
812#define WM8915_DSP2RXL_ENA_WIDTH 1 /* DSP2RXL_ENA */
813#define WM8915_DSP2RXR_ENA 0x0400 /* DSP2RXR_ENA */
814#define WM8915_DSP2RXR_ENA_MASK 0x0400 /* DSP2RXR_ENA */
815#define WM8915_DSP2RXR_ENA_SHIFT 10 /* DSP2RXR_ENA */
816#define WM8915_DSP2RXR_ENA_WIDTH 1 /* DSP2RXR_ENA */
817#define WM8915_DSP1RXL_ENA 0x0200 /* DSP1RXL_ENA */
818#define WM8915_DSP1RXL_ENA_MASK 0x0200 /* DSP1RXL_ENA */
819#define WM8915_DSP1RXL_ENA_SHIFT 9 /* DSP1RXL_ENA */
820#define WM8915_DSP1RXL_ENA_WIDTH 1 /* DSP1RXL_ENA */
821#define WM8915_DSP1RXR_ENA 0x0100 /* DSP1RXR_ENA */
822#define WM8915_DSP1RXR_ENA_MASK 0x0100 /* DSP1RXR_ENA */
823#define WM8915_DSP1RXR_ENA_SHIFT 8 /* DSP1RXR_ENA */
824#define WM8915_DSP1RXR_ENA_WIDTH 1 /* DSP1RXR_ENA */
825#define WM8915_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */
826#define WM8915_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */
827#define WM8915_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */
828#define WM8915_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */
829#define WM8915_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */
830#define WM8915_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */
831#define WM8915_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */
832#define WM8915_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */
833#define WM8915_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */
834#define WM8915_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */
835#define WM8915_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */
836#define WM8915_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */
837#define WM8915_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */
838#define WM8915_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */
839#define WM8915_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */
840#define WM8915_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */
841#define WM8915_ADCL_ENA 0x0002 /* ADCL_ENA */
842#define WM8915_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */
843#define WM8915_ADCL_ENA_SHIFT 1 /* ADCL_ENA */
844#define WM8915_ADCL_ENA_WIDTH 1 /* ADCL_ENA */
845#define WM8915_ADCR_ENA 0x0001 /* ADCR_ENA */
846#define WM8915_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
847#define WM8915_ADCR_ENA_SHIFT 0 /* ADCR_ENA */
848#define WM8915_ADCR_ENA_WIDTH 1 /* ADCR_ENA */
849
850/*
851 * R4 (0x04) - Power Management (4)
852 */
853#define WM8915_AIF2RX_CHAN1_ENA 0x0200 /* AIF2RX_CHAN1_ENA */
854#define WM8915_AIF2RX_CHAN1_ENA_MASK 0x0200 /* AIF2RX_CHAN1_ENA */
855#define WM8915_AIF2RX_CHAN1_ENA_SHIFT 9 /* AIF2RX_CHAN1_ENA */
856#define WM8915_AIF2RX_CHAN1_ENA_WIDTH 1 /* AIF2RX_CHAN1_ENA */
857#define WM8915_AIF2RX_CHAN0_ENA 0x0100 /* AIF2RX_CHAN0_ENA */
858#define WM8915_AIF2RX_CHAN0_ENA_MASK 0x0100 /* AIF2RX_CHAN0_ENA */
859#define WM8915_AIF2RX_CHAN0_ENA_SHIFT 8 /* AIF2RX_CHAN0_ENA */
860#define WM8915_AIF2RX_CHAN0_ENA_WIDTH 1 /* AIF2RX_CHAN0_ENA */
861#define WM8915_AIF1RX_CHAN5_ENA 0x0020 /* AIF1RX_CHAN5_ENA */
862#define WM8915_AIF1RX_CHAN5_ENA_MASK 0x0020 /* AIF1RX_CHAN5_ENA */
863#define WM8915_AIF1RX_CHAN5_ENA_SHIFT 5 /* AIF1RX_CHAN5_ENA */
864#define WM8915_AIF1RX_CHAN5_ENA_WIDTH 1 /* AIF1RX_CHAN5_ENA */
865#define WM8915_AIF1RX_CHAN4_ENA 0x0010 /* AIF1RX_CHAN4_ENA */
866#define WM8915_AIF1RX_CHAN4_ENA_MASK 0x0010 /* AIF1RX_CHAN4_ENA */
867#define WM8915_AIF1RX_CHAN4_ENA_SHIFT 4 /* AIF1RX_CHAN4_ENA */
868#define WM8915_AIF1RX_CHAN4_ENA_WIDTH 1 /* AIF1RX_CHAN4_ENA */
869#define WM8915_AIF1RX_CHAN3_ENA 0x0008 /* AIF1RX_CHAN3_ENA */
870#define WM8915_AIF1RX_CHAN3_ENA_MASK 0x0008 /* AIF1RX_CHAN3_ENA */
871#define WM8915_AIF1RX_CHAN3_ENA_SHIFT 3 /* AIF1RX_CHAN3_ENA */
872#define WM8915_AIF1RX_CHAN3_ENA_WIDTH 1 /* AIF1RX_CHAN3_ENA */
873#define WM8915_AIF1RX_CHAN2_ENA 0x0004 /* AIF1RX_CHAN2_ENA */
874#define WM8915_AIF1RX_CHAN2_ENA_MASK 0x0004 /* AIF1RX_CHAN2_ENA */
875#define WM8915_AIF1RX_CHAN2_ENA_SHIFT 2 /* AIF1RX_CHAN2_ENA */
876#define WM8915_AIF1RX_CHAN2_ENA_WIDTH 1 /* AIF1RX_CHAN2_ENA */
877#define WM8915_AIF1RX_CHAN1_ENA 0x0002 /* AIF1RX_CHAN1_ENA */
878#define WM8915_AIF1RX_CHAN1_ENA_MASK 0x0002 /* AIF1RX_CHAN1_ENA */
879#define WM8915_AIF1RX_CHAN1_ENA_SHIFT 1 /* AIF1RX_CHAN1_ENA */
880#define WM8915_AIF1RX_CHAN1_ENA_WIDTH 1 /* AIF1RX_CHAN1_ENA */
881#define WM8915_AIF1RX_CHAN0_ENA 0x0001 /* AIF1RX_CHAN0_ENA */
882#define WM8915_AIF1RX_CHAN0_ENA_MASK 0x0001 /* AIF1RX_CHAN0_ENA */
883#define WM8915_AIF1RX_CHAN0_ENA_SHIFT 0 /* AIF1RX_CHAN0_ENA */
884#define WM8915_AIF1RX_CHAN0_ENA_WIDTH 1 /* AIF1RX_CHAN0_ENA */
885
886/*
887 * R5 (0x05) - Power Management (5)
888 */
889#define WM8915_DSP2TXL_ENA 0x0800 /* DSP2TXL_ENA */
890#define WM8915_DSP2TXL_ENA_MASK 0x0800 /* DSP2TXL_ENA */
891#define WM8915_DSP2TXL_ENA_SHIFT 11 /* DSP2TXL_ENA */
892#define WM8915_DSP2TXL_ENA_WIDTH 1 /* DSP2TXL_ENA */
893#define WM8915_DSP2TXR_ENA 0x0400 /* DSP2TXR_ENA */
894#define WM8915_DSP2TXR_ENA_MASK 0x0400 /* DSP2TXR_ENA */
895#define WM8915_DSP2TXR_ENA_SHIFT 10 /* DSP2TXR_ENA */
896#define WM8915_DSP2TXR_ENA_WIDTH 1 /* DSP2TXR_ENA */
897#define WM8915_DSP1TXL_ENA 0x0200 /* DSP1TXL_ENA */
898#define WM8915_DSP1TXL_ENA_MASK 0x0200 /* DSP1TXL_ENA */
899#define WM8915_DSP1TXL_ENA_SHIFT 9 /* DSP1TXL_ENA */
900#define WM8915_DSP1TXL_ENA_WIDTH 1 /* DSP1TXL_ENA */
901#define WM8915_DSP1TXR_ENA 0x0100 /* DSP1TXR_ENA */
902#define WM8915_DSP1TXR_ENA_MASK 0x0100 /* DSP1TXR_ENA */
903#define WM8915_DSP1TXR_ENA_SHIFT 8 /* DSP1TXR_ENA */
904#define WM8915_DSP1TXR_ENA_WIDTH 1 /* DSP1TXR_ENA */
905#define WM8915_DAC2L_ENA 0x0008 /* DAC2L_ENA */
906#define WM8915_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */
907#define WM8915_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */
908#define WM8915_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */
909#define WM8915_DAC2R_ENA 0x0004 /* DAC2R_ENA */
910#define WM8915_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */
911#define WM8915_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */
912#define WM8915_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */
913#define WM8915_DAC1L_ENA 0x0002 /* DAC1L_ENA */
914#define WM8915_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */
915#define WM8915_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */
916#define WM8915_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */
917#define WM8915_DAC1R_ENA 0x0001 /* DAC1R_ENA */
918#define WM8915_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */
919#define WM8915_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */
920#define WM8915_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */
921
922/*
923 * R6 (0x06) - Power Management (6)
924 */
925#define WM8915_AIF2TX_CHAN1_ENA 0x0200 /* AIF2TX_CHAN1_ENA */
926#define WM8915_AIF2TX_CHAN1_ENA_MASK 0x0200 /* AIF2TX_CHAN1_ENA */
927#define WM8915_AIF2TX_CHAN1_ENA_SHIFT 9 /* AIF2TX_CHAN1_ENA */
928#define WM8915_AIF2TX_CHAN1_ENA_WIDTH 1 /* AIF2TX_CHAN1_ENA */
929#define WM8915_AIF2TX_CHAN0_ENA 0x0100 /* AIF2TX_CHAN0_ENA */
930#define WM8915_AIF2TX_CHAN0_ENA_MASK 0x0100 /* AIF2TX_CHAN0_ENA */
931#define WM8915_AIF2TX_CHAN0_ENA_SHIFT 8 /* AIF2TX_CHAN0_ENA */
932#define WM8915_AIF2TX_CHAN0_ENA_WIDTH 1 /* AIF2TX_CHAN0_ENA */
933#define WM8915_AIF1TX_CHAN5_ENA 0x0020 /* AIF1TX_CHAN5_ENA */
934#define WM8915_AIF1TX_CHAN5_ENA_MASK 0x0020 /* AIF1TX_CHAN5_ENA */
935#define WM8915_AIF1TX_CHAN5_ENA_SHIFT 5 /* AIF1TX_CHAN5_ENA */
936#define WM8915_AIF1TX_CHAN5_ENA_WIDTH 1 /* AIF1TX_CHAN5_ENA */
937#define WM8915_AIF1TX_CHAN4_ENA 0x0010 /* AIF1TX_CHAN4_ENA */
938#define WM8915_AIF1TX_CHAN4_ENA_MASK 0x0010 /* AIF1TX_CHAN4_ENA */
939#define WM8915_AIF1TX_CHAN4_ENA_SHIFT 4 /* AIF1TX_CHAN4_ENA */
940#define WM8915_AIF1TX_CHAN4_ENA_WIDTH 1 /* AIF1TX_CHAN4_ENA */
941#define WM8915_AIF1TX_CHAN3_ENA 0x0008 /* AIF1TX_CHAN3_ENA */
942#define WM8915_AIF1TX_CHAN3_ENA_MASK 0x0008 /* AIF1TX_CHAN3_ENA */
943#define WM8915_AIF1TX_CHAN3_ENA_SHIFT 3 /* AIF1TX_CHAN3_ENA */
944#define WM8915_AIF1TX_CHAN3_ENA_WIDTH 1 /* AIF1TX_CHAN3_ENA */
945#define WM8915_AIF1TX_CHAN2_ENA 0x0004 /* AIF1TX_CHAN2_ENA */
946#define WM8915_AIF1TX_CHAN2_ENA_MASK 0x0004 /* AIF1TX_CHAN2_ENA */
947#define WM8915_AIF1TX_CHAN2_ENA_SHIFT 2 /* AIF1TX_CHAN2_ENA */
948#define WM8915_AIF1TX_CHAN2_ENA_WIDTH 1 /* AIF1TX_CHAN2_ENA */
949#define WM8915_AIF1TX_CHAN1_ENA 0x0002 /* AIF1TX_CHAN1_ENA */
950#define WM8915_AIF1TX_CHAN1_ENA_MASK 0x0002 /* AIF1TX_CHAN1_ENA */
951#define WM8915_AIF1TX_CHAN1_ENA_SHIFT 1 /* AIF1TX_CHAN1_ENA */
952#define WM8915_AIF1TX_CHAN1_ENA_WIDTH 1 /* AIF1TX_CHAN1_ENA */
953#define WM8915_AIF1TX_CHAN0_ENA 0x0001 /* AIF1TX_CHAN0_ENA */
954#define WM8915_AIF1TX_CHAN0_ENA_MASK 0x0001 /* AIF1TX_CHAN0_ENA */
955#define WM8915_AIF1TX_CHAN0_ENA_SHIFT 0 /* AIF1TX_CHAN0_ENA */
956#define WM8915_AIF1TX_CHAN0_ENA_WIDTH 1 /* AIF1TX_CHAN0_ENA */
957
958/*
959 * R7 (0x07) - Power Management (7)
960 */
961#define WM8915_DMIC2_FN 0x0200 /* DMIC2_FN */
962#define WM8915_DMIC2_FN_MASK 0x0200 /* DMIC2_FN */
963#define WM8915_DMIC2_FN_SHIFT 9 /* DMIC2_FN */
964#define WM8915_DMIC2_FN_WIDTH 1 /* DMIC2_FN */
965#define WM8915_DMIC1_FN 0x0100 /* DMIC1_FN */
966#define WM8915_DMIC1_FN_MASK 0x0100 /* DMIC1_FN */
967#define WM8915_DMIC1_FN_SHIFT 8 /* DMIC1_FN */
968#define WM8915_DMIC1_FN_WIDTH 1 /* DMIC1_FN */
969#define WM8915_ADC_DMIC_DSP2R_ENA 0x0080 /* ADC_DMIC_DSP2R_ENA */
970#define WM8915_ADC_DMIC_DSP2R_ENA_MASK 0x0080 /* ADC_DMIC_DSP2R_ENA */
971#define WM8915_ADC_DMIC_DSP2R_ENA_SHIFT 7 /* ADC_DMIC_DSP2R_ENA */
972#define WM8915_ADC_DMIC_DSP2R_ENA_WIDTH 1 /* ADC_DMIC_DSP2R_ENA */
973#define WM8915_ADC_DMIC_DSP2L_ENA 0x0040 /* ADC_DMIC_DSP2L_ENA */
974#define WM8915_ADC_DMIC_DSP2L_ENA_MASK 0x0040 /* ADC_DMIC_DSP2L_ENA */
975#define WM8915_ADC_DMIC_DSP2L_ENA_SHIFT 6 /* ADC_DMIC_DSP2L_ENA */
976#define WM8915_ADC_DMIC_DSP2L_ENA_WIDTH 1 /* ADC_DMIC_DSP2L_ENA */
977#define WM8915_ADC_DMIC_SRC2_MASK 0x0030 /* ADC_DMIC_SRC2 - [5:4] */
978#define WM8915_ADC_DMIC_SRC2_SHIFT 4 /* ADC_DMIC_SRC2 - [5:4] */
979#define WM8915_ADC_DMIC_SRC2_WIDTH 2 /* ADC_DMIC_SRC2 - [5:4] */
980#define WM8915_ADC_DMIC_DSP1R_ENA 0x0008 /* ADC_DMIC_DSP1R_ENA */
981#define WM8915_ADC_DMIC_DSP1R_ENA_MASK 0x0008 /* ADC_DMIC_DSP1R_ENA */
982#define WM8915_ADC_DMIC_DSP1R_ENA_SHIFT 3 /* ADC_DMIC_DSP1R_ENA */
983#define WM8915_ADC_DMIC_DSP1R_ENA_WIDTH 1 /* ADC_DMIC_DSP1R_ENA */
984#define WM8915_ADC_DMIC_DSP1L_ENA 0x0004 /* ADC_DMIC_DSP1L_ENA */
985#define WM8915_ADC_DMIC_DSP1L_ENA_MASK 0x0004 /* ADC_DMIC_DSP1L_ENA */
986#define WM8915_ADC_DMIC_DSP1L_ENA_SHIFT 2 /* ADC_DMIC_DSP1L_ENA */
987#define WM8915_ADC_DMIC_DSP1L_ENA_WIDTH 1 /* ADC_DMIC_DSP1L_ENA */
988#define WM8915_ADC_DMIC_SRC1_MASK 0x0003 /* ADC_DMIC_SRC1 - [1:0] */
989#define WM8915_ADC_DMIC_SRC1_SHIFT 0 /* ADC_DMIC_SRC1 - [1:0] */
990#define WM8915_ADC_DMIC_SRC1_WIDTH 2 /* ADC_DMIC_SRC1 - [1:0] */
991
992/*
993 * R8 (0x08) - Power Management (8)
994 */
995#define WM8915_AIF2TX_SRC_MASK 0x00C0 /* AIF2TX_SRC - [7:6] */
996#define WM8915_AIF2TX_SRC_SHIFT 6 /* AIF2TX_SRC - [7:6] */
997#define WM8915_AIF2TX_SRC_WIDTH 2 /* AIF2TX_SRC - [7:6] */
998#define WM8915_DSP2RX_SRC 0x0010 /* DSP2RX_SRC */
999#define WM8915_DSP2RX_SRC_MASK 0x0010 /* DSP2RX_SRC */
1000#define WM8915_DSP2RX_SRC_SHIFT 4 /* DSP2RX_SRC */
1001#define WM8915_DSP2RX_SRC_WIDTH 1 /* DSP2RX_SRC */
1002#define WM8915_DSP1RX_SRC 0x0001 /* DSP1RX_SRC */
1003#define WM8915_DSP1RX_SRC_MASK 0x0001 /* DSP1RX_SRC */
1004#define WM8915_DSP1RX_SRC_SHIFT 0 /* DSP1RX_SRC */
1005#define WM8915_DSP1RX_SRC_WIDTH 1 /* DSP1RX_SRC */
1006
1007/*
1008 * R16 (0x10) - Left Line Input Volume
1009 */
1010#define WM8915_IN1_VU 0x0080 /* IN1_VU */
1011#define WM8915_IN1_VU_MASK 0x0080 /* IN1_VU */
1012#define WM8915_IN1_VU_SHIFT 7 /* IN1_VU */
1013#define WM8915_IN1_VU_WIDTH 1 /* IN1_VU */
1014#define WM8915_IN1L_ZC 0x0020 /* IN1L_ZC */
1015#define WM8915_IN1L_ZC_MASK 0x0020 /* IN1L_ZC */
1016#define WM8915_IN1L_ZC_SHIFT 5 /* IN1L_ZC */
1017#define WM8915_IN1L_ZC_WIDTH 1 /* IN1L_ZC */
1018#define WM8915_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */
1019#define WM8915_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */
1020#define WM8915_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */
1021
1022/*
1023 * R17 (0x11) - Right Line Input Volume
1024 */
1025#define WM8915_IN1_VU 0x0080 /* IN1_VU */
1026#define WM8915_IN1_VU_MASK 0x0080 /* IN1_VU */
1027#define WM8915_IN1_VU_SHIFT 7 /* IN1_VU */
1028#define WM8915_IN1_VU_WIDTH 1 /* IN1_VU */
1029#define WM8915_IN1R_ZC 0x0020 /* IN1R_ZC */
1030#define WM8915_IN1R_ZC_MASK 0x0020 /* IN1R_ZC */
1031#define WM8915_IN1R_ZC_SHIFT 5 /* IN1R_ZC */
1032#define WM8915_IN1R_ZC_WIDTH 1 /* IN1R_ZC */
1033#define WM8915_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */
1034#define WM8915_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */
1035#define WM8915_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */
1036
1037/*
1038 * R18 (0x12) - Line Input Control
1039 */
1040#define WM8915_INL_MODE_MASK 0x000C /* INL_MODE - [3:2] */
1041#define WM8915_INL_MODE_SHIFT 2 /* INL_MODE - [3:2] */
1042#define WM8915_INL_MODE_WIDTH 2 /* INL_MODE - [3:2] */
1043#define WM8915_INR_MODE_MASK 0x0003 /* INR_MODE - [1:0] */
1044#define WM8915_INR_MODE_SHIFT 0 /* INR_MODE - [1:0] */
1045#define WM8915_INR_MODE_WIDTH 2 /* INR_MODE - [1:0] */
1046
1047/*
1048 * R21 (0x15) - DAC1 HPOUT1 Volume
1049 */
1050#define WM8915_DAC1R_HPOUT1R_VOL_MASK 0x00F0 /* DAC1R_HPOUT1R_VOL - [7:4] */
1051#define WM8915_DAC1R_HPOUT1R_VOL_SHIFT 4 /* DAC1R_HPOUT1R_VOL - [7:4] */
1052#define WM8915_DAC1R_HPOUT1R_VOL_WIDTH 4 /* DAC1R_HPOUT1R_VOL - [7:4] */
1053#define WM8915_DAC1L_HPOUT1L_VOL_MASK 0x000F /* DAC1L_HPOUT1L_VOL - [3:0] */
1054#define WM8915_DAC1L_HPOUT1L_VOL_SHIFT 0 /* DAC1L_HPOUT1L_VOL - [3:0] */
1055#define WM8915_DAC1L_HPOUT1L_VOL_WIDTH 4 /* DAC1L_HPOUT1L_VOL - [3:0] */
1056
1057/*
1058 * R22 (0x16) - DAC2 HPOUT2 Volume
1059 */
1060#define WM8915_DAC2R_HPOUT2R_VOL_MASK 0x00F0 /* DAC2R_HPOUT2R_VOL - [7:4] */
1061#define WM8915_DAC2R_HPOUT2R_VOL_SHIFT 4 /* DAC2R_HPOUT2R_VOL - [7:4] */
1062#define WM8915_DAC2R_HPOUT2R_VOL_WIDTH 4 /* DAC2R_HPOUT2R_VOL - [7:4] */
1063#define WM8915_DAC2L_HPOUT2L_VOL_MASK 0x000F /* DAC2L_HPOUT2L_VOL - [3:0] */
1064#define WM8915_DAC2L_HPOUT2L_VOL_SHIFT 0 /* DAC2L_HPOUT2L_VOL - [3:0] */
1065#define WM8915_DAC2L_HPOUT2L_VOL_WIDTH 4 /* DAC2L_HPOUT2L_VOL - [3:0] */
1066
1067/*
1068 * R24 (0x18) - DAC1 Left Volume
1069 */
1070#define WM8915_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */
1071#define WM8915_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */
1072#define WM8915_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */
1073#define WM8915_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */
1074#define WM8915_DAC1_VU 0x0100 /* DAC1_VU */
1075#define WM8915_DAC1_VU_MASK 0x0100 /* DAC1_VU */
1076#define WM8915_DAC1_VU_SHIFT 8 /* DAC1_VU */
1077#define WM8915_DAC1_VU_WIDTH 1 /* DAC1_VU */
1078#define WM8915_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */
1079#define WM8915_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */
1080#define WM8915_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */
1081
1082/*
1083 * R25 (0x19) - DAC1 Right Volume
1084 */
1085#define WM8915_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */
1086#define WM8915_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */
1087#define WM8915_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */
1088#define WM8915_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */
1089#define WM8915_DAC1_VU 0x0100 /* DAC1_VU */
1090#define WM8915_DAC1_VU_MASK 0x0100 /* DAC1_VU */
1091#define WM8915_DAC1_VU_SHIFT 8 /* DAC1_VU */
1092#define WM8915_DAC1_VU_WIDTH 1 /* DAC1_VU */
1093#define WM8915_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */
1094#define WM8915_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */
1095#define WM8915_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */
1096
1097/*
1098 * R26 (0x1A) - DAC2 Left Volume
1099 */
1100#define WM8915_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */
1101#define WM8915_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */
1102#define WM8915_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */
1103#define WM8915_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */
1104#define WM8915_DAC2_VU 0x0100 /* DAC2_VU */
1105#define WM8915_DAC2_VU_MASK 0x0100 /* DAC2_VU */
1106#define WM8915_DAC2_VU_SHIFT 8 /* DAC2_VU */
1107#define WM8915_DAC2_VU_WIDTH 1 /* DAC2_VU */
1108#define WM8915_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */
1109#define WM8915_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */
1110#define WM8915_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */
1111
1112/*
1113 * R27 (0x1B) - DAC2 Right Volume
1114 */
1115#define WM8915_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */
1116#define WM8915_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */
1117#define WM8915_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */
1118#define WM8915_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */
1119#define WM8915_DAC2_VU 0x0100 /* DAC2_VU */
1120#define WM8915_DAC2_VU_MASK 0x0100 /* DAC2_VU */
1121#define WM8915_DAC2_VU_SHIFT 8 /* DAC2_VU */
1122#define WM8915_DAC2_VU_WIDTH 1 /* DAC2_VU */
1123#define WM8915_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */
1124#define WM8915_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */
1125#define WM8915_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */
1126
1127/*
1128 * R28 (0x1C) - Output1 Left Volume
1129 */
1130#define WM8915_DAC1_VU 0x0100 /* DAC1_VU */
1131#define WM8915_DAC1_VU_MASK 0x0100 /* DAC1_VU */
1132#define WM8915_DAC1_VU_SHIFT 8 /* DAC1_VU */
1133#define WM8915_DAC1_VU_WIDTH 1 /* DAC1_VU */
1134#define WM8915_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */
1135#define WM8915_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */
1136#define WM8915_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */
1137#define WM8915_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */
1138#define WM8915_HPOUT1L_VOL_MASK 0x000F /* HPOUT1L_VOL - [3:0] */
1139#define WM8915_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [3:0] */
1140#define WM8915_HPOUT1L_VOL_WIDTH 4 /* HPOUT1L_VOL - [3:0] */
1141
1142/*
1143 * R29 (0x1D) - Output1 Right Volume
1144 */
1145#define WM8915_DAC1_VU 0x0100 /* DAC1_VU */
1146#define WM8915_DAC1_VU_MASK 0x0100 /* DAC1_VU */
1147#define WM8915_DAC1_VU_SHIFT 8 /* DAC1_VU */
1148#define WM8915_DAC1_VU_WIDTH 1 /* DAC1_VU */
1149#define WM8915_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */
1150#define WM8915_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */
1151#define WM8915_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */
1152#define WM8915_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */
1153#define WM8915_HPOUT1R_VOL_MASK 0x000F /* HPOUT1R_VOL - [3:0] */
1154#define WM8915_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [3:0] */
1155#define WM8915_HPOUT1R_VOL_WIDTH 4 /* HPOUT1R_VOL - [3:0] */
1156
1157/*
1158 * R30 (0x1E) - Output2 Left Volume
1159 */
1160#define WM8915_DAC2_VU 0x0100 /* DAC2_VU */
1161#define WM8915_DAC2_VU_MASK 0x0100 /* DAC2_VU */
1162#define WM8915_DAC2_VU_SHIFT 8 /* DAC2_VU */
1163#define WM8915_DAC2_VU_WIDTH 1 /* DAC2_VU */
1164#define WM8915_HPOUT2L_ZC 0x0080 /* HPOUT2L_ZC */
1165#define WM8915_HPOUT2L_ZC_MASK 0x0080 /* HPOUT2L_ZC */
1166#define WM8915_HPOUT2L_ZC_SHIFT 7 /* HPOUT2L_ZC */
1167#define WM8915_HPOUT2L_ZC_WIDTH 1 /* HPOUT2L_ZC */
1168#define WM8915_HPOUT2L_VOL_MASK 0x000F /* HPOUT2L_VOL - [3:0] */
1169#define WM8915_HPOUT2L_VOL_SHIFT 0 /* HPOUT2L_VOL - [3:0] */
1170#define WM8915_HPOUT2L_VOL_WIDTH 4 /* HPOUT2L_VOL - [3:0] */
1171
1172/*
1173 * R31 (0x1F) - Output2 Right Volume
1174 */
1175#define WM8915_DAC2_VU 0x0100 /* DAC2_VU */
1176#define WM8915_DAC2_VU_MASK 0x0100 /* DAC2_VU */
1177#define WM8915_DAC2_VU_SHIFT 8 /* DAC2_VU */
1178#define WM8915_DAC2_VU_WIDTH 1 /* DAC2_VU */
1179#define WM8915_HPOUT2R_ZC 0x0080 /* HPOUT2R_ZC */
1180#define WM8915_HPOUT2R_ZC_MASK 0x0080 /* HPOUT2R_ZC */
1181#define WM8915_HPOUT2R_ZC_SHIFT 7 /* HPOUT2R_ZC */
1182#define WM8915_HPOUT2R_ZC_WIDTH 1 /* HPOUT2R_ZC */
1183#define WM8915_HPOUT2R_VOL_MASK 0x000F /* HPOUT2R_VOL - [3:0] */
1184#define WM8915_HPOUT2R_VOL_SHIFT 0 /* HPOUT2R_VOL - [3:0] */
1185#define WM8915_HPOUT2R_VOL_WIDTH 4 /* HPOUT2R_VOL - [3:0] */
1186
1187/*
1188 * R32 (0x20) - MICBIAS (1)
1189 */
1190#define WM8915_MICB1_RATE 0x0020 /* MICB1_RATE */
1191#define WM8915_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */
1192#define WM8915_MICB1_RATE_SHIFT 5 /* MICB1_RATE */
1193#define WM8915_MICB1_RATE_WIDTH 1 /* MICB1_RATE */
1194#define WM8915_MICB1_MODE 0x0010 /* MICB1_MODE */
1195#define WM8915_MICB1_MODE_MASK 0x0010 /* MICB1_MODE */
1196#define WM8915_MICB1_MODE_SHIFT 4 /* MICB1_MODE */
1197#define WM8915_MICB1_MODE_WIDTH 1 /* MICB1_MODE */
1198#define WM8915_MICB1_LVL_MASK 0x000E /* MICB1_LVL - [3:1] */
1199#define WM8915_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [3:1] */
1200#define WM8915_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [3:1] */
1201#define WM8915_MICB1_DISCH 0x0001 /* MICB1_DISCH */
1202#define WM8915_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */
1203#define WM8915_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */
1204#define WM8915_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
1205
1206/*
1207 * R33 (0x21) - MICBIAS (2)
1208 */
1209#define WM8915_MICB2_RATE 0x0020 /* MICB2_RATE */
1210#define WM8915_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */
1211#define WM8915_MICB2_RATE_SHIFT 5 /* MICB2_RATE */
1212#define WM8915_MICB2_RATE_WIDTH 1 /* MICB2_RATE */
1213#define WM8915_MICB2_MODE 0x0010 /* MICB2_MODE */
1214#define WM8915_MICB2_MODE_MASK 0x0010 /* MICB2_MODE */
1215#define WM8915_MICB2_MODE_SHIFT 4 /* MICB2_MODE */
1216#define WM8915_MICB2_MODE_WIDTH 1 /* MICB2_MODE */
1217#define WM8915_MICB2_LVL_MASK 0x000E /* MICB2_LVL - [3:1] */
1218#define WM8915_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [3:1] */
1219#define WM8915_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [3:1] */
1220#define WM8915_MICB2_DISCH 0x0001 /* MICB2_DISCH */
1221#define WM8915_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */
1222#define WM8915_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */
1223#define WM8915_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
1224
1225/*
1226 * R40 (0x28) - LDO 1
1227 */
1228#define WM8915_LDO1_MODE 0x0020 /* LDO1_MODE */
1229#define WM8915_LDO1_MODE_MASK 0x0020 /* LDO1_MODE */
1230#define WM8915_LDO1_MODE_SHIFT 5 /* LDO1_MODE */
1231#define WM8915_LDO1_MODE_WIDTH 1 /* LDO1_MODE */
1232#define WM8915_LDO1_VSEL_MASK 0x0006 /* LDO1_VSEL - [2:1] */
1233#define WM8915_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [2:1] */
1234#define WM8915_LDO1_VSEL_WIDTH 2 /* LDO1_VSEL - [2:1] */
1235#define WM8915_LDO1_DISCH 0x0001 /* LDO1_DISCH */
1236#define WM8915_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */
1237#define WM8915_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */
1238#define WM8915_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */
1239
1240/*
1241 * R41 (0x29) - LDO 2
1242 */
1243#define WM8915_LDO2_MODE 0x0020 /* LDO2_MODE */
1244#define WM8915_LDO2_MODE_MASK 0x0020 /* LDO2_MODE */
1245#define WM8915_LDO2_MODE_SHIFT 5 /* LDO2_MODE */
1246#define WM8915_LDO2_MODE_WIDTH 1 /* LDO2_MODE */
1247#define WM8915_LDO2_VSEL_MASK 0x001E /* LDO2_VSEL - [4:1] */
1248#define WM8915_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [4:1] */
1249#define WM8915_LDO2_VSEL_WIDTH 4 /* LDO2_VSEL - [4:1] */
1250#define WM8915_LDO2_DISCH 0x0001 /* LDO2_DISCH */
1251#define WM8915_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */
1252#define WM8915_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */
1253#define WM8915_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */
1254
1255/*
1256 * R48 (0x30) - Accessory Detect Mode 1
1257 */
1258#define WM8915_JD_MODE_MASK 0x0003 /* JD_MODE - [1:0] */
1259#define WM8915_JD_MODE_SHIFT 0 /* JD_MODE - [1:0] */
1260#define WM8915_JD_MODE_WIDTH 2 /* JD_MODE - [1:0] */
1261
1262/*
1263 * R49 (0x31) - Accessory Detect Mode 2
1264 */
1265#define WM8915_HPOUT1FB_SRC 0x0004 /* HPOUT1FB_SRC */
1266#define WM8915_HPOUT1FB_SRC_MASK 0x0004 /* HPOUT1FB_SRC */
1267#define WM8915_HPOUT1FB_SRC_SHIFT 2 /* HPOUT1FB_SRC */
1268#define WM8915_HPOUT1FB_SRC_WIDTH 1 /* HPOUT1FB_SRC */
1269#define WM8915_MICD_SRC 0x0002 /* MICD_SRC */
1270#define WM8915_MICD_SRC_MASK 0x0002 /* MICD_SRC */
1271#define WM8915_MICD_SRC_SHIFT 1 /* MICD_SRC */
1272#define WM8915_MICD_SRC_WIDTH 1 /* MICD_SRC */
1273#define WM8915_MICD_BIAS_SRC 0x0001 /* MICD_BIAS_SRC */
1274#define WM8915_MICD_BIAS_SRC_MASK 0x0001 /* MICD_BIAS_SRC */
1275#define WM8915_MICD_BIAS_SRC_SHIFT 0 /* MICD_BIAS_SRC */
1276#define WM8915_MICD_BIAS_SRC_WIDTH 1 /* MICD_BIAS_SRC */
1277
1278/*
1279 * R52 (0x34) - Headphone Detect 1
1280 */
1281#define WM8915_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */
1282#define WM8915_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */
1283#define WM8915_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */
1284#define WM8915_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */
1285#define WM8915_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */
1286#define WM8915_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */
1287#define WM8915_HP_STEP_SIZE 0x0002 /* HP_STEP_SIZE */
1288#define WM8915_HP_STEP_SIZE_MASK 0x0002 /* HP_STEP_SIZE */
1289#define WM8915_HP_STEP_SIZE_SHIFT 1 /* HP_STEP_SIZE */
1290#define WM8915_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */
1291#define WM8915_HP_POLL 0x0001 /* HP_POLL */
1292#define WM8915_HP_POLL_MASK 0x0001 /* HP_POLL */
1293#define WM8915_HP_POLL_SHIFT 0 /* HP_POLL */
1294#define WM8915_HP_POLL_WIDTH 1 /* HP_POLL */
1295
1296/*
1297 * R53 (0x35) - Headphone Detect 2
1298 */
1299#define WM8915_HP_DONE 0x0080 /* HP_DONE */
1300#define WM8915_HP_DONE_MASK 0x0080 /* HP_DONE */
1301#define WM8915_HP_DONE_SHIFT 7 /* HP_DONE */
1302#define WM8915_HP_DONE_WIDTH 1 /* HP_DONE */
1303#define WM8915_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */
1304#define WM8915_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */
1305#define WM8915_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */
1306
1307/*
1308 * R56 (0x38) - Mic Detect 1
1309 */
1310#define WM8915_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */
1311#define WM8915_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */
1312#define WM8915_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */
1313#define WM8915_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */
1314#define WM8915_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */
1315#define WM8915_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */
1316#define WM8915_MICD_DBTIME 0x0002 /* MICD_DBTIME */
1317#define WM8915_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */
1318#define WM8915_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */
1319#define WM8915_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */
1320#define WM8915_MICD_ENA 0x0001 /* MICD_ENA */
1321#define WM8915_MICD_ENA_MASK 0x0001 /* MICD_ENA */
1322#define WM8915_MICD_ENA_SHIFT 0 /* MICD_ENA */
1323#define WM8915_MICD_ENA_WIDTH 1 /* MICD_ENA */
1324
1325/*
1326 * R57 (0x39) - Mic Detect 2
1327 */
1328#define WM8915_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */
1329#define WM8915_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */
1330#define WM8915_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */
1331
1332/*
1333 * R58 (0x3A) - Mic Detect 3
1334 */
1335#define WM8915_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */
1336#define WM8915_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */
1337#define WM8915_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */
1338#define WM8915_MICD_VALID 0x0002 /* MICD_VALID */
1339#define WM8915_MICD_VALID_MASK 0x0002 /* MICD_VALID */
1340#define WM8915_MICD_VALID_SHIFT 1 /* MICD_VALID */
1341#define WM8915_MICD_VALID_WIDTH 1 /* MICD_VALID */
1342#define WM8915_MICD_STS 0x0001 /* MICD_STS */
1343#define WM8915_MICD_STS_MASK 0x0001 /* MICD_STS */
1344#define WM8915_MICD_STS_SHIFT 0 /* MICD_STS */
1345#define WM8915_MICD_STS_WIDTH 1 /* MICD_STS */
1346
1347/*
1348 * R64 (0x40) - Charge Pump (1)
1349 */
1350#define WM8915_CP_ENA 0x8000 /* CP_ENA */
1351#define WM8915_CP_ENA_MASK 0x8000 /* CP_ENA */
1352#define WM8915_CP_ENA_SHIFT 15 /* CP_ENA */
1353#define WM8915_CP_ENA_WIDTH 1 /* CP_ENA */
1354
1355/*
1356 * R65 (0x41) - Charge Pump (2)
1357 */
1358#define WM8915_CP_DISCH 0x8000 /* CP_DISCH */
1359#define WM8915_CP_DISCH_MASK 0x8000 /* CP_DISCH */
1360#define WM8915_CP_DISCH_SHIFT 15 /* CP_DISCH */
1361#define WM8915_CP_DISCH_WIDTH 1 /* CP_DISCH */
1362
1363/*
1364 * R80 (0x50) - DC Servo (1)
1365 */
1366#define WM8915_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */
1367#define WM8915_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */
1368#define WM8915_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */
1369#define WM8915_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */
1370#define WM8915_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */
1371#define WM8915_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */
1372#define WM8915_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */
1373#define WM8915_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */
1374#define WM8915_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */
1375#define WM8915_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */
1376#define WM8915_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */
1377#define WM8915_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */
1378#define WM8915_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */
1379#define WM8915_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */
1380#define WM8915_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */
1381#define WM8915_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */
1382
1383/*
1384 * R81 (0x51) - DC Servo (2)
1385 */
1386#define WM8915_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */
1387#define WM8915_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */
1388#define WM8915_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */
1389#define WM8915_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */
1390#define WM8915_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */
1391#define WM8915_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */
1392#define WM8915_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */
1393#define WM8915_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */
1394#define WM8915_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */
1395#define WM8915_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */
1396#define WM8915_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */
1397#define WM8915_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */
1398#define WM8915_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */
1399#define WM8915_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */
1400#define WM8915_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */
1401#define WM8915_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */
1402#define WM8915_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */
1403#define WM8915_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */
1404#define WM8915_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */
1405#define WM8915_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */
1406#define WM8915_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */
1407#define WM8915_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */
1408#define WM8915_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */
1409#define WM8915_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */
1410#define WM8915_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */
1411#define WM8915_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */
1412#define WM8915_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */
1413#define WM8915_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */
1414#define WM8915_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */
1415#define WM8915_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */
1416#define WM8915_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */
1417#define WM8915_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */
1418#define WM8915_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */
1419#define WM8915_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */
1420#define WM8915_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */
1421#define WM8915_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */
1422#define WM8915_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */
1423#define WM8915_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */
1424#define WM8915_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */
1425#define WM8915_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */
1426#define WM8915_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */
1427#define WM8915_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */
1428#define WM8915_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */
1429#define WM8915_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */
1430#define WM8915_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */
1431#define WM8915_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */
1432#define WM8915_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */
1433#define WM8915_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */
1434#define WM8915_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */
1435#define WM8915_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */
1436#define WM8915_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */
1437#define WM8915_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */
1438#define WM8915_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */
1439#define WM8915_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */
1440#define WM8915_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */
1441#define WM8915_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */
1442#define WM8915_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */
1443#define WM8915_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */
1444#define WM8915_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */
1445#define WM8915_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */
1446#define WM8915_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */
1447#define WM8915_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */
1448#define WM8915_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */
1449#define WM8915_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */
1450
1451/*
1452 * R82 (0x52) - DC Servo (3)
1453 */
1454#define WM8915_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */
1455#define WM8915_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */
1456#define WM8915_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */
1457#define WM8915_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */
1458#define WM8915_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */
1459#define WM8915_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */
1460
1461/*
1462 * R84 (0x54) - DC Servo (5)
1463 */
1464#define WM8915_DCS_SERIES_NO_23_MASK 0x7F00 /* DCS_SERIES_NO_23 - [14:8] */
1465#define WM8915_DCS_SERIES_NO_23_SHIFT 8 /* DCS_SERIES_NO_23 - [14:8] */
1466#define WM8915_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [14:8] */
1467#define WM8915_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */
1468#define WM8915_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */
1469#define WM8915_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */
1470
1471/*
1472 * R85 (0x55) - DC Servo (6)
1473 */
1474#define WM8915_DCS_DAC_WR_VAL_3_MASK 0xFF00 /* DCS_DAC_WR_VAL_3 - [15:8] */
1475#define WM8915_DCS_DAC_WR_VAL_3_SHIFT 8 /* DCS_DAC_WR_VAL_3 - [15:8] */
1476#define WM8915_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [15:8] */
1477#define WM8915_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */
1478#define WM8915_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */
1479#define WM8915_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */
1480
1481/*
1482 * R86 (0x56) - DC Servo (7)
1483 */
1484#define WM8915_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */
1485#define WM8915_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
1486#define WM8915_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
1487#define WM8915_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */
1488#define WM8915_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */
1489#define WM8915_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */
1490
1491/*
1492 * R87 (0x57) - DC Servo Readback 0
1493 */
1494#define WM8915_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */
1495#define WM8915_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */
1496#define WM8915_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */
1497#define WM8915_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */
1498#define WM8915_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */
1499#define WM8915_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */
1500#define WM8915_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */
1501#define WM8915_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */
1502#define WM8915_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */
1503
1504/*
1505 * R96 (0x60) - Analogue HP (1)
1506 */
1507#define WM8915_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */
1508#define WM8915_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */
1509#define WM8915_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */
1510#define WM8915_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */
1511#define WM8915_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */
1512#define WM8915_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */
1513#define WM8915_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */
1514#define WM8915_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */
1515#define WM8915_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */
1516#define WM8915_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */
1517#define WM8915_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */
1518#define WM8915_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */
1519#define WM8915_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */
1520#define WM8915_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */
1521#define WM8915_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */
1522#define WM8915_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */
1523#define WM8915_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */
1524#define WM8915_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */
1525#define WM8915_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */
1526#define WM8915_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */
1527#define WM8915_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */
1528#define WM8915_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */
1529#define WM8915_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */
1530#define WM8915_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */
1531
1532/*
1533 * R97 (0x61) - Analogue HP (2)
1534 */
1535#define WM8915_HPOUT2L_RMV_SHORT 0x0080 /* HPOUT2L_RMV_SHORT */
1536#define WM8915_HPOUT2L_RMV_SHORT_MASK 0x0080 /* HPOUT2L_RMV_SHORT */
1537#define WM8915_HPOUT2L_RMV_SHORT_SHIFT 7 /* HPOUT2L_RMV_SHORT */
1538#define WM8915_HPOUT2L_RMV_SHORT_WIDTH 1 /* HPOUT2L_RMV_SHORT */
1539#define WM8915_HPOUT2L_OUTP 0x0040 /* HPOUT2L_OUTP */
1540#define WM8915_HPOUT2L_OUTP_MASK 0x0040 /* HPOUT2L_OUTP */
1541#define WM8915_HPOUT2L_OUTP_SHIFT 6 /* HPOUT2L_OUTP */
1542#define WM8915_HPOUT2L_OUTP_WIDTH 1 /* HPOUT2L_OUTP */
1543#define WM8915_HPOUT2L_DLY 0x0020 /* HPOUT2L_DLY */
1544#define WM8915_HPOUT2L_DLY_MASK 0x0020 /* HPOUT2L_DLY */
1545#define WM8915_HPOUT2L_DLY_SHIFT 5 /* HPOUT2L_DLY */
1546#define WM8915_HPOUT2L_DLY_WIDTH 1 /* HPOUT2L_DLY */
1547#define WM8915_HPOUT2R_RMV_SHORT 0x0008 /* HPOUT2R_RMV_SHORT */
1548#define WM8915_HPOUT2R_RMV_SHORT_MASK 0x0008 /* HPOUT2R_RMV_SHORT */
1549#define WM8915_HPOUT2R_RMV_SHORT_SHIFT 3 /* HPOUT2R_RMV_SHORT */
1550#define WM8915_HPOUT2R_RMV_SHORT_WIDTH 1 /* HPOUT2R_RMV_SHORT */
1551#define WM8915_HPOUT2R_OUTP 0x0004 /* HPOUT2R_OUTP */
1552#define WM8915_HPOUT2R_OUTP_MASK 0x0004 /* HPOUT2R_OUTP */
1553#define WM8915_HPOUT2R_OUTP_SHIFT 2 /* HPOUT2R_OUTP */
1554#define WM8915_HPOUT2R_OUTP_WIDTH 1 /* HPOUT2R_OUTP */
1555#define WM8915_HPOUT2R_DLY 0x0002 /* HPOUT2R_DLY */
1556#define WM8915_HPOUT2R_DLY_MASK 0x0002 /* HPOUT2R_DLY */
1557#define WM8915_HPOUT2R_DLY_SHIFT 1 /* HPOUT2R_DLY */
1558#define WM8915_HPOUT2R_DLY_WIDTH 1 /* HPOUT2R_DLY */
1559
1560/*
1561 * R256 (0x100) - Chip Revision
1562 */
1563#define WM8915_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */
1564#define WM8915_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */
1565#define WM8915_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */
1566
1567/*
1568 * R257 (0x101) - Control Interface (1)
1569 */
1570#define WM8915_AUTO_INC 0x0004 /* AUTO_INC */
1571#define WM8915_AUTO_INC_MASK 0x0004 /* AUTO_INC */
1572#define WM8915_AUTO_INC_SHIFT 2 /* AUTO_INC */
1573#define WM8915_AUTO_INC_WIDTH 1 /* AUTO_INC */
1574
1575/*
1576 * R272 (0x110) - Write Sequencer Ctrl (1)
1577 */
1578#define WM8915_WSEQ_ENA 0x8000 /* WSEQ_ENA */
1579#define WM8915_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */
1580#define WM8915_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */
1581#define WM8915_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
1582#define WM8915_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
1583#define WM8915_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
1584#define WM8915_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
1585#define WM8915_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
1586#define WM8915_WSEQ_START 0x0100 /* WSEQ_START */
1587#define WM8915_WSEQ_START_MASK 0x0100 /* WSEQ_START */
1588#define WM8915_WSEQ_START_SHIFT 8 /* WSEQ_START */
1589#define WM8915_WSEQ_START_WIDTH 1 /* WSEQ_START */
1590#define WM8915_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
1591#define WM8915_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
1592#define WM8915_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
1593
1594/*
1595 * R273 (0x111) - Write Sequencer Ctrl (2)
1596 */
1597#define WM8915_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */
1598#define WM8915_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */
1599#define WM8915_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */
1600#define WM8915_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
1601#define WM8915_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */
1602#define WM8915_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */
1603#define WM8915_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */
1604
1605/*
1606 * R512 (0x200) - AIF Clocking (1)
1607 */
1608#define WM8915_SYSCLK_SRC_MASK 0x0018 /* SYSCLK_SRC - [4:3] */
1609#define WM8915_SYSCLK_SRC_SHIFT 3 /* SYSCLK_SRC - [4:3] */
1610#define WM8915_SYSCLK_SRC_WIDTH 2 /* SYSCLK_SRC - [4:3] */
1611#define WM8915_SYSCLK_INV 0x0004 /* SYSCLK_INV */
1612#define WM8915_SYSCLK_INV_MASK 0x0004 /* SYSCLK_INV */
1613#define WM8915_SYSCLK_INV_SHIFT 2 /* SYSCLK_INV */
1614#define WM8915_SYSCLK_INV_WIDTH 1 /* SYSCLK_INV */
1615#define WM8915_SYSCLK_DIV 0x0002 /* SYSCLK_DIV */
1616#define WM8915_SYSCLK_DIV_MASK 0x0002 /* SYSCLK_DIV */
1617#define WM8915_SYSCLK_DIV_SHIFT 1 /* SYSCLK_DIV */
1618#define WM8915_SYSCLK_DIV_WIDTH 1 /* SYSCLK_DIV */
1619#define WM8915_SYSCLK_ENA 0x0001 /* SYSCLK_ENA */
1620#define WM8915_SYSCLK_ENA_MASK 0x0001 /* SYSCLK_ENA */
1621#define WM8915_SYSCLK_ENA_SHIFT 0 /* SYSCLK_ENA */
1622#define WM8915_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */
1623
1624/*
1625 * R513 (0x201) - AIF Clocking (2)
1626 */
1627#define WM8915_DSP2_DIV_MASK 0x0018 /* DSP2_DIV - [4:3] */
1628#define WM8915_DSP2_DIV_SHIFT 3 /* DSP2_DIV - [4:3] */
1629#define WM8915_DSP2_DIV_WIDTH 2 /* DSP2_DIV - [4:3] */
1630#define WM8915_DSP1_DIV_MASK 0x0003 /* DSP1_DIV - [1:0] */
1631#define WM8915_DSP1_DIV_SHIFT 0 /* DSP1_DIV - [1:0] */
1632#define WM8915_DSP1_DIV_WIDTH 2 /* DSP1_DIV - [1:0] */
1633
1634/*
1635 * R520 (0x208) - Clocking (1)
1636 */
1637#define WM8915_LFCLK_ENA 0x0020 /* LFCLK_ENA */
1638#define WM8915_LFCLK_ENA_MASK 0x0020 /* LFCLK_ENA */
1639#define WM8915_LFCLK_ENA_SHIFT 5 /* LFCLK_ENA */
1640#define WM8915_LFCLK_ENA_WIDTH 1 /* LFCLK_ENA */
1641#define WM8915_TOCLK_ENA 0x0010 /* TOCLK_ENA */
1642#define WM8915_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */
1643#define WM8915_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */
1644#define WM8915_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
1645#define WM8915_AIFCLK_ENA 0x0004 /* AIFCLK_ENA */
1646#define WM8915_AIFCLK_ENA_MASK 0x0004 /* AIFCLK_ENA */
1647#define WM8915_AIFCLK_ENA_SHIFT 2 /* AIFCLK_ENA */
1648#define WM8915_AIFCLK_ENA_WIDTH 1 /* AIFCLK_ENA */
1649#define WM8915_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */
1650#define WM8915_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */
1651#define WM8915_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */
1652#define WM8915_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */
1653
1654/*
1655 * R521 (0x209) - Clocking (2)
1656 */
1657#define WM8915_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */
1658#define WM8915_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */
1659#define WM8915_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */
1660#define WM8915_DBCLK_DIV_MASK 0x00F0 /* DBCLK_DIV - [7:4] */
1661#define WM8915_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [7:4] */
1662#define WM8915_DBCLK_DIV_WIDTH 4 /* DBCLK_DIV - [7:4] */
1663#define WM8915_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */
1664#define WM8915_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */
1665#define WM8915_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */
1666
1667/*
1668 * R528 (0x210) - AIF Rate
1669 */
1670#define WM8915_SYSCLK_RATE 0x0001 /* SYSCLK_RATE */
1671#define WM8915_SYSCLK_RATE_MASK 0x0001 /* SYSCLK_RATE */
1672#define WM8915_SYSCLK_RATE_SHIFT 0 /* SYSCLK_RATE */
1673#define WM8915_SYSCLK_RATE_WIDTH 1 /* SYSCLK_RATE */
1674
1675/*
1676 * R544 (0x220) - FLL Control (1)
1677 */
1678#define WM8915_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */
1679#define WM8915_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */
1680#define WM8915_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */
1681#define WM8915_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */
1682#define WM8915_FLL_ENA 0x0001 /* FLL_ENA */
1683#define WM8915_FLL_ENA_MASK 0x0001 /* FLL_ENA */
1684#define WM8915_FLL_ENA_SHIFT 0 /* FLL_ENA */
1685#define WM8915_FLL_ENA_WIDTH 1 /* FLL_ENA */
1686
1687/*
1688 * R545 (0x221) - FLL Control (2)
1689 */
1690#define WM8915_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */
1691#define WM8915_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */
1692#define WM8915_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */
1693#define WM8915_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
1694#define WM8915_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
1695#define WM8915_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
1696
1697/*
1698 * R546 (0x222) - FLL Control (3)
1699 */
1700#define WM8915_FLL_THETA_MASK 0xFFFF /* FLL_THETA - [15:0] */
1701#define WM8915_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */
1702#define WM8915_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */
1703
1704/*
1705 * R547 (0x223) - FLL Control (4)
1706 */
1707#define WM8915_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
1708#define WM8915_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
1709#define WM8915_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
1710#define WM8915_FLL_LOOP_GAIN_MASK 0x000F /* FLL_LOOP_GAIN - [3:0] */
1711#define WM8915_FLL_LOOP_GAIN_SHIFT 0 /* FLL_LOOP_GAIN - [3:0] */
1712#define WM8915_FLL_LOOP_GAIN_WIDTH 4 /* FLL_LOOP_GAIN - [3:0] */
1713
1714/*
1715 * R548 (0x224) - FLL Control (5)
1716 */
1717#define WM8915_FLL_FRC_NCO_VAL_MASK 0x1F80 /* FLL_FRC_NCO_VAL - [12:7] */
1718#define WM8915_FLL_FRC_NCO_VAL_SHIFT 7 /* FLL_FRC_NCO_VAL - [12:7] */
1719#define WM8915_FLL_FRC_NCO_VAL_WIDTH 6 /* FLL_FRC_NCO_VAL - [12:7] */
1720#define WM8915_FLL_FRC_NCO 0x0040 /* FLL_FRC_NCO */
1721#define WM8915_FLL_FRC_NCO_MASK 0x0040 /* FLL_FRC_NCO */
1722#define WM8915_FLL_FRC_NCO_SHIFT 6 /* FLL_FRC_NCO */
1723#define WM8915_FLL_FRC_NCO_WIDTH 1 /* FLL_FRC_NCO */
1724#define WM8915_FLL_REFCLK_DIV_MASK 0x0018 /* FLL_REFCLK_DIV - [4:3] */
1725#define WM8915_FLL_REFCLK_DIV_SHIFT 3 /* FLL_REFCLK_DIV - [4:3] */
1726#define WM8915_FLL_REFCLK_DIV_WIDTH 2 /* FLL_REFCLK_DIV - [4:3] */
1727#define WM8915_FLL_REF_FREQ 0x0004 /* FLL_REF_FREQ */
1728#define WM8915_FLL_REF_FREQ_MASK 0x0004 /* FLL_REF_FREQ */
1729#define WM8915_FLL_REF_FREQ_SHIFT 2 /* FLL_REF_FREQ */
1730#define WM8915_FLL_REF_FREQ_WIDTH 1 /* FLL_REF_FREQ */
1731#define WM8915_FLL_REFCLK_SRC_MASK 0x0003 /* FLL_REFCLK_SRC - [1:0] */
1732#define WM8915_FLL_REFCLK_SRC_SHIFT 0 /* FLL_REFCLK_SRC - [1:0] */
1733#define WM8915_FLL_REFCLK_SRC_WIDTH 2 /* FLL_REFCLK_SRC - [1:0] */
1734
1735/*
1736 * R549 (0x225) - FLL Control (6)
1737 */
1738#define WM8915_FLL_REFCLK_SRC_STS_MASK 0x000C /* FLL_REFCLK_SRC_STS - [3:2] */
1739#define WM8915_FLL_REFCLK_SRC_STS_SHIFT 2 /* FLL_REFCLK_SRC_STS - [3:2] */
1740#define WM8915_FLL_REFCLK_SRC_STS_WIDTH 2 /* FLL_REFCLK_SRC_STS - [3:2] */
1741#define WM8915_FLL_SWITCH_CLK 0x0001 /* FLL_SWITCH_CLK */
1742#define WM8915_FLL_SWITCH_CLK_MASK 0x0001 /* FLL_SWITCH_CLK */
1743#define WM8915_FLL_SWITCH_CLK_SHIFT 0 /* FLL_SWITCH_CLK */
1744#define WM8915_FLL_SWITCH_CLK_WIDTH 1 /* FLL_SWITCH_CLK */
1745
1746/*
1747 * R550 (0x226) - FLL EFS 1
1748 */
1749#define WM8915_FLL_LAMBDA_MASK 0xFFFF /* FLL_LAMBDA - [15:0] */
1750#define WM8915_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */
1751#define WM8915_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */
1752
1753/*
1754 * R551 (0x227) - FLL EFS 2
1755 */
1756#define WM8915_FLL_LFSR_SEL_MASK 0x0006 /* FLL_LFSR_SEL - [2:1] */
1757#define WM8915_FLL_LFSR_SEL_SHIFT 1 /* FLL_LFSR_SEL - [2:1] */
1758#define WM8915_FLL_LFSR_SEL_WIDTH 2 /* FLL_LFSR_SEL - [2:1] */
1759#define WM8915_FLL_EFS_ENA 0x0001 /* FLL_EFS_ENA */
1760#define WM8915_FLL_EFS_ENA_MASK 0x0001 /* FLL_EFS_ENA */
1761#define WM8915_FLL_EFS_ENA_SHIFT 0 /* FLL_EFS_ENA */
1762#define WM8915_FLL_EFS_ENA_WIDTH 1 /* FLL_EFS_ENA */
1763
1764/*
1765 * R768 (0x300) - AIF1 Control
1766 */
1767#define WM8915_AIF1_TRI 0x0004 /* AIF1_TRI */
1768#define WM8915_AIF1_TRI_MASK 0x0004 /* AIF1_TRI */
1769#define WM8915_AIF1_TRI_SHIFT 2 /* AIF1_TRI */
1770#define WM8915_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
1771#define WM8915_AIF1_FMT_MASK 0x0003 /* AIF1_FMT - [1:0] */
1772#define WM8915_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [1:0] */
1773#define WM8915_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [1:0] */
1774
1775/*
1776 * R769 (0x301) - AIF1 BCLK
1777 */
1778#define WM8915_AIF1_BCLK_INV 0x0400 /* AIF1_BCLK_INV */
1779#define WM8915_AIF1_BCLK_INV_MASK 0x0400 /* AIF1_BCLK_INV */
1780#define WM8915_AIF1_BCLK_INV_SHIFT 10 /* AIF1_BCLK_INV */
1781#define WM8915_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
1782#define WM8915_AIF1_BCLK_FRC 0x0200 /* AIF1_BCLK_FRC */
1783#define WM8915_AIF1_BCLK_FRC_MASK 0x0200 /* AIF1_BCLK_FRC */
1784#define WM8915_AIF1_BCLK_FRC_SHIFT 9 /* AIF1_BCLK_FRC */
1785#define WM8915_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */
1786#define WM8915_AIF1_BCLK_MSTR 0x0100 /* AIF1_BCLK_MSTR */
1787#define WM8915_AIF1_BCLK_MSTR_MASK 0x0100 /* AIF1_BCLK_MSTR */
1788#define WM8915_AIF1_BCLK_MSTR_SHIFT 8 /* AIF1_BCLK_MSTR */
1789#define WM8915_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */
1790#define WM8915_AIF1_BCLK_DIV_MASK 0x000F /* AIF1_BCLK_DIV - [3:0] */
1791#define WM8915_AIF1_BCLK_DIV_SHIFT 0 /* AIF1_BCLK_DIV - [3:0] */
1792#define WM8915_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [3:0] */
1793
1794/*
1795 * R770 (0x302) - AIF1 TX LRCLK(1)
1796 */
1797#define WM8915_AIF1TX_RATE_MASK 0x07FF /* AIF1TX_RATE - [10:0] */
1798#define WM8915_AIF1TX_RATE_SHIFT 0 /* AIF1TX_RATE - [10:0] */
1799#define WM8915_AIF1TX_RATE_WIDTH 11 /* AIF1TX_RATE - [10:0] */
1800
1801/*
1802 * R771 (0x303) - AIF1 TX LRCLK(2)
1803 */
1804#define WM8915_AIF1TX_LRCLK_MODE 0x0008 /* AIF1TX_LRCLK_MODE */
1805#define WM8915_AIF1TX_LRCLK_MODE_MASK 0x0008 /* AIF1TX_LRCLK_MODE */
1806#define WM8915_AIF1TX_LRCLK_MODE_SHIFT 3 /* AIF1TX_LRCLK_MODE */
1807#define WM8915_AIF1TX_LRCLK_MODE_WIDTH 1 /* AIF1TX_LRCLK_MODE */
1808#define WM8915_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */
1809#define WM8915_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */
1810#define WM8915_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */
1811#define WM8915_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */
1812#define WM8915_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */
1813#define WM8915_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */
1814#define WM8915_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */
1815#define WM8915_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */
1816#define WM8915_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */
1817#define WM8915_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */
1818#define WM8915_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */
1819#define WM8915_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */
1820
1821/*
1822 * R772 (0x304) - AIF1 RX LRCLK(1)
1823 */
1824#define WM8915_AIF1RX_RATE_MASK 0x07FF /* AIF1RX_RATE - [10:0] */
1825#define WM8915_AIF1RX_RATE_SHIFT 0 /* AIF1RX_RATE - [10:0] */
1826#define WM8915_AIF1RX_RATE_WIDTH 11 /* AIF1RX_RATE - [10:0] */
1827
1828/*
1829 * R773 (0x305) - AIF1 RX LRCLK(2)
1830 */
1831#define WM8915_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */
1832#define WM8915_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */
1833#define WM8915_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */
1834#define WM8915_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */
1835#define WM8915_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */
1836#define WM8915_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */
1837#define WM8915_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */
1838#define WM8915_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */
1839#define WM8915_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */
1840#define WM8915_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */
1841#define WM8915_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */
1842#define WM8915_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */
1843
1844/*
1845 * R774 (0x306) - AIF1TX Data Configuration (1)
1846 */
1847#define WM8915_AIF1TX_WL_MASK 0xFF00 /* AIF1TX_WL - [15:8] */
1848#define WM8915_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [15:8] */
1849#define WM8915_AIF1TX_WL_WIDTH 8 /* AIF1TX_WL - [15:8] */
1850#define WM8915_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */
1851#define WM8915_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */
1852#define WM8915_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */
1853
1854/*
1855 * R775 (0x307) - AIF1TX Data Configuration (2)
1856 */
1857#define WM8915_AIF1TX_DAT_TRI 0x0001 /* AIF1TX_DAT_TRI */
1858#define WM8915_AIF1TX_DAT_TRI_MASK 0x0001 /* AIF1TX_DAT_TRI */
1859#define WM8915_AIF1TX_DAT_TRI_SHIFT 0 /* AIF1TX_DAT_TRI */
1860#define WM8915_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */
1861
1862/*
1863 * R776 (0x308) - AIF1RX Data Configuration
1864 */
1865#define WM8915_AIF1RX_WL_MASK 0xFF00 /* AIF1RX_WL - [15:8] */
1866#define WM8915_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [15:8] */
1867#define WM8915_AIF1RX_WL_WIDTH 8 /* AIF1RX_WL - [15:8] */
1868#define WM8915_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */
1869#define WM8915_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */
1870#define WM8915_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */
1871
1872/*
1873 * R777 (0x309) - AIF1TX Channel 0 Configuration
1874 */
1875#define WM8915_AIF1TX_CHAN0_DAT_INV 0x8000 /* AIF1TX_CHAN0_DAT_INV */
1876#define WM8915_AIF1TX_CHAN0_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN0_DAT_INV */
1877#define WM8915_AIF1TX_CHAN0_DAT_INV_SHIFT 15 /* AIF1TX_CHAN0_DAT_INV */
1878#define WM8915_AIF1TX_CHAN0_DAT_INV_WIDTH 1 /* AIF1TX_CHAN0_DAT_INV */
1879#define WM8915_AIF1TX_CHAN0_SPACING_MASK 0x7E00 /* AIF1TX_CHAN0_SPACING - [14:9] */
1880#define WM8915_AIF1TX_CHAN0_SPACING_SHIFT 9 /* AIF1TX_CHAN0_SPACING - [14:9] */
1881#define WM8915_AIF1TX_CHAN0_SPACING_WIDTH 6 /* AIF1TX_CHAN0_SPACING - [14:9] */
1882#define WM8915_AIF1TX_CHAN0_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN0_SLOTS - [8:6] */
1883#define WM8915_AIF1TX_CHAN0_SLOTS_SHIFT 6 /* AIF1TX_CHAN0_SLOTS - [8:6] */
1884#define WM8915_AIF1TX_CHAN0_SLOTS_WIDTH 3 /* AIF1TX_CHAN0_SLOTS - [8:6] */
1885#define WM8915_AIF1TX_CHAN0_START_SLOT_MASK 0x003F /* AIF1TX_CHAN0_START_SLOT - [5:0] */
1886#define WM8915_AIF1TX_CHAN0_START_SLOT_SHIFT 0 /* AIF1TX_CHAN0_START_SLOT - [5:0] */
1887#define WM8915_AIF1TX_CHAN0_START_SLOT_WIDTH 6 /* AIF1TX_CHAN0_START_SLOT - [5:0] */
1888
1889/*
1890 * R778 (0x30A) - AIF1TX Channel 1 Configuration
1891 */
1892#define WM8915_AIF1TX_CHAN1_DAT_INV 0x8000 /* AIF1TX_CHAN1_DAT_INV */
1893#define WM8915_AIF1TX_CHAN1_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN1_DAT_INV */
1894#define WM8915_AIF1TX_CHAN1_DAT_INV_SHIFT 15 /* AIF1TX_CHAN1_DAT_INV */
1895#define WM8915_AIF1TX_CHAN1_DAT_INV_WIDTH 1 /* AIF1TX_CHAN1_DAT_INV */
1896#define WM8915_AIF1TX_CHAN1_SPACING_MASK 0x7E00 /* AIF1TX_CHAN1_SPACING - [14:9] */
1897#define WM8915_AIF1TX_CHAN1_SPACING_SHIFT 9 /* AIF1TX_CHAN1_SPACING - [14:9] */
1898#define WM8915_AIF1TX_CHAN1_SPACING_WIDTH 6 /* AIF1TX_CHAN1_SPACING - [14:9] */
1899#define WM8915_AIF1TX_CHAN1_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN1_SLOTS - [8:6] */
1900#define WM8915_AIF1TX_CHAN1_SLOTS_SHIFT 6 /* AIF1TX_CHAN1_SLOTS - [8:6] */
1901#define WM8915_AIF1TX_CHAN1_SLOTS_WIDTH 3 /* AIF1TX_CHAN1_SLOTS - [8:6] */
1902#define WM8915_AIF1TX_CHAN1_START_SLOT_MASK 0x003F /* AIF1TX_CHAN1_START_SLOT - [5:0] */
1903#define WM8915_AIF1TX_CHAN1_START_SLOT_SHIFT 0 /* AIF1TX_CHAN1_START_SLOT - [5:0] */
1904#define WM8915_AIF1TX_CHAN1_START_SLOT_WIDTH 6 /* AIF1TX_CHAN1_START_SLOT - [5:0] */
1905
1906/*
1907 * R779 (0x30B) - AIF1TX Channel 2 Configuration
1908 */
1909#define WM8915_AIF1TX_CHAN2_DAT_INV 0x8000 /* AIF1TX_CHAN2_DAT_INV */
1910#define WM8915_AIF1TX_CHAN2_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN2_DAT_INV */
1911#define WM8915_AIF1TX_CHAN2_DAT_INV_SHIFT 15 /* AIF1TX_CHAN2_DAT_INV */
1912#define WM8915_AIF1TX_CHAN2_DAT_INV_WIDTH 1 /* AIF1TX_CHAN2_DAT_INV */
1913#define WM8915_AIF1TX_CHAN2_SPACING_MASK 0x7E00 /* AIF1TX_CHAN2_SPACING - [14:9] */
1914#define WM8915_AIF1TX_CHAN2_SPACING_SHIFT 9 /* AIF1TX_CHAN2_SPACING - [14:9] */
1915#define WM8915_AIF1TX_CHAN2_SPACING_WIDTH 6 /* AIF1TX_CHAN2_SPACING - [14:9] */
1916#define WM8915_AIF1TX_CHAN2_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN2_SLOTS - [8:6] */
1917#define WM8915_AIF1TX_CHAN2_SLOTS_SHIFT 6 /* AIF1TX_CHAN2_SLOTS - [8:6] */
1918#define WM8915_AIF1TX_CHAN2_SLOTS_WIDTH 3 /* AIF1TX_CHAN2_SLOTS - [8:6] */
1919#define WM8915_AIF1TX_CHAN2_START_SLOT_MASK 0x003F /* AIF1TX_CHAN2_START_SLOT - [5:0] */
1920#define WM8915_AIF1TX_CHAN2_START_SLOT_SHIFT 0 /* AIF1TX_CHAN2_START_SLOT - [5:0] */
1921#define WM8915_AIF1TX_CHAN2_START_SLOT_WIDTH 6 /* AIF1TX_CHAN2_START_SLOT - [5:0] */
1922
1923/*
1924 * R780 (0x30C) - AIF1TX Channel 3 Configuration
1925 */
1926#define WM8915_AIF1TX_CHAN3_DAT_INV 0x8000 /* AIF1TX_CHAN3_DAT_INV */
1927#define WM8915_AIF1TX_CHAN3_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN3_DAT_INV */
1928#define WM8915_AIF1TX_CHAN3_DAT_INV_SHIFT 15 /* AIF1TX_CHAN3_DAT_INV */
1929#define WM8915_AIF1TX_CHAN3_DAT_INV_WIDTH 1 /* AIF1TX_CHAN3_DAT_INV */
1930#define WM8915_AIF1TX_CHAN3_SPACING_MASK 0x7E00 /* AIF1TX_CHAN3_SPACING - [14:9] */
1931#define WM8915_AIF1TX_CHAN3_SPACING_SHIFT 9 /* AIF1TX_CHAN3_SPACING - [14:9] */
1932#define WM8915_AIF1TX_CHAN3_SPACING_WIDTH 6 /* AIF1TX_CHAN3_SPACING - [14:9] */
1933#define WM8915_AIF1TX_CHAN3_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN3_SLOTS - [8:6] */
1934#define WM8915_AIF1TX_CHAN3_SLOTS_SHIFT 6 /* AIF1TX_CHAN3_SLOTS - [8:6] */
1935#define WM8915_AIF1TX_CHAN3_SLOTS_WIDTH 3 /* AIF1TX_CHAN3_SLOTS - [8:6] */
1936#define WM8915_AIF1TX_CHAN3_START_SLOT_MASK 0x003F /* AIF1TX_CHAN3_START_SLOT - [5:0] */
1937#define WM8915_AIF1TX_CHAN3_START_SLOT_SHIFT 0 /* AIF1TX_CHAN3_START_SLOT - [5:0] */
1938#define WM8915_AIF1TX_CHAN3_START_SLOT_WIDTH 6 /* AIF1TX_CHAN3_START_SLOT - [5:0] */
1939
1940/*
1941 * R781 (0x30D) - AIF1TX Channel 4 Configuration
1942 */
1943#define WM8915_AIF1TX_CHAN4_DAT_INV 0x8000 /* AIF1TX_CHAN4_DAT_INV */
1944#define WM8915_AIF1TX_CHAN4_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN4_DAT_INV */
1945#define WM8915_AIF1TX_CHAN4_DAT_INV_SHIFT 15 /* AIF1TX_CHAN4_DAT_INV */
1946#define WM8915_AIF1TX_CHAN4_DAT_INV_WIDTH 1 /* AIF1TX_CHAN4_DAT_INV */
1947#define WM8915_AIF1TX_CHAN4_SPACING_MASK 0x7E00 /* AIF1TX_CHAN4_SPACING - [14:9] */
1948#define WM8915_AIF1TX_CHAN4_SPACING_SHIFT 9 /* AIF1TX_CHAN4_SPACING - [14:9] */
1949#define WM8915_AIF1TX_CHAN4_SPACING_WIDTH 6 /* AIF1TX_CHAN4_SPACING - [14:9] */
1950#define WM8915_AIF1TX_CHAN4_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN4_SLOTS - [8:6] */
1951#define WM8915_AIF1TX_CHAN4_SLOTS_SHIFT 6 /* AIF1TX_CHAN4_SLOTS - [8:6] */
1952#define WM8915_AIF1TX_CHAN4_SLOTS_WIDTH 3 /* AIF1TX_CHAN4_SLOTS - [8:6] */
1953#define WM8915_AIF1TX_CHAN4_START_SLOT_MASK 0x003F /* AIF1TX_CHAN4_START_SLOT - [5:0] */
1954#define WM8915_AIF1TX_CHAN4_START_SLOT_SHIFT 0 /* AIF1TX_CHAN4_START_SLOT - [5:0] */
1955#define WM8915_AIF1TX_CHAN4_START_SLOT_WIDTH 6 /* AIF1TX_CHAN4_START_SLOT - [5:0] */
1956
1957/*
1958 * R782 (0x30E) - AIF1TX Channel 5 Configuration
1959 */
1960#define WM8915_AIF1TX_CHAN5_DAT_INV 0x8000 /* AIF1TX_CHAN5_DAT_INV */
1961#define WM8915_AIF1TX_CHAN5_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN5_DAT_INV */
1962#define WM8915_AIF1TX_CHAN5_DAT_INV_SHIFT 15 /* AIF1TX_CHAN5_DAT_INV */
1963#define WM8915_AIF1TX_CHAN5_DAT_INV_WIDTH 1 /* AIF1TX_CHAN5_DAT_INV */
1964#define WM8915_AIF1TX_CHAN5_SPACING_MASK 0x7E00 /* AIF1TX_CHAN5_SPACING - [14:9] */
1965#define WM8915_AIF1TX_CHAN5_SPACING_SHIFT 9 /* AIF1TX_CHAN5_SPACING - [14:9] */
1966#define WM8915_AIF1TX_CHAN5_SPACING_WIDTH 6 /* AIF1TX_CHAN5_SPACING - [14:9] */
1967#define WM8915_AIF1TX_CHAN5_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN5_SLOTS - [8:6] */
1968#define WM8915_AIF1TX_CHAN5_SLOTS_SHIFT 6 /* AIF1TX_CHAN5_SLOTS - [8:6] */
1969#define WM8915_AIF1TX_CHAN5_SLOTS_WIDTH 3 /* AIF1TX_CHAN5_SLOTS - [8:6] */
1970#define WM8915_AIF1TX_CHAN5_START_SLOT_MASK 0x003F /* AIF1TX_CHAN5_START_SLOT - [5:0] */
1971#define WM8915_AIF1TX_CHAN5_START_SLOT_SHIFT 0 /* AIF1TX_CHAN5_START_SLOT - [5:0] */
1972#define WM8915_AIF1TX_CHAN5_START_SLOT_WIDTH 6 /* AIF1TX_CHAN5_START_SLOT - [5:0] */
1973
1974/*
1975 * R783 (0x30F) - AIF1RX Channel 0 Configuration
1976 */
1977#define WM8915_AIF1RX_CHAN0_DAT_INV 0x8000 /* AIF1RX_CHAN0_DAT_INV */
1978#define WM8915_AIF1RX_CHAN0_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN0_DAT_INV */
1979#define WM8915_AIF1RX_CHAN0_DAT_INV_SHIFT 15 /* AIF1RX_CHAN0_DAT_INV */
1980#define WM8915_AIF1RX_CHAN0_DAT_INV_WIDTH 1 /* AIF1RX_CHAN0_DAT_INV */
1981#define WM8915_AIF1RX_CHAN0_SPACING_MASK 0x7E00 /* AIF1RX_CHAN0_SPACING - [14:9] */
1982#define WM8915_AIF1RX_CHAN0_SPACING_SHIFT 9 /* AIF1RX_CHAN0_SPACING - [14:9] */
1983#define WM8915_AIF1RX_CHAN0_SPACING_WIDTH 6 /* AIF1RX_CHAN0_SPACING - [14:9] */
1984#define WM8915_AIF1RX_CHAN0_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN0_SLOTS - [8:6] */
1985#define WM8915_AIF1RX_CHAN0_SLOTS_SHIFT 6 /* AIF1RX_CHAN0_SLOTS - [8:6] */
1986#define WM8915_AIF1RX_CHAN0_SLOTS_WIDTH 3 /* AIF1RX_CHAN0_SLOTS - [8:6] */
1987#define WM8915_AIF1RX_CHAN0_START_SLOT_MASK 0x003F /* AIF1RX_CHAN0_START_SLOT - [5:0] */
1988#define WM8915_AIF1RX_CHAN0_START_SLOT_SHIFT 0 /* AIF1RX_CHAN0_START_SLOT - [5:0] */
1989#define WM8915_AIF1RX_CHAN0_START_SLOT_WIDTH 6 /* AIF1RX_CHAN0_START_SLOT - [5:0] */
1990
1991/*
1992 * R784 (0x310) - AIF1RX Channel 1 Configuration
1993 */
1994#define WM8915_AIF1RX_CHAN1_DAT_INV 0x8000 /* AIF1RX_CHAN1_DAT_INV */
1995#define WM8915_AIF1RX_CHAN1_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN1_DAT_INV */
1996#define WM8915_AIF1RX_CHAN1_DAT_INV_SHIFT 15 /* AIF1RX_CHAN1_DAT_INV */
1997#define WM8915_AIF1RX_CHAN1_DAT_INV_WIDTH 1 /* AIF1RX_CHAN1_DAT_INV */
1998#define WM8915_AIF1RX_CHAN1_SPACING_MASK 0x7E00 /* AIF1RX_CHAN1_SPACING - [14:9] */
1999#define WM8915_AIF1RX_CHAN1_SPACING_SHIFT 9 /* AIF1RX_CHAN1_SPACING - [14:9] */
2000#define WM8915_AIF1RX_CHAN1_SPACING_WIDTH 6 /* AIF1RX_CHAN1_SPACING - [14:9] */
2001#define WM8915_AIF1RX_CHAN1_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN1_SLOTS - [8:6] */
2002#define WM8915_AIF1RX_CHAN1_SLOTS_SHIFT 6 /* AIF1RX_CHAN1_SLOTS - [8:6] */
2003#define WM8915_AIF1RX_CHAN1_SLOTS_WIDTH 3 /* AIF1RX_CHAN1_SLOTS - [8:6] */
2004#define WM8915_AIF1RX_CHAN1_START_SLOT_MASK 0x003F /* AIF1RX_CHAN1_START_SLOT - [5:0] */
2005#define WM8915_AIF1RX_CHAN1_START_SLOT_SHIFT 0 /* AIF1RX_CHAN1_START_SLOT - [5:0] */
2006#define WM8915_AIF1RX_CHAN1_START_SLOT_WIDTH 6 /* AIF1RX_CHAN1_START_SLOT - [5:0] */
2007
2008/*
2009 * R785 (0x311) - AIF1RX Channel 2 Configuration
2010 */
2011#define WM8915_AIF1RX_CHAN2_DAT_INV 0x8000 /* AIF1RX_CHAN2_DAT_INV */
2012#define WM8915_AIF1RX_CHAN2_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN2_DAT_INV */
2013#define WM8915_AIF1RX_CHAN2_DAT_INV_SHIFT 15 /* AIF1RX_CHAN2_DAT_INV */
2014#define WM8915_AIF1RX_CHAN2_DAT_INV_WIDTH 1 /* AIF1RX_CHAN2_DAT_INV */
2015#define WM8915_AIF1RX_CHAN2_SPACING_MASK 0x7E00 /* AIF1RX_CHAN2_SPACING - [14:9] */
2016#define WM8915_AIF1RX_CHAN2_SPACING_SHIFT 9 /* AIF1RX_CHAN2_SPACING - [14:9] */
2017#define WM8915_AIF1RX_CHAN2_SPACING_WIDTH 6 /* AIF1RX_CHAN2_SPACING - [14:9] */
2018#define WM8915_AIF1RX_CHAN2_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN2_SLOTS - [8:6] */
2019#define WM8915_AIF1RX_CHAN2_SLOTS_SHIFT 6 /* AIF1RX_CHAN2_SLOTS - [8:6] */
2020#define WM8915_AIF1RX_CHAN2_SLOTS_WIDTH 3 /* AIF1RX_CHAN2_SLOTS - [8:6] */
2021#define WM8915_AIF1RX_CHAN2_START_SLOT_MASK 0x003F /* AIF1RX_CHAN2_START_SLOT - [5:0] */
2022#define WM8915_AIF1RX_CHAN2_START_SLOT_SHIFT 0 /* AIF1RX_CHAN2_START_SLOT - [5:0] */
2023#define WM8915_AIF1RX_CHAN2_START_SLOT_WIDTH 6 /* AIF1RX_CHAN2_START_SLOT - [5:0] */
2024
2025/*
2026 * R786 (0x312) - AIF1RX Channel 3 Configuration
2027 */
2028#define WM8915_AIF1RX_CHAN3_DAT_INV 0x8000 /* AIF1RX_CHAN3_DAT_INV */
2029#define WM8915_AIF1RX_CHAN3_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN3_DAT_INV */
2030#define WM8915_AIF1RX_CHAN3_DAT_INV_SHIFT 15 /* AIF1RX_CHAN3_DAT_INV */
2031#define WM8915_AIF1RX_CHAN3_DAT_INV_WIDTH 1 /* AIF1RX_CHAN3_DAT_INV */
2032#define WM8915_AIF1RX_CHAN3_SPACING_MASK 0x7E00 /* AIF1RX_CHAN3_SPACING - [14:9] */
2033#define WM8915_AIF1RX_CHAN3_SPACING_SHIFT 9 /* AIF1RX_CHAN3_SPACING - [14:9] */
2034#define WM8915_AIF1RX_CHAN3_SPACING_WIDTH 6 /* AIF1RX_CHAN3_SPACING - [14:9] */
2035#define WM8915_AIF1RX_CHAN3_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN3_SLOTS - [8:6] */
2036#define WM8915_AIF1RX_CHAN3_SLOTS_SHIFT 6 /* AIF1RX_CHAN3_SLOTS - [8:6] */
2037#define WM8915_AIF1RX_CHAN3_SLOTS_WIDTH 3 /* AIF1RX_CHAN3_SLOTS - [8:6] */
2038#define WM8915_AIF1RX_CHAN3_START_SLOT_MASK 0x003F /* AIF1RX_CHAN3_START_SLOT - [5:0] */
2039#define WM8915_AIF1RX_CHAN3_START_SLOT_SHIFT 0 /* AIF1RX_CHAN3_START_SLOT - [5:0] */
2040#define WM8915_AIF1RX_CHAN3_START_SLOT_WIDTH 6 /* AIF1RX_CHAN3_START_SLOT - [5:0] */
2041
2042/*
2043 * R787 (0x313) - AIF1RX Channel 4 Configuration
2044 */
2045#define WM8915_AIF1RX_CHAN4_DAT_INV 0x8000 /* AIF1RX_CHAN4_DAT_INV */
2046#define WM8915_AIF1RX_CHAN4_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN4_DAT_INV */
2047#define WM8915_AIF1RX_CHAN4_DAT_INV_SHIFT 15 /* AIF1RX_CHAN4_DAT_INV */
2048#define WM8915_AIF1RX_CHAN4_DAT_INV_WIDTH 1 /* AIF1RX_CHAN4_DAT_INV */
2049#define WM8915_AIF1RX_CHAN4_SPACING_MASK 0x7E00 /* AIF1RX_CHAN4_SPACING - [14:9] */
2050#define WM8915_AIF1RX_CHAN4_SPACING_SHIFT 9 /* AIF1RX_CHAN4_SPACING - [14:9] */
2051#define WM8915_AIF1RX_CHAN4_SPACING_WIDTH 6 /* AIF1RX_CHAN4_SPACING - [14:9] */
2052#define WM8915_AIF1RX_CHAN4_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN4_SLOTS - [8:6] */
2053#define WM8915_AIF1RX_CHAN4_SLOTS_SHIFT 6 /* AIF1RX_CHAN4_SLOTS - [8:6] */
2054#define WM8915_AIF1RX_CHAN4_SLOTS_WIDTH 3 /* AIF1RX_CHAN4_SLOTS - [8:6] */
2055#define WM8915_AIF1RX_CHAN4_START_SLOT_MASK 0x003F /* AIF1RX_CHAN4_START_SLOT - [5:0] */
2056#define WM8915_AIF1RX_CHAN4_START_SLOT_SHIFT 0 /* AIF1RX_CHAN4_START_SLOT - [5:0] */
2057#define WM8915_AIF1RX_CHAN4_START_SLOT_WIDTH 6 /* AIF1RX_CHAN4_START_SLOT - [5:0] */
2058
2059/*
2060 * R788 (0x314) - AIF1RX Channel 5 Configuration
2061 */
2062#define WM8915_AIF1RX_CHAN5_DAT_INV 0x8000 /* AIF1RX_CHAN5_DAT_INV */
2063#define WM8915_AIF1RX_CHAN5_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN5_DAT_INV */
2064#define WM8915_AIF1RX_CHAN5_DAT_INV_SHIFT 15 /* AIF1RX_CHAN5_DAT_INV */
2065#define WM8915_AIF1RX_CHAN5_DAT_INV_WIDTH 1 /* AIF1RX_CHAN5_DAT_INV */
2066#define WM8915_AIF1RX_CHAN5_SPACING_MASK 0x7E00 /* AIF1RX_CHAN5_SPACING - [14:9] */
2067#define WM8915_AIF1RX_CHAN5_SPACING_SHIFT 9 /* AIF1RX_CHAN5_SPACING - [14:9] */
2068#define WM8915_AIF1RX_CHAN5_SPACING_WIDTH 6 /* AIF1RX_CHAN5_SPACING - [14:9] */
2069#define WM8915_AIF1RX_CHAN5_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN5_SLOTS - [8:6] */
2070#define WM8915_AIF1RX_CHAN5_SLOTS_SHIFT 6 /* AIF1RX_CHAN5_SLOTS - [8:6] */
2071#define WM8915_AIF1RX_CHAN5_SLOTS_WIDTH 3 /* AIF1RX_CHAN5_SLOTS - [8:6] */
2072#define WM8915_AIF1RX_CHAN5_START_SLOT_MASK 0x003F /* AIF1RX_CHAN5_START_SLOT - [5:0] */
2073#define WM8915_AIF1RX_CHAN5_START_SLOT_SHIFT 0 /* AIF1RX_CHAN5_START_SLOT - [5:0] */
2074#define WM8915_AIF1RX_CHAN5_START_SLOT_WIDTH 6 /* AIF1RX_CHAN5_START_SLOT - [5:0] */
2075
2076/*
2077 * R789 (0x315) - AIF1RX Mono Configuration
2078 */
2079#define WM8915_AIF1RX_CHAN4_MONO_MODE 0x0004 /* AIF1RX_CHAN4_MONO_MODE */
2080#define WM8915_AIF1RX_CHAN4_MONO_MODE_MASK 0x0004 /* AIF1RX_CHAN4_MONO_MODE */
2081#define WM8915_AIF1RX_CHAN4_MONO_MODE_SHIFT 2 /* AIF1RX_CHAN4_MONO_MODE */
2082#define WM8915_AIF1RX_CHAN4_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN4_MONO_MODE */
2083#define WM8915_AIF1RX_CHAN2_MONO_MODE 0x0002 /* AIF1RX_CHAN2_MONO_MODE */
2084#define WM8915_AIF1RX_CHAN2_MONO_MODE_MASK 0x0002 /* AIF1RX_CHAN2_MONO_MODE */
2085#define WM8915_AIF1RX_CHAN2_MONO_MODE_SHIFT 1 /* AIF1RX_CHAN2_MONO_MODE */
2086#define WM8915_AIF1RX_CHAN2_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN2_MONO_MODE */
2087#define WM8915_AIF1RX_CHAN0_MONO_MODE 0x0001 /* AIF1RX_CHAN0_MONO_MODE */
2088#define WM8915_AIF1RX_CHAN0_MONO_MODE_MASK 0x0001 /* AIF1RX_CHAN0_MONO_MODE */
2089#define WM8915_AIF1RX_CHAN0_MONO_MODE_SHIFT 0 /* AIF1RX_CHAN0_MONO_MODE */
2090#define WM8915_AIF1RX_CHAN0_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN0_MONO_MODE */
2091
2092/*
2093 * R794 (0x31A) - AIF1TX Test
2094 */
2095#define WM8915_AIF1TX45_DITHER_ENA 0x0004 /* AIF1TX45_DITHER_ENA */
2096#define WM8915_AIF1TX45_DITHER_ENA_MASK 0x0004 /* AIF1TX45_DITHER_ENA */
2097#define WM8915_AIF1TX45_DITHER_ENA_SHIFT 2 /* AIF1TX45_DITHER_ENA */
2098#define WM8915_AIF1TX45_DITHER_ENA_WIDTH 1 /* AIF1TX45_DITHER_ENA */
2099#define WM8915_AIF1TX23_DITHER_ENA 0x0002 /* AIF1TX23_DITHER_ENA */
2100#define WM8915_AIF1TX23_DITHER_ENA_MASK 0x0002 /* AIF1TX23_DITHER_ENA */
2101#define WM8915_AIF1TX23_DITHER_ENA_SHIFT 1 /* AIF1TX23_DITHER_ENA */
2102#define WM8915_AIF1TX23_DITHER_ENA_WIDTH 1 /* AIF1TX23_DITHER_ENA */
2103#define WM8915_AIF1TX01_DITHER_ENA 0x0001 /* AIF1TX01_DITHER_ENA */
2104#define WM8915_AIF1TX01_DITHER_ENA_MASK 0x0001 /* AIF1TX01_DITHER_ENA */
2105#define WM8915_AIF1TX01_DITHER_ENA_SHIFT 0 /* AIF1TX01_DITHER_ENA */
2106#define WM8915_AIF1TX01_DITHER_ENA_WIDTH 1 /* AIF1TX01_DITHER_ENA */
2107
2108/*
2109 * R800 (0x320) - AIF2 Control
2110 */
2111#define WM8915_AIF2_TRI 0x0004 /* AIF2_TRI */
2112#define WM8915_AIF2_TRI_MASK 0x0004 /* AIF2_TRI */
2113#define WM8915_AIF2_TRI_SHIFT 2 /* AIF2_TRI */
2114#define WM8915_AIF2_TRI_WIDTH 1 /* AIF2_TRI */
2115#define WM8915_AIF2_FMT_MASK 0x0003 /* AIF2_FMT - [1:0] */
2116#define WM8915_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [1:0] */
2117#define WM8915_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [1:0] */
2118
2119/*
2120 * R801 (0x321) - AIF2 BCLK
2121 */
2122#define WM8915_AIF2_BCLK_INV 0x0400 /* AIF2_BCLK_INV */
2123#define WM8915_AIF2_BCLK_INV_MASK 0x0400 /* AIF2_BCLK_INV */
2124#define WM8915_AIF2_BCLK_INV_SHIFT 10 /* AIF2_BCLK_INV */
2125#define WM8915_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */
2126#define WM8915_AIF2_BCLK_FRC 0x0200 /* AIF2_BCLK_FRC */
2127#define WM8915_AIF2_BCLK_FRC_MASK 0x0200 /* AIF2_BCLK_FRC */
2128#define WM8915_AIF2_BCLK_FRC_SHIFT 9 /* AIF2_BCLK_FRC */
2129#define WM8915_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */
2130#define WM8915_AIF2_BCLK_MSTR 0x0100 /* AIF2_BCLK_MSTR */
2131#define WM8915_AIF2_BCLK_MSTR_MASK 0x0100 /* AIF2_BCLK_MSTR */
2132#define WM8915_AIF2_BCLK_MSTR_SHIFT 8 /* AIF2_BCLK_MSTR */
2133#define WM8915_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */
2134#define WM8915_AIF2_BCLK_DIV_MASK 0x000F /* AIF2_BCLK_DIV - [3:0] */
2135#define WM8915_AIF2_BCLK_DIV_SHIFT 0 /* AIF2_BCLK_DIV - [3:0] */
2136#define WM8915_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [3:0] */
2137
2138/*
2139 * R802 (0x322) - AIF2 TX LRCLK(1)
2140 */
2141#define WM8915_AIF2TX_RATE_MASK 0x07FF /* AIF2TX_RATE - [10:0] */
2142#define WM8915_AIF2TX_RATE_SHIFT 0 /* AIF2TX_RATE - [10:0] */
2143#define WM8915_AIF2TX_RATE_WIDTH 11 /* AIF2TX_RATE - [10:0] */
2144
2145/*
2146 * R803 (0x323) - AIF2 TX LRCLK(2)
2147 */
2148#define WM8915_AIF2TX_LRCLK_MODE 0x0008 /* AIF2TX_LRCLK_MODE */
2149#define WM8915_AIF2TX_LRCLK_MODE_MASK 0x0008 /* AIF2TX_LRCLK_MODE */
2150#define WM8915_AIF2TX_LRCLK_MODE_SHIFT 3 /* AIF2TX_LRCLK_MODE */
2151#define WM8915_AIF2TX_LRCLK_MODE_WIDTH 1 /* AIF2TX_LRCLK_MODE */
2152#define WM8915_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */
2153#define WM8915_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */
2154#define WM8915_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */
2155#define WM8915_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */
2156#define WM8915_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */
2157#define WM8915_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */
2158#define WM8915_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */
2159#define WM8915_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */
2160#define WM8915_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */
2161#define WM8915_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */
2162#define WM8915_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */
2163#define WM8915_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */
2164
2165/*
2166 * R804 (0x324) - AIF2 RX LRCLK(1)
2167 */
2168#define WM8915_AIF2RX_RATE_MASK 0x07FF /* AIF2RX_RATE - [10:0] */
2169#define WM8915_AIF2RX_RATE_SHIFT 0 /* AIF2RX_RATE - [10:0] */
2170#define WM8915_AIF2RX_RATE_WIDTH 11 /* AIF2RX_RATE - [10:0] */
2171
2172/*
2173 * R805 (0x325) - AIF2 RX LRCLK(2)
2174 */
2175#define WM8915_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */
2176#define WM8915_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */
2177#define WM8915_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */
2178#define WM8915_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */
2179#define WM8915_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */
2180#define WM8915_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */
2181#define WM8915_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */
2182#define WM8915_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */
2183#define WM8915_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */
2184#define WM8915_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */
2185#define WM8915_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */
2186#define WM8915_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */
2187
2188/*
2189 * R806 (0x326) - AIF2TX Data Configuration (1)
2190 */
2191#define WM8915_AIF2TX_WL_MASK 0xFF00 /* AIF2TX_WL - [15:8] */
2192#define WM8915_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [15:8] */
2193#define WM8915_AIF2TX_WL_WIDTH 8 /* AIF2TX_WL - [15:8] */
2194#define WM8915_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */
2195#define WM8915_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */
2196#define WM8915_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */
2197
2198/*
2199 * R807 (0x327) - AIF2TX Data Configuration (2)
2200 */
2201#define WM8915_AIF2TX_DAT_TRI 0x0001 /* AIF2TX_DAT_TRI */
2202#define WM8915_AIF2TX_DAT_TRI_MASK 0x0001 /* AIF2TX_DAT_TRI */
2203#define WM8915_AIF2TX_DAT_TRI_SHIFT 0 /* AIF2TX_DAT_TRI */
2204#define WM8915_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */
2205
2206/*
2207 * R808 (0x328) - AIF2RX Data Configuration
2208 */
2209#define WM8915_AIF2RX_WL_MASK 0xFF00 /* AIF2RX_WL - [15:8] */
2210#define WM8915_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [15:8] */
2211#define WM8915_AIF2RX_WL_WIDTH 8 /* AIF2RX_WL - [15:8] */
2212#define WM8915_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */
2213#define WM8915_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */
2214#define WM8915_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */
2215
2216/*
2217 * R809 (0x329) - AIF2TX Channel 0 Configuration
2218 */
2219#define WM8915_AIF2TX_CHAN0_DAT_INV 0x8000 /* AIF2TX_CHAN0_DAT_INV */
2220#define WM8915_AIF2TX_CHAN0_DAT_INV_MASK 0x8000 /* AIF2TX_CHAN0_DAT_INV */
2221#define WM8915_AIF2TX_CHAN0_DAT_INV_SHIFT 15 /* AIF2TX_CHAN0_DAT_INV */
2222#define WM8915_AIF2TX_CHAN0_DAT_INV_WIDTH 1 /* AIF2TX_CHAN0_DAT_INV */
2223#define WM8915_AIF2TX_CHAN0_SPACING_MASK 0x7E00 /* AIF2TX_CHAN0_SPACING - [14:9] */
2224#define WM8915_AIF2TX_CHAN0_SPACING_SHIFT 9 /* AIF2TX_CHAN0_SPACING - [14:9] */
2225#define WM8915_AIF2TX_CHAN0_SPACING_WIDTH 6 /* AIF2TX_CHAN0_SPACING - [14:9] */
2226#define WM8915_AIF2TX_CHAN0_SLOTS_MASK 0x01C0 /* AIF2TX_CHAN0_SLOTS - [8:6] */
2227#define WM8915_AIF2TX_CHAN0_SLOTS_SHIFT 6 /* AIF2TX_CHAN0_SLOTS - [8:6] */
2228#define WM8915_AIF2TX_CHAN0_SLOTS_WIDTH 3 /* AIF2TX_CHAN0_SLOTS - [8:6] */
2229#define WM8915_AIF2TX_CHAN0_START_SLOT_MASK 0x003F /* AIF2TX_CHAN0_START_SLOT - [5:0] */
2230#define WM8915_AIF2TX_CHAN0_START_SLOT_SHIFT 0 /* AIF2TX_CHAN0_START_SLOT - [5:0] */
2231#define WM8915_AIF2TX_CHAN0_START_SLOT_WIDTH 6 /* AIF2TX_CHAN0_START_SLOT - [5:0] */
2232
2233/*
2234 * R810 (0x32A) - AIF2TX Channel 1 Configuration
2235 */
2236#define WM8915_AIF2TX_CHAN1_DAT_INV 0x8000 /* AIF2TX_CHAN1_DAT_INV */
2237#define WM8915_AIF2TX_CHAN1_DAT_INV_MASK 0x8000 /* AIF2TX_CHAN1_DAT_INV */
2238#define WM8915_AIF2TX_CHAN1_DAT_INV_SHIFT 15 /* AIF2TX_CHAN1_DAT_INV */
2239#define WM8915_AIF2TX_CHAN1_DAT_INV_WIDTH 1 /* AIF2TX_CHAN1_DAT_INV */
2240#define WM8915_AIF2TX_CHAN1_SPACING_MASK 0x7E00 /* AIF2TX_CHAN1_SPACING - [14:9] */
2241#define WM8915_AIF2TX_CHAN1_SPACING_SHIFT 9 /* AIF2TX_CHAN1_SPACING - [14:9] */
2242#define WM8915_AIF2TX_CHAN1_SPACING_WIDTH 6 /* AIF2TX_CHAN1_SPACING - [14:9] */
2243#define WM8915_AIF2TX_CHAN1_SLOTS_MASK 0x01C0 /* AIF2TX_CHAN1_SLOTS - [8:6] */
2244#define WM8915_AIF2TX_CHAN1_SLOTS_SHIFT 6 /* AIF2TX_CHAN1_SLOTS - [8:6] */
2245#define WM8915_AIF2TX_CHAN1_SLOTS_WIDTH 3 /* AIF2TX_CHAN1_SLOTS - [8:6] */
2246#define WM8915_AIF2TX_CHAN1_START_SLOT_MASK 0x003F /* AIF2TX_CHAN1_START_SLOT - [5:0] */
2247#define WM8915_AIF2TX_CHAN1_START_SLOT_SHIFT 0 /* AIF2TX_CHAN1_START_SLOT - [5:0] */
2248#define WM8915_AIF2TX_CHAN1_START_SLOT_WIDTH 6 /* AIF2TX_CHAN1_START_SLOT - [5:0] */
2249
2250/*
2251 * R811 (0x32B) - AIF2RX Channel 0 Configuration
2252 */
2253#define WM8915_AIF2RX_CHAN0_DAT_INV 0x8000 /* AIF2RX_CHAN0_DAT_INV */
2254#define WM8915_AIF2RX_CHAN0_DAT_INV_MASK 0x8000 /* AIF2RX_CHAN0_DAT_INV */
2255#define WM8915_AIF2RX_CHAN0_DAT_INV_SHIFT 15 /* AIF2RX_CHAN0_DAT_INV */
2256#define WM8915_AIF2RX_CHAN0_DAT_INV_WIDTH 1 /* AIF2RX_CHAN0_DAT_INV */
2257#define WM8915_AIF2RX_CHAN0_SPACING_MASK 0x7E00 /* AIF2RX_CHAN0_SPACING - [14:9] */
2258#define WM8915_AIF2RX_CHAN0_SPACING_SHIFT 9 /* AIF2RX_CHAN0_SPACING - [14:9] */
2259#define WM8915_AIF2RX_CHAN0_SPACING_WIDTH 6 /* AIF2RX_CHAN0_SPACING - [14:9] */
2260#define WM8915_AIF2RX_CHAN0_SLOTS_MASK 0x01C0 /* AIF2RX_CHAN0_SLOTS - [8:6] */
2261#define WM8915_AIF2RX_CHAN0_SLOTS_SHIFT 6 /* AIF2RX_CHAN0_SLOTS - [8:6] */
2262#define WM8915_AIF2RX_CHAN0_SLOTS_WIDTH 3 /* AIF2RX_CHAN0_SLOTS - [8:6] */
2263#define WM8915_AIF2RX_CHAN0_START_SLOT_MASK 0x003F /* AIF2RX_CHAN0_START_SLOT - [5:0] */
2264#define WM8915_AIF2RX_CHAN0_START_SLOT_SHIFT 0 /* AIF2RX_CHAN0_START_SLOT - [5:0] */
2265#define WM8915_AIF2RX_CHAN0_START_SLOT_WIDTH 6 /* AIF2RX_CHAN0_START_SLOT - [5:0] */
2266
2267/*
2268 * R812 (0x32C) - AIF2RX Channel 1 Configuration
2269 */
2270#define WM8915_AIF2RX_CHAN1_DAT_INV 0x8000 /* AIF2RX_CHAN1_DAT_INV */
2271#define WM8915_AIF2RX_CHAN1_DAT_INV_MASK 0x8000 /* AIF2RX_CHAN1_DAT_INV */
2272#define WM8915_AIF2RX_CHAN1_DAT_INV_SHIFT 15 /* AIF2RX_CHAN1_DAT_INV */
2273#define WM8915_AIF2RX_CHAN1_DAT_INV_WIDTH 1 /* AIF2RX_CHAN1_DAT_INV */
2274#define WM8915_AIF2RX_CHAN1_SPACING_MASK 0x7E00 /* AIF2RX_CHAN1_SPACING - [14:9] */
2275#define WM8915_AIF2RX_CHAN1_SPACING_SHIFT 9 /* AIF2RX_CHAN1_SPACING - [14:9] */
2276#define WM8915_AIF2RX_CHAN1_SPACING_WIDTH 6 /* AIF2RX_CHAN1_SPACING - [14:9] */
2277#define WM8915_AIF2RX_CHAN1_SLOTS_MASK 0x01C0 /* AIF2RX_CHAN1_SLOTS - [8:6] */
2278#define WM8915_AIF2RX_CHAN1_SLOTS_SHIFT 6 /* AIF2RX_CHAN1_SLOTS - [8:6] */
2279#define WM8915_AIF2RX_CHAN1_SLOTS_WIDTH 3 /* AIF2RX_CHAN1_SLOTS - [8:6] */
2280#define WM8915_AIF2RX_CHAN1_START_SLOT_MASK 0x003F /* AIF2RX_CHAN1_START_SLOT - [5:0] */
2281#define WM8915_AIF2RX_CHAN1_START_SLOT_SHIFT 0 /* AIF2RX_CHAN1_START_SLOT - [5:0] */
2282#define WM8915_AIF2RX_CHAN1_START_SLOT_WIDTH 6 /* AIF2RX_CHAN1_START_SLOT - [5:0] */
2283
2284/*
2285 * R813 (0x32D) - AIF2RX Mono Configuration
2286 */
2287#define WM8915_AIF2RX_CHAN0_MONO_MODE 0x0001 /* AIF2RX_CHAN0_MONO_MODE */
2288#define WM8915_AIF2RX_CHAN0_MONO_MODE_MASK 0x0001 /* AIF2RX_CHAN0_MONO_MODE */
2289#define WM8915_AIF2RX_CHAN0_MONO_MODE_SHIFT 0 /* AIF2RX_CHAN0_MONO_MODE */
2290#define WM8915_AIF2RX_CHAN0_MONO_MODE_WIDTH 1 /* AIF2RX_CHAN0_MONO_MODE */
2291
2292/*
2293 * R815 (0x32F) - AIF2TX Test
2294 */
2295#define WM8915_AIF2TX_DITHER_ENA 0x0001 /* AIF2TX_DITHER_ENA */
2296#define WM8915_AIF2TX_DITHER_ENA_MASK 0x0001 /* AIF2TX_DITHER_ENA */
2297#define WM8915_AIF2TX_DITHER_ENA_SHIFT 0 /* AIF2TX_DITHER_ENA */
2298#define WM8915_AIF2TX_DITHER_ENA_WIDTH 1 /* AIF2TX_DITHER_ENA */
2299
2300/*
2301 * R1024 (0x400) - DSP1 TX Left Volume
2302 */
2303#define WM8915_DSP1TX_VU 0x0100 /* DSP1TX_VU */
2304#define WM8915_DSP1TX_VU_MASK 0x0100 /* DSP1TX_VU */
2305#define WM8915_DSP1TX_VU_SHIFT 8 /* DSP1TX_VU */
2306#define WM8915_DSP1TX_VU_WIDTH 1 /* DSP1TX_VU */
2307#define WM8915_DSP1TXL_VOL_MASK 0x00FF /* DSP1TXL_VOL - [7:0] */
2308#define WM8915_DSP1TXL_VOL_SHIFT 0 /* DSP1TXL_VOL - [7:0] */
2309#define WM8915_DSP1TXL_VOL_WIDTH 8 /* DSP1TXL_VOL - [7:0] */
2310
2311/*
2312 * R1025 (0x401) - DSP1 TX Right Volume
2313 */
2314#define WM8915_DSP1TX_VU 0x0100 /* DSP1TX_VU */
2315#define WM8915_DSP1TX_VU_MASK 0x0100 /* DSP1TX_VU */
2316#define WM8915_DSP1TX_VU_SHIFT 8 /* DSP1TX_VU */
2317#define WM8915_DSP1TX_VU_WIDTH 1 /* DSP1TX_VU */
2318#define WM8915_DSP1TXR_VOL_MASK 0x00FF /* DSP1TXR_VOL - [7:0] */
2319#define WM8915_DSP1TXR_VOL_SHIFT 0 /* DSP1TXR_VOL - [7:0] */
2320#define WM8915_DSP1TXR_VOL_WIDTH 8 /* DSP1TXR_VOL - [7:0] */
2321
2322/*
2323 * R1026 (0x402) - DSP1 RX Left Volume
2324 */
2325#define WM8915_DSP1RX_VU 0x0100 /* DSP1RX_VU */
2326#define WM8915_DSP1RX_VU_MASK 0x0100 /* DSP1RX_VU */
2327#define WM8915_DSP1RX_VU_SHIFT 8 /* DSP1RX_VU */
2328#define WM8915_DSP1RX_VU_WIDTH 1 /* DSP1RX_VU */
2329#define WM8915_DSP1RXL_VOL_MASK 0x00FF /* DSP1RXL_VOL - [7:0] */
2330#define WM8915_DSP1RXL_VOL_SHIFT 0 /* DSP1RXL_VOL - [7:0] */
2331#define WM8915_DSP1RXL_VOL_WIDTH 8 /* DSP1RXL_VOL - [7:0] */
2332
2333/*
2334 * R1027 (0x403) - DSP1 RX Right Volume
2335 */
2336#define WM8915_DSP1RX_VU 0x0100 /* DSP1RX_VU */
2337#define WM8915_DSP1RX_VU_MASK 0x0100 /* DSP1RX_VU */
2338#define WM8915_DSP1RX_VU_SHIFT 8 /* DSP1RX_VU */
2339#define WM8915_DSP1RX_VU_WIDTH 1 /* DSP1RX_VU */
2340#define WM8915_DSP1RXR_VOL_MASK 0x00FF /* DSP1RXR_VOL - [7:0] */
2341#define WM8915_DSP1RXR_VOL_SHIFT 0 /* DSP1RXR_VOL - [7:0] */
2342#define WM8915_DSP1RXR_VOL_WIDTH 8 /* DSP1RXR_VOL - [7:0] */
2343
2344/*
2345 * R1040 (0x410) - DSP1 TX Filters
2346 */
2347#define WM8915_DSP1TX_NF 0x2000 /* DSP1TX_NF */
2348#define WM8915_DSP1TX_NF_MASK 0x2000 /* DSP1TX_NF */
2349#define WM8915_DSP1TX_NF_SHIFT 13 /* DSP1TX_NF */
2350#define WM8915_DSP1TX_NF_WIDTH 1 /* DSP1TX_NF */
2351#define WM8915_DSP1TXL_HPF 0x1000 /* DSP1TXL_HPF */
2352#define WM8915_DSP1TXL_HPF_MASK 0x1000 /* DSP1TXL_HPF */
2353#define WM8915_DSP1TXL_HPF_SHIFT 12 /* DSP1TXL_HPF */
2354#define WM8915_DSP1TXL_HPF_WIDTH 1 /* DSP1TXL_HPF */
2355#define WM8915_DSP1TXR_HPF 0x0800 /* DSP1TXR_HPF */
2356#define WM8915_DSP1TXR_HPF_MASK 0x0800 /* DSP1TXR_HPF */
2357#define WM8915_DSP1TXR_HPF_SHIFT 11 /* DSP1TXR_HPF */
2358#define WM8915_DSP1TXR_HPF_WIDTH 1 /* DSP1TXR_HPF */
2359#define WM8915_DSP1TX_HPF_MODE_MASK 0x0018 /* DSP1TX_HPF_MODE - [4:3] */
2360#define WM8915_DSP1TX_HPF_MODE_SHIFT 3 /* DSP1TX_HPF_MODE - [4:3] */
2361#define WM8915_DSP1TX_HPF_MODE_WIDTH 2 /* DSP1TX_HPF_MODE - [4:3] */
2362#define WM8915_DSP1TX_HPF_CUT_MASK 0x0007 /* DSP1TX_HPF_CUT - [2:0] */
2363#define WM8915_DSP1TX_HPF_CUT_SHIFT 0 /* DSP1TX_HPF_CUT - [2:0] */
2364#define WM8915_DSP1TX_HPF_CUT_WIDTH 3 /* DSP1TX_HPF_CUT - [2:0] */
2365
2366/*
2367 * R1056 (0x420) - DSP1 RX Filters (1)
2368 */
2369#define WM8915_DSP1RX_MUTE 0x0200 /* DSP1RX_MUTE */
2370#define WM8915_DSP1RX_MUTE_MASK 0x0200 /* DSP1RX_MUTE */
2371#define WM8915_DSP1RX_MUTE_SHIFT 9 /* DSP1RX_MUTE */
2372#define WM8915_DSP1RX_MUTE_WIDTH 1 /* DSP1RX_MUTE */
2373#define WM8915_DSP1RX_MONO 0x0080 /* DSP1RX_MONO */
2374#define WM8915_DSP1RX_MONO_MASK 0x0080 /* DSP1RX_MONO */
2375#define WM8915_DSP1RX_MONO_SHIFT 7 /* DSP1RX_MONO */
2376#define WM8915_DSP1RX_MONO_WIDTH 1 /* DSP1RX_MONO */
2377#define WM8915_DSP1RX_MUTERATE 0x0020 /* DSP1RX_MUTERATE */
2378#define WM8915_DSP1RX_MUTERATE_MASK 0x0020 /* DSP1RX_MUTERATE */
2379#define WM8915_DSP1RX_MUTERATE_SHIFT 5 /* DSP1RX_MUTERATE */
2380#define WM8915_DSP1RX_MUTERATE_WIDTH 1 /* DSP1RX_MUTERATE */
2381#define WM8915_DSP1RX_UNMUTE_RAMP 0x0010 /* DSP1RX_UNMUTE_RAMP */
2382#define WM8915_DSP1RX_UNMUTE_RAMP_MASK 0x0010 /* DSP1RX_UNMUTE_RAMP */
2383#define WM8915_DSP1RX_UNMUTE_RAMP_SHIFT 4 /* DSP1RX_UNMUTE_RAMP */
2384#define WM8915_DSP1RX_UNMUTE_RAMP_WIDTH 1 /* DSP1RX_UNMUTE_RAMP */
2385
2386/*
2387 * R1057 (0x421) - DSP1 RX Filters (2)
2388 */
2389#define WM8915_DSP1RX_3D_GAIN_MASK 0x3E00 /* DSP1RX_3D_GAIN - [13:9] */
2390#define WM8915_DSP1RX_3D_GAIN_SHIFT 9 /* DSP1RX_3D_GAIN - [13:9] */
2391#define WM8915_DSP1RX_3D_GAIN_WIDTH 5 /* DSP1RX_3D_GAIN - [13:9] */
2392#define WM8915_DSP1RX_3D_ENA 0x0100 /* DSP1RX_3D_ENA */
2393#define WM8915_DSP1RX_3D_ENA_MASK 0x0100 /* DSP1RX_3D_ENA */
2394#define WM8915_DSP1RX_3D_ENA_SHIFT 8 /* DSP1RX_3D_ENA */
2395#define WM8915_DSP1RX_3D_ENA_WIDTH 1 /* DSP1RX_3D_ENA */
2396
2397/*
2398 * R1088 (0x440) - DSP1 DRC (1)
2399 */
2400#define WM8915_DSP1DRC_SIG_DET_RMS_MASK 0xF800 /* DSP1DRC_SIG_DET_RMS - [15:11] */
2401#define WM8915_DSP1DRC_SIG_DET_RMS_SHIFT 11 /* DSP1DRC_SIG_DET_RMS - [15:11] */
2402#define WM8915_DSP1DRC_SIG_DET_RMS_WIDTH 5 /* DSP1DRC_SIG_DET_RMS - [15:11] */
2403#define WM8915_DSP1DRC_SIG_DET_PK_MASK 0x0600 /* DSP1DRC_SIG_DET_PK - [10:9] */
2404#define WM8915_DSP1DRC_SIG_DET_PK_SHIFT 9 /* DSP1DRC_SIG_DET_PK - [10:9] */
2405#define WM8915_DSP1DRC_SIG_DET_PK_WIDTH 2 /* DSP1DRC_SIG_DET_PK - [10:9] */
2406#define WM8915_DSP1DRC_NG_ENA 0x0100 /* DSP1DRC_NG_ENA */
2407#define WM8915_DSP1DRC_NG_ENA_MASK 0x0100 /* DSP1DRC_NG_ENA */
2408#define WM8915_DSP1DRC_NG_ENA_SHIFT 8 /* DSP1DRC_NG_ENA */
2409#define WM8915_DSP1DRC_NG_ENA_WIDTH 1 /* DSP1DRC_NG_ENA */
2410#define WM8915_DSP1DRC_SIG_DET_MODE 0x0080 /* DSP1DRC_SIG_DET_MODE */
2411#define WM8915_DSP1DRC_SIG_DET_MODE_MASK 0x0080 /* DSP1DRC_SIG_DET_MODE */
2412#define WM8915_DSP1DRC_SIG_DET_MODE_SHIFT 7 /* DSP1DRC_SIG_DET_MODE */
2413#define WM8915_DSP1DRC_SIG_DET_MODE_WIDTH 1 /* DSP1DRC_SIG_DET_MODE */
2414#define WM8915_DSP1DRC_SIG_DET 0x0040 /* DSP1DRC_SIG_DET */
2415#define WM8915_DSP1DRC_SIG_DET_MASK 0x0040 /* DSP1DRC_SIG_DET */
2416#define WM8915_DSP1DRC_SIG_DET_SHIFT 6 /* DSP1DRC_SIG_DET */
2417#define WM8915_DSP1DRC_SIG_DET_WIDTH 1 /* DSP1DRC_SIG_DET */
2418#define WM8915_DSP1DRC_KNEE2_OP_ENA 0x0020 /* DSP1DRC_KNEE2_OP_ENA */
2419#define WM8915_DSP1DRC_KNEE2_OP_ENA_MASK 0x0020 /* DSP1DRC_KNEE2_OP_ENA */
2420#define WM8915_DSP1DRC_KNEE2_OP_ENA_SHIFT 5 /* DSP1DRC_KNEE2_OP_ENA */
2421#define WM8915_DSP1DRC_KNEE2_OP_ENA_WIDTH 1 /* DSP1DRC_KNEE2_OP_ENA */
2422#define WM8915_DSP1DRC_QR 0x0010 /* DSP1DRC_QR */
2423#define WM8915_DSP1DRC_QR_MASK 0x0010 /* DSP1DRC_QR */
2424#define WM8915_DSP1DRC_QR_SHIFT 4 /* DSP1DRC_QR */
2425#define WM8915_DSP1DRC_QR_WIDTH 1 /* DSP1DRC_QR */
2426#define WM8915_DSP1DRC_ANTICLIP 0x0008 /* DSP1DRC_ANTICLIP */
2427#define WM8915_DSP1DRC_ANTICLIP_MASK 0x0008 /* DSP1DRC_ANTICLIP */
2428#define WM8915_DSP1DRC_ANTICLIP_SHIFT 3 /* DSP1DRC_ANTICLIP */
2429#define WM8915_DSP1DRC_ANTICLIP_WIDTH 1 /* DSP1DRC_ANTICLIP */
2430#define WM8915_DSP1RX_DRC_ENA 0x0004 /* DSP1RX_DRC_ENA */
2431#define WM8915_DSP1RX_DRC_ENA_MASK 0x0004 /* DSP1RX_DRC_ENA */
2432#define WM8915_DSP1RX_DRC_ENA_SHIFT 2 /* DSP1RX_DRC_ENA */
2433#define WM8915_DSP1RX_DRC_ENA_WIDTH 1 /* DSP1RX_DRC_ENA */
2434#define WM8915_DSP1TXL_DRC_ENA 0x0002 /* DSP1TXL_DRC_ENA */
2435#define WM8915_DSP1TXL_DRC_ENA_MASK 0x0002 /* DSP1TXL_DRC_ENA */
2436#define WM8915_DSP1TXL_DRC_ENA_SHIFT 1 /* DSP1TXL_DRC_ENA */
2437#define WM8915_DSP1TXL_DRC_ENA_WIDTH 1 /* DSP1TXL_DRC_ENA */
2438#define WM8915_DSP1TXR_DRC_ENA 0x0001 /* DSP1TXR_DRC_ENA */
2439#define WM8915_DSP1TXR_DRC_ENA_MASK 0x0001 /* DSP1TXR_DRC_ENA */
2440#define WM8915_DSP1TXR_DRC_ENA_SHIFT 0 /* DSP1TXR_DRC_ENA */
2441#define WM8915_DSP1TXR_DRC_ENA_WIDTH 1 /* DSP1TXR_DRC_ENA */
2442
2443/*
2444 * R1089 (0x441) - DSP1 DRC (2)
2445 */
2446#define WM8915_DSP1DRC_ATK_MASK 0x1E00 /* DSP1DRC_ATK - [12:9] */
2447#define WM8915_DSP1DRC_ATK_SHIFT 9 /* DSP1DRC_ATK - [12:9] */
2448#define WM8915_DSP1DRC_ATK_WIDTH 4 /* DSP1DRC_ATK - [12:9] */
2449#define WM8915_DSP1DRC_DCY_MASK 0x01E0 /* DSP1DRC_DCY - [8:5] */
2450#define WM8915_DSP1DRC_DCY_SHIFT 5 /* DSP1DRC_DCY - [8:5] */
2451#define WM8915_DSP1DRC_DCY_WIDTH 4 /* DSP1DRC_DCY - [8:5] */
2452#define WM8915_DSP1DRC_MINGAIN_MASK 0x001C /* DSP1DRC_MINGAIN - [4:2] */
2453#define WM8915_DSP1DRC_MINGAIN_SHIFT 2 /* DSP1DRC_MINGAIN - [4:2] */
2454#define WM8915_DSP1DRC_MINGAIN_WIDTH 3 /* DSP1DRC_MINGAIN - [4:2] */
2455#define WM8915_DSP1DRC_MAXGAIN_MASK 0x0003 /* DSP1DRC_MAXGAIN - [1:0] */
2456#define WM8915_DSP1DRC_MAXGAIN_SHIFT 0 /* DSP1DRC_MAXGAIN - [1:0] */
2457#define WM8915_DSP1DRC_MAXGAIN_WIDTH 2 /* DSP1DRC_MAXGAIN - [1:0] */
2458
2459/*
2460 * R1090 (0x442) - DSP1 DRC (3)
2461 */
2462#define WM8915_DSP1DRC_NG_MINGAIN_MASK 0xF000 /* DSP1DRC_NG_MINGAIN - [15:12] */
2463#define WM8915_DSP1DRC_NG_MINGAIN_SHIFT 12 /* DSP1DRC_NG_MINGAIN - [15:12] */
2464#define WM8915_DSP1DRC_NG_MINGAIN_WIDTH 4 /* DSP1DRC_NG_MINGAIN - [15:12] */
2465#define WM8915_DSP1DRC_NG_EXP_MASK 0x0C00 /* DSP1DRC_NG_EXP - [11:10] */
2466#define WM8915_DSP1DRC_NG_EXP_SHIFT 10 /* DSP1DRC_NG_EXP - [11:10] */
2467#define WM8915_DSP1DRC_NG_EXP_WIDTH 2 /* DSP1DRC_NG_EXP - [11:10] */
2468#define WM8915_DSP1DRC_QR_THR_MASK 0x0300 /* DSP1DRC_QR_THR - [9:8] */
2469#define WM8915_DSP1DRC_QR_THR_SHIFT 8 /* DSP1DRC_QR_THR - [9:8] */
2470#define WM8915_DSP1DRC_QR_THR_WIDTH 2 /* DSP1DRC_QR_THR - [9:8] */
2471#define WM8915_DSP1DRC_QR_DCY_MASK 0x00C0 /* DSP1DRC_QR_DCY - [7:6] */
2472#define WM8915_DSP1DRC_QR_DCY_SHIFT 6 /* DSP1DRC_QR_DCY - [7:6] */
2473#define WM8915_DSP1DRC_QR_DCY_WIDTH 2 /* DSP1DRC_QR_DCY - [7:6] */
2474#define WM8915_DSP1DRC_HI_COMP_MASK 0x0038 /* DSP1DRC_HI_COMP - [5:3] */
2475#define WM8915_DSP1DRC_HI_COMP_SHIFT 3 /* DSP1DRC_HI_COMP - [5:3] */
2476#define WM8915_DSP1DRC_HI_COMP_WIDTH 3 /* DSP1DRC_HI_COMP - [5:3] */
2477#define WM8915_DSP1DRC_LO_COMP_MASK 0x0007 /* DSP1DRC_LO_COMP - [2:0] */
2478#define WM8915_DSP1DRC_LO_COMP_SHIFT 0 /* DSP1DRC_LO_COMP - [2:0] */
2479#define WM8915_DSP1DRC_LO_COMP_WIDTH 3 /* DSP1DRC_LO_COMP - [2:0] */
2480
2481/*
2482 * R1091 (0x443) - DSP1 DRC (4)
2483 */
2484#define WM8915_DSP1DRC_KNEE_IP_MASK 0x07E0 /* DSP1DRC_KNEE_IP - [10:5] */
2485#define WM8915_DSP1DRC_KNEE_IP_SHIFT 5 /* DSP1DRC_KNEE_IP - [10:5] */
2486#define WM8915_DSP1DRC_KNEE_IP_WIDTH 6 /* DSP1DRC_KNEE_IP - [10:5] */
2487#define WM8915_DSP1DRC_KNEE_OP_MASK 0x001F /* DSP1DRC_KNEE_OP - [4:0] */
2488#define WM8915_DSP1DRC_KNEE_OP_SHIFT 0 /* DSP1DRC_KNEE_OP - [4:0] */
2489#define WM8915_DSP1DRC_KNEE_OP_WIDTH 5 /* DSP1DRC_KNEE_OP - [4:0] */
2490
2491/*
2492 * R1092 (0x444) - DSP1 DRC (5)
2493 */
2494#define WM8915_DSP1DRC_KNEE2_IP_MASK 0x03E0 /* DSP1DRC_KNEE2_IP - [9:5] */
2495#define WM8915_DSP1DRC_KNEE2_IP_SHIFT 5 /* DSP1DRC_KNEE2_IP - [9:5] */
2496#define WM8915_DSP1DRC_KNEE2_IP_WIDTH 5 /* DSP1DRC_KNEE2_IP - [9:5] */
2497#define WM8915_DSP1DRC_KNEE2_OP_MASK 0x001F /* DSP1DRC_KNEE2_OP - [4:0] */
2498#define WM8915_DSP1DRC_KNEE2_OP_SHIFT 0 /* DSP1DRC_KNEE2_OP - [4:0] */
2499#define WM8915_DSP1DRC_KNEE2_OP_WIDTH 5 /* DSP1DRC_KNEE2_OP - [4:0] */
2500
2501/*
2502 * R1152 (0x480) - DSP1 RX EQ Gains (1)
2503 */
2504#define WM8915_DSP1RX_EQ_B1_GAIN_MASK 0xF800 /* DSP1RX_EQ_B1_GAIN - [15:11] */
2505#define WM8915_DSP1RX_EQ_B1_GAIN_SHIFT 11 /* DSP1RX_EQ_B1_GAIN - [15:11] */
2506#define WM8915_DSP1RX_EQ_B1_GAIN_WIDTH 5 /* DSP1RX_EQ_B1_GAIN - [15:11] */
2507#define WM8915_DSP1RX_EQ_B2_GAIN_MASK 0x07C0 /* DSP1RX_EQ_B2_GAIN - [10:6] */
2508#define WM8915_DSP1RX_EQ_B2_GAIN_SHIFT 6 /* DSP1RX_EQ_B2_GAIN - [10:6] */
2509#define WM8915_DSP1RX_EQ_B2_GAIN_WIDTH 5 /* DSP1RX_EQ_B2_GAIN - [10:6] */
2510#define WM8915_DSP1RX_EQ_B3_GAIN_MASK 0x003E /* DSP1RX_EQ_B3_GAIN - [5:1] */
2511#define WM8915_DSP1RX_EQ_B3_GAIN_SHIFT 1 /* DSP1RX_EQ_B3_GAIN - [5:1] */
2512#define WM8915_DSP1RX_EQ_B3_GAIN_WIDTH 5 /* DSP1RX_EQ_B3_GAIN - [5:1] */
2513#define WM8915_DSP1RX_EQ_ENA 0x0001 /* DSP1RX_EQ_ENA */
2514#define WM8915_DSP1RX_EQ_ENA_MASK 0x0001 /* DSP1RX_EQ_ENA */
2515#define WM8915_DSP1RX_EQ_ENA_SHIFT 0 /* DSP1RX_EQ_ENA */
2516#define WM8915_DSP1RX_EQ_ENA_WIDTH 1 /* DSP1RX_EQ_ENA */
2517
2518/*
2519 * R1153 (0x481) - DSP1 RX EQ Gains (2)
2520 */
2521#define WM8915_DSP1RX_EQ_B4_GAIN_MASK 0xF800 /* DSP1RX_EQ_B4_GAIN - [15:11] */
2522#define WM8915_DSP1RX_EQ_B4_GAIN_SHIFT 11 /* DSP1RX_EQ_B4_GAIN - [15:11] */
2523#define WM8915_DSP1RX_EQ_B4_GAIN_WIDTH 5 /* DSP1RX_EQ_B4_GAIN - [15:11] */
2524#define WM8915_DSP1RX_EQ_B5_GAIN_MASK 0x07C0 /* DSP1RX_EQ_B5_GAIN - [10:6] */
2525#define WM8915_DSP1RX_EQ_B5_GAIN_SHIFT 6 /* DSP1RX_EQ_B5_GAIN - [10:6] */
2526#define WM8915_DSP1RX_EQ_B5_GAIN_WIDTH 5 /* DSP1RX_EQ_B5_GAIN - [10:6] */
2527
2528/*
2529 * R1154 (0x482) - DSP1 RX EQ Band 1 A
2530 */
2531#define WM8915_DSP1RX_EQ_B1_A_MASK 0xFFFF /* DSP1RX_EQ_B1_A - [15:0] */
2532#define WM8915_DSP1RX_EQ_B1_A_SHIFT 0 /* DSP1RX_EQ_B1_A - [15:0] */
2533#define WM8915_DSP1RX_EQ_B1_A_WIDTH 16 /* DSP1RX_EQ_B1_A - [15:0] */
2534
2535/*
2536 * R1155 (0x483) - DSP1 RX EQ Band 1 B
2537 */
2538#define WM8915_DSP1RX_EQ_B1_B_MASK 0xFFFF /* DSP1RX_EQ_B1_B - [15:0] */
2539#define WM8915_DSP1RX_EQ_B1_B_SHIFT 0 /* DSP1RX_EQ_B1_B - [15:0] */
2540#define WM8915_DSP1RX_EQ_B1_B_WIDTH 16 /* DSP1RX_EQ_B1_B - [15:0] */
2541
2542/*
2543 * R1156 (0x484) - DSP1 RX EQ Band 1 PG
2544 */
2545#define WM8915_DSP1RX_EQ_B1_PG_MASK 0xFFFF /* DSP1RX_EQ_B1_PG - [15:0] */
2546#define WM8915_DSP1RX_EQ_B1_PG_SHIFT 0 /* DSP1RX_EQ_B1_PG - [15:0] */
2547#define WM8915_DSP1RX_EQ_B1_PG_WIDTH 16 /* DSP1RX_EQ_B1_PG - [15:0] */
2548
2549/*
2550 * R1157 (0x485) - DSP1 RX EQ Band 2 A
2551 */
2552#define WM8915_DSP1RX_EQ_B2_A_MASK 0xFFFF /* DSP1RX_EQ_B2_A - [15:0] */
2553#define WM8915_DSP1RX_EQ_B2_A_SHIFT 0 /* DSP1RX_EQ_B2_A - [15:0] */
2554#define WM8915_DSP1RX_EQ_B2_A_WIDTH 16 /* DSP1RX_EQ_B2_A - [15:0] */
2555
2556/*
2557 * R1158 (0x486) - DSP1 RX EQ Band 2 B
2558 */
2559#define WM8915_DSP1RX_EQ_B2_B_MASK 0xFFFF /* DSP1RX_EQ_B2_B - [15:0] */
2560#define WM8915_DSP1RX_EQ_B2_B_SHIFT 0 /* DSP1RX_EQ_B2_B - [15:0] */
2561#define WM8915_DSP1RX_EQ_B2_B_WIDTH 16 /* DSP1RX_EQ_B2_B - [15:0] */
2562
2563/*
2564 * R1159 (0x487) - DSP1 RX EQ Band 2 C
2565 */
2566#define WM8915_DSP1RX_EQ_B2_C_MASK 0xFFFF /* DSP1RX_EQ_B2_C - [15:0] */
2567#define WM8915_DSP1RX_EQ_B2_C_SHIFT 0 /* DSP1RX_EQ_B2_C - [15:0] */
2568#define WM8915_DSP1RX_EQ_B2_C_WIDTH 16 /* DSP1RX_EQ_B2_C - [15:0] */
2569
2570/*
2571 * R1160 (0x488) - DSP1 RX EQ Band 2 PG
2572 */
2573#define WM8915_DSP1RX_EQ_B2_PG_MASK 0xFFFF /* DSP1RX_EQ_B2_PG - [15:0] */
2574#define WM8915_DSP1RX_EQ_B2_PG_SHIFT 0 /* DSP1RX_EQ_B2_PG - [15:0] */
2575#define WM8915_DSP1RX_EQ_B2_PG_WIDTH 16 /* DSP1RX_EQ_B2_PG - [15:0] */
2576
2577/*
2578 * R1161 (0x489) - DSP1 RX EQ Band 3 A
2579 */
2580#define WM8915_DSP1RX_EQ_B3_A_MASK 0xFFFF /* DSP1RX_EQ_B3_A - [15:0] */
2581#define WM8915_DSP1RX_EQ_B3_A_SHIFT 0 /* DSP1RX_EQ_B3_A - [15:0] */
2582#define WM8915_DSP1RX_EQ_B3_A_WIDTH 16 /* DSP1RX_EQ_B3_A - [15:0] */
2583
2584/*
2585 * R1162 (0x48A) - DSP1 RX EQ Band 3 B
2586 */
2587#define WM8915_DSP1RX_EQ_B3_B_MASK 0xFFFF /* DSP1RX_EQ_B3_B - [15:0] */
2588#define WM8915_DSP1RX_EQ_B3_B_SHIFT 0 /* DSP1RX_EQ_B3_B - [15:0] */
2589#define WM8915_DSP1RX_EQ_B3_B_WIDTH 16 /* DSP1RX_EQ_B3_B - [15:0] */
2590
2591/*
2592 * R1163 (0x48B) - DSP1 RX EQ Band 3 C
2593 */
2594#define WM8915_DSP1RX_EQ_B3_C_MASK 0xFFFF /* DSP1RX_EQ_B3_C - [15:0] */
2595#define WM8915_DSP1RX_EQ_B3_C_SHIFT 0 /* DSP1RX_EQ_B3_C - [15:0] */
2596#define WM8915_DSP1RX_EQ_B3_C_WIDTH 16 /* DSP1RX_EQ_B3_C - [15:0] */
2597
2598/*
2599 * R1164 (0x48C) - DSP1 RX EQ Band 3 PG
2600 */
2601#define WM8915_DSP1RX_EQ_B3_PG_MASK 0xFFFF /* DSP1RX_EQ_B3_PG - [15:0] */
2602#define WM8915_DSP1RX_EQ_B3_PG_SHIFT 0 /* DSP1RX_EQ_B3_PG - [15:0] */
2603#define WM8915_DSP1RX_EQ_B3_PG_WIDTH 16 /* DSP1RX_EQ_B3_PG - [15:0] */
2604
2605/*
2606 * R1165 (0x48D) - DSP1 RX EQ Band 4 A
2607 */
2608#define WM8915_DSP1RX_EQ_B4_A_MASK 0xFFFF /* DSP1RX_EQ_B4_A - [15:0] */
2609#define WM8915_DSP1RX_EQ_B4_A_SHIFT 0 /* DSP1RX_EQ_B4_A - [15:0] */
2610#define WM8915_DSP1RX_EQ_B4_A_WIDTH 16 /* DSP1RX_EQ_B4_A - [15:0] */
2611
2612/*
2613 * R1166 (0x48E) - DSP1 RX EQ Band 4 B
2614 */
2615#define WM8915_DSP1RX_EQ_B4_B_MASK 0xFFFF /* DSP1RX_EQ_B4_B - [15:0] */
2616#define WM8915_DSP1RX_EQ_B4_B_SHIFT 0 /* DSP1RX_EQ_B4_B - [15:0] */
2617#define WM8915_DSP1RX_EQ_B4_B_WIDTH 16 /* DSP1RX_EQ_B4_B - [15:0] */
2618
2619/*
2620 * R1167 (0x48F) - DSP1 RX EQ Band 4 C
2621 */
2622#define WM8915_DSP1RX_EQ_B4_C_MASK 0xFFFF /* DSP1RX_EQ_B4_C - [15:0] */
2623#define WM8915_DSP1RX_EQ_B4_C_SHIFT 0 /* DSP1RX_EQ_B4_C - [15:0] */
2624#define WM8915_DSP1RX_EQ_B4_C_WIDTH 16 /* DSP1RX_EQ_B4_C - [15:0] */
2625
2626/*
2627 * R1168 (0x490) - DSP1 RX EQ Band 4 PG
2628 */
2629#define WM8915_DSP1RX_EQ_B4_PG_MASK 0xFFFF /* DSP1RX_EQ_B4_PG - [15:0] */
2630#define WM8915_DSP1RX_EQ_B4_PG_SHIFT 0 /* DSP1RX_EQ_B4_PG - [15:0] */
2631#define WM8915_DSP1RX_EQ_B4_PG_WIDTH 16 /* DSP1RX_EQ_B4_PG - [15:0] */
2632
2633/*
2634 * R1169 (0x491) - DSP1 RX EQ Band 5 A
2635 */
2636#define WM8915_DSP1RX_EQ_B5_A_MASK 0xFFFF /* DSP1RX_EQ_B5_A - [15:0] */
2637#define WM8915_DSP1RX_EQ_B5_A_SHIFT 0 /* DSP1RX_EQ_B5_A - [15:0] */
2638#define WM8915_DSP1RX_EQ_B5_A_WIDTH 16 /* DSP1RX_EQ_B5_A - [15:0] */
2639
2640/*
2641 * R1170 (0x492) - DSP1 RX EQ Band 5 B
2642 */
2643#define WM8915_DSP1RX_EQ_B5_B_MASK 0xFFFF /* DSP1RX_EQ_B5_B - [15:0] */
2644#define WM8915_DSP1RX_EQ_B5_B_SHIFT 0 /* DSP1RX_EQ_B5_B - [15:0] */
2645#define WM8915_DSP1RX_EQ_B5_B_WIDTH 16 /* DSP1RX_EQ_B5_B - [15:0] */
2646
2647/*
2648 * R1171 (0x493) - DSP1 RX EQ Band 5 PG
2649 */
2650#define WM8915_DSP1RX_EQ_B5_PG_MASK 0xFFFF /* DSP1RX_EQ_B5_PG - [15:0] */
2651#define WM8915_DSP1RX_EQ_B5_PG_SHIFT 0 /* DSP1RX_EQ_B5_PG - [15:0] */
2652#define WM8915_DSP1RX_EQ_B5_PG_WIDTH 16 /* DSP1RX_EQ_B5_PG - [15:0] */
2653
2654/*
2655 * R1280 (0x500) - DSP2 TX Left Volume
2656 */
2657#define WM8915_DSP2TX_VU 0x0100 /* DSP2TX_VU */
2658#define WM8915_DSP2TX_VU_MASK 0x0100 /* DSP2TX_VU */
2659#define WM8915_DSP2TX_VU_SHIFT 8 /* DSP2TX_VU */
2660#define WM8915_DSP2TX_VU_WIDTH 1 /* DSP2TX_VU */
2661#define WM8915_DSP2TXL_VOL_MASK 0x00FF /* DSP2TXL_VOL - [7:0] */
2662#define WM8915_DSP2TXL_VOL_SHIFT 0 /* DSP2TXL_VOL - [7:0] */
2663#define WM8915_DSP2TXL_VOL_WIDTH 8 /* DSP2TXL_VOL - [7:0] */
2664
2665/*
2666 * R1281 (0x501) - DSP2 TX Right Volume
2667 */
2668#define WM8915_DSP2TX_VU 0x0100 /* DSP2TX_VU */
2669#define WM8915_DSP2TX_VU_MASK 0x0100 /* DSP2TX_VU */
2670#define WM8915_DSP2TX_VU_SHIFT 8 /* DSP2TX_VU */
2671#define WM8915_DSP2TX_VU_WIDTH 1 /* DSP2TX_VU */
2672#define WM8915_DSP2TXR_VOL_MASK 0x00FF /* DSP2TXR_VOL - [7:0] */
2673#define WM8915_DSP2TXR_VOL_SHIFT 0 /* DSP2TXR_VOL - [7:0] */
2674#define WM8915_DSP2TXR_VOL_WIDTH 8 /* DSP2TXR_VOL - [7:0] */
2675
2676/*
2677 * R1282 (0x502) - DSP2 RX Left Volume
2678 */
2679#define WM8915_DSP2RX_VU 0x0100 /* DSP2RX_VU */
2680#define WM8915_DSP2RX_VU_MASK 0x0100 /* DSP2RX_VU */
2681#define WM8915_DSP2RX_VU_SHIFT 8 /* DSP2RX_VU */
2682#define WM8915_DSP2RX_VU_WIDTH 1 /* DSP2RX_VU */
2683#define WM8915_DSP2RXL_VOL_MASK 0x00FF /* DSP2RXL_VOL - [7:0] */
2684#define WM8915_DSP2RXL_VOL_SHIFT 0 /* DSP2RXL_VOL - [7:0] */
2685#define WM8915_DSP2RXL_VOL_WIDTH 8 /* DSP2RXL_VOL - [7:0] */
2686
2687/*
2688 * R1283 (0x503) - DSP2 RX Right Volume
2689 */
2690#define WM8915_DSP2RX_VU 0x0100 /* DSP2RX_VU */
2691#define WM8915_DSP2RX_VU_MASK 0x0100 /* DSP2RX_VU */
2692#define WM8915_DSP2RX_VU_SHIFT 8 /* DSP2RX_VU */
2693#define WM8915_DSP2RX_VU_WIDTH 1 /* DSP2RX_VU */
2694#define WM8915_DSP2RXR_VOL_MASK 0x00FF /* DSP2RXR_VOL - [7:0] */
2695#define WM8915_DSP2RXR_VOL_SHIFT 0 /* DSP2RXR_VOL - [7:0] */
2696#define WM8915_DSP2RXR_VOL_WIDTH 8 /* DSP2RXR_VOL - [7:0] */
2697
2698/*
2699 * R1296 (0x510) - DSP2 TX Filters
2700 */
2701#define WM8915_DSP2TX_NF 0x2000 /* DSP2TX_NF */
2702#define WM8915_DSP2TX_NF_MASK 0x2000 /* DSP2TX_NF */
2703#define WM8915_DSP2TX_NF_SHIFT 13 /* DSP2TX_NF */
2704#define WM8915_DSP2TX_NF_WIDTH 1 /* DSP2TX_NF */
2705#define WM8915_DSP2TXL_HPF 0x1000 /* DSP2TXL_HPF */
2706#define WM8915_DSP2TXL_HPF_MASK 0x1000 /* DSP2TXL_HPF */
2707#define WM8915_DSP2TXL_HPF_SHIFT 12 /* DSP2TXL_HPF */
2708#define WM8915_DSP2TXL_HPF_WIDTH 1 /* DSP2TXL_HPF */
2709#define WM8915_DSP2TXR_HPF 0x0800 /* DSP2TXR_HPF */
2710#define WM8915_DSP2TXR_HPF_MASK 0x0800 /* DSP2TXR_HPF */
2711#define WM8915_DSP2TXR_HPF_SHIFT 11 /* DSP2TXR_HPF */
2712#define WM8915_DSP2TXR_HPF_WIDTH 1 /* DSP2TXR_HPF */
2713#define WM8915_DSP2TX_HPF_MODE_MASK 0x0018 /* DSP2TX_HPF_MODE - [4:3] */
2714#define WM8915_DSP2TX_HPF_MODE_SHIFT 3 /* DSP2TX_HPF_MODE - [4:3] */
2715#define WM8915_DSP2TX_HPF_MODE_WIDTH 2 /* DSP2TX_HPF_MODE - [4:3] */
2716#define WM8915_DSP2TX_HPF_CUT_MASK 0x0007 /* DSP2TX_HPF_CUT - [2:0] */
2717#define WM8915_DSP2TX_HPF_CUT_SHIFT 0 /* DSP2TX_HPF_CUT - [2:0] */
2718#define WM8915_DSP2TX_HPF_CUT_WIDTH 3 /* DSP2TX_HPF_CUT - [2:0] */
2719
2720/*
2721 * R1312 (0x520) - DSP2 RX Filters (1)
2722 */
2723#define WM8915_DSP2RX_MUTE 0x0200 /* DSP2RX_MUTE */
2724#define WM8915_DSP2RX_MUTE_MASK 0x0200 /* DSP2RX_MUTE */
2725#define WM8915_DSP2RX_MUTE_SHIFT 9 /* DSP2RX_MUTE */
2726#define WM8915_DSP2RX_MUTE_WIDTH 1 /* DSP2RX_MUTE */
2727#define WM8915_DSP2RX_MONO 0x0080 /* DSP2RX_MONO */
2728#define WM8915_DSP2RX_MONO_MASK 0x0080 /* DSP2RX_MONO */
2729#define WM8915_DSP2RX_MONO_SHIFT 7 /* DSP2RX_MONO */
2730#define WM8915_DSP2RX_MONO_WIDTH 1 /* DSP2RX_MONO */
2731#define WM8915_DSP2RX_MUTERATE 0x0020 /* DSP2RX_MUTERATE */
2732#define WM8915_DSP2RX_MUTERATE_MASK 0x0020 /* DSP2RX_MUTERATE */
2733#define WM8915_DSP2RX_MUTERATE_SHIFT 5 /* DSP2RX_MUTERATE */
2734#define WM8915_DSP2RX_MUTERATE_WIDTH 1 /* DSP2RX_MUTERATE */
2735#define WM8915_DSP2RX_UNMUTE_RAMP 0x0010 /* DSP2RX_UNMUTE_RAMP */
2736#define WM8915_DSP2RX_UNMUTE_RAMP_MASK 0x0010 /* DSP2RX_UNMUTE_RAMP */
2737#define WM8915_DSP2RX_UNMUTE_RAMP_SHIFT 4 /* DSP2RX_UNMUTE_RAMP */
2738#define WM8915_DSP2RX_UNMUTE_RAMP_WIDTH 1 /* DSP2RX_UNMUTE_RAMP */
2739
2740/*
2741 * R1313 (0x521) - DSP2 RX Filters (2)
2742 */
2743#define WM8915_DSP2RX_3D_GAIN_MASK 0x3E00 /* DSP2RX_3D_GAIN - [13:9] */
2744#define WM8915_DSP2RX_3D_GAIN_SHIFT 9 /* DSP2RX_3D_GAIN - [13:9] */
2745#define WM8915_DSP2RX_3D_GAIN_WIDTH 5 /* DSP2RX_3D_GAIN - [13:9] */
2746#define WM8915_DSP2RX_3D_ENA 0x0100 /* DSP2RX_3D_ENA */
2747#define WM8915_DSP2RX_3D_ENA_MASK 0x0100 /* DSP2RX_3D_ENA */
2748#define WM8915_DSP2RX_3D_ENA_SHIFT 8 /* DSP2RX_3D_ENA */
2749#define WM8915_DSP2RX_3D_ENA_WIDTH 1 /* DSP2RX_3D_ENA */
2750
2751/*
2752 * R1344 (0x540) - DSP2 DRC (1)
2753 */
2754#define WM8915_DSP2DRC_SIG_DET_RMS_MASK 0xF800 /* DSP2DRC_SIG_DET_RMS - [15:11] */
2755#define WM8915_DSP2DRC_SIG_DET_RMS_SHIFT 11 /* DSP2DRC_SIG_DET_RMS - [15:11] */
2756#define WM8915_DSP2DRC_SIG_DET_RMS_WIDTH 5 /* DSP2DRC_SIG_DET_RMS - [15:11] */
2757#define WM8915_DSP2DRC_SIG_DET_PK_MASK 0x0600 /* DSP2DRC_SIG_DET_PK - [10:9] */
2758#define WM8915_DSP2DRC_SIG_DET_PK_SHIFT 9 /* DSP2DRC_SIG_DET_PK - [10:9] */
2759#define WM8915_DSP2DRC_SIG_DET_PK_WIDTH 2 /* DSP2DRC_SIG_DET_PK - [10:9] */
2760#define WM8915_DSP2DRC_NG_ENA 0x0100 /* DSP2DRC_NG_ENA */
2761#define WM8915_DSP2DRC_NG_ENA_MASK 0x0100 /* DSP2DRC_NG_ENA */
2762#define WM8915_DSP2DRC_NG_ENA_SHIFT 8 /* DSP2DRC_NG_ENA */
2763#define WM8915_DSP2DRC_NG_ENA_WIDTH 1 /* DSP2DRC_NG_ENA */
2764#define WM8915_DSP2DRC_SIG_DET_MODE 0x0080 /* DSP2DRC_SIG_DET_MODE */
2765#define WM8915_DSP2DRC_SIG_DET_MODE_MASK 0x0080 /* DSP2DRC_SIG_DET_MODE */
2766#define WM8915_DSP2DRC_SIG_DET_MODE_SHIFT 7 /* DSP2DRC_SIG_DET_MODE */
2767#define WM8915_DSP2DRC_SIG_DET_MODE_WIDTH 1 /* DSP2DRC_SIG_DET_MODE */
2768#define WM8915_DSP2DRC_SIG_DET 0x0040 /* DSP2DRC_SIG_DET */
2769#define WM8915_DSP2DRC_SIG_DET_MASK 0x0040 /* DSP2DRC_SIG_DET */
2770#define WM8915_DSP2DRC_SIG_DET_SHIFT 6 /* DSP2DRC_SIG_DET */
2771#define WM8915_DSP2DRC_SIG_DET_WIDTH 1 /* DSP2DRC_SIG_DET */
2772#define WM8915_DSP2DRC_KNEE2_OP_ENA 0x0020 /* DSP2DRC_KNEE2_OP_ENA */
2773#define WM8915_DSP2DRC_KNEE2_OP_ENA_MASK 0x0020 /* DSP2DRC_KNEE2_OP_ENA */
2774#define WM8915_DSP2DRC_KNEE2_OP_ENA_SHIFT 5 /* DSP2DRC_KNEE2_OP_ENA */
2775#define WM8915_DSP2DRC_KNEE2_OP_ENA_WIDTH 1 /* DSP2DRC_KNEE2_OP_ENA */
2776#define WM8915_DSP2DRC_QR 0x0010 /* DSP2DRC_QR */
2777#define WM8915_DSP2DRC_QR_MASK 0x0010 /* DSP2DRC_QR */
2778#define WM8915_DSP2DRC_QR_SHIFT 4 /* DSP2DRC_QR */
2779#define WM8915_DSP2DRC_QR_WIDTH 1 /* DSP2DRC_QR */
2780#define WM8915_DSP2DRC_ANTICLIP 0x0008 /* DSP2DRC_ANTICLIP */
2781#define WM8915_DSP2DRC_ANTICLIP_MASK 0x0008 /* DSP2DRC_ANTICLIP */
2782#define WM8915_DSP2DRC_ANTICLIP_SHIFT 3 /* DSP2DRC_ANTICLIP */
2783#define WM8915_DSP2DRC_ANTICLIP_WIDTH 1 /* DSP2DRC_ANTICLIP */
2784#define WM8915_DSP2RX_DRC_ENA 0x0004 /* DSP2RX_DRC_ENA */
2785#define WM8915_DSP2RX_DRC_ENA_MASK 0x0004 /* DSP2RX_DRC_ENA */
2786#define WM8915_DSP2RX_DRC_ENA_SHIFT 2 /* DSP2RX_DRC_ENA */
2787#define WM8915_DSP2RX_DRC_ENA_WIDTH 1 /* DSP2RX_DRC_ENA */
2788#define WM8915_DSP2TXL_DRC_ENA 0x0002 /* DSP2TXL_DRC_ENA */
2789#define WM8915_DSP2TXL_DRC_ENA_MASK 0x0002 /* DSP2TXL_DRC_ENA */
2790#define WM8915_DSP2TXL_DRC_ENA_SHIFT 1 /* DSP2TXL_DRC_ENA */
2791#define WM8915_DSP2TXL_DRC_ENA_WIDTH 1 /* DSP2TXL_DRC_ENA */
2792#define WM8915_DSP2TXR_DRC_ENA 0x0001 /* DSP2TXR_DRC_ENA */
2793#define WM8915_DSP2TXR_DRC_ENA_MASK 0x0001 /* DSP2TXR_DRC_ENA */
2794#define WM8915_DSP2TXR_DRC_ENA_SHIFT 0 /* DSP2TXR_DRC_ENA */
2795#define WM8915_DSP2TXR_DRC_ENA_WIDTH 1 /* DSP2TXR_DRC_ENA */
2796
2797/*
2798 * R1345 (0x541) - DSP2 DRC (2)
2799 */
2800#define WM8915_DSP2DRC_ATK_MASK 0x1E00 /* DSP2DRC_ATK - [12:9] */
2801#define WM8915_DSP2DRC_ATK_SHIFT 9 /* DSP2DRC_ATK - [12:9] */
2802#define WM8915_DSP2DRC_ATK_WIDTH 4 /* DSP2DRC_ATK - [12:9] */
2803#define WM8915_DSP2DRC_DCY_MASK 0x01E0 /* DSP2DRC_DCY - [8:5] */
2804#define WM8915_DSP2DRC_DCY_SHIFT 5 /* DSP2DRC_DCY - [8:5] */
2805#define WM8915_DSP2DRC_DCY_WIDTH 4 /* DSP2DRC_DCY - [8:5] */
2806#define WM8915_DSP2DRC_MINGAIN_MASK 0x001C /* DSP2DRC_MINGAIN - [4:2] */
2807#define WM8915_DSP2DRC_MINGAIN_SHIFT 2 /* DSP2DRC_MINGAIN - [4:2] */
2808#define WM8915_DSP2DRC_MINGAIN_WIDTH 3 /* DSP2DRC_MINGAIN - [4:2] */
2809#define WM8915_DSP2DRC_MAXGAIN_MASK 0x0003 /* DSP2DRC_MAXGAIN - [1:0] */
2810#define WM8915_DSP2DRC_MAXGAIN_SHIFT 0 /* DSP2DRC_MAXGAIN - [1:0] */
2811#define WM8915_DSP2DRC_MAXGAIN_WIDTH 2 /* DSP2DRC_MAXGAIN - [1:0] */
2812
2813/*
2814 * R1346 (0x542) - DSP2 DRC (3)
2815 */
2816#define WM8915_DSP2DRC_NG_MINGAIN_MASK 0xF000 /* DSP2DRC_NG_MINGAIN - [15:12] */
2817#define WM8915_DSP2DRC_NG_MINGAIN_SHIFT 12 /* DSP2DRC_NG_MINGAIN - [15:12] */
2818#define WM8915_DSP2DRC_NG_MINGAIN_WIDTH 4 /* DSP2DRC_NG_MINGAIN - [15:12] */
2819#define WM8915_DSP2DRC_NG_EXP_MASK 0x0C00 /* DSP2DRC_NG_EXP - [11:10] */
2820#define WM8915_DSP2DRC_NG_EXP_SHIFT 10 /* DSP2DRC_NG_EXP - [11:10] */
2821#define WM8915_DSP2DRC_NG_EXP_WIDTH 2 /* DSP2DRC_NG_EXP - [11:10] */
2822#define WM8915_DSP2DRC_QR_THR_MASK 0x0300 /* DSP2DRC_QR_THR - [9:8] */
2823#define WM8915_DSP2DRC_QR_THR_SHIFT 8 /* DSP2DRC_QR_THR - [9:8] */
2824#define WM8915_DSP2DRC_QR_THR_WIDTH 2 /* DSP2DRC_QR_THR - [9:8] */
2825#define WM8915_DSP2DRC_QR_DCY_MASK 0x00C0 /* DSP2DRC_QR_DCY - [7:6] */
2826#define WM8915_DSP2DRC_QR_DCY_SHIFT 6 /* DSP2DRC_QR_DCY - [7:6] */
2827#define WM8915_DSP2DRC_QR_DCY_WIDTH 2 /* DSP2DRC_QR_DCY - [7:6] */
2828#define WM8915_DSP2DRC_HI_COMP_MASK 0x0038 /* DSP2DRC_HI_COMP - [5:3] */
2829#define WM8915_DSP2DRC_HI_COMP_SHIFT 3 /* DSP2DRC_HI_COMP - [5:3] */
2830#define WM8915_DSP2DRC_HI_COMP_WIDTH 3 /* DSP2DRC_HI_COMP - [5:3] */
2831#define WM8915_DSP2DRC_LO_COMP_MASK 0x0007 /* DSP2DRC_LO_COMP - [2:0] */
2832#define WM8915_DSP2DRC_LO_COMP_SHIFT 0 /* DSP2DRC_LO_COMP - [2:0] */
2833#define WM8915_DSP2DRC_LO_COMP_WIDTH 3 /* DSP2DRC_LO_COMP - [2:0] */
2834
2835/*
2836 * R1347 (0x543) - DSP2 DRC (4)
2837 */
2838#define WM8915_DSP2DRC_KNEE_IP_MASK 0x07E0 /* DSP2DRC_KNEE_IP - [10:5] */
2839#define WM8915_DSP2DRC_KNEE_IP_SHIFT 5 /* DSP2DRC_KNEE_IP - [10:5] */
2840#define WM8915_DSP2DRC_KNEE_IP_WIDTH 6 /* DSP2DRC_KNEE_IP - [10:5] */
2841#define WM8915_DSP2DRC_KNEE_OP_MASK 0x001F /* DSP2DRC_KNEE_OP - [4:0] */
2842#define WM8915_DSP2DRC_KNEE_OP_SHIFT 0 /* DSP2DRC_KNEE_OP - [4:0] */
2843#define WM8915_DSP2DRC_KNEE_OP_WIDTH 5 /* DSP2DRC_KNEE_OP - [4:0] */
2844
2845/*
2846 * R1348 (0x544) - DSP2 DRC (5)
2847 */
2848#define WM8915_DSP2DRC_KNEE2_IP_MASK 0x03E0 /* DSP2DRC_KNEE2_IP - [9:5] */
2849#define WM8915_DSP2DRC_KNEE2_IP_SHIFT 5 /* DSP2DRC_KNEE2_IP - [9:5] */
2850#define WM8915_DSP2DRC_KNEE2_IP_WIDTH 5 /* DSP2DRC_KNEE2_IP - [9:5] */
2851#define WM8915_DSP2DRC_KNEE2_OP_MASK 0x001F /* DSP2DRC_KNEE2_OP - [4:0] */
2852#define WM8915_DSP2DRC_KNEE2_OP_SHIFT 0 /* DSP2DRC_KNEE2_OP - [4:0] */
2853#define WM8915_DSP2DRC_KNEE2_OP_WIDTH 5 /* DSP2DRC_KNEE2_OP - [4:0] */
2854
2855/*
2856 * R1408 (0x580) - DSP2 RX EQ Gains (1)
2857 */
2858#define WM8915_DSP2RX_EQ_B1_GAIN_MASK 0xF800 /* DSP2RX_EQ_B1_GAIN - [15:11] */
2859#define WM8915_DSP2RX_EQ_B1_GAIN_SHIFT 11 /* DSP2RX_EQ_B1_GAIN - [15:11] */
2860#define WM8915_DSP2RX_EQ_B1_GAIN_WIDTH 5 /* DSP2RX_EQ_B1_GAIN - [15:11] */
2861#define WM8915_DSP2RX_EQ_B2_GAIN_MASK 0x07C0 /* DSP2RX_EQ_B2_GAIN - [10:6] */
2862#define WM8915_DSP2RX_EQ_B2_GAIN_SHIFT 6 /* DSP2RX_EQ_B2_GAIN - [10:6] */
2863#define WM8915_DSP2RX_EQ_B2_GAIN_WIDTH 5 /* DSP2RX_EQ_B2_GAIN - [10:6] */
2864#define WM8915_DSP2RX_EQ_B3_GAIN_MASK 0x003E /* DSP2RX_EQ_B3_GAIN - [5:1] */
2865#define WM8915_DSP2RX_EQ_B3_GAIN_SHIFT 1 /* DSP2RX_EQ_B3_GAIN - [5:1] */
2866#define WM8915_DSP2RX_EQ_B3_GAIN_WIDTH 5 /* DSP2RX_EQ_B3_GAIN - [5:1] */
2867#define WM8915_DSP2RX_EQ_ENA 0x0001 /* DSP2RX_EQ_ENA */
2868#define WM8915_DSP2RX_EQ_ENA_MASK 0x0001 /* DSP2RX_EQ_ENA */
2869#define WM8915_DSP2RX_EQ_ENA_SHIFT 0 /* DSP2RX_EQ_ENA */
2870#define WM8915_DSP2RX_EQ_ENA_WIDTH 1 /* DSP2RX_EQ_ENA */
2871
2872/*
2873 * R1409 (0x581) - DSP2 RX EQ Gains (2)
2874 */
2875#define WM8915_DSP2RX_EQ_B4_GAIN_MASK 0xF800 /* DSP2RX_EQ_B4_GAIN - [15:11] */
2876#define WM8915_DSP2RX_EQ_B4_GAIN_SHIFT 11 /* DSP2RX_EQ_B4_GAIN - [15:11] */
2877#define WM8915_DSP2RX_EQ_B4_GAIN_WIDTH 5 /* DSP2RX_EQ_B4_GAIN - [15:11] */
2878#define WM8915_DSP2RX_EQ_B5_GAIN_MASK 0x07C0 /* DSP2RX_EQ_B5_GAIN - [10:6] */
2879#define WM8915_DSP2RX_EQ_B5_GAIN_SHIFT 6 /* DSP2RX_EQ_B5_GAIN - [10:6] */
2880#define WM8915_DSP2RX_EQ_B5_GAIN_WIDTH 5 /* DSP2RX_EQ_B5_GAIN - [10:6] */
2881
2882/*
2883 * R1410 (0x582) - DSP2 RX EQ Band 1 A
2884 */
2885#define WM8915_DSP2RX_EQ_B1_A_MASK 0xFFFF /* DSP2RX_EQ_B1_A - [15:0] */
2886#define WM8915_DSP2RX_EQ_B1_A_SHIFT 0 /* DSP2RX_EQ_B1_A - [15:0] */
2887#define WM8915_DSP2RX_EQ_B1_A_WIDTH 16 /* DSP2RX_EQ_B1_A - [15:0] */
2888
2889/*
2890 * R1411 (0x583) - DSP2 RX EQ Band 1 B
2891 */
2892#define WM8915_DSP2RX_EQ_B1_B_MASK 0xFFFF /* DSP2RX_EQ_B1_B - [15:0] */
2893#define WM8915_DSP2RX_EQ_B1_B_SHIFT 0 /* DSP2RX_EQ_B1_B - [15:0] */
2894#define WM8915_DSP2RX_EQ_B1_B_WIDTH 16 /* DSP2RX_EQ_B1_B - [15:0] */
2895
2896/*
2897 * R1412 (0x584) - DSP2 RX EQ Band 1 PG
2898 */
2899#define WM8915_DSP2RX_EQ_B1_PG_MASK 0xFFFF /* DSP2RX_EQ_B1_PG - [15:0] */
2900#define WM8915_DSP2RX_EQ_B1_PG_SHIFT 0 /* DSP2RX_EQ_B1_PG - [15:0] */
2901#define WM8915_DSP2RX_EQ_B1_PG_WIDTH 16 /* DSP2RX_EQ_B1_PG - [15:0] */
2902
2903/*
2904 * R1413 (0x585) - DSP2 RX EQ Band 2 A
2905 */
2906#define WM8915_DSP2RX_EQ_B2_A_MASK 0xFFFF /* DSP2RX_EQ_B2_A - [15:0] */
2907#define WM8915_DSP2RX_EQ_B2_A_SHIFT 0 /* DSP2RX_EQ_B2_A - [15:0] */
2908#define WM8915_DSP2RX_EQ_B2_A_WIDTH 16 /* DSP2RX_EQ_B2_A - [15:0] */
2909
2910/*
2911 * R1414 (0x586) - DSP2 RX EQ Band 2 B
2912 */
2913#define WM8915_DSP2RX_EQ_B2_B_MASK 0xFFFF /* DSP2RX_EQ_B2_B - [15:0] */
2914#define WM8915_DSP2RX_EQ_B2_B_SHIFT 0 /* DSP2RX_EQ_B2_B - [15:0] */
2915#define WM8915_DSP2RX_EQ_B2_B_WIDTH 16 /* DSP2RX_EQ_B2_B - [15:0] */
2916
2917/*
2918 * R1415 (0x587) - DSP2 RX EQ Band 2 C
2919 */
2920#define WM8915_DSP2RX_EQ_B2_C_MASK 0xFFFF /* DSP2RX_EQ_B2_C - [15:0] */
2921#define WM8915_DSP2RX_EQ_B2_C_SHIFT 0 /* DSP2RX_EQ_B2_C - [15:0] */
2922#define WM8915_DSP2RX_EQ_B2_C_WIDTH 16 /* DSP2RX_EQ_B2_C - [15:0] */
2923
2924/*
2925 * R1416 (0x588) - DSP2 RX EQ Band 2 PG
2926 */
2927#define WM8915_DSP2RX_EQ_B2_PG_MASK 0xFFFF /* DSP2RX_EQ_B2_PG - [15:0] */
2928#define WM8915_DSP2RX_EQ_B2_PG_SHIFT 0 /* DSP2RX_EQ_B2_PG - [15:0] */
2929#define WM8915_DSP2RX_EQ_B2_PG_WIDTH 16 /* DSP2RX_EQ_B2_PG - [15:0] */
2930
2931/*
2932 * R1417 (0x589) - DSP2 RX EQ Band 3 A
2933 */
2934#define WM8915_DSP2RX_EQ_B3_A_MASK 0xFFFF /* DSP2RX_EQ_B3_A - [15:0] */
2935#define WM8915_DSP2RX_EQ_B3_A_SHIFT 0 /* DSP2RX_EQ_B3_A - [15:0] */
2936#define WM8915_DSP2RX_EQ_B3_A_WIDTH 16 /* DSP2RX_EQ_B3_A - [15:0] */
2937
2938/*
2939 * R1418 (0x58A) - DSP2 RX EQ Band 3 B
2940 */
2941#define WM8915_DSP2RX_EQ_B3_B_MASK 0xFFFF /* DSP2RX_EQ_B3_B - [15:0] */
2942#define WM8915_DSP2RX_EQ_B3_B_SHIFT 0 /* DSP2RX_EQ_B3_B - [15:0] */
2943#define WM8915_DSP2RX_EQ_B3_B_WIDTH 16 /* DSP2RX_EQ_B3_B - [15:0] */
2944
2945/*
2946 * R1419 (0x58B) - DSP2 RX EQ Band 3 C
2947 */
2948#define WM8915_DSP2RX_EQ_B3_C_MASK 0xFFFF /* DSP2RX_EQ_B3_C - [15:0] */
2949#define WM8915_DSP2RX_EQ_B3_C_SHIFT 0 /* DSP2RX_EQ_B3_C - [15:0] */
2950#define WM8915_DSP2RX_EQ_B3_C_WIDTH 16 /* DSP2RX_EQ_B3_C - [15:0] */
2951
2952/*
2953 * R1420 (0x58C) - DSP2 RX EQ Band 3 PG
2954 */
2955#define WM8915_DSP2RX_EQ_B3_PG_MASK 0xFFFF /* DSP2RX_EQ_B3_PG - [15:0] */
2956#define WM8915_DSP2RX_EQ_B3_PG_SHIFT 0 /* DSP2RX_EQ_B3_PG - [15:0] */
2957#define WM8915_DSP2RX_EQ_B3_PG_WIDTH 16 /* DSP2RX_EQ_B3_PG - [15:0] */
2958
2959/*
2960 * R1421 (0x58D) - DSP2 RX EQ Band 4 A
2961 */
2962#define WM8915_DSP2RX_EQ_B4_A_MASK 0xFFFF /* DSP2RX_EQ_B4_A - [15:0] */
2963#define WM8915_DSP2RX_EQ_B4_A_SHIFT 0 /* DSP2RX_EQ_B4_A - [15:0] */
2964#define WM8915_DSP2RX_EQ_B4_A_WIDTH 16 /* DSP2RX_EQ_B4_A - [15:0] */
2965
2966/*
2967 * R1422 (0x58E) - DSP2 RX EQ Band 4 B
2968 */
2969#define WM8915_DSP2RX_EQ_B4_B_MASK 0xFFFF /* DSP2RX_EQ_B4_B - [15:0] */
2970#define WM8915_DSP2RX_EQ_B4_B_SHIFT 0 /* DSP2RX_EQ_B4_B - [15:0] */
2971#define WM8915_DSP2RX_EQ_B4_B_WIDTH 16 /* DSP2RX_EQ_B4_B - [15:0] */
2972
2973/*
2974 * R1423 (0x58F) - DSP2 RX EQ Band 4 C
2975 */
2976#define WM8915_DSP2RX_EQ_B4_C_MASK 0xFFFF /* DSP2RX_EQ_B4_C - [15:0] */
2977#define WM8915_DSP2RX_EQ_B4_C_SHIFT 0 /* DSP2RX_EQ_B4_C - [15:0] */
2978#define WM8915_DSP2RX_EQ_B4_C_WIDTH 16 /* DSP2RX_EQ_B4_C - [15:0] */
2979
2980/*
2981 * R1424 (0x590) - DSP2 RX EQ Band 4 PG
2982 */
2983#define WM8915_DSP2RX_EQ_B4_PG_MASK 0xFFFF /* DSP2RX_EQ_B4_PG - [15:0] */
2984#define WM8915_DSP2RX_EQ_B4_PG_SHIFT 0 /* DSP2RX_EQ_B4_PG - [15:0] */
2985#define WM8915_DSP2RX_EQ_B4_PG_WIDTH 16 /* DSP2RX_EQ_B4_PG - [15:0] */
2986
2987/*
2988 * R1425 (0x591) - DSP2 RX EQ Band 5 A
2989 */
2990#define WM8915_DSP2RX_EQ_B5_A_MASK 0xFFFF /* DSP2RX_EQ_B5_A - [15:0] */
2991#define WM8915_DSP2RX_EQ_B5_A_SHIFT 0 /* DSP2RX_EQ_B5_A - [15:0] */
2992#define WM8915_DSP2RX_EQ_B5_A_WIDTH 16 /* DSP2RX_EQ_B5_A - [15:0] */
2993
2994/*
2995 * R1426 (0x592) - DSP2 RX EQ Band 5 B
2996 */
2997#define WM8915_DSP2RX_EQ_B5_B_MASK 0xFFFF /* DSP2RX_EQ_B5_B - [15:0] */
2998#define WM8915_DSP2RX_EQ_B5_B_SHIFT 0 /* DSP2RX_EQ_B5_B - [15:0] */
2999#define WM8915_DSP2RX_EQ_B5_B_WIDTH 16 /* DSP2RX_EQ_B5_B - [15:0] */
3000
3001/*
3002 * R1427 (0x593) - DSP2 RX EQ Band 5 PG
3003 */
3004#define WM8915_DSP2RX_EQ_B5_PG_MASK 0xFFFF /* DSP2RX_EQ_B5_PG - [15:0] */
3005#define WM8915_DSP2RX_EQ_B5_PG_SHIFT 0 /* DSP2RX_EQ_B5_PG - [15:0] */
3006#define WM8915_DSP2RX_EQ_B5_PG_WIDTH 16 /* DSP2RX_EQ_B5_PG - [15:0] */
3007
3008/*
3009 * R1536 (0x600) - DAC1 Mixer Volumes
3010 */
3011#define WM8915_ADCR_DAC1_VOL_MASK 0x03E0 /* ADCR_DAC1_VOL - [9:5] */
3012#define WM8915_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [9:5] */
3013#define WM8915_ADCR_DAC1_VOL_WIDTH 5 /* ADCR_DAC1_VOL - [9:5] */
3014#define WM8915_ADCL_DAC1_VOL_MASK 0x001F /* ADCL_DAC1_VOL - [4:0] */
3015#define WM8915_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [4:0] */
3016#define WM8915_ADCL_DAC1_VOL_WIDTH 5 /* ADCL_DAC1_VOL - [4:0] */
3017
3018/*
3019 * R1537 (0x601) - DAC1 Left Mixer Routing
3020 */
3021#define WM8915_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */
3022#define WM8915_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */
3023#define WM8915_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */
3024#define WM8915_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */
3025#define WM8915_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */
3026#define WM8915_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */
3027#define WM8915_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */
3028#define WM8915_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */
3029#define WM8915_DSP2RXL_TO_DAC1L 0x0002 /* DSP2RXL_TO_DAC1L */
3030#define WM8915_DSP2RXL_TO_DAC1L_MASK 0x0002 /* DSP2RXL_TO_DAC1L */
3031#define WM8915_DSP2RXL_TO_DAC1L_SHIFT 1 /* DSP2RXL_TO_DAC1L */
3032#define WM8915_DSP2RXL_TO_DAC1L_WIDTH 1 /* DSP2RXL_TO_DAC1L */
3033#define WM8915_DSP1RXL_TO_DAC1L 0x0001 /* DSP1RXL_TO_DAC1L */
3034#define WM8915_DSP1RXL_TO_DAC1L_MASK 0x0001 /* DSP1RXL_TO_DAC1L */
3035#define WM8915_DSP1RXL_TO_DAC1L_SHIFT 0 /* DSP1RXL_TO_DAC1L */
3036#define WM8915_DSP1RXL_TO_DAC1L_WIDTH 1 /* DSP1RXL_TO_DAC1L */
3037
3038/*
3039 * R1538 (0x602) - DAC1 Right Mixer Routing
3040 */
3041#define WM8915_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */
3042#define WM8915_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */
3043#define WM8915_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */
3044#define WM8915_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */
3045#define WM8915_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */
3046#define WM8915_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */
3047#define WM8915_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */
3048#define WM8915_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */
3049#define WM8915_DSP2RXR_TO_DAC1R 0x0002 /* DSP2RXR_TO_DAC1R */
3050#define WM8915_DSP2RXR_TO_DAC1R_MASK 0x0002 /* DSP2RXR_TO_DAC1R */
3051#define WM8915_DSP2RXR_TO_DAC1R_SHIFT 1 /* DSP2RXR_TO_DAC1R */
3052#define WM8915_DSP2RXR_TO_DAC1R_WIDTH 1 /* DSP2RXR_TO_DAC1R */
3053#define WM8915_DSP1RXR_TO_DAC1R 0x0001 /* DSP1RXR_TO_DAC1R */
3054#define WM8915_DSP1RXR_TO_DAC1R_MASK 0x0001 /* DSP1RXR_TO_DAC1R */
3055#define WM8915_DSP1RXR_TO_DAC1R_SHIFT 0 /* DSP1RXR_TO_DAC1R */
3056#define WM8915_DSP1RXR_TO_DAC1R_WIDTH 1 /* DSP1RXR_TO_DAC1R */
3057
3058/*
3059 * R1539 (0x603) - DAC2 Mixer Volumes
3060 */
3061#define WM8915_ADCR_DAC2_VOL_MASK 0x03E0 /* ADCR_DAC2_VOL - [9:5] */
3062#define WM8915_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [9:5] */
3063#define WM8915_ADCR_DAC2_VOL_WIDTH 5 /* ADCR_DAC2_VOL - [9:5] */
3064#define WM8915_ADCL_DAC2_VOL_MASK 0x001F /* ADCL_DAC2_VOL - [4:0] */
3065#define WM8915_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [4:0] */
3066#define WM8915_ADCL_DAC2_VOL_WIDTH 5 /* ADCL_DAC2_VOL - [4:0] */
3067
3068/*
3069 * R1540 (0x604) - DAC2 Left Mixer Routing
3070 */
3071#define WM8915_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */
3072#define WM8915_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */
3073#define WM8915_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */
3074#define WM8915_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */
3075#define WM8915_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */
3076#define WM8915_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */
3077#define WM8915_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */
3078#define WM8915_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */
3079#define WM8915_DSP2RXL_TO_DAC2L 0x0002 /* DSP2RXL_TO_DAC2L */
3080#define WM8915_DSP2RXL_TO_DAC2L_MASK 0x0002 /* DSP2RXL_TO_DAC2L */
3081#define WM8915_DSP2RXL_TO_DAC2L_SHIFT 1 /* DSP2RXL_TO_DAC2L */
3082#define WM8915_DSP2RXL_TO_DAC2L_WIDTH 1 /* DSP2RXL_TO_DAC2L */
3083#define WM8915_DSP1RXL_TO_DAC2L 0x0001 /* DSP1RXL_TO_DAC2L */
3084#define WM8915_DSP1RXL_TO_DAC2L_MASK 0x0001 /* DSP1RXL_TO_DAC2L */
3085#define WM8915_DSP1RXL_TO_DAC2L_SHIFT 0 /* DSP1RXL_TO_DAC2L */
3086#define WM8915_DSP1RXL_TO_DAC2L_WIDTH 1 /* DSP1RXL_TO_DAC2L */
3087
3088/*
3089 * R1541 (0x605) - DAC2 Right Mixer Routing
3090 */
3091#define WM8915_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */
3092#define WM8915_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */
3093#define WM8915_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */
3094#define WM8915_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */
3095#define WM8915_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */
3096#define WM8915_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */
3097#define WM8915_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */
3098#define WM8915_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */
3099#define WM8915_DSP2RXR_TO_DAC2R 0x0002 /* DSP2RXR_TO_DAC2R */
3100#define WM8915_DSP2RXR_TO_DAC2R_MASK 0x0002 /* DSP2RXR_TO_DAC2R */
3101#define WM8915_DSP2RXR_TO_DAC2R_SHIFT 1 /* DSP2RXR_TO_DAC2R */
3102#define WM8915_DSP2RXR_TO_DAC2R_WIDTH 1 /* DSP2RXR_TO_DAC2R */
3103#define WM8915_DSP1RXR_TO_DAC2R 0x0001 /* DSP1RXR_TO_DAC2R */
3104#define WM8915_DSP1RXR_TO_DAC2R_MASK 0x0001 /* DSP1RXR_TO_DAC2R */
3105#define WM8915_DSP1RXR_TO_DAC2R_SHIFT 0 /* DSP1RXR_TO_DAC2R */
3106#define WM8915_DSP1RXR_TO_DAC2R_WIDTH 1 /* DSP1RXR_TO_DAC2R */
3107
3108/*
3109 * R1542 (0x606) - DSP1 TX Left Mixer Routing
3110 */
3111#define WM8915_ADC1L_TO_DSP1TXL 0x0002 /* ADC1L_TO_DSP1TXL */
3112#define WM8915_ADC1L_TO_DSP1TXL_MASK 0x0002 /* ADC1L_TO_DSP1TXL */
3113#define WM8915_ADC1L_TO_DSP1TXL_SHIFT 1 /* ADC1L_TO_DSP1TXL */
3114#define WM8915_ADC1L_TO_DSP1TXL_WIDTH 1 /* ADC1L_TO_DSP1TXL */
3115#define WM8915_DACL_TO_DSP1TXL 0x0001 /* DACL_TO_DSP1TXL */
3116#define WM8915_DACL_TO_DSP1TXL_MASK 0x0001 /* DACL_TO_DSP1TXL */
3117#define WM8915_DACL_TO_DSP1TXL_SHIFT 0 /* DACL_TO_DSP1TXL */
3118#define WM8915_DACL_TO_DSP1TXL_WIDTH 1 /* DACL_TO_DSP1TXL */
3119
3120/*
3121 * R1543 (0x607) - DSP1 TX Right Mixer Routing
3122 */
3123#define WM8915_ADC1R_TO_DSP1TXR 0x0002 /* ADC1R_TO_DSP1TXR */
3124#define WM8915_ADC1R_TO_DSP1TXR_MASK 0x0002 /* ADC1R_TO_DSP1TXR */
3125#define WM8915_ADC1R_TO_DSP1TXR_SHIFT 1 /* ADC1R_TO_DSP1TXR */
3126#define WM8915_ADC1R_TO_DSP1TXR_WIDTH 1 /* ADC1R_TO_DSP1TXR */
3127#define WM8915_DACR_TO_DSP1TXR 0x0001 /* DACR_TO_DSP1TXR */
3128#define WM8915_DACR_TO_DSP1TXR_MASK 0x0001 /* DACR_TO_DSP1TXR */
3129#define WM8915_DACR_TO_DSP1TXR_SHIFT 0 /* DACR_TO_DSP1TXR */
3130#define WM8915_DACR_TO_DSP1TXR_WIDTH 1 /* DACR_TO_DSP1TXR */
3131
3132/*
3133 * R1544 (0x608) - DSP2 TX Left Mixer Routing
3134 */
3135#define WM8915_ADC2L_TO_DSP2TXL 0x0002 /* ADC2L_TO_DSP2TXL */
3136#define WM8915_ADC2L_TO_DSP2TXL_MASK 0x0002 /* ADC2L_TO_DSP2TXL */
3137#define WM8915_ADC2L_TO_DSP2TXL_SHIFT 1 /* ADC2L_TO_DSP2TXL */
3138#define WM8915_ADC2L_TO_DSP2TXL_WIDTH 1 /* ADC2L_TO_DSP2TXL */
3139#define WM8915_DACL_TO_DSP2TXL 0x0001 /* DACL_TO_DSP2TXL */
3140#define WM8915_DACL_TO_DSP2TXL_MASK 0x0001 /* DACL_TO_DSP2TXL */
3141#define WM8915_DACL_TO_DSP2TXL_SHIFT 0 /* DACL_TO_DSP2TXL */
3142#define WM8915_DACL_TO_DSP2TXL_WIDTH 1 /* DACL_TO_DSP2TXL */
3143
3144/*
3145 * R1545 (0x609) - DSP2 TX Right Mixer Routing
3146 */
3147#define WM8915_ADC2R_TO_DSP2TXR 0x0002 /* ADC2R_TO_DSP2TXR */
3148#define WM8915_ADC2R_TO_DSP2TXR_MASK 0x0002 /* ADC2R_TO_DSP2TXR */
3149#define WM8915_ADC2R_TO_DSP2TXR_SHIFT 1 /* ADC2R_TO_DSP2TXR */
3150#define WM8915_ADC2R_TO_DSP2TXR_WIDTH 1 /* ADC2R_TO_DSP2TXR */
3151#define WM8915_DACR_TO_DSP2TXR 0x0001 /* DACR_TO_DSP2TXR */
3152#define WM8915_DACR_TO_DSP2TXR_MASK 0x0001 /* DACR_TO_DSP2TXR */
3153#define WM8915_DACR_TO_DSP2TXR_SHIFT 0 /* DACR_TO_DSP2TXR */
3154#define WM8915_DACR_TO_DSP2TXR_WIDTH 1 /* DACR_TO_DSP2TXR */
3155
3156/*
3157 * R1546 (0x60A) - DSP TX Mixer Select
3158 */
3159#define WM8915_DAC_TO_DSPTX_SRC 0x0001 /* DAC_TO_DSPTX_SRC */
3160#define WM8915_DAC_TO_DSPTX_SRC_MASK 0x0001 /* DAC_TO_DSPTX_SRC */
3161#define WM8915_DAC_TO_DSPTX_SRC_SHIFT 0 /* DAC_TO_DSPTX_SRC */
3162#define WM8915_DAC_TO_DSPTX_SRC_WIDTH 1 /* DAC_TO_DSPTX_SRC */
3163
3164/*
3165 * R1552 (0x610) - DAC Softmute
3166 */
3167#define WM8915_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */
3168#define WM8915_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */
3169#define WM8915_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */
3170#define WM8915_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */
3171#define WM8915_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */
3172#define WM8915_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */
3173#define WM8915_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */
3174#define WM8915_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
3175
3176/*
3177 * R1568 (0x620) - Oversampling
3178 */
3179#define WM8915_SPK_OSR128 0x0008 /* SPK_OSR128 */
3180#define WM8915_SPK_OSR128_MASK 0x0008 /* SPK_OSR128 */
3181#define WM8915_SPK_OSR128_SHIFT 3 /* SPK_OSR128 */
3182#define WM8915_SPK_OSR128_WIDTH 1 /* SPK_OSR128 */
3183#define WM8915_DMIC_OSR64 0x0004 /* DMIC_OSR64 */
3184#define WM8915_DMIC_OSR64_MASK 0x0004 /* DMIC_OSR64 */
3185#define WM8915_DMIC_OSR64_SHIFT 2 /* DMIC_OSR64 */
3186#define WM8915_DMIC_OSR64_WIDTH 1 /* DMIC_OSR64 */
3187#define WM8915_ADC_OSR128 0x0002 /* ADC_OSR128 */
3188#define WM8915_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */
3189#define WM8915_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */
3190#define WM8915_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */
3191#define WM8915_DAC_OSR128 0x0001 /* DAC_OSR128 */
3192#define WM8915_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */
3193#define WM8915_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */
3194#define WM8915_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */
3195
3196/*
3197 * R1569 (0x621) - Sidetone
3198 */
3199#define WM8915_ST_LPF 0x1000 /* ST_LPF */
3200#define WM8915_ST_LPF_MASK 0x1000 /* ST_LPF */
3201#define WM8915_ST_LPF_SHIFT 12 /* ST_LPF */
3202#define WM8915_ST_LPF_WIDTH 1 /* ST_LPF */
3203#define WM8915_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */
3204#define WM8915_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */
3205#define WM8915_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */
3206#define WM8915_ST_HPF 0x0040 /* ST_HPF */
3207#define WM8915_ST_HPF_MASK 0x0040 /* ST_HPF */
3208#define WM8915_ST_HPF_SHIFT 6 /* ST_HPF */
3209#define WM8915_ST_HPF_WIDTH 1 /* ST_HPF */
3210#define WM8915_STR_SEL 0x0002 /* STR_SEL */
3211#define WM8915_STR_SEL_MASK 0x0002 /* STR_SEL */
3212#define WM8915_STR_SEL_SHIFT 1 /* STR_SEL */
3213#define WM8915_STR_SEL_WIDTH 1 /* STR_SEL */
3214#define WM8915_STL_SEL 0x0001 /* STL_SEL */
3215#define WM8915_STL_SEL_MASK 0x0001 /* STL_SEL */
3216#define WM8915_STL_SEL_SHIFT 0 /* STL_SEL */
3217#define WM8915_STL_SEL_WIDTH 1 /* STL_SEL */
3218
3219/*
3220 * R1792 (0x700) - GPIO 1
3221 */
3222#define WM8915_GP1_DIR 0x8000 /* GP1_DIR */
3223#define WM8915_GP1_DIR_MASK 0x8000 /* GP1_DIR */
3224#define WM8915_GP1_DIR_SHIFT 15 /* GP1_DIR */
3225#define WM8915_GP1_DIR_WIDTH 1 /* GP1_DIR */
3226#define WM8915_GP1_PU 0x4000 /* GP1_PU */
3227#define WM8915_GP1_PU_MASK 0x4000 /* GP1_PU */
3228#define WM8915_GP1_PU_SHIFT 14 /* GP1_PU */
3229#define WM8915_GP1_PU_WIDTH 1 /* GP1_PU */
3230#define WM8915_GP1_PD 0x2000 /* GP1_PD */
3231#define WM8915_GP1_PD_MASK 0x2000 /* GP1_PD */
3232#define WM8915_GP1_PD_SHIFT 13 /* GP1_PD */
3233#define WM8915_GP1_PD_WIDTH 1 /* GP1_PD */
3234#define WM8915_GP1_POL 0x0400 /* GP1_POL */
3235#define WM8915_GP1_POL_MASK 0x0400 /* GP1_POL */
3236#define WM8915_GP1_POL_SHIFT 10 /* GP1_POL */
3237#define WM8915_GP1_POL_WIDTH 1 /* GP1_POL */
3238#define WM8915_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */
3239#define WM8915_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */
3240#define WM8915_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */
3241#define WM8915_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */
3242#define WM8915_GP1_DB 0x0100 /* GP1_DB */
3243#define WM8915_GP1_DB_MASK 0x0100 /* GP1_DB */
3244#define WM8915_GP1_DB_SHIFT 8 /* GP1_DB */
3245#define WM8915_GP1_DB_WIDTH 1 /* GP1_DB */
3246#define WM8915_GP1_LVL 0x0040 /* GP1_LVL */
3247#define WM8915_GP1_LVL_MASK 0x0040 /* GP1_LVL */
3248#define WM8915_GP1_LVL_SHIFT 6 /* GP1_LVL */
3249#define WM8915_GP1_LVL_WIDTH 1 /* GP1_LVL */
3250#define WM8915_GP1_FN_MASK 0x000F /* GP1_FN - [3:0] */
3251#define WM8915_GP1_FN_SHIFT 0 /* GP1_FN - [3:0] */
3252#define WM8915_GP1_FN_WIDTH 4 /* GP1_FN - [3:0] */
3253
3254/*
3255 * R1793 (0x701) - GPIO 2
3256 */
3257#define WM8915_GP2_DIR 0x8000 /* GP2_DIR */
3258#define WM8915_GP2_DIR_MASK 0x8000 /* GP2_DIR */
3259#define WM8915_GP2_DIR_SHIFT 15 /* GP2_DIR */
3260#define WM8915_GP2_DIR_WIDTH 1 /* GP2_DIR */
3261#define WM8915_GP2_PU 0x4000 /* GP2_PU */
3262#define WM8915_GP2_PU_MASK 0x4000 /* GP2_PU */
3263#define WM8915_GP2_PU_SHIFT 14 /* GP2_PU */
3264#define WM8915_GP2_PU_WIDTH 1 /* GP2_PU */
3265#define WM8915_GP2_PD 0x2000 /* GP2_PD */
3266#define WM8915_GP2_PD_MASK 0x2000 /* GP2_PD */
3267#define WM8915_GP2_PD_SHIFT 13 /* GP2_PD */
3268#define WM8915_GP2_PD_WIDTH 1 /* GP2_PD */
3269#define WM8915_GP2_POL 0x0400 /* GP2_POL */
3270#define WM8915_GP2_POL_MASK 0x0400 /* GP2_POL */
3271#define WM8915_GP2_POL_SHIFT 10 /* GP2_POL */
3272#define WM8915_GP2_POL_WIDTH 1 /* GP2_POL */
3273#define WM8915_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */
3274#define WM8915_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */
3275#define WM8915_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */
3276#define WM8915_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */
3277#define WM8915_GP2_DB 0x0100 /* GP2_DB */
3278#define WM8915_GP2_DB_MASK 0x0100 /* GP2_DB */
3279#define WM8915_GP2_DB_SHIFT 8 /* GP2_DB */
3280#define WM8915_GP2_DB_WIDTH 1 /* GP2_DB */
3281#define WM8915_GP2_LVL 0x0040 /* GP2_LVL */
3282#define WM8915_GP2_LVL_MASK 0x0040 /* GP2_LVL */
3283#define WM8915_GP2_LVL_SHIFT 6 /* GP2_LVL */
3284#define WM8915_GP2_LVL_WIDTH 1 /* GP2_LVL */
3285#define WM8915_GP2_FN_MASK 0x000F /* GP2_FN - [3:0] */
3286#define WM8915_GP2_FN_SHIFT 0 /* GP2_FN - [3:0] */
3287#define WM8915_GP2_FN_WIDTH 4 /* GP2_FN - [3:0] */
3288
3289/*
3290 * R1794 (0x702) - GPIO 3
3291 */
3292#define WM8915_GP3_DIR 0x8000 /* GP3_DIR */
3293#define WM8915_GP3_DIR_MASK 0x8000 /* GP3_DIR */
3294#define WM8915_GP3_DIR_SHIFT 15 /* GP3_DIR */
3295#define WM8915_GP3_DIR_WIDTH 1 /* GP3_DIR */
3296#define WM8915_GP3_PU 0x4000 /* GP3_PU */
3297#define WM8915_GP3_PU_MASK 0x4000 /* GP3_PU */
3298#define WM8915_GP3_PU_SHIFT 14 /* GP3_PU */
3299#define WM8915_GP3_PU_WIDTH 1 /* GP3_PU */
3300#define WM8915_GP3_PD 0x2000 /* GP3_PD */
3301#define WM8915_GP3_PD_MASK 0x2000 /* GP3_PD */
3302#define WM8915_GP3_PD_SHIFT 13 /* GP3_PD */
3303#define WM8915_GP3_PD_WIDTH 1 /* GP3_PD */
3304#define WM8915_GP3_POL 0x0400 /* GP3_POL */
3305#define WM8915_GP3_POL_MASK 0x0400 /* GP3_POL */
3306#define WM8915_GP3_POL_SHIFT 10 /* GP3_POL */
3307#define WM8915_GP3_POL_WIDTH 1 /* GP3_POL */
3308#define WM8915_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */
3309#define WM8915_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */
3310#define WM8915_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */
3311#define WM8915_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */
3312#define WM8915_GP3_DB 0x0100 /* GP3_DB */
3313#define WM8915_GP3_DB_MASK 0x0100 /* GP3_DB */
3314#define WM8915_GP3_DB_SHIFT 8 /* GP3_DB */
3315#define WM8915_GP3_DB_WIDTH 1 /* GP3_DB */
3316#define WM8915_GP3_LVL 0x0040 /* GP3_LVL */
3317#define WM8915_GP3_LVL_MASK 0x0040 /* GP3_LVL */
3318#define WM8915_GP3_LVL_SHIFT 6 /* GP3_LVL */
3319#define WM8915_GP3_LVL_WIDTH 1 /* GP3_LVL */
3320#define WM8915_GP3_FN_MASK 0x000F /* GP3_FN - [3:0] */
3321#define WM8915_GP3_FN_SHIFT 0 /* GP3_FN - [3:0] */
3322#define WM8915_GP3_FN_WIDTH 4 /* GP3_FN - [3:0] */
3323
3324/*
3325 * R1795 (0x703) - GPIO 4
3326 */
3327#define WM8915_GP4_DIR 0x8000 /* GP4_DIR */
3328#define WM8915_GP4_DIR_MASK 0x8000 /* GP4_DIR */
3329#define WM8915_GP4_DIR_SHIFT 15 /* GP4_DIR */
3330#define WM8915_GP4_DIR_WIDTH 1 /* GP4_DIR */
3331#define WM8915_GP4_PU 0x4000 /* GP4_PU */
3332#define WM8915_GP4_PU_MASK 0x4000 /* GP4_PU */
3333#define WM8915_GP4_PU_SHIFT 14 /* GP4_PU */
3334#define WM8915_GP4_PU_WIDTH 1 /* GP4_PU */
3335#define WM8915_GP4_PD 0x2000 /* GP4_PD */
3336#define WM8915_GP4_PD_MASK 0x2000 /* GP4_PD */
3337#define WM8915_GP4_PD_SHIFT 13 /* GP4_PD */
3338#define WM8915_GP4_PD_WIDTH 1 /* GP4_PD */
3339#define WM8915_GP4_POL 0x0400 /* GP4_POL */
3340#define WM8915_GP4_POL_MASK 0x0400 /* GP4_POL */
3341#define WM8915_GP4_POL_SHIFT 10 /* GP4_POL */
3342#define WM8915_GP4_POL_WIDTH 1 /* GP4_POL */
3343#define WM8915_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */
3344#define WM8915_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */
3345#define WM8915_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */
3346#define WM8915_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */
3347#define WM8915_GP4_DB 0x0100 /* GP4_DB */
3348#define WM8915_GP4_DB_MASK 0x0100 /* GP4_DB */
3349#define WM8915_GP4_DB_SHIFT 8 /* GP4_DB */
3350#define WM8915_GP4_DB_WIDTH 1 /* GP4_DB */
3351#define WM8915_GP4_LVL 0x0040 /* GP4_LVL */
3352#define WM8915_GP4_LVL_MASK 0x0040 /* GP4_LVL */
3353#define WM8915_GP4_LVL_SHIFT 6 /* GP4_LVL */
3354#define WM8915_GP4_LVL_WIDTH 1 /* GP4_LVL */
3355#define WM8915_GP4_FN_MASK 0x000F /* GP4_FN - [3:0] */
3356#define WM8915_GP4_FN_SHIFT 0 /* GP4_FN - [3:0] */
3357#define WM8915_GP4_FN_WIDTH 4 /* GP4_FN - [3:0] */
3358
3359/*
3360 * R1796 (0x704) - GPIO 5
3361 */
3362#define WM8915_GP5_DIR 0x8000 /* GP5_DIR */
3363#define WM8915_GP5_DIR_MASK 0x8000 /* GP5_DIR */
3364#define WM8915_GP5_DIR_SHIFT 15 /* GP5_DIR */
3365#define WM8915_GP5_DIR_WIDTH 1 /* GP5_DIR */
3366#define WM8915_GP5_PU 0x4000 /* GP5_PU */
3367#define WM8915_GP5_PU_MASK 0x4000 /* GP5_PU */
3368#define WM8915_GP5_PU_SHIFT 14 /* GP5_PU */
3369#define WM8915_GP5_PU_WIDTH 1 /* GP5_PU */
3370#define WM8915_GP5_PD 0x2000 /* GP5_PD */
3371#define WM8915_GP5_PD_MASK 0x2000 /* GP5_PD */
3372#define WM8915_GP5_PD_SHIFT 13 /* GP5_PD */
3373#define WM8915_GP5_PD_WIDTH 1 /* GP5_PD */
3374#define WM8915_GP5_POL 0x0400 /* GP5_POL */
3375#define WM8915_GP5_POL_MASK 0x0400 /* GP5_POL */
3376#define WM8915_GP5_POL_SHIFT 10 /* GP5_POL */
3377#define WM8915_GP5_POL_WIDTH 1 /* GP5_POL */
3378#define WM8915_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */
3379#define WM8915_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */
3380#define WM8915_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */
3381#define WM8915_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */
3382#define WM8915_GP5_DB 0x0100 /* GP5_DB */
3383#define WM8915_GP5_DB_MASK 0x0100 /* GP5_DB */
3384#define WM8915_GP5_DB_SHIFT 8 /* GP5_DB */
3385#define WM8915_GP5_DB_WIDTH 1 /* GP5_DB */
3386#define WM8915_GP5_LVL 0x0040 /* GP5_LVL */
3387#define WM8915_GP5_LVL_MASK 0x0040 /* GP5_LVL */
3388#define WM8915_GP5_LVL_SHIFT 6 /* GP5_LVL */
3389#define WM8915_GP5_LVL_WIDTH 1 /* GP5_LVL */
3390#define WM8915_GP5_FN_MASK 0x000F /* GP5_FN - [3:0] */
3391#define WM8915_GP5_FN_SHIFT 0 /* GP5_FN - [3:0] */
3392#define WM8915_GP5_FN_WIDTH 4 /* GP5_FN - [3:0] */
3393
3394/*
3395 * R1824 (0x720) - Pull Control (1)
3396 */
3397#define WM8915_DMICDAT2_PD 0x1000 /* DMICDAT2_PD */
3398#define WM8915_DMICDAT2_PD_MASK 0x1000 /* DMICDAT2_PD */
3399#define WM8915_DMICDAT2_PD_SHIFT 12 /* DMICDAT2_PD */
3400#define WM8915_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
3401#define WM8915_DMICDAT1_PD 0x0400 /* DMICDAT1_PD */
3402#define WM8915_DMICDAT1_PD_MASK 0x0400 /* DMICDAT1_PD */
3403#define WM8915_DMICDAT1_PD_SHIFT 10 /* DMICDAT1_PD */
3404#define WM8915_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
3405#define WM8915_MCLK2_PU 0x0200 /* MCLK2_PU */
3406#define WM8915_MCLK2_PU_MASK 0x0200 /* MCLK2_PU */
3407#define WM8915_MCLK2_PU_SHIFT 9 /* MCLK2_PU */
3408#define WM8915_MCLK2_PU_WIDTH 1 /* MCLK2_PU */
3409#define WM8915_MCLK2_PD 0x0100 /* MCLK2_PD */
3410#define WM8915_MCLK2_PD_MASK 0x0100 /* MCLK2_PD */
3411#define WM8915_MCLK2_PD_SHIFT 8 /* MCLK2_PD */
3412#define WM8915_MCLK2_PD_WIDTH 1 /* MCLK2_PD */
3413#define WM8915_MCLK1_PU 0x0080 /* MCLK1_PU */
3414#define WM8915_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */
3415#define WM8915_MCLK1_PU_SHIFT 7 /* MCLK1_PU */
3416#define WM8915_MCLK1_PU_WIDTH 1 /* MCLK1_PU */
3417#define WM8915_MCLK1_PD 0x0040 /* MCLK1_PD */
3418#define WM8915_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */
3419#define WM8915_MCLK1_PD_SHIFT 6 /* MCLK1_PD */
3420#define WM8915_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
3421#define WM8915_DACDAT1_PU 0x0020 /* DACDAT1_PU */
3422#define WM8915_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */
3423#define WM8915_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */
3424#define WM8915_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */
3425#define WM8915_DACDAT1_PD 0x0010 /* DACDAT1_PD */
3426#define WM8915_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */
3427#define WM8915_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */
3428#define WM8915_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */
3429#define WM8915_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */
3430#define WM8915_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */
3431#define WM8915_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */
3432#define WM8915_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */
3433#define WM8915_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */
3434#define WM8915_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */
3435#define WM8915_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */
3436#define WM8915_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */
3437#define WM8915_BCLK1_PU 0x0002 /* BCLK1_PU */
3438#define WM8915_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */
3439#define WM8915_BCLK1_PU_SHIFT 1 /* BCLK1_PU */
3440#define WM8915_BCLK1_PU_WIDTH 1 /* BCLK1_PU */
3441#define WM8915_BCLK1_PD 0x0001 /* BCLK1_PD */
3442#define WM8915_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */
3443#define WM8915_BCLK1_PD_SHIFT 0 /* BCLK1_PD */
3444#define WM8915_BCLK1_PD_WIDTH 1 /* BCLK1_PD */
3445
3446/*
3447 * R1825 (0x721) - Pull Control (2)
3448 */
3449#define WM8915_LDO1ENA_PD 0x0100 /* LDO1ENA_PD */
3450#define WM8915_LDO1ENA_PD_MASK 0x0100 /* LDO1ENA_PD */
3451#define WM8915_LDO1ENA_PD_SHIFT 8 /* LDO1ENA_PD */
3452#define WM8915_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */
3453#define WM8915_ADDR_PD 0x0040 /* ADDR_PD */
3454#define WM8915_ADDR_PD_MASK 0x0040 /* ADDR_PD */
3455#define WM8915_ADDR_PD_SHIFT 6 /* ADDR_PD */
3456#define WM8915_ADDR_PD_WIDTH 1 /* ADDR_PD */
3457#define WM8915_DACDAT2_PU 0x0020 /* DACDAT2_PU */
3458#define WM8915_DACDAT2_PU_MASK 0x0020 /* DACDAT2_PU */
3459#define WM8915_DACDAT2_PU_SHIFT 5 /* DACDAT2_PU */
3460#define WM8915_DACDAT2_PU_WIDTH 1 /* DACDAT2_PU */
3461#define WM8915_DACDAT2_PD 0x0010 /* DACDAT2_PD */
3462#define WM8915_DACDAT2_PD_MASK 0x0010 /* DACDAT2_PD */
3463#define WM8915_DACDAT2_PD_SHIFT 4 /* DACDAT2_PD */
3464#define WM8915_DACDAT2_PD_WIDTH 1 /* DACDAT2_PD */
3465#define WM8915_DACLRCLK2_PU 0x0008 /* DACLRCLK2_PU */
3466#define WM8915_DACLRCLK2_PU_MASK 0x0008 /* DACLRCLK2_PU */
3467#define WM8915_DACLRCLK2_PU_SHIFT 3 /* DACLRCLK2_PU */
3468#define WM8915_DACLRCLK2_PU_WIDTH 1 /* DACLRCLK2_PU */
3469#define WM8915_DACLRCLK2_PD 0x0004 /* DACLRCLK2_PD */
3470#define WM8915_DACLRCLK2_PD_MASK 0x0004 /* DACLRCLK2_PD */
3471#define WM8915_DACLRCLK2_PD_SHIFT 2 /* DACLRCLK2_PD */
3472#define WM8915_DACLRCLK2_PD_WIDTH 1 /* DACLRCLK2_PD */
3473#define WM8915_BCLK2_PU 0x0002 /* BCLK2_PU */
3474#define WM8915_BCLK2_PU_MASK 0x0002 /* BCLK2_PU */
3475#define WM8915_BCLK2_PU_SHIFT 1 /* BCLK2_PU */
3476#define WM8915_BCLK2_PU_WIDTH 1 /* BCLK2_PU */
3477#define WM8915_BCLK2_PD 0x0001 /* BCLK2_PD */
3478#define WM8915_BCLK2_PD_MASK 0x0001 /* BCLK2_PD */
3479#define WM8915_BCLK2_PD_SHIFT 0 /* BCLK2_PD */
3480#define WM8915_BCLK2_PD_WIDTH 1 /* BCLK2_PD */
3481
3482/*
3483 * R1840 (0x730) - Interrupt Status 1
3484 */
3485#define WM8915_GP5_EINT 0x0010 /* GP5_EINT */
3486#define WM8915_GP5_EINT_MASK 0x0010 /* GP5_EINT */
3487#define WM8915_GP5_EINT_SHIFT 4 /* GP5_EINT */
3488#define WM8915_GP5_EINT_WIDTH 1 /* GP5_EINT */
3489#define WM8915_GP4_EINT 0x0008 /* GP4_EINT */
3490#define WM8915_GP4_EINT_MASK 0x0008 /* GP4_EINT */
3491#define WM8915_GP4_EINT_SHIFT 3 /* GP4_EINT */
3492#define WM8915_GP4_EINT_WIDTH 1 /* GP4_EINT */
3493#define WM8915_GP3_EINT 0x0004 /* GP3_EINT */
3494#define WM8915_GP3_EINT_MASK 0x0004 /* GP3_EINT */
3495#define WM8915_GP3_EINT_SHIFT 2 /* GP3_EINT */
3496#define WM8915_GP3_EINT_WIDTH 1 /* GP3_EINT */
3497#define WM8915_GP2_EINT 0x0002 /* GP2_EINT */
3498#define WM8915_GP2_EINT_MASK 0x0002 /* GP2_EINT */
3499#define WM8915_GP2_EINT_SHIFT 1 /* GP2_EINT */
3500#define WM8915_GP2_EINT_WIDTH 1 /* GP2_EINT */
3501#define WM8915_GP1_EINT 0x0001 /* GP1_EINT */
3502#define WM8915_GP1_EINT_MASK 0x0001 /* GP1_EINT */
3503#define WM8915_GP1_EINT_SHIFT 0 /* GP1_EINT */
3504#define WM8915_GP1_EINT_WIDTH 1 /* GP1_EINT */
3505
3506/*
3507 * R1841 (0x731) - Interrupt Status 2
3508 */
3509#define WM8915_DCS_DONE_23_EINT 0x1000 /* DCS_DONE_23_EINT */
3510#define WM8915_DCS_DONE_23_EINT_MASK 0x1000 /* DCS_DONE_23_EINT */
3511#define WM8915_DCS_DONE_23_EINT_SHIFT 12 /* DCS_DONE_23_EINT */
3512#define WM8915_DCS_DONE_23_EINT_WIDTH 1 /* DCS_DONE_23_EINT */
3513#define WM8915_DCS_DONE_01_EINT 0x0800 /* DCS_DONE_01_EINT */
3514#define WM8915_DCS_DONE_01_EINT_MASK 0x0800 /* DCS_DONE_01_EINT */
3515#define WM8915_DCS_DONE_01_EINT_SHIFT 11 /* DCS_DONE_01_EINT */
3516#define WM8915_DCS_DONE_01_EINT_WIDTH 1 /* DCS_DONE_01_EINT */
3517#define WM8915_WSEQ_DONE_EINT 0x0400 /* WSEQ_DONE_EINT */
3518#define WM8915_WSEQ_DONE_EINT_MASK 0x0400 /* WSEQ_DONE_EINT */
3519#define WM8915_WSEQ_DONE_EINT_SHIFT 10 /* WSEQ_DONE_EINT */
3520#define WM8915_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */
3521#define WM8915_FIFOS_ERR_EINT 0x0200 /* FIFOS_ERR_EINT */
3522#define WM8915_FIFOS_ERR_EINT_MASK 0x0200 /* FIFOS_ERR_EINT */
3523#define WM8915_FIFOS_ERR_EINT_SHIFT 9 /* FIFOS_ERR_EINT */
3524#define WM8915_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */
3525#define WM8915_DSP2DRC_SIG_DET_EINT 0x0080 /* DSP2DRC_SIG_DET_EINT */
3526#define WM8915_DSP2DRC_SIG_DET_EINT_MASK 0x0080 /* DSP2DRC_SIG_DET_EINT */
3527#define WM8915_DSP2DRC_SIG_DET_EINT_SHIFT 7 /* DSP2DRC_SIG_DET_EINT */
3528#define WM8915_DSP2DRC_SIG_DET_EINT_WIDTH 1 /* DSP2DRC_SIG_DET_EINT */
3529#define WM8915_DSP1DRC_SIG_DET_EINT 0x0040 /* DSP1DRC_SIG_DET_EINT */
3530#define WM8915_DSP1DRC_SIG_DET_EINT_MASK 0x0040 /* DSP1DRC_SIG_DET_EINT */
3531#define WM8915_DSP1DRC_SIG_DET_EINT_SHIFT 6 /* DSP1DRC_SIG_DET_EINT */
3532#define WM8915_DSP1DRC_SIG_DET_EINT_WIDTH 1 /* DSP1DRC_SIG_DET_EINT */
3533#define WM8915_FLL_SW_CLK_DONE_EINT 0x0008 /* FLL_SW_CLK_DONE_EINT */
3534#define WM8915_FLL_SW_CLK_DONE_EINT_MASK 0x0008 /* FLL_SW_CLK_DONE_EINT */
3535#define WM8915_FLL_SW_CLK_DONE_EINT_SHIFT 3 /* FLL_SW_CLK_DONE_EINT */
3536#define WM8915_FLL_SW_CLK_DONE_EINT_WIDTH 1 /* FLL_SW_CLK_DONE_EINT */
3537#define WM8915_FLL_LOCK_EINT 0x0004 /* FLL_LOCK_EINT */
3538#define WM8915_FLL_LOCK_EINT_MASK 0x0004 /* FLL_LOCK_EINT */
3539#define WM8915_FLL_LOCK_EINT_SHIFT 2 /* FLL_LOCK_EINT */
3540#define WM8915_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */
3541#define WM8915_HP_DONE_EINT 0x0002 /* HP_DONE_EINT */
3542#define WM8915_HP_DONE_EINT_MASK 0x0002 /* HP_DONE_EINT */
3543#define WM8915_HP_DONE_EINT_SHIFT 1 /* HP_DONE_EINT */
3544#define WM8915_HP_DONE_EINT_WIDTH 1 /* HP_DONE_EINT */
3545#define WM8915_MICD_EINT 0x0001 /* MICD_EINT */
3546#define WM8915_MICD_EINT_MASK 0x0001 /* MICD_EINT */
3547#define WM8915_MICD_EINT_SHIFT 0 /* MICD_EINT */
3548#define WM8915_MICD_EINT_WIDTH 1 /* MICD_EINT */
3549
3550/*
3551 * R1842 (0x732) - Interrupt Raw Status 2
3552 */
3553#define WM8915_DCS_DONE_23_STS 0x1000 /* DCS_DONE_23_STS */
3554#define WM8915_DCS_DONE_23_STS_MASK 0x1000 /* DCS_DONE_23_STS */
3555#define WM8915_DCS_DONE_23_STS_SHIFT 12 /* DCS_DONE_23_STS */
3556#define WM8915_DCS_DONE_23_STS_WIDTH 1 /* DCS_DONE_23_STS */
3557#define WM8915_DCS_DONE_01_STS 0x0800 /* DCS_DONE_01_STS */
3558#define WM8915_DCS_DONE_01_STS_MASK 0x0800 /* DCS_DONE_01_STS */
3559#define WM8915_DCS_DONE_01_STS_SHIFT 11 /* DCS_DONE_01_STS */
3560#define WM8915_DCS_DONE_01_STS_WIDTH 1 /* DCS_DONE_01_STS */
3561#define WM8915_WSEQ_DONE_STS 0x0400 /* WSEQ_DONE_STS */
3562#define WM8915_WSEQ_DONE_STS_MASK 0x0400 /* WSEQ_DONE_STS */
3563#define WM8915_WSEQ_DONE_STS_SHIFT 10 /* WSEQ_DONE_STS */
3564#define WM8915_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */
3565#define WM8915_FIFOS_ERR_STS 0x0200 /* FIFOS_ERR_STS */
3566#define WM8915_FIFOS_ERR_STS_MASK 0x0200 /* FIFOS_ERR_STS */
3567#define WM8915_FIFOS_ERR_STS_SHIFT 9 /* FIFOS_ERR_STS */
3568#define WM8915_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */
3569#define WM8915_DSP2DRC_SIG_DET_STS 0x0080 /* DSP2DRC_SIG_DET_STS */
3570#define WM8915_DSP2DRC_SIG_DET_STS_MASK 0x0080 /* DSP2DRC_SIG_DET_STS */
3571#define WM8915_DSP2DRC_SIG_DET_STS_SHIFT 7 /* DSP2DRC_SIG_DET_STS */
3572#define WM8915_DSP2DRC_SIG_DET_STS_WIDTH 1 /* DSP2DRC_SIG_DET_STS */
3573#define WM8915_DSP1DRC_SIG_DET_STS 0x0040 /* DSP1DRC_SIG_DET_STS */
3574#define WM8915_DSP1DRC_SIG_DET_STS_MASK 0x0040 /* DSP1DRC_SIG_DET_STS */
3575#define WM8915_DSP1DRC_SIG_DET_STS_SHIFT 6 /* DSP1DRC_SIG_DET_STS */
3576#define WM8915_DSP1DRC_SIG_DET_STS_WIDTH 1 /* DSP1DRC_SIG_DET_STS */
3577#define WM8915_FLL_LOCK_STS 0x0004 /* FLL_LOCK_STS */
3578#define WM8915_FLL_LOCK_STS_MASK 0x0004 /* FLL_LOCK_STS */
3579#define WM8915_FLL_LOCK_STS_SHIFT 2 /* FLL_LOCK_STS */
3580#define WM8915_FLL_LOCK_STS_WIDTH 1 /* FLL_LOCK_STS */
3581
3582/*
3583 * R1848 (0x738) - Interrupt Status 1 Mask
3584 */
3585#define WM8915_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
3586#define WM8915_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
3587#define WM8915_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
3588#define WM8915_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
3589#define WM8915_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
3590#define WM8915_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
3591#define WM8915_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
3592#define WM8915_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
3593#define WM8915_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
3594#define WM8915_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
3595#define WM8915_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
3596#define WM8915_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
3597#define WM8915_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
3598#define WM8915_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
3599#define WM8915_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
3600#define WM8915_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
3601#define WM8915_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
3602#define WM8915_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
3603#define WM8915_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
3604#define WM8915_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
3605
3606/*
3607 * R1849 (0x739) - Interrupt Status 2 Mask
3608 */
3609#define WM8915_IM_DCS_DONE_23_EINT 0x1000 /* IM_DCS_DONE_23_EINT */
3610#define WM8915_IM_DCS_DONE_23_EINT_MASK 0x1000 /* IM_DCS_DONE_23_EINT */
3611#define WM8915_IM_DCS_DONE_23_EINT_SHIFT 12 /* IM_DCS_DONE_23_EINT */
3612#define WM8915_IM_DCS_DONE_23_EINT_WIDTH 1 /* IM_DCS_DONE_23_EINT */
3613#define WM8915_IM_DCS_DONE_01_EINT 0x0800 /* IM_DCS_DONE_01_EINT */
3614#define WM8915_IM_DCS_DONE_01_EINT_MASK 0x0800 /* IM_DCS_DONE_01_EINT */
3615#define WM8915_IM_DCS_DONE_01_EINT_SHIFT 11 /* IM_DCS_DONE_01_EINT */
3616#define WM8915_IM_DCS_DONE_01_EINT_WIDTH 1 /* IM_DCS_DONE_01_EINT */
3617#define WM8915_IM_WSEQ_DONE_EINT 0x0400 /* IM_WSEQ_DONE_EINT */
3618#define WM8915_IM_WSEQ_DONE_EINT_MASK 0x0400 /* IM_WSEQ_DONE_EINT */
3619#define WM8915_IM_WSEQ_DONE_EINT_SHIFT 10 /* IM_WSEQ_DONE_EINT */
3620#define WM8915_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */
3621#define WM8915_IM_FIFOS_ERR_EINT 0x0200 /* IM_FIFOS_ERR_EINT */
3622#define WM8915_IM_FIFOS_ERR_EINT_MASK 0x0200 /* IM_FIFOS_ERR_EINT */
3623#define WM8915_IM_FIFOS_ERR_EINT_SHIFT 9 /* IM_FIFOS_ERR_EINT */
3624#define WM8915_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */
3625#define WM8915_IM_DSP2DRC_SIG_DET_EINT 0x0080 /* IM_DSP2DRC_SIG_DET_EINT */
3626#define WM8915_IM_DSP2DRC_SIG_DET_EINT_MASK 0x0080 /* IM_DSP2DRC_SIG_DET_EINT */
3627#define WM8915_IM_DSP2DRC_SIG_DET_EINT_SHIFT 7 /* IM_DSP2DRC_SIG_DET_EINT */
3628#define WM8915_IM_DSP2DRC_SIG_DET_EINT_WIDTH 1 /* IM_DSP2DRC_SIG_DET_EINT */
3629#define WM8915_IM_DSP1DRC_SIG_DET_EINT 0x0040 /* IM_DSP1DRC_SIG_DET_EINT */
3630#define WM8915_IM_DSP1DRC_SIG_DET_EINT_MASK 0x0040 /* IM_DSP1DRC_SIG_DET_EINT */
3631#define WM8915_IM_DSP1DRC_SIG_DET_EINT_SHIFT 6 /* IM_DSP1DRC_SIG_DET_EINT */
3632#define WM8915_IM_DSP1DRC_SIG_DET_EINT_WIDTH 1 /* IM_DSP1DRC_SIG_DET_EINT */
3633#define WM8915_IM_FLL_SW_CLK_DONE_EINT 0x0008 /* IM_FLL_SW_CLK_DONE_EINT */
3634#define WM8915_IM_FLL_SW_CLK_DONE_EINT_MASK 0x0008 /* IM_FLL_SW_CLK_DONE_EINT */
3635#define WM8915_IM_FLL_SW_CLK_DONE_EINT_SHIFT 3 /* IM_FLL_SW_CLK_DONE_EINT */
3636#define WM8915_IM_FLL_SW_CLK_DONE_EINT_WIDTH 1 /* IM_FLL_SW_CLK_DONE_EINT */
3637#define WM8915_IM_FLL_LOCK_EINT 0x0004 /* IM_FLL_LOCK_EINT */
3638#define WM8915_IM_FLL_LOCK_EINT_MASK 0x0004 /* IM_FLL_LOCK_EINT */
3639#define WM8915_IM_FLL_LOCK_EINT_SHIFT 2 /* IM_FLL_LOCK_EINT */
3640#define WM8915_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */
3641#define WM8915_IM_HP_DONE_EINT 0x0002 /* IM_HP_DONE_EINT */
3642#define WM8915_IM_HP_DONE_EINT_MASK 0x0002 /* IM_HP_DONE_EINT */
3643#define WM8915_IM_HP_DONE_EINT_SHIFT 1 /* IM_HP_DONE_EINT */
3644#define WM8915_IM_HP_DONE_EINT_WIDTH 1 /* IM_HP_DONE_EINT */
3645#define WM8915_IM_MICD_EINT 0x0001 /* IM_MICD_EINT */
3646#define WM8915_IM_MICD_EINT_MASK 0x0001 /* IM_MICD_EINT */
3647#define WM8915_IM_MICD_EINT_SHIFT 0 /* IM_MICD_EINT */
3648#define WM8915_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */
3649
3650/*
3651 * R1856 (0x740) - Interrupt Control
3652 */
3653#define WM8915_IM_IRQ 0x0001 /* IM_IRQ */
3654#define WM8915_IM_IRQ_MASK 0x0001 /* IM_IRQ */
3655#define WM8915_IM_IRQ_SHIFT 0 /* IM_IRQ */
3656#define WM8915_IM_IRQ_WIDTH 1 /* IM_IRQ */
3657
3658/*
3659 * R2048 (0x800) - Left PDM Speaker
3660 */
3661#define WM8915_SPKL_ENA 0x0010 /* SPKL_ENA */
3662#define WM8915_SPKL_ENA_MASK 0x0010 /* SPKL_ENA */
3663#define WM8915_SPKL_ENA_SHIFT 4 /* SPKL_ENA */
3664#define WM8915_SPKL_ENA_WIDTH 1 /* SPKL_ENA */
3665#define WM8915_SPKL_MUTE 0x0008 /* SPKL_MUTE */
3666#define WM8915_SPKL_MUTE_MASK 0x0008 /* SPKL_MUTE */
3667#define WM8915_SPKL_MUTE_SHIFT 3 /* SPKL_MUTE */
3668#define WM8915_SPKL_MUTE_WIDTH 1 /* SPKL_MUTE */
3669#define WM8915_SPKL_MUTE_ZC 0x0004 /* SPKL_MUTE_ZC */
3670#define WM8915_SPKL_MUTE_ZC_MASK 0x0004 /* SPKL_MUTE_ZC */
3671#define WM8915_SPKL_MUTE_ZC_SHIFT 2 /* SPKL_MUTE_ZC */
3672#define WM8915_SPKL_MUTE_ZC_WIDTH 1 /* SPKL_MUTE_ZC */
3673#define WM8915_SPKL_SRC_MASK 0x0003 /* SPKL_SRC - [1:0] */
3674#define WM8915_SPKL_SRC_SHIFT 0 /* SPKL_SRC - [1:0] */
3675#define WM8915_SPKL_SRC_WIDTH 2 /* SPKL_SRC - [1:0] */
3676
3677/*
3678 * R2049 (0x801) - Right PDM Speaker
3679 */
3680#define WM8915_SPKR_ENA 0x0010 /* SPKR_ENA */
3681#define WM8915_SPKR_ENA_MASK 0x0010 /* SPKR_ENA */
3682#define WM8915_SPKR_ENA_SHIFT 4 /* SPKR_ENA */
3683#define WM8915_SPKR_ENA_WIDTH 1 /* SPKR_ENA */
3684#define WM8915_SPKR_MUTE 0x0008 /* SPKR_MUTE */
3685#define WM8915_SPKR_MUTE_MASK 0x0008 /* SPKR_MUTE */
3686#define WM8915_SPKR_MUTE_SHIFT 3 /* SPKR_MUTE */
3687#define WM8915_SPKR_MUTE_WIDTH 1 /* SPKR_MUTE */
3688#define WM8915_SPKR_MUTE_ZC 0x0004 /* SPKR_MUTE_ZC */
3689#define WM8915_SPKR_MUTE_ZC_MASK 0x0004 /* SPKR_MUTE_ZC */
3690#define WM8915_SPKR_MUTE_ZC_SHIFT 2 /* SPKR_MUTE_ZC */
3691#define WM8915_SPKR_MUTE_ZC_WIDTH 1 /* SPKR_MUTE_ZC */
3692#define WM8915_SPKR_SRC_MASK 0x0003 /* SPKR_SRC - [1:0] */
3693#define WM8915_SPKR_SRC_SHIFT 0 /* SPKR_SRC - [1:0] */
3694#define WM8915_SPKR_SRC_WIDTH 2 /* SPKR_SRC - [1:0] */
3695
3696/*
3697 * R2050 (0x802) - PDM Speaker Mute Sequence
3698 */
3699#define WM8915_SPK_MUTE_ENDIAN 0x0100 /* SPK_MUTE_ENDIAN */
3700#define WM8915_SPK_MUTE_ENDIAN_MASK 0x0100 /* SPK_MUTE_ENDIAN */
3701#define WM8915_SPK_MUTE_ENDIAN_SHIFT 8 /* SPK_MUTE_ENDIAN */
3702#define WM8915_SPK_MUTE_ENDIAN_WIDTH 1 /* SPK_MUTE_ENDIAN */
3703#define WM8915_SPK_MUTE_SEQ1_MASK 0x00FF /* SPK_MUTE_SEQ1 - [7:0] */
3704#define WM8915_SPK_MUTE_SEQ1_SHIFT 0 /* SPK_MUTE_SEQ1 - [7:0] */
3705#define WM8915_SPK_MUTE_SEQ1_WIDTH 8 /* SPK_MUTE_SEQ1 - [7:0] */
3706
3707/*
3708 * R2051 (0x803) - PDM Speaker Volume
3709 */
3710#define WM8915_SPKR_VOL_MASK 0x00F0 /* SPKR_VOL - [7:4] */
3711#define WM8915_SPKR_VOL_SHIFT 4 /* SPKR_VOL - [7:4] */
3712#define WM8915_SPKR_VOL_WIDTH 4 /* SPKR_VOL - [7:4] */
3713#define WM8915_SPKL_VOL_MASK 0x000F /* SPKL_VOL - [3:0] */
3714#define WM8915_SPKL_VOL_SHIFT 0 /* SPKL_VOL - [3:0] */
3715#define WM8915_SPKL_VOL_WIDTH 4 /* SPKL_VOL - [3:0] */
3716
3717#endif
diff --git a/sound/soc/codecs/wm8994.c b/sound/soc/codecs/wm8994.c
index 09e680ae88b2..b393f9fac97a 100644
--- a/sound/soc/codecs/wm8994.c
+++ b/sound/soc/codecs/wm8994.c
@@ -2981,6 +2981,7 @@ static int wm8994_codec_probe(struct snd_soc_codec *codec)
2981 wm8994->hubs.dcs_readback_mode = 1; 2981 wm8994->hubs.dcs_readback_mode = 1;
2982 break; 2982 break;
2983 } 2983 }
2984 break;
2984 2985
2985 case WM8958: 2986 case WM8958:
2986 wm8994->hubs.dcs_readback_mode = 1; 2987 wm8994->hubs.dcs_readback_mode = 1;
diff --git a/sound/soc/codecs/wm8996.c b/sound/soc/codecs/wm8996.c
new file mode 100644
index 000000000000..ab8e9d1aaff0
--- /dev/null
+++ b/sound/soc/codecs/wm8996.c
@@ -0,0 +1,2994 @@
1/*
2 * wm8996.c - WM8996 audio codec interface
3 *
4 * Copyright 2011 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/completion.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
20#include <linux/gpio.h>
21#include <linux/i2c.h>
22#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24#include <linux/workqueue.h>
25#include <sound/core.h>
26#include <sound/jack.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32#include <trace/events/asoc.h>
33
34#include <sound/wm8996.h>
35#include "wm8996.h"
36
37#define WM8996_AIFS 2
38
39#define HPOUT1L 1
40#define HPOUT1R 2
41#define HPOUT2L 4
42#define HPOUT2R 8
43
44#define WM8996_NUM_SUPPLIES 4
45static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
46 "DBVDD",
47 "AVDD1",
48 "AVDD2",
49 "CPVDD",
50};
51
52struct wm8996_priv {
53 struct snd_soc_codec *codec;
54
55 int ldo1ena;
56
57 int sysclk;
58 int sysclk_src;
59
60 int fll_src;
61 int fll_fref;
62 int fll_fout;
63
64 struct completion fll_lock;
65
66 u16 dcs_pending;
67 struct completion dcs_done;
68
69 u16 hpout_ena;
70 u16 hpout_pending;
71
72 struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
73 struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
74
75 struct wm8996_pdata pdata;
76
77 int rx_rate[WM8996_AIFS];
78 int bclk_rate[WM8996_AIFS];
79
80 /* Platform dependant ReTune mobile configuration */
81 int num_retune_mobile_texts;
82 const char **retune_mobile_texts;
83 int retune_mobile_cfg[2];
84 struct soc_enum retune_mobile_enum;
85
86 struct snd_soc_jack *jack;
87 bool detecting;
88 bool jack_mic;
89 wm8996_polarity_fn polarity_cb;
90
91#ifdef CONFIG_GPIOLIB
92 struct gpio_chip gpio_chip;
93#endif
94};
95
96/* We can't use the same notifier block for more than one supply and
97 * there's no way I can see to get from a callback to the caller
98 * except container_of().
99 */
100#define WM8996_REGULATOR_EVENT(n) \
101static int wm8996_regulator_event_##n(struct notifier_block *nb, \
102 unsigned long event, void *data) \
103{ \
104 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
105 disable_nb[n]); \
106 if (event & REGULATOR_EVENT_DISABLE) { \
107 wm8996->codec->cache_sync = 1; \
108 } \
109 return 0; \
110}
111
112WM8996_REGULATOR_EVENT(0)
113WM8996_REGULATOR_EVENT(1)
114WM8996_REGULATOR_EVENT(2)
115WM8996_REGULATOR_EVENT(3)
116
117static const u16 wm8996_reg[WM8996_MAX_REGISTER] = {
118 [WM8996_SOFTWARE_RESET] = 0x8996,
119 [WM8996_POWER_MANAGEMENT_7] = 0x10,
120 [WM8996_DAC1_HPOUT1_VOLUME] = 0x88,
121 [WM8996_DAC2_HPOUT2_VOLUME] = 0x88,
122 [WM8996_DAC1_LEFT_VOLUME] = 0x2c0,
123 [WM8996_DAC1_RIGHT_VOLUME] = 0x2c0,
124 [WM8996_DAC2_LEFT_VOLUME] = 0x2c0,
125 [WM8996_DAC2_RIGHT_VOLUME] = 0x2c0,
126 [WM8996_OUTPUT1_LEFT_VOLUME] = 0x80,
127 [WM8996_OUTPUT1_RIGHT_VOLUME] = 0x80,
128 [WM8996_OUTPUT2_LEFT_VOLUME] = 0x80,
129 [WM8996_OUTPUT2_RIGHT_VOLUME] = 0x80,
130 [WM8996_MICBIAS_1] = 0x39,
131 [WM8996_MICBIAS_2] = 0x39,
132 [WM8996_LDO_1] = 0x3,
133 [WM8996_LDO_2] = 0x13,
134 [WM8996_ACCESSORY_DETECT_MODE_1] = 0x4,
135 [WM8996_HEADPHONE_DETECT_1] = 0x20,
136 [WM8996_MIC_DETECT_1] = 0x7600,
137 [WM8996_MIC_DETECT_2] = 0xbf,
138 [WM8996_CHARGE_PUMP_1] = 0x1f25,
139 [WM8996_CHARGE_PUMP_2] = 0xab19,
140 [WM8996_DC_SERVO_5] = 0x2a2a,
141 [WM8996_CONTROL_INTERFACE_1] = 0x8004,
142 [WM8996_CLOCKING_1] = 0x10,
143 [WM8996_AIF_RATE] = 0x83,
144 [WM8996_FLL_CONTROL_4] = 0x5dc0,
145 [WM8996_FLL_CONTROL_5] = 0xc84,
146 [WM8996_FLL_EFS_2] = 0x2,
147 [WM8996_AIF1_TX_LRCLK_1] = 0x80,
148 [WM8996_AIF1_TX_LRCLK_2] = 0x8,
149 [WM8996_AIF1_RX_LRCLK_1] = 0x80,
150 [WM8996_AIF1TX_DATA_CONFIGURATION_1] = 0x1818,
151 [WM8996_AIF1RX_DATA_CONFIGURATION] = 0x1818,
152 [WM8996_AIF1TX_TEST] = 0x7,
153 [WM8996_AIF2_TX_LRCLK_1] = 0x80,
154 [WM8996_AIF2_TX_LRCLK_2] = 0x8,
155 [WM8996_AIF2_RX_LRCLK_1] = 0x80,
156 [WM8996_AIF2TX_DATA_CONFIGURATION_1] = 0x1818,
157 [WM8996_AIF2RX_DATA_CONFIGURATION] = 0x1818,
158 [WM8996_AIF2TX_TEST] = 0x1,
159 [WM8996_DSP1_TX_LEFT_VOLUME] = 0xc0,
160 [WM8996_DSP1_TX_RIGHT_VOLUME] = 0xc0,
161 [WM8996_DSP1_RX_LEFT_VOLUME] = 0xc0,
162 [WM8996_DSP1_RX_RIGHT_VOLUME] = 0xc0,
163 [WM8996_DSP1_TX_FILTERS] = 0x2000,
164 [WM8996_DSP1_RX_FILTERS_1] = 0x200,
165 [WM8996_DSP1_RX_FILTERS_2] = 0x10,
166 [WM8996_DSP1_DRC_1] = 0x98,
167 [WM8996_DSP1_DRC_2] = 0x845,
168 [WM8996_DSP1_RX_EQ_GAINS_1] = 0x6318,
169 [WM8996_DSP1_RX_EQ_GAINS_2] = 0x6300,
170 [WM8996_DSP1_RX_EQ_BAND_1_A] = 0xfca,
171 [WM8996_DSP1_RX_EQ_BAND_1_B] = 0x400,
172 [WM8996_DSP1_RX_EQ_BAND_1_PG] = 0xd8,
173 [WM8996_DSP1_RX_EQ_BAND_2_A] = 0x1eb5,
174 [WM8996_DSP1_RX_EQ_BAND_2_B] = 0xf145,
175 [WM8996_DSP1_RX_EQ_BAND_2_C] = 0xb75,
176 [WM8996_DSP1_RX_EQ_BAND_2_PG] = 0x1c5,
177 [WM8996_DSP1_RX_EQ_BAND_3_A] = 0x1c58,
178 [WM8996_DSP1_RX_EQ_BAND_3_B] = 0xf373,
179 [WM8996_DSP1_RX_EQ_BAND_3_C] = 0xa54,
180 [WM8996_DSP1_RX_EQ_BAND_3_PG] = 0x558,
181 [WM8996_DSP1_RX_EQ_BAND_4_A] = 0x168e,
182 [WM8996_DSP1_RX_EQ_BAND_4_B] = 0xf829,
183 [WM8996_DSP1_RX_EQ_BAND_4_C] = 0x7ad,
184 [WM8996_DSP1_RX_EQ_BAND_4_PG] = 0x1103,
185 [WM8996_DSP1_RX_EQ_BAND_5_A] = 0x564,
186 [WM8996_DSP1_RX_EQ_BAND_5_B] = 0x559,
187 [WM8996_DSP1_RX_EQ_BAND_5_PG] = 0x4000,
188 [WM8996_DSP2_TX_LEFT_VOLUME] = 0xc0,
189 [WM8996_DSP2_TX_RIGHT_VOLUME] = 0xc0,
190 [WM8996_DSP2_RX_LEFT_VOLUME] = 0xc0,
191 [WM8996_DSP2_RX_RIGHT_VOLUME] = 0xc0,
192 [WM8996_DSP2_TX_FILTERS] = 0x2000,
193 [WM8996_DSP2_RX_FILTERS_1] = 0x200,
194 [WM8996_DSP2_RX_FILTERS_2] = 0x10,
195 [WM8996_DSP2_DRC_1] = 0x98,
196 [WM8996_DSP2_DRC_2] = 0x845,
197 [WM8996_DSP2_RX_EQ_GAINS_1] = 0x6318,
198 [WM8996_DSP2_RX_EQ_GAINS_2] = 0x6300,
199 [WM8996_DSP2_RX_EQ_BAND_1_A] = 0xfca,
200 [WM8996_DSP2_RX_EQ_BAND_1_B] = 0x400,
201 [WM8996_DSP2_RX_EQ_BAND_1_PG] = 0xd8,
202 [WM8996_DSP2_RX_EQ_BAND_2_A] = 0x1eb5,
203 [WM8996_DSP2_RX_EQ_BAND_2_B] = 0xf145,
204 [WM8996_DSP2_RX_EQ_BAND_2_C] = 0xb75,
205 [WM8996_DSP2_RX_EQ_BAND_2_PG] = 0x1c5,
206 [WM8996_DSP2_RX_EQ_BAND_3_A] = 0x1c58,
207 [WM8996_DSP2_RX_EQ_BAND_3_B] = 0xf373,
208 [WM8996_DSP2_RX_EQ_BAND_3_C] = 0xa54,
209 [WM8996_DSP2_RX_EQ_BAND_3_PG] = 0x558,
210 [WM8996_DSP2_RX_EQ_BAND_4_A] = 0x168e,
211 [WM8996_DSP2_RX_EQ_BAND_4_B] = 0xf829,
212 [WM8996_DSP2_RX_EQ_BAND_4_C] = 0x7ad,
213 [WM8996_DSP2_RX_EQ_BAND_4_PG] = 0x1103,
214 [WM8996_DSP2_RX_EQ_BAND_5_A] = 0x564,
215 [WM8996_DSP2_RX_EQ_BAND_5_B] = 0x559,
216 [WM8996_DSP2_RX_EQ_BAND_5_PG] = 0x4000,
217 [WM8996_OVERSAMPLING] = 0xd,
218 [WM8996_SIDETONE] = 0x1040,
219 [WM8996_GPIO_1] = 0xa101,
220 [WM8996_GPIO_2] = 0xa101,
221 [WM8996_GPIO_3] = 0xa101,
222 [WM8996_GPIO_4] = 0xa101,
223 [WM8996_GPIO_5] = 0xa101,
224 [WM8996_PULL_CONTROL_2] = 0x140,
225 [WM8996_INTERRUPT_STATUS_1_MASK] = 0x1f,
226 [WM8996_INTERRUPT_STATUS_2_MASK] = 0x1ecf,
227 [WM8996_RIGHT_PDM_SPEAKER] = 0x1,
228 [WM8996_PDM_SPEAKER_MUTE_SEQUENCE] = 0x69,
229 [WM8996_PDM_SPEAKER_VOLUME] = 0x66,
230 [WM8996_WRITE_SEQUENCER_0] = 0x1,
231 [WM8996_WRITE_SEQUENCER_1] = 0x1,
232 [WM8996_WRITE_SEQUENCER_3] = 0x6,
233 [WM8996_WRITE_SEQUENCER_4] = 0x40,
234 [WM8996_WRITE_SEQUENCER_5] = 0x1,
235 [WM8996_WRITE_SEQUENCER_6] = 0xf,
236 [WM8996_WRITE_SEQUENCER_7] = 0x6,
237 [WM8996_WRITE_SEQUENCER_8] = 0x1,
238 [WM8996_WRITE_SEQUENCER_9] = 0x3,
239 [WM8996_WRITE_SEQUENCER_10] = 0x104,
240 [WM8996_WRITE_SEQUENCER_12] = 0x60,
241 [WM8996_WRITE_SEQUENCER_13] = 0x11,
242 [WM8996_WRITE_SEQUENCER_14] = 0x401,
243 [WM8996_WRITE_SEQUENCER_16] = 0x50,
244 [WM8996_WRITE_SEQUENCER_17] = 0x3,
245 [WM8996_WRITE_SEQUENCER_18] = 0x100,
246 [WM8996_WRITE_SEQUENCER_20] = 0x51,
247 [WM8996_WRITE_SEQUENCER_21] = 0x3,
248 [WM8996_WRITE_SEQUENCER_22] = 0x104,
249 [WM8996_WRITE_SEQUENCER_23] = 0xa,
250 [WM8996_WRITE_SEQUENCER_24] = 0x60,
251 [WM8996_WRITE_SEQUENCER_25] = 0x3b,
252 [WM8996_WRITE_SEQUENCER_26] = 0x502,
253 [WM8996_WRITE_SEQUENCER_27] = 0x100,
254 [WM8996_WRITE_SEQUENCER_28] = 0x2fff,
255 [WM8996_WRITE_SEQUENCER_32] = 0x2fff,
256 [WM8996_WRITE_SEQUENCER_36] = 0x2fff,
257 [WM8996_WRITE_SEQUENCER_40] = 0x2fff,
258 [WM8996_WRITE_SEQUENCER_44] = 0x2fff,
259 [WM8996_WRITE_SEQUENCER_48] = 0x2fff,
260 [WM8996_WRITE_SEQUENCER_52] = 0x2fff,
261 [WM8996_WRITE_SEQUENCER_56] = 0x2fff,
262 [WM8996_WRITE_SEQUENCER_60] = 0x2fff,
263 [WM8996_WRITE_SEQUENCER_64] = 0x1,
264 [WM8996_WRITE_SEQUENCER_65] = 0x1,
265 [WM8996_WRITE_SEQUENCER_67] = 0x6,
266 [WM8996_WRITE_SEQUENCER_68] = 0x40,
267 [WM8996_WRITE_SEQUENCER_69] = 0x1,
268 [WM8996_WRITE_SEQUENCER_70] = 0xf,
269 [WM8996_WRITE_SEQUENCER_71] = 0x6,
270 [WM8996_WRITE_SEQUENCER_72] = 0x1,
271 [WM8996_WRITE_SEQUENCER_73] = 0x3,
272 [WM8996_WRITE_SEQUENCER_74] = 0x104,
273 [WM8996_WRITE_SEQUENCER_76] = 0x60,
274 [WM8996_WRITE_SEQUENCER_77] = 0x11,
275 [WM8996_WRITE_SEQUENCER_78] = 0x401,
276 [WM8996_WRITE_SEQUENCER_80] = 0x50,
277 [WM8996_WRITE_SEQUENCER_81] = 0x3,
278 [WM8996_WRITE_SEQUENCER_82] = 0x100,
279 [WM8996_WRITE_SEQUENCER_84] = 0x60,
280 [WM8996_WRITE_SEQUENCER_85] = 0x3b,
281 [WM8996_WRITE_SEQUENCER_86] = 0x502,
282 [WM8996_WRITE_SEQUENCER_87] = 0x100,
283 [WM8996_WRITE_SEQUENCER_88] = 0x2fff,
284 [WM8996_WRITE_SEQUENCER_92] = 0x2fff,
285 [WM8996_WRITE_SEQUENCER_96] = 0x2fff,
286 [WM8996_WRITE_SEQUENCER_100] = 0x2fff,
287 [WM8996_WRITE_SEQUENCER_104] = 0x2fff,
288 [WM8996_WRITE_SEQUENCER_108] = 0x2fff,
289 [WM8996_WRITE_SEQUENCER_112] = 0x2fff,
290 [WM8996_WRITE_SEQUENCER_116] = 0x2fff,
291 [WM8996_WRITE_SEQUENCER_120] = 0x2fff,
292 [WM8996_WRITE_SEQUENCER_124] = 0x2fff,
293 [WM8996_WRITE_SEQUENCER_128] = 0x1,
294 [WM8996_WRITE_SEQUENCER_129] = 0x1,
295 [WM8996_WRITE_SEQUENCER_131] = 0x6,
296 [WM8996_WRITE_SEQUENCER_132] = 0x40,
297 [WM8996_WRITE_SEQUENCER_133] = 0x1,
298 [WM8996_WRITE_SEQUENCER_134] = 0xf,
299 [WM8996_WRITE_SEQUENCER_135] = 0x6,
300 [WM8996_WRITE_SEQUENCER_136] = 0x1,
301 [WM8996_WRITE_SEQUENCER_137] = 0x3,
302 [WM8996_WRITE_SEQUENCER_138] = 0x106,
303 [WM8996_WRITE_SEQUENCER_140] = 0x61,
304 [WM8996_WRITE_SEQUENCER_141] = 0x11,
305 [WM8996_WRITE_SEQUENCER_142] = 0x401,
306 [WM8996_WRITE_SEQUENCER_144] = 0x50,
307 [WM8996_WRITE_SEQUENCER_145] = 0x3,
308 [WM8996_WRITE_SEQUENCER_146] = 0x102,
309 [WM8996_WRITE_SEQUENCER_148] = 0x51,
310 [WM8996_WRITE_SEQUENCER_149] = 0x3,
311 [WM8996_WRITE_SEQUENCER_150] = 0x106,
312 [WM8996_WRITE_SEQUENCER_151] = 0xa,
313 [WM8996_WRITE_SEQUENCER_152] = 0x61,
314 [WM8996_WRITE_SEQUENCER_153] = 0x3b,
315 [WM8996_WRITE_SEQUENCER_154] = 0x502,
316 [WM8996_WRITE_SEQUENCER_155] = 0x100,
317 [WM8996_WRITE_SEQUENCER_156] = 0x2fff,
318 [WM8996_WRITE_SEQUENCER_160] = 0x2fff,
319 [WM8996_WRITE_SEQUENCER_164] = 0x2fff,
320 [WM8996_WRITE_SEQUENCER_168] = 0x2fff,
321 [WM8996_WRITE_SEQUENCER_172] = 0x2fff,
322 [WM8996_WRITE_SEQUENCER_176] = 0x2fff,
323 [WM8996_WRITE_SEQUENCER_180] = 0x2fff,
324 [WM8996_WRITE_SEQUENCER_184] = 0x2fff,
325 [WM8996_WRITE_SEQUENCER_188] = 0x2fff,
326 [WM8996_WRITE_SEQUENCER_192] = 0x1,
327 [WM8996_WRITE_SEQUENCER_193] = 0x1,
328 [WM8996_WRITE_SEQUENCER_195] = 0x6,
329 [WM8996_WRITE_SEQUENCER_196] = 0x40,
330 [WM8996_WRITE_SEQUENCER_197] = 0x1,
331 [WM8996_WRITE_SEQUENCER_198] = 0xf,
332 [WM8996_WRITE_SEQUENCER_199] = 0x6,
333 [WM8996_WRITE_SEQUENCER_200] = 0x1,
334 [WM8996_WRITE_SEQUENCER_201] = 0x3,
335 [WM8996_WRITE_SEQUENCER_202] = 0x106,
336 [WM8996_WRITE_SEQUENCER_204] = 0x61,
337 [WM8996_WRITE_SEQUENCER_205] = 0x11,
338 [WM8996_WRITE_SEQUENCER_206] = 0x401,
339 [WM8996_WRITE_SEQUENCER_208] = 0x50,
340 [WM8996_WRITE_SEQUENCER_209] = 0x3,
341 [WM8996_WRITE_SEQUENCER_210] = 0x102,
342 [WM8996_WRITE_SEQUENCER_212] = 0x61,
343 [WM8996_WRITE_SEQUENCER_213] = 0x3b,
344 [WM8996_WRITE_SEQUENCER_214] = 0x502,
345 [WM8996_WRITE_SEQUENCER_215] = 0x100,
346 [WM8996_WRITE_SEQUENCER_216] = 0x2fff,
347 [WM8996_WRITE_SEQUENCER_220] = 0x2fff,
348 [WM8996_WRITE_SEQUENCER_224] = 0x2fff,
349 [WM8996_WRITE_SEQUENCER_228] = 0x2fff,
350 [WM8996_WRITE_SEQUENCER_232] = 0x2fff,
351 [WM8996_WRITE_SEQUENCER_236] = 0x2fff,
352 [WM8996_WRITE_SEQUENCER_240] = 0x2fff,
353 [WM8996_WRITE_SEQUENCER_244] = 0x2fff,
354 [WM8996_WRITE_SEQUENCER_248] = 0x2fff,
355 [WM8996_WRITE_SEQUENCER_252] = 0x2fff,
356 [WM8996_WRITE_SEQUENCER_256] = 0x60,
357 [WM8996_WRITE_SEQUENCER_258] = 0x601,
358 [WM8996_WRITE_SEQUENCER_260] = 0x50,
359 [WM8996_WRITE_SEQUENCER_262] = 0x100,
360 [WM8996_WRITE_SEQUENCER_264] = 0x1,
361 [WM8996_WRITE_SEQUENCER_266] = 0x104,
362 [WM8996_WRITE_SEQUENCER_267] = 0x100,
363 [WM8996_WRITE_SEQUENCER_268] = 0x2fff,
364 [WM8996_WRITE_SEQUENCER_272] = 0x2fff,
365 [WM8996_WRITE_SEQUENCER_276] = 0x2fff,
366 [WM8996_WRITE_SEQUENCER_280] = 0x2fff,
367 [WM8996_WRITE_SEQUENCER_284] = 0x2fff,
368 [WM8996_WRITE_SEQUENCER_288] = 0x2fff,
369 [WM8996_WRITE_SEQUENCER_292] = 0x2fff,
370 [WM8996_WRITE_SEQUENCER_296] = 0x2fff,
371 [WM8996_WRITE_SEQUENCER_300] = 0x2fff,
372 [WM8996_WRITE_SEQUENCER_304] = 0x2fff,
373 [WM8996_WRITE_SEQUENCER_308] = 0x2fff,
374 [WM8996_WRITE_SEQUENCER_312] = 0x2fff,
375 [WM8996_WRITE_SEQUENCER_316] = 0x2fff,
376 [WM8996_WRITE_SEQUENCER_320] = 0x61,
377 [WM8996_WRITE_SEQUENCER_322] = 0x601,
378 [WM8996_WRITE_SEQUENCER_324] = 0x50,
379 [WM8996_WRITE_SEQUENCER_326] = 0x102,
380 [WM8996_WRITE_SEQUENCER_328] = 0x1,
381 [WM8996_WRITE_SEQUENCER_330] = 0x106,
382 [WM8996_WRITE_SEQUENCER_331] = 0x100,
383 [WM8996_WRITE_SEQUENCER_332] = 0x2fff,
384 [WM8996_WRITE_SEQUENCER_336] = 0x2fff,
385 [WM8996_WRITE_SEQUENCER_340] = 0x2fff,
386 [WM8996_WRITE_SEQUENCER_344] = 0x2fff,
387 [WM8996_WRITE_SEQUENCER_348] = 0x2fff,
388 [WM8996_WRITE_SEQUENCER_352] = 0x2fff,
389 [WM8996_WRITE_SEQUENCER_356] = 0x2fff,
390 [WM8996_WRITE_SEQUENCER_360] = 0x2fff,
391 [WM8996_WRITE_SEQUENCER_364] = 0x2fff,
392 [WM8996_WRITE_SEQUENCER_368] = 0x2fff,
393 [WM8996_WRITE_SEQUENCER_372] = 0x2fff,
394 [WM8996_WRITE_SEQUENCER_376] = 0x2fff,
395 [WM8996_WRITE_SEQUENCER_380] = 0x2fff,
396 [WM8996_WRITE_SEQUENCER_384] = 0x60,
397 [WM8996_WRITE_SEQUENCER_386] = 0x601,
398 [WM8996_WRITE_SEQUENCER_388] = 0x61,
399 [WM8996_WRITE_SEQUENCER_390] = 0x601,
400 [WM8996_WRITE_SEQUENCER_392] = 0x50,
401 [WM8996_WRITE_SEQUENCER_394] = 0x300,
402 [WM8996_WRITE_SEQUENCER_396] = 0x1,
403 [WM8996_WRITE_SEQUENCER_398] = 0x304,
404 [WM8996_WRITE_SEQUENCER_400] = 0x40,
405 [WM8996_WRITE_SEQUENCER_402] = 0xf,
406 [WM8996_WRITE_SEQUENCER_404] = 0x1,
407 [WM8996_WRITE_SEQUENCER_407] = 0x100,
408};
409
410static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
411static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
412static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
413static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
414static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
415static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
416static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
417
418static const char *sidetone_hpf_text[] = {
419 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
420};
421
422static const struct soc_enum sidetone_hpf =
423 SOC_ENUM_SINGLE(WM8996_SIDETONE, 7, 6, sidetone_hpf_text);
424
425static const char *hpf_mode_text[] = {
426 "HiFi", "Custom", "Voice"
427};
428
429static const struct soc_enum dsp1tx_hpf_mode =
430 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
431
432static const struct soc_enum dsp2tx_hpf_mode =
433 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
434
435static const char *hpf_cutoff_text[] = {
436 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
437};
438
439static const struct soc_enum dsp1tx_hpf_cutoff =
440 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
441
442static const struct soc_enum dsp2tx_hpf_cutoff =
443 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
444
445static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block)
446{
447 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
448 struct wm8996_pdata *pdata = &wm8996->pdata;
449 int base, best, best_val, save, i, cfg, iface;
450
451 if (!wm8996->num_retune_mobile_texts)
452 return;
453
454 switch (block) {
455 case 0:
456 base = WM8996_DSP1_RX_EQ_GAINS_1;
457 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
458 WM8996_DSP1RX_SRC)
459 iface = 1;
460 else
461 iface = 0;
462 break;
463 case 1:
464 base = WM8996_DSP1_RX_EQ_GAINS_2;
465 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
466 WM8996_DSP2RX_SRC)
467 iface = 1;
468 else
469 iface = 0;
470 break;
471 default:
472 return;
473 }
474
475 /* Find the version of the currently selected configuration
476 * with the nearest sample rate. */
477 cfg = wm8996->retune_mobile_cfg[block];
478 best = 0;
479 best_val = INT_MAX;
480 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
481 if (strcmp(pdata->retune_mobile_cfgs[i].name,
482 wm8996->retune_mobile_texts[cfg]) == 0 &&
483 abs(pdata->retune_mobile_cfgs[i].rate
484 - wm8996->rx_rate[iface]) < best_val) {
485 best = i;
486 best_val = abs(pdata->retune_mobile_cfgs[i].rate
487 - wm8996->rx_rate[iface]);
488 }
489 }
490
491 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
492 block,
493 pdata->retune_mobile_cfgs[best].name,
494 pdata->retune_mobile_cfgs[best].rate,
495 wm8996->rx_rate[iface]);
496
497 /* The EQ will be disabled while reconfiguring it, remember the
498 * current configuration.
499 */
500 save = snd_soc_read(codec, base);
501 save &= WM8996_DSP1RX_EQ_ENA;
502
503 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
504 snd_soc_update_bits(codec, base + i, 0xffff,
505 pdata->retune_mobile_cfgs[best].regs[i]);
506
507 snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save);
508}
509
510/* Icky as hell but saves code duplication */
511static int wm8996_get_retune_mobile_block(const char *name)
512{
513 if (strcmp(name, "DSP1 EQ Mode") == 0)
514 return 0;
515 if (strcmp(name, "DSP2 EQ Mode") == 0)
516 return 1;
517 return -EINVAL;
518}
519
520static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
521 struct snd_ctl_elem_value *ucontrol)
522{
523 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
524 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
525 struct wm8996_pdata *pdata = &wm8996->pdata;
526 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
527 int value = ucontrol->value.integer.value[0];
528
529 if (block < 0)
530 return block;
531
532 if (value >= pdata->num_retune_mobile_cfgs)
533 return -EINVAL;
534
535 wm8996->retune_mobile_cfg[block] = value;
536
537 wm8996_set_retune_mobile(codec, block);
538
539 return 0;
540}
541
542static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
543 struct snd_ctl_elem_value *ucontrol)
544{
545 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
546 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
547 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
548
549 ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
550
551 return 0;
552}
553
554static const struct snd_kcontrol_new wm8996_snd_controls[] = {
555SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
556 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
557SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
558 WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
559
560SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
561 0, 5, 24, 0, sidetone_tlv),
562SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
563 0, 5, 24, 0, sidetone_tlv),
564SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
565SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
566SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
567
568SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
569 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
570SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
571 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
572
573SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
574 13, 1, 0),
575SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
576SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
577SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
578
579SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
580 13, 1, 0),
581SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
582SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
583SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
584
585SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
586 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
587SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
588
589SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
590 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
591SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
592
593SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
594 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
595SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
596 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
597
598SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
599 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
600SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
601 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
602
603SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
604SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
605SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
606SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
607
608SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
609SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
610
611SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
612 8, 0, out_digital_tlv),
613SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
614 8, 0, out_digital_tlv),
615
616SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
617 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
618SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME,
619 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
620
621SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
622 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
623SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME,
624 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
625
626SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
627 spk_tlv),
628SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
629 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
630SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
631 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
632
633SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
634SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
635};
636
637static const struct snd_kcontrol_new wm8996_eq_controls[] = {
638SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
639 eq_tlv),
640SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
641 eq_tlv),
642SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
643 eq_tlv),
644SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
645 eq_tlv),
646SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
647 eq_tlv),
648
649SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
650 eq_tlv),
651SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
652 eq_tlv),
653SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
654 eq_tlv),
655SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
656 eq_tlv),
657SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
658 eq_tlv),
659};
660
661static int cp_event(struct snd_soc_dapm_widget *w,
662 struct snd_kcontrol *kcontrol, int event)
663{
664 switch (event) {
665 case SND_SOC_DAPM_POST_PMU:
666 msleep(5);
667 break;
668 default:
669 BUG();
670 return -EINVAL;
671 }
672
673 return 0;
674}
675
676static int rmv_short_event(struct snd_soc_dapm_widget *w,
677 struct snd_kcontrol *kcontrol, int event)
678{
679 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
680
681 /* Record which outputs we enabled */
682 switch (event) {
683 case SND_SOC_DAPM_PRE_PMD:
684 wm8996->hpout_pending &= ~w->shift;
685 break;
686 case SND_SOC_DAPM_PRE_PMU:
687 wm8996->hpout_pending |= w->shift;
688 break;
689 default:
690 BUG();
691 return -EINVAL;
692 }
693
694 return 0;
695}
696
697static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
698{
699 struct i2c_client *i2c = to_i2c_client(codec->dev);
700 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
701 int i, ret;
702 unsigned long timeout = 200;
703
704 snd_soc_write(codec, WM8996_DC_SERVO_2, mask);
705
706 /* Use the interrupt if possible */
707 do {
708 if (i2c->irq) {
709 timeout = wait_for_completion_timeout(&wm8996->dcs_done,
710 msecs_to_jiffies(200));
711 if (timeout == 0)
712 dev_err(codec->dev, "DC servo timed out\n");
713
714 } else {
715 msleep(1);
716 if (--i) {
717 timeout = 0;
718 break;
719 }
720 }
721
722 ret = snd_soc_read(codec, WM8996_DC_SERVO_2);
723 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
724 } while (ret & mask);
725
726 if (timeout == 0)
727 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
728 else
729 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
730}
731
732static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm,
733 enum snd_soc_dapm_type event, int subseq)
734{
735 struct snd_soc_codec *codec = container_of(dapm,
736 struct snd_soc_codec, dapm);
737 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
738 u16 val, mask;
739
740 /* Complete any pending DC servo starts */
741 if (wm8996->dcs_pending) {
742 dev_dbg(codec->dev, "Starting DC servo for %x\n",
743 wm8996->dcs_pending);
744
745 /* Trigger a startup sequence */
746 wait_for_dc_servo(codec, wm8996->dcs_pending
747 << WM8996_DCS_TRIG_STARTUP_0_SHIFT);
748
749 wm8996->dcs_pending = 0;
750 }
751
752 if (wm8996->hpout_pending != wm8996->hpout_ena) {
753 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
754 wm8996->hpout_ena, wm8996->hpout_pending);
755
756 val = 0;
757 mask = 0;
758 if (wm8996->hpout_pending & HPOUT1L) {
759 val |= WM8996_HPOUT1L_RMV_SHORT;
760 mask |= WM8996_HPOUT1L_RMV_SHORT;
761 } else {
762 mask |= WM8996_HPOUT1L_RMV_SHORT |
763 WM8996_HPOUT1L_OUTP |
764 WM8996_HPOUT1L_DLY;
765 }
766
767 if (wm8996->hpout_pending & HPOUT1R) {
768 val |= WM8996_HPOUT1R_RMV_SHORT;
769 mask |= WM8996_HPOUT1R_RMV_SHORT;
770 } else {
771 mask |= WM8996_HPOUT1R_RMV_SHORT |
772 WM8996_HPOUT1R_OUTP |
773 WM8996_HPOUT1R_DLY;
774 }
775
776 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val);
777
778 val = 0;
779 mask = 0;
780 if (wm8996->hpout_pending & HPOUT2L) {
781 val |= WM8996_HPOUT2L_RMV_SHORT;
782 mask |= WM8996_HPOUT2L_RMV_SHORT;
783 } else {
784 mask |= WM8996_HPOUT2L_RMV_SHORT |
785 WM8996_HPOUT2L_OUTP |
786 WM8996_HPOUT2L_DLY;
787 }
788
789 if (wm8996->hpout_pending & HPOUT2R) {
790 val |= WM8996_HPOUT2R_RMV_SHORT;
791 mask |= WM8996_HPOUT2R_RMV_SHORT;
792 } else {
793 mask |= WM8996_HPOUT2R_RMV_SHORT |
794 WM8996_HPOUT2R_OUTP |
795 WM8996_HPOUT2R_DLY;
796 }
797
798 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val);
799
800 wm8996->hpout_ena = wm8996->hpout_pending;
801 }
802}
803
804static int dcs_start(struct snd_soc_dapm_widget *w,
805 struct snd_kcontrol *kcontrol, int event)
806{
807 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
808
809 switch (event) {
810 case SND_SOC_DAPM_POST_PMU:
811 wm8996->dcs_pending |= 1 << w->shift;
812 break;
813 default:
814 BUG();
815 return -EINVAL;
816 }
817
818 return 0;
819}
820
821static const char *sidetone_text[] = {
822 "IN1", "IN2",
823};
824
825static const struct soc_enum left_sidetone_enum =
826 SOC_ENUM_SINGLE(WM8996_SIDETONE, 0, 2, sidetone_text);
827
828static const struct snd_kcontrol_new left_sidetone =
829 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
830
831static const struct soc_enum right_sidetone_enum =
832 SOC_ENUM_SINGLE(WM8996_SIDETONE, 1, 2, sidetone_text);
833
834static const struct snd_kcontrol_new right_sidetone =
835 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
836
837static const char *spk_text[] = {
838 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
839};
840
841static const struct soc_enum spkl_enum =
842 SOC_ENUM_SINGLE(WM8996_LEFT_PDM_SPEAKER, 0, 4, spk_text);
843
844static const struct snd_kcontrol_new spkl_mux =
845 SOC_DAPM_ENUM("SPKL", spkl_enum);
846
847static const struct soc_enum spkr_enum =
848 SOC_ENUM_SINGLE(WM8996_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
849
850static const struct snd_kcontrol_new spkr_mux =
851 SOC_DAPM_ENUM("SPKR", spkr_enum);
852
853static const char *dsp1rx_text[] = {
854 "AIF1", "AIF2"
855};
856
857static const struct soc_enum dsp1rx_enum =
858 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
859
860static const struct snd_kcontrol_new dsp1rx =
861 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
862
863static const char *dsp2rx_text[] = {
864 "AIF2", "AIF1"
865};
866
867static const struct soc_enum dsp2rx_enum =
868 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
869
870static const struct snd_kcontrol_new dsp2rx =
871 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
872
873static const char *aif2tx_text[] = {
874 "DSP2", "DSP1", "AIF1"
875};
876
877static const struct soc_enum aif2tx_enum =
878 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
879
880static const struct snd_kcontrol_new aif2tx =
881 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
882
883static const char *inmux_text[] = {
884 "ADC", "DMIC1", "DMIC2"
885};
886
887static const struct soc_enum in1_enum =
888 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 0, 3, inmux_text);
889
890static const struct snd_kcontrol_new in1_mux =
891 SOC_DAPM_ENUM("IN1 Mux", in1_enum);
892
893static const struct soc_enum in2_enum =
894 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 4, 3, inmux_text);
895
896static const struct snd_kcontrol_new in2_mux =
897 SOC_DAPM_ENUM("IN2 Mux", in2_enum);
898
899static const struct snd_kcontrol_new dac2r_mix[] = {
900SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
901 5, 1, 0),
902SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
903 4, 1, 0),
904SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
905SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
906};
907
908static const struct snd_kcontrol_new dac2l_mix[] = {
909SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
910 5, 1, 0),
911SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
912 4, 1, 0),
913SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
914SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
915};
916
917static const struct snd_kcontrol_new dac1r_mix[] = {
918SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
919 5, 1, 0),
920SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
921 4, 1, 0),
922SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
923SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
924};
925
926static const struct snd_kcontrol_new dac1l_mix[] = {
927SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
928 5, 1, 0),
929SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
930 4, 1, 0),
931SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
932SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
933};
934
935static const struct snd_kcontrol_new dsp1txl[] = {
936SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
937 1, 1, 0),
938SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
939 0, 1, 0),
940};
941
942static const struct snd_kcontrol_new dsp1txr[] = {
943SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
944 1, 1, 0),
945SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
946 0, 1, 0),
947};
948
949static const struct snd_kcontrol_new dsp2txl[] = {
950SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
951 1, 1, 0),
952SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
953 0, 1, 0),
954};
955
956static const struct snd_kcontrol_new dsp2txr[] = {
957SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
958 1, 1, 0),
959SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
960 0, 1, 0),
961};
962
963
964static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
965SND_SOC_DAPM_INPUT("IN1LN"),
966SND_SOC_DAPM_INPUT("IN1LP"),
967SND_SOC_DAPM_INPUT("IN1RN"),
968SND_SOC_DAPM_INPUT("IN1RP"),
969
970SND_SOC_DAPM_INPUT("IN2LN"),
971SND_SOC_DAPM_INPUT("IN2LP"),
972SND_SOC_DAPM_INPUT("IN2RN"),
973SND_SOC_DAPM_INPUT("IN2RP"),
974
975SND_SOC_DAPM_INPUT("DMIC1DAT"),
976SND_SOC_DAPM_INPUT("DMIC2DAT"),
977
978SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
979SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
980SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
981SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
982 SND_SOC_DAPM_POST_PMU),
983
984SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
985SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
986SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
987
988SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
989SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
990
991SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &in1_mux),
992SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &in1_mux),
993SND_SOC_DAPM_MUX("IN2L Mux", SND_SOC_NOPM, 0, 0, &in2_mux),
994SND_SOC_DAPM_MUX("IN2R Mux", SND_SOC_NOPM, 0, 0, &in2_mux),
995
996SND_SOC_DAPM_PGA("IN1L", WM8996_POWER_MANAGEMENT_7, 2, 0, NULL, 0),
997SND_SOC_DAPM_PGA("IN1R", WM8996_POWER_MANAGEMENT_7, 3, 0, NULL, 0),
998SND_SOC_DAPM_PGA("IN2L", WM8996_POWER_MANAGEMENT_7, 6, 0, NULL, 0),
999SND_SOC_DAPM_PGA("IN2R", WM8996_POWER_MANAGEMENT_7, 7, 0, NULL, 0),
1000
1001SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
1002SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
1003
1004SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
1005SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
1006SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
1007SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
1008
1009SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
1010SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
1011
1012SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
1013SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
1014
1015SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
1016SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
1017SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
1018SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
1019
1020SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
1021 dsp2txl, ARRAY_SIZE(dsp2txl)),
1022SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
1023 dsp2txr, ARRAY_SIZE(dsp2txr)),
1024SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
1025 dsp1txl, ARRAY_SIZE(dsp1txl)),
1026SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
1027 dsp1txr, ARRAY_SIZE(dsp1txr)),
1028
1029SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1030 dac2l_mix, ARRAY_SIZE(dac2l_mix)),
1031SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1032 dac2r_mix, ARRAY_SIZE(dac2r_mix)),
1033SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1034 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1035SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1036 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1037
1038SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
1039SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
1040SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
1041SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
1042
1043SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 1,
1044 WM8996_POWER_MANAGEMENT_4, 9, 0),
1045SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 2,
1046 WM8996_POWER_MANAGEMENT_4, 8, 0),
1047
1048SND_SOC_DAPM_AIF_IN("AIF2TX1", "AIF2 Capture", 1,
1049 WM8996_POWER_MANAGEMENT_6, 9, 0),
1050SND_SOC_DAPM_AIF_IN("AIF2TX0", "AIF2 Capture", 2,
1051 WM8996_POWER_MANAGEMENT_6, 8, 0),
1052
1053SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
1054 WM8996_POWER_MANAGEMENT_4, 5, 0),
1055SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
1056 WM8996_POWER_MANAGEMENT_4, 4, 0),
1057SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
1058 WM8996_POWER_MANAGEMENT_4, 3, 0),
1059SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
1060 WM8996_POWER_MANAGEMENT_4, 2, 0),
1061SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
1062 WM8996_POWER_MANAGEMENT_4, 1, 0),
1063SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
1064 WM8996_POWER_MANAGEMENT_4, 0, 0),
1065
1066SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
1067 WM8996_POWER_MANAGEMENT_6, 5, 0),
1068SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
1069 WM8996_POWER_MANAGEMENT_6, 4, 0),
1070SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
1071 WM8996_POWER_MANAGEMENT_6, 3, 0),
1072SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
1073 WM8996_POWER_MANAGEMENT_6, 2, 0),
1074SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
1075 WM8996_POWER_MANAGEMENT_6, 1, 0),
1076SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
1077 WM8996_POWER_MANAGEMENT_6, 0, 0),
1078
1079/* We route as stereo pairs so define some dummy widgets to squash
1080 * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1081SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1082SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1083SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1084SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1085SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1086
1087SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1088SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1089SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1090
1091SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1092SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1093SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1094SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1095
1096SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1097SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
1098SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
1099 SND_SOC_DAPM_POST_PMU),
1100SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8996_ANALOGUE_HP_2, 6, 0, NULL, 0),
1101SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1102 rmv_short_event,
1103 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1104
1105SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1106SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
1107SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
1108 SND_SOC_DAPM_POST_PMU),
1109SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8996_ANALOGUE_HP_2, 2, 0, NULL, 0),
1110SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1111 rmv_short_event,
1112 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1113
1114SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1115SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
1116SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
1117 SND_SOC_DAPM_POST_PMU),
1118SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8996_ANALOGUE_HP_1, 6, 0, NULL, 0),
1119SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1120 rmv_short_event,
1121 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1122
1123SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1124SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
1125SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
1126 SND_SOC_DAPM_POST_PMU),
1127SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8996_ANALOGUE_HP_1, 2, 0, NULL, 0),
1128SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1129 rmv_short_event,
1130 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1131
1132SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1133SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1134SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1135SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1136SND_SOC_DAPM_OUTPUT("SPKDAT"),
1137};
1138
1139static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
1140 { "AIFCLK", NULL, "SYSCLK" },
1141 { "SYSDSPCLK", NULL, "SYSCLK" },
1142 { "Charge Pump", NULL, "SYSCLK" },
1143
1144 { "MICB1", NULL, "LDO2" },
1145 { "MICB2", NULL, "LDO2" },
1146
1147 { "IN1L PGA", NULL, "IN2LN" },
1148 { "IN1L PGA", NULL, "IN2LP" },
1149 { "IN1L PGA", NULL, "IN1LN" },
1150 { "IN1L PGA", NULL, "IN1LP" },
1151
1152 { "IN1R PGA", NULL, "IN2RN" },
1153 { "IN1R PGA", NULL, "IN2RP" },
1154 { "IN1R PGA", NULL, "IN1RN" },
1155 { "IN1R PGA", NULL, "IN1RP" },
1156
1157 { "ADCL", NULL, "IN1L PGA" },
1158
1159 { "ADCR", NULL, "IN1R PGA" },
1160
1161 { "DMIC1L", NULL, "DMIC1DAT" },
1162 { "DMIC1R", NULL, "DMIC1DAT" },
1163 { "DMIC2L", NULL, "DMIC2DAT" },
1164 { "DMIC2R", NULL, "DMIC2DAT" },
1165
1166 { "DMIC2L", NULL, "DMIC2" },
1167 { "DMIC2R", NULL, "DMIC2" },
1168 { "DMIC1L", NULL, "DMIC1" },
1169 { "DMIC1R", NULL, "DMIC1" },
1170
1171 { "IN1L Mux", "ADC", "ADCL" },
1172 { "IN1L Mux", "DMIC1", "DMIC1L" },
1173 { "IN1L Mux", "DMIC2", "DMIC2L" },
1174
1175 { "IN1R Mux", "ADC", "ADCR" },
1176 { "IN1R Mux", "DMIC1", "DMIC1R" },
1177 { "IN1R Mux", "DMIC2", "DMIC2R" },
1178
1179 { "IN2L Mux", "ADC", "ADCL" },
1180 { "IN2L Mux", "DMIC1", "DMIC1L" },
1181 { "IN2L Mux", "DMIC2", "DMIC2L" },
1182
1183 { "IN2R Mux", "ADC", "ADCR" },
1184 { "IN2R Mux", "DMIC1", "DMIC1R" },
1185 { "IN2R Mux", "DMIC2", "DMIC2R" },
1186
1187 { "Left Sidetone", "IN1", "IN1L Mux" },
1188 { "Left Sidetone", "IN2", "IN2L Mux" },
1189
1190 { "Right Sidetone", "IN1", "IN1R Mux" },
1191 { "Right Sidetone", "IN2", "IN2R Mux" },
1192
1193 { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1194 { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1195
1196 { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1197 { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1198
1199 { "AIF1TX0", NULL, "DSP1TXL" },
1200 { "AIF1TX1", NULL, "DSP1TXR" },
1201 { "AIF1TX2", NULL, "DSP2TXL" },
1202 { "AIF1TX3", NULL, "DSP2TXR" },
1203 { "AIF1TX4", NULL, "AIF2RX0" },
1204 { "AIF1TX5", NULL, "AIF2RX1" },
1205
1206 { "AIF1RX0", NULL, "AIFCLK" },
1207 { "AIF1RX1", NULL, "AIFCLK" },
1208 { "AIF1RX2", NULL, "AIFCLK" },
1209 { "AIF1RX3", NULL, "AIFCLK" },
1210 { "AIF1RX4", NULL, "AIFCLK" },
1211 { "AIF1RX5", NULL, "AIFCLK" },
1212
1213 { "AIF2RX0", NULL, "AIFCLK" },
1214 { "AIF2RX1", NULL, "AIFCLK" },
1215
1216 { "DSP1RXL", NULL, "SYSDSPCLK" },
1217 { "DSP1RXR", NULL, "SYSDSPCLK" },
1218 { "DSP2RXL", NULL, "SYSDSPCLK" },
1219 { "DSP2RXR", NULL, "SYSDSPCLK" },
1220 { "DSP1TXL", NULL, "SYSDSPCLK" },
1221 { "DSP1TXR", NULL, "SYSDSPCLK" },
1222 { "DSP2TXL", NULL, "SYSDSPCLK" },
1223 { "DSP2TXR", NULL, "SYSDSPCLK" },
1224
1225 { "AIF1RXA", NULL, "AIF1RX0" },
1226 { "AIF1RXA", NULL, "AIF1RX1" },
1227 { "AIF1RXB", NULL, "AIF1RX2" },
1228 { "AIF1RXB", NULL, "AIF1RX3" },
1229 { "AIF1RXC", NULL, "AIF1RX4" },
1230 { "AIF1RXC", NULL, "AIF1RX5" },
1231
1232 { "AIF2RX", NULL, "AIF2RX0" },
1233 { "AIF2RX", NULL, "AIF2RX1" },
1234
1235 { "AIF2TX", "DSP2", "DSP2TX" },
1236 { "AIF2TX", "DSP1", "DSP1RX" },
1237 { "AIF2TX", "AIF1", "AIF1RXC" },
1238
1239 { "DSP1RXL", NULL, "DSP1RX" },
1240 { "DSP1RXR", NULL, "DSP1RX" },
1241 { "DSP2RXL", NULL, "DSP2RX" },
1242 { "DSP2RXR", NULL, "DSP2RX" },
1243
1244 { "DSP2TX", NULL, "DSP2TXL" },
1245 { "DSP2TX", NULL, "DSP2TXR" },
1246
1247 { "DSP1RX", "AIF1", "AIF1RXA" },
1248 { "DSP1RX", "AIF2", "AIF2RX" },
1249
1250 { "DSP2RX", "AIF1", "AIF1RXB" },
1251 { "DSP2RX", "AIF2", "AIF2RX" },
1252
1253 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1254 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1255 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1256 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1257
1258 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1259 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1260 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1261 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1262
1263 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1264 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1265 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1266 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1267
1268 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1269 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1270 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1271 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1272
1273 { "DAC1L", NULL, "DAC1L Mixer" },
1274 { "DAC1R", NULL, "DAC1R Mixer" },
1275 { "DAC2L", NULL, "DAC2L Mixer" },
1276 { "DAC2R", NULL, "DAC2R Mixer" },
1277
1278 { "HPOUT2L PGA", NULL, "Charge Pump" },
1279 { "HPOUT2L PGA", NULL, "DAC2L" },
1280 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1281 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1282 { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" },
1283 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" },
1284
1285 { "HPOUT2R PGA", NULL, "Charge Pump" },
1286 { "HPOUT2R PGA", NULL, "DAC2R" },
1287 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1288 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1289 { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" },
1290 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" },
1291
1292 { "HPOUT1L PGA", NULL, "Charge Pump" },
1293 { "HPOUT1L PGA", NULL, "DAC1L" },
1294 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1295 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1296 { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" },
1297 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" },
1298
1299 { "HPOUT1R PGA", NULL, "Charge Pump" },
1300 { "HPOUT1R PGA", NULL, "DAC1R" },
1301 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1302 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1303 { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" },
1304 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" },
1305
1306 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1307 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1308 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1309 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1310
1311 { "SPKL", "DAC1L", "DAC1L" },
1312 { "SPKL", "DAC1R", "DAC1R" },
1313 { "SPKL", "DAC2L", "DAC2L" },
1314 { "SPKL", "DAC2R", "DAC2R" },
1315
1316 { "SPKR", "DAC1L", "DAC1L" },
1317 { "SPKR", "DAC1R", "DAC1R" },
1318 { "SPKR", "DAC2L", "DAC2L" },
1319 { "SPKR", "DAC2R", "DAC2R" },
1320
1321 { "SPKL PGA", NULL, "SPKL" },
1322 { "SPKR PGA", NULL, "SPKR" },
1323
1324 { "SPKDAT", NULL, "SPKL PGA" },
1325 { "SPKDAT", NULL, "SPKR PGA" },
1326};
1327
1328static int wm8996_readable_register(struct snd_soc_codec *codec,
1329 unsigned int reg)
1330{
1331 /* Due to the sparseness of the register map the compiler
1332 * output from an explicit switch statement ends up being much
1333 * more efficient than a table.
1334 */
1335 switch (reg) {
1336 case WM8996_SOFTWARE_RESET:
1337 case WM8996_POWER_MANAGEMENT_1:
1338 case WM8996_POWER_MANAGEMENT_2:
1339 case WM8996_POWER_MANAGEMENT_3:
1340 case WM8996_POWER_MANAGEMENT_4:
1341 case WM8996_POWER_MANAGEMENT_5:
1342 case WM8996_POWER_MANAGEMENT_6:
1343 case WM8996_POWER_MANAGEMENT_7:
1344 case WM8996_POWER_MANAGEMENT_8:
1345 case WM8996_LEFT_LINE_INPUT_VOLUME:
1346 case WM8996_RIGHT_LINE_INPUT_VOLUME:
1347 case WM8996_LINE_INPUT_CONTROL:
1348 case WM8996_DAC1_HPOUT1_VOLUME:
1349 case WM8996_DAC2_HPOUT2_VOLUME:
1350 case WM8996_DAC1_LEFT_VOLUME:
1351 case WM8996_DAC1_RIGHT_VOLUME:
1352 case WM8996_DAC2_LEFT_VOLUME:
1353 case WM8996_DAC2_RIGHT_VOLUME:
1354 case WM8996_OUTPUT1_LEFT_VOLUME:
1355 case WM8996_OUTPUT1_RIGHT_VOLUME:
1356 case WM8996_OUTPUT2_LEFT_VOLUME:
1357 case WM8996_OUTPUT2_RIGHT_VOLUME:
1358 case WM8996_MICBIAS_1:
1359 case WM8996_MICBIAS_2:
1360 case WM8996_LDO_1:
1361 case WM8996_LDO_2:
1362 case WM8996_ACCESSORY_DETECT_MODE_1:
1363 case WM8996_ACCESSORY_DETECT_MODE_2:
1364 case WM8996_HEADPHONE_DETECT_1:
1365 case WM8996_HEADPHONE_DETECT_2:
1366 case WM8996_MIC_DETECT_1:
1367 case WM8996_MIC_DETECT_2:
1368 case WM8996_MIC_DETECT_3:
1369 case WM8996_CHARGE_PUMP_1:
1370 case WM8996_CHARGE_PUMP_2:
1371 case WM8996_DC_SERVO_1:
1372 case WM8996_DC_SERVO_2:
1373 case WM8996_DC_SERVO_3:
1374 case WM8996_DC_SERVO_5:
1375 case WM8996_DC_SERVO_6:
1376 case WM8996_DC_SERVO_7:
1377 case WM8996_DC_SERVO_READBACK_0:
1378 case WM8996_ANALOGUE_HP_1:
1379 case WM8996_ANALOGUE_HP_2:
1380 case WM8996_CHIP_REVISION:
1381 case WM8996_CONTROL_INTERFACE_1:
1382 case WM8996_WRITE_SEQUENCER_CTRL_1:
1383 case WM8996_WRITE_SEQUENCER_CTRL_2:
1384 case WM8996_AIF_CLOCKING_1:
1385 case WM8996_AIF_CLOCKING_2:
1386 case WM8996_CLOCKING_1:
1387 case WM8996_CLOCKING_2:
1388 case WM8996_AIF_RATE:
1389 case WM8996_FLL_CONTROL_1:
1390 case WM8996_FLL_CONTROL_2:
1391 case WM8996_FLL_CONTROL_3:
1392 case WM8996_FLL_CONTROL_4:
1393 case WM8996_FLL_CONTROL_5:
1394 case WM8996_FLL_CONTROL_6:
1395 case WM8996_FLL_EFS_1:
1396 case WM8996_FLL_EFS_2:
1397 case WM8996_AIF1_CONTROL:
1398 case WM8996_AIF1_BCLK:
1399 case WM8996_AIF1_TX_LRCLK_1:
1400 case WM8996_AIF1_TX_LRCLK_2:
1401 case WM8996_AIF1_RX_LRCLK_1:
1402 case WM8996_AIF1_RX_LRCLK_2:
1403 case WM8996_AIF1TX_DATA_CONFIGURATION_1:
1404 case WM8996_AIF1TX_DATA_CONFIGURATION_2:
1405 case WM8996_AIF1RX_DATA_CONFIGURATION:
1406 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
1407 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
1408 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
1409 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
1410 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
1411 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
1412 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
1413 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
1414 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
1415 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
1416 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
1417 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
1418 case WM8996_AIF1RX_MONO_CONFIGURATION:
1419 case WM8996_AIF1TX_TEST:
1420 case WM8996_AIF2_CONTROL:
1421 case WM8996_AIF2_BCLK:
1422 case WM8996_AIF2_TX_LRCLK_1:
1423 case WM8996_AIF2_TX_LRCLK_2:
1424 case WM8996_AIF2_RX_LRCLK_1:
1425 case WM8996_AIF2_RX_LRCLK_2:
1426 case WM8996_AIF2TX_DATA_CONFIGURATION_1:
1427 case WM8996_AIF2TX_DATA_CONFIGURATION_2:
1428 case WM8996_AIF2RX_DATA_CONFIGURATION:
1429 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
1430 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
1431 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
1432 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
1433 case WM8996_AIF2RX_MONO_CONFIGURATION:
1434 case WM8996_AIF2TX_TEST:
1435 case WM8996_DSP1_TX_LEFT_VOLUME:
1436 case WM8996_DSP1_TX_RIGHT_VOLUME:
1437 case WM8996_DSP1_RX_LEFT_VOLUME:
1438 case WM8996_DSP1_RX_RIGHT_VOLUME:
1439 case WM8996_DSP1_TX_FILTERS:
1440 case WM8996_DSP1_RX_FILTERS_1:
1441 case WM8996_DSP1_RX_FILTERS_2:
1442 case WM8996_DSP1_DRC_1:
1443 case WM8996_DSP1_DRC_2:
1444 case WM8996_DSP1_DRC_3:
1445 case WM8996_DSP1_DRC_4:
1446 case WM8996_DSP1_DRC_5:
1447 case WM8996_DSP1_RX_EQ_GAINS_1:
1448 case WM8996_DSP1_RX_EQ_GAINS_2:
1449 case WM8996_DSP1_RX_EQ_BAND_1_A:
1450 case WM8996_DSP1_RX_EQ_BAND_1_B:
1451 case WM8996_DSP1_RX_EQ_BAND_1_PG:
1452 case WM8996_DSP1_RX_EQ_BAND_2_A:
1453 case WM8996_DSP1_RX_EQ_BAND_2_B:
1454 case WM8996_DSP1_RX_EQ_BAND_2_C:
1455 case WM8996_DSP1_RX_EQ_BAND_2_PG:
1456 case WM8996_DSP1_RX_EQ_BAND_3_A:
1457 case WM8996_DSP1_RX_EQ_BAND_3_B:
1458 case WM8996_DSP1_RX_EQ_BAND_3_C:
1459 case WM8996_DSP1_RX_EQ_BAND_3_PG:
1460 case WM8996_DSP1_RX_EQ_BAND_4_A:
1461 case WM8996_DSP1_RX_EQ_BAND_4_B:
1462 case WM8996_DSP1_RX_EQ_BAND_4_C:
1463 case WM8996_DSP1_RX_EQ_BAND_4_PG:
1464 case WM8996_DSP1_RX_EQ_BAND_5_A:
1465 case WM8996_DSP1_RX_EQ_BAND_5_B:
1466 case WM8996_DSP1_RX_EQ_BAND_5_PG:
1467 case WM8996_DSP2_TX_LEFT_VOLUME:
1468 case WM8996_DSP2_TX_RIGHT_VOLUME:
1469 case WM8996_DSP2_RX_LEFT_VOLUME:
1470 case WM8996_DSP2_RX_RIGHT_VOLUME:
1471 case WM8996_DSP2_TX_FILTERS:
1472 case WM8996_DSP2_RX_FILTERS_1:
1473 case WM8996_DSP2_RX_FILTERS_2:
1474 case WM8996_DSP2_DRC_1:
1475 case WM8996_DSP2_DRC_2:
1476 case WM8996_DSP2_DRC_3:
1477 case WM8996_DSP2_DRC_4:
1478 case WM8996_DSP2_DRC_5:
1479 case WM8996_DSP2_RX_EQ_GAINS_1:
1480 case WM8996_DSP2_RX_EQ_GAINS_2:
1481 case WM8996_DSP2_RX_EQ_BAND_1_A:
1482 case WM8996_DSP2_RX_EQ_BAND_1_B:
1483 case WM8996_DSP2_RX_EQ_BAND_1_PG:
1484 case WM8996_DSP2_RX_EQ_BAND_2_A:
1485 case WM8996_DSP2_RX_EQ_BAND_2_B:
1486 case WM8996_DSP2_RX_EQ_BAND_2_C:
1487 case WM8996_DSP2_RX_EQ_BAND_2_PG:
1488 case WM8996_DSP2_RX_EQ_BAND_3_A:
1489 case WM8996_DSP2_RX_EQ_BAND_3_B:
1490 case WM8996_DSP2_RX_EQ_BAND_3_C:
1491 case WM8996_DSP2_RX_EQ_BAND_3_PG:
1492 case WM8996_DSP2_RX_EQ_BAND_4_A:
1493 case WM8996_DSP2_RX_EQ_BAND_4_B:
1494 case WM8996_DSP2_RX_EQ_BAND_4_C:
1495 case WM8996_DSP2_RX_EQ_BAND_4_PG:
1496 case WM8996_DSP2_RX_EQ_BAND_5_A:
1497 case WM8996_DSP2_RX_EQ_BAND_5_B:
1498 case WM8996_DSP2_RX_EQ_BAND_5_PG:
1499 case WM8996_DAC1_MIXER_VOLUMES:
1500 case WM8996_DAC1_LEFT_MIXER_ROUTING:
1501 case WM8996_DAC1_RIGHT_MIXER_ROUTING:
1502 case WM8996_DAC2_MIXER_VOLUMES:
1503 case WM8996_DAC2_LEFT_MIXER_ROUTING:
1504 case WM8996_DAC2_RIGHT_MIXER_ROUTING:
1505 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
1506 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
1507 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
1508 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
1509 case WM8996_DSP_TX_MIXER_SELECT:
1510 case WM8996_DAC_SOFTMUTE:
1511 case WM8996_OVERSAMPLING:
1512 case WM8996_SIDETONE:
1513 case WM8996_GPIO_1:
1514 case WM8996_GPIO_2:
1515 case WM8996_GPIO_3:
1516 case WM8996_GPIO_4:
1517 case WM8996_GPIO_5:
1518 case WM8996_PULL_CONTROL_1:
1519 case WM8996_PULL_CONTROL_2:
1520 case WM8996_INTERRUPT_STATUS_1:
1521 case WM8996_INTERRUPT_STATUS_2:
1522 case WM8996_INTERRUPT_RAW_STATUS_2:
1523 case WM8996_INTERRUPT_STATUS_1_MASK:
1524 case WM8996_INTERRUPT_STATUS_2_MASK:
1525 case WM8996_INTERRUPT_CONTROL:
1526 case WM8996_LEFT_PDM_SPEAKER:
1527 case WM8996_RIGHT_PDM_SPEAKER:
1528 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
1529 case WM8996_PDM_SPEAKER_VOLUME:
1530 return 1;
1531 default:
1532 return 0;
1533 }
1534}
1535
1536static int wm8996_volatile_register(struct snd_soc_codec *codec,
1537 unsigned int reg)
1538{
1539 switch (reg) {
1540 case WM8996_SOFTWARE_RESET:
1541 case WM8996_CHIP_REVISION:
1542 case WM8996_LDO_1:
1543 case WM8996_LDO_2:
1544 case WM8996_INTERRUPT_STATUS_1:
1545 case WM8996_INTERRUPT_STATUS_2:
1546 case WM8996_INTERRUPT_RAW_STATUS_2:
1547 case WM8996_DC_SERVO_READBACK_0:
1548 case WM8996_DC_SERVO_2:
1549 case WM8996_DC_SERVO_6:
1550 case WM8996_DC_SERVO_7:
1551 case WM8996_FLL_CONTROL_6:
1552 case WM8996_MIC_DETECT_3:
1553 case WM8996_HEADPHONE_DETECT_1:
1554 case WM8996_HEADPHONE_DETECT_2:
1555 return 1;
1556 default:
1557 return 0;
1558 }
1559}
1560
1561static int wm8996_reset(struct snd_soc_codec *codec)
1562{
1563 return snd_soc_write(codec, WM8996_SOFTWARE_RESET, 0x8915);
1564}
1565
1566static const int bclk_divs[] = {
1567 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1568};
1569
1570static void wm8996_update_bclk(struct snd_soc_codec *codec)
1571{
1572 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1573 int aif, best, cur_val, bclk_rate, bclk_reg, i;
1574
1575 /* Don't bother if we're in a low frequency idle mode that
1576 * can't support audio.
1577 */
1578 if (wm8996->sysclk < 64000)
1579 return;
1580
1581 for (aif = 0; aif < WM8996_AIFS; aif++) {
1582 switch (aif) {
1583 case 0:
1584 bclk_reg = WM8996_AIF1_BCLK;
1585 break;
1586 case 1:
1587 bclk_reg = WM8996_AIF2_BCLK;
1588 break;
1589 }
1590
1591 bclk_rate = wm8996->bclk_rate[aif];
1592
1593 /* Pick a divisor for BCLK as close as we can get to ideal */
1594 best = 0;
1595 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1596 cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
1597 if (cur_val < 0) /* BCLK table is sorted */
1598 break;
1599 best = i;
1600 }
1601 bclk_rate = wm8996->sysclk / bclk_divs[best];
1602 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1603 bclk_divs[best], bclk_rate);
1604
1605 snd_soc_update_bits(codec, bclk_reg,
1606 WM8996_AIF1_BCLK_DIV_MASK, best);
1607 }
1608}
1609
1610static int wm8996_set_bias_level(struct snd_soc_codec *codec,
1611 enum snd_soc_bias_level level)
1612{
1613 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1614 int ret;
1615
1616 switch (level) {
1617 case SND_SOC_BIAS_ON:
1618 break;
1619
1620 case SND_SOC_BIAS_PREPARE:
1621 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1622 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
1623 WM8996_BG_ENA, WM8996_BG_ENA);
1624 msleep(2);
1625 }
1626 break;
1627
1628 case SND_SOC_BIAS_STANDBY:
1629 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1630 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
1631 wm8996->supplies);
1632 if (ret != 0) {
1633 dev_err(codec->dev,
1634 "Failed to enable supplies: %d\n",
1635 ret);
1636 return ret;
1637 }
1638
1639 if (wm8996->pdata.ldo_ena >= 0) {
1640 gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
1641 1);
1642 msleep(5);
1643 }
1644
1645 codec->cache_only = false;
1646 snd_soc_cache_sync(codec);
1647 }
1648
1649 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
1650 WM8996_BG_ENA, 0);
1651 break;
1652
1653 case SND_SOC_BIAS_OFF:
1654 codec->cache_only = true;
1655 if (wm8996->pdata.ldo_ena >= 0)
1656 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1657 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
1658 wm8996->supplies);
1659 break;
1660 }
1661
1662 codec->dapm.bias_level = level;
1663
1664 return 0;
1665}
1666
1667static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1668{
1669 struct snd_soc_codec *codec = dai->codec;
1670 int aifctrl = 0;
1671 int bclk = 0;
1672 int lrclk_tx = 0;
1673 int lrclk_rx = 0;
1674 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1675
1676 switch (dai->id) {
1677 case 0:
1678 aifctrl_reg = WM8996_AIF1_CONTROL;
1679 bclk_reg = WM8996_AIF1_BCLK;
1680 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
1681 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
1682 break;
1683 case 1:
1684 aifctrl_reg = WM8996_AIF2_CONTROL;
1685 bclk_reg = WM8996_AIF2_BCLK;
1686 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
1687 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
1688 break;
1689 default:
1690 BUG();
1691 return -EINVAL;
1692 }
1693
1694 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1695 case SND_SOC_DAIFMT_NB_NF:
1696 break;
1697 case SND_SOC_DAIFMT_IB_NF:
1698 bclk |= WM8996_AIF1_BCLK_INV;
1699 break;
1700 case SND_SOC_DAIFMT_NB_IF:
1701 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1702 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1703 break;
1704 case SND_SOC_DAIFMT_IB_IF:
1705 bclk |= WM8996_AIF1_BCLK_INV;
1706 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1707 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1708 break;
1709 }
1710
1711 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1712 case SND_SOC_DAIFMT_CBS_CFS:
1713 break;
1714 case SND_SOC_DAIFMT_CBS_CFM:
1715 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1716 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1717 break;
1718 case SND_SOC_DAIFMT_CBM_CFS:
1719 bclk |= WM8996_AIF1_BCLK_MSTR;
1720 break;
1721 case SND_SOC_DAIFMT_CBM_CFM:
1722 bclk |= WM8996_AIF1_BCLK_MSTR;
1723 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1724 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1725 break;
1726 default:
1727 return -EINVAL;
1728 }
1729
1730 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1731 case SND_SOC_DAIFMT_DSP_A:
1732 break;
1733 case SND_SOC_DAIFMT_DSP_B:
1734 aifctrl |= 1;
1735 break;
1736 case SND_SOC_DAIFMT_I2S:
1737 aifctrl |= 2;
1738 break;
1739 case SND_SOC_DAIFMT_LEFT_J:
1740 aifctrl |= 3;
1741 break;
1742 default:
1743 return -EINVAL;
1744 }
1745
1746 snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
1747 snd_soc_update_bits(codec, bclk_reg,
1748 WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
1749 bclk);
1750 snd_soc_update_bits(codec, lrclk_tx_reg,
1751 WM8996_AIF1TX_LRCLK_INV |
1752 WM8996_AIF1TX_LRCLK_MSTR,
1753 lrclk_tx);
1754 snd_soc_update_bits(codec, lrclk_rx_reg,
1755 WM8996_AIF1RX_LRCLK_INV |
1756 WM8996_AIF1RX_LRCLK_MSTR,
1757 lrclk_rx);
1758
1759 return 0;
1760}
1761
1762static const int dsp_divs[] = {
1763 48000, 32000, 16000, 8000
1764};
1765
1766static int wm8996_hw_params(struct snd_pcm_substream *substream,
1767 struct snd_pcm_hw_params *params,
1768 struct snd_soc_dai *dai)
1769{
1770 struct snd_soc_codec *codec = dai->codec;
1771 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1772 int bits, i, bclk_rate;
1773 int aifdata = 0;
1774 int lrclk = 0;
1775 int dsp = 0;
1776 int aifdata_reg, lrclk_reg, dsp_shift;
1777
1778 switch (dai->id) {
1779 case 0:
1780 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1781 (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
1782 aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
1783 lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
1784 } else {
1785 aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
1786 lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
1787 }
1788 dsp_shift = 0;
1789 break;
1790 case 1:
1791 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1792 (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
1793 aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
1794 lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
1795 } else {
1796 aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
1797 lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
1798 }
1799 dsp_shift = WM8996_DSP2_DIV_SHIFT;
1800 break;
1801 default:
1802 BUG();
1803 return -EINVAL;
1804 }
1805
1806 bclk_rate = snd_soc_params_to_bclk(params);
1807 if (bclk_rate < 0) {
1808 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1809 return bclk_rate;
1810 }
1811
1812 wm8996->bclk_rate[dai->id] = bclk_rate;
1813 wm8996->rx_rate[dai->id] = params_rate(params);
1814
1815 /* Needs looking at for TDM */
1816 bits = snd_pcm_format_width(params_format(params));
1817 if (bits < 0)
1818 return bits;
1819 aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
1820
1821 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1822 if (dsp_divs[i] == params_rate(params))
1823 break;
1824 }
1825 if (i == ARRAY_SIZE(dsp_divs)) {
1826 dev_err(codec->dev, "Unsupported sample rate %dHz\n",
1827 params_rate(params));
1828 return -EINVAL;
1829 }
1830 dsp |= i << dsp_shift;
1831
1832 wm8996_update_bclk(codec);
1833
1834 lrclk = bclk_rate / params_rate(params);
1835 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1836 lrclk, bclk_rate / lrclk);
1837
1838 snd_soc_update_bits(codec, aifdata_reg,
1839 WM8996_AIF1TX_WL_MASK |
1840 WM8996_AIF1TX_SLOT_LEN_MASK,
1841 aifdata);
1842 snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
1843 lrclk);
1844 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2,
1845 WM8996_DSP1_DIV_SHIFT << dsp_shift, dsp);
1846
1847 return 0;
1848}
1849
1850static int wm8996_set_sysclk(struct snd_soc_dai *dai,
1851 int clk_id, unsigned int freq, int dir)
1852{
1853 struct snd_soc_codec *codec = dai->codec;
1854 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1855 int lfclk = 0;
1856 int ratediv = 0;
1857 int src;
1858 int old;
1859
1860 if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
1861 return 0;
1862
1863 /* Disable SYSCLK while we reconfigure */
1864 old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
1865 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1866 WM8996_SYSCLK_ENA, 0);
1867
1868 switch (clk_id) {
1869 case WM8996_SYSCLK_MCLK1:
1870 wm8996->sysclk = freq;
1871 src = 0;
1872 break;
1873 case WM8996_SYSCLK_MCLK2:
1874 wm8996->sysclk = freq;
1875 src = 1;
1876 break;
1877 case WM8996_SYSCLK_FLL:
1878 wm8996->sysclk = freq;
1879 src = 2;
1880 break;
1881 default:
1882 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
1883 return -EINVAL;
1884 }
1885
1886 switch (wm8996->sysclk) {
1887 case 6144000:
1888 snd_soc_update_bits(codec, WM8996_AIF_RATE,
1889 WM8996_SYSCLK_RATE, 0);
1890 break;
1891 case 24576000:
1892 ratediv = WM8996_SYSCLK_DIV;
1893 case 12288000:
1894 snd_soc_update_bits(codec, WM8996_AIF_RATE,
1895 WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
1896 break;
1897 case 32000:
1898 case 32768:
1899 lfclk = WM8996_LFCLK_ENA;
1900 break;
1901 default:
1902 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
1903 wm8996->sysclk);
1904 return -EINVAL;
1905 }
1906
1907 wm8996_update_bclk(codec);
1908
1909 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1910 WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
1911 src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
1912 snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
1913 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1914 WM8996_SYSCLK_ENA, old);
1915
1916 wm8996->sysclk_src = clk_id;
1917
1918 return 0;
1919}
1920
1921struct _fll_div {
1922 u16 fll_fratio;
1923 u16 fll_outdiv;
1924 u16 fll_refclk_div;
1925 u16 fll_loop_gain;
1926 u16 fll_ref_freq;
1927 u16 n;
1928 u16 theta;
1929 u16 lambda;
1930};
1931
1932static struct {
1933 unsigned int min;
1934 unsigned int max;
1935 u16 fll_fratio;
1936 int ratio;
1937} fll_fratios[] = {
1938 { 0, 64000, 4, 16 },
1939 { 64000, 128000, 3, 8 },
1940 { 128000, 256000, 2, 4 },
1941 { 256000, 1000000, 1, 2 },
1942 { 1000000, 13500000, 0, 1 },
1943};
1944
1945static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1946 unsigned int Fout)
1947{
1948 unsigned int target;
1949 unsigned int div;
1950 unsigned int fratio, gcd_fll;
1951 int i;
1952
1953 /* Fref must be <=13.5MHz */
1954 div = 1;
1955 fll_div->fll_refclk_div = 0;
1956 while ((Fref / div) > 13500000) {
1957 div *= 2;
1958 fll_div->fll_refclk_div++;
1959
1960 if (div > 8) {
1961 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1962 Fref);
1963 return -EINVAL;
1964 }
1965 }
1966
1967 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1968
1969 /* Apply the division for our remaining calculations */
1970 Fref /= div;
1971
1972 if (Fref >= 3000000)
1973 fll_div->fll_loop_gain = 5;
1974 else
1975 fll_div->fll_loop_gain = 0;
1976
1977 if (Fref >= 48000)
1978 fll_div->fll_ref_freq = 0;
1979 else
1980 fll_div->fll_ref_freq = 1;
1981
1982 /* Fvco should be 90-100MHz; don't check the upper bound */
1983 div = 2;
1984 while (Fout * div < 90000000) {
1985 div++;
1986 if (div > 64) {
1987 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1988 Fout);
1989 return -EINVAL;
1990 }
1991 }
1992 target = Fout * div;
1993 fll_div->fll_outdiv = div - 1;
1994
1995 pr_debug("FLL Fvco=%dHz\n", target);
1996
1997 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1998 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1999 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2000 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2001 fratio = fll_fratios[i].ratio;
2002 break;
2003 }
2004 }
2005 if (i == ARRAY_SIZE(fll_fratios)) {
2006 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2007 return -EINVAL;
2008 }
2009
2010 fll_div->n = target / (fratio * Fref);
2011
2012 if (target % Fref == 0) {
2013 fll_div->theta = 0;
2014 fll_div->lambda = 0;
2015 } else {
2016 gcd_fll = gcd(target, fratio * Fref);
2017
2018 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2019 / gcd_fll;
2020 fll_div->lambda = (fratio * Fref) / gcd_fll;
2021 }
2022
2023 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2024 fll_div->n, fll_div->theta, fll_div->lambda);
2025 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2026 fll_div->fll_fratio, fll_div->fll_outdiv,
2027 fll_div->fll_refclk_div);
2028
2029 return 0;
2030}
2031
2032static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2033 unsigned int Fref, unsigned int Fout)
2034{
2035 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2036 struct i2c_client *i2c = to_i2c_client(codec->dev);
2037 struct _fll_div fll_div;
2038 unsigned long timeout;
2039 int ret, reg;
2040
2041 /* Any change? */
2042 if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
2043 Fout == wm8996->fll_fout)
2044 return 0;
2045
2046 if (Fout == 0) {
2047 dev_dbg(codec->dev, "FLL disabled\n");
2048
2049 wm8996->fll_fref = 0;
2050 wm8996->fll_fout = 0;
2051
2052 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2053 WM8996_FLL_ENA, 0);
2054
2055 return 0;
2056 }
2057
2058 ret = fll_factors(&fll_div, Fref, Fout);
2059 if (ret != 0)
2060 return ret;
2061
2062 switch (source) {
2063 case WM8996_FLL_MCLK1:
2064 reg = 0;
2065 break;
2066 case WM8996_FLL_MCLK2:
2067 reg = 1;
2068 break;
2069 case WM8996_FLL_DACLRCLK1:
2070 reg = 2;
2071 break;
2072 case WM8996_FLL_BCLK1:
2073 reg = 3;
2074 break;
2075 default:
2076 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2077 return -EINVAL;
2078 }
2079
2080 reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
2081 reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
2082
2083 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5,
2084 WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
2085 WM8996_FLL_REFCLK_SRC_MASK, reg);
2086
2087 reg = 0;
2088 if (fll_div.theta || fll_div.lambda)
2089 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
2090 else
2091 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
2092 snd_soc_write(codec, WM8996_FLL_EFS_2, reg);
2093
2094 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2,
2095 WM8996_FLL_OUTDIV_MASK |
2096 WM8996_FLL_FRATIO_MASK,
2097 (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
2098 (fll_div.fll_fratio));
2099
2100 snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta);
2101
2102 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4,
2103 WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
2104 (fll_div.n << WM8996_FLL_N_SHIFT) |
2105 fll_div.fll_loop_gain);
2106
2107 snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda);
2108
2109 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2110 WM8996_FLL_ENA, WM8996_FLL_ENA);
2111
2112 /* The FLL supports live reconfiguration - kick that in case we were
2113 * already enabled.
2114 */
2115 snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
2116
2117 /* Wait for the FLL to lock, using the interrupt if possible */
2118 if (Fref > 1000000)
2119 timeout = usecs_to_jiffies(300);
2120 else
2121 timeout = msecs_to_jiffies(2);
2122
2123 /* Allow substantially longer if we've actually got the IRQ */
2124 if (i2c->irq)
2125 timeout *= 1000;
2126
2127 ret = wait_for_completion_timeout(&wm8996->fll_lock, timeout);
2128
2129 if (ret == 0 && i2c->irq) {
2130 dev_err(codec->dev, "Timed out waiting for FLL\n");
2131 ret = -ETIMEDOUT;
2132 } else {
2133 ret = 0;
2134 }
2135
2136 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2137
2138 wm8996->fll_fref = Fref;
2139 wm8996->fll_fout = Fout;
2140 wm8996->fll_src = source;
2141
2142 return ret;
2143}
2144
2145#ifdef CONFIG_GPIOLIB
2146static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip)
2147{
2148 return container_of(chip, struct wm8996_priv, gpio_chip);
2149}
2150
2151static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2152{
2153 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2154 struct snd_soc_codec *codec = wm8996->codec;
2155
2156 snd_soc_update_bits(codec, WM8996_GPIO_1 + offset,
2157 WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
2158}
2159
2160static int wm8996_gpio_direction_out(struct gpio_chip *chip,
2161 unsigned offset, int value)
2162{
2163 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2164 struct snd_soc_codec *codec = wm8996->codec;
2165 int val;
2166
2167 val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
2168
2169 return snd_soc_update_bits(codec, WM8996_GPIO_1 + offset,
2170 WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
2171 WM8996_GP1_LVL, val);
2172}
2173
2174static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
2175{
2176 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2177 struct snd_soc_codec *codec = wm8996->codec;
2178 int ret;
2179
2180 ret = snd_soc_read(codec, WM8996_GPIO_1 + offset);
2181 if (ret < 0)
2182 return ret;
2183
2184 return (ret & WM8996_GP1_LVL) != 0;
2185}
2186
2187static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2188{
2189 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2190 struct snd_soc_codec *codec = wm8996->codec;
2191
2192 return snd_soc_update_bits(codec, WM8996_GPIO_1 + offset,
2193 WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
2194 (1 << WM8996_GP1_FN_SHIFT) |
2195 (1 << WM8996_GP1_DIR_SHIFT));
2196}
2197
2198static struct gpio_chip wm8996_template_chip = {
2199 .label = "wm8996",
2200 .owner = THIS_MODULE,
2201 .direction_output = wm8996_gpio_direction_out,
2202 .set = wm8996_gpio_set,
2203 .direction_input = wm8996_gpio_direction_in,
2204 .get = wm8996_gpio_get,
2205 .can_sleep = 1,
2206};
2207
2208static void wm8996_init_gpio(struct snd_soc_codec *codec)
2209{
2210 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2211 int ret;
2212
2213 wm8996->gpio_chip = wm8996_template_chip;
2214 wm8996->gpio_chip.ngpio = 5;
2215 wm8996->gpio_chip.dev = codec->dev;
2216
2217 if (wm8996->pdata.gpio_base)
2218 wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
2219 else
2220 wm8996->gpio_chip.base = -1;
2221
2222 ret = gpiochip_add(&wm8996->gpio_chip);
2223 if (ret != 0)
2224 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
2225}
2226
2227static void wm8996_free_gpio(struct snd_soc_codec *codec)
2228{
2229 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2230 int ret;
2231
2232 ret = gpiochip_remove(&wm8996->gpio_chip);
2233 if (ret != 0)
2234 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
2235}
2236#else
2237static void wm8996_init_gpio(struct snd_soc_codec *codec)
2238{
2239}
2240
2241static void wm8996_free_gpio(struct snd_soc_codec *codec)
2242{
2243}
2244#endif
2245
2246/**
2247 * wm8996_detect - Enable default WM8996 jack detection
2248 *
2249 * The WM8996 has advanced accessory detection support for headsets.
2250 * This function provides a default implementation which integrates
2251 * the majority of this functionality with minimal user configuration.
2252 *
2253 * This will detect headset, headphone and short circuit button and
2254 * will also detect inverted microphone ground connections and update
2255 * the polarity of the connections.
2256 */
2257int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2258 wm8996_polarity_fn polarity_cb)
2259{
2260 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2261
2262 wm8996->jack = jack;
2263 wm8996->detecting = true;
2264 wm8996->polarity_cb = polarity_cb;
2265
2266 if (wm8996->polarity_cb)
2267 wm8996->polarity_cb(codec, 0);
2268
2269 /* Clear discarge to avoid noise during detection */
2270 snd_soc_update_bits(codec, WM8996_MICBIAS_1,
2271 WM8996_MICB1_DISCH, 0);
2272 snd_soc_update_bits(codec, WM8996_MICBIAS_2,
2273 WM8996_MICB2_DISCH, 0);
2274
2275 /* LDO2 powers the microphones, SYSCLK clocks detection */
2276 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2277 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2278
2279 /* We start off just enabling microphone detection - even a
2280 * plain headphone will trigger detection.
2281 */
2282 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2283 WM8996_MICD_ENA, WM8996_MICD_ENA);
2284
2285 /* Slowest detection rate, gives debounce for initial detection */
2286 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2287 WM8996_MICD_RATE_MASK,
2288 WM8996_MICD_RATE_MASK);
2289
2290 /* Enable interrupts and we're off */
2291 snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK,
2292 WM8996_IM_MICD_EINT, 0);
2293
2294 return 0;
2295}
2296EXPORT_SYMBOL_GPL(wm8996_detect);
2297
2298static void wm8996_micd(struct snd_soc_codec *codec)
2299{
2300 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2301 int val, reg;
2302
2303 val = snd_soc_read(codec, WM8996_MIC_DETECT_3);
2304
2305 dev_dbg(codec->dev, "Microphone event: %x\n", val);
2306
2307 if (!(val & WM8996_MICD_VALID)) {
2308 dev_warn(codec->dev, "Microphone detection state invalid\n");
2309 return;
2310 }
2311
2312 /* No accessory, reset everything and report removal */
2313 if (!(val & WM8996_MICD_STS)) {
2314 dev_dbg(codec->dev, "Jack removal detected\n");
2315 wm8996->jack_mic = false;
2316 wm8996->detecting = true;
2317 snd_soc_jack_report(wm8996->jack, 0,
2318 SND_JACK_HEADSET | SND_JACK_BTN_0);
2319 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2320 WM8996_MICD_RATE_MASK,
2321 WM8996_MICD_RATE_MASK);
2322 return;
2323 }
2324
2325 /* If the measurement is very high we've got a microphone but
2326 * do a little debounce to account for mechanical issues.
2327 */
2328 if (val & 0x400) {
2329 dev_dbg(codec->dev, "Microphone detected\n");
2330 snd_soc_jack_report(wm8996->jack, SND_JACK_HEADSET,
2331 SND_JACK_HEADSET | SND_JACK_BTN_0);
2332 wm8996->jack_mic = true;
2333 wm8996->detecting = false;
2334
2335 /* Increase poll rate to give better responsiveness
2336 * for buttons */
2337 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2338 WM8996_MICD_RATE_MASK,
2339 5 << WM8996_MICD_RATE_SHIFT);
2340 }
2341
2342 /* If we detected a lower impedence during initial startup
2343 * then we probably have the wrong polarity, flip it. Don't
2344 * do this for the lowest impedences to speed up detection of
2345 * plain headphones.
2346 */
2347 if (wm8996->detecting && (val & 0x3f0)) {
2348 reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2);
2349 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2350 WM8996_MICD_BIAS_SRC;
2351 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2352 WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2353 WM8996_MICD_BIAS_SRC, reg);
2354
2355 if (wm8996->polarity_cb)
2356 wm8996->polarity_cb(codec,
2357 (reg & WM8996_MICD_SRC) != 0);
2358
2359 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2360 (reg & WM8996_MICD_SRC) != 0);
2361
2362 return;
2363 }
2364
2365 /* Don't distinguish between buttons, just report any low
2366 * impedence as BTN_0.
2367 */
2368 if (val & 0x3fc) {
2369 if (wm8996->jack_mic) {
2370 dev_dbg(codec->dev, "Mic button detected\n");
2371 snd_soc_jack_report(wm8996->jack,
2372 SND_JACK_HEADSET | SND_JACK_BTN_0,
2373 SND_JACK_HEADSET | SND_JACK_BTN_0);
2374 } else {
2375 dev_dbg(codec->dev, "Headphone detected\n");
2376 snd_soc_jack_report(wm8996->jack,
2377 SND_JACK_HEADPHONE,
2378 SND_JACK_HEADSET |
2379 SND_JACK_BTN_0);
2380
2381 /* Increase the detection rate a bit for
2382 * responsiveness.
2383 */
2384 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2385 WM8996_MICD_RATE_MASK,
2386 7 << WM8996_MICD_RATE_SHIFT);
2387
2388 wm8996->detecting = false;
2389 }
2390 }
2391}
2392
2393static irqreturn_t wm8996_irq(int irq, void *data)
2394{
2395 struct snd_soc_codec *codec = data;
2396 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2397 int irq_val;
2398
2399 irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2);
2400 if (irq_val < 0) {
2401 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2402 irq_val);
2403 return IRQ_NONE;
2404 }
2405 irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK);
2406
2407 snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val);
2408
2409 if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
2410 dev_dbg(codec->dev, "DC servo IRQ\n");
2411 complete(&wm8996->dcs_done);
2412 }
2413
2414 if (irq_val & WM8996_FIFOS_ERR_EINT)
2415 dev_err(codec->dev, "Digital core FIFO error\n");
2416
2417 if (irq_val & WM8996_FLL_LOCK_EINT) {
2418 dev_dbg(codec->dev, "FLL locked\n");
2419 complete(&wm8996->fll_lock);
2420 }
2421
2422 if (irq_val & WM8996_MICD_EINT)
2423 wm8996_micd(codec);
2424
2425 if (irq_val)
2426 return IRQ_HANDLED;
2427 else
2428 return IRQ_NONE;
2429}
2430
2431static irqreturn_t wm8996_edge_irq(int irq, void *data)
2432{
2433 irqreturn_t ret = IRQ_NONE;
2434 irqreturn_t val;
2435
2436 do {
2437 val = wm8996_irq(irq, data);
2438 if (val != IRQ_NONE)
2439 ret = val;
2440 } while (val != IRQ_NONE);
2441
2442 return ret;
2443}
2444
2445static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec)
2446{
2447 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2448 struct wm8996_pdata *pdata = &wm8996->pdata;
2449
2450 struct snd_kcontrol_new controls[] = {
2451 SOC_ENUM_EXT("DSP1 EQ Mode",
2452 wm8996->retune_mobile_enum,
2453 wm8996_get_retune_mobile_enum,
2454 wm8996_put_retune_mobile_enum),
2455 SOC_ENUM_EXT("DSP2 EQ Mode",
2456 wm8996->retune_mobile_enum,
2457 wm8996_get_retune_mobile_enum,
2458 wm8996_put_retune_mobile_enum),
2459 };
2460 int ret, i, j;
2461 const char **t;
2462
2463 /* We need an array of texts for the enum API but the number
2464 * of texts is likely to be less than the number of
2465 * configurations due to the sample rate dependency of the
2466 * configurations. */
2467 wm8996->num_retune_mobile_texts = 0;
2468 wm8996->retune_mobile_texts = NULL;
2469 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2470 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
2471 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2472 wm8996->retune_mobile_texts[j]) == 0)
2473 break;
2474 }
2475
2476 if (j != wm8996->num_retune_mobile_texts)
2477 continue;
2478
2479 /* Expand the array... */
2480 t = krealloc(wm8996->retune_mobile_texts,
2481 sizeof(char *) *
2482 (wm8996->num_retune_mobile_texts + 1),
2483 GFP_KERNEL);
2484 if (t == NULL)
2485 continue;
2486
2487 /* ...store the new entry... */
2488 t[wm8996->num_retune_mobile_texts] =
2489 pdata->retune_mobile_cfgs[i].name;
2490
2491 /* ...and remember the new version. */
2492 wm8996->num_retune_mobile_texts++;
2493 wm8996->retune_mobile_texts = t;
2494 }
2495
2496 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2497 wm8996->num_retune_mobile_texts);
2498
2499 wm8996->retune_mobile_enum.max = wm8996->num_retune_mobile_texts;
2500 wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
2501
2502 ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
2503 if (ret != 0)
2504 dev_err(codec->dev,
2505 "Failed to add ReTune Mobile controls: %d\n", ret);
2506}
2507
2508static int wm8996_probe(struct snd_soc_codec *codec)
2509{
2510 int ret;
2511 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2512 struct i2c_client *i2c = to_i2c_client(codec->dev);
2513 struct snd_soc_dapm_context *dapm = &codec->dapm;
2514 int i, irq_flags;
2515
2516 wm8996->codec = codec;
2517
2518 init_completion(&wm8996->dcs_done);
2519 init_completion(&wm8996->fll_lock);
2520
2521 dapm->idle_bias_off = true;
2522 dapm->bias_level = SND_SOC_BIAS_OFF;
2523
2524 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
2525 if (ret != 0) {
2526 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2527 goto err;
2528 }
2529
2530 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
2531 wm8996->supplies[i].supply = wm8996_supply_names[i];
2532
2533 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8996->supplies),
2534 wm8996->supplies);
2535 if (ret != 0) {
2536 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
2537 goto err;
2538 }
2539
2540 wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
2541 wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
2542 wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
2543 wm8996->disable_nb[3].notifier_call = wm8996_regulator_event_3;
2544
2545 /* This should really be moved into the regulator core */
2546 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
2547 ret = regulator_register_notifier(wm8996->supplies[i].consumer,
2548 &wm8996->disable_nb[i]);
2549 if (ret != 0) {
2550 dev_err(codec->dev,
2551 "Failed to register regulator notifier: %d\n",
2552 ret);
2553 }
2554 }
2555
2556 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
2557 wm8996->supplies);
2558 if (ret != 0) {
2559 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
2560 goto err_get;
2561 }
2562
2563 if (wm8996->pdata.ldo_ena >= 0) {
2564 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
2565 msleep(5);
2566 }
2567
2568 ret = snd_soc_read(codec, WM8996_SOFTWARE_RESET);
2569 if (ret < 0) {
2570 dev_err(codec->dev, "Failed to read ID register: %d\n", ret);
2571 goto err_enable;
2572 }
2573 if (ret != 0x8915) {
2574 dev_err(codec->dev, "Device is not a WM8996, ID %x\n", ret);
2575 ret = -EINVAL;
2576 goto err_enable;
2577 }
2578
2579 ret = snd_soc_read(codec, WM8996_CHIP_REVISION);
2580 if (ret < 0) {
2581 dev_err(codec->dev, "Failed to read device revision: %d\n",
2582 ret);
2583 goto err_enable;
2584 }
2585
2586 dev_info(codec->dev, "revision %c\n",
2587 (ret & WM8996_CHIP_REV_MASK) + 'A');
2588
2589 if (wm8996->pdata.ldo_ena >= 0) {
2590 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
2591 } else {
2592 ret = wm8996_reset(codec);
2593 if (ret < 0) {
2594 dev_err(codec->dev, "Failed to issue reset\n");
2595 goto err_enable;
2596 }
2597 }
2598
2599 codec->cache_only = true;
2600
2601 /* Apply platform data settings */
2602 snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL,
2603 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2604 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2605 wm8996->pdata.inr_mode);
2606
2607 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2608 if (!wm8996->pdata.gpio_default[i])
2609 continue;
2610
2611 snd_soc_write(codec, WM8996_GPIO_1 + i,
2612 wm8996->pdata.gpio_default[i] & 0xffff);
2613 }
2614
2615 if (wm8996->pdata.spkmute_seq)
2616 snd_soc_update_bits(codec, WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2617 WM8996_SPK_MUTE_ENDIAN |
2618 WM8996_SPK_MUTE_SEQ1_MASK,
2619 wm8996->pdata.spkmute_seq);
2620
2621 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2622 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2623 WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2624
2625 /* Latch volume update bits */
2626 snd_soc_update_bits(codec, WM8996_LEFT_LINE_INPUT_VOLUME,
2627 WM8996_IN1_VU, WM8996_IN1_VU);
2628 snd_soc_update_bits(codec, WM8996_RIGHT_LINE_INPUT_VOLUME,
2629 WM8996_IN1_VU, WM8996_IN1_VU);
2630
2631 snd_soc_update_bits(codec, WM8996_DAC1_LEFT_VOLUME,
2632 WM8996_DAC1_VU, WM8996_DAC1_VU);
2633 snd_soc_update_bits(codec, WM8996_DAC1_RIGHT_VOLUME,
2634 WM8996_DAC1_VU, WM8996_DAC1_VU);
2635 snd_soc_update_bits(codec, WM8996_DAC2_LEFT_VOLUME,
2636 WM8996_DAC2_VU, WM8996_DAC2_VU);
2637 snd_soc_update_bits(codec, WM8996_DAC2_RIGHT_VOLUME,
2638 WM8996_DAC2_VU, WM8996_DAC2_VU);
2639
2640 snd_soc_update_bits(codec, WM8996_OUTPUT1_LEFT_VOLUME,
2641 WM8996_DAC1_VU, WM8996_DAC1_VU);
2642 snd_soc_update_bits(codec, WM8996_OUTPUT1_RIGHT_VOLUME,
2643 WM8996_DAC1_VU, WM8996_DAC1_VU);
2644 snd_soc_update_bits(codec, WM8996_OUTPUT2_LEFT_VOLUME,
2645 WM8996_DAC2_VU, WM8996_DAC2_VU);
2646 snd_soc_update_bits(codec, WM8996_OUTPUT2_RIGHT_VOLUME,
2647 WM8996_DAC2_VU, WM8996_DAC2_VU);
2648
2649 snd_soc_update_bits(codec, WM8996_DSP1_TX_LEFT_VOLUME,
2650 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2651 snd_soc_update_bits(codec, WM8996_DSP1_TX_RIGHT_VOLUME,
2652 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2653 snd_soc_update_bits(codec, WM8996_DSP2_TX_LEFT_VOLUME,
2654 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2655 snd_soc_update_bits(codec, WM8996_DSP2_TX_RIGHT_VOLUME,
2656 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2657
2658 snd_soc_update_bits(codec, WM8996_DSP1_RX_LEFT_VOLUME,
2659 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2660 snd_soc_update_bits(codec, WM8996_DSP1_RX_RIGHT_VOLUME,
2661 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2662 snd_soc_update_bits(codec, WM8996_DSP2_RX_LEFT_VOLUME,
2663 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2664 snd_soc_update_bits(codec, WM8996_DSP2_RX_RIGHT_VOLUME,
2665 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2666
2667 /* No support currently for the underclocked TDM modes and
2668 * pick a default TDM layout with each channel pair working with
2669 * slots 0 and 1. */
2670 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2671 WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2672 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2673 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2674 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2675 WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2676 WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2677 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2678 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2679 WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2680 WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2681 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2682 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2683 WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2684 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2685 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2686 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2687 WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2688 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2689 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2690 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2691 WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2692 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2693 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2694
2695 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2696 WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2697 WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2698 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2699 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2700 WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2701 WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2702 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2703
2704 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2705 WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2706 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2707 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2708 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2709 WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2710 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2711 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2712 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
2713 WM8996_AIF1TX_CHAN2_SLOTS_MASK |
2714 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2715 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2716 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
2717 WM8996_AIF1TX_CHAN3_SLOTS_MASK |
2718 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2719 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2720 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
2721 WM8996_AIF1TX_CHAN4_SLOTS_MASK |
2722 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2723 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2724 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
2725 WM8996_AIF1TX_CHAN5_SLOTS_MASK |
2726 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2727 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
2728
2729 snd_soc_update_bits(codec, WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
2730 WM8996_AIF2TX_CHAN0_SLOTS_MASK |
2731 WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
2732 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
2733 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2734 WM8996_AIF2TX_CHAN1_SLOTS_MASK |
2735 WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
2736 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2737
2738 if (wm8996->pdata.num_retune_mobile_cfgs)
2739 wm8996_retune_mobile_pdata(codec);
2740 else
2741 snd_soc_add_controls(codec, wm8996_eq_controls,
2742 ARRAY_SIZE(wm8996_eq_controls));
2743
2744 /* If the TX LRCLK pins are not in LRCLK mode configure the
2745 * AIFs to source their clocks from the RX LRCLKs.
2746 */
2747 if ((snd_soc_read(codec, WM8996_GPIO_1)))
2748 snd_soc_update_bits(codec, WM8996_AIF1_TX_LRCLK_2,
2749 WM8996_AIF1TX_LRCLK_MODE,
2750 WM8996_AIF1TX_LRCLK_MODE);
2751
2752 if ((snd_soc_read(codec, WM8996_GPIO_2)))
2753 snd_soc_update_bits(codec, WM8996_AIF2_TX_LRCLK_2,
2754 WM8996_AIF2TX_LRCLK_MODE,
2755 WM8996_AIF2TX_LRCLK_MODE);
2756
2757 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2758
2759 wm8996_init_gpio(codec);
2760
2761 if (i2c->irq) {
2762 if (wm8996->pdata.irq_flags)
2763 irq_flags = wm8996->pdata.irq_flags;
2764 else
2765 irq_flags = IRQF_TRIGGER_LOW;
2766
2767 irq_flags |= IRQF_ONESHOT;
2768
2769 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2770 ret = request_threaded_irq(i2c->irq, NULL,
2771 wm8996_edge_irq,
2772 irq_flags, "wm8996", codec);
2773 else
2774 ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
2775 irq_flags, "wm8996", codec);
2776
2777 if (ret == 0) {
2778 /* Unmask the interrupt */
2779 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
2780 WM8996_IM_IRQ, 0);
2781
2782 /* Enable error reporting and DC servo status */
2783 snd_soc_update_bits(codec,
2784 WM8996_INTERRUPT_STATUS_2_MASK,
2785 WM8996_IM_DCS_DONE_23_EINT |
2786 WM8996_IM_DCS_DONE_01_EINT |
2787 WM8996_IM_FLL_LOCK_EINT |
2788 WM8996_IM_FIFOS_ERR_EINT,
2789 0);
2790 } else {
2791 dev_err(codec->dev, "Failed to request IRQ: %d\n",
2792 ret);
2793 }
2794 }
2795
2796 return 0;
2797
2798err_enable:
2799 if (wm8996->pdata.ldo_ena >= 0)
2800 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
2801
2802 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2803err_get:
2804 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2805err:
2806 return ret;
2807}
2808
2809static int wm8996_remove(struct snd_soc_codec *codec)
2810{
2811 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2812 struct i2c_client *i2c = to_i2c_client(codec->dev);
2813 int i;
2814
2815 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
2816 WM8996_IM_IRQ, WM8996_IM_IRQ);
2817
2818 if (i2c->irq)
2819 free_irq(i2c->irq, codec);
2820
2821 wm8996_free_gpio(codec);
2822
2823 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
2824 regulator_unregister_notifier(wm8996->supplies[i].consumer,
2825 &wm8996->disable_nb[i]);
2826 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2827
2828 return 0;
2829}
2830
2831static struct snd_soc_codec_driver soc_codec_dev_wm8996 = {
2832 .probe = wm8996_probe,
2833 .remove = wm8996_remove,
2834 .set_bias_level = wm8996_set_bias_level,
2835 .seq_notifier = wm8996_seq_notifier,
2836 .reg_cache_size = WM8996_MAX_REGISTER + 1,
2837 .reg_word_size = sizeof(u16),
2838 .reg_cache_default = wm8996_reg,
2839 .volatile_register = wm8996_volatile_register,
2840 .readable_register = wm8996_readable_register,
2841 .compress_type = SND_SOC_RBTREE_COMPRESSION,
2842 .controls = wm8996_snd_controls,
2843 .num_controls = ARRAY_SIZE(wm8996_snd_controls),
2844 .dapm_widgets = wm8996_dapm_widgets,
2845 .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
2846 .dapm_routes = wm8996_dapm_routes,
2847 .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
2848 .set_pll = wm8996_set_fll,
2849};
2850
2851#define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
2852 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
2853#define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
2854 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
2855 SNDRV_PCM_FMTBIT_S32_LE)
2856
2857static struct snd_soc_dai_ops wm8996_dai_ops = {
2858 .set_fmt = wm8996_set_fmt,
2859 .hw_params = wm8996_hw_params,
2860 .set_sysclk = wm8996_set_sysclk,
2861};
2862
2863static struct snd_soc_dai_driver wm8996_dai[] = {
2864 {
2865 .name = "wm8996-aif1",
2866 .playback = {
2867 .stream_name = "AIF1 Playback",
2868 .channels_min = 1,
2869 .channels_max = 6,
2870 .rates = WM8996_RATES,
2871 .formats = WM8996_FORMATS,
2872 },
2873 .capture = {
2874 .stream_name = "AIF1 Capture",
2875 .channels_min = 1,
2876 .channels_max = 6,
2877 .rates = WM8996_RATES,
2878 .formats = WM8996_FORMATS,
2879 },
2880 .ops = &wm8996_dai_ops,
2881 },
2882 {
2883 .name = "wm8996-aif2",
2884 .playback = {
2885 .stream_name = "AIF2 Playback",
2886 .channels_min = 1,
2887 .channels_max = 2,
2888 .rates = WM8996_RATES,
2889 .formats = WM8996_FORMATS,
2890 },
2891 .capture = {
2892 .stream_name = "AIF2 Capture",
2893 .channels_min = 1,
2894 .channels_max = 2,
2895 .rates = WM8996_RATES,
2896 .formats = WM8996_FORMATS,
2897 },
2898 .ops = &wm8996_dai_ops,
2899 },
2900};
2901
2902static __devinit int wm8996_i2c_probe(struct i2c_client *i2c,
2903 const struct i2c_device_id *id)
2904{
2905 struct wm8996_priv *wm8996;
2906 int ret;
2907
2908 wm8996 = kzalloc(sizeof(struct wm8996_priv), GFP_KERNEL);
2909 if (wm8996 == NULL)
2910 return -ENOMEM;
2911
2912 i2c_set_clientdata(i2c, wm8996);
2913
2914 if (dev_get_platdata(&i2c->dev))
2915 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
2916 sizeof(wm8996->pdata));
2917
2918 if (wm8996->pdata.ldo_ena > 0) {
2919 ret = gpio_request_one(wm8996->pdata.ldo_ena,
2920 GPIOF_OUT_INIT_LOW, "WM8996 ENA");
2921 if (ret < 0) {
2922 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
2923 wm8996->pdata.ldo_ena, ret);
2924 goto err;
2925 }
2926 }
2927
2928 ret = snd_soc_register_codec(&i2c->dev,
2929 &soc_codec_dev_wm8996, wm8996_dai,
2930 ARRAY_SIZE(wm8996_dai));
2931 if (ret < 0)
2932 goto err_gpio;
2933
2934 return ret;
2935
2936err_gpio:
2937 if (wm8996->pdata.ldo_ena > 0)
2938 gpio_free(wm8996->pdata.ldo_ena);
2939err:
2940 kfree(wm8996);
2941
2942 return ret;
2943}
2944
2945static __devexit int wm8996_i2c_remove(struct i2c_client *client)
2946{
2947 struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
2948
2949 snd_soc_unregister_codec(&client->dev);
2950 if (wm8996->pdata.ldo_ena > 0)
2951 gpio_free(wm8996->pdata.ldo_ena);
2952 kfree(i2c_get_clientdata(client));
2953 return 0;
2954}
2955
2956static const struct i2c_device_id wm8996_i2c_id[] = {
2957 { "wm8996", 0 },
2958 { }
2959};
2960MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
2961
2962static struct i2c_driver wm8996_i2c_driver = {
2963 .driver = {
2964 .name = "wm8996",
2965 .owner = THIS_MODULE,
2966 },
2967 .probe = wm8996_i2c_probe,
2968 .remove = __devexit_p(wm8996_i2c_remove),
2969 .id_table = wm8996_i2c_id,
2970};
2971
2972static int __init wm8996_modinit(void)
2973{
2974 int ret;
2975
2976 ret = i2c_add_driver(&wm8996_i2c_driver);
2977 if (ret != 0) {
2978 printk(KERN_ERR "Failed to register WM8996 I2C driver: %d\n",
2979 ret);
2980 }
2981
2982 return ret;
2983}
2984module_init(wm8996_modinit);
2985
2986static void __exit wm8996_exit(void)
2987{
2988 i2c_del_driver(&wm8996_i2c_driver);
2989}
2990module_exit(wm8996_exit);
2991
2992MODULE_DESCRIPTION("ASoC WM8996 driver");
2993MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2994MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/wm8996.h b/sound/soc/codecs/wm8996.h
new file mode 100644
index 000000000000..0fde643194ce
--- /dev/null
+++ b/sound/soc/codecs/wm8996.h
@@ -0,0 +1,3717 @@
1/*
2 * wm8996.h - WM8996 audio codec interface
3 *
4 * Copyright 2011 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef _WM8996_H
14#define _WM8996_H
15
16#define WM8996_SYSCLK_MCLK1 1
17#define WM8996_SYSCLK_MCLK2 2
18#define WM8996_SYSCLK_FLL 3
19
20#define WM8996_FLL_MCLK1 1
21#define WM8996_FLL_MCLK2 2
22#define WM8996_FLL_DACLRCLK1 3
23#define WM8996_FLL_BCLK1 4
24
25typedef void (*wm8996_polarity_fn)(struct snd_soc_codec *codec, int polarity);
26
27int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
28 wm8996_polarity_fn polarity_cb);
29
30/*
31 * Register values.
32 */
33#define WM8996_SOFTWARE_RESET 0x00
34#define WM8996_POWER_MANAGEMENT_1 0x01
35#define WM8996_POWER_MANAGEMENT_2 0x02
36#define WM8996_POWER_MANAGEMENT_3 0x03
37#define WM8996_POWER_MANAGEMENT_4 0x04
38#define WM8996_POWER_MANAGEMENT_5 0x05
39#define WM8996_POWER_MANAGEMENT_6 0x06
40#define WM8996_POWER_MANAGEMENT_7 0x07
41#define WM8996_POWER_MANAGEMENT_8 0x08
42#define WM8996_LEFT_LINE_INPUT_VOLUME 0x10
43#define WM8996_RIGHT_LINE_INPUT_VOLUME 0x11
44#define WM8996_LINE_INPUT_CONTROL 0x12
45#define WM8996_DAC1_HPOUT1_VOLUME 0x15
46#define WM8996_DAC2_HPOUT2_VOLUME 0x16
47#define WM8996_DAC1_LEFT_VOLUME 0x18
48#define WM8996_DAC1_RIGHT_VOLUME 0x19
49#define WM8996_DAC2_LEFT_VOLUME 0x1A
50#define WM8996_DAC2_RIGHT_VOLUME 0x1B
51#define WM8996_OUTPUT1_LEFT_VOLUME 0x1C
52#define WM8996_OUTPUT1_RIGHT_VOLUME 0x1D
53#define WM8996_OUTPUT2_LEFT_VOLUME 0x1E
54#define WM8996_OUTPUT2_RIGHT_VOLUME 0x1F
55#define WM8996_MICBIAS_1 0x20
56#define WM8996_MICBIAS_2 0x21
57#define WM8996_LDO_1 0x28
58#define WM8996_LDO_2 0x29
59#define WM8996_ACCESSORY_DETECT_MODE_1 0x30
60#define WM8996_ACCESSORY_DETECT_MODE_2 0x31
61#define WM8996_HEADPHONE_DETECT_1 0x34
62#define WM8996_HEADPHONE_DETECT_2 0x35
63#define WM8996_MIC_DETECT_1 0x38
64#define WM8996_MIC_DETECT_2 0x39
65#define WM8996_MIC_DETECT_3 0x3A
66#define WM8996_CHARGE_PUMP_1 0x40
67#define WM8996_CHARGE_PUMP_2 0x41
68#define WM8996_DC_SERVO_1 0x50
69#define WM8996_DC_SERVO_2 0x51
70#define WM8996_DC_SERVO_3 0x52
71#define WM8996_DC_SERVO_5 0x54
72#define WM8996_DC_SERVO_6 0x55
73#define WM8996_DC_SERVO_7 0x56
74#define WM8996_DC_SERVO_READBACK_0 0x57
75#define WM8996_ANALOGUE_HP_1 0x60
76#define WM8996_ANALOGUE_HP_2 0x61
77#define WM8996_CHIP_REVISION 0x100
78#define WM8996_CONTROL_INTERFACE_1 0x101
79#define WM8996_WRITE_SEQUENCER_CTRL_1 0x110
80#define WM8996_WRITE_SEQUENCER_CTRL_2 0x111
81#define WM8996_AIF_CLOCKING_1 0x200
82#define WM8996_AIF_CLOCKING_2 0x201
83#define WM8996_CLOCKING_1 0x208
84#define WM8996_CLOCKING_2 0x209
85#define WM8996_AIF_RATE 0x210
86#define WM8996_FLL_CONTROL_1 0x220
87#define WM8996_FLL_CONTROL_2 0x221
88#define WM8996_FLL_CONTROL_3 0x222
89#define WM8996_FLL_CONTROL_4 0x223
90#define WM8996_FLL_CONTROL_5 0x224
91#define WM8996_FLL_CONTROL_6 0x225
92#define WM8996_FLL_EFS_1 0x226
93#define WM8996_FLL_EFS_2 0x227
94#define WM8996_AIF1_CONTROL 0x300
95#define WM8996_AIF1_BCLK 0x301
96#define WM8996_AIF1_TX_LRCLK_1 0x302
97#define WM8996_AIF1_TX_LRCLK_2 0x303
98#define WM8996_AIF1_RX_LRCLK_1 0x304
99#define WM8996_AIF1_RX_LRCLK_2 0x305
100#define WM8996_AIF1TX_DATA_CONFIGURATION_1 0x306
101#define WM8996_AIF1TX_DATA_CONFIGURATION_2 0x307
102#define WM8996_AIF1RX_DATA_CONFIGURATION 0x308
103#define WM8996_AIF1TX_CHANNEL_0_CONFIGURATION 0x309
104#define WM8996_AIF1TX_CHANNEL_1_CONFIGURATION 0x30A
105#define WM8996_AIF1TX_CHANNEL_2_CONFIGURATION 0x30B
106#define WM8996_AIF1TX_CHANNEL_3_CONFIGURATION 0x30C
107#define WM8996_AIF1TX_CHANNEL_4_CONFIGURATION 0x30D
108#define WM8996_AIF1TX_CHANNEL_5_CONFIGURATION 0x30E
109#define WM8996_AIF1RX_CHANNEL_0_CONFIGURATION 0x30F
110#define WM8996_AIF1RX_CHANNEL_1_CONFIGURATION 0x310
111#define WM8996_AIF1RX_CHANNEL_2_CONFIGURATION 0x311
112#define WM8996_AIF1RX_CHANNEL_3_CONFIGURATION 0x312
113#define WM8996_AIF1RX_CHANNEL_4_CONFIGURATION 0x313
114#define WM8996_AIF1RX_CHANNEL_5_CONFIGURATION 0x314
115#define WM8996_AIF1RX_MONO_CONFIGURATION 0x315
116#define WM8996_AIF1TX_TEST 0x31A
117#define WM8996_AIF2_CONTROL 0x320
118#define WM8996_AIF2_BCLK 0x321
119#define WM8996_AIF2_TX_LRCLK_1 0x322
120#define WM8996_AIF2_TX_LRCLK_2 0x323
121#define WM8996_AIF2_RX_LRCLK_1 0x324
122#define WM8996_AIF2_RX_LRCLK_2 0x325
123#define WM8996_AIF2TX_DATA_CONFIGURATION_1 0x326
124#define WM8996_AIF2TX_DATA_CONFIGURATION_2 0x327
125#define WM8996_AIF2RX_DATA_CONFIGURATION 0x328
126#define WM8996_AIF2TX_CHANNEL_0_CONFIGURATION 0x329
127#define WM8996_AIF2TX_CHANNEL_1_CONFIGURATION 0x32A
128#define WM8996_AIF2RX_CHANNEL_0_CONFIGURATION 0x32B
129#define WM8996_AIF2RX_CHANNEL_1_CONFIGURATION 0x32C
130#define WM8996_AIF2RX_MONO_CONFIGURATION 0x32D
131#define WM8996_AIF2TX_TEST 0x32F
132#define WM8996_DSP1_TX_LEFT_VOLUME 0x400
133#define WM8996_DSP1_TX_RIGHT_VOLUME 0x401
134#define WM8996_DSP1_RX_LEFT_VOLUME 0x402
135#define WM8996_DSP1_RX_RIGHT_VOLUME 0x403
136#define WM8996_DSP1_TX_FILTERS 0x410
137#define WM8996_DSP1_RX_FILTERS_1 0x420
138#define WM8996_DSP1_RX_FILTERS_2 0x421
139#define WM8996_DSP1_DRC_1 0x440
140#define WM8996_DSP1_DRC_2 0x441
141#define WM8996_DSP1_DRC_3 0x442
142#define WM8996_DSP1_DRC_4 0x443
143#define WM8996_DSP1_DRC_5 0x444
144#define WM8996_DSP1_RX_EQ_GAINS_1 0x480
145#define WM8996_DSP1_RX_EQ_GAINS_2 0x481
146#define WM8996_DSP1_RX_EQ_BAND_1_A 0x482
147#define WM8996_DSP1_RX_EQ_BAND_1_B 0x483
148#define WM8996_DSP1_RX_EQ_BAND_1_PG 0x484
149#define WM8996_DSP1_RX_EQ_BAND_2_A 0x485
150#define WM8996_DSP1_RX_EQ_BAND_2_B 0x486
151#define WM8996_DSP1_RX_EQ_BAND_2_C 0x487
152#define WM8996_DSP1_RX_EQ_BAND_2_PG 0x488
153#define WM8996_DSP1_RX_EQ_BAND_3_A 0x489
154#define WM8996_DSP1_RX_EQ_BAND_3_B 0x48A
155#define WM8996_DSP1_RX_EQ_BAND_3_C 0x48B
156#define WM8996_DSP1_RX_EQ_BAND_3_PG 0x48C
157#define WM8996_DSP1_RX_EQ_BAND_4_A 0x48D
158#define WM8996_DSP1_RX_EQ_BAND_4_B 0x48E
159#define WM8996_DSP1_RX_EQ_BAND_4_C 0x48F
160#define WM8996_DSP1_RX_EQ_BAND_4_PG 0x490
161#define WM8996_DSP1_RX_EQ_BAND_5_A 0x491
162#define WM8996_DSP1_RX_EQ_BAND_5_B 0x492
163#define WM8996_DSP1_RX_EQ_BAND_5_PG 0x493
164#define WM8996_DSP2_TX_LEFT_VOLUME 0x500
165#define WM8996_DSP2_TX_RIGHT_VOLUME 0x501
166#define WM8996_DSP2_RX_LEFT_VOLUME 0x502
167#define WM8996_DSP2_RX_RIGHT_VOLUME 0x503
168#define WM8996_DSP2_TX_FILTERS 0x510
169#define WM8996_DSP2_RX_FILTERS_1 0x520
170#define WM8996_DSP2_RX_FILTERS_2 0x521
171#define WM8996_DSP2_DRC_1 0x540
172#define WM8996_DSP2_DRC_2 0x541
173#define WM8996_DSP2_DRC_3 0x542
174#define WM8996_DSP2_DRC_4 0x543
175#define WM8996_DSP2_DRC_5 0x544
176#define WM8996_DSP2_RX_EQ_GAINS_1 0x580
177#define WM8996_DSP2_RX_EQ_GAINS_2 0x581
178#define WM8996_DSP2_RX_EQ_BAND_1_A 0x582
179#define WM8996_DSP2_RX_EQ_BAND_1_B 0x583
180#define WM8996_DSP2_RX_EQ_BAND_1_PG 0x584
181#define WM8996_DSP2_RX_EQ_BAND_2_A 0x585
182#define WM8996_DSP2_RX_EQ_BAND_2_B 0x586
183#define WM8996_DSP2_RX_EQ_BAND_2_C 0x587
184#define WM8996_DSP2_RX_EQ_BAND_2_PG 0x588
185#define WM8996_DSP2_RX_EQ_BAND_3_A 0x589
186#define WM8996_DSP2_RX_EQ_BAND_3_B 0x58A
187#define WM8996_DSP2_RX_EQ_BAND_3_C 0x58B
188#define WM8996_DSP2_RX_EQ_BAND_3_PG 0x58C
189#define WM8996_DSP2_RX_EQ_BAND_4_A 0x58D
190#define WM8996_DSP2_RX_EQ_BAND_4_B 0x58E
191#define WM8996_DSP2_RX_EQ_BAND_4_C 0x58F
192#define WM8996_DSP2_RX_EQ_BAND_4_PG 0x590
193#define WM8996_DSP2_RX_EQ_BAND_5_A 0x591
194#define WM8996_DSP2_RX_EQ_BAND_5_B 0x592
195#define WM8996_DSP2_RX_EQ_BAND_5_PG 0x593
196#define WM8996_DAC1_MIXER_VOLUMES 0x600
197#define WM8996_DAC1_LEFT_MIXER_ROUTING 0x601
198#define WM8996_DAC1_RIGHT_MIXER_ROUTING 0x602
199#define WM8996_DAC2_MIXER_VOLUMES 0x603
200#define WM8996_DAC2_LEFT_MIXER_ROUTING 0x604
201#define WM8996_DAC2_RIGHT_MIXER_ROUTING 0x605
202#define WM8996_DSP1_TX_LEFT_MIXER_ROUTING 0x606
203#define WM8996_DSP1_TX_RIGHT_MIXER_ROUTING 0x607
204#define WM8996_DSP2_TX_LEFT_MIXER_ROUTING 0x608
205#define WM8996_DSP2_TX_RIGHT_MIXER_ROUTING 0x609
206#define WM8996_DSP_TX_MIXER_SELECT 0x60A
207#define WM8996_DAC_SOFTMUTE 0x610
208#define WM8996_OVERSAMPLING 0x620
209#define WM8996_SIDETONE 0x621
210#define WM8996_GPIO_1 0x700
211#define WM8996_GPIO_2 0x701
212#define WM8996_GPIO_3 0x702
213#define WM8996_GPIO_4 0x703
214#define WM8996_GPIO_5 0x704
215#define WM8996_PULL_CONTROL_1 0x720
216#define WM8996_PULL_CONTROL_2 0x721
217#define WM8996_INTERRUPT_STATUS_1 0x730
218#define WM8996_INTERRUPT_STATUS_2 0x731
219#define WM8996_INTERRUPT_RAW_STATUS_2 0x732
220#define WM8996_INTERRUPT_STATUS_1_MASK 0x738
221#define WM8996_INTERRUPT_STATUS_2_MASK 0x739
222#define WM8996_INTERRUPT_CONTROL 0x740
223#define WM8996_LEFT_PDM_SPEAKER 0x800
224#define WM8996_RIGHT_PDM_SPEAKER 0x801
225#define WM8996_PDM_SPEAKER_MUTE_SEQUENCE 0x802
226#define WM8996_PDM_SPEAKER_VOLUME 0x803
227#define WM8996_WRITE_SEQUENCER_0 0x3000
228#define WM8996_WRITE_SEQUENCER_1 0x3001
229#define WM8996_WRITE_SEQUENCER_2 0x3002
230#define WM8996_WRITE_SEQUENCER_3 0x3003
231#define WM8996_WRITE_SEQUENCER_4 0x3004
232#define WM8996_WRITE_SEQUENCER_5 0x3005
233#define WM8996_WRITE_SEQUENCER_6 0x3006
234#define WM8996_WRITE_SEQUENCER_7 0x3007
235#define WM8996_WRITE_SEQUENCER_8 0x3008
236#define WM8996_WRITE_SEQUENCER_9 0x3009
237#define WM8996_WRITE_SEQUENCER_10 0x300A
238#define WM8996_WRITE_SEQUENCER_11 0x300B
239#define WM8996_WRITE_SEQUENCER_12 0x300C
240#define WM8996_WRITE_SEQUENCER_13 0x300D
241#define WM8996_WRITE_SEQUENCER_14 0x300E
242#define WM8996_WRITE_SEQUENCER_15 0x300F
243#define WM8996_WRITE_SEQUENCER_16 0x3010
244#define WM8996_WRITE_SEQUENCER_17 0x3011
245#define WM8996_WRITE_SEQUENCER_18 0x3012
246#define WM8996_WRITE_SEQUENCER_19 0x3013
247#define WM8996_WRITE_SEQUENCER_20 0x3014
248#define WM8996_WRITE_SEQUENCER_21 0x3015
249#define WM8996_WRITE_SEQUENCER_22 0x3016
250#define WM8996_WRITE_SEQUENCER_23 0x3017
251#define WM8996_WRITE_SEQUENCER_24 0x3018
252#define WM8996_WRITE_SEQUENCER_25 0x3019
253#define WM8996_WRITE_SEQUENCER_26 0x301A
254#define WM8996_WRITE_SEQUENCER_27 0x301B
255#define WM8996_WRITE_SEQUENCER_28 0x301C
256#define WM8996_WRITE_SEQUENCER_29 0x301D
257#define WM8996_WRITE_SEQUENCER_30 0x301E
258#define WM8996_WRITE_SEQUENCER_31 0x301F
259#define WM8996_WRITE_SEQUENCER_32 0x3020
260#define WM8996_WRITE_SEQUENCER_33 0x3021
261#define WM8996_WRITE_SEQUENCER_34 0x3022
262#define WM8996_WRITE_SEQUENCER_35 0x3023
263#define WM8996_WRITE_SEQUENCER_36 0x3024
264#define WM8996_WRITE_SEQUENCER_37 0x3025
265#define WM8996_WRITE_SEQUENCER_38 0x3026
266#define WM8996_WRITE_SEQUENCER_39 0x3027
267#define WM8996_WRITE_SEQUENCER_40 0x3028
268#define WM8996_WRITE_SEQUENCER_41 0x3029
269#define WM8996_WRITE_SEQUENCER_42 0x302A
270#define WM8996_WRITE_SEQUENCER_43 0x302B
271#define WM8996_WRITE_SEQUENCER_44 0x302C
272#define WM8996_WRITE_SEQUENCER_45 0x302D
273#define WM8996_WRITE_SEQUENCER_46 0x302E
274#define WM8996_WRITE_SEQUENCER_47 0x302F
275#define WM8996_WRITE_SEQUENCER_48 0x3030
276#define WM8996_WRITE_SEQUENCER_49 0x3031
277#define WM8996_WRITE_SEQUENCER_50 0x3032
278#define WM8996_WRITE_SEQUENCER_51 0x3033
279#define WM8996_WRITE_SEQUENCER_52 0x3034
280#define WM8996_WRITE_SEQUENCER_53 0x3035
281#define WM8996_WRITE_SEQUENCER_54 0x3036
282#define WM8996_WRITE_SEQUENCER_55 0x3037
283#define WM8996_WRITE_SEQUENCER_56 0x3038
284#define WM8996_WRITE_SEQUENCER_57 0x3039
285#define WM8996_WRITE_SEQUENCER_58 0x303A
286#define WM8996_WRITE_SEQUENCER_59 0x303B
287#define WM8996_WRITE_SEQUENCER_60 0x303C
288#define WM8996_WRITE_SEQUENCER_61 0x303D
289#define WM8996_WRITE_SEQUENCER_62 0x303E
290#define WM8996_WRITE_SEQUENCER_63 0x303F
291#define WM8996_WRITE_SEQUENCER_64 0x3040
292#define WM8996_WRITE_SEQUENCER_65 0x3041
293#define WM8996_WRITE_SEQUENCER_66 0x3042
294#define WM8996_WRITE_SEQUENCER_67 0x3043
295#define WM8996_WRITE_SEQUENCER_68 0x3044
296#define WM8996_WRITE_SEQUENCER_69 0x3045
297#define WM8996_WRITE_SEQUENCER_70 0x3046
298#define WM8996_WRITE_SEQUENCER_71 0x3047
299#define WM8996_WRITE_SEQUENCER_72 0x3048
300#define WM8996_WRITE_SEQUENCER_73 0x3049
301#define WM8996_WRITE_SEQUENCER_74 0x304A
302#define WM8996_WRITE_SEQUENCER_75 0x304B
303#define WM8996_WRITE_SEQUENCER_76 0x304C
304#define WM8996_WRITE_SEQUENCER_77 0x304D
305#define WM8996_WRITE_SEQUENCER_78 0x304E
306#define WM8996_WRITE_SEQUENCER_79 0x304F
307#define WM8996_WRITE_SEQUENCER_80 0x3050
308#define WM8996_WRITE_SEQUENCER_81 0x3051
309#define WM8996_WRITE_SEQUENCER_82 0x3052
310#define WM8996_WRITE_SEQUENCER_83 0x3053
311#define WM8996_WRITE_SEQUENCER_84 0x3054
312#define WM8996_WRITE_SEQUENCER_85 0x3055
313#define WM8996_WRITE_SEQUENCER_86 0x3056
314#define WM8996_WRITE_SEQUENCER_87 0x3057
315#define WM8996_WRITE_SEQUENCER_88 0x3058
316#define WM8996_WRITE_SEQUENCER_89 0x3059
317#define WM8996_WRITE_SEQUENCER_90 0x305A
318#define WM8996_WRITE_SEQUENCER_91 0x305B
319#define WM8996_WRITE_SEQUENCER_92 0x305C
320#define WM8996_WRITE_SEQUENCER_93 0x305D
321#define WM8996_WRITE_SEQUENCER_94 0x305E
322#define WM8996_WRITE_SEQUENCER_95 0x305F
323#define WM8996_WRITE_SEQUENCER_96 0x3060
324#define WM8996_WRITE_SEQUENCER_97 0x3061
325#define WM8996_WRITE_SEQUENCER_98 0x3062
326#define WM8996_WRITE_SEQUENCER_99 0x3063
327#define WM8996_WRITE_SEQUENCER_100 0x3064
328#define WM8996_WRITE_SEQUENCER_101 0x3065
329#define WM8996_WRITE_SEQUENCER_102 0x3066
330#define WM8996_WRITE_SEQUENCER_103 0x3067
331#define WM8996_WRITE_SEQUENCER_104 0x3068
332#define WM8996_WRITE_SEQUENCER_105 0x3069
333#define WM8996_WRITE_SEQUENCER_106 0x306A
334#define WM8996_WRITE_SEQUENCER_107 0x306B
335#define WM8996_WRITE_SEQUENCER_108 0x306C
336#define WM8996_WRITE_SEQUENCER_109 0x306D
337#define WM8996_WRITE_SEQUENCER_110 0x306E
338#define WM8996_WRITE_SEQUENCER_111 0x306F
339#define WM8996_WRITE_SEQUENCER_112 0x3070
340#define WM8996_WRITE_SEQUENCER_113 0x3071
341#define WM8996_WRITE_SEQUENCER_114 0x3072
342#define WM8996_WRITE_SEQUENCER_115 0x3073
343#define WM8996_WRITE_SEQUENCER_116 0x3074
344#define WM8996_WRITE_SEQUENCER_117 0x3075
345#define WM8996_WRITE_SEQUENCER_118 0x3076
346#define WM8996_WRITE_SEQUENCER_119 0x3077
347#define WM8996_WRITE_SEQUENCER_120 0x3078
348#define WM8996_WRITE_SEQUENCER_121 0x3079
349#define WM8996_WRITE_SEQUENCER_122 0x307A
350#define WM8996_WRITE_SEQUENCER_123 0x307B
351#define WM8996_WRITE_SEQUENCER_124 0x307C
352#define WM8996_WRITE_SEQUENCER_125 0x307D
353#define WM8996_WRITE_SEQUENCER_126 0x307E
354#define WM8996_WRITE_SEQUENCER_127 0x307F
355#define WM8996_WRITE_SEQUENCER_128 0x3080
356#define WM8996_WRITE_SEQUENCER_129 0x3081
357#define WM8996_WRITE_SEQUENCER_130 0x3082
358#define WM8996_WRITE_SEQUENCER_131 0x3083
359#define WM8996_WRITE_SEQUENCER_132 0x3084
360#define WM8996_WRITE_SEQUENCER_133 0x3085
361#define WM8996_WRITE_SEQUENCER_134 0x3086
362#define WM8996_WRITE_SEQUENCER_135 0x3087
363#define WM8996_WRITE_SEQUENCER_136 0x3088
364#define WM8996_WRITE_SEQUENCER_137 0x3089
365#define WM8996_WRITE_SEQUENCER_138 0x308A
366#define WM8996_WRITE_SEQUENCER_139 0x308B
367#define WM8996_WRITE_SEQUENCER_140 0x308C
368#define WM8996_WRITE_SEQUENCER_141 0x308D
369#define WM8996_WRITE_SEQUENCER_142 0x308E
370#define WM8996_WRITE_SEQUENCER_143 0x308F
371#define WM8996_WRITE_SEQUENCER_144 0x3090
372#define WM8996_WRITE_SEQUENCER_145 0x3091
373#define WM8996_WRITE_SEQUENCER_146 0x3092
374#define WM8996_WRITE_SEQUENCER_147 0x3093
375#define WM8996_WRITE_SEQUENCER_148 0x3094
376#define WM8996_WRITE_SEQUENCER_149 0x3095
377#define WM8996_WRITE_SEQUENCER_150 0x3096
378#define WM8996_WRITE_SEQUENCER_151 0x3097
379#define WM8996_WRITE_SEQUENCER_152 0x3098
380#define WM8996_WRITE_SEQUENCER_153 0x3099
381#define WM8996_WRITE_SEQUENCER_154 0x309A
382#define WM8996_WRITE_SEQUENCER_155 0x309B
383#define WM8996_WRITE_SEQUENCER_156 0x309C
384#define WM8996_WRITE_SEQUENCER_157 0x309D
385#define WM8996_WRITE_SEQUENCER_158 0x309E
386#define WM8996_WRITE_SEQUENCER_159 0x309F
387#define WM8996_WRITE_SEQUENCER_160 0x30A0
388#define WM8996_WRITE_SEQUENCER_161 0x30A1
389#define WM8996_WRITE_SEQUENCER_162 0x30A2
390#define WM8996_WRITE_SEQUENCER_163 0x30A3
391#define WM8996_WRITE_SEQUENCER_164 0x30A4
392#define WM8996_WRITE_SEQUENCER_165 0x30A5
393#define WM8996_WRITE_SEQUENCER_166 0x30A6
394#define WM8996_WRITE_SEQUENCER_167 0x30A7
395#define WM8996_WRITE_SEQUENCER_168 0x30A8
396#define WM8996_WRITE_SEQUENCER_169 0x30A9
397#define WM8996_WRITE_SEQUENCER_170 0x30AA
398#define WM8996_WRITE_SEQUENCER_171 0x30AB
399#define WM8996_WRITE_SEQUENCER_172 0x30AC
400#define WM8996_WRITE_SEQUENCER_173 0x30AD
401#define WM8996_WRITE_SEQUENCER_174 0x30AE
402#define WM8996_WRITE_SEQUENCER_175 0x30AF
403#define WM8996_WRITE_SEQUENCER_176 0x30B0
404#define WM8996_WRITE_SEQUENCER_177 0x30B1
405#define WM8996_WRITE_SEQUENCER_178 0x30B2
406#define WM8996_WRITE_SEQUENCER_179 0x30B3
407#define WM8996_WRITE_SEQUENCER_180 0x30B4
408#define WM8996_WRITE_SEQUENCER_181 0x30B5
409#define WM8996_WRITE_SEQUENCER_182 0x30B6
410#define WM8996_WRITE_SEQUENCER_183 0x30B7
411#define WM8996_WRITE_SEQUENCER_184 0x30B8
412#define WM8996_WRITE_SEQUENCER_185 0x30B9
413#define WM8996_WRITE_SEQUENCER_186 0x30BA
414#define WM8996_WRITE_SEQUENCER_187 0x30BB
415#define WM8996_WRITE_SEQUENCER_188 0x30BC
416#define WM8996_WRITE_SEQUENCER_189 0x30BD
417#define WM8996_WRITE_SEQUENCER_190 0x30BE
418#define WM8996_WRITE_SEQUENCER_191 0x30BF
419#define WM8996_WRITE_SEQUENCER_192 0x30C0
420#define WM8996_WRITE_SEQUENCER_193 0x30C1
421#define WM8996_WRITE_SEQUENCER_194 0x30C2
422#define WM8996_WRITE_SEQUENCER_195 0x30C3
423#define WM8996_WRITE_SEQUENCER_196 0x30C4
424#define WM8996_WRITE_SEQUENCER_197 0x30C5
425#define WM8996_WRITE_SEQUENCER_198 0x30C6
426#define WM8996_WRITE_SEQUENCER_199 0x30C7
427#define WM8996_WRITE_SEQUENCER_200 0x30C8
428#define WM8996_WRITE_SEQUENCER_201 0x30C9
429#define WM8996_WRITE_SEQUENCER_202 0x30CA
430#define WM8996_WRITE_SEQUENCER_203 0x30CB
431#define WM8996_WRITE_SEQUENCER_204 0x30CC
432#define WM8996_WRITE_SEQUENCER_205 0x30CD
433#define WM8996_WRITE_SEQUENCER_206 0x30CE
434#define WM8996_WRITE_SEQUENCER_207 0x30CF
435#define WM8996_WRITE_SEQUENCER_208 0x30D0
436#define WM8996_WRITE_SEQUENCER_209 0x30D1
437#define WM8996_WRITE_SEQUENCER_210 0x30D2
438#define WM8996_WRITE_SEQUENCER_211 0x30D3
439#define WM8996_WRITE_SEQUENCER_212 0x30D4
440#define WM8996_WRITE_SEQUENCER_213 0x30D5
441#define WM8996_WRITE_SEQUENCER_214 0x30D6
442#define WM8996_WRITE_SEQUENCER_215 0x30D7
443#define WM8996_WRITE_SEQUENCER_216 0x30D8
444#define WM8996_WRITE_SEQUENCER_217 0x30D9
445#define WM8996_WRITE_SEQUENCER_218 0x30DA
446#define WM8996_WRITE_SEQUENCER_219 0x30DB
447#define WM8996_WRITE_SEQUENCER_220 0x30DC
448#define WM8996_WRITE_SEQUENCER_221 0x30DD
449#define WM8996_WRITE_SEQUENCER_222 0x30DE
450#define WM8996_WRITE_SEQUENCER_223 0x30DF
451#define WM8996_WRITE_SEQUENCER_224 0x30E0
452#define WM8996_WRITE_SEQUENCER_225 0x30E1
453#define WM8996_WRITE_SEQUENCER_226 0x30E2
454#define WM8996_WRITE_SEQUENCER_227 0x30E3
455#define WM8996_WRITE_SEQUENCER_228 0x30E4
456#define WM8996_WRITE_SEQUENCER_229 0x30E5
457#define WM8996_WRITE_SEQUENCER_230 0x30E6
458#define WM8996_WRITE_SEQUENCER_231 0x30E7
459#define WM8996_WRITE_SEQUENCER_232 0x30E8
460#define WM8996_WRITE_SEQUENCER_233 0x30E9
461#define WM8996_WRITE_SEQUENCER_234 0x30EA
462#define WM8996_WRITE_SEQUENCER_235 0x30EB
463#define WM8996_WRITE_SEQUENCER_236 0x30EC
464#define WM8996_WRITE_SEQUENCER_237 0x30ED
465#define WM8996_WRITE_SEQUENCER_238 0x30EE
466#define WM8996_WRITE_SEQUENCER_239 0x30EF
467#define WM8996_WRITE_SEQUENCER_240 0x30F0
468#define WM8996_WRITE_SEQUENCER_241 0x30F1
469#define WM8996_WRITE_SEQUENCER_242 0x30F2
470#define WM8996_WRITE_SEQUENCER_243 0x30F3
471#define WM8996_WRITE_SEQUENCER_244 0x30F4
472#define WM8996_WRITE_SEQUENCER_245 0x30F5
473#define WM8996_WRITE_SEQUENCER_246 0x30F6
474#define WM8996_WRITE_SEQUENCER_247 0x30F7
475#define WM8996_WRITE_SEQUENCER_248 0x30F8
476#define WM8996_WRITE_SEQUENCER_249 0x30F9
477#define WM8996_WRITE_SEQUENCER_250 0x30FA
478#define WM8996_WRITE_SEQUENCER_251 0x30FB
479#define WM8996_WRITE_SEQUENCER_252 0x30FC
480#define WM8996_WRITE_SEQUENCER_253 0x30FD
481#define WM8996_WRITE_SEQUENCER_254 0x30FE
482#define WM8996_WRITE_SEQUENCER_255 0x30FF
483#define WM8996_WRITE_SEQUENCER_256 0x3100
484#define WM8996_WRITE_SEQUENCER_257 0x3101
485#define WM8996_WRITE_SEQUENCER_258 0x3102
486#define WM8996_WRITE_SEQUENCER_259 0x3103
487#define WM8996_WRITE_SEQUENCER_260 0x3104
488#define WM8996_WRITE_SEQUENCER_261 0x3105
489#define WM8996_WRITE_SEQUENCER_262 0x3106
490#define WM8996_WRITE_SEQUENCER_263 0x3107
491#define WM8996_WRITE_SEQUENCER_264 0x3108
492#define WM8996_WRITE_SEQUENCER_265 0x3109
493#define WM8996_WRITE_SEQUENCER_266 0x310A
494#define WM8996_WRITE_SEQUENCER_267 0x310B
495#define WM8996_WRITE_SEQUENCER_268 0x310C
496#define WM8996_WRITE_SEQUENCER_269 0x310D
497#define WM8996_WRITE_SEQUENCER_270 0x310E
498#define WM8996_WRITE_SEQUENCER_271 0x310F
499#define WM8996_WRITE_SEQUENCER_272 0x3110
500#define WM8996_WRITE_SEQUENCER_273 0x3111
501#define WM8996_WRITE_SEQUENCER_274 0x3112
502#define WM8996_WRITE_SEQUENCER_275 0x3113
503#define WM8996_WRITE_SEQUENCER_276 0x3114
504#define WM8996_WRITE_SEQUENCER_277 0x3115
505#define WM8996_WRITE_SEQUENCER_278 0x3116
506#define WM8996_WRITE_SEQUENCER_279 0x3117
507#define WM8996_WRITE_SEQUENCER_280 0x3118
508#define WM8996_WRITE_SEQUENCER_281 0x3119
509#define WM8996_WRITE_SEQUENCER_282 0x311A
510#define WM8996_WRITE_SEQUENCER_283 0x311B
511#define WM8996_WRITE_SEQUENCER_284 0x311C
512#define WM8996_WRITE_SEQUENCER_285 0x311D
513#define WM8996_WRITE_SEQUENCER_286 0x311E
514#define WM8996_WRITE_SEQUENCER_287 0x311F
515#define WM8996_WRITE_SEQUENCER_288 0x3120
516#define WM8996_WRITE_SEQUENCER_289 0x3121
517#define WM8996_WRITE_SEQUENCER_290 0x3122
518#define WM8996_WRITE_SEQUENCER_291 0x3123
519#define WM8996_WRITE_SEQUENCER_292 0x3124
520#define WM8996_WRITE_SEQUENCER_293 0x3125
521#define WM8996_WRITE_SEQUENCER_294 0x3126
522#define WM8996_WRITE_SEQUENCER_295 0x3127
523#define WM8996_WRITE_SEQUENCER_296 0x3128
524#define WM8996_WRITE_SEQUENCER_297 0x3129
525#define WM8996_WRITE_SEQUENCER_298 0x312A
526#define WM8996_WRITE_SEQUENCER_299 0x312B
527#define WM8996_WRITE_SEQUENCER_300 0x312C
528#define WM8996_WRITE_SEQUENCER_301 0x312D
529#define WM8996_WRITE_SEQUENCER_302 0x312E
530#define WM8996_WRITE_SEQUENCER_303 0x312F
531#define WM8996_WRITE_SEQUENCER_304 0x3130
532#define WM8996_WRITE_SEQUENCER_305 0x3131
533#define WM8996_WRITE_SEQUENCER_306 0x3132
534#define WM8996_WRITE_SEQUENCER_307 0x3133
535#define WM8996_WRITE_SEQUENCER_308 0x3134
536#define WM8996_WRITE_SEQUENCER_309 0x3135
537#define WM8996_WRITE_SEQUENCER_310 0x3136
538#define WM8996_WRITE_SEQUENCER_311 0x3137
539#define WM8996_WRITE_SEQUENCER_312 0x3138
540#define WM8996_WRITE_SEQUENCER_313 0x3139
541#define WM8996_WRITE_SEQUENCER_314 0x313A
542#define WM8996_WRITE_SEQUENCER_315 0x313B
543#define WM8996_WRITE_SEQUENCER_316 0x313C
544#define WM8996_WRITE_SEQUENCER_317 0x313D
545#define WM8996_WRITE_SEQUENCER_318 0x313E
546#define WM8996_WRITE_SEQUENCER_319 0x313F
547#define WM8996_WRITE_SEQUENCER_320 0x3140
548#define WM8996_WRITE_SEQUENCER_321 0x3141
549#define WM8996_WRITE_SEQUENCER_322 0x3142
550#define WM8996_WRITE_SEQUENCER_323 0x3143
551#define WM8996_WRITE_SEQUENCER_324 0x3144
552#define WM8996_WRITE_SEQUENCER_325 0x3145
553#define WM8996_WRITE_SEQUENCER_326 0x3146
554#define WM8996_WRITE_SEQUENCER_327 0x3147
555#define WM8996_WRITE_SEQUENCER_328 0x3148
556#define WM8996_WRITE_SEQUENCER_329 0x3149
557#define WM8996_WRITE_SEQUENCER_330 0x314A
558#define WM8996_WRITE_SEQUENCER_331 0x314B
559#define WM8996_WRITE_SEQUENCER_332 0x314C
560#define WM8996_WRITE_SEQUENCER_333 0x314D
561#define WM8996_WRITE_SEQUENCER_334 0x314E
562#define WM8996_WRITE_SEQUENCER_335 0x314F
563#define WM8996_WRITE_SEQUENCER_336 0x3150
564#define WM8996_WRITE_SEQUENCER_337 0x3151
565#define WM8996_WRITE_SEQUENCER_338 0x3152
566#define WM8996_WRITE_SEQUENCER_339 0x3153
567#define WM8996_WRITE_SEQUENCER_340 0x3154
568#define WM8996_WRITE_SEQUENCER_341 0x3155
569#define WM8996_WRITE_SEQUENCER_342 0x3156
570#define WM8996_WRITE_SEQUENCER_343 0x3157
571#define WM8996_WRITE_SEQUENCER_344 0x3158
572#define WM8996_WRITE_SEQUENCER_345 0x3159
573#define WM8996_WRITE_SEQUENCER_346 0x315A
574#define WM8996_WRITE_SEQUENCER_347 0x315B
575#define WM8996_WRITE_SEQUENCER_348 0x315C
576#define WM8996_WRITE_SEQUENCER_349 0x315D
577#define WM8996_WRITE_SEQUENCER_350 0x315E
578#define WM8996_WRITE_SEQUENCER_351 0x315F
579#define WM8996_WRITE_SEQUENCER_352 0x3160
580#define WM8996_WRITE_SEQUENCER_353 0x3161
581#define WM8996_WRITE_SEQUENCER_354 0x3162
582#define WM8996_WRITE_SEQUENCER_355 0x3163
583#define WM8996_WRITE_SEQUENCER_356 0x3164
584#define WM8996_WRITE_SEQUENCER_357 0x3165
585#define WM8996_WRITE_SEQUENCER_358 0x3166
586#define WM8996_WRITE_SEQUENCER_359 0x3167
587#define WM8996_WRITE_SEQUENCER_360 0x3168
588#define WM8996_WRITE_SEQUENCER_361 0x3169
589#define WM8996_WRITE_SEQUENCER_362 0x316A
590#define WM8996_WRITE_SEQUENCER_363 0x316B
591#define WM8996_WRITE_SEQUENCER_364 0x316C
592#define WM8996_WRITE_SEQUENCER_365 0x316D
593#define WM8996_WRITE_SEQUENCER_366 0x316E
594#define WM8996_WRITE_SEQUENCER_367 0x316F
595#define WM8996_WRITE_SEQUENCER_368 0x3170
596#define WM8996_WRITE_SEQUENCER_369 0x3171
597#define WM8996_WRITE_SEQUENCER_370 0x3172
598#define WM8996_WRITE_SEQUENCER_371 0x3173
599#define WM8996_WRITE_SEQUENCER_372 0x3174
600#define WM8996_WRITE_SEQUENCER_373 0x3175
601#define WM8996_WRITE_SEQUENCER_374 0x3176
602#define WM8996_WRITE_SEQUENCER_375 0x3177
603#define WM8996_WRITE_SEQUENCER_376 0x3178
604#define WM8996_WRITE_SEQUENCER_377 0x3179
605#define WM8996_WRITE_SEQUENCER_378 0x317A
606#define WM8996_WRITE_SEQUENCER_379 0x317B
607#define WM8996_WRITE_SEQUENCER_380 0x317C
608#define WM8996_WRITE_SEQUENCER_381 0x317D
609#define WM8996_WRITE_SEQUENCER_382 0x317E
610#define WM8996_WRITE_SEQUENCER_383 0x317F
611#define WM8996_WRITE_SEQUENCER_384 0x3180
612#define WM8996_WRITE_SEQUENCER_385 0x3181
613#define WM8996_WRITE_SEQUENCER_386 0x3182
614#define WM8996_WRITE_SEQUENCER_387 0x3183
615#define WM8996_WRITE_SEQUENCER_388 0x3184
616#define WM8996_WRITE_SEQUENCER_389 0x3185
617#define WM8996_WRITE_SEQUENCER_390 0x3186
618#define WM8996_WRITE_SEQUENCER_391 0x3187
619#define WM8996_WRITE_SEQUENCER_392 0x3188
620#define WM8996_WRITE_SEQUENCER_393 0x3189
621#define WM8996_WRITE_SEQUENCER_394 0x318A
622#define WM8996_WRITE_SEQUENCER_395 0x318B
623#define WM8996_WRITE_SEQUENCER_396 0x318C
624#define WM8996_WRITE_SEQUENCER_397 0x318D
625#define WM8996_WRITE_SEQUENCER_398 0x318E
626#define WM8996_WRITE_SEQUENCER_399 0x318F
627#define WM8996_WRITE_SEQUENCER_400 0x3190
628#define WM8996_WRITE_SEQUENCER_401 0x3191
629#define WM8996_WRITE_SEQUENCER_402 0x3192
630#define WM8996_WRITE_SEQUENCER_403 0x3193
631#define WM8996_WRITE_SEQUENCER_404 0x3194
632#define WM8996_WRITE_SEQUENCER_405 0x3195
633#define WM8996_WRITE_SEQUENCER_406 0x3196
634#define WM8996_WRITE_SEQUENCER_407 0x3197
635#define WM8996_WRITE_SEQUENCER_408 0x3198
636#define WM8996_WRITE_SEQUENCER_409 0x3199
637#define WM8996_WRITE_SEQUENCER_410 0x319A
638#define WM8996_WRITE_SEQUENCER_411 0x319B
639#define WM8996_WRITE_SEQUENCER_412 0x319C
640#define WM8996_WRITE_SEQUENCER_413 0x319D
641#define WM8996_WRITE_SEQUENCER_414 0x319E
642#define WM8996_WRITE_SEQUENCER_415 0x319F
643#define WM8996_WRITE_SEQUENCER_416 0x31A0
644#define WM8996_WRITE_SEQUENCER_417 0x31A1
645#define WM8996_WRITE_SEQUENCER_418 0x31A2
646#define WM8996_WRITE_SEQUENCER_419 0x31A3
647#define WM8996_WRITE_SEQUENCER_420 0x31A4
648#define WM8996_WRITE_SEQUENCER_421 0x31A5
649#define WM8996_WRITE_SEQUENCER_422 0x31A6
650#define WM8996_WRITE_SEQUENCER_423 0x31A7
651#define WM8996_WRITE_SEQUENCER_424 0x31A8
652#define WM8996_WRITE_SEQUENCER_425 0x31A9
653#define WM8996_WRITE_SEQUENCER_426 0x31AA
654#define WM8996_WRITE_SEQUENCER_427 0x31AB
655#define WM8996_WRITE_SEQUENCER_428 0x31AC
656#define WM8996_WRITE_SEQUENCER_429 0x31AD
657#define WM8996_WRITE_SEQUENCER_430 0x31AE
658#define WM8996_WRITE_SEQUENCER_431 0x31AF
659#define WM8996_WRITE_SEQUENCER_432 0x31B0
660#define WM8996_WRITE_SEQUENCER_433 0x31B1
661#define WM8996_WRITE_SEQUENCER_434 0x31B2
662#define WM8996_WRITE_SEQUENCER_435 0x31B3
663#define WM8996_WRITE_SEQUENCER_436 0x31B4
664#define WM8996_WRITE_SEQUENCER_437 0x31B5
665#define WM8996_WRITE_SEQUENCER_438 0x31B6
666#define WM8996_WRITE_SEQUENCER_439 0x31B7
667#define WM8996_WRITE_SEQUENCER_440 0x31B8
668#define WM8996_WRITE_SEQUENCER_441 0x31B9
669#define WM8996_WRITE_SEQUENCER_442 0x31BA
670#define WM8996_WRITE_SEQUENCER_443 0x31BB
671#define WM8996_WRITE_SEQUENCER_444 0x31BC
672#define WM8996_WRITE_SEQUENCER_445 0x31BD
673#define WM8996_WRITE_SEQUENCER_446 0x31BE
674#define WM8996_WRITE_SEQUENCER_447 0x31BF
675#define WM8996_WRITE_SEQUENCER_448 0x31C0
676#define WM8996_WRITE_SEQUENCER_449 0x31C1
677#define WM8996_WRITE_SEQUENCER_450 0x31C2
678#define WM8996_WRITE_SEQUENCER_451 0x31C3
679#define WM8996_WRITE_SEQUENCER_452 0x31C4
680#define WM8996_WRITE_SEQUENCER_453 0x31C5
681#define WM8996_WRITE_SEQUENCER_454 0x31C6
682#define WM8996_WRITE_SEQUENCER_455 0x31C7
683#define WM8996_WRITE_SEQUENCER_456 0x31C8
684#define WM8996_WRITE_SEQUENCER_457 0x31C9
685#define WM8996_WRITE_SEQUENCER_458 0x31CA
686#define WM8996_WRITE_SEQUENCER_459 0x31CB
687#define WM8996_WRITE_SEQUENCER_460 0x31CC
688#define WM8996_WRITE_SEQUENCER_461 0x31CD
689#define WM8996_WRITE_SEQUENCER_462 0x31CE
690#define WM8996_WRITE_SEQUENCER_463 0x31CF
691#define WM8996_WRITE_SEQUENCER_464 0x31D0
692#define WM8996_WRITE_SEQUENCER_465 0x31D1
693#define WM8996_WRITE_SEQUENCER_466 0x31D2
694#define WM8996_WRITE_SEQUENCER_467 0x31D3
695#define WM8996_WRITE_SEQUENCER_468 0x31D4
696#define WM8996_WRITE_SEQUENCER_469 0x31D5
697#define WM8996_WRITE_SEQUENCER_470 0x31D6
698#define WM8996_WRITE_SEQUENCER_471 0x31D7
699#define WM8996_WRITE_SEQUENCER_472 0x31D8
700#define WM8996_WRITE_SEQUENCER_473 0x31D9
701#define WM8996_WRITE_SEQUENCER_474 0x31DA
702#define WM8996_WRITE_SEQUENCER_475 0x31DB
703#define WM8996_WRITE_SEQUENCER_476 0x31DC
704#define WM8996_WRITE_SEQUENCER_477 0x31DD
705#define WM8996_WRITE_SEQUENCER_478 0x31DE
706#define WM8996_WRITE_SEQUENCER_479 0x31DF
707#define WM8996_WRITE_SEQUENCER_480 0x31E0
708#define WM8996_WRITE_SEQUENCER_481 0x31E1
709#define WM8996_WRITE_SEQUENCER_482 0x31E2
710#define WM8996_WRITE_SEQUENCER_483 0x31E3
711#define WM8996_WRITE_SEQUENCER_484 0x31E4
712#define WM8996_WRITE_SEQUENCER_485 0x31E5
713#define WM8996_WRITE_SEQUENCER_486 0x31E6
714#define WM8996_WRITE_SEQUENCER_487 0x31E7
715#define WM8996_WRITE_SEQUENCER_488 0x31E8
716#define WM8996_WRITE_SEQUENCER_489 0x31E9
717#define WM8996_WRITE_SEQUENCER_490 0x31EA
718#define WM8996_WRITE_SEQUENCER_491 0x31EB
719#define WM8996_WRITE_SEQUENCER_492 0x31EC
720#define WM8996_WRITE_SEQUENCER_493 0x31ED
721#define WM8996_WRITE_SEQUENCER_494 0x31EE
722#define WM8996_WRITE_SEQUENCER_495 0x31EF
723#define WM8996_WRITE_SEQUENCER_496 0x31F0
724#define WM8996_WRITE_SEQUENCER_497 0x31F1
725#define WM8996_WRITE_SEQUENCER_498 0x31F2
726#define WM8996_WRITE_SEQUENCER_499 0x31F3
727#define WM8996_WRITE_SEQUENCER_500 0x31F4
728#define WM8996_WRITE_SEQUENCER_501 0x31F5
729#define WM8996_WRITE_SEQUENCER_502 0x31F6
730#define WM8996_WRITE_SEQUENCER_503 0x31F7
731#define WM8996_WRITE_SEQUENCER_504 0x31F8
732#define WM8996_WRITE_SEQUENCER_505 0x31F9
733#define WM8996_WRITE_SEQUENCER_506 0x31FA
734#define WM8996_WRITE_SEQUENCER_507 0x31FB
735#define WM8996_WRITE_SEQUENCER_508 0x31FC
736#define WM8996_WRITE_SEQUENCER_509 0x31FD
737#define WM8996_WRITE_SEQUENCER_510 0x31FE
738#define WM8996_WRITE_SEQUENCER_511 0x31FF
739
740#define WM8996_REGISTER_COUNT 706
741#define WM8996_MAX_REGISTER 0x31FF
742
743/*
744 * Field Definitions.
745 */
746
747/*
748 * R0 (0x00) - Software Reset
749 */
750#define WM8996_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */
751#define WM8996_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */
752#define WM8996_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */
753
754/*
755 * R1 (0x01) - Power Management (1)
756 */
757#define WM8996_MICB2_ENA 0x0200 /* MICB2_ENA */
758#define WM8996_MICB2_ENA_MASK 0x0200 /* MICB2_ENA */
759#define WM8996_MICB2_ENA_SHIFT 9 /* MICB2_ENA */
760#define WM8996_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
761#define WM8996_MICB1_ENA 0x0100 /* MICB1_ENA */
762#define WM8996_MICB1_ENA_MASK 0x0100 /* MICB1_ENA */
763#define WM8996_MICB1_ENA_SHIFT 8 /* MICB1_ENA */
764#define WM8996_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
765#define WM8996_HPOUT2L_ENA 0x0080 /* HPOUT2L_ENA */
766#define WM8996_HPOUT2L_ENA_MASK 0x0080 /* HPOUT2L_ENA */
767#define WM8996_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */
768#define WM8996_HPOUT2L_ENA_WIDTH 1 /* HPOUT2L_ENA */
769#define WM8996_HPOUT2R_ENA 0x0040 /* HPOUT2R_ENA */
770#define WM8996_HPOUT2R_ENA_MASK 0x0040 /* HPOUT2R_ENA */
771#define WM8996_HPOUT2R_ENA_SHIFT 6 /* HPOUT2R_ENA */
772#define WM8996_HPOUT2R_ENA_WIDTH 1 /* HPOUT2R_ENA */
773#define WM8996_HPOUT1L_ENA 0x0020 /* HPOUT1L_ENA */
774#define WM8996_HPOUT1L_ENA_MASK 0x0020 /* HPOUT1L_ENA */
775#define WM8996_HPOUT1L_ENA_SHIFT 5 /* HPOUT1L_ENA */
776#define WM8996_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */
777#define WM8996_HPOUT1R_ENA 0x0010 /* HPOUT1R_ENA */
778#define WM8996_HPOUT1R_ENA_MASK 0x0010 /* HPOUT1R_ENA */
779#define WM8996_HPOUT1R_ENA_SHIFT 4 /* HPOUT1R_ENA */
780#define WM8996_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */
781#define WM8996_BG_ENA 0x0001 /* BG_ENA */
782#define WM8996_BG_ENA_MASK 0x0001 /* BG_ENA */
783#define WM8996_BG_ENA_SHIFT 0 /* BG_ENA */
784#define WM8996_BG_ENA_WIDTH 1 /* BG_ENA */
785
786/*
787 * R2 (0x02) - Power Management (2)
788 */
789#define WM8996_OPCLK_ENA 0x0800 /* OPCLK_ENA */
790#define WM8996_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */
791#define WM8996_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */
792#define WM8996_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
793#define WM8996_INL_ENA 0x0020 /* INL_ENA */
794#define WM8996_INL_ENA_MASK 0x0020 /* INL_ENA */
795#define WM8996_INL_ENA_SHIFT 5 /* INL_ENA */
796#define WM8996_INL_ENA_WIDTH 1 /* INL_ENA */
797#define WM8996_INR_ENA 0x0010 /* INR_ENA */
798#define WM8996_INR_ENA_MASK 0x0010 /* INR_ENA */
799#define WM8996_INR_ENA_SHIFT 4 /* INR_ENA */
800#define WM8996_INR_ENA_WIDTH 1 /* INR_ENA */
801#define WM8996_LDO2_ENA 0x0002 /* LDO2_ENA */
802#define WM8996_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */
803#define WM8996_LDO2_ENA_SHIFT 1 /* LDO2_ENA */
804#define WM8996_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
805
806/*
807 * R3 (0x03) - Power Management (3)
808 */
809#define WM8996_DSP2RXL_ENA 0x0800 /* DSP2RXL_ENA */
810#define WM8996_DSP2RXL_ENA_MASK 0x0800 /* DSP2RXL_ENA */
811#define WM8996_DSP2RXL_ENA_SHIFT 11 /* DSP2RXL_ENA */
812#define WM8996_DSP2RXL_ENA_WIDTH 1 /* DSP2RXL_ENA */
813#define WM8996_DSP2RXR_ENA 0x0400 /* DSP2RXR_ENA */
814#define WM8996_DSP2RXR_ENA_MASK 0x0400 /* DSP2RXR_ENA */
815#define WM8996_DSP2RXR_ENA_SHIFT 10 /* DSP2RXR_ENA */
816#define WM8996_DSP2RXR_ENA_WIDTH 1 /* DSP2RXR_ENA */
817#define WM8996_DSP1RXL_ENA 0x0200 /* DSP1RXL_ENA */
818#define WM8996_DSP1RXL_ENA_MASK 0x0200 /* DSP1RXL_ENA */
819#define WM8996_DSP1RXL_ENA_SHIFT 9 /* DSP1RXL_ENA */
820#define WM8996_DSP1RXL_ENA_WIDTH 1 /* DSP1RXL_ENA */
821#define WM8996_DSP1RXR_ENA 0x0100 /* DSP1RXR_ENA */
822#define WM8996_DSP1RXR_ENA_MASK 0x0100 /* DSP1RXR_ENA */
823#define WM8996_DSP1RXR_ENA_SHIFT 8 /* DSP1RXR_ENA */
824#define WM8996_DSP1RXR_ENA_WIDTH 1 /* DSP1RXR_ENA */
825#define WM8996_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */
826#define WM8996_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */
827#define WM8996_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */
828#define WM8996_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */
829#define WM8996_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */
830#define WM8996_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */
831#define WM8996_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */
832#define WM8996_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */
833#define WM8996_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */
834#define WM8996_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */
835#define WM8996_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */
836#define WM8996_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */
837#define WM8996_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */
838#define WM8996_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */
839#define WM8996_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */
840#define WM8996_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */
841#define WM8996_ADCL_ENA 0x0002 /* ADCL_ENA */
842#define WM8996_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */
843#define WM8996_ADCL_ENA_SHIFT 1 /* ADCL_ENA */
844#define WM8996_ADCL_ENA_WIDTH 1 /* ADCL_ENA */
845#define WM8996_ADCR_ENA 0x0001 /* ADCR_ENA */
846#define WM8996_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */
847#define WM8996_ADCR_ENA_SHIFT 0 /* ADCR_ENA */
848#define WM8996_ADCR_ENA_WIDTH 1 /* ADCR_ENA */
849
850/*
851 * R4 (0x04) - Power Management (4)
852 */
853#define WM8996_AIF2RX_CHAN1_ENA 0x0200 /* AIF2RX_CHAN1_ENA */
854#define WM8996_AIF2RX_CHAN1_ENA_MASK 0x0200 /* AIF2RX_CHAN1_ENA */
855#define WM8996_AIF2RX_CHAN1_ENA_SHIFT 9 /* AIF2RX_CHAN1_ENA */
856#define WM8996_AIF2RX_CHAN1_ENA_WIDTH 1 /* AIF2RX_CHAN1_ENA */
857#define WM8996_AIF2RX_CHAN0_ENA 0x0100 /* AIF2RX_CHAN0_ENA */
858#define WM8996_AIF2RX_CHAN0_ENA_MASK 0x0100 /* AIF2RX_CHAN0_ENA */
859#define WM8996_AIF2RX_CHAN0_ENA_SHIFT 8 /* AIF2RX_CHAN0_ENA */
860#define WM8996_AIF2RX_CHAN0_ENA_WIDTH 1 /* AIF2RX_CHAN0_ENA */
861#define WM8996_AIF1RX_CHAN5_ENA 0x0020 /* AIF1RX_CHAN5_ENA */
862#define WM8996_AIF1RX_CHAN5_ENA_MASK 0x0020 /* AIF1RX_CHAN5_ENA */
863#define WM8996_AIF1RX_CHAN5_ENA_SHIFT 5 /* AIF1RX_CHAN5_ENA */
864#define WM8996_AIF1RX_CHAN5_ENA_WIDTH 1 /* AIF1RX_CHAN5_ENA */
865#define WM8996_AIF1RX_CHAN4_ENA 0x0010 /* AIF1RX_CHAN4_ENA */
866#define WM8996_AIF1RX_CHAN4_ENA_MASK 0x0010 /* AIF1RX_CHAN4_ENA */
867#define WM8996_AIF1RX_CHAN4_ENA_SHIFT 4 /* AIF1RX_CHAN4_ENA */
868#define WM8996_AIF1RX_CHAN4_ENA_WIDTH 1 /* AIF1RX_CHAN4_ENA */
869#define WM8996_AIF1RX_CHAN3_ENA 0x0008 /* AIF1RX_CHAN3_ENA */
870#define WM8996_AIF1RX_CHAN3_ENA_MASK 0x0008 /* AIF1RX_CHAN3_ENA */
871#define WM8996_AIF1RX_CHAN3_ENA_SHIFT 3 /* AIF1RX_CHAN3_ENA */
872#define WM8996_AIF1RX_CHAN3_ENA_WIDTH 1 /* AIF1RX_CHAN3_ENA */
873#define WM8996_AIF1RX_CHAN2_ENA 0x0004 /* AIF1RX_CHAN2_ENA */
874#define WM8996_AIF1RX_CHAN2_ENA_MASK 0x0004 /* AIF1RX_CHAN2_ENA */
875#define WM8996_AIF1RX_CHAN2_ENA_SHIFT 2 /* AIF1RX_CHAN2_ENA */
876#define WM8996_AIF1RX_CHAN2_ENA_WIDTH 1 /* AIF1RX_CHAN2_ENA */
877#define WM8996_AIF1RX_CHAN1_ENA 0x0002 /* AIF1RX_CHAN1_ENA */
878#define WM8996_AIF1RX_CHAN1_ENA_MASK 0x0002 /* AIF1RX_CHAN1_ENA */
879#define WM8996_AIF1RX_CHAN1_ENA_SHIFT 1 /* AIF1RX_CHAN1_ENA */
880#define WM8996_AIF1RX_CHAN1_ENA_WIDTH 1 /* AIF1RX_CHAN1_ENA */
881#define WM8996_AIF1RX_CHAN0_ENA 0x0001 /* AIF1RX_CHAN0_ENA */
882#define WM8996_AIF1RX_CHAN0_ENA_MASK 0x0001 /* AIF1RX_CHAN0_ENA */
883#define WM8996_AIF1RX_CHAN0_ENA_SHIFT 0 /* AIF1RX_CHAN0_ENA */
884#define WM8996_AIF1RX_CHAN0_ENA_WIDTH 1 /* AIF1RX_CHAN0_ENA */
885
886/*
887 * R5 (0x05) - Power Management (5)
888 */
889#define WM8996_DSP2TXL_ENA 0x0800 /* DSP2TXL_ENA */
890#define WM8996_DSP2TXL_ENA_MASK 0x0800 /* DSP2TXL_ENA */
891#define WM8996_DSP2TXL_ENA_SHIFT 11 /* DSP2TXL_ENA */
892#define WM8996_DSP2TXL_ENA_WIDTH 1 /* DSP2TXL_ENA */
893#define WM8996_DSP2TXR_ENA 0x0400 /* DSP2TXR_ENA */
894#define WM8996_DSP2TXR_ENA_MASK 0x0400 /* DSP2TXR_ENA */
895#define WM8996_DSP2TXR_ENA_SHIFT 10 /* DSP2TXR_ENA */
896#define WM8996_DSP2TXR_ENA_WIDTH 1 /* DSP2TXR_ENA */
897#define WM8996_DSP1TXL_ENA 0x0200 /* DSP1TXL_ENA */
898#define WM8996_DSP1TXL_ENA_MASK 0x0200 /* DSP1TXL_ENA */
899#define WM8996_DSP1TXL_ENA_SHIFT 9 /* DSP1TXL_ENA */
900#define WM8996_DSP1TXL_ENA_WIDTH 1 /* DSP1TXL_ENA */
901#define WM8996_DSP1TXR_ENA 0x0100 /* DSP1TXR_ENA */
902#define WM8996_DSP1TXR_ENA_MASK 0x0100 /* DSP1TXR_ENA */
903#define WM8996_DSP1TXR_ENA_SHIFT 8 /* DSP1TXR_ENA */
904#define WM8996_DSP1TXR_ENA_WIDTH 1 /* DSP1TXR_ENA */
905#define WM8996_DAC2L_ENA 0x0008 /* DAC2L_ENA */
906#define WM8996_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */
907#define WM8996_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */
908#define WM8996_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */
909#define WM8996_DAC2R_ENA 0x0004 /* DAC2R_ENA */
910#define WM8996_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */
911#define WM8996_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */
912#define WM8996_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */
913#define WM8996_DAC1L_ENA 0x0002 /* DAC1L_ENA */
914#define WM8996_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */
915#define WM8996_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */
916#define WM8996_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */
917#define WM8996_DAC1R_ENA 0x0001 /* DAC1R_ENA */
918#define WM8996_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */
919#define WM8996_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */
920#define WM8996_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */
921
922/*
923 * R6 (0x06) - Power Management (6)
924 */
925#define WM8996_AIF2TX_CHAN1_ENA 0x0200 /* AIF2TX_CHAN1_ENA */
926#define WM8996_AIF2TX_CHAN1_ENA_MASK 0x0200 /* AIF2TX_CHAN1_ENA */
927#define WM8996_AIF2TX_CHAN1_ENA_SHIFT 9 /* AIF2TX_CHAN1_ENA */
928#define WM8996_AIF2TX_CHAN1_ENA_WIDTH 1 /* AIF2TX_CHAN1_ENA */
929#define WM8996_AIF2TX_CHAN0_ENA 0x0100 /* AIF2TX_CHAN0_ENA */
930#define WM8996_AIF2TX_CHAN0_ENA_MASK 0x0100 /* AIF2TX_CHAN0_ENA */
931#define WM8996_AIF2TX_CHAN0_ENA_SHIFT 8 /* AIF2TX_CHAN0_ENA */
932#define WM8996_AIF2TX_CHAN0_ENA_WIDTH 1 /* AIF2TX_CHAN0_ENA */
933#define WM8996_AIF1TX_CHAN5_ENA 0x0020 /* AIF1TX_CHAN5_ENA */
934#define WM8996_AIF1TX_CHAN5_ENA_MASK 0x0020 /* AIF1TX_CHAN5_ENA */
935#define WM8996_AIF1TX_CHAN5_ENA_SHIFT 5 /* AIF1TX_CHAN5_ENA */
936#define WM8996_AIF1TX_CHAN5_ENA_WIDTH 1 /* AIF1TX_CHAN5_ENA */
937#define WM8996_AIF1TX_CHAN4_ENA 0x0010 /* AIF1TX_CHAN4_ENA */
938#define WM8996_AIF1TX_CHAN4_ENA_MASK 0x0010 /* AIF1TX_CHAN4_ENA */
939#define WM8996_AIF1TX_CHAN4_ENA_SHIFT 4 /* AIF1TX_CHAN4_ENA */
940#define WM8996_AIF1TX_CHAN4_ENA_WIDTH 1 /* AIF1TX_CHAN4_ENA */
941#define WM8996_AIF1TX_CHAN3_ENA 0x0008 /* AIF1TX_CHAN3_ENA */
942#define WM8996_AIF1TX_CHAN3_ENA_MASK 0x0008 /* AIF1TX_CHAN3_ENA */
943#define WM8996_AIF1TX_CHAN3_ENA_SHIFT 3 /* AIF1TX_CHAN3_ENA */
944#define WM8996_AIF1TX_CHAN3_ENA_WIDTH 1 /* AIF1TX_CHAN3_ENA */
945#define WM8996_AIF1TX_CHAN2_ENA 0x0004 /* AIF1TX_CHAN2_ENA */
946#define WM8996_AIF1TX_CHAN2_ENA_MASK 0x0004 /* AIF1TX_CHAN2_ENA */
947#define WM8996_AIF1TX_CHAN2_ENA_SHIFT 2 /* AIF1TX_CHAN2_ENA */
948#define WM8996_AIF1TX_CHAN2_ENA_WIDTH 1 /* AIF1TX_CHAN2_ENA */
949#define WM8996_AIF1TX_CHAN1_ENA 0x0002 /* AIF1TX_CHAN1_ENA */
950#define WM8996_AIF1TX_CHAN1_ENA_MASK 0x0002 /* AIF1TX_CHAN1_ENA */
951#define WM8996_AIF1TX_CHAN1_ENA_SHIFT 1 /* AIF1TX_CHAN1_ENA */
952#define WM8996_AIF1TX_CHAN1_ENA_WIDTH 1 /* AIF1TX_CHAN1_ENA */
953#define WM8996_AIF1TX_CHAN0_ENA 0x0001 /* AIF1TX_CHAN0_ENA */
954#define WM8996_AIF1TX_CHAN0_ENA_MASK 0x0001 /* AIF1TX_CHAN0_ENA */
955#define WM8996_AIF1TX_CHAN0_ENA_SHIFT 0 /* AIF1TX_CHAN0_ENA */
956#define WM8996_AIF1TX_CHAN0_ENA_WIDTH 1 /* AIF1TX_CHAN0_ENA */
957
958/*
959 * R7 (0x07) - Power Management (7)
960 */
961#define WM8996_DMIC2_FN 0x0200 /* DMIC2_FN */
962#define WM8996_DMIC2_FN_MASK 0x0200 /* DMIC2_FN */
963#define WM8996_DMIC2_FN_SHIFT 9 /* DMIC2_FN */
964#define WM8996_DMIC2_FN_WIDTH 1 /* DMIC2_FN */
965#define WM8996_DMIC1_FN 0x0100 /* DMIC1_FN */
966#define WM8996_DMIC1_FN_MASK 0x0100 /* DMIC1_FN */
967#define WM8996_DMIC1_FN_SHIFT 8 /* DMIC1_FN */
968#define WM8996_DMIC1_FN_WIDTH 1 /* DMIC1_FN */
969#define WM8996_ADC_DMIC_DSP2R_ENA 0x0080 /* ADC_DMIC_DSP2R_ENA */
970#define WM8996_ADC_DMIC_DSP2R_ENA_MASK 0x0080 /* ADC_DMIC_DSP2R_ENA */
971#define WM8996_ADC_DMIC_DSP2R_ENA_SHIFT 7 /* ADC_DMIC_DSP2R_ENA */
972#define WM8996_ADC_DMIC_DSP2R_ENA_WIDTH 1 /* ADC_DMIC_DSP2R_ENA */
973#define WM8996_ADC_DMIC_DSP2L_ENA 0x0040 /* ADC_DMIC_DSP2L_ENA */
974#define WM8996_ADC_DMIC_DSP2L_ENA_MASK 0x0040 /* ADC_DMIC_DSP2L_ENA */
975#define WM8996_ADC_DMIC_DSP2L_ENA_SHIFT 6 /* ADC_DMIC_DSP2L_ENA */
976#define WM8996_ADC_DMIC_DSP2L_ENA_WIDTH 1 /* ADC_DMIC_DSP2L_ENA */
977#define WM8996_ADC_DMIC_SRC2_MASK 0x0030 /* ADC_DMIC_SRC2 - [5:4] */
978#define WM8996_ADC_DMIC_SRC2_SHIFT 4 /* ADC_DMIC_SRC2 - [5:4] */
979#define WM8996_ADC_DMIC_SRC2_WIDTH 2 /* ADC_DMIC_SRC2 - [5:4] */
980#define WM8996_ADC_DMIC_DSP1R_ENA 0x0008 /* ADC_DMIC_DSP1R_ENA */
981#define WM8996_ADC_DMIC_DSP1R_ENA_MASK 0x0008 /* ADC_DMIC_DSP1R_ENA */
982#define WM8996_ADC_DMIC_DSP1R_ENA_SHIFT 3 /* ADC_DMIC_DSP1R_ENA */
983#define WM8996_ADC_DMIC_DSP1R_ENA_WIDTH 1 /* ADC_DMIC_DSP1R_ENA */
984#define WM8996_ADC_DMIC_DSP1L_ENA 0x0004 /* ADC_DMIC_DSP1L_ENA */
985#define WM8996_ADC_DMIC_DSP1L_ENA_MASK 0x0004 /* ADC_DMIC_DSP1L_ENA */
986#define WM8996_ADC_DMIC_DSP1L_ENA_SHIFT 2 /* ADC_DMIC_DSP1L_ENA */
987#define WM8996_ADC_DMIC_DSP1L_ENA_WIDTH 1 /* ADC_DMIC_DSP1L_ENA */
988#define WM8996_ADC_DMIC_SRC1_MASK 0x0003 /* ADC_DMIC_SRC1 - [1:0] */
989#define WM8996_ADC_DMIC_SRC1_SHIFT 0 /* ADC_DMIC_SRC1 - [1:0] */
990#define WM8996_ADC_DMIC_SRC1_WIDTH 2 /* ADC_DMIC_SRC1 - [1:0] */
991
992/*
993 * R8 (0x08) - Power Management (8)
994 */
995#define WM8996_AIF2TX_SRC_MASK 0x00C0 /* AIF2TX_SRC - [7:6] */
996#define WM8996_AIF2TX_SRC_SHIFT 6 /* AIF2TX_SRC - [7:6] */
997#define WM8996_AIF2TX_SRC_WIDTH 2 /* AIF2TX_SRC - [7:6] */
998#define WM8996_DSP2RX_SRC 0x0010 /* DSP2RX_SRC */
999#define WM8996_DSP2RX_SRC_MASK 0x0010 /* DSP2RX_SRC */
1000#define WM8996_DSP2RX_SRC_SHIFT 4 /* DSP2RX_SRC */
1001#define WM8996_DSP2RX_SRC_WIDTH 1 /* DSP2RX_SRC */
1002#define WM8996_DSP1RX_SRC 0x0001 /* DSP1RX_SRC */
1003#define WM8996_DSP1RX_SRC_MASK 0x0001 /* DSP1RX_SRC */
1004#define WM8996_DSP1RX_SRC_SHIFT 0 /* DSP1RX_SRC */
1005#define WM8996_DSP1RX_SRC_WIDTH 1 /* DSP1RX_SRC */
1006
1007/*
1008 * R16 (0x10) - Left Line Input Volume
1009 */
1010#define WM8996_IN1_VU 0x0080 /* IN1_VU */
1011#define WM8996_IN1_VU_MASK 0x0080 /* IN1_VU */
1012#define WM8996_IN1_VU_SHIFT 7 /* IN1_VU */
1013#define WM8996_IN1_VU_WIDTH 1 /* IN1_VU */
1014#define WM8996_IN1L_ZC 0x0020 /* IN1L_ZC */
1015#define WM8996_IN1L_ZC_MASK 0x0020 /* IN1L_ZC */
1016#define WM8996_IN1L_ZC_SHIFT 5 /* IN1L_ZC */
1017#define WM8996_IN1L_ZC_WIDTH 1 /* IN1L_ZC */
1018#define WM8996_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */
1019#define WM8996_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */
1020#define WM8996_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */
1021
1022/*
1023 * R17 (0x11) - Right Line Input Volume
1024 */
1025#define WM8996_IN1_VU 0x0080 /* IN1_VU */
1026#define WM8996_IN1_VU_MASK 0x0080 /* IN1_VU */
1027#define WM8996_IN1_VU_SHIFT 7 /* IN1_VU */
1028#define WM8996_IN1_VU_WIDTH 1 /* IN1_VU */
1029#define WM8996_IN1R_ZC 0x0020 /* IN1R_ZC */
1030#define WM8996_IN1R_ZC_MASK 0x0020 /* IN1R_ZC */
1031#define WM8996_IN1R_ZC_SHIFT 5 /* IN1R_ZC */
1032#define WM8996_IN1R_ZC_WIDTH 1 /* IN1R_ZC */
1033#define WM8996_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */
1034#define WM8996_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */
1035#define WM8996_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */
1036
1037/*
1038 * R18 (0x12) - Line Input Control
1039 */
1040#define WM8996_INL_MODE_MASK 0x000C /* INL_MODE - [3:2] */
1041#define WM8996_INL_MODE_SHIFT 2 /* INL_MODE - [3:2] */
1042#define WM8996_INL_MODE_WIDTH 2 /* INL_MODE - [3:2] */
1043#define WM8996_INR_MODE_MASK 0x0003 /* INR_MODE - [1:0] */
1044#define WM8996_INR_MODE_SHIFT 0 /* INR_MODE - [1:0] */
1045#define WM8996_INR_MODE_WIDTH 2 /* INR_MODE - [1:0] */
1046
1047/*
1048 * R21 (0x15) - DAC1 HPOUT1 Volume
1049 */
1050#define WM8996_DAC1R_HPOUT1R_VOL_MASK 0x00F0 /* DAC1R_HPOUT1R_VOL - [7:4] */
1051#define WM8996_DAC1R_HPOUT1R_VOL_SHIFT 4 /* DAC1R_HPOUT1R_VOL - [7:4] */
1052#define WM8996_DAC1R_HPOUT1R_VOL_WIDTH 4 /* DAC1R_HPOUT1R_VOL - [7:4] */
1053#define WM8996_DAC1L_HPOUT1L_VOL_MASK 0x000F /* DAC1L_HPOUT1L_VOL - [3:0] */
1054#define WM8996_DAC1L_HPOUT1L_VOL_SHIFT 0 /* DAC1L_HPOUT1L_VOL - [3:0] */
1055#define WM8996_DAC1L_HPOUT1L_VOL_WIDTH 4 /* DAC1L_HPOUT1L_VOL - [3:0] */
1056
1057/*
1058 * R22 (0x16) - DAC2 HPOUT2 Volume
1059 */
1060#define WM8996_DAC2R_HPOUT2R_VOL_MASK 0x00F0 /* DAC2R_HPOUT2R_VOL - [7:4] */
1061#define WM8996_DAC2R_HPOUT2R_VOL_SHIFT 4 /* DAC2R_HPOUT2R_VOL - [7:4] */
1062#define WM8996_DAC2R_HPOUT2R_VOL_WIDTH 4 /* DAC2R_HPOUT2R_VOL - [7:4] */
1063#define WM8996_DAC2L_HPOUT2L_VOL_MASK 0x000F /* DAC2L_HPOUT2L_VOL - [3:0] */
1064#define WM8996_DAC2L_HPOUT2L_VOL_SHIFT 0 /* DAC2L_HPOUT2L_VOL - [3:0] */
1065#define WM8996_DAC2L_HPOUT2L_VOL_WIDTH 4 /* DAC2L_HPOUT2L_VOL - [3:0] */
1066
1067/*
1068 * R24 (0x18) - DAC1 Left Volume
1069 */
1070#define WM8996_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */
1071#define WM8996_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */
1072#define WM8996_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */
1073#define WM8996_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */
1074#define WM8996_DAC1_VU 0x0100 /* DAC1_VU */
1075#define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */
1076#define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */
1077#define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */
1078#define WM8996_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */
1079#define WM8996_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */
1080#define WM8996_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */
1081
1082/*
1083 * R25 (0x19) - DAC1 Right Volume
1084 */
1085#define WM8996_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */
1086#define WM8996_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */
1087#define WM8996_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */
1088#define WM8996_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */
1089#define WM8996_DAC1_VU 0x0100 /* DAC1_VU */
1090#define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */
1091#define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */
1092#define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */
1093#define WM8996_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */
1094#define WM8996_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */
1095#define WM8996_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */
1096
1097/*
1098 * R26 (0x1A) - DAC2 Left Volume
1099 */
1100#define WM8996_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */
1101#define WM8996_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */
1102#define WM8996_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */
1103#define WM8996_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */
1104#define WM8996_DAC2_VU 0x0100 /* DAC2_VU */
1105#define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */
1106#define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */
1107#define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */
1108#define WM8996_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */
1109#define WM8996_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */
1110#define WM8996_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */
1111
1112/*
1113 * R27 (0x1B) - DAC2 Right Volume
1114 */
1115#define WM8996_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */
1116#define WM8996_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */
1117#define WM8996_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */
1118#define WM8996_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */
1119#define WM8996_DAC2_VU 0x0100 /* DAC2_VU */
1120#define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */
1121#define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */
1122#define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */
1123#define WM8996_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */
1124#define WM8996_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */
1125#define WM8996_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */
1126
1127/*
1128 * R28 (0x1C) - Output1 Left Volume
1129 */
1130#define WM8996_DAC1_VU 0x0100 /* DAC1_VU */
1131#define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */
1132#define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */
1133#define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */
1134#define WM8996_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */
1135#define WM8996_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */
1136#define WM8996_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */
1137#define WM8996_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */
1138#define WM8996_HPOUT1L_VOL_MASK 0x000F /* HPOUT1L_VOL - [3:0] */
1139#define WM8996_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [3:0] */
1140#define WM8996_HPOUT1L_VOL_WIDTH 4 /* HPOUT1L_VOL - [3:0] */
1141
1142/*
1143 * R29 (0x1D) - Output1 Right Volume
1144 */
1145#define WM8996_DAC1_VU 0x0100 /* DAC1_VU */
1146#define WM8996_DAC1_VU_MASK 0x0100 /* DAC1_VU */
1147#define WM8996_DAC1_VU_SHIFT 8 /* DAC1_VU */
1148#define WM8996_DAC1_VU_WIDTH 1 /* DAC1_VU */
1149#define WM8996_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */
1150#define WM8996_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */
1151#define WM8996_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */
1152#define WM8996_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */
1153#define WM8996_HPOUT1R_VOL_MASK 0x000F /* HPOUT1R_VOL - [3:0] */
1154#define WM8996_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [3:0] */
1155#define WM8996_HPOUT1R_VOL_WIDTH 4 /* HPOUT1R_VOL - [3:0] */
1156
1157/*
1158 * R30 (0x1E) - Output2 Left Volume
1159 */
1160#define WM8996_DAC2_VU 0x0100 /* DAC2_VU */
1161#define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */
1162#define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */
1163#define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */
1164#define WM8996_HPOUT2L_ZC 0x0080 /* HPOUT2L_ZC */
1165#define WM8996_HPOUT2L_ZC_MASK 0x0080 /* HPOUT2L_ZC */
1166#define WM8996_HPOUT2L_ZC_SHIFT 7 /* HPOUT2L_ZC */
1167#define WM8996_HPOUT2L_ZC_WIDTH 1 /* HPOUT2L_ZC */
1168#define WM8996_HPOUT2L_VOL_MASK 0x000F /* HPOUT2L_VOL - [3:0] */
1169#define WM8996_HPOUT2L_VOL_SHIFT 0 /* HPOUT2L_VOL - [3:0] */
1170#define WM8996_HPOUT2L_VOL_WIDTH 4 /* HPOUT2L_VOL - [3:0] */
1171
1172/*
1173 * R31 (0x1F) - Output2 Right Volume
1174 */
1175#define WM8996_DAC2_VU 0x0100 /* DAC2_VU */
1176#define WM8996_DAC2_VU_MASK 0x0100 /* DAC2_VU */
1177#define WM8996_DAC2_VU_SHIFT 8 /* DAC2_VU */
1178#define WM8996_DAC2_VU_WIDTH 1 /* DAC2_VU */
1179#define WM8996_HPOUT2R_ZC 0x0080 /* HPOUT2R_ZC */
1180#define WM8996_HPOUT2R_ZC_MASK 0x0080 /* HPOUT2R_ZC */
1181#define WM8996_HPOUT2R_ZC_SHIFT 7 /* HPOUT2R_ZC */
1182#define WM8996_HPOUT2R_ZC_WIDTH 1 /* HPOUT2R_ZC */
1183#define WM8996_HPOUT2R_VOL_MASK 0x000F /* HPOUT2R_VOL - [3:0] */
1184#define WM8996_HPOUT2R_VOL_SHIFT 0 /* HPOUT2R_VOL - [3:0] */
1185#define WM8996_HPOUT2R_VOL_WIDTH 4 /* HPOUT2R_VOL - [3:0] */
1186
1187/*
1188 * R32 (0x20) - MICBIAS (1)
1189 */
1190#define WM8996_MICB1_RATE 0x0020 /* MICB1_RATE */
1191#define WM8996_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */
1192#define WM8996_MICB1_RATE_SHIFT 5 /* MICB1_RATE */
1193#define WM8996_MICB1_RATE_WIDTH 1 /* MICB1_RATE */
1194#define WM8996_MICB1_MODE 0x0010 /* MICB1_MODE */
1195#define WM8996_MICB1_MODE_MASK 0x0010 /* MICB1_MODE */
1196#define WM8996_MICB1_MODE_SHIFT 4 /* MICB1_MODE */
1197#define WM8996_MICB1_MODE_WIDTH 1 /* MICB1_MODE */
1198#define WM8996_MICB1_LVL_MASK 0x000E /* MICB1_LVL - [3:1] */
1199#define WM8996_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [3:1] */
1200#define WM8996_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [3:1] */
1201#define WM8996_MICB1_DISCH 0x0001 /* MICB1_DISCH */
1202#define WM8996_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */
1203#define WM8996_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */
1204#define WM8996_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
1205
1206/*
1207 * R33 (0x21) - MICBIAS (2)
1208 */
1209#define WM8996_MICB2_RATE 0x0020 /* MICB2_RATE */
1210#define WM8996_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */
1211#define WM8996_MICB2_RATE_SHIFT 5 /* MICB2_RATE */
1212#define WM8996_MICB2_RATE_WIDTH 1 /* MICB2_RATE */
1213#define WM8996_MICB2_MODE 0x0010 /* MICB2_MODE */
1214#define WM8996_MICB2_MODE_MASK 0x0010 /* MICB2_MODE */
1215#define WM8996_MICB2_MODE_SHIFT 4 /* MICB2_MODE */
1216#define WM8996_MICB2_MODE_WIDTH 1 /* MICB2_MODE */
1217#define WM8996_MICB2_LVL_MASK 0x000E /* MICB2_LVL - [3:1] */
1218#define WM8996_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [3:1] */
1219#define WM8996_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [3:1] */
1220#define WM8996_MICB2_DISCH 0x0001 /* MICB2_DISCH */
1221#define WM8996_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */
1222#define WM8996_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */
1223#define WM8996_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
1224
1225/*
1226 * R40 (0x28) - LDO 1
1227 */
1228#define WM8996_LDO1_MODE 0x0020 /* LDO1_MODE */
1229#define WM8996_LDO1_MODE_MASK 0x0020 /* LDO1_MODE */
1230#define WM8996_LDO1_MODE_SHIFT 5 /* LDO1_MODE */
1231#define WM8996_LDO1_MODE_WIDTH 1 /* LDO1_MODE */
1232#define WM8996_LDO1_VSEL_MASK 0x0006 /* LDO1_VSEL - [2:1] */
1233#define WM8996_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [2:1] */
1234#define WM8996_LDO1_VSEL_WIDTH 2 /* LDO1_VSEL - [2:1] */
1235#define WM8996_LDO1_DISCH 0x0001 /* LDO1_DISCH */
1236#define WM8996_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */
1237#define WM8996_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */
1238#define WM8996_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */
1239
1240/*
1241 * R41 (0x29) - LDO 2
1242 */
1243#define WM8996_LDO2_MODE 0x0020 /* LDO2_MODE */
1244#define WM8996_LDO2_MODE_MASK 0x0020 /* LDO2_MODE */
1245#define WM8996_LDO2_MODE_SHIFT 5 /* LDO2_MODE */
1246#define WM8996_LDO2_MODE_WIDTH 1 /* LDO2_MODE */
1247#define WM8996_LDO2_VSEL_MASK 0x001E /* LDO2_VSEL - [4:1] */
1248#define WM8996_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [4:1] */
1249#define WM8996_LDO2_VSEL_WIDTH 4 /* LDO2_VSEL - [4:1] */
1250#define WM8996_LDO2_DISCH 0x0001 /* LDO2_DISCH */
1251#define WM8996_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */
1252#define WM8996_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */
1253#define WM8996_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */
1254
1255/*
1256 * R48 (0x30) - Accessory Detect Mode 1
1257 */
1258#define WM8996_JD_MODE_MASK 0x0003 /* JD_MODE - [1:0] */
1259#define WM8996_JD_MODE_SHIFT 0 /* JD_MODE - [1:0] */
1260#define WM8996_JD_MODE_WIDTH 2 /* JD_MODE - [1:0] */
1261
1262/*
1263 * R49 (0x31) - Accessory Detect Mode 2
1264 */
1265#define WM8996_HPOUT1FB_SRC 0x0004 /* HPOUT1FB_SRC */
1266#define WM8996_HPOUT1FB_SRC_MASK 0x0004 /* HPOUT1FB_SRC */
1267#define WM8996_HPOUT1FB_SRC_SHIFT 2 /* HPOUT1FB_SRC */
1268#define WM8996_HPOUT1FB_SRC_WIDTH 1 /* HPOUT1FB_SRC */
1269#define WM8996_MICD_SRC 0x0002 /* MICD_SRC */
1270#define WM8996_MICD_SRC_MASK 0x0002 /* MICD_SRC */
1271#define WM8996_MICD_SRC_SHIFT 1 /* MICD_SRC */
1272#define WM8996_MICD_SRC_WIDTH 1 /* MICD_SRC */
1273#define WM8996_MICD_BIAS_SRC 0x0001 /* MICD_BIAS_SRC */
1274#define WM8996_MICD_BIAS_SRC_MASK 0x0001 /* MICD_BIAS_SRC */
1275#define WM8996_MICD_BIAS_SRC_SHIFT 0 /* MICD_BIAS_SRC */
1276#define WM8996_MICD_BIAS_SRC_WIDTH 1 /* MICD_BIAS_SRC */
1277
1278/*
1279 * R52 (0x34) - Headphone Detect 1
1280 */
1281#define WM8996_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */
1282#define WM8996_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */
1283#define WM8996_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */
1284#define WM8996_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */
1285#define WM8996_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */
1286#define WM8996_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */
1287#define WM8996_HP_STEP_SIZE 0x0002 /* HP_STEP_SIZE */
1288#define WM8996_HP_STEP_SIZE_MASK 0x0002 /* HP_STEP_SIZE */
1289#define WM8996_HP_STEP_SIZE_SHIFT 1 /* HP_STEP_SIZE */
1290#define WM8996_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */
1291#define WM8996_HP_POLL 0x0001 /* HP_POLL */
1292#define WM8996_HP_POLL_MASK 0x0001 /* HP_POLL */
1293#define WM8996_HP_POLL_SHIFT 0 /* HP_POLL */
1294#define WM8996_HP_POLL_WIDTH 1 /* HP_POLL */
1295
1296/*
1297 * R53 (0x35) - Headphone Detect 2
1298 */
1299#define WM8996_HP_DONE 0x0080 /* HP_DONE */
1300#define WM8996_HP_DONE_MASK 0x0080 /* HP_DONE */
1301#define WM8996_HP_DONE_SHIFT 7 /* HP_DONE */
1302#define WM8996_HP_DONE_WIDTH 1 /* HP_DONE */
1303#define WM8996_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */
1304#define WM8996_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */
1305#define WM8996_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */
1306
1307/*
1308 * R56 (0x38) - Mic Detect 1
1309 */
1310#define WM8996_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */
1311#define WM8996_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */
1312#define WM8996_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */
1313#define WM8996_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */
1314#define WM8996_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */
1315#define WM8996_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */
1316#define WM8996_MICD_DBTIME 0x0002 /* MICD_DBTIME */
1317#define WM8996_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */
1318#define WM8996_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */
1319#define WM8996_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */
1320#define WM8996_MICD_ENA 0x0001 /* MICD_ENA */
1321#define WM8996_MICD_ENA_MASK 0x0001 /* MICD_ENA */
1322#define WM8996_MICD_ENA_SHIFT 0 /* MICD_ENA */
1323#define WM8996_MICD_ENA_WIDTH 1 /* MICD_ENA */
1324
1325/*
1326 * R57 (0x39) - Mic Detect 2
1327 */
1328#define WM8996_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */
1329#define WM8996_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */
1330#define WM8996_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */
1331
1332/*
1333 * R58 (0x3A) - Mic Detect 3
1334 */
1335#define WM8996_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */
1336#define WM8996_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */
1337#define WM8996_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */
1338#define WM8996_MICD_VALID 0x0002 /* MICD_VALID */
1339#define WM8996_MICD_VALID_MASK 0x0002 /* MICD_VALID */
1340#define WM8996_MICD_VALID_SHIFT 1 /* MICD_VALID */
1341#define WM8996_MICD_VALID_WIDTH 1 /* MICD_VALID */
1342#define WM8996_MICD_STS 0x0001 /* MICD_STS */
1343#define WM8996_MICD_STS_MASK 0x0001 /* MICD_STS */
1344#define WM8996_MICD_STS_SHIFT 0 /* MICD_STS */
1345#define WM8996_MICD_STS_WIDTH 1 /* MICD_STS */
1346
1347/*
1348 * R64 (0x40) - Charge Pump (1)
1349 */
1350#define WM8996_CP_ENA 0x8000 /* CP_ENA */
1351#define WM8996_CP_ENA_MASK 0x8000 /* CP_ENA */
1352#define WM8996_CP_ENA_SHIFT 15 /* CP_ENA */
1353#define WM8996_CP_ENA_WIDTH 1 /* CP_ENA */
1354
1355/*
1356 * R65 (0x41) - Charge Pump (2)
1357 */
1358#define WM8996_CP_DISCH 0x8000 /* CP_DISCH */
1359#define WM8996_CP_DISCH_MASK 0x8000 /* CP_DISCH */
1360#define WM8996_CP_DISCH_SHIFT 15 /* CP_DISCH */
1361#define WM8996_CP_DISCH_WIDTH 1 /* CP_DISCH */
1362
1363/*
1364 * R80 (0x50) - DC Servo (1)
1365 */
1366#define WM8996_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */
1367#define WM8996_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */
1368#define WM8996_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */
1369#define WM8996_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */
1370#define WM8996_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */
1371#define WM8996_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */
1372#define WM8996_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */
1373#define WM8996_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */
1374#define WM8996_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */
1375#define WM8996_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */
1376#define WM8996_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */
1377#define WM8996_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */
1378#define WM8996_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */
1379#define WM8996_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */
1380#define WM8996_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */
1381#define WM8996_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */
1382
1383/*
1384 * R81 (0x51) - DC Servo (2)
1385 */
1386#define WM8996_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */
1387#define WM8996_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */
1388#define WM8996_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */
1389#define WM8996_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */
1390#define WM8996_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */
1391#define WM8996_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */
1392#define WM8996_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */
1393#define WM8996_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */
1394#define WM8996_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */
1395#define WM8996_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */
1396#define WM8996_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */
1397#define WM8996_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */
1398#define WM8996_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */
1399#define WM8996_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */
1400#define WM8996_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */
1401#define WM8996_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */
1402#define WM8996_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */
1403#define WM8996_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */
1404#define WM8996_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */
1405#define WM8996_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */
1406#define WM8996_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */
1407#define WM8996_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */
1408#define WM8996_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */
1409#define WM8996_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */
1410#define WM8996_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */
1411#define WM8996_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */
1412#define WM8996_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */
1413#define WM8996_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */
1414#define WM8996_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */
1415#define WM8996_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */
1416#define WM8996_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */
1417#define WM8996_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */
1418#define WM8996_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */
1419#define WM8996_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */
1420#define WM8996_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */
1421#define WM8996_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */
1422#define WM8996_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */
1423#define WM8996_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */
1424#define WM8996_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */
1425#define WM8996_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */
1426#define WM8996_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */
1427#define WM8996_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */
1428#define WM8996_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */
1429#define WM8996_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */
1430#define WM8996_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */
1431#define WM8996_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */
1432#define WM8996_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */
1433#define WM8996_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */
1434#define WM8996_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */
1435#define WM8996_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */
1436#define WM8996_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */
1437#define WM8996_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */
1438#define WM8996_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */
1439#define WM8996_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */
1440#define WM8996_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */
1441#define WM8996_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */
1442#define WM8996_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */
1443#define WM8996_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */
1444#define WM8996_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */
1445#define WM8996_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */
1446#define WM8996_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */
1447#define WM8996_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */
1448#define WM8996_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */
1449#define WM8996_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */
1450
1451/*
1452 * R82 (0x52) - DC Servo (3)
1453 */
1454#define WM8996_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */
1455#define WM8996_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */
1456#define WM8996_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */
1457#define WM8996_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */
1458#define WM8996_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */
1459#define WM8996_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */
1460
1461/*
1462 * R84 (0x54) - DC Servo (5)
1463 */
1464#define WM8996_DCS_SERIES_NO_23_MASK 0x7F00 /* DCS_SERIES_NO_23 - [14:8] */
1465#define WM8996_DCS_SERIES_NO_23_SHIFT 8 /* DCS_SERIES_NO_23 - [14:8] */
1466#define WM8996_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [14:8] */
1467#define WM8996_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */
1468#define WM8996_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */
1469#define WM8996_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */
1470
1471/*
1472 * R85 (0x55) - DC Servo (6)
1473 */
1474#define WM8996_DCS_DAC_WR_VAL_3_MASK 0xFF00 /* DCS_DAC_WR_VAL_3 - [15:8] */
1475#define WM8996_DCS_DAC_WR_VAL_3_SHIFT 8 /* DCS_DAC_WR_VAL_3 - [15:8] */
1476#define WM8996_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [15:8] */
1477#define WM8996_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */
1478#define WM8996_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */
1479#define WM8996_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */
1480
1481/*
1482 * R86 (0x56) - DC Servo (7)
1483 */
1484#define WM8996_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */
1485#define WM8996_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
1486#define WM8996_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */
1487#define WM8996_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */
1488#define WM8996_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */
1489#define WM8996_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */
1490
1491/*
1492 * R87 (0x57) - DC Servo Readback 0
1493 */
1494#define WM8996_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */
1495#define WM8996_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */
1496#define WM8996_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */
1497#define WM8996_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */
1498#define WM8996_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */
1499#define WM8996_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */
1500#define WM8996_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */
1501#define WM8996_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */
1502#define WM8996_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */
1503
1504/*
1505 * R96 (0x60) - Analogue HP (1)
1506 */
1507#define WM8996_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */
1508#define WM8996_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */
1509#define WM8996_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */
1510#define WM8996_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */
1511#define WM8996_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */
1512#define WM8996_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */
1513#define WM8996_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */
1514#define WM8996_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */
1515#define WM8996_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */
1516#define WM8996_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */
1517#define WM8996_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */
1518#define WM8996_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */
1519#define WM8996_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */
1520#define WM8996_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */
1521#define WM8996_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */
1522#define WM8996_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */
1523#define WM8996_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */
1524#define WM8996_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */
1525#define WM8996_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */
1526#define WM8996_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */
1527#define WM8996_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */
1528#define WM8996_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */
1529#define WM8996_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */
1530#define WM8996_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */
1531
1532/*
1533 * R97 (0x61) - Analogue HP (2)
1534 */
1535#define WM8996_HPOUT2L_RMV_SHORT 0x0080 /* HPOUT2L_RMV_SHORT */
1536#define WM8996_HPOUT2L_RMV_SHORT_MASK 0x0080 /* HPOUT2L_RMV_SHORT */
1537#define WM8996_HPOUT2L_RMV_SHORT_SHIFT 7 /* HPOUT2L_RMV_SHORT */
1538#define WM8996_HPOUT2L_RMV_SHORT_WIDTH 1 /* HPOUT2L_RMV_SHORT */
1539#define WM8996_HPOUT2L_OUTP 0x0040 /* HPOUT2L_OUTP */
1540#define WM8996_HPOUT2L_OUTP_MASK 0x0040 /* HPOUT2L_OUTP */
1541#define WM8996_HPOUT2L_OUTP_SHIFT 6 /* HPOUT2L_OUTP */
1542#define WM8996_HPOUT2L_OUTP_WIDTH 1 /* HPOUT2L_OUTP */
1543#define WM8996_HPOUT2L_DLY 0x0020 /* HPOUT2L_DLY */
1544#define WM8996_HPOUT2L_DLY_MASK 0x0020 /* HPOUT2L_DLY */
1545#define WM8996_HPOUT2L_DLY_SHIFT 5 /* HPOUT2L_DLY */
1546#define WM8996_HPOUT2L_DLY_WIDTH 1 /* HPOUT2L_DLY */
1547#define WM8996_HPOUT2R_RMV_SHORT 0x0008 /* HPOUT2R_RMV_SHORT */
1548#define WM8996_HPOUT2R_RMV_SHORT_MASK 0x0008 /* HPOUT2R_RMV_SHORT */
1549#define WM8996_HPOUT2R_RMV_SHORT_SHIFT 3 /* HPOUT2R_RMV_SHORT */
1550#define WM8996_HPOUT2R_RMV_SHORT_WIDTH 1 /* HPOUT2R_RMV_SHORT */
1551#define WM8996_HPOUT2R_OUTP 0x0004 /* HPOUT2R_OUTP */
1552#define WM8996_HPOUT2R_OUTP_MASK 0x0004 /* HPOUT2R_OUTP */
1553#define WM8996_HPOUT2R_OUTP_SHIFT 2 /* HPOUT2R_OUTP */
1554#define WM8996_HPOUT2R_OUTP_WIDTH 1 /* HPOUT2R_OUTP */
1555#define WM8996_HPOUT2R_DLY 0x0002 /* HPOUT2R_DLY */
1556#define WM8996_HPOUT2R_DLY_MASK 0x0002 /* HPOUT2R_DLY */
1557#define WM8996_HPOUT2R_DLY_SHIFT 1 /* HPOUT2R_DLY */
1558#define WM8996_HPOUT2R_DLY_WIDTH 1 /* HPOUT2R_DLY */
1559
1560/*
1561 * R256 (0x100) - Chip Revision
1562 */
1563#define WM8996_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */
1564#define WM8996_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */
1565#define WM8996_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */
1566
1567/*
1568 * R257 (0x101) - Control Interface (1)
1569 */
1570#define WM8996_AUTO_INC 0x0004 /* AUTO_INC */
1571#define WM8996_AUTO_INC_MASK 0x0004 /* AUTO_INC */
1572#define WM8996_AUTO_INC_SHIFT 2 /* AUTO_INC */
1573#define WM8996_AUTO_INC_WIDTH 1 /* AUTO_INC */
1574
1575/*
1576 * R272 (0x110) - Write Sequencer Ctrl (1)
1577 */
1578#define WM8996_WSEQ_ENA 0x8000 /* WSEQ_ENA */
1579#define WM8996_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */
1580#define WM8996_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */
1581#define WM8996_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
1582#define WM8996_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
1583#define WM8996_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
1584#define WM8996_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */
1585#define WM8996_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
1586#define WM8996_WSEQ_START 0x0100 /* WSEQ_START */
1587#define WM8996_WSEQ_START_MASK 0x0100 /* WSEQ_START */
1588#define WM8996_WSEQ_START_SHIFT 8 /* WSEQ_START */
1589#define WM8996_WSEQ_START_WIDTH 1 /* WSEQ_START */
1590#define WM8996_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */
1591#define WM8996_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */
1592#define WM8996_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */
1593
1594/*
1595 * R273 (0x111) - Write Sequencer Ctrl (2)
1596 */
1597#define WM8996_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */
1598#define WM8996_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */
1599#define WM8996_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */
1600#define WM8996_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
1601#define WM8996_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */
1602#define WM8996_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */
1603#define WM8996_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */
1604
1605/*
1606 * R512 (0x200) - AIF Clocking (1)
1607 */
1608#define WM8996_SYSCLK_SRC_MASK 0x0018 /* SYSCLK_SRC - [4:3] */
1609#define WM8996_SYSCLK_SRC_SHIFT 3 /* SYSCLK_SRC - [4:3] */
1610#define WM8996_SYSCLK_SRC_WIDTH 2 /* SYSCLK_SRC - [4:3] */
1611#define WM8996_SYSCLK_INV 0x0004 /* SYSCLK_INV */
1612#define WM8996_SYSCLK_INV_MASK 0x0004 /* SYSCLK_INV */
1613#define WM8996_SYSCLK_INV_SHIFT 2 /* SYSCLK_INV */
1614#define WM8996_SYSCLK_INV_WIDTH 1 /* SYSCLK_INV */
1615#define WM8996_SYSCLK_DIV 0x0002 /* SYSCLK_DIV */
1616#define WM8996_SYSCLK_DIV_MASK 0x0002 /* SYSCLK_DIV */
1617#define WM8996_SYSCLK_DIV_SHIFT 1 /* SYSCLK_DIV */
1618#define WM8996_SYSCLK_DIV_WIDTH 1 /* SYSCLK_DIV */
1619#define WM8996_SYSCLK_ENA 0x0001 /* SYSCLK_ENA */
1620#define WM8996_SYSCLK_ENA_MASK 0x0001 /* SYSCLK_ENA */
1621#define WM8996_SYSCLK_ENA_SHIFT 0 /* SYSCLK_ENA */
1622#define WM8996_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */
1623
1624/*
1625 * R513 (0x201) - AIF Clocking (2)
1626 */
1627#define WM8996_DSP2_DIV_MASK 0x0018 /* DSP2_DIV - [4:3] */
1628#define WM8996_DSP2_DIV_SHIFT 3 /* DSP2_DIV - [4:3] */
1629#define WM8996_DSP2_DIV_WIDTH 2 /* DSP2_DIV - [4:3] */
1630#define WM8996_DSP1_DIV_MASK 0x0003 /* DSP1_DIV - [1:0] */
1631#define WM8996_DSP1_DIV_SHIFT 0 /* DSP1_DIV - [1:0] */
1632#define WM8996_DSP1_DIV_WIDTH 2 /* DSP1_DIV - [1:0] */
1633
1634/*
1635 * R520 (0x208) - Clocking (1)
1636 */
1637#define WM8996_LFCLK_ENA 0x0020 /* LFCLK_ENA */
1638#define WM8996_LFCLK_ENA_MASK 0x0020 /* LFCLK_ENA */
1639#define WM8996_LFCLK_ENA_SHIFT 5 /* LFCLK_ENA */
1640#define WM8996_LFCLK_ENA_WIDTH 1 /* LFCLK_ENA */
1641#define WM8996_TOCLK_ENA 0x0010 /* TOCLK_ENA */
1642#define WM8996_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */
1643#define WM8996_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */
1644#define WM8996_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */
1645#define WM8996_AIFCLK_ENA 0x0004 /* AIFCLK_ENA */
1646#define WM8996_AIFCLK_ENA_MASK 0x0004 /* AIFCLK_ENA */
1647#define WM8996_AIFCLK_ENA_SHIFT 2 /* AIFCLK_ENA */
1648#define WM8996_AIFCLK_ENA_WIDTH 1 /* AIFCLK_ENA */
1649#define WM8996_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */
1650#define WM8996_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */
1651#define WM8996_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */
1652#define WM8996_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */
1653
1654/*
1655 * R521 (0x209) - Clocking (2)
1656 */
1657#define WM8996_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */
1658#define WM8996_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */
1659#define WM8996_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */
1660#define WM8996_DBCLK_DIV_MASK 0x00F0 /* DBCLK_DIV - [7:4] */
1661#define WM8996_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [7:4] */
1662#define WM8996_DBCLK_DIV_WIDTH 4 /* DBCLK_DIV - [7:4] */
1663#define WM8996_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */
1664#define WM8996_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */
1665#define WM8996_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */
1666
1667/*
1668 * R528 (0x210) - AIF Rate
1669 */
1670#define WM8996_SYSCLK_RATE 0x0001 /* SYSCLK_RATE */
1671#define WM8996_SYSCLK_RATE_MASK 0x0001 /* SYSCLK_RATE */
1672#define WM8996_SYSCLK_RATE_SHIFT 0 /* SYSCLK_RATE */
1673#define WM8996_SYSCLK_RATE_WIDTH 1 /* SYSCLK_RATE */
1674
1675/*
1676 * R544 (0x220) - FLL Control (1)
1677 */
1678#define WM8996_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */
1679#define WM8996_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */
1680#define WM8996_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */
1681#define WM8996_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */
1682#define WM8996_FLL_ENA 0x0001 /* FLL_ENA */
1683#define WM8996_FLL_ENA_MASK 0x0001 /* FLL_ENA */
1684#define WM8996_FLL_ENA_SHIFT 0 /* FLL_ENA */
1685#define WM8996_FLL_ENA_WIDTH 1 /* FLL_ENA */
1686
1687/*
1688 * R545 (0x221) - FLL Control (2)
1689 */
1690#define WM8996_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */
1691#define WM8996_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */
1692#define WM8996_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */
1693#define WM8996_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
1694#define WM8996_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
1695#define WM8996_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
1696
1697/*
1698 * R546 (0x222) - FLL Control (3)
1699 */
1700#define WM8996_FLL_THETA_MASK 0xFFFF /* FLL_THETA - [15:0] */
1701#define WM8996_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */
1702#define WM8996_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */
1703
1704/*
1705 * R547 (0x223) - FLL Control (4)
1706 */
1707#define WM8996_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
1708#define WM8996_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
1709#define WM8996_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
1710#define WM8996_FLL_LOOP_GAIN_MASK 0x000F /* FLL_LOOP_GAIN - [3:0] */
1711#define WM8996_FLL_LOOP_GAIN_SHIFT 0 /* FLL_LOOP_GAIN - [3:0] */
1712#define WM8996_FLL_LOOP_GAIN_WIDTH 4 /* FLL_LOOP_GAIN - [3:0] */
1713
1714/*
1715 * R548 (0x224) - FLL Control (5)
1716 */
1717#define WM8996_FLL_FRC_NCO_VAL_MASK 0x1F80 /* FLL_FRC_NCO_VAL - [12:7] */
1718#define WM8996_FLL_FRC_NCO_VAL_SHIFT 7 /* FLL_FRC_NCO_VAL - [12:7] */
1719#define WM8996_FLL_FRC_NCO_VAL_WIDTH 6 /* FLL_FRC_NCO_VAL - [12:7] */
1720#define WM8996_FLL_FRC_NCO 0x0040 /* FLL_FRC_NCO */
1721#define WM8996_FLL_FRC_NCO_MASK 0x0040 /* FLL_FRC_NCO */
1722#define WM8996_FLL_FRC_NCO_SHIFT 6 /* FLL_FRC_NCO */
1723#define WM8996_FLL_FRC_NCO_WIDTH 1 /* FLL_FRC_NCO */
1724#define WM8996_FLL_REFCLK_DIV_MASK 0x0018 /* FLL_REFCLK_DIV - [4:3] */
1725#define WM8996_FLL_REFCLK_DIV_SHIFT 3 /* FLL_REFCLK_DIV - [4:3] */
1726#define WM8996_FLL_REFCLK_DIV_WIDTH 2 /* FLL_REFCLK_DIV - [4:3] */
1727#define WM8996_FLL_REF_FREQ 0x0004 /* FLL_REF_FREQ */
1728#define WM8996_FLL_REF_FREQ_MASK 0x0004 /* FLL_REF_FREQ */
1729#define WM8996_FLL_REF_FREQ_SHIFT 2 /* FLL_REF_FREQ */
1730#define WM8996_FLL_REF_FREQ_WIDTH 1 /* FLL_REF_FREQ */
1731#define WM8996_FLL_REFCLK_SRC_MASK 0x0003 /* FLL_REFCLK_SRC - [1:0] */
1732#define WM8996_FLL_REFCLK_SRC_SHIFT 0 /* FLL_REFCLK_SRC - [1:0] */
1733#define WM8996_FLL_REFCLK_SRC_WIDTH 2 /* FLL_REFCLK_SRC - [1:0] */
1734
1735/*
1736 * R549 (0x225) - FLL Control (6)
1737 */
1738#define WM8996_FLL_REFCLK_SRC_STS_MASK 0x000C /* FLL_REFCLK_SRC_STS - [3:2] */
1739#define WM8996_FLL_REFCLK_SRC_STS_SHIFT 2 /* FLL_REFCLK_SRC_STS - [3:2] */
1740#define WM8996_FLL_REFCLK_SRC_STS_WIDTH 2 /* FLL_REFCLK_SRC_STS - [3:2] */
1741#define WM8996_FLL_SWITCH_CLK 0x0001 /* FLL_SWITCH_CLK */
1742#define WM8996_FLL_SWITCH_CLK_MASK 0x0001 /* FLL_SWITCH_CLK */
1743#define WM8996_FLL_SWITCH_CLK_SHIFT 0 /* FLL_SWITCH_CLK */
1744#define WM8996_FLL_SWITCH_CLK_WIDTH 1 /* FLL_SWITCH_CLK */
1745
1746/*
1747 * R550 (0x226) - FLL EFS 1
1748 */
1749#define WM8996_FLL_LAMBDA_MASK 0xFFFF /* FLL_LAMBDA - [15:0] */
1750#define WM8996_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */
1751#define WM8996_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */
1752
1753/*
1754 * R551 (0x227) - FLL EFS 2
1755 */
1756#define WM8996_FLL_LFSR_SEL_MASK 0x0006 /* FLL_LFSR_SEL - [2:1] */
1757#define WM8996_FLL_LFSR_SEL_SHIFT 1 /* FLL_LFSR_SEL - [2:1] */
1758#define WM8996_FLL_LFSR_SEL_WIDTH 2 /* FLL_LFSR_SEL - [2:1] */
1759#define WM8996_FLL_EFS_ENA 0x0001 /* FLL_EFS_ENA */
1760#define WM8996_FLL_EFS_ENA_MASK 0x0001 /* FLL_EFS_ENA */
1761#define WM8996_FLL_EFS_ENA_SHIFT 0 /* FLL_EFS_ENA */
1762#define WM8996_FLL_EFS_ENA_WIDTH 1 /* FLL_EFS_ENA */
1763
1764/*
1765 * R768 (0x300) - AIF1 Control
1766 */
1767#define WM8996_AIF1_TRI 0x0004 /* AIF1_TRI */
1768#define WM8996_AIF1_TRI_MASK 0x0004 /* AIF1_TRI */
1769#define WM8996_AIF1_TRI_SHIFT 2 /* AIF1_TRI */
1770#define WM8996_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
1771#define WM8996_AIF1_FMT_MASK 0x0003 /* AIF1_FMT - [1:0] */
1772#define WM8996_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [1:0] */
1773#define WM8996_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [1:0] */
1774
1775/*
1776 * R769 (0x301) - AIF1 BCLK
1777 */
1778#define WM8996_AIF1_BCLK_INV 0x0400 /* AIF1_BCLK_INV */
1779#define WM8996_AIF1_BCLK_INV_MASK 0x0400 /* AIF1_BCLK_INV */
1780#define WM8996_AIF1_BCLK_INV_SHIFT 10 /* AIF1_BCLK_INV */
1781#define WM8996_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
1782#define WM8996_AIF1_BCLK_FRC 0x0200 /* AIF1_BCLK_FRC */
1783#define WM8996_AIF1_BCLK_FRC_MASK 0x0200 /* AIF1_BCLK_FRC */
1784#define WM8996_AIF1_BCLK_FRC_SHIFT 9 /* AIF1_BCLK_FRC */
1785#define WM8996_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */
1786#define WM8996_AIF1_BCLK_MSTR 0x0100 /* AIF1_BCLK_MSTR */
1787#define WM8996_AIF1_BCLK_MSTR_MASK 0x0100 /* AIF1_BCLK_MSTR */
1788#define WM8996_AIF1_BCLK_MSTR_SHIFT 8 /* AIF1_BCLK_MSTR */
1789#define WM8996_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */
1790#define WM8996_AIF1_BCLK_DIV_MASK 0x000F /* AIF1_BCLK_DIV - [3:0] */
1791#define WM8996_AIF1_BCLK_DIV_SHIFT 0 /* AIF1_BCLK_DIV - [3:0] */
1792#define WM8996_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [3:0] */
1793
1794/*
1795 * R770 (0x302) - AIF1 TX LRCLK(1)
1796 */
1797#define WM8996_AIF1TX_RATE_MASK 0x07FF /* AIF1TX_RATE - [10:0] */
1798#define WM8996_AIF1TX_RATE_SHIFT 0 /* AIF1TX_RATE - [10:0] */
1799#define WM8996_AIF1TX_RATE_WIDTH 11 /* AIF1TX_RATE - [10:0] */
1800
1801/*
1802 * R771 (0x303) - AIF1 TX LRCLK(2)
1803 */
1804#define WM8996_AIF1TX_LRCLK_MODE 0x0008 /* AIF1TX_LRCLK_MODE */
1805#define WM8996_AIF1TX_LRCLK_MODE_MASK 0x0008 /* AIF1TX_LRCLK_MODE */
1806#define WM8996_AIF1TX_LRCLK_MODE_SHIFT 3 /* AIF1TX_LRCLK_MODE */
1807#define WM8996_AIF1TX_LRCLK_MODE_WIDTH 1 /* AIF1TX_LRCLK_MODE */
1808#define WM8996_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */
1809#define WM8996_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */
1810#define WM8996_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */
1811#define WM8996_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */
1812#define WM8996_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */
1813#define WM8996_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */
1814#define WM8996_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */
1815#define WM8996_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */
1816#define WM8996_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */
1817#define WM8996_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */
1818#define WM8996_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */
1819#define WM8996_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */
1820
1821/*
1822 * R772 (0x304) - AIF1 RX LRCLK(1)
1823 */
1824#define WM8996_AIF1RX_RATE_MASK 0x07FF /* AIF1RX_RATE - [10:0] */
1825#define WM8996_AIF1RX_RATE_SHIFT 0 /* AIF1RX_RATE - [10:0] */
1826#define WM8996_AIF1RX_RATE_WIDTH 11 /* AIF1RX_RATE - [10:0] */
1827
1828/*
1829 * R773 (0x305) - AIF1 RX LRCLK(2)
1830 */
1831#define WM8996_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */
1832#define WM8996_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */
1833#define WM8996_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */
1834#define WM8996_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */
1835#define WM8996_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */
1836#define WM8996_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */
1837#define WM8996_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */
1838#define WM8996_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */
1839#define WM8996_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */
1840#define WM8996_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */
1841#define WM8996_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */
1842#define WM8996_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */
1843
1844/*
1845 * R774 (0x306) - AIF1TX Data Configuration (1)
1846 */
1847#define WM8996_AIF1TX_WL_MASK 0xFF00 /* AIF1TX_WL - [15:8] */
1848#define WM8996_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [15:8] */
1849#define WM8996_AIF1TX_WL_WIDTH 8 /* AIF1TX_WL - [15:8] */
1850#define WM8996_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */
1851#define WM8996_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */
1852#define WM8996_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */
1853
1854/*
1855 * R775 (0x307) - AIF1TX Data Configuration (2)
1856 */
1857#define WM8996_AIF1TX_DAT_TRI 0x0001 /* AIF1TX_DAT_TRI */
1858#define WM8996_AIF1TX_DAT_TRI_MASK 0x0001 /* AIF1TX_DAT_TRI */
1859#define WM8996_AIF1TX_DAT_TRI_SHIFT 0 /* AIF1TX_DAT_TRI */
1860#define WM8996_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */
1861
1862/*
1863 * R776 (0x308) - AIF1RX Data Configuration
1864 */
1865#define WM8996_AIF1RX_WL_MASK 0xFF00 /* AIF1RX_WL - [15:8] */
1866#define WM8996_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [15:8] */
1867#define WM8996_AIF1RX_WL_WIDTH 8 /* AIF1RX_WL - [15:8] */
1868#define WM8996_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */
1869#define WM8996_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */
1870#define WM8996_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */
1871
1872/*
1873 * R777 (0x309) - AIF1TX Channel 0 Configuration
1874 */
1875#define WM8996_AIF1TX_CHAN0_DAT_INV 0x8000 /* AIF1TX_CHAN0_DAT_INV */
1876#define WM8996_AIF1TX_CHAN0_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN0_DAT_INV */
1877#define WM8996_AIF1TX_CHAN0_DAT_INV_SHIFT 15 /* AIF1TX_CHAN0_DAT_INV */
1878#define WM8996_AIF1TX_CHAN0_DAT_INV_WIDTH 1 /* AIF1TX_CHAN0_DAT_INV */
1879#define WM8996_AIF1TX_CHAN0_SPACING_MASK 0x7E00 /* AIF1TX_CHAN0_SPACING - [14:9] */
1880#define WM8996_AIF1TX_CHAN0_SPACING_SHIFT 9 /* AIF1TX_CHAN0_SPACING - [14:9] */
1881#define WM8996_AIF1TX_CHAN0_SPACING_WIDTH 6 /* AIF1TX_CHAN0_SPACING - [14:9] */
1882#define WM8996_AIF1TX_CHAN0_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN0_SLOTS - [8:6] */
1883#define WM8996_AIF1TX_CHAN0_SLOTS_SHIFT 6 /* AIF1TX_CHAN0_SLOTS - [8:6] */
1884#define WM8996_AIF1TX_CHAN0_SLOTS_WIDTH 3 /* AIF1TX_CHAN0_SLOTS - [8:6] */
1885#define WM8996_AIF1TX_CHAN0_START_SLOT_MASK 0x003F /* AIF1TX_CHAN0_START_SLOT - [5:0] */
1886#define WM8996_AIF1TX_CHAN0_START_SLOT_SHIFT 0 /* AIF1TX_CHAN0_START_SLOT - [5:0] */
1887#define WM8996_AIF1TX_CHAN0_START_SLOT_WIDTH 6 /* AIF1TX_CHAN0_START_SLOT - [5:0] */
1888
1889/*
1890 * R778 (0x30A) - AIF1TX Channel 1 Configuration
1891 */
1892#define WM8996_AIF1TX_CHAN1_DAT_INV 0x8000 /* AIF1TX_CHAN1_DAT_INV */
1893#define WM8996_AIF1TX_CHAN1_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN1_DAT_INV */
1894#define WM8996_AIF1TX_CHAN1_DAT_INV_SHIFT 15 /* AIF1TX_CHAN1_DAT_INV */
1895#define WM8996_AIF1TX_CHAN1_DAT_INV_WIDTH 1 /* AIF1TX_CHAN1_DAT_INV */
1896#define WM8996_AIF1TX_CHAN1_SPACING_MASK 0x7E00 /* AIF1TX_CHAN1_SPACING - [14:9] */
1897#define WM8996_AIF1TX_CHAN1_SPACING_SHIFT 9 /* AIF1TX_CHAN1_SPACING - [14:9] */
1898#define WM8996_AIF1TX_CHAN1_SPACING_WIDTH 6 /* AIF1TX_CHAN1_SPACING - [14:9] */
1899#define WM8996_AIF1TX_CHAN1_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN1_SLOTS - [8:6] */
1900#define WM8996_AIF1TX_CHAN1_SLOTS_SHIFT 6 /* AIF1TX_CHAN1_SLOTS - [8:6] */
1901#define WM8996_AIF1TX_CHAN1_SLOTS_WIDTH 3 /* AIF1TX_CHAN1_SLOTS - [8:6] */
1902#define WM8996_AIF1TX_CHAN1_START_SLOT_MASK 0x003F /* AIF1TX_CHAN1_START_SLOT - [5:0] */
1903#define WM8996_AIF1TX_CHAN1_START_SLOT_SHIFT 0 /* AIF1TX_CHAN1_START_SLOT - [5:0] */
1904#define WM8996_AIF1TX_CHAN1_START_SLOT_WIDTH 6 /* AIF1TX_CHAN1_START_SLOT - [5:0] */
1905
1906/*
1907 * R779 (0x30B) - AIF1TX Channel 2 Configuration
1908 */
1909#define WM8996_AIF1TX_CHAN2_DAT_INV 0x8000 /* AIF1TX_CHAN2_DAT_INV */
1910#define WM8996_AIF1TX_CHAN2_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN2_DAT_INV */
1911#define WM8996_AIF1TX_CHAN2_DAT_INV_SHIFT 15 /* AIF1TX_CHAN2_DAT_INV */
1912#define WM8996_AIF1TX_CHAN2_DAT_INV_WIDTH 1 /* AIF1TX_CHAN2_DAT_INV */
1913#define WM8996_AIF1TX_CHAN2_SPACING_MASK 0x7E00 /* AIF1TX_CHAN2_SPACING - [14:9] */
1914#define WM8996_AIF1TX_CHAN2_SPACING_SHIFT 9 /* AIF1TX_CHAN2_SPACING - [14:9] */
1915#define WM8996_AIF1TX_CHAN2_SPACING_WIDTH 6 /* AIF1TX_CHAN2_SPACING - [14:9] */
1916#define WM8996_AIF1TX_CHAN2_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN2_SLOTS - [8:6] */
1917#define WM8996_AIF1TX_CHAN2_SLOTS_SHIFT 6 /* AIF1TX_CHAN2_SLOTS - [8:6] */
1918#define WM8996_AIF1TX_CHAN2_SLOTS_WIDTH 3 /* AIF1TX_CHAN2_SLOTS - [8:6] */
1919#define WM8996_AIF1TX_CHAN2_START_SLOT_MASK 0x003F /* AIF1TX_CHAN2_START_SLOT - [5:0] */
1920#define WM8996_AIF1TX_CHAN2_START_SLOT_SHIFT 0 /* AIF1TX_CHAN2_START_SLOT - [5:0] */
1921#define WM8996_AIF1TX_CHAN2_START_SLOT_WIDTH 6 /* AIF1TX_CHAN2_START_SLOT - [5:0] */
1922
1923/*
1924 * R780 (0x30C) - AIF1TX Channel 3 Configuration
1925 */
1926#define WM8996_AIF1TX_CHAN3_DAT_INV 0x8000 /* AIF1TX_CHAN3_DAT_INV */
1927#define WM8996_AIF1TX_CHAN3_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN3_DAT_INV */
1928#define WM8996_AIF1TX_CHAN3_DAT_INV_SHIFT 15 /* AIF1TX_CHAN3_DAT_INV */
1929#define WM8996_AIF1TX_CHAN3_DAT_INV_WIDTH 1 /* AIF1TX_CHAN3_DAT_INV */
1930#define WM8996_AIF1TX_CHAN3_SPACING_MASK 0x7E00 /* AIF1TX_CHAN3_SPACING - [14:9] */
1931#define WM8996_AIF1TX_CHAN3_SPACING_SHIFT 9 /* AIF1TX_CHAN3_SPACING - [14:9] */
1932#define WM8996_AIF1TX_CHAN3_SPACING_WIDTH 6 /* AIF1TX_CHAN3_SPACING - [14:9] */
1933#define WM8996_AIF1TX_CHAN3_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN3_SLOTS - [8:6] */
1934#define WM8996_AIF1TX_CHAN3_SLOTS_SHIFT 6 /* AIF1TX_CHAN3_SLOTS - [8:6] */
1935#define WM8996_AIF1TX_CHAN3_SLOTS_WIDTH 3 /* AIF1TX_CHAN3_SLOTS - [8:6] */
1936#define WM8996_AIF1TX_CHAN3_START_SLOT_MASK 0x003F /* AIF1TX_CHAN3_START_SLOT - [5:0] */
1937#define WM8996_AIF1TX_CHAN3_START_SLOT_SHIFT 0 /* AIF1TX_CHAN3_START_SLOT - [5:0] */
1938#define WM8996_AIF1TX_CHAN3_START_SLOT_WIDTH 6 /* AIF1TX_CHAN3_START_SLOT - [5:0] */
1939
1940/*
1941 * R781 (0x30D) - AIF1TX Channel 4 Configuration
1942 */
1943#define WM8996_AIF1TX_CHAN4_DAT_INV 0x8000 /* AIF1TX_CHAN4_DAT_INV */
1944#define WM8996_AIF1TX_CHAN4_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN4_DAT_INV */
1945#define WM8996_AIF1TX_CHAN4_DAT_INV_SHIFT 15 /* AIF1TX_CHAN4_DAT_INV */
1946#define WM8996_AIF1TX_CHAN4_DAT_INV_WIDTH 1 /* AIF1TX_CHAN4_DAT_INV */
1947#define WM8996_AIF1TX_CHAN4_SPACING_MASK 0x7E00 /* AIF1TX_CHAN4_SPACING - [14:9] */
1948#define WM8996_AIF1TX_CHAN4_SPACING_SHIFT 9 /* AIF1TX_CHAN4_SPACING - [14:9] */
1949#define WM8996_AIF1TX_CHAN4_SPACING_WIDTH 6 /* AIF1TX_CHAN4_SPACING - [14:9] */
1950#define WM8996_AIF1TX_CHAN4_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN4_SLOTS - [8:6] */
1951#define WM8996_AIF1TX_CHAN4_SLOTS_SHIFT 6 /* AIF1TX_CHAN4_SLOTS - [8:6] */
1952#define WM8996_AIF1TX_CHAN4_SLOTS_WIDTH 3 /* AIF1TX_CHAN4_SLOTS - [8:6] */
1953#define WM8996_AIF1TX_CHAN4_START_SLOT_MASK 0x003F /* AIF1TX_CHAN4_START_SLOT - [5:0] */
1954#define WM8996_AIF1TX_CHAN4_START_SLOT_SHIFT 0 /* AIF1TX_CHAN4_START_SLOT - [5:0] */
1955#define WM8996_AIF1TX_CHAN4_START_SLOT_WIDTH 6 /* AIF1TX_CHAN4_START_SLOT - [5:0] */
1956
1957/*
1958 * R782 (0x30E) - AIF1TX Channel 5 Configuration
1959 */
1960#define WM8996_AIF1TX_CHAN5_DAT_INV 0x8000 /* AIF1TX_CHAN5_DAT_INV */
1961#define WM8996_AIF1TX_CHAN5_DAT_INV_MASK 0x8000 /* AIF1TX_CHAN5_DAT_INV */
1962#define WM8996_AIF1TX_CHAN5_DAT_INV_SHIFT 15 /* AIF1TX_CHAN5_DAT_INV */
1963#define WM8996_AIF1TX_CHAN5_DAT_INV_WIDTH 1 /* AIF1TX_CHAN5_DAT_INV */
1964#define WM8996_AIF1TX_CHAN5_SPACING_MASK 0x7E00 /* AIF1TX_CHAN5_SPACING - [14:9] */
1965#define WM8996_AIF1TX_CHAN5_SPACING_SHIFT 9 /* AIF1TX_CHAN5_SPACING - [14:9] */
1966#define WM8996_AIF1TX_CHAN5_SPACING_WIDTH 6 /* AIF1TX_CHAN5_SPACING - [14:9] */
1967#define WM8996_AIF1TX_CHAN5_SLOTS_MASK 0x01C0 /* AIF1TX_CHAN5_SLOTS - [8:6] */
1968#define WM8996_AIF1TX_CHAN5_SLOTS_SHIFT 6 /* AIF1TX_CHAN5_SLOTS - [8:6] */
1969#define WM8996_AIF1TX_CHAN5_SLOTS_WIDTH 3 /* AIF1TX_CHAN5_SLOTS - [8:6] */
1970#define WM8996_AIF1TX_CHAN5_START_SLOT_MASK 0x003F /* AIF1TX_CHAN5_START_SLOT - [5:0] */
1971#define WM8996_AIF1TX_CHAN5_START_SLOT_SHIFT 0 /* AIF1TX_CHAN5_START_SLOT - [5:0] */
1972#define WM8996_AIF1TX_CHAN5_START_SLOT_WIDTH 6 /* AIF1TX_CHAN5_START_SLOT - [5:0] */
1973
1974/*
1975 * R783 (0x30F) - AIF1RX Channel 0 Configuration
1976 */
1977#define WM8996_AIF1RX_CHAN0_DAT_INV 0x8000 /* AIF1RX_CHAN0_DAT_INV */
1978#define WM8996_AIF1RX_CHAN0_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN0_DAT_INV */
1979#define WM8996_AIF1RX_CHAN0_DAT_INV_SHIFT 15 /* AIF1RX_CHAN0_DAT_INV */
1980#define WM8996_AIF1RX_CHAN0_DAT_INV_WIDTH 1 /* AIF1RX_CHAN0_DAT_INV */
1981#define WM8996_AIF1RX_CHAN0_SPACING_MASK 0x7E00 /* AIF1RX_CHAN0_SPACING - [14:9] */
1982#define WM8996_AIF1RX_CHAN0_SPACING_SHIFT 9 /* AIF1RX_CHAN0_SPACING - [14:9] */
1983#define WM8996_AIF1RX_CHAN0_SPACING_WIDTH 6 /* AIF1RX_CHAN0_SPACING - [14:9] */
1984#define WM8996_AIF1RX_CHAN0_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN0_SLOTS - [8:6] */
1985#define WM8996_AIF1RX_CHAN0_SLOTS_SHIFT 6 /* AIF1RX_CHAN0_SLOTS - [8:6] */
1986#define WM8996_AIF1RX_CHAN0_SLOTS_WIDTH 3 /* AIF1RX_CHAN0_SLOTS - [8:6] */
1987#define WM8996_AIF1RX_CHAN0_START_SLOT_MASK 0x003F /* AIF1RX_CHAN0_START_SLOT - [5:0] */
1988#define WM8996_AIF1RX_CHAN0_START_SLOT_SHIFT 0 /* AIF1RX_CHAN0_START_SLOT - [5:0] */
1989#define WM8996_AIF1RX_CHAN0_START_SLOT_WIDTH 6 /* AIF1RX_CHAN0_START_SLOT - [5:0] */
1990
1991/*
1992 * R784 (0x310) - AIF1RX Channel 1 Configuration
1993 */
1994#define WM8996_AIF1RX_CHAN1_DAT_INV 0x8000 /* AIF1RX_CHAN1_DAT_INV */
1995#define WM8996_AIF1RX_CHAN1_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN1_DAT_INV */
1996#define WM8996_AIF1RX_CHAN1_DAT_INV_SHIFT 15 /* AIF1RX_CHAN1_DAT_INV */
1997#define WM8996_AIF1RX_CHAN1_DAT_INV_WIDTH 1 /* AIF1RX_CHAN1_DAT_INV */
1998#define WM8996_AIF1RX_CHAN1_SPACING_MASK 0x7E00 /* AIF1RX_CHAN1_SPACING - [14:9] */
1999#define WM8996_AIF1RX_CHAN1_SPACING_SHIFT 9 /* AIF1RX_CHAN1_SPACING - [14:9] */
2000#define WM8996_AIF1RX_CHAN1_SPACING_WIDTH 6 /* AIF1RX_CHAN1_SPACING - [14:9] */
2001#define WM8996_AIF1RX_CHAN1_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN1_SLOTS - [8:6] */
2002#define WM8996_AIF1RX_CHAN1_SLOTS_SHIFT 6 /* AIF1RX_CHAN1_SLOTS - [8:6] */
2003#define WM8996_AIF1RX_CHAN1_SLOTS_WIDTH 3 /* AIF1RX_CHAN1_SLOTS - [8:6] */
2004#define WM8996_AIF1RX_CHAN1_START_SLOT_MASK 0x003F /* AIF1RX_CHAN1_START_SLOT - [5:0] */
2005#define WM8996_AIF1RX_CHAN1_START_SLOT_SHIFT 0 /* AIF1RX_CHAN1_START_SLOT - [5:0] */
2006#define WM8996_AIF1RX_CHAN1_START_SLOT_WIDTH 6 /* AIF1RX_CHAN1_START_SLOT - [5:0] */
2007
2008/*
2009 * R785 (0x311) - AIF1RX Channel 2 Configuration
2010 */
2011#define WM8996_AIF1RX_CHAN2_DAT_INV 0x8000 /* AIF1RX_CHAN2_DAT_INV */
2012#define WM8996_AIF1RX_CHAN2_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN2_DAT_INV */
2013#define WM8996_AIF1RX_CHAN2_DAT_INV_SHIFT 15 /* AIF1RX_CHAN2_DAT_INV */
2014#define WM8996_AIF1RX_CHAN2_DAT_INV_WIDTH 1 /* AIF1RX_CHAN2_DAT_INV */
2015#define WM8996_AIF1RX_CHAN2_SPACING_MASK 0x7E00 /* AIF1RX_CHAN2_SPACING - [14:9] */
2016#define WM8996_AIF1RX_CHAN2_SPACING_SHIFT 9 /* AIF1RX_CHAN2_SPACING - [14:9] */
2017#define WM8996_AIF1RX_CHAN2_SPACING_WIDTH 6 /* AIF1RX_CHAN2_SPACING - [14:9] */
2018#define WM8996_AIF1RX_CHAN2_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN2_SLOTS - [8:6] */
2019#define WM8996_AIF1RX_CHAN2_SLOTS_SHIFT 6 /* AIF1RX_CHAN2_SLOTS - [8:6] */
2020#define WM8996_AIF1RX_CHAN2_SLOTS_WIDTH 3 /* AIF1RX_CHAN2_SLOTS - [8:6] */
2021#define WM8996_AIF1RX_CHAN2_START_SLOT_MASK 0x003F /* AIF1RX_CHAN2_START_SLOT - [5:0] */
2022#define WM8996_AIF1RX_CHAN2_START_SLOT_SHIFT 0 /* AIF1RX_CHAN2_START_SLOT - [5:0] */
2023#define WM8996_AIF1RX_CHAN2_START_SLOT_WIDTH 6 /* AIF1RX_CHAN2_START_SLOT - [5:0] */
2024
2025/*
2026 * R786 (0x312) - AIF1RX Channel 3 Configuration
2027 */
2028#define WM8996_AIF1RX_CHAN3_DAT_INV 0x8000 /* AIF1RX_CHAN3_DAT_INV */
2029#define WM8996_AIF1RX_CHAN3_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN3_DAT_INV */
2030#define WM8996_AIF1RX_CHAN3_DAT_INV_SHIFT 15 /* AIF1RX_CHAN3_DAT_INV */
2031#define WM8996_AIF1RX_CHAN3_DAT_INV_WIDTH 1 /* AIF1RX_CHAN3_DAT_INV */
2032#define WM8996_AIF1RX_CHAN3_SPACING_MASK 0x7E00 /* AIF1RX_CHAN3_SPACING - [14:9] */
2033#define WM8996_AIF1RX_CHAN3_SPACING_SHIFT 9 /* AIF1RX_CHAN3_SPACING - [14:9] */
2034#define WM8996_AIF1RX_CHAN3_SPACING_WIDTH 6 /* AIF1RX_CHAN3_SPACING - [14:9] */
2035#define WM8996_AIF1RX_CHAN3_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN3_SLOTS - [8:6] */
2036#define WM8996_AIF1RX_CHAN3_SLOTS_SHIFT 6 /* AIF1RX_CHAN3_SLOTS - [8:6] */
2037#define WM8996_AIF1RX_CHAN3_SLOTS_WIDTH 3 /* AIF1RX_CHAN3_SLOTS - [8:6] */
2038#define WM8996_AIF1RX_CHAN3_START_SLOT_MASK 0x003F /* AIF1RX_CHAN3_START_SLOT - [5:0] */
2039#define WM8996_AIF1RX_CHAN3_START_SLOT_SHIFT 0 /* AIF1RX_CHAN3_START_SLOT - [5:0] */
2040#define WM8996_AIF1RX_CHAN3_START_SLOT_WIDTH 6 /* AIF1RX_CHAN3_START_SLOT - [5:0] */
2041
2042/*
2043 * R787 (0x313) - AIF1RX Channel 4 Configuration
2044 */
2045#define WM8996_AIF1RX_CHAN4_DAT_INV 0x8000 /* AIF1RX_CHAN4_DAT_INV */
2046#define WM8996_AIF1RX_CHAN4_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN4_DAT_INV */
2047#define WM8996_AIF1RX_CHAN4_DAT_INV_SHIFT 15 /* AIF1RX_CHAN4_DAT_INV */
2048#define WM8996_AIF1RX_CHAN4_DAT_INV_WIDTH 1 /* AIF1RX_CHAN4_DAT_INV */
2049#define WM8996_AIF1RX_CHAN4_SPACING_MASK 0x7E00 /* AIF1RX_CHAN4_SPACING - [14:9] */
2050#define WM8996_AIF1RX_CHAN4_SPACING_SHIFT 9 /* AIF1RX_CHAN4_SPACING - [14:9] */
2051#define WM8996_AIF1RX_CHAN4_SPACING_WIDTH 6 /* AIF1RX_CHAN4_SPACING - [14:9] */
2052#define WM8996_AIF1RX_CHAN4_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN4_SLOTS - [8:6] */
2053#define WM8996_AIF1RX_CHAN4_SLOTS_SHIFT 6 /* AIF1RX_CHAN4_SLOTS - [8:6] */
2054#define WM8996_AIF1RX_CHAN4_SLOTS_WIDTH 3 /* AIF1RX_CHAN4_SLOTS - [8:6] */
2055#define WM8996_AIF1RX_CHAN4_START_SLOT_MASK 0x003F /* AIF1RX_CHAN4_START_SLOT - [5:0] */
2056#define WM8996_AIF1RX_CHAN4_START_SLOT_SHIFT 0 /* AIF1RX_CHAN4_START_SLOT - [5:0] */
2057#define WM8996_AIF1RX_CHAN4_START_SLOT_WIDTH 6 /* AIF1RX_CHAN4_START_SLOT - [5:0] */
2058
2059/*
2060 * R788 (0x314) - AIF1RX Channel 5 Configuration
2061 */
2062#define WM8996_AIF1RX_CHAN5_DAT_INV 0x8000 /* AIF1RX_CHAN5_DAT_INV */
2063#define WM8996_AIF1RX_CHAN5_DAT_INV_MASK 0x8000 /* AIF1RX_CHAN5_DAT_INV */
2064#define WM8996_AIF1RX_CHAN5_DAT_INV_SHIFT 15 /* AIF1RX_CHAN5_DAT_INV */
2065#define WM8996_AIF1RX_CHAN5_DAT_INV_WIDTH 1 /* AIF1RX_CHAN5_DAT_INV */
2066#define WM8996_AIF1RX_CHAN5_SPACING_MASK 0x7E00 /* AIF1RX_CHAN5_SPACING - [14:9] */
2067#define WM8996_AIF1RX_CHAN5_SPACING_SHIFT 9 /* AIF1RX_CHAN5_SPACING - [14:9] */
2068#define WM8996_AIF1RX_CHAN5_SPACING_WIDTH 6 /* AIF1RX_CHAN5_SPACING - [14:9] */
2069#define WM8996_AIF1RX_CHAN5_SLOTS_MASK 0x01C0 /* AIF1RX_CHAN5_SLOTS - [8:6] */
2070#define WM8996_AIF1RX_CHAN5_SLOTS_SHIFT 6 /* AIF1RX_CHAN5_SLOTS - [8:6] */
2071#define WM8996_AIF1RX_CHAN5_SLOTS_WIDTH 3 /* AIF1RX_CHAN5_SLOTS - [8:6] */
2072#define WM8996_AIF1RX_CHAN5_START_SLOT_MASK 0x003F /* AIF1RX_CHAN5_START_SLOT - [5:0] */
2073#define WM8996_AIF1RX_CHAN5_START_SLOT_SHIFT 0 /* AIF1RX_CHAN5_START_SLOT - [5:0] */
2074#define WM8996_AIF1RX_CHAN5_START_SLOT_WIDTH 6 /* AIF1RX_CHAN5_START_SLOT - [5:0] */
2075
2076/*
2077 * R789 (0x315) - AIF1RX Mono Configuration
2078 */
2079#define WM8996_AIF1RX_CHAN4_MONO_MODE 0x0004 /* AIF1RX_CHAN4_MONO_MODE */
2080#define WM8996_AIF1RX_CHAN4_MONO_MODE_MASK 0x0004 /* AIF1RX_CHAN4_MONO_MODE */
2081#define WM8996_AIF1RX_CHAN4_MONO_MODE_SHIFT 2 /* AIF1RX_CHAN4_MONO_MODE */
2082#define WM8996_AIF1RX_CHAN4_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN4_MONO_MODE */
2083#define WM8996_AIF1RX_CHAN2_MONO_MODE 0x0002 /* AIF1RX_CHAN2_MONO_MODE */
2084#define WM8996_AIF1RX_CHAN2_MONO_MODE_MASK 0x0002 /* AIF1RX_CHAN2_MONO_MODE */
2085#define WM8996_AIF1RX_CHAN2_MONO_MODE_SHIFT 1 /* AIF1RX_CHAN2_MONO_MODE */
2086#define WM8996_AIF1RX_CHAN2_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN2_MONO_MODE */
2087#define WM8996_AIF1RX_CHAN0_MONO_MODE 0x0001 /* AIF1RX_CHAN0_MONO_MODE */
2088#define WM8996_AIF1RX_CHAN0_MONO_MODE_MASK 0x0001 /* AIF1RX_CHAN0_MONO_MODE */
2089#define WM8996_AIF1RX_CHAN0_MONO_MODE_SHIFT 0 /* AIF1RX_CHAN0_MONO_MODE */
2090#define WM8996_AIF1RX_CHAN0_MONO_MODE_WIDTH 1 /* AIF1RX_CHAN0_MONO_MODE */
2091
2092/*
2093 * R794 (0x31A) - AIF1TX Test
2094 */
2095#define WM8996_AIF1TX45_DITHER_ENA 0x0004 /* AIF1TX45_DITHER_ENA */
2096#define WM8996_AIF1TX45_DITHER_ENA_MASK 0x0004 /* AIF1TX45_DITHER_ENA */
2097#define WM8996_AIF1TX45_DITHER_ENA_SHIFT 2 /* AIF1TX45_DITHER_ENA */
2098#define WM8996_AIF1TX45_DITHER_ENA_WIDTH 1 /* AIF1TX45_DITHER_ENA */
2099#define WM8996_AIF1TX23_DITHER_ENA 0x0002 /* AIF1TX23_DITHER_ENA */
2100#define WM8996_AIF1TX23_DITHER_ENA_MASK 0x0002 /* AIF1TX23_DITHER_ENA */
2101#define WM8996_AIF1TX23_DITHER_ENA_SHIFT 1 /* AIF1TX23_DITHER_ENA */
2102#define WM8996_AIF1TX23_DITHER_ENA_WIDTH 1 /* AIF1TX23_DITHER_ENA */
2103#define WM8996_AIF1TX01_DITHER_ENA 0x0001 /* AIF1TX01_DITHER_ENA */
2104#define WM8996_AIF1TX01_DITHER_ENA_MASK 0x0001 /* AIF1TX01_DITHER_ENA */
2105#define WM8996_AIF1TX01_DITHER_ENA_SHIFT 0 /* AIF1TX01_DITHER_ENA */
2106#define WM8996_AIF1TX01_DITHER_ENA_WIDTH 1 /* AIF1TX01_DITHER_ENA */
2107
2108/*
2109 * R800 (0x320) - AIF2 Control
2110 */
2111#define WM8996_AIF2_TRI 0x0004 /* AIF2_TRI */
2112#define WM8996_AIF2_TRI_MASK 0x0004 /* AIF2_TRI */
2113#define WM8996_AIF2_TRI_SHIFT 2 /* AIF2_TRI */
2114#define WM8996_AIF2_TRI_WIDTH 1 /* AIF2_TRI */
2115#define WM8996_AIF2_FMT_MASK 0x0003 /* AIF2_FMT - [1:0] */
2116#define WM8996_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [1:0] */
2117#define WM8996_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [1:0] */
2118
2119/*
2120 * R801 (0x321) - AIF2 BCLK
2121 */
2122#define WM8996_AIF2_BCLK_INV 0x0400 /* AIF2_BCLK_INV */
2123#define WM8996_AIF2_BCLK_INV_MASK 0x0400 /* AIF2_BCLK_INV */
2124#define WM8996_AIF2_BCLK_INV_SHIFT 10 /* AIF2_BCLK_INV */
2125#define WM8996_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */
2126#define WM8996_AIF2_BCLK_FRC 0x0200 /* AIF2_BCLK_FRC */
2127#define WM8996_AIF2_BCLK_FRC_MASK 0x0200 /* AIF2_BCLK_FRC */
2128#define WM8996_AIF2_BCLK_FRC_SHIFT 9 /* AIF2_BCLK_FRC */
2129#define WM8996_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */
2130#define WM8996_AIF2_BCLK_MSTR 0x0100 /* AIF2_BCLK_MSTR */
2131#define WM8996_AIF2_BCLK_MSTR_MASK 0x0100 /* AIF2_BCLK_MSTR */
2132#define WM8996_AIF2_BCLK_MSTR_SHIFT 8 /* AIF2_BCLK_MSTR */
2133#define WM8996_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */
2134#define WM8996_AIF2_BCLK_DIV_MASK 0x000F /* AIF2_BCLK_DIV - [3:0] */
2135#define WM8996_AIF2_BCLK_DIV_SHIFT 0 /* AIF2_BCLK_DIV - [3:0] */
2136#define WM8996_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [3:0] */
2137
2138/*
2139 * R802 (0x322) - AIF2 TX LRCLK(1)
2140 */
2141#define WM8996_AIF2TX_RATE_MASK 0x07FF /* AIF2TX_RATE - [10:0] */
2142#define WM8996_AIF2TX_RATE_SHIFT 0 /* AIF2TX_RATE - [10:0] */
2143#define WM8996_AIF2TX_RATE_WIDTH 11 /* AIF2TX_RATE - [10:0] */
2144
2145/*
2146 * R803 (0x323) - AIF2 TX LRCLK(2)
2147 */
2148#define WM8996_AIF2TX_LRCLK_MODE 0x0008 /* AIF2TX_LRCLK_MODE */
2149#define WM8996_AIF2TX_LRCLK_MODE_MASK 0x0008 /* AIF2TX_LRCLK_MODE */
2150#define WM8996_AIF2TX_LRCLK_MODE_SHIFT 3 /* AIF2TX_LRCLK_MODE */
2151#define WM8996_AIF2TX_LRCLK_MODE_WIDTH 1 /* AIF2TX_LRCLK_MODE */
2152#define WM8996_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */
2153#define WM8996_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */
2154#define WM8996_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */
2155#define WM8996_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */
2156#define WM8996_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */
2157#define WM8996_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */
2158#define WM8996_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */
2159#define WM8996_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */
2160#define WM8996_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */
2161#define WM8996_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */
2162#define WM8996_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */
2163#define WM8996_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */
2164
2165/*
2166 * R804 (0x324) - AIF2 RX LRCLK(1)
2167 */
2168#define WM8996_AIF2RX_RATE_MASK 0x07FF /* AIF2RX_RATE - [10:0] */
2169#define WM8996_AIF2RX_RATE_SHIFT 0 /* AIF2RX_RATE - [10:0] */
2170#define WM8996_AIF2RX_RATE_WIDTH 11 /* AIF2RX_RATE - [10:0] */
2171
2172/*
2173 * R805 (0x325) - AIF2 RX LRCLK(2)
2174 */
2175#define WM8996_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */
2176#define WM8996_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */
2177#define WM8996_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */
2178#define WM8996_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */
2179#define WM8996_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */
2180#define WM8996_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */
2181#define WM8996_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */
2182#define WM8996_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */
2183#define WM8996_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */
2184#define WM8996_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */
2185#define WM8996_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */
2186#define WM8996_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */
2187
2188/*
2189 * R806 (0x326) - AIF2TX Data Configuration (1)
2190 */
2191#define WM8996_AIF2TX_WL_MASK 0xFF00 /* AIF2TX_WL - [15:8] */
2192#define WM8996_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [15:8] */
2193#define WM8996_AIF2TX_WL_WIDTH 8 /* AIF2TX_WL - [15:8] */
2194#define WM8996_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */
2195#define WM8996_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */
2196#define WM8996_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */
2197
2198/*
2199 * R807 (0x327) - AIF2TX Data Configuration (2)
2200 */
2201#define WM8996_AIF2TX_DAT_TRI 0x0001 /* AIF2TX_DAT_TRI */
2202#define WM8996_AIF2TX_DAT_TRI_MASK 0x0001 /* AIF2TX_DAT_TRI */
2203#define WM8996_AIF2TX_DAT_TRI_SHIFT 0 /* AIF2TX_DAT_TRI */
2204#define WM8996_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */
2205
2206/*
2207 * R808 (0x328) - AIF2RX Data Configuration
2208 */
2209#define WM8996_AIF2RX_WL_MASK 0xFF00 /* AIF2RX_WL - [15:8] */
2210#define WM8996_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [15:8] */
2211#define WM8996_AIF2RX_WL_WIDTH 8 /* AIF2RX_WL - [15:8] */
2212#define WM8996_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */
2213#define WM8996_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */
2214#define WM8996_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */
2215
2216/*
2217 * R809 (0x329) - AIF2TX Channel 0 Configuration
2218 */
2219#define WM8996_AIF2TX_CHAN0_DAT_INV 0x8000 /* AIF2TX_CHAN0_DAT_INV */
2220#define WM8996_AIF2TX_CHAN0_DAT_INV_MASK 0x8000 /* AIF2TX_CHAN0_DAT_INV */
2221#define WM8996_AIF2TX_CHAN0_DAT_INV_SHIFT 15 /* AIF2TX_CHAN0_DAT_INV */
2222#define WM8996_AIF2TX_CHAN0_DAT_INV_WIDTH 1 /* AIF2TX_CHAN0_DAT_INV */
2223#define WM8996_AIF2TX_CHAN0_SPACING_MASK 0x7E00 /* AIF2TX_CHAN0_SPACING - [14:9] */
2224#define WM8996_AIF2TX_CHAN0_SPACING_SHIFT 9 /* AIF2TX_CHAN0_SPACING - [14:9] */
2225#define WM8996_AIF2TX_CHAN0_SPACING_WIDTH 6 /* AIF2TX_CHAN0_SPACING - [14:9] */
2226#define WM8996_AIF2TX_CHAN0_SLOTS_MASK 0x01C0 /* AIF2TX_CHAN0_SLOTS - [8:6] */
2227#define WM8996_AIF2TX_CHAN0_SLOTS_SHIFT 6 /* AIF2TX_CHAN0_SLOTS - [8:6] */
2228#define WM8996_AIF2TX_CHAN0_SLOTS_WIDTH 3 /* AIF2TX_CHAN0_SLOTS - [8:6] */
2229#define WM8996_AIF2TX_CHAN0_START_SLOT_MASK 0x003F /* AIF2TX_CHAN0_START_SLOT - [5:0] */
2230#define WM8996_AIF2TX_CHAN0_START_SLOT_SHIFT 0 /* AIF2TX_CHAN0_START_SLOT - [5:0] */
2231#define WM8996_AIF2TX_CHAN0_START_SLOT_WIDTH 6 /* AIF2TX_CHAN0_START_SLOT - [5:0] */
2232
2233/*
2234 * R810 (0x32A) - AIF2TX Channel 1 Configuration
2235 */
2236#define WM8996_AIF2TX_CHAN1_DAT_INV 0x8000 /* AIF2TX_CHAN1_DAT_INV */
2237#define WM8996_AIF2TX_CHAN1_DAT_INV_MASK 0x8000 /* AIF2TX_CHAN1_DAT_INV */
2238#define WM8996_AIF2TX_CHAN1_DAT_INV_SHIFT 15 /* AIF2TX_CHAN1_DAT_INV */
2239#define WM8996_AIF2TX_CHAN1_DAT_INV_WIDTH 1 /* AIF2TX_CHAN1_DAT_INV */
2240#define WM8996_AIF2TX_CHAN1_SPACING_MASK 0x7E00 /* AIF2TX_CHAN1_SPACING - [14:9] */
2241#define WM8996_AIF2TX_CHAN1_SPACING_SHIFT 9 /* AIF2TX_CHAN1_SPACING - [14:9] */
2242#define WM8996_AIF2TX_CHAN1_SPACING_WIDTH 6 /* AIF2TX_CHAN1_SPACING - [14:9] */
2243#define WM8996_AIF2TX_CHAN1_SLOTS_MASK 0x01C0 /* AIF2TX_CHAN1_SLOTS - [8:6] */
2244#define WM8996_AIF2TX_CHAN1_SLOTS_SHIFT 6 /* AIF2TX_CHAN1_SLOTS - [8:6] */
2245#define WM8996_AIF2TX_CHAN1_SLOTS_WIDTH 3 /* AIF2TX_CHAN1_SLOTS - [8:6] */
2246#define WM8996_AIF2TX_CHAN1_START_SLOT_MASK 0x003F /* AIF2TX_CHAN1_START_SLOT - [5:0] */
2247#define WM8996_AIF2TX_CHAN1_START_SLOT_SHIFT 0 /* AIF2TX_CHAN1_START_SLOT - [5:0] */
2248#define WM8996_AIF2TX_CHAN1_START_SLOT_WIDTH 6 /* AIF2TX_CHAN1_START_SLOT - [5:0] */
2249
2250/*
2251 * R811 (0x32B) - AIF2RX Channel 0 Configuration
2252 */
2253#define WM8996_AIF2RX_CHAN0_DAT_INV 0x8000 /* AIF2RX_CHAN0_DAT_INV */
2254#define WM8996_AIF2RX_CHAN0_DAT_INV_MASK 0x8000 /* AIF2RX_CHAN0_DAT_INV */
2255#define WM8996_AIF2RX_CHAN0_DAT_INV_SHIFT 15 /* AIF2RX_CHAN0_DAT_INV */
2256#define WM8996_AIF2RX_CHAN0_DAT_INV_WIDTH 1 /* AIF2RX_CHAN0_DAT_INV */
2257#define WM8996_AIF2RX_CHAN0_SPACING_MASK 0x7E00 /* AIF2RX_CHAN0_SPACING - [14:9] */
2258#define WM8996_AIF2RX_CHAN0_SPACING_SHIFT 9 /* AIF2RX_CHAN0_SPACING - [14:9] */
2259#define WM8996_AIF2RX_CHAN0_SPACING_WIDTH 6 /* AIF2RX_CHAN0_SPACING - [14:9] */
2260#define WM8996_AIF2RX_CHAN0_SLOTS_MASK 0x01C0 /* AIF2RX_CHAN0_SLOTS - [8:6] */
2261#define WM8996_AIF2RX_CHAN0_SLOTS_SHIFT 6 /* AIF2RX_CHAN0_SLOTS - [8:6] */
2262#define WM8996_AIF2RX_CHAN0_SLOTS_WIDTH 3 /* AIF2RX_CHAN0_SLOTS - [8:6] */
2263#define WM8996_AIF2RX_CHAN0_START_SLOT_MASK 0x003F /* AIF2RX_CHAN0_START_SLOT - [5:0] */
2264#define WM8996_AIF2RX_CHAN0_START_SLOT_SHIFT 0 /* AIF2RX_CHAN0_START_SLOT - [5:0] */
2265#define WM8996_AIF2RX_CHAN0_START_SLOT_WIDTH 6 /* AIF2RX_CHAN0_START_SLOT - [5:0] */
2266
2267/*
2268 * R812 (0x32C) - AIF2RX Channel 1 Configuration
2269 */
2270#define WM8996_AIF2RX_CHAN1_DAT_INV 0x8000 /* AIF2RX_CHAN1_DAT_INV */
2271#define WM8996_AIF2RX_CHAN1_DAT_INV_MASK 0x8000 /* AIF2RX_CHAN1_DAT_INV */
2272#define WM8996_AIF2RX_CHAN1_DAT_INV_SHIFT 15 /* AIF2RX_CHAN1_DAT_INV */
2273#define WM8996_AIF2RX_CHAN1_DAT_INV_WIDTH 1 /* AIF2RX_CHAN1_DAT_INV */
2274#define WM8996_AIF2RX_CHAN1_SPACING_MASK 0x7E00 /* AIF2RX_CHAN1_SPACING - [14:9] */
2275#define WM8996_AIF2RX_CHAN1_SPACING_SHIFT 9 /* AIF2RX_CHAN1_SPACING - [14:9] */
2276#define WM8996_AIF2RX_CHAN1_SPACING_WIDTH 6 /* AIF2RX_CHAN1_SPACING - [14:9] */
2277#define WM8996_AIF2RX_CHAN1_SLOTS_MASK 0x01C0 /* AIF2RX_CHAN1_SLOTS - [8:6] */
2278#define WM8996_AIF2RX_CHAN1_SLOTS_SHIFT 6 /* AIF2RX_CHAN1_SLOTS - [8:6] */
2279#define WM8996_AIF2RX_CHAN1_SLOTS_WIDTH 3 /* AIF2RX_CHAN1_SLOTS - [8:6] */
2280#define WM8996_AIF2RX_CHAN1_START_SLOT_MASK 0x003F /* AIF2RX_CHAN1_START_SLOT - [5:0] */
2281#define WM8996_AIF2RX_CHAN1_START_SLOT_SHIFT 0 /* AIF2RX_CHAN1_START_SLOT - [5:0] */
2282#define WM8996_AIF2RX_CHAN1_START_SLOT_WIDTH 6 /* AIF2RX_CHAN1_START_SLOT - [5:0] */
2283
2284/*
2285 * R813 (0x32D) - AIF2RX Mono Configuration
2286 */
2287#define WM8996_AIF2RX_CHAN0_MONO_MODE 0x0001 /* AIF2RX_CHAN0_MONO_MODE */
2288#define WM8996_AIF2RX_CHAN0_MONO_MODE_MASK 0x0001 /* AIF2RX_CHAN0_MONO_MODE */
2289#define WM8996_AIF2RX_CHAN0_MONO_MODE_SHIFT 0 /* AIF2RX_CHAN0_MONO_MODE */
2290#define WM8996_AIF2RX_CHAN0_MONO_MODE_WIDTH 1 /* AIF2RX_CHAN0_MONO_MODE */
2291
2292/*
2293 * R815 (0x32F) - AIF2TX Test
2294 */
2295#define WM8996_AIF2TX_DITHER_ENA 0x0001 /* AIF2TX_DITHER_ENA */
2296#define WM8996_AIF2TX_DITHER_ENA_MASK 0x0001 /* AIF2TX_DITHER_ENA */
2297#define WM8996_AIF2TX_DITHER_ENA_SHIFT 0 /* AIF2TX_DITHER_ENA */
2298#define WM8996_AIF2TX_DITHER_ENA_WIDTH 1 /* AIF2TX_DITHER_ENA */
2299
2300/*
2301 * R1024 (0x400) - DSP1 TX Left Volume
2302 */
2303#define WM8996_DSP1TX_VU 0x0100 /* DSP1TX_VU */
2304#define WM8996_DSP1TX_VU_MASK 0x0100 /* DSP1TX_VU */
2305#define WM8996_DSP1TX_VU_SHIFT 8 /* DSP1TX_VU */
2306#define WM8996_DSP1TX_VU_WIDTH 1 /* DSP1TX_VU */
2307#define WM8996_DSP1TXL_VOL_MASK 0x00FF /* DSP1TXL_VOL - [7:0] */
2308#define WM8996_DSP1TXL_VOL_SHIFT 0 /* DSP1TXL_VOL - [7:0] */
2309#define WM8996_DSP1TXL_VOL_WIDTH 8 /* DSP1TXL_VOL - [7:0] */
2310
2311/*
2312 * R1025 (0x401) - DSP1 TX Right Volume
2313 */
2314#define WM8996_DSP1TX_VU 0x0100 /* DSP1TX_VU */
2315#define WM8996_DSP1TX_VU_MASK 0x0100 /* DSP1TX_VU */
2316#define WM8996_DSP1TX_VU_SHIFT 8 /* DSP1TX_VU */
2317#define WM8996_DSP1TX_VU_WIDTH 1 /* DSP1TX_VU */
2318#define WM8996_DSP1TXR_VOL_MASK 0x00FF /* DSP1TXR_VOL - [7:0] */
2319#define WM8996_DSP1TXR_VOL_SHIFT 0 /* DSP1TXR_VOL - [7:0] */
2320#define WM8996_DSP1TXR_VOL_WIDTH 8 /* DSP1TXR_VOL - [7:0] */
2321
2322/*
2323 * R1026 (0x402) - DSP1 RX Left Volume
2324 */
2325#define WM8996_DSP1RX_VU 0x0100 /* DSP1RX_VU */
2326#define WM8996_DSP1RX_VU_MASK 0x0100 /* DSP1RX_VU */
2327#define WM8996_DSP1RX_VU_SHIFT 8 /* DSP1RX_VU */
2328#define WM8996_DSP1RX_VU_WIDTH 1 /* DSP1RX_VU */
2329#define WM8996_DSP1RXL_VOL_MASK 0x00FF /* DSP1RXL_VOL - [7:0] */
2330#define WM8996_DSP1RXL_VOL_SHIFT 0 /* DSP1RXL_VOL - [7:0] */
2331#define WM8996_DSP1RXL_VOL_WIDTH 8 /* DSP1RXL_VOL - [7:0] */
2332
2333/*
2334 * R1027 (0x403) - DSP1 RX Right Volume
2335 */
2336#define WM8996_DSP1RX_VU 0x0100 /* DSP1RX_VU */
2337#define WM8996_DSP1RX_VU_MASK 0x0100 /* DSP1RX_VU */
2338#define WM8996_DSP1RX_VU_SHIFT 8 /* DSP1RX_VU */
2339#define WM8996_DSP1RX_VU_WIDTH 1 /* DSP1RX_VU */
2340#define WM8996_DSP1RXR_VOL_MASK 0x00FF /* DSP1RXR_VOL - [7:0] */
2341#define WM8996_DSP1RXR_VOL_SHIFT 0 /* DSP1RXR_VOL - [7:0] */
2342#define WM8996_DSP1RXR_VOL_WIDTH 8 /* DSP1RXR_VOL - [7:0] */
2343
2344/*
2345 * R1040 (0x410) - DSP1 TX Filters
2346 */
2347#define WM8996_DSP1TX_NF 0x2000 /* DSP1TX_NF */
2348#define WM8996_DSP1TX_NF_MASK 0x2000 /* DSP1TX_NF */
2349#define WM8996_DSP1TX_NF_SHIFT 13 /* DSP1TX_NF */
2350#define WM8996_DSP1TX_NF_WIDTH 1 /* DSP1TX_NF */
2351#define WM8996_DSP1TXL_HPF 0x1000 /* DSP1TXL_HPF */
2352#define WM8996_DSP1TXL_HPF_MASK 0x1000 /* DSP1TXL_HPF */
2353#define WM8996_DSP1TXL_HPF_SHIFT 12 /* DSP1TXL_HPF */
2354#define WM8996_DSP1TXL_HPF_WIDTH 1 /* DSP1TXL_HPF */
2355#define WM8996_DSP1TXR_HPF 0x0800 /* DSP1TXR_HPF */
2356#define WM8996_DSP1TXR_HPF_MASK 0x0800 /* DSP1TXR_HPF */
2357#define WM8996_DSP1TXR_HPF_SHIFT 11 /* DSP1TXR_HPF */
2358#define WM8996_DSP1TXR_HPF_WIDTH 1 /* DSP1TXR_HPF */
2359#define WM8996_DSP1TX_HPF_MODE_MASK 0x0018 /* DSP1TX_HPF_MODE - [4:3] */
2360#define WM8996_DSP1TX_HPF_MODE_SHIFT 3 /* DSP1TX_HPF_MODE - [4:3] */
2361#define WM8996_DSP1TX_HPF_MODE_WIDTH 2 /* DSP1TX_HPF_MODE - [4:3] */
2362#define WM8996_DSP1TX_HPF_CUT_MASK 0x0007 /* DSP1TX_HPF_CUT - [2:0] */
2363#define WM8996_DSP1TX_HPF_CUT_SHIFT 0 /* DSP1TX_HPF_CUT - [2:0] */
2364#define WM8996_DSP1TX_HPF_CUT_WIDTH 3 /* DSP1TX_HPF_CUT - [2:0] */
2365
2366/*
2367 * R1056 (0x420) - DSP1 RX Filters (1)
2368 */
2369#define WM8996_DSP1RX_MUTE 0x0200 /* DSP1RX_MUTE */
2370#define WM8996_DSP1RX_MUTE_MASK 0x0200 /* DSP1RX_MUTE */
2371#define WM8996_DSP1RX_MUTE_SHIFT 9 /* DSP1RX_MUTE */
2372#define WM8996_DSP1RX_MUTE_WIDTH 1 /* DSP1RX_MUTE */
2373#define WM8996_DSP1RX_MONO 0x0080 /* DSP1RX_MONO */
2374#define WM8996_DSP1RX_MONO_MASK 0x0080 /* DSP1RX_MONO */
2375#define WM8996_DSP1RX_MONO_SHIFT 7 /* DSP1RX_MONO */
2376#define WM8996_DSP1RX_MONO_WIDTH 1 /* DSP1RX_MONO */
2377#define WM8996_DSP1RX_MUTERATE 0x0020 /* DSP1RX_MUTERATE */
2378#define WM8996_DSP1RX_MUTERATE_MASK 0x0020 /* DSP1RX_MUTERATE */
2379#define WM8996_DSP1RX_MUTERATE_SHIFT 5 /* DSP1RX_MUTERATE */
2380#define WM8996_DSP1RX_MUTERATE_WIDTH 1 /* DSP1RX_MUTERATE */
2381#define WM8996_DSP1RX_UNMUTE_RAMP 0x0010 /* DSP1RX_UNMUTE_RAMP */
2382#define WM8996_DSP1RX_UNMUTE_RAMP_MASK 0x0010 /* DSP1RX_UNMUTE_RAMP */
2383#define WM8996_DSP1RX_UNMUTE_RAMP_SHIFT 4 /* DSP1RX_UNMUTE_RAMP */
2384#define WM8996_DSP1RX_UNMUTE_RAMP_WIDTH 1 /* DSP1RX_UNMUTE_RAMP */
2385
2386/*
2387 * R1057 (0x421) - DSP1 RX Filters (2)
2388 */
2389#define WM8996_DSP1RX_3D_GAIN_MASK 0x3E00 /* DSP1RX_3D_GAIN - [13:9] */
2390#define WM8996_DSP1RX_3D_GAIN_SHIFT 9 /* DSP1RX_3D_GAIN - [13:9] */
2391#define WM8996_DSP1RX_3D_GAIN_WIDTH 5 /* DSP1RX_3D_GAIN - [13:9] */
2392#define WM8996_DSP1RX_3D_ENA 0x0100 /* DSP1RX_3D_ENA */
2393#define WM8996_DSP1RX_3D_ENA_MASK 0x0100 /* DSP1RX_3D_ENA */
2394#define WM8996_DSP1RX_3D_ENA_SHIFT 8 /* DSP1RX_3D_ENA */
2395#define WM8996_DSP1RX_3D_ENA_WIDTH 1 /* DSP1RX_3D_ENA */
2396
2397/*
2398 * R1088 (0x440) - DSP1 DRC (1)
2399 */
2400#define WM8996_DSP1DRC_SIG_DET_RMS_MASK 0xF800 /* DSP1DRC_SIG_DET_RMS - [15:11] */
2401#define WM8996_DSP1DRC_SIG_DET_RMS_SHIFT 11 /* DSP1DRC_SIG_DET_RMS - [15:11] */
2402#define WM8996_DSP1DRC_SIG_DET_RMS_WIDTH 5 /* DSP1DRC_SIG_DET_RMS - [15:11] */
2403#define WM8996_DSP1DRC_SIG_DET_PK_MASK 0x0600 /* DSP1DRC_SIG_DET_PK - [10:9] */
2404#define WM8996_DSP1DRC_SIG_DET_PK_SHIFT 9 /* DSP1DRC_SIG_DET_PK - [10:9] */
2405#define WM8996_DSP1DRC_SIG_DET_PK_WIDTH 2 /* DSP1DRC_SIG_DET_PK - [10:9] */
2406#define WM8996_DSP1DRC_NG_ENA 0x0100 /* DSP1DRC_NG_ENA */
2407#define WM8996_DSP1DRC_NG_ENA_MASK 0x0100 /* DSP1DRC_NG_ENA */
2408#define WM8996_DSP1DRC_NG_ENA_SHIFT 8 /* DSP1DRC_NG_ENA */
2409#define WM8996_DSP1DRC_NG_ENA_WIDTH 1 /* DSP1DRC_NG_ENA */
2410#define WM8996_DSP1DRC_SIG_DET_MODE 0x0080 /* DSP1DRC_SIG_DET_MODE */
2411#define WM8996_DSP1DRC_SIG_DET_MODE_MASK 0x0080 /* DSP1DRC_SIG_DET_MODE */
2412#define WM8996_DSP1DRC_SIG_DET_MODE_SHIFT 7 /* DSP1DRC_SIG_DET_MODE */
2413#define WM8996_DSP1DRC_SIG_DET_MODE_WIDTH 1 /* DSP1DRC_SIG_DET_MODE */
2414#define WM8996_DSP1DRC_SIG_DET 0x0040 /* DSP1DRC_SIG_DET */
2415#define WM8996_DSP1DRC_SIG_DET_MASK 0x0040 /* DSP1DRC_SIG_DET */
2416#define WM8996_DSP1DRC_SIG_DET_SHIFT 6 /* DSP1DRC_SIG_DET */
2417#define WM8996_DSP1DRC_SIG_DET_WIDTH 1 /* DSP1DRC_SIG_DET */
2418#define WM8996_DSP1DRC_KNEE2_OP_ENA 0x0020 /* DSP1DRC_KNEE2_OP_ENA */
2419#define WM8996_DSP1DRC_KNEE2_OP_ENA_MASK 0x0020 /* DSP1DRC_KNEE2_OP_ENA */
2420#define WM8996_DSP1DRC_KNEE2_OP_ENA_SHIFT 5 /* DSP1DRC_KNEE2_OP_ENA */
2421#define WM8996_DSP1DRC_KNEE2_OP_ENA_WIDTH 1 /* DSP1DRC_KNEE2_OP_ENA */
2422#define WM8996_DSP1DRC_QR 0x0010 /* DSP1DRC_QR */
2423#define WM8996_DSP1DRC_QR_MASK 0x0010 /* DSP1DRC_QR */
2424#define WM8996_DSP1DRC_QR_SHIFT 4 /* DSP1DRC_QR */
2425#define WM8996_DSP1DRC_QR_WIDTH 1 /* DSP1DRC_QR */
2426#define WM8996_DSP1DRC_ANTICLIP 0x0008 /* DSP1DRC_ANTICLIP */
2427#define WM8996_DSP1DRC_ANTICLIP_MASK 0x0008 /* DSP1DRC_ANTICLIP */
2428#define WM8996_DSP1DRC_ANTICLIP_SHIFT 3 /* DSP1DRC_ANTICLIP */
2429#define WM8996_DSP1DRC_ANTICLIP_WIDTH 1 /* DSP1DRC_ANTICLIP */
2430#define WM8996_DSP1RX_DRC_ENA 0x0004 /* DSP1RX_DRC_ENA */
2431#define WM8996_DSP1RX_DRC_ENA_MASK 0x0004 /* DSP1RX_DRC_ENA */
2432#define WM8996_DSP1RX_DRC_ENA_SHIFT 2 /* DSP1RX_DRC_ENA */
2433#define WM8996_DSP1RX_DRC_ENA_WIDTH 1 /* DSP1RX_DRC_ENA */
2434#define WM8996_DSP1TXL_DRC_ENA 0x0002 /* DSP1TXL_DRC_ENA */
2435#define WM8996_DSP1TXL_DRC_ENA_MASK 0x0002 /* DSP1TXL_DRC_ENA */
2436#define WM8996_DSP1TXL_DRC_ENA_SHIFT 1 /* DSP1TXL_DRC_ENA */
2437#define WM8996_DSP1TXL_DRC_ENA_WIDTH 1 /* DSP1TXL_DRC_ENA */
2438#define WM8996_DSP1TXR_DRC_ENA 0x0001 /* DSP1TXR_DRC_ENA */
2439#define WM8996_DSP1TXR_DRC_ENA_MASK 0x0001 /* DSP1TXR_DRC_ENA */
2440#define WM8996_DSP1TXR_DRC_ENA_SHIFT 0 /* DSP1TXR_DRC_ENA */
2441#define WM8996_DSP1TXR_DRC_ENA_WIDTH 1 /* DSP1TXR_DRC_ENA */
2442
2443/*
2444 * R1089 (0x441) - DSP1 DRC (2)
2445 */
2446#define WM8996_DSP1DRC_ATK_MASK 0x1E00 /* DSP1DRC_ATK - [12:9] */
2447#define WM8996_DSP1DRC_ATK_SHIFT 9 /* DSP1DRC_ATK - [12:9] */
2448#define WM8996_DSP1DRC_ATK_WIDTH 4 /* DSP1DRC_ATK - [12:9] */
2449#define WM8996_DSP1DRC_DCY_MASK 0x01E0 /* DSP1DRC_DCY - [8:5] */
2450#define WM8996_DSP1DRC_DCY_SHIFT 5 /* DSP1DRC_DCY - [8:5] */
2451#define WM8996_DSP1DRC_DCY_WIDTH 4 /* DSP1DRC_DCY - [8:5] */
2452#define WM8996_DSP1DRC_MINGAIN_MASK 0x001C /* DSP1DRC_MINGAIN - [4:2] */
2453#define WM8996_DSP1DRC_MINGAIN_SHIFT 2 /* DSP1DRC_MINGAIN - [4:2] */
2454#define WM8996_DSP1DRC_MINGAIN_WIDTH 3 /* DSP1DRC_MINGAIN - [4:2] */
2455#define WM8996_DSP1DRC_MAXGAIN_MASK 0x0003 /* DSP1DRC_MAXGAIN - [1:0] */
2456#define WM8996_DSP1DRC_MAXGAIN_SHIFT 0 /* DSP1DRC_MAXGAIN - [1:0] */
2457#define WM8996_DSP1DRC_MAXGAIN_WIDTH 2 /* DSP1DRC_MAXGAIN - [1:0] */
2458
2459/*
2460 * R1090 (0x442) - DSP1 DRC (3)
2461 */
2462#define WM8996_DSP1DRC_NG_MINGAIN_MASK 0xF000 /* DSP1DRC_NG_MINGAIN - [15:12] */
2463#define WM8996_DSP1DRC_NG_MINGAIN_SHIFT 12 /* DSP1DRC_NG_MINGAIN - [15:12] */
2464#define WM8996_DSP1DRC_NG_MINGAIN_WIDTH 4 /* DSP1DRC_NG_MINGAIN - [15:12] */
2465#define WM8996_DSP1DRC_NG_EXP_MASK 0x0C00 /* DSP1DRC_NG_EXP - [11:10] */
2466#define WM8996_DSP1DRC_NG_EXP_SHIFT 10 /* DSP1DRC_NG_EXP - [11:10] */
2467#define WM8996_DSP1DRC_NG_EXP_WIDTH 2 /* DSP1DRC_NG_EXP - [11:10] */
2468#define WM8996_DSP1DRC_QR_THR_MASK 0x0300 /* DSP1DRC_QR_THR - [9:8] */
2469#define WM8996_DSP1DRC_QR_THR_SHIFT 8 /* DSP1DRC_QR_THR - [9:8] */
2470#define WM8996_DSP1DRC_QR_THR_WIDTH 2 /* DSP1DRC_QR_THR - [9:8] */
2471#define WM8996_DSP1DRC_QR_DCY_MASK 0x00C0 /* DSP1DRC_QR_DCY - [7:6] */
2472#define WM8996_DSP1DRC_QR_DCY_SHIFT 6 /* DSP1DRC_QR_DCY - [7:6] */
2473#define WM8996_DSP1DRC_QR_DCY_WIDTH 2 /* DSP1DRC_QR_DCY - [7:6] */
2474#define WM8996_DSP1DRC_HI_COMP_MASK 0x0038 /* DSP1DRC_HI_COMP - [5:3] */
2475#define WM8996_DSP1DRC_HI_COMP_SHIFT 3 /* DSP1DRC_HI_COMP - [5:3] */
2476#define WM8996_DSP1DRC_HI_COMP_WIDTH 3 /* DSP1DRC_HI_COMP - [5:3] */
2477#define WM8996_DSP1DRC_LO_COMP_MASK 0x0007 /* DSP1DRC_LO_COMP - [2:0] */
2478#define WM8996_DSP1DRC_LO_COMP_SHIFT 0 /* DSP1DRC_LO_COMP - [2:0] */
2479#define WM8996_DSP1DRC_LO_COMP_WIDTH 3 /* DSP1DRC_LO_COMP - [2:0] */
2480
2481/*
2482 * R1091 (0x443) - DSP1 DRC (4)
2483 */
2484#define WM8996_DSP1DRC_KNEE_IP_MASK 0x07E0 /* DSP1DRC_KNEE_IP - [10:5] */
2485#define WM8996_DSP1DRC_KNEE_IP_SHIFT 5 /* DSP1DRC_KNEE_IP - [10:5] */
2486#define WM8996_DSP1DRC_KNEE_IP_WIDTH 6 /* DSP1DRC_KNEE_IP - [10:5] */
2487#define WM8996_DSP1DRC_KNEE_OP_MASK 0x001F /* DSP1DRC_KNEE_OP - [4:0] */
2488#define WM8996_DSP1DRC_KNEE_OP_SHIFT 0 /* DSP1DRC_KNEE_OP - [4:0] */
2489#define WM8996_DSP1DRC_KNEE_OP_WIDTH 5 /* DSP1DRC_KNEE_OP - [4:0] */
2490
2491/*
2492 * R1092 (0x444) - DSP1 DRC (5)
2493 */
2494#define WM8996_DSP1DRC_KNEE2_IP_MASK 0x03E0 /* DSP1DRC_KNEE2_IP - [9:5] */
2495#define WM8996_DSP1DRC_KNEE2_IP_SHIFT 5 /* DSP1DRC_KNEE2_IP - [9:5] */
2496#define WM8996_DSP1DRC_KNEE2_IP_WIDTH 5 /* DSP1DRC_KNEE2_IP - [9:5] */
2497#define WM8996_DSP1DRC_KNEE2_OP_MASK 0x001F /* DSP1DRC_KNEE2_OP - [4:0] */
2498#define WM8996_DSP1DRC_KNEE2_OP_SHIFT 0 /* DSP1DRC_KNEE2_OP - [4:0] */
2499#define WM8996_DSP1DRC_KNEE2_OP_WIDTH 5 /* DSP1DRC_KNEE2_OP - [4:0] */
2500
2501/*
2502 * R1152 (0x480) - DSP1 RX EQ Gains (1)
2503 */
2504#define WM8996_DSP1RX_EQ_B1_GAIN_MASK 0xF800 /* DSP1RX_EQ_B1_GAIN - [15:11] */
2505#define WM8996_DSP1RX_EQ_B1_GAIN_SHIFT 11 /* DSP1RX_EQ_B1_GAIN - [15:11] */
2506#define WM8996_DSP1RX_EQ_B1_GAIN_WIDTH 5 /* DSP1RX_EQ_B1_GAIN - [15:11] */
2507#define WM8996_DSP1RX_EQ_B2_GAIN_MASK 0x07C0 /* DSP1RX_EQ_B2_GAIN - [10:6] */
2508#define WM8996_DSP1RX_EQ_B2_GAIN_SHIFT 6 /* DSP1RX_EQ_B2_GAIN - [10:6] */
2509#define WM8996_DSP1RX_EQ_B2_GAIN_WIDTH 5 /* DSP1RX_EQ_B2_GAIN - [10:6] */
2510#define WM8996_DSP1RX_EQ_B3_GAIN_MASK 0x003E /* DSP1RX_EQ_B3_GAIN - [5:1] */
2511#define WM8996_DSP1RX_EQ_B3_GAIN_SHIFT 1 /* DSP1RX_EQ_B3_GAIN - [5:1] */
2512#define WM8996_DSP1RX_EQ_B3_GAIN_WIDTH 5 /* DSP1RX_EQ_B3_GAIN - [5:1] */
2513#define WM8996_DSP1RX_EQ_ENA 0x0001 /* DSP1RX_EQ_ENA */
2514#define WM8996_DSP1RX_EQ_ENA_MASK 0x0001 /* DSP1RX_EQ_ENA */
2515#define WM8996_DSP1RX_EQ_ENA_SHIFT 0 /* DSP1RX_EQ_ENA */
2516#define WM8996_DSP1RX_EQ_ENA_WIDTH 1 /* DSP1RX_EQ_ENA */
2517
2518/*
2519 * R1153 (0x481) - DSP1 RX EQ Gains (2)
2520 */
2521#define WM8996_DSP1RX_EQ_B4_GAIN_MASK 0xF800 /* DSP1RX_EQ_B4_GAIN - [15:11] */
2522#define WM8996_DSP1RX_EQ_B4_GAIN_SHIFT 11 /* DSP1RX_EQ_B4_GAIN - [15:11] */
2523#define WM8996_DSP1RX_EQ_B4_GAIN_WIDTH 5 /* DSP1RX_EQ_B4_GAIN - [15:11] */
2524#define WM8996_DSP1RX_EQ_B5_GAIN_MASK 0x07C0 /* DSP1RX_EQ_B5_GAIN - [10:6] */
2525#define WM8996_DSP1RX_EQ_B5_GAIN_SHIFT 6 /* DSP1RX_EQ_B5_GAIN - [10:6] */
2526#define WM8996_DSP1RX_EQ_B5_GAIN_WIDTH 5 /* DSP1RX_EQ_B5_GAIN - [10:6] */
2527
2528/*
2529 * R1154 (0x482) - DSP1 RX EQ Band 1 A
2530 */
2531#define WM8996_DSP1RX_EQ_B1_A_MASK 0xFFFF /* DSP1RX_EQ_B1_A - [15:0] */
2532#define WM8996_DSP1RX_EQ_B1_A_SHIFT 0 /* DSP1RX_EQ_B1_A - [15:0] */
2533#define WM8996_DSP1RX_EQ_B1_A_WIDTH 16 /* DSP1RX_EQ_B1_A - [15:0] */
2534
2535/*
2536 * R1155 (0x483) - DSP1 RX EQ Band 1 B
2537 */
2538#define WM8996_DSP1RX_EQ_B1_B_MASK 0xFFFF /* DSP1RX_EQ_B1_B - [15:0] */
2539#define WM8996_DSP1RX_EQ_B1_B_SHIFT 0 /* DSP1RX_EQ_B1_B - [15:0] */
2540#define WM8996_DSP1RX_EQ_B1_B_WIDTH 16 /* DSP1RX_EQ_B1_B - [15:0] */
2541
2542/*
2543 * R1156 (0x484) - DSP1 RX EQ Band 1 PG
2544 */
2545#define WM8996_DSP1RX_EQ_B1_PG_MASK 0xFFFF /* DSP1RX_EQ_B1_PG - [15:0] */
2546#define WM8996_DSP1RX_EQ_B1_PG_SHIFT 0 /* DSP1RX_EQ_B1_PG - [15:0] */
2547#define WM8996_DSP1RX_EQ_B1_PG_WIDTH 16 /* DSP1RX_EQ_B1_PG - [15:0] */
2548
2549/*
2550 * R1157 (0x485) - DSP1 RX EQ Band 2 A
2551 */
2552#define WM8996_DSP1RX_EQ_B2_A_MASK 0xFFFF /* DSP1RX_EQ_B2_A - [15:0] */
2553#define WM8996_DSP1RX_EQ_B2_A_SHIFT 0 /* DSP1RX_EQ_B2_A - [15:0] */
2554#define WM8996_DSP1RX_EQ_B2_A_WIDTH 16 /* DSP1RX_EQ_B2_A - [15:0] */
2555
2556/*
2557 * R1158 (0x486) - DSP1 RX EQ Band 2 B
2558 */
2559#define WM8996_DSP1RX_EQ_B2_B_MASK 0xFFFF /* DSP1RX_EQ_B2_B - [15:0] */
2560#define WM8996_DSP1RX_EQ_B2_B_SHIFT 0 /* DSP1RX_EQ_B2_B - [15:0] */
2561#define WM8996_DSP1RX_EQ_B2_B_WIDTH 16 /* DSP1RX_EQ_B2_B - [15:0] */
2562
2563/*
2564 * R1159 (0x487) - DSP1 RX EQ Band 2 C
2565 */
2566#define WM8996_DSP1RX_EQ_B2_C_MASK 0xFFFF /* DSP1RX_EQ_B2_C - [15:0] */
2567#define WM8996_DSP1RX_EQ_B2_C_SHIFT 0 /* DSP1RX_EQ_B2_C - [15:0] */
2568#define WM8996_DSP1RX_EQ_B2_C_WIDTH 16 /* DSP1RX_EQ_B2_C - [15:0] */
2569
2570/*
2571 * R1160 (0x488) - DSP1 RX EQ Band 2 PG
2572 */
2573#define WM8996_DSP1RX_EQ_B2_PG_MASK 0xFFFF /* DSP1RX_EQ_B2_PG - [15:0] */
2574#define WM8996_DSP1RX_EQ_B2_PG_SHIFT 0 /* DSP1RX_EQ_B2_PG - [15:0] */
2575#define WM8996_DSP1RX_EQ_B2_PG_WIDTH 16 /* DSP1RX_EQ_B2_PG - [15:0] */
2576
2577/*
2578 * R1161 (0x489) - DSP1 RX EQ Band 3 A
2579 */
2580#define WM8996_DSP1RX_EQ_B3_A_MASK 0xFFFF /* DSP1RX_EQ_B3_A - [15:0] */
2581#define WM8996_DSP1RX_EQ_B3_A_SHIFT 0 /* DSP1RX_EQ_B3_A - [15:0] */
2582#define WM8996_DSP1RX_EQ_B3_A_WIDTH 16 /* DSP1RX_EQ_B3_A - [15:0] */
2583
2584/*
2585 * R1162 (0x48A) - DSP1 RX EQ Band 3 B
2586 */
2587#define WM8996_DSP1RX_EQ_B3_B_MASK 0xFFFF /* DSP1RX_EQ_B3_B - [15:0] */
2588#define WM8996_DSP1RX_EQ_B3_B_SHIFT 0 /* DSP1RX_EQ_B3_B - [15:0] */
2589#define WM8996_DSP1RX_EQ_B3_B_WIDTH 16 /* DSP1RX_EQ_B3_B - [15:0] */
2590
2591/*
2592 * R1163 (0x48B) - DSP1 RX EQ Band 3 C
2593 */
2594#define WM8996_DSP1RX_EQ_B3_C_MASK 0xFFFF /* DSP1RX_EQ_B3_C - [15:0] */
2595#define WM8996_DSP1RX_EQ_B3_C_SHIFT 0 /* DSP1RX_EQ_B3_C - [15:0] */
2596#define WM8996_DSP1RX_EQ_B3_C_WIDTH 16 /* DSP1RX_EQ_B3_C - [15:0] */
2597
2598/*
2599 * R1164 (0x48C) - DSP1 RX EQ Band 3 PG
2600 */
2601#define WM8996_DSP1RX_EQ_B3_PG_MASK 0xFFFF /* DSP1RX_EQ_B3_PG - [15:0] */
2602#define WM8996_DSP1RX_EQ_B3_PG_SHIFT 0 /* DSP1RX_EQ_B3_PG - [15:0] */
2603#define WM8996_DSP1RX_EQ_B3_PG_WIDTH 16 /* DSP1RX_EQ_B3_PG - [15:0] */
2604
2605/*
2606 * R1165 (0x48D) - DSP1 RX EQ Band 4 A
2607 */
2608#define WM8996_DSP1RX_EQ_B4_A_MASK 0xFFFF /* DSP1RX_EQ_B4_A - [15:0] */
2609#define WM8996_DSP1RX_EQ_B4_A_SHIFT 0 /* DSP1RX_EQ_B4_A - [15:0] */
2610#define WM8996_DSP1RX_EQ_B4_A_WIDTH 16 /* DSP1RX_EQ_B4_A - [15:0] */
2611
2612/*
2613 * R1166 (0x48E) - DSP1 RX EQ Band 4 B
2614 */
2615#define WM8996_DSP1RX_EQ_B4_B_MASK 0xFFFF /* DSP1RX_EQ_B4_B - [15:0] */
2616#define WM8996_DSP1RX_EQ_B4_B_SHIFT 0 /* DSP1RX_EQ_B4_B - [15:0] */
2617#define WM8996_DSP1RX_EQ_B4_B_WIDTH 16 /* DSP1RX_EQ_B4_B - [15:0] */
2618
2619/*
2620 * R1167 (0x48F) - DSP1 RX EQ Band 4 C
2621 */
2622#define WM8996_DSP1RX_EQ_B4_C_MASK 0xFFFF /* DSP1RX_EQ_B4_C - [15:0] */
2623#define WM8996_DSP1RX_EQ_B4_C_SHIFT 0 /* DSP1RX_EQ_B4_C - [15:0] */
2624#define WM8996_DSP1RX_EQ_B4_C_WIDTH 16 /* DSP1RX_EQ_B4_C - [15:0] */
2625
2626/*
2627 * R1168 (0x490) - DSP1 RX EQ Band 4 PG
2628 */
2629#define WM8996_DSP1RX_EQ_B4_PG_MASK 0xFFFF /* DSP1RX_EQ_B4_PG - [15:0] */
2630#define WM8996_DSP1RX_EQ_B4_PG_SHIFT 0 /* DSP1RX_EQ_B4_PG - [15:0] */
2631#define WM8996_DSP1RX_EQ_B4_PG_WIDTH 16 /* DSP1RX_EQ_B4_PG - [15:0] */
2632
2633/*
2634 * R1169 (0x491) - DSP1 RX EQ Band 5 A
2635 */
2636#define WM8996_DSP1RX_EQ_B5_A_MASK 0xFFFF /* DSP1RX_EQ_B5_A - [15:0] */
2637#define WM8996_DSP1RX_EQ_B5_A_SHIFT 0 /* DSP1RX_EQ_B5_A - [15:0] */
2638#define WM8996_DSP1RX_EQ_B5_A_WIDTH 16 /* DSP1RX_EQ_B5_A - [15:0] */
2639
2640/*
2641 * R1170 (0x492) - DSP1 RX EQ Band 5 B
2642 */
2643#define WM8996_DSP1RX_EQ_B5_B_MASK 0xFFFF /* DSP1RX_EQ_B5_B - [15:0] */
2644#define WM8996_DSP1RX_EQ_B5_B_SHIFT 0 /* DSP1RX_EQ_B5_B - [15:0] */
2645#define WM8996_DSP1RX_EQ_B5_B_WIDTH 16 /* DSP1RX_EQ_B5_B - [15:0] */
2646
2647/*
2648 * R1171 (0x493) - DSP1 RX EQ Band 5 PG
2649 */
2650#define WM8996_DSP1RX_EQ_B5_PG_MASK 0xFFFF /* DSP1RX_EQ_B5_PG - [15:0] */
2651#define WM8996_DSP1RX_EQ_B5_PG_SHIFT 0 /* DSP1RX_EQ_B5_PG - [15:0] */
2652#define WM8996_DSP1RX_EQ_B5_PG_WIDTH 16 /* DSP1RX_EQ_B5_PG - [15:0] */
2653
2654/*
2655 * R1280 (0x500) - DSP2 TX Left Volume
2656 */
2657#define WM8996_DSP2TX_VU 0x0100 /* DSP2TX_VU */
2658#define WM8996_DSP2TX_VU_MASK 0x0100 /* DSP2TX_VU */
2659#define WM8996_DSP2TX_VU_SHIFT 8 /* DSP2TX_VU */
2660#define WM8996_DSP2TX_VU_WIDTH 1 /* DSP2TX_VU */
2661#define WM8996_DSP2TXL_VOL_MASK 0x00FF /* DSP2TXL_VOL - [7:0] */
2662#define WM8996_DSP2TXL_VOL_SHIFT 0 /* DSP2TXL_VOL - [7:0] */
2663#define WM8996_DSP2TXL_VOL_WIDTH 8 /* DSP2TXL_VOL - [7:0] */
2664
2665/*
2666 * R1281 (0x501) - DSP2 TX Right Volume
2667 */
2668#define WM8996_DSP2TX_VU 0x0100 /* DSP2TX_VU */
2669#define WM8996_DSP2TX_VU_MASK 0x0100 /* DSP2TX_VU */
2670#define WM8996_DSP2TX_VU_SHIFT 8 /* DSP2TX_VU */
2671#define WM8996_DSP2TX_VU_WIDTH 1 /* DSP2TX_VU */
2672#define WM8996_DSP2TXR_VOL_MASK 0x00FF /* DSP2TXR_VOL - [7:0] */
2673#define WM8996_DSP2TXR_VOL_SHIFT 0 /* DSP2TXR_VOL - [7:0] */
2674#define WM8996_DSP2TXR_VOL_WIDTH 8 /* DSP2TXR_VOL - [7:0] */
2675
2676/*
2677 * R1282 (0x502) - DSP2 RX Left Volume
2678 */
2679#define WM8996_DSP2RX_VU 0x0100 /* DSP2RX_VU */
2680#define WM8996_DSP2RX_VU_MASK 0x0100 /* DSP2RX_VU */
2681#define WM8996_DSP2RX_VU_SHIFT 8 /* DSP2RX_VU */
2682#define WM8996_DSP2RX_VU_WIDTH 1 /* DSP2RX_VU */
2683#define WM8996_DSP2RXL_VOL_MASK 0x00FF /* DSP2RXL_VOL - [7:0] */
2684#define WM8996_DSP2RXL_VOL_SHIFT 0 /* DSP2RXL_VOL - [7:0] */
2685#define WM8996_DSP2RXL_VOL_WIDTH 8 /* DSP2RXL_VOL - [7:0] */
2686
2687/*
2688 * R1283 (0x503) - DSP2 RX Right Volume
2689 */
2690#define WM8996_DSP2RX_VU 0x0100 /* DSP2RX_VU */
2691#define WM8996_DSP2RX_VU_MASK 0x0100 /* DSP2RX_VU */
2692#define WM8996_DSP2RX_VU_SHIFT 8 /* DSP2RX_VU */
2693#define WM8996_DSP2RX_VU_WIDTH 1 /* DSP2RX_VU */
2694#define WM8996_DSP2RXR_VOL_MASK 0x00FF /* DSP2RXR_VOL - [7:0] */
2695#define WM8996_DSP2RXR_VOL_SHIFT 0 /* DSP2RXR_VOL - [7:0] */
2696#define WM8996_DSP2RXR_VOL_WIDTH 8 /* DSP2RXR_VOL - [7:0] */
2697
2698/*
2699 * R1296 (0x510) - DSP2 TX Filters
2700 */
2701#define WM8996_DSP2TX_NF 0x2000 /* DSP2TX_NF */
2702#define WM8996_DSP2TX_NF_MASK 0x2000 /* DSP2TX_NF */
2703#define WM8996_DSP2TX_NF_SHIFT 13 /* DSP2TX_NF */
2704#define WM8996_DSP2TX_NF_WIDTH 1 /* DSP2TX_NF */
2705#define WM8996_DSP2TXL_HPF 0x1000 /* DSP2TXL_HPF */
2706#define WM8996_DSP2TXL_HPF_MASK 0x1000 /* DSP2TXL_HPF */
2707#define WM8996_DSP2TXL_HPF_SHIFT 12 /* DSP2TXL_HPF */
2708#define WM8996_DSP2TXL_HPF_WIDTH 1 /* DSP2TXL_HPF */
2709#define WM8996_DSP2TXR_HPF 0x0800 /* DSP2TXR_HPF */
2710#define WM8996_DSP2TXR_HPF_MASK 0x0800 /* DSP2TXR_HPF */
2711#define WM8996_DSP2TXR_HPF_SHIFT 11 /* DSP2TXR_HPF */
2712#define WM8996_DSP2TXR_HPF_WIDTH 1 /* DSP2TXR_HPF */
2713#define WM8996_DSP2TX_HPF_MODE_MASK 0x0018 /* DSP2TX_HPF_MODE - [4:3] */
2714#define WM8996_DSP2TX_HPF_MODE_SHIFT 3 /* DSP2TX_HPF_MODE - [4:3] */
2715#define WM8996_DSP2TX_HPF_MODE_WIDTH 2 /* DSP2TX_HPF_MODE - [4:3] */
2716#define WM8996_DSP2TX_HPF_CUT_MASK 0x0007 /* DSP2TX_HPF_CUT - [2:0] */
2717#define WM8996_DSP2TX_HPF_CUT_SHIFT 0 /* DSP2TX_HPF_CUT - [2:0] */
2718#define WM8996_DSP2TX_HPF_CUT_WIDTH 3 /* DSP2TX_HPF_CUT - [2:0] */
2719
2720/*
2721 * R1312 (0x520) - DSP2 RX Filters (1)
2722 */
2723#define WM8996_DSP2RX_MUTE 0x0200 /* DSP2RX_MUTE */
2724#define WM8996_DSP2RX_MUTE_MASK 0x0200 /* DSP2RX_MUTE */
2725#define WM8996_DSP2RX_MUTE_SHIFT 9 /* DSP2RX_MUTE */
2726#define WM8996_DSP2RX_MUTE_WIDTH 1 /* DSP2RX_MUTE */
2727#define WM8996_DSP2RX_MONO 0x0080 /* DSP2RX_MONO */
2728#define WM8996_DSP2RX_MONO_MASK 0x0080 /* DSP2RX_MONO */
2729#define WM8996_DSP2RX_MONO_SHIFT 7 /* DSP2RX_MONO */
2730#define WM8996_DSP2RX_MONO_WIDTH 1 /* DSP2RX_MONO */
2731#define WM8996_DSP2RX_MUTERATE 0x0020 /* DSP2RX_MUTERATE */
2732#define WM8996_DSP2RX_MUTERATE_MASK 0x0020 /* DSP2RX_MUTERATE */
2733#define WM8996_DSP2RX_MUTERATE_SHIFT 5 /* DSP2RX_MUTERATE */
2734#define WM8996_DSP2RX_MUTERATE_WIDTH 1 /* DSP2RX_MUTERATE */
2735#define WM8996_DSP2RX_UNMUTE_RAMP 0x0010 /* DSP2RX_UNMUTE_RAMP */
2736#define WM8996_DSP2RX_UNMUTE_RAMP_MASK 0x0010 /* DSP2RX_UNMUTE_RAMP */
2737#define WM8996_DSP2RX_UNMUTE_RAMP_SHIFT 4 /* DSP2RX_UNMUTE_RAMP */
2738#define WM8996_DSP2RX_UNMUTE_RAMP_WIDTH 1 /* DSP2RX_UNMUTE_RAMP */
2739
2740/*
2741 * R1313 (0x521) - DSP2 RX Filters (2)
2742 */
2743#define WM8996_DSP2RX_3D_GAIN_MASK 0x3E00 /* DSP2RX_3D_GAIN - [13:9] */
2744#define WM8996_DSP2RX_3D_GAIN_SHIFT 9 /* DSP2RX_3D_GAIN - [13:9] */
2745#define WM8996_DSP2RX_3D_GAIN_WIDTH 5 /* DSP2RX_3D_GAIN - [13:9] */
2746#define WM8996_DSP2RX_3D_ENA 0x0100 /* DSP2RX_3D_ENA */
2747#define WM8996_DSP2RX_3D_ENA_MASK 0x0100 /* DSP2RX_3D_ENA */
2748#define WM8996_DSP2RX_3D_ENA_SHIFT 8 /* DSP2RX_3D_ENA */
2749#define WM8996_DSP2RX_3D_ENA_WIDTH 1 /* DSP2RX_3D_ENA */
2750
2751/*
2752 * R1344 (0x540) - DSP2 DRC (1)
2753 */
2754#define WM8996_DSP2DRC_SIG_DET_RMS_MASK 0xF800 /* DSP2DRC_SIG_DET_RMS - [15:11] */
2755#define WM8996_DSP2DRC_SIG_DET_RMS_SHIFT 11 /* DSP2DRC_SIG_DET_RMS - [15:11] */
2756#define WM8996_DSP2DRC_SIG_DET_RMS_WIDTH 5 /* DSP2DRC_SIG_DET_RMS - [15:11] */
2757#define WM8996_DSP2DRC_SIG_DET_PK_MASK 0x0600 /* DSP2DRC_SIG_DET_PK - [10:9] */
2758#define WM8996_DSP2DRC_SIG_DET_PK_SHIFT 9 /* DSP2DRC_SIG_DET_PK - [10:9] */
2759#define WM8996_DSP2DRC_SIG_DET_PK_WIDTH 2 /* DSP2DRC_SIG_DET_PK - [10:9] */
2760#define WM8996_DSP2DRC_NG_ENA 0x0100 /* DSP2DRC_NG_ENA */
2761#define WM8996_DSP2DRC_NG_ENA_MASK 0x0100 /* DSP2DRC_NG_ENA */
2762#define WM8996_DSP2DRC_NG_ENA_SHIFT 8 /* DSP2DRC_NG_ENA */
2763#define WM8996_DSP2DRC_NG_ENA_WIDTH 1 /* DSP2DRC_NG_ENA */
2764#define WM8996_DSP2DRC_SIG_DET_MODE 0x0080 /* DSP2DRC_SIG_DET_MODE */
2765#define WM8996_DSP2DRC_SIG_DET_MODE_MASK 0x0080 /* DSP2DRC_SIG_DET_MODE */
2766#define WM8996_DSP2DRC_SIG_DET_MODE_SHIFT 7 /* DSP2DRC_SIG_DET_MODE */
2767#define WM8996_DSP2DRC_SIG_DET_MODE_WIDTH 1 /* DSP2DRC_SIG_DET_MODE */
2768#define WM8996_DSP2DRC_SIG_DET 0x0040 /* DSP2DRC_SIG_DET */
2769#define WM8996_DSP2DRC_SIG_DET_MASK 0x0040 /* DSP2DRC_SIG_DET */
2770#define WM8996_DSP2DRC_SIG_DET_SHIFT 6 /* DSP2DRC_SIG_DET */
2771#define WM8996_DSP2DRC_SIG_DET_WIDTH 1 /* DSP2DRC_SIG_DET */
2772#define WM8996_DSP2DRC_KNEE2_OP_ENA 0x0020 /* DSP2DRC_KNEE2_OP_ENA */
2773#define WM8996_DSP2DRC_KNEE2_OP_ENA_MASK 0x0020 /* DSP2DRC_KNEE2_OP_ENA */
2774#define WM8996_DSP2DRC_KNEE2_OP_ENA_SHIFT 5 /* DSP2DRC_KNEE2_OP_ENA */
2775#define WM8996_DSP2DRC_KNEE2_OP_ENA_WIDTH 1 /* DSP2DRC_KNEE2_OP_ENA */
2776#define WM8996_DSP2DRC_QR 0x0010 /* DSP2DRC_QR */
2777#define WM8996_DSP2DRC_QR_MASK 0x0010 /* DSP2DRC_QR */
2778#define WM8996_DSP2DRC_QR_SHIFT 4 /* DSP2DRC_QR */
2779#define WM8996_DSP2DRC_QR_WIDTH 1 /* DSP2DRC_QR */
2780#define WM8996_DSP2DRC_ANTICLIP 0x0008 /* DSP2DRC_ANTICLIP */
2781#define WM8996_DSP2DRC_ANTICLIP_MASK 0x0008 /* DSP2DRC_ANTICLIP */
2782#define WM8996_DSP2DRC_ANTICLIP_SHIFT 3 /* DSP2DRC_ANTICLIP */
2783#define WM8996_DSP2DRC_ANTICLIP_WIDTH 1 /* DSP2DRC_ANTICLIP */
2784#define WM8996_DSP2RX_DRC_ENA 0x0004 /* DSP2RX_DRC_ENA */
2785#define WM8996_DSP2RX_DRC_ENA_MASK 0x0004 /* DSP2RX_DRC_ENA */
2786#define WM8996_DSP2RX_DRC_ENA_SHIFT 2 /* DSP2RX_DRC_ENA */
2787#define WM8996_DSP2RX_DRC_ENA_WIDTH 1 /* DSP2RX_DRC_ENA */
2788#define WM8996_DSP2TXL_DRC_ENA 0x0002 /* DSP2TXL_DRC_ENA */
2789#define WM8996_DSP2TXL_DRC_ENA_MASK 0x0002 /* DSP2TXL_DRC_ENA */
2790#define WM8996_DSP2TXL_DRC_ENA_SHIFT 1 /* DSP2TXL_DRC_ENA */
2791#define WM8996_DSP2TXL_DRC_ENA_WIDTH 1 /* DSP2TXL_DRC_ENA */
2792#define WM8996_DSP2TXR_DRC_ENA 0x0001 /* DSP2TXR_DRC_ENA */
2793#define WM8996_DSP2TXR_DRC_ENA_MASK 0x0001 /* DSP2TXR_DRC_ENA */
2794#define WM8996_DSP2TXR_DRC_ENA_SHIFT 0 /* DSP2TXR_DRC_ENA */
2795#define WM8996_DSP2TXR_DRC_ENA_WIDTH 1 /* DSP2TXR_DRC_ENA */
2796
2797/*
2798 * R1345 (0x541) - DSP2 DRC (2)
2799 */
2800#define WM8996_DSP2DRC_ATK_MASK 0x1E00 /* DSP2DRC_ATK - [12:9] */
2801#define WM8996_DSP2DRC_ATK_SHIFT 9 /* DSP2DRC_ATK - [12:9] */
2802#define WM8996_DSP2DRC_ATK_WIDTH 4 /* DSP2DRC_ATK - [12:9] */
2803#define WM8996_DSP2DRC_DCY_MASK 0x01E0 /* DSP2DRC_DCY - [8:5] */
2804#define WM8996_DSP2DRC_DCY_SHIFT 5 /* DSP2DRC_DCY - [8:5] */
2805#define WM8996_DSP2DRC_DCY_WIDTH 4 /* DSP2DRC_DCY - [8:5] */
2806#define WM8996_DSP2DRC_MINGAIN_MASK 0x001C /* DSP2DRC_MINGAIN - [4:2] */
2807#define WM8996_DSP2DRC_MINGAIN_SHIFT 2 /* DSP2DRC_MINGAIN - [4:2] */
2808#define WM8996_DSP2DRC_MINGAIN_WIDTH 3 /* DSP2DRC_MINGAIN - [4:2] */
2809#define WM8996_DSP2DRC_MAXGAIN_MASK 0x0003 /* DSP2DRC_MAXGAIN - [1:0] */
2810#define WM8996_DSP2DRC_MAXGAIN_SHIFT 0 /* DSP2DRC_MAXGAIN - [1:0] */
2811#define WM8996_DSP2DRC_MAXGAIN_WIDTH 2 /* DSP2DRC_MAXGAIN - [1:0] */
2812
2813/*
2814 * R1346 (0x542) - DSP2 DRC (3)
2815 */
2816#define WM8996_DSP2DRC_NG_MINGAIN_MASK 0xF000 /* DSP2DRC_NG_MINGAIN - [15:12] */
2817#define WM8996_DSP2DRC_NG_MINGAIN_SHIFT 12 /* DSP2DRC_NG_MINGAIN - [15:12] */
2818#define WM8996_DSP2DRC_NG_MINGAIN_WIDTH 4 /* DSP2DRC_NG_MINGAIN - [15:12] */
2819#define WM8996_DSP2DRC_NG_EXP_MASK 0x0C00 /* DSP2DRC_NG_EXP - [11:10] */
2820#define WM8996_DSP2DRC_NG_EXP_SHIFT 10 /* DSP2DRC_NG_EXP - [11:10] */
2821#define WM8996_DSP2DRC_NG_EXP_WIDTH 2 /* DSP2DRC_NG_EXP - [11:10] */
2822#define WM8996_DSP2DRC_QR_THR_MASK 0x0300 /* DSP2DRC_QR_THR - [9:8] */
2823#define WM8996_DSP2DRC_QR_THR_SHIFT 8 /* DSP2DRC_QR_THR - [9:8] */
2824#define WM8996_DSP2DRC_QR_THR_WIDTH 2 /* DSP2DRC_QR_THR - [9:8] */
2825#define WM8996_DSP2DRC_QR_DCY_MASK 0x00C0 /* DSP2DRC_QR_DCY - [7:6] */
2826#define WM8996_DSP2DRC_QR_DCY_SHIFT 6 /* DSP2DRC_QR_DCY - [7:6] */
2827#define WM8996_DSP2DRC_QR_DCY_WIDTH 2 /* DSP2DRC_QR_DCY - [7:6] */
2828#define WM8996_DSP2DRC_HI_COMP_MASK 0x0038 /* DSP2DRC_HI_COMP - [5:3] */
2829#define WM8996_DSP2DRC_HI_COMP_SHIFT 3 /* DSP2DRC_HI_COMP - [5:3] */
2830#define WM8996_DSP2DRC_HI_COMP_WIDTH 3 /* DSP2DRC_HI_COMP - [5:3] */
2831#define WM8996_DSP2DRC_LO_COMP_MASK 0x0007 /* DSP2DRC_LO_COMP - [2:0] */
2832#define WM8996_DSP2DRC_LO_COMP_SHIFT 0 /* DSP2DRC_LO_COMP - [2:0] */
2833#define WM8996_DSP2DRC_LO_COMP_WIDTH 3 /* DSP2DRC_LO_COMP - [2:0] */
2834
2835/*
2836 * R1347 (0x543) - DSP2 DRC (4)
2837 */
2838#define WM8996_DSP2DRC_KNEE_IP_MASK 0x07E0 /* DSP2DRC_KNEE_IP - [10:5] */
2839#define WM8996_DSP2DRC_KNEE_IP_SHIFT 5 /* DSP2DRC_KNEE_IP - [10:5] */
2840#define WM8996_DSP2DRC_KNEE_IP_WIDTH 6 /* DSP2DRC_KNEE_IP - [10:5] */
2841#define WM8996_DSP2DRC_KNEE_OP_MASK 0x001F /* DSP2DRC_KNEE_OP - [4:0] */
2842#define WM8996_DSP2DRC_KNEE_OP_SHIFT 0 /* DSP2DRC_KNEE_OP - [4:0] */
2843#define WM8996_DSP2DRC_KNEE_OP_WIDTH 5 /* DSP2DRC_KNEE_OP - [4:0] */
2844
2845/*
2846 * R1348 (0x544) - DSP2 DRC (5)
2847 */
2848#define WM8996_DSP2DRC_KNEE2_IP_MASK 0x03E0 /* DSP2DRC_KNEE2_IP - [9:5] */
2849#define WM8996_DSP2DRC_KNEE2_IP_SHIFT 5 /* DSP2DRC_KNEE2_IP - [9:5] */
2850#define WM8996_DSP2DRC_KNEE2_IP_WIDTH 5 /* DSP2DRC_KNEE2_IP - [9:5] */
2851#define WM8996_DSP2DRC_KNEE2_OP_MASK 0x001F /* DSP2DRC_KNEE2_OP - [4:0] */
2852#define WM8996_DSP2DRC_KNEE2_OP_SHIFT 0 /* DSP2DRC_KNEE2_OP - [4:0] */
2853#define WM8996_DSP2DRC_KNEE2_OP_WIDTH 5 /* DSP2DRC_KNEE2_OP - [4:0] */
2854
2855/*
2856 * R1408 (0x580) - DSP2 RX EQ Gains (1)
2857 */
2858#define WM8996_DSP2RX_EQ_B1_GAIN_MASK 0xF800 /* DSP2RX_EQ_B1_GAIN - [15:11] */
2859#define WM8996_DSP2RX_EQ_B1_GAIN_SHIFT 11 /* DSP2RX_EQ_B1_GAIN - [15:11] */
2860#define WM8996_DSP2RX_EQ_B1_GAIN_WIDTH 5 /* DSP2RX_EQ_B1_GAIN - [15:11] */
2861#define WM8996_DSP2RX_EQ_B2_GAIN_MASK 0x07C0 /* DSP2RX_EQ_B2_GAIN - [10:6] */
2862#define WM8996_DSP2RX_EQ_B2_GAIN_SHIFT 6 /* DSP2RX_EQ_B2_GAIN - [10:6] */
2863#define WM8996_DSP2RX_EQ_B2_GAIN_WIDTH 5 /* DSP2RX_EQ_B2_GAIN - [10:6] */
2864#define WM8996_DSP2RX_EQ_B3_GAIN_MASK 0x003E /* DSP2RX_EQ_B3_GAIN - [5:1] */
2865#define WM8996_DSP2RX_EQ_B3_GAIN_SHIFT 1 /* DSP2RX_EQ_B3_GAIN - [5:1] */
2866#define WM8996_DSP2RX_EQ_B3_GAIN_WIDTH 5 /* DSP2RX_EQ_B3_GAIN - [5:1] */
2867#define WM8996_DSP2RX_EQ_ENA 0x0001 /* DSP2RX_EQ_ENA */
2868#define WM8996_DSP2RX_EQ_ENA_MASK 0x0001 /* DSP2RX_EQ_ENA */
2869#define WM8996_DSP2RX_EQ_ENA_SHIFT 0 /* DSP2RX_EQ_ENA */
2870#define WM8996_DSP2RX_EQ_ENA_WIDTH 1 /* DSP2RX_EQ_ENA */
2871
2872/*
2873 * R1409 (0x581) - DSP2 RX EQ Gains (2)
2874 */
2875#define WM8996_DSP2RX_EQ_B4_GAIN_MASK 0xF800 /* DSP2RX_EQ_B4_GAIN - [15:11] */
2876#define WM8996_DSP2RX_EQ_B4_GAIN_SHIFT 11 /* DSP2RX_EQ_B4_GAIN - [15:11] */
2877#define WM8996_DSP2RX_EQ_B4_GAIN_WIDTH 5 /* DSP2RX_EQ_B4_GAIN - [15:11] */
2878#define WM8996_DSP2RX_EQ_B5_GAIN_MASK 0x07C0 /* DSP2RX_EQ_B5_GAIN - [10:6] */
2879#define WM8996_DSP2RX_EQ_B5_GAIN_SHIFT 6 /* DSP2RX_EQ_B5_GAIN - [10:6] */
2880#define WM8996_DSP2RX_EQ_B5_GAIN_WIDTH 5 /* DSP2RX_EQ_B5_GAIN - [10:6] */
2881
2882/*
2883 * R1410 (0x582) - DSP2 RX EQ Band 1 A
2884 */
2885#define WM8996_DSP2RX_EQ_B1_A_MASK 0xFFFF /* DSP2RX_EQ_B1_A - [15:0] */
2886#define WM8996_DSP2RX_EQ_B1_A_SHIFT 0 /* DSP2RX_EQ_B1_A - [15:0] */
2887#define WM8996_DSP2RX_EQ_B1_A_WIDTH 16 /* DSP2RX_EQ_B1_A - [15:0] */
2888
2889/*
2890 * R1411 (0x583) - DSP2 RX EQ Band 1 B
2891 */
2892#define WM8996_DSP2RX_EQ_B1_B_MASK 0xFFFF /* DSP2RX_EQ_B1_B - [15:0] */
2893#define WM8996_DSP2RX_EQ_B1_B_SHIFT 0 /* DSP2RX_EQ_B1_B - [15:0] */
2894#define WM8996_DSP2RX_EQ_B1_B_WIDTH 16 /* DSP2RX_EQ_B1_B - [15:0] */
2895
2896/*
2897 * R1412 (0x584) - DSP2 RX EQ Band 1 PG
2898 */
2899#define WM8996_DSP2RX_EQ_B1_PG_MASK 0xFFFF /* DSP2RX_EQ_B1_PG - [15:0] */
2900#define WM8996_DSP2RX_EQ_B1_PG_SHIFT 0 /* DSP2RX_EQ_B1_PG - [15:0] */
2901#define WM8996_DSP2RX_EQ_B1_PG_WIDTH 16 /* DSP2RX_EQ_B1_PG - [15:0] */
2902
2903/*
2904 * R1413 (0x585) - DSP2 RX EQ Band 2 A
2905 */
2906#define WM8996_DSP2RX_EQ_B2_A_MASK 0xFFFF /* DSP2RX_EQ_B2_A - [15:0] */
2907#define WM8996_DSP2RX_EQ_B2_A_SHIFT 0 /* DSP2RX_EQ_B2_A - [15:0] */
2908#define WM8996_DSP2RX_EQ_B2_A_WIDTH 16 /* DSP2RX_EQ_B2_A - [15:0] */
2909
2910/*
2911 * R1414 (0x586) - DSP2 RX EQ Band 2 B
2912 */
2913#define WM8996_DSP2RX_EQ_B2_B_MASK 0xFFFF /* DSP2RX_EQ_B2_B - [15:0] */
2914#define WM8996_DSP2RX_EQ_B2_B_SHIFT 0 /* DSP2RX_EQ_B2_B - [15:0] */
2915#define WM8996_DSP2RX_EQ_B2_B_WIDTH 16 /* DSP2RX_EQ_B2_B - [15:0] */
2916
2917/*
2918 * R1415 (0x587) - DSP2 RX EQ Band 2 C
2919 */
2920#define WM8996_DSP2RX_EQ_B2_C_MASK 0xFFFF /* DSP2RX_EQ_B2_C - [15:0] */
2921#define WM8996_DSP2RX_EQ_B2_C_SHIFT 0 /* DSP2RX_EQ_B2_C - [15:0] */
2922#define WM8996_DSP2RX_EQ_B2_C_WIDTH 16 /* DSP2RX_EQ_B2_C - [15:0] */
2923
2924/*
2925 * R1416 (0x588) - DSP2 RX EQ Band 2 PG
2926 */
2927#define WM8996_DSP2RX_EQ_B2_PG_MASK 0xFFFF /* DSP2RX_EQ_B2_PG - [15:0] */
2928#define WM8996_DSP2RX_EQ_B2_PG_SHIFT 0 /* DSP2RX_EQ_B2_PG - [15:0] */
2929#define WM8996_DSP2RX_EQ_B2_PG_WIDTH 16 /* DSP2RX_EQ_B2_PG - [15:0] */
2930
2931/*
2932 * R1417 (0x589) - DSP2 RX EQ Band 3 A
2933 */
2934#define WM8996_DSP2RX_EQ_B3_A_MASK 0xFFFF /* DSP2RX_EQ_B3_A - [15:0] */
2935#define WM8996_DSP2RX_EQ_B3_A_SHIFT 0 /* DSP2RX_EQ_B3_A - [15:0] */
2936#define WM8996_DSP2RX_EQ_B3_A_WIDTH 16 /* DSP2RX_EQ_B3_A - [15:0] */
2937
2938/*
2939 * R1418 (0x58A) - DSP2 RX EQ Band 3 B
2940 */
2941#define WM8996_DSP2RX_EQ_B3_B_MASK 0xFFFF /* DSP2RX_EQ_B3_B - [15:0] */
2942#define WM8996_DSP2RX_EQ_B3_B_SHIFT 0 /* DSP2RX_EQ_B3_B - [15:0] */
2943#define WM8996_DSP2RX_EQ_B3_B_WIDTH 16 /* DSP2RX_EQ_B3_B - [15:0] */
2944
2945/*
2946 * R1419 (0x58B) - DSP2 RX EQ Band 3 C
2947 */
2948#define WM8996_DSP2RX_EQ_B3_C_MASK 0xFFFF /* DSP2RX_EQ_B3_C - [15:0] */
2949#define WM8996_DSP2RX_EQ_B3_C_SHIFT 0 /* DSP2RX_EQ_B3_C - [15:0] */
2950#define WM8996_DSP2RX_EQ_B3_C_WIDTH 16 /* DSP2RX_EQ_B3_C - [15:0] */
2951
2952/*
2953 * R1420 (0x58C) - DSP2 RX EQ Band 3 PG
2954 */
2955#define WM8996_DSP2RX_EQ_B3_PG_MASK 0xFFFF /* DSP2RX_EQ_B3_PG - [15:0] */
2956#define WM8996_DSP2RX_EQ_B3_PG_SHIFT 0 /* DSP2RX_EQ_B3_PG - [15:0] */
2957#define WM8996_DSP2RX_EQ_B3_PG_WIDTH 16 /* DSP2RX_EQ_B3_PG - [15:0] */
2958
2959/*
2960 * R1421 (0x58D) - DSP2 RX EQ Band 4 A
2961 */
2962#define WM8996_DSP2RX_EQ_B4_A_MASK 0xFFFF /* DSP2RX_EQ_B4_A - [15:0] */
2963#define WM8996_DSP2RX_EQ_B4_A_SHIFT 0 /* DSP2RX_EQ_B4_A - [15:0] */
2964#define WM8996_DSP2RX_EQ_B4_A_WIDTH 16 /* DSP2RX_EQ_B4_A - [15:0] */
2965
2966/*
2967 * R1422 (0x58E) - DSP2 RX EQ Band 4 B
2968 */
2969#define WM8996_DSP2RX_EQ_B4_B_MASK 0xFFFF /* DSP2RX_EQ_B4_B - [15:0] */
2970#define WM8996_DSP2RX_EQ_B4_B_SHIFT 0 /* DSP2RX_EQ_B4_B - [15:0] */
2971#define WM8996_DSP2RX_EQ_B4_B_WIDTH 16 /* DSP2RX_EQ_B4_B - [15:0] */
2972
2973/*
2974 * R1423 (0x58F) - DSP2 RX EQ Band 4 C
2975 */
2976#define WM8996_DSP2RX_EQ_B4_C_MASK 0xFFFF /* DSP2RX_EQ_B4_C - [15:0] */
2977#define WM8996_DSP2RX_EQ_B4_C_SHIFT 0 /* DSP2RX_EQ_B4_C - [15:0] */
2978#define WM8996_DSP2RX_EQ_B4_C_WIDTH 16 /* DSP2RX_EQ_B4_C - [15:0] */
2979
2980/*
2981 * R1424 (0x590) - DSP2 RX EQ Band 4 PG
2982 */
2983#define WM8996_DSP2RX_EQ_B4_PG_MASK 0xFFFF /* DSP2RX_EQ_B4_PG - [15:0] */
2984#define WM8996_DSP2RX_EQ_B4_PG_SHIFT 0 /* DSP2RX_EQ_B4_PG - [15:0] */
2985#define WM8996_DSP2RX_EQ_B4_PG_WIDTH 16 /* DSP2RX_EQ_B4_PG - [15:0] */
2986
2987/*
2988 * R1425 (0x591) - DSP2 RX EQ Band 5 A
2989 */
2990#define WM8996_DSP2RX_EQ_B5_A_MASK 0xFFFF /* DSP2RX_EQ_B5_A - [15:0] */
2991#define WM8996_DSP2RX_EQ_B5_A_SHIFT 0 /* DSP2RX_EQ_B5_A - [15:0] */
2992#define WM8996_DSP2RX_EQ_B5_A_WIDTH 16 /* DSP2RX_EQ_B5_A - [15:0] */
2993
2994/*
2995 * R1426 (0x592) - DSP2 RX EQ Band 5 B
2996 */
2997#define WM8996_DSP2RX_EQ_B5_B_MASK 0xFFFF /* DSP2RX_EQ_B5_B - [15:0] */
2998#define WM8996_DSP2RX_EQ_B5_B_SHIFT 0 /* DSP2RX_EQ_B5_B - [15:0] */
2999#define WM8996_DSP2RX_EQ_B5_B_WIDTH 16 /* DSP2RX_EQ_B5_B - [15:0] */
3000
3001/*
3002 * R1427 (0x593) - DSP2 RX EQ Band 5 PG
3003 */
3004#define WM8996_DSP2RX_EQ_B5_PG_MASK 0xFFFF /* DSP2RX_EQ_B5_PG - [15:0] */
3005#define WM8996_DSP2RX_EQ_B5_PG_SHIFT 0 /* DSP2RX_EQ_B5_PG - [15:0] */
3006#define WM8996_DSP2RX_EQ_B5_PG_WIDTH 16 /* DSP2RX_EQ_B5_PG - [15:0] */
3007
3008/*
3009 * R1536 (0x600) - DAC1 Mixer Volumes
3010 */
3011#define WM8996_ADCR_DAC1_VOL_MASK 0x03E0 /* ADCR_DAC1_VOL - [9:5] */
3012#define WM8996_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [9:5] */
3013#define WM8996_ADCR_DAC1_VOL_WIDTH 5 /* ADCR_DAC1_VOL - [9:5] */
3014#define WM8996_ADCL_DAC1_VOL_MASK 0x001F /* ADCL_DAC1_VOL - [4:0] */
3015#define WM8996_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [4:0] */
3016#define WM8996_ADCL_DAC1_VOL_WIDTH 5 /* ADCL_DAC1_VOL - [4:0] */
3017
3018/*
3019 * R1537 (0x601) - DAC1 Left Mixer Routing
3020 */
3021#define WM8996_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */
3022#define WM8996_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */
3023#define WM8996_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */
3024#define WM8996_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */
3025#define WM8996_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */
3026#define WM8996_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */
3027#define WM8996_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */
3028#define WM8996_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */
3029#define WM8996_DSP2RXL_TO_DAC1L 0x0002 /* DSP2RXL_TO_DAC1L */
3030#define WM8996_DSP2RXL_TO_DAC1L_MASK 0x0002 /* DSP2RXL_TO_DAC1L */
3031#define WM8996_DSP2RXL_TO_DAC1L_SHIFT 1 /* DSP2RXL_TO_DAC1L */
3032#define WM8996_DSP2RXL_TO_DAC1L_WIDTH 1 /* DSP2RXL_TO_DAC1L */
3033#define WM8996_DSP1RXL_TO_DAC1L 0x0001 /* DSP1RXL_TO_DAC1L */
3034#define WM8996_DSP1RXL_TO_DAC1L_MASK 0x0001 /* DSP1RXL_TO_DAC1L */
3035#define WM8996_DSP1RXL_TO_DAC1L_SHIFT 0 /* DSP1RXL_TO_DAC1L */
3036#define WM8996_DSP1RXL_TO_DAC1L_WIDTH 1 /* DSP1RXL_TO_DAC1L */
3037
3038/*
3039 * R1538 (0x602) - DAC1 Right Mixer Routing
3040 */
3041#define WM8996_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */
3042#define WM8996_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */
3043#define WM8996_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */
3044#define WM8996_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */
3045#define WM8996_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */
3046#define WM8996_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */
3047#define WM8996_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */
3048#define WM8996_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */
3049#define WM8996_DSP2RXR_TO_DAC1R 0x0002 /* DSP2RXR_TO_DAC1R */
3050#define WM8996_DSP2RXR_TO_DAC1R_MASK 0x0002 /* DSP2RXR_TO_DAC1R */
3051#define WM8996_DSP2RXR_TO_DAC1R_SHIFT 1 /* DSP2RXR_TO_DAC1R */
3052#define WM8996_DSP2RXR_TO_DAC1R_WIDTH 1 /* DSP2RXR_TO_DAC1R */
3053#define WM8996_DSP1RXR_TO_DAC1R 0x0001 /* DSP1RXR_TO_DAC1R */
3054#define WM8996_DSP1RXR_TO_DAC1R_MASK 0x0001 /* DSP1RXR_TO_DAC1R */
3055#define WM8996_DSP1RXR_TO_DAC1R_SHIFT 0 /* DSP1RXR_TO_DAC1R */
3056#define WM8996_DSP1RXR_TO_DAC1R_WIDTH 1 /* DSP1RXR_TO_DAC1R */
3057
3058/*
3059 * R1539 (0x603) - DAC2 Mixer Volumes
3060 */
3061#define WM8996_ADCR_DAC2_VOL_MASK 0x03E0 /* ADCR_DAC2_VOL - [9:5] */
3062#define WM8996_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [9:5] */
3063#define WM8996_ADCR_DAC2_VOL_WIDTH 5 /* ADCR_DAC2_VOL - [9:5] */
3064#define WM8996_ADCL_DAC2_VOL_MASK 0x001F /* ADCL_DAC2_VOL - [4:0] */
3065#define WM8996_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [4:0] */
3066#define WM8996_ADCL_DAC2_VOL_WIDTH 5 /* ADCL_DAC2_VOL - [4:0] */
3067
3068/*
3069 * R1540 (0x604) - DAC2 Left Mixer Routing
3070 */
3071#define WM8996_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */
3072#define WM8996_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */
3073#define WM8996_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */
3074#define WM8996_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */
3075#define WM8996_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */
3076#define WM8996_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */
3077#define WM8996_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */
3078#define WM8996_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */
3079#define WM8996_DSP2RXL_TO_DAC2L 0x0002 /* DSP2RXL_TO_DAC2L */
3080#define WM8996_DSP2RXL_TO_DAC2L_MASK 0x0002 /* DSP2RXL_TO_DAC2L */
3081#define WM8996_DSP2RXL_TO_DAC2L_SHIFT 1 /* DSP2RXL_TO_DAC2L */
3082#define WM8996_DSP2RXL_TO_DAC2L_WIDTH 1 /* DSP2RXL_TO_DAC2L */
3083#define WM8996_DSP1RXL_TO_DAC2L 0x0001 /* DSP1RXL_TO_DAC2L */
3084#define WM8996_DSP1RXL_TO_DAC2L_MASK 0x0001 /* DSP1RXL_TO_DAC2L */
3085#define WM8996_DSP1RXL_TO_DAC2L_SHIFT 0 /* DSP1RXL_TO_DAC2L */
3086#define WM8996_DSP1RXL_TO_DAC2L_WIDTH 1 /* DSP1RXL_TO_DAC2L */
3087
3088/*
3089 * R1541 (0x605) - DAC2 Right Mixer Routing
3090 */
3091#define WM8996_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */
3092#define WM8996_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */
3093#define WM8996_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */
3094#define WM8996_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */
3095#define WM8996_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */
3096#define WM8996_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */
3097#define WM8996_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */
3098#define WM8996_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */
3099#define WM8996_DSP2RXR_TO_DAC2R 0x0002 /* DSP2RXR_TO_DAC2R */
3100#define WM8996_DSP2RXR_TO_DAC2R_MASK 0x0002 /* DSP2RXR_TO_DAC2R */
3101#define WM8996_DSP2RXR_TO_DAC2R_SHIFT 1 /* DSP2RXR_TO_DAC2R */
3102#define WM8996_DSP2RXR_TO_DAC2R_WIDTH 1 /* DSP2RXR_TO_DAC2R */
3103#define WM8996_DSP1RXR_TO_DAC2R 0x0001 /* DSP1RXR_TO_DAC2R */
3104#define WM8996_DSP1RXR_TO_DAC2R_MASK 0x0001 /* DSP1RXR_TO_DAC2R */
3105#define WM8996_DSP1RXR_TO_DAC2R_SHIFT 0 /* DSP1RXR_TO_DAC2R */
3106#define WM8996_DSP1RXR_TO_DAC2R_WIDTH 1 /* DSP1RXR_TO_DAC2R */
3107
3108/*
3109 * R1542 (0x606) - DSP1 TX Left Mixer Routing
3110 */
3111#define WM8996_ADC1L_TO_DSP1TXL 0x0002 /* ADC1L_TO_DSP1TXL */
3112#define WM8996_ADC1L_TO_DSP1TXL_MASK 0x0002 /* ADC1L_TO_DSP1TXL */
3113#define WM8996_ADC1L_TO_DSP1TXL_SHIFT 1 /* ADC1L_TO_DSP1TXL */
3114#define WM8996_ADC1L_TO_DSP1TXL_WIDTH 1 /* ADC1L_TO_DSP1TXL */
3115#define WM8996_DACL_TO_DSP1TXL 0x0001 /* DACL_TO_DSP1TXL */
3116#define WM8996_DACL_TO_DSP1TXL_MASK 0x0001 /* DACL_TO_DSP1TXL */
3117#define WM8996_DACL_TO_DSP1TXL_SHIFT 0 /* DACL_TO_DSP1TXL */
3118#define WM8996_DACL_TO_DSP1TXL_WIDTH 1 /* DACL_TO_DSP1TXL */
3119
3120/*
3121 * R1543 (0x607) - DSP1 TX Right Mixer Routing
3122 */
3123#define WM8996_ADC1R_TO_DSP1TXR 0x0002 /* ADC1R_TO_DSP1TXR */
3124#define WM8996_ADC1R_TO_DSP1TXR_MASK 0x0002 /* ADC1R_TO_DSP1TXR */
3125#define WM8996_ADC1R_TO_DSP1TXR_SHIFT 1 /* ADC1R_TO_DSP1TXR */
3126#define WM8996_ADC1R_TO_DSP1TXR_WIDTH 1 /* ADC1R_TO_DSP1TXR */
3127#define WM8996_DACR_TO_DSP1TXR 0x0001 /* DACR_TO_DSP1TXR */
3128#define WM8996_DACR_TO_DSP1TXR_MASK 0x0001 /* DACR_TO_DSP1TXR */
3129#define WM8996_DACR_TO_DSP1TXR_SHIFT 0 /* DACR_TO_DSP1TXR */
3130#define WM8996_DACR_TO_DSP1TXR_WIDTH 1 /* DACR_TO_DSP1TXR */
3131
3132/*
3133 * R1544 (0x608) - DSP2 TX Left Mixer Routing
3134 */
3135#define WM8996_ADC2L_TO_DSP2TXL 0x0002 /* ADC2L_TO_DSP2TXL */
3136#define WM8996_ADC2L_TO_DSP2TXL_MASK 0x0002 /* ADC2L_TO_DSP2TXL */
3137#define WM8996_ADC2L_TO_DSP2TXL_SHIFT 1 /* ADC2L_TO_DSP2TXL */
3138#define WM8996_ADC2L_TO_DSP2TXL_WIDTH 1 /* ADC2L_TO_DSP2TXL */
3139#define WM8996_DACL_TO_DSP2TXL 0x0001 /* DACL_TO_DSP2TXL */
3140#define WM8996_DACL_TO_DSP2TXL_MASK 0x0001 /* DACL_TO_DSP2TXL */
3141#define WM8996_DACL_TO_DSP2TXL_SHIFT 0 /* DACL_TO_DSP2TXL */
3142#define WM8996_DACL_TO_DSP2TXL_WIDTH 1 /* DACL_TO_DSP2TXL */
3143
3144/*
3145 * R1545 (0x609) - DSP2 TX Right Mixer Routing
3146 */
3147#define WM8996_ADC2R_TO_DSP2TXR 0x0002 /* ADC2R_TO_DSP2TXR */
3148#define WM8996_ADC2R_TO_DSP2TXR_MASK 0x0002 /* ADC2R_TO_DSP2TXR */
3149#define WM8996_ADC2R_TO_DSP2TXR_SHIFT 1 /* ADC2R_TO_DSP2TXR */
3150#define WM8996_ADC2R_TO_DSP2TXR_WIDTH 1 /* ADC2R_TO_DSP2TXR */
3151#define WM8996_DACR_TO_DSP2TXR 0x0001 /* DACR_TO_DSP2TXR */
3152#define WM8996_DACR_TO_DSP2TXR_MASK 0x0001 /* DACR_TO_DSP2TXR */
3153#define WM8996_DACR_TO_DSP2TXR_SHIFT 0 /* DACR_TO_DSP2TXR */
3154#define WM8996_DACR_TO_DSP2TXR_WIDTH 1 /* DACR_TO_DSP2TXR */
3155
3156/*
3157 * R1546 (0x60A) - DSP TX Mixer Select
3158 */
3159#define WM8996_DAC_TO_DSPTX_SRC 0x0001 /* DAC_TO_DSPTX_SRC */
3160#define WM8996_DAC_TO_DSPTX_SRC_MASK 0x0001 /* DAC_TO_DSPTX_SRC */
3161#define WM8996_DAC_TO_DSPTX_SRC_SHIFT 0 /* DAC_TO_DSPTX_SRC */
3162#define WM8996_DAC_TO_DSPTX_SRC_WIDTH 1 /* DAC_TO_DSPTX_SRC */
3163
3164/*
3165 * R1552 (0x610) - DAC Softmute
3166 */
3167#define WM8996_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */
3168#define WM8996_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */
3169#define WM8996_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */
3170#define WM8996_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */
3171#define WM8996_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */
3172#define WM8996_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */
3173#define WM8996_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */
3174#define WM8996_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */
3175
3176/*
3177 * R1568 (0x620) - Oversampling
3178 */
3179#define WM8996_SPK_OSR128 0x0008 /* SPK_OSR128 */
3180#define WM8996_SPK_OSR128_MASK 0x0008 /* SPK_OSR128 */
3181#define WM8996_SPK_OSR128_SHIFT 3 /* SPK_OSR128 */
3182#define WM8996_SPK_OSR128_WIDTH 1 /* SPK_OSR128 */
3183#define WM8996_DMIC_OSR64 0x0004 /* DMIC_OSR64 */
3184#define WM8996_DMIC_OSR64_MASK 0x0004 /* DMIC_OSR64 */
3185#define WM8996_DMIC_OSR64_SHIFT 2 /* DMIC_OSR64 */
3186#define WM8996_DMIC_OSR64_WIDTH 1 /* DMIC_OSR64 */
3187#define WM8996_ADC_OSR128 0x0002 /* ADC_OSR128 */
3188#define WM8996_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */
3189#define WM8996_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */
3190#define WM8996_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */
3191#define WM8996_DAC_OSR128 0x0001 /* DAC_OSR128 */
3192#define WM8996_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */
3193#define WM8996_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */
3194#define WM8996_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */
3195
3196/*
3197 * R1569 (0x621) - Sidetone
3198 */
3199#define WM8996_ST_LPF 0x1000 /* ST_LPF */
3200#define WM8996_ST_LPF_MASK 0x1000 /* ST_LPF */
3201#define WM8996_ST_LPF_SHIFT 12 /* ST_LPF */
3202#define WM8996_ST_LPF_WIDTH 1 /* ST_LPF */
3203#define WM8996_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */
3204#define WM8996_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */
3205#define WM8996_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */
3206#define WM8996_ST_HPF 0x0040 /* ST_HPF */
3207#define WM8996_ST_HPF_MASK 0x0040 /* ST_HPF */
3208#define WM8996_ST_HPF_SHIFT 6 /* ST_HPF */
3209#define WM8996_ST_HPF_WIDTH 1 /* ST_HPF */
3210#define WM8996_STR_SEL 0x0002 /* STR_SEL */
3211#define WM8996_STR_SEL_MASK 0x0002 /* STR_SEL */
3212#define WM8996_STR_SEL_SHIFT 1 /* STR_SEL */
3213#define WM8996_STR_SEL_WIDTH 1 /* STR_SEL */
3214#define WM8996_STL_SEL 0x0001 /* STL_SEL */
3215#define WM8996_STL_SEL_MASK 0x0001 /* STL_SEL */
3216#define WM8996_STL_SEL_SHIFT 0 /* STL_SEL */
3217#define WM8996_STL_SEL_WIDTH 1 /* STL_SEL */
3218
3219/*
3220 * R1792 (0x700) - GPIO 1
3221 */
3222#define WM8996_GP1_DIR 0x8000 /* GP1_DIR */
3223#define WM8996_GP1_DIR_MASK 0x8000 /* GP1_DIR */
3224#define WM8996_GP1_DIR_SHIFT 15 /* GP1_DIR */
3225#define WM8996_GP1_DIR_WIDTH 1 /* GP1_DIR */
3226#define WM8996_GP1_PU 0x4000 /* GP1_PU */
3227#define WM8996_GP1_PU_MASK 0x4000 /* GP1_PU */
3228#define WM8996_GP1_PU_SHIFT 14 /* GP1_PU */
3229#define WM8996_GP1_PU_WIDTH 1 /* GP1_PU */
3230#define WM8996_GP1_PD 0x2000 /* GP1_PD */
3231#define WM8996_GP1_PD_MASK 0x2000 /* GP1_PD */
3232#define WM8996_GP1_PD_SHIFT 13 /* GP1_PD */
3233#define WM8996_GP1_PD_WIDTH 1 /* GP1_PD */
3234#define WM8996_GP1_POL 0x0400 /* GP1_POL */
3235#define WM8996_GP1_POL_MASK 0x0400 /* GP1_POL */
3236#define WM8996_GP1_POL_SHIFT 10 /* GP1_POL */
3237#define WM8996_GP1_POL_WIDTH 1 /* GP1_POL */
3238#define WM8996_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */
3239#define WM8996_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */
3240#define WM8996_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */
3241#define WM8996_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */
3242#define WM8996_GP1_DB 0x0100 /* GP1_DB */
3243#define WM8996_GP1_DB_MASK 0x0100 /* GP1_DB */
3244#define WM8996_GP1_DB_SHIFT 8 /* GP1_DB */
3245#define WM8996_GP1_DB_WIDTH 1 /* GP1_DB */
3246#define WM8996_GP1_LVL 0x0040 /* GP1_LVL */
3247#define WM8996_GP1_LVL_MASK 0x0040 /* GP1_LVL */
3248#define WM8996_GP1_LVL_SHIFT 6 /* GP1_LVL */
3249#define WM8996_GP1_LVL_WIDTH 1 /* GP1_LVL */
3250#define WM8996_GP1_FN_MASK 0x000F /* GP1_FN - [3:0] */
3251#define WM8996_GP1_FN_SHIFT 0 /* GP1_FN - [3:0] */
3252#define WM8996_GP1_FN_WIDTH 4 /* GP1_FN - [3:0] */
3253
3254/*
3255 * R1793 (0x701) - GPIO 2
3256 */
3257#define WM8996_GP2_DIR 0x8000 /* GP2_DIR */
3258#define WM8996_GP2_DIR_MASK 0x8000 /* GP2_DIR */
3259#define WM8996_GP2_DIR_SHIFT 15 /* GP2_DIR */
3260#define WM8996_GP2_DIR_WIDTH 1 /* GP2_DIR */
3261#define WM8996_GP2_PU 0x4000 /* GP2_PU */
3262#define WM8996_GP2_PU_MASK 0x4000 /* GP2_PU */
3263#define WM8996_GP2_PU_SHIFT 14 /* GP2_PU */
3264#define WM8996_GP2_PU_WIDTH 1 /* GP2_PU */
3265#define WM8996_GP2_PD 0x2000 /* GP2_PD */
3266#define WM8996_GP2_PD_MASK 0x2000 /* GP2_PD */
3267#define WM8996_GP2_PD_SHIFT 13 /* GP2_PD */
3268#define WM8996_GP2_PD_WIDTH 1 /* GP2_PD */
3269#define WM8996_GP2_POL 0x0400 /* GP2_POL */
3270#define WM8996_GP2_POL_MASK 0x0400 /* GP2_POL */
3271#define WM8996_GP2_POL_SHIFT 10 /* GP2_POL */
3272#define WM8996_GP2_POL_WIDTH 1 /* GP2_POL */
3273#define WM8996_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */
3274#define WM8996_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */
3275#define WM8996_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */
3276#define WM8996_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */
3277#define WM8996_GP2_DB 0x0100 /* GP2_DB */
3278#define WM8996_GP2_DB_MASK 0x0100 /* GP2_DB */
3279#define WM8996_GP2_DB_SHIFT 8 /* GP2_DB */
3280#define WM8996_GP2_DB_WIDTH 1 /* GP2_DB */
3281#define WM8996_GP2_LVL 0x0040 /* GP2_LVL */
3282#define WM8996_GP2_LVL_MASK 0x0040 /* GP2_LVL */
3283#define WM8996_GP2_LVL_SHIFT 6 /* GP2_LVL */
3284#define WM8996_GP2_LVL_WIDTH 1 /* GP2_LVL */
3285#define WM8996_GP2_FN_MASK 0x000F /* GP2_FN - [3:0] */
3286#define WM8996_GP2_FN_SHIFT 0 /* GP2_FN - [3:0] */
3287#define WM8996_GP2_FN_WIDTH 4 /* GP2_FN - [3:0] */
3288
3289/*
3290 * R1794 (0x702) - GPIO 3
3291 */
3292#define WM8996_GP3_DIR 0x8000 /* GP3_DIR */
3293#define WM8996_GP3_DIR_MASK 0x8000 /* GP3_DIR */
3294#define WM8996_GP3_DIR_SHIFT 15 /* GP3_DIR */
3295#define WM8996_GP3_DIR_WIDTH 1 /* GP3_DIR */
3296#define WM8996_GP3_PU 0x4000 /* GP3_PU */
3297#define WM8996_GP3_PU_MASK 0x4000 /* GP3_PU */
3298#define WM8996_GP3_PU_SHIFT 14 /* GP3_PU */
3299#define WM8996_GP3_PU_WIDTH 1 /* GP3_PU */
3300#define WM8996_GP3_PD 0x2000 /* GP3_PD */
3301#define WM8996_GP3_PD_MASK 0x2000 /* GP3_PD */
3302#define WM8996_GP3_PD_SHIFT 13 /* GP3_PD */
3303#define WM8996_GP3_PD_WIDTH 1 /* GP3_PD */
3304#define WM8996_GP3_POL 0x0400 /* GP3_POL */
3305#define WM8996_GP3_POL_MASK 0x0400 /* GP3_POL */
3306#define WM8996_GP3_POL_SHIFT 10 /* GP3_POL */
3307#define WM8996_GP3_POL_WIDTH 1 /* GP3_POL */
3308#define WM8996_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */
3309#define WM8996_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */
3310#define WM8996_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */
3311#define WM8996_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */
3312#define WM8996_GP3_DB 0x0100 /* GP3_DB */
3313#define WM8996_GP3_DB_MASK 0x0100 /* GP3_DB */
3314#define WM8996_GP3_DB_SHIFT 8 /* GP3_DB */
3315#define WM8996_GP3_DB_WIDTH 1 /* GP3_DB */
3316#define WM8996_GP3_LVL 0x0040 /* GP3_LVL */
3317#define WM8996_GP3_LVL_MASK 0x0040 /* GP3_LVL */
3318#define WM8996_GP3_LVL_SHIFT 6 /* GP3_LVL */
3319#define WM8996_GP3_LVL_WIDTH 1 /* GP3_LVL */
3320#define WM8996_GP3_FN_MASK 0x000F /* GP3_FN - [3:0] */
3321#define WM8996_GP3_FN_SHIFT 0 /* GP3_FN - [3:0] */
3322#define WM8996_GP3_FN_WIDTH 4 /* GP3_FN - [3:0] */
3323
3324/*
3325 * R1795 (0x703) - GPIO 4
3326 */
3327#define WM8996_GP4_DIR 0x8000 /* GP4_DIR */
3328#define WM8996_GP4_DIR_MASK 0x8000 /* GP4_DIR */
3329#define WM8996_GP4_DIR_SHIFT 15 /* GP4_DIR */
3330#define WM8996_GP4_DIR_WIDTH 1 /* GP4_DIR */
3331#define WM8996_GP4_PU 0x4000 /* GP4_PU */
3332#define WM8996_GP4_PU_MASK 0x4000 /* GP4_PU */
3333#define WM8996_GP4_PU_SHIFT 14 /* GP4_PU */
3334#define WM8996_GP4_PU_WIDTH 1 /* GP4_PU */
3335#define WM8996_GP4_PD 0x2000 /* GP4_PD */
3336#define WM8996_GP4_PD_MASK 0x2000 /* GP4_PD */
3337#define WM8996_GP4_PD_SHIFT 13 /* GP4_PD */
3338#define WM8996_GP4_PD_WIDTH 1 /* GP4_PD */
3339#define WM8996_GP4_POL 0x0400 /* GP4_POL */
3340#define WM8996_GP4_POL_MASK 0x0400 /* GP4_POL */
3341#define WM8996_GP4_POL_SHIFT 10 /* GP4_POL */
3342#define WM8996_GP4_POL_WIDTH 1 /* GP4_POL */
3343#define WM8996_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */
3344#define WM8996_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */
3345#define WM8996_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */
3346#define WM8996_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */
3347#define WM8996_GP4_DB 0x0100 /* GP4_DB */
3348#define WM8996_GP4_DB_MASK 0x0100 /* GP4_DB */
3349#define WM8996_GP4_DB_SHIFT 8 /* GP4_DB */
3350#define WM8996_GP4_DB_WIDTH 1 /* GP4_DB */
3351#define WM8996_GP4_LVL 0x0040 /* GP4_LVL */
3352#define WM8996_GP4_LVL_MASK 0x0040 /* GP4_LVL */
3353#define WM8996_GP4_LVL_SHIFT 6 /* GP4_LVL */
3354#define WM8996_GP4_LVL_WIDTH 1 /* GP4_LVL */
3355#define WM8996_GP4_FN_MASK 0x000F /* GP4_FN - [3:0] */
3356#define WM8996_GP4_FN_SHIFT 0 /* GP4_FN - [3:0] */
3357#define WM8996_GP4_FN_WIDTH 4 /* GP4_FN - [3:0] */
3358
3359/*
3360 * R1796 (0x704) - GPIO 5
3361 */
3362#define WM8996_GP5_DIR 0x8000 /* GP5_DIR */
3363#define WM8996_GP5_DIR_MASK 0x8000 /* GP5_DIR */
3364#define WM8996_GP5_DIR_SHIFT 15 /* GP5_DIR */
3365#define WM8996_GP5_DIR_WIDTH 1 /* GP5_DIR */
3366#define WM8996_GP5_PU 0x4000 /* GP5_PU */
3367#define WM8996_GP5_PU_MASK 0x4000 /* GP5_PU */
3368#define WM8996_GP5_PU_SHIFT 14 /* GP5_PU */
3369#define WM8996_GP5_PU_WIDTH 1 /* GP5_PU */
3370#define WM8996_GP5_PD 0x2000 /* GP5_PD */
3371#define WM8996_GP5_PD_MASK 0x2000 /* GP5_PD */
3372#define WM8996_GP5_PD_SHIFT 13 /* GP5_PD */
3373#define WM8996_GP5_PD_WIDTH 1 /* GP5_PD */
3374#define WM8996_GP5_POL 0x0400 /* GP5_POL */
3375#define WM8996_GP5_POL_MASK 0x0400 /* GP5_POL */
3376#define WM8996_GP5_POL_SHIFT 10 /* GP5_POL */
3377#define WM8996_GP5_POL_WIDTH 1 /* GP5_POL */
3378#define WM8996_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */
3379#define WM8996_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */
3380#define WM8996_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */
3381#define WM8996_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */
3382#define WM8996_GP5_DB 0x0100 /* GP5_DB */
3383#define WM8996_GP5_DB_MASK 0x0100 /* GP5_DB */
3384#define WM8996_GP5_DB_SHIFT 8 /* GP5_DB */
3385#define WM8996_GP5_DB_WIDTH 1 /* GP5_DB */
3386#define WM8996_GP5_LVL 0x0040 /* GP5_LVL */
3387#define WM8996_GP5_LVL_MASK 0x0040 /* GP5_LVL */
3388#define WM8996_GP5_LVL_SHIFT 6 /* GP5_LVL */
3389#define WM8996_GP5_LVL_WIDTH 1 /* GP5_LVL */
3390#define WM8996_GP5_FN_MASK 0x000F /* GP5_FN - [3:0] */
3391#define WM8996_GP5_FN_SHIFT 0 /* GP5_FN - [3:0] */
3392#define WM8996_GP5_FN_WIDTH 4 /* GP5_FN - [3:0] */
3393
3394/*
3395 * R1824 (0x720) - Pull Control (1)
3396 */
3397#define WM8996_DMICDAT2_PD 0x1000 /* DMICDAT2_PD */
3398#define WM8996_DMICDAT2_PD_MASK 0x1000 /* DMICDAT2_PD */
3399#define WM8996_DMICDAT2_PD_SHIFT 12 /* DMICDAT2_PD */
3400#define WM8996_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
3401#define WM8996_DMICDAT1_PD 0x0400 /* DMICDAT1_PD */
3402#define WM8996_DMICDAT1_PD_MASK 0x0400 /* DMICDAT1_PD */
3403#define WM8996_DMICDAT1_PD_SHIFT 10 /* DMICDAT1_PD */
3404#define WM8996_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
3405#define WM8996_MCLK2_PU 0x0200 /* MCLK2_PU */
3406#define WM8996_MCLK2_PU_MASK 0x0200 /* MCLK2_PU */
3407#define WM8996_MCLK2_PU_SHIFT 9 /* MCLK2_PU */
3408#define WM8996_MCLK2_PU_WIDTH 1 /* MCLK2_PU */
3409#define WM8996_MCLK2_PD 0x0100 /* MCLK2_PD */
3410#define WM8996_MCLK2_PD_MASK 0x0100 /* MCLK2_PD */
3411#define WM8996_MCLK2_PD_SHIFT 8 /* MCLK2_PD */
3412#define WM8996_MCLK2_PD_WIDTH 1 /* MCLK2_PD */
3413#define WM8996_MCLK1_PU 0x0080 /* MCLK1_PU */
3414#define WM8996_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */
3415#define WM8996_MCLK1_PU_SHIFT 7 /* MCLK1_PU */
3416#define WM8996_MCLK1_PU_WIDTH 1 /* MCLK1_PU */
3417#define WM8996_MCLK1_PD 0x0040 /* MCLK1_PD */
3418#define WM8996_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */
3419#define WM8996_MCLK1_PD_SHIFT 6 /* MCLK1_PD */
3420#define WM8996_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
3421#define WM8996_DACDAT1_PU 0x0020 /* DACDAT1_PU */
3422#define WM8996_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */
3423#define WM8996_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */
3424#define WM8996_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */
3425#define WM8996_DACDAT1_PD 0x0010 /* DACDAT1_PD */
3426#define WM8996_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */
3427#define WM8996_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */
3428#define WM8996_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */
3429#define WM8996_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */
3430#define WM8996_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */
3431#define WM8996_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */
3432#define WM8996_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */
3433#define WM8996_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */
3434#define WM8996_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */
3435#define WM8996_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */
3436#define WM8996_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */
3437#define WM8996_BCLK1_PU 0x0002 /* BCLK1_PU */
3438#define WM8996_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */
3439#define WM8996_BCLK1_PU_SHIFT 1 /* BCLK1_PU */
3440#define WM8996_BCLK1_PU_WIDTH 1 /* BCLK1_PU */
3441#define WM8996_BCLK1_PD 0x0001 /* BCLK1_PD */
3442#define WM8996_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */
3443#define WM8996_BCLK1_PD_SHIFT 0 /* BCLK1_PD */
3444#define WM8996_BCLK1_PD_WIDTH 1 /* BCLK1_PD */
3445
3446/*
3447 * R1825 (0x721) - Pull Control (2)
3448 */
3449#define WM8996_LDO1ENA_PD 0x0100 /* LDO1ENA_PD */
3450#define WM8996_LDO1ENA_PD_MASK 0x0100 /* LDO1ENA_PD */
3451#define WM8996_LDO1ENA_PD_SHIFT 8 /* LDO1ENA_PD */
3452#define WM8996_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */
3453#define WM8996_ADDR_PD 0x0040 /* ADDR_PD */
3454#define WM8996_ADDR_PD_MASK 0x0040 /* ADDR_PD */
3455#define WM8996_ADDR_PD_SHIFT 6 /* ADDR_PD */
3456#define WM8996_ADDR_PD_WIDTH 1 /* ADDR_PD */
3457#define WM8996_DACDAT2_PU 0x0020 /* DACDAT2_PU */
3458#define WM8996_DACDAT2_PU_MASK 0x0020 /* DACDAT2_PU */
3459#define WM8996_DACDAT2_PU_SHIFT 5 /* DACDAT2_PU */
3460#define WM8996_DACDAT2_PU_WIDTH 1 /* DACDAT2_PU */
3461#define WM8996_DACDAT2_PD 0x0010 /* DACDAT2_PD */
3462#define WM8996_DACDAT2_PD_MASK 0x0010 /* DACDAT2_PD */
3463#define WM8996_DACDAT2_PD_SHIFT 4 /* DACDAT2_PD */
3464#define WM8996_DACDAT2_PD_WIDTH 1 /* DACDAT2_PD */
3465#define WM8996_DACLRCLK2_PU 0x0008 /* DACLRCLK2_PU */
3466#define WM8996_DACLRCLK2_PU_MASK 0x0008 /* DACLRCLK2_PU */
3467#define WM8996_DACLRCLK2_PU_SHIFT 3 /* DACLRCLK2_PU */
3468#define WM8996_DACLRCLK2_PU_WIDTH 1 /* DACLRCLK2_PU */
3469#define WM8996_DACLRCLK2_PD 0x0004 /* DACLRCLK2_PD */
3470#define WM8996_DACLRCLK2_PD_MASK 0x0004 /* DACLRCLK2_PD */
3471#define WM8996_DACLRCLK2_PD_SHIFT 2 /* DACLRCLK2_PD */
3472#define WM8996_DACLRCLK2_PD_WIDTH 1 /* DACLRCLK2_PD */
3473#define WM8996_BCLK2_PU 0x0002 /* BCLK2_PU */
3474#define WM8996_BCLK2_PU_MASK 0x0002 /* BCLK2_PU */
3475#define WM8996_BCLK2_PU_SHIFT 1 /* BCLK2_PU */
3476#define WM8996_BCLK2_PU_WIDTH 1 /* BCLK2_PU */
3477#define WM8996_BCLK2_PD 0x0001 /* BCLK2_PD */
3478#define WM8996_BCLK2_PD_MASK 0x0001 /* BCLK2_PD */
3479#define WM8996_BCLK2_PD_SHIFT 0 /* BCLK2_PD */
3480#define WM8996_BCLK2_PD_WIDTH 1 /* BCLK2_PD */
3481
3482/*
3483 * R1840 (0x730) - Interrupt Status 1
3484 */
3485#define WM8996_GP5_EINT 0x0010 /* GP5_EINT */
3486#define WM8996_GP5_EINT_MASK 0x0010 /* GP5_EINT */
3487#define WM8996_GP5_EINT_SHIFT 4 /* GP5_EINT */
3488#define WM8996_GP5_EINT_WIDTH 1 /* GP5_EINT */
3489#define WM8996_GP4_EINT 0x0008 /* GP4_EINT */
3490#define WM8996_GP4_EINT_MASK 0x0008 /* GP4_EINT */
3491#define WM8996_GP4_EINT_SHIFT 3 /* GP4_EINT */
3492#define WM8996_GP4_EINT_WIDTH 1 /* GP4_EINT */
3493#define WM8996_GP3_EINT 0x0004 /* GP3_EINT */
3494#define WM8996_GP3_EINT_MASK 0x0004 /* GP3_EINT */
3495#define WM8996_GP3_EINT_SHIFT 2 /* GP3_EINT */
3496#define WM8996_GP3_EINT_WIDTH 1 /* GP3_EINT */
3497#define WM8996_GP2_EINT 0x0002 /* GP2_EINT */
3498#define WM8996_GP2_EINT_MASK 0x0002 /* GP2_EINT */
3499#define WM8996_GP2_EINT_SHIFT 1 /* GP2_EINT */
3500#define WM8996_GP2_EINT_WIDTH 1 /* GP2_EINT */
3501#define WM8996_GP1_EINT 0x0001 /* GP1_EINT */
3502#define WM8996_GP1_EINT_MASK 0x0001 /* GP1_EINT */
3503#define WM8996_GP1_EINT_SHIFT 0 /* GP1_EINT */
3504#define WM8996_GP1_EINT_WIDTH 1 /* GP1_EINT */
3505
3506/*
3507 * R1841 (0x731) - Interrupt Status 2
3508 */
3509#define WM8996_DCS_DONE_23_EINT 0x1000 /* DCS_DONE_23_EINT */
3510#define WM8996_DCS_DONE_23_EINT_MASK 0x1000 /* DCS_DONE_23_EINT */
3511#define WM8996_DCS_DONE_23_EINT_SHIFT 12 /* DCS_DONE_23_EINT */
3512#define WM8996_DCS_DONE_23_EINT_WIDTH 1 /* DCS_DONE_23_EINT */
3513#define WM8996_DCS_DONE_01_EINT 0x0800 /* DCS_DONE_01_EINT */
3514#define WM8996_DCS_DONE_01_EINT_MASK 0x0800 /* DCS_DONE_01_EINT */
3515#define WM8996_DCS_DONE_01_EINT_SHIFT 11 /* DCS_DONE_01_EINT */
3516#define WM8996_DCS_DONE_01_EINT_WIDTH 1 /* DCS_DONE_01_EINT */
3517#define WM8996_WSEQ_DONE_EINT 0x0400 /* WSEQ_DONE_EINT */
3518#define WM8996_WSEQ_DONE_EINT_MASK 0x0400 /* WSEQ_DONE_EINT */
3519#define WM8996_WSEQ_DONE_EINT_SHIFT 10 /* WSEQ_DONE_EINT */
3520#define WM8996_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */
3521#define WM8996_FIFOS_ERR_EINT 0x0200 /* FIFOS_ERR_EINT */
3522#define WM8996_FIFOS_ERR_EINT_MASK 0x0200 /* FIFOS_ERR_EINT */
3523#define WM8996_FIFOS_ERR_EINT_SHIFT 9 /* FIFOS_ERR_EINT */
3524#define WM8996_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */
3525#define WM8996_DSP2DRC_SIG_DET_EINT 0x0080 /* DSP2DRC_SIG_DET_EINT */
3526#define WM8996_DSP2DRC_SIG_DET_EINT_MASK 0x0080 /* DSP2DRC_SIG_DET_EINT */
3527#define WM8996_DSP2DRC_SIG_DET_EINT_SHIFT 7 /* DSP2DRC_SIG_DET_EINT */
3528#define WM8996_DSP2DRC_SIG_DET_EINT_WIDTH 1 /* DSP2DRC_SIG_DET_EINT */
3529#define WM8996_DSP1DRC_SIG_DET_EINT 0x0040 /* DSP1DRC_SIG_DET_EINT */
3530#define WM8996_DSP1DRC_SIG_DET_EINT_MASK 0x0040 /* DSP1DRC_SIG_DET_EINT */
3531#define WM8996_DSP1DRC_SIG_DET_EINT_SHIFT 6 /* DSP1DRC_SIG_DET_EINT */
3532#define WM8996_DSP1DRC_SIG_DET_EINT_WIDTH 1 /* DSP1DRC_SIG_DET_EINT */
3533#define WM8996_FLL_SW_CLK_DONE_EINT 0x0008 /* FLL_SW_CLK_DONE_EINT */
3534#define WM8996_FLL_SW_CLK_DONE_EINT_MASK 0x0008 /* FLL_SW_CLK_DONE_EINT */
3535#define WM8996_FLL_SW_CLK_DONE_EINT_SHIFT 3 /* FLL_SW_CLK_DONE_EINT */
3536#define WM8996_FLL_SW_CLK_DONE_EINT_WIDTH 1 /* FLL_SW_CLK_DONE_EINT */
3537#define WM8996_FLL_LOCK_EINT 0x0004 /* FLL_LOCK_EINT */
3538#define WM8996_FLL_LOCK_EINT_MASK 0x0004 /* FLL_LOCK_EINT */
3539#define WM8996_FLL_LOCK_EINT_SHIFT 2 /* FLL_LOCK_EINT */
3540#define WM8996_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */
3541#define WM8996_HP_DONE_EINT 0x0002 /* HP_DONE_EINT */
3542#define WM8996_HP_DONE_EINT_MASK 0x0002 /* HP_DONE_EINT */
3543#define WM8996_HP_DONE_EINT_SHIFT 1 /* HP_DONE_EINT */
3544#define WM8996_HP_DONE_EINT_WIDTH 1 /* HP_DONE_EINT */
3545#define WM8996_MICD_EINT 0x0001 /* MICD_EINT */
3546#define WM8996_MICD_EINT_MASK 0x0001 /* MICD_EINT */
3547#define WM8996_MICD_EINT_SHIFT 0 /* MICD_EINT */
3548#define WM8996_MICD_EINT_WIDTH 1 /* MICD_EINT */
3549
3550/*
3551 * R1842 (0x732) - Interrupt Raw Status 2
3552 */
3553#define WM8996_DCS_DONE_23_STS 0x1000 /* DCS_DONE_23_STS */
3554#define WM8996_DCS_DONE_23_STS_MASK 0x1000 /* DCS_DONE_23_STS */
3555#define WM8996_DCS_DONE_23_STS_SHIFT 12 /* DCS_DONE_23_STS */
3556#define WM8996_DCS_DONE_23_STS_WIDTH 1 /* DCS_DONE_23_STS */
3557#define WM8996_DCS_DONE_01_STS 0x0800 /* DCS_DONE_01_STS */
3558#define WM8996_DCS_DONE_01_STS_MASK 0x0800 /* DCS_DONE_01_STS */
3559#define WM8996_DCS_DONE_01_STS_SHIFT 11 /* DCS_DONE_01_STS */
3560#define WM8996_DCS_DONE_01_STS_WIDTH 1 /* DCS_DONE_01_STS */
3561#define WM8996_WSEQ_DONE_STS 0x0400 /* WSEQ_DONE_STS */
3562#define WM8996_WSEQ_DONE_STS_MASK 0x0400 /* WSEQ_DONE_STS */
3563#define WM8996_WSEQ_DONE_STS_SHIFT 10 /* WSEQ_DONE_STS */
3564#define WM8996_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */
3565#define WM8996_FIFOS_ERR_STS 0x0200 /* FIFOS_ERR_STS */
3566#define WM8996_FIFOS_ERR_STS_MASK 0x0200 /* FIFOS_ERR_STS */
3567#define WM8996_FIFOS_ERR_STS_SHIFT 9 /* FIFOS_ERR_STS */
3568#define WM8996_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */
3569#define WM8996_DSP2DRC_SIG_DET_STS 0x0080 /* DSP2DRC_SIG_DET_STS */
3570#define WM8996_DSP2DRC_SIG_DET_STS_MASK 0x0080 /* DSP2DRC_SIG_DET_STS */
3571#define WM8996_DSP2DRC_SIG_DET_STS_SHIFT 7 /* DSP2DRC_SIG_DET_STS */
3572#define WM8996_DSP2DRC_SIG_DET_STS_WIDTH 1 /* DSP2DRC_SIG_DET_STS */
3573#define WM8996_DSP1DRC_SIG_DET_STS 0x0040 /* DSP1DRC_SIG_DET_STS */
3574#define WM8996_DSP1DRC_SIG_DET_STS_MASK 0x0040 /* DSP1DRC_SIG_DET_STS */
3575#define WM8996_DSP1DRC_SIG_DET_STS_SHIFT 6 /* DSP1DRC_SIG_DET_STS */
3576#define WM8996_DSP1DRC_SIG_DET_STS_WIDTH 1 /* DSP1DRC_SIG_DET_STS */
3577#define WM8996_FLL_LOCK_STS 0x0004 /* FLL_LOCK_STS */
3578#define WM8996_FLL_LOCK_STS_MASK 0x0004 /* FLL_LOCK_STS */
3579#define WM8996_FLL_LOCK_STS_SHIFT 2 /* FLL_LOCK_STS */
3580#define WM8996_FLL_LOCK_STS_WIDTH 1 /* FLL_LOCK_STS */
3581
3582/*
3583 * R1848 (0x738) - Interrupt Status 1 Mask
3584 */
3585#define WM8996_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
3586#define WM8996_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
3587#define WM8996_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
3588#define WM8996_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
3589#define WM8996_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
3590#define WM8996_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
3591#define WM8996_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
3592#define WM8996_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
3593#define WM8996_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
3594#define WM8996_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
3595#define WM8996_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
3596#define WM8996_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
3597#define WM8996_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
3598#define WM8996_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
3599#define WM8996_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
3600#define WM8996_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
3601#define WM8996_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
3602#define WM8996_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
3603#define WM8996_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
3604#define WM8996_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
3605
3606/*
3607 * R1849 (0x739) - Interrupt Status 2 Mask
3608 */
3609#define WM8996_IM_DCS_DONE_23_EINT 0x1000 /* IM_DCS_DONE_23_EINT */
3610#define WM8996_IM_DCS_DONE_23_EINT_MASK 0x1000 /* IM_DCS_DONE_23_EINT */
3611#define WM8996_IM_DCS_DONE_23_EINT_SHIFT 12 /* IM_DCS_DONE_23_EINT */
3612#define WM8996_IM_DCS_DONE_23_EINT_WIDTH 1 /* IM_DCS_DONE_23_EINT */
3613#define WM8996_IM_DCS_DONE_01_EINT 0x0800 /* IM_DCS_DONE_01_EINT */
3614#define WM8996_IM_DCS_DONE_01_EINT_MASK 0x0800 /* IM_DCS_DONE_01_EINT */
3615#define WM8996_IM_DCS_DONE_01_EINT_SHIFT 11 /* IM_DCS_DONE_01_EINT */
3616#define WM8996_IM_DCS_DONE_01_EINT_WIDTH 1 /* IM_DCS_DONE_01_EINT */
3617#define WM8996_IM_WSEQ_DONE_EINT 0x0400 /* IM_WSEQ_DONE_EINT */
3618#define WM8996_IM_WSEQ_DONE_EINT_MASK 0x0400 /* IM_WSEQ_DONE_EINT */
3619#define WM8996_IM_WSEQ_DONE_EINT_SHIFT 10 /* IM_WSEQ_DONE_EINT */
3620#define WM8996_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */
3621#define WM8996_IM_FIFOS_ERR_EINT 0x0200 /* IM_FIFOS_ERR_EINT */
3622#define WM8996_IM_FIFOS_ERR_EINT_MASK 0x0200 /* IM_FIFOS_ERR_EINT */
3623#define WM8996_IM_FIFOS_ERR_EINT_SHIFT 9 /* IM_FIFOS_ERR_EINT */
3624#define WM8996_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */
3625#define WM8996_IM_DSP2DRC_SIG_DET_EINT 0x0080 /* IM_DSP2DRC_SIG_DET_EINT */
3626#define WM8996_IM_DSP2DRC_SIG_DET_EINT_MASK 0x0080 /* IM_DSP2DRC_SIG_DET_EINT */
3627#define WM8996_IM_DSP2DRC_SIG_DET_EINT_SHIFT 7 /* IM_DSP2DRC_SIG_DET_EINT */
3628#define WM8996_IM_DSP2DRC_SIG_DET_EINT_WIDTH 1 /* IM_DSP2DRC_SIG_DET_EINT */
3629#define WM8996_IM_DSP1DRC_SIG_DET_EINT 0x0040 /* IM_DSP1DRC_SIG_DET_EINT */
3630#define WM8996_IM_DSP1DRC_SIG_DET_EINT_MASK 0x0040 /* IM_DSP1DRC_SIG_DET_EINT */
3631#define WM8996_IM_DSP1DRC_SIG_DET_EINT_SHIFT 6 /* IM_DSP1DRC_SIG_DET_EINT */
3632#define WM8996_IM_DSP1DRC_SIG_DET_EINT_WIDTH 1 /* IM_DSP1DRC_SIG_DET_EINT */
3633#define WM8996_IM_FLL_SW_CLK_DONE_EINT 0x0008 /* IM_FLL_SW_CLK_DONE_EINT */
3634#define WM8996_IM_FLL_SW_CLK_DONE_EINT_MASK 0x0008 /* IM_FLL_SW_CLK_DONE_EINT */
3635#define WM8996_IM_FLL_SW_CLK_DONE_EINT_SHIFT 3 /* IM_FLL_SW_CLK_DONE_EINT */
3636#define WM8996_IM_FLL_SW_CLK_DONE_EINT_WIDTH 1 /* IM_FLL_SW_CLK_DONE_EINT */
3637#define WM8996_IM_FLL_LOCK_EINT 0x0004 /* IM_FLL_LOCK_EINT */
3638#define WM8996_IM_FLL_LOCK_EINT_MASK 0x0004 /* IM_FLL_LOCK_EINT */
3639#define WM8996_IM_FLL_LOCK_EINT_SHIFT 2 /* IM_FLL_LOCK_EINT */
3640#define WM8996_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */
3641#define WM8996_IM_HP_DONE_EINT 0x0002 /* IM_HP_DONE_EINT */
3642#define WM8996_IM_HP_DONE_EINT_MASK 0x0002 /* IM_HP_DONE_EINT */
3643#define WM8996_IM_HP_DONE_EINT_SHIFT 1 /* IM_HP_DONE_EINT */
3644#define WM8996_IM_HP_DONE_EINT_WIDTH 1 /* IM_HP_DONE_EINT */
3645#define WM8996_IM_MICD_EINT 0x0001 /* IM_MICD_EINT */
3646#define WM8996_IM_MICD_EINT_MASK 0x0001 /* IM_MICD_EINT */
3647#define WM8996_IM_MICD_EINT_SHIFT 0 /* IM_MICD_EINT */
3648#define WM8996_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */
3649
3650/*
3651 * R1856 (0x740) - Interrupt Control
3652 */
3653#define WM8996_IM_IRQ 0x0001 /* IM_IRQ */
3654#define WM8996_IM_IRQ_MASK 0x0001 /* IM_IRQ */
3655#define WM8996_IM_IRQ_SHIFT 0 /* IM_IRQ */
3656#define WM8996_IM_IRQ_WIDTH 1 /* IM_IRQ */
3657
3658/*
3659 * R2048 (0x800) - Left PDM Speaker
3660 */
3661#define WM8996_SPKL_ENA 0x0010 /* SPKL_ENA */
3662#define WM8996_SPKL_ENA_MASK 0x0010 /* SPKL_ENA */
3663#define WM8996_SPKL_ENA_SHIFT 4 /* SPKL_ENA */
3664#define WM8996_SPKL_ENA_WIDTH 1 /* SPKL_ENA */
3665#define WM8996_SPKL_MUTE 0x0008 /* SPKL_MUTE */
3666#define WM8996_SPKL_MUTE_MASK 0x0008 /* SPKL_MUTE */
3667#define WM8996_SPKL_MUTE_SHIFT 3 /* SPKL_MUTE */
3668#define WM8996_SPKL_MUTE_WIDTH 1 /* SPKL_MUTE */
3669#define WM8996_SPKL_MUTE_ZC 0x0004 /* SPKL_MUTE_ZC */
3670#define WM8996_SPKL_MUTE_ZC_MASK 0x0004 /* SPKL_MUTE_ZC */
3671#define WM8996_SPKL_MUTE_ZC_SHIFT 2 /* SPKL_MUTE_ZC */
3672#define WM8996_SPKL_MUTE_ZC_WIDTH 1 /* SPKL_MUTE_ZC */
3673#define WM8996_SPKL_SRC_MASK 0x0003 /* SPKL_SRC - [1:0] */
3674#define WM8996_SPKL_SRC_SHIFT 0 /* SPKL_SRC - [1:0] */
3675#define WM8996_SPKL_SRC_WIDTH 2 /* SPKL_SRC - [1:0] */
3676
3677/*
3678 * R2049 (0x801) - Right PDM Speaker
3679 */
3680#define WM8996_SPKR_ENA 0x0010 /* SPKR_ENA */
3681#define WM8996_SPKR_ENA_MASK 0x0010 /* SPKR_ENA */
3682#define WM8996_SPKR_ENA_SHIFT 4 /* SPKR_ENA */
3683#define WM8996_SPKR_ENA_WIDTH 1 /* SPKR_ENA */
3684#define WM8996_SPKR_MUTE 0x0008 /* SPKR_MUTE */
3685#define WM8996_SPKR_MUTE_MASK 0x0008 /* SPKR_MUTE */
3686#define WM8996_SPKR_MUTE_SHIFT 3 /* SPKR_MUTE */
3687#define WM8996_SPKR_MUTE_WIDTH 1 /* SPKR_MUTE */
3688#define WM8996_SPKR_MUTE_ZC 0x0004 /* SPKR_MUTE_ZC */
3689#define WM8996_SPKR_MUTE_ZC_MASK 0x0004 /* SPKR_MUTE_ZC */
3690#define WM8996_SPKR_MUTE_ZC_SHIFT 2 /* SPKR_MUTE_ZC */
3691#define WM8996_SPKR_MUTE_ZC_WIDTH 1 /* SPKR_MUTE_ZC */
3692#define WM8996_SPKR_SRC_MASK 0x0003 /* SPKR_SRC - [1:0] */
3693#define WM8996_SPKR_SRC_SHIFT 0 /* SPKR_SRC - [1:0] */
3694#define WM8996_SPKR_SRC_WIDTH 2 /* SPKR_SRC - [1:0] */
3695
3696/*
3697 * R2050 (0x802) - PDM Speaker Mute Sequence
3698 */
3699#define WM8996_SPK_MUTE_ENDIAN 0x0100 /* SPK_MUTE_ENDIAN */
3700#define WM8996_SPK_MUTE_ENDIAN_MASK 0x0100 /* SPK_MUTE_ENDIAN */
3701#define WM8996_SPK_MUTE_ENDIAN_SHIFT 8 /* SPK_MUTE_ENDIAN */
3702#define WM8996_SPK_MUTE_ENDIAN_WIDTH 1 /* SPK_MUTE_ENDIAN */
3703#define WM8996_SPK_MUTE_SEQ1_MASK 0x00FF /* SPK_MUTE_SEQ1 - [7:0] */
3704#define WM8996_SPK_MUTE_SEQ1_SHIFT 0 /* SPK_MUTE_SEQ1 - [7:0] */
3705#define WM8996_SPK_MUTE_SEQ1_WIDTH 8 /* SPK_MUTE_SEQ1 - [7:0] */
3706
3707/*
3708 * R2051 (0x803) - PDM Speaker Volume
3709 */
3710#define WM8996_SPKR_VOL_MASK 0x00F0 /* SPKR_VOL - [7:4] */
3711#define WM8996_SPKR_VOL_SHIFT 4 /* SPKR_VOL - [7:4] */
3712#define WM8996_SPKR_VOL_WIDTH 4 /* SPKR_VOL - [7:4] */
3713#define WM8996_SPKL_VOL_MASK 0x000F /* SPKL_VOL - [3:0] */
3714#define WM8996_SPKL_VOL_SHIFT 0 /* SPKL_VOL - [3:0] */
3715#define WM8996_SPKL_VOL_WIDTH 4 /* SPKL_VOL - [3:0] */
3716
3717#endif
diff --git a/sound/soc/codecs/wm_hubs.c b/sound/soc/codecs/wm_hubs.c
index 4cc2d567f22f..e763c54c55dc 100644
--- a/sound/soc/codecs/wm_hubs.c
+++ b/sound/soc/codecs/wm_hubs.c
@@ -440,9 +440,8 @@ static int hp_event(struct snd_soc_dapm_widget *w,
440 reg |= WM8993_HPOUT1L_DLY | WM8993_HPOUT1R_DLY; 440 reg |= WM8993_HPOUT1L_DLY | WM8993_HPOUT1R_DLY;
441 snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg); 441 snd_soc_write(codec, WM8993_ANALOGUE_HP_0, reg);
442 442
443 /* Smallest supported update interval */
444 snd_soc_update_bits(codec, WM8993_DC_SERVO_1, 443 snd_soc_update_bits(codec, WM8993_DC_SERVO_1,
445 WM8993_DCS_TIMER_PERIOD_01_MASK, 1); 444 WM8993_DCS_TIMER_PERIOD_01_MASK, 0);
446 445
447 calibrate_dc_servo(codec); 446 calibrate_dc_servo(codec);
448 447
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-02 07:26:08 -0400